C3PM/C3RM cPCI Pentium M Based Single Board
Contents
1. Resistor GPlOLine gt gt eee R247 EEE a eae EBRO pres Resistor R251 ER 4 4 CompactFlash Drive Installation The C3PM supports a bootable CompactFlash Drive for single slot booting Connector J2 is a Type I CompactFlash connector with a retention clip for rugged applications and is used for this purpose J2 is located on a special CompactFlash carrier module that bolts to the top side cooling plate heat sink so that the drive will be accessible Use a screwdriver to release the clip The CompactFlash module must be unbolted and removed before the CF drive can be replaced or removed 16 C3PM cPCI Pentium Processor Board User s Manual Dynatem Appendix A Connector Pin outs A Connector Pin outs The locations of the C3PM connectors are shown below sa a J6 CompactFlash Dynatem C3PM cPCI Pentium Processor Board User s Manual 17 Appendix A Connector Pin outs 18 A 1 CompactFlash Interface Connector Pm Signal Pin Signal s je Jia TT De a js 7 eu gt os 8 Jeno a Nocomnecion s feo a oor tes oa m ew 20 oo No conection a Do s Pupos e m w joe 8 gt e jg CompactFlash Type II Interface Connector J2 on CF carrier C3PM cPCI Pentium Processor Board User s Manual Dynatem Appendix A Connector Pin outs A 2 cPCI Connectors J1 amp J2 Connector J2 brings a2. Pin 107100 Signal Description A6 A Receive Data RX TP1 Unused TP3 Unused TP3 10 100 Signal Description Port B Transmit Data TX B Transmit Data TX B Receive Data RX Unused Unused B Receive Data RX Unused Unused 10BaseT 100BaseTX Fast Ethernet Connector J4 J3 RJ 45 Connectors A8 AG AReceiveData RX TP A7 Urused Pa A Unused PB WW W NP lt vu N ajA W co USB Port 0 Negative USB Port O Positive USB Vcc USB Port 1 Negative 7 USB Port 1 Positive 10 E Dual Port USB 2 0 Connector J1 Dynatem C3PM cPCI Pentium Processor Board User s Manual 27 Appendix D C3PMPTB Rear Plug in I O Expansion Module for the C3PM Sera beserta E SG Return on De CR Return ee Ratu GRD oe we TT Horizontal Sync HSYNC Output Vertical Sync VSYNC Output VGA Connector J2 DB15F Connector The metal shell of the connector goes to chassis ground 28 C3PM cPCI Pentium Processor Board User s Manual Dynatem
3. 32 bit 33 MHz capable PCI bus to the CompactPCI backplane PU stands for pulled up As was described in Chapter 4 some pins can be used for GPIO lines in red font or for COMI signals Signal names in blue italics were changed for C3RM Manual Rev 105 February 1 2008 BIOS WP GAO ETHO DA ETHO DA ETHO DB z 509 006 Gu Bzz CLK5 COM3_TXD COM3_TXD COM3_RTS C ETHO DC ETHO DC ETHO DD ETHO DB GNT6 VBATT GNT5 ETH1_DA ETH1_DA Es DN EM ETH1_DB GA1 GND GND GND R 8 io 39 0 GND c E z GND C COM3_RXD C ETHO DD FAL Pulled up USBO_VCC ETH1_DB ETH1_DC ETH1_DC ETH1_DD ETH1_DD GPIO43 VGA_ Green VGA Blue GNT4 REQ3 REQ2 C COM1_RTS 3 G OM1_RXD 3 COM1_CTS 4 OM1_CTS 41 GPIO42 VGA Red REQ4 CompactPCI Backplane Connector J2 Row F is grounded RS 232 Signals RS 4xx Signals Clear To Send CTS Input GA4 GND VGA VCC VGA DDCD VGA DDCC A22 A19 A18 LA A16 A15 ELA LAB A12 LAN LATO A09 Aoa A07 A06 AOS Aoa AOS A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 Received Data RxD Input Transmitted Data TxD Output Request To Send RTS Output Conversion between RS 232 and RS 4xx ports applies to both COM1 amp COM3 RS 4xx negative lines are not used when in the
4. Board User s Manual Dynatem Chapter 3 Hardware Description JJ 3 9 Reset Circuitry The reset circuitry is shown below PCI PCI Bridge to the CompactPCI Backplane cPCI SYSRESET ENUM Atmel ATmega 128L IPMI Coniroller a Optional Reset BG VCSR_SET RES Switch PB1 On X3PMRIO SYSRESET d BD SEL Payload Interface 6300ESB ICH PCI Reset PCI peripherals SYSRESET Reset Control Register Pentium M soft reset z PWRGD_VR Vcore Monitor Pentium M hard reset NN NN 2 5 V Good Reset Circuitry Dynatem C3PM cPCI Pentium Processor Board User s Manual 11 Chapter 3 Hardware Description ar There are multiple ways to perform a hard reset of the C3PM e A simple power cycle turn the chassis power off and on e There is an option for using a push button reset the PRST signal on the backplane connector J2 pin C17 that is generally connected to the chassis reset button the optional X3PMRIO rear plug in module also provides a push button for restting through poin C17 of J2 e When the C3PM is installed in a peripheral slot it can be reset by the system controller module through a conventional PCI Reset e The PWRGD Circuitry that monitors the on board power supplies For further information on the peripherals that play a part in the reset circuitry refer to ICH datasheet that s referenced in Section 2 12 C3PM cPCI Pentium Processor Board
5. RS232 mode Dynatem C3PM cPCI Pentium Processor Board User s Manual 19 Appendix A Connector Pin outs Connector J1 brings a 32 bit 33 MHz capable PCI bus to the CompactPCI backplane PU stands for pulled up ADT vo ADO ADA AD AD AD GND 622 ssvoc p22 A ADS ADO ADE GIBEOR GND vo AD10 GND AD13 GND PAR CIBET GND PERR GND vio LOCK TROY 0 a A oo Ig Y a KEY KEY KEY KEY KEY Ads en Aby em ao on cw GBE2R GND co Save Dio ao Eo Abis cre Boo Nose coo aos Doo cu AD22 GND vio ADD GND AD27 Recos 806 POL Presens coe 33voc Doe ciko Eos ADI GND GNTO O INT INTD TCK Tus 100 Toi CompactPCI Backplane Connector J1 Row F is grounded 20 C3PM cPCI Pentium Processor Board User s Manual Dynatem Appendix B Address Maps Interrupts DMA Channels B Address Maps Interrupts DMA Channels Tables of the C3PM s address maps interrupt request assignments and DMA channel usage are given in the following sections All addresses are shown in hexadecimal notation B 1 Memory Map The C3PM s memory map is shown below 00000000 OOOFFFFF DOS legacy address range 00100000 1FFFFFFF On board DDR DRAM 512 MB This is the memory map on the chipset For further details on the C3PM memory space map refer to Section 5 1 in Intel s 855GM 855GME Chipset Graphics and Memory Controller Hub GMCH Datasheet Document 252615 00
6. User s Manual Dynatem Chapter 4 Installation I S 4 Installation The following sections cover the steps necessary to configure the C3PM and install it into a cPCI system for single slot operation This chapter should be read in its entirety before proceeding with the installation The C3PM is shipped in an antistatic bag Be sure to observe proper handling procedures during the configuration and installation process to avoid damage due to electrostatic discharge ESD 4 1 Installing the C3PM in a CompactPCI Chassis The C3PM features a Universal PCI PCI bridge to the backplane Without changing any jumpers the C3PM will operate as a system slot card coming up in transparent mode whereby it can initialize peripheral cards on the backplane when installed in the system slot or as a peripheral card in peripheral slots coming up in non transparent mode so that initialization will be done locally without interference from the system slot processor board 4 2 Jumper 8 GPIO Selectable Options The C3PM contains four jumpers for system configuration The jumpers are indicated in the photo below JP4 3 pins and pin 1 is in a square AR COMI is in RS 232 mode when pins 2 amp 3 are shunted RS 4xx when pins 1 amp 2 are shunted GPIO56 is COM1 TE and it must be high to enable RS 4xx Dynatem C3PM cPCI Pentium Processor Board User s Manual 13 Chapter 4 Installation JJ Jumper JP1 determines the status of XB MEM
7. and it should be left open XB MEM when in the Transparent Mode When the C3PM is installed in the System Slot SYS_EN on the backplane will ground the TRANS line and put the module s 6254 PCI PCI bridge to the backplane in the transparent mode XB MEM will also be grounded as that signal is connected to TRANS and SYS EN through 0 ohm resistor R338 KB MEM when in the Non Transparent Mode When installed in peripheral slots the C3PM will be in the Non Transparent mode When XB MEM is set to 1 the PCI 6540 automatically claims 16 MB of Memory space This allows the boot up of the Low Priority Boot port to proceed without waiting for the Priority Boot port to program the corresponding Memory Base Address registers BARs JP1 must be left open in order for the C3PM to boot in peripheral slots Jumper JP3 is used to restore default BIOS settings It works differently when NV RAM is battery backed than when the settings are stored in a serial EEPROM When the board uses a battery for holding NV RAM and RTC data close JP3 momentarily for about 15 seconds when the power is off or the C3PM is out of the chassis to flush RTC and NV RAM and revert to BIOS defaults The shunt for JP3 should normally be off when a battery is used In rugged systems where no battery is available JP3 should normally be closed Follow these steps to change the stored BIOS settings 1 Power off the card Remove JP3 then power on The BIOS would come up with de
8. e Operating System OS and driver support including Windows NT Embedded NT XP QNX VxWorks Linux Solaris and pSOS 2 C3PM cPCI Pentium Processor Board User s Manual Dynatem Chapter 2 Related Documents FFP PSPSS r ITIOODRMDIRIDURhDDURDMI IRCRI D D LA IAADADADRDADADIA IDLD R D D DADAD ARARARCDADUAUADAUDMAD M D DA OOOOOOOOUDIIRI TRDIDRIRARDI D D P DPTPTIRIAO EPFEOO ARORJPP TPDPOBP JJ 2 Related Documents Listed below are documents that describe the Pentium processor and chipset and the peripheral components used on the C3PM Either download from the Internet or contact your local distributor for copies of these documents The C3PM uses the Low Voltage Pentium M For information on this processor go to http www intel com design intarch pentiumm pentiumm htm For the ICH component in the 6300ESBchipset get the Intel 6300ESB I O Controller Hub Datasheet It is document number 300641 003 http www intel com design intarch datashts 300641 htm For the GMCH component in the chipset get the Intel 855GM 855GME Chipset Graphics and Memory Controller Hub GMCH Datasheet It is document number 252615 005 http www intel com design chipsets datashts 252615 htm For data sheets on I O controllers e 82546EB Fast Ethernet PCI Controller http developer intel com design network products lan controllers 82546 htm e CompactPCI Specificati
9. with wedgelocks stiffener bar and a full board heatsink for rugged applications When referring to attributes of both versions we will use the name C3PM The C3PM employs Intel s embedded technology to assure long term availability Features of the C3PM include e Single slot cPCI operation with on board CompactFlash disk for bootable mass storage e VGA graphics two USB 2 0 ports one Serial ATA port two Fast Ethernet ports and driven COM1 amp 3 ports are routed out to the backplane via the J2 connector e The Intel 855GME Graphics Memory Controller Hub GMCH and Intel 6300ESB I O Controller Hub ICH provide high speed memory control built in graphics integrated I O including Serial ATA USB 2 0 IDE supporting Ultra 100 DMA Mode for transfers up to 88 88 MB sec and 64 bit PCI X bus transfers at 66 MHz e Intel s 82546 Ethernet Controller offers two 10 100 1000BaseTX support routed to J2 e 512 MB of DDR 266 DRAM provided on board e PLX PCI6254 dual mode Universal asynchronous PCI PCI bridge lets the C3PM act as a peripheral card or system slot module Dynatem C3PM cPCI Pentium Processor Board User s Manual 1 Chapter 1 Features EEE E EPE e Pigeon Point s IPM Sentry offers IPMI system management in compliance with PICMG 2 9 e Primary IDE port for CompactFlash on board for flash based mass storage for single slot booting e General Software s flash based system BIOS e PXE for diskless booting over Ethernet
10. 0ESB Southbridge provides the 5 pin interface to the E82802AC The upper 256 KB of the E82802AC is located from 000C0000 OOOFFFFF and its full I MB of memory is aliased from FFF00000 FFFFFFFF where it can be fully accessed after booting up through the BIOS Here s a link to a datasheet for the 82802AC ftp download intel com design chipsets datashts 29065804 pdf 3 8 Clock Drivers The clock driver circuitry is shown below Cypress 28409 14 31818 MHz Pentium M CPU Crystal 100 MHz differential clocks for GMCH To GMCH for SDRAM Clocks ICH ITP amp CPU ICH 32 768 KHz To ICH for clocks Crystal Real Time ITP Port Clock 48 MHz T MH To Ethernet Routed to ICH for wo 250 MHZ controller USB and UART s and Oscillators 82546 to the GMCH for Graphics To ICH for USB amp Serial To GMCH for dot clocks Clock Driver Circuitry The clocks are generated by the Cypress CY28409 which is driven by a 14 31818 MHz crystal DRAM clocks are synthesized by the GMCH and Hub Interface and PCI X clocks are produced by the ICH A 32 768 KHz Crystal drives the Real Time Clock RTC on the ICH The Fast Ethernet port provided to the front panel by the 82541 and the two Gb Ethernet ports provided to the backplane by the 82546 require separate 25 0 MHz oscillators one of the two oscillators is also used for the watchdog timer clock A 64 0 MHz oscillator drives the PCI 6254cPCI circuitry 10 C3PM cPCI Pentium Processor
11. 4 available from Intel Corporation B 2 PCI Configuration Space Map The PCI configuration space map will vary if the PMCX expansion slot is used to support a PMCX add on mezzanine card and if that PMCX module uses a expansion bridge designed for multiple targets on the secondary bus This is an extremely unlikely situation but the bus numbers in this condition will differ from those provided in the following table The Vendor ID and Device ID in hex for the PMCX slot are shown as xxxx since they depend on the type of device installed in the PMC slot Fere 6300ESB ICH P2L Bridge 6 zone jean CH ride meas o f ena 000 to POLIS ms 0020 PCI 6054 bridge to CPCI bus ES ee alee E O PCI Configuration Ea Dynatem C3PM cPCI Pentium Processor Board User s Manual 21 Appendix B Address Maps Interrupts DMA Channels B 3 Interrupt Request Routing The ISA interrupt request routing is shown below Timer O ICH Cascade Interrupt from slave PIC ICH 12 Es Math Coprocessor ICH Primary IDE Interface CompaciFlash ICH The PCI interrupt request routing of additional interrupts all IRQs are routed to the 6300ESB ICH PIIX4 PCI IRQ E 001 C3PM Rev 002 C3PM These are IRQs routed from J1 on the CompactPCI backplane Rev 001 versions of the module use a flex cable connection to the CompactFlash sub assembly or can be identified by PWB D010 6062 001 being etched into the PC
12. B on the solder side near the front edge For further details on interrupts refer to the documentation for the various peripherals that generate interrupts as well as Intel 6300ESB I O Controller Hub Datasheet Document 300641 002 22 C3PM cPCI Pentium Processor Board User s Manual Dynatem Appendix C Power and Environmental Requirements 3 SS eS ee Se E PMB PESE ES C Power and Environmental Requirements The C3PM power and environmental requirements are shown in the tables below 1 4 MHz Pentium M 5 VDC 3 4 A max 3 3 VDC 2 2 A max 3 0 VDC Lithium Coin Cell 3 4 uA Power Requirements The 3 Volt lithium coin cell is a CR2032 with 190 mAhours capacity and it is used to battery back the Real Time Clock the 2 MB of NV SRAM and the BIOS s NV RAM At 3 4 HA this battery should last for over six years with power off Operating Temperature 40 to 71 C can be screened for 40 to 85 C Storage Temperature 50 to 105 C Environmental Requirements Dynatem C3PM cPCI Pentium Processor Board User s Manual 23 Appendix C Power and Environmental Requirements EEE EEE EE EE SEE 24 C3PM cPCI Pentium Processor Board User s Manual Dynatem Appendix D X3PMRIO Rear Plug in I O Expansion Module for the C3PM D X3PMRIO Rear Plug in I O Expansion Module for the C3PM All of the C3PM s I O is routed directly through the J2 connector so a rear plug in module is useful for inter
13. DYNATEM C3PM C3RM cPCI Pentium M Based Single Board Computer User s Manual C3RM Manual Rev 1 06 March 17 2008 Dynatem 23263 Madero Suite C Mission Viejo CA 92691 Phone 949 855 3235 Fax 949 770 3481 www dynatem com Dynatem Table of Contents Features Related Documents Hardware Description Overview Processor Chipset DRAM Intel s FW82802A Firmware Hub Holds the System BIOS In Flash Memory Clock Drivers Installation Installing C3PM in a CompactPCI Chassis Jumper amp GPIO Selectable Options 0 Discrete I O vs COMI Line Routing CompactFlash Drive Installation C3PM cPCI Pentium Processor Board User s Manual Al A 2 B 1 B 2 B 3 Connector Pin outs 17 CompactFlash Interface Connector J2 on carrier card cPCI Connectors J1 amp J2 Address Maps Interrupts DMA Channels 18 19 21 Memory Map PCI Configuration Space Map Interrupt Reguest Routing Power and Environmental Reguirements 21 21 22 23 X3PMRIO Rear Plug in I O Expansion Module C3PM cPCI Pentium Processor Board User s Manual 25 Dynatem Chapter 1 Features OO 1 Features The Dynatem C3PM is a single slot 3U cPCI Single Board Computer SBC The C3PM offers full PC performance with a Pentium M low power processor The C3PM is available in two versions the C3PM for standard industrial applications and the ANSI VITA 30 1 2002 compliant conduction cooled CRM1
14. arded to the other side using an address translation mechanism A non transparent bridge is used when there is more than one intelligent entity such as multiple processors in the system It is a common mechanism used on intelligent I O cards and in multi processor systems The C3PM reset circuitry is tied to the bridge since the C3PM can generate the cPCI SYSRESET signal as well as be reset by another cPCI board that asserts the SYSRESET signal The C3PM reset circuitry is discussed in detail in Section 3 12 This section supplements the PCI to PCI Bus Bridge documentation downloadable from PLX Technology s website at http www plxtech com products fastlane bridges default asp which contains comprehensive descriptions of the operation and programming of the PCI 6254 3 7 Intel s FW82802AC Firmware Hub Holds the System BIOS In Flash Memory The Intel FW82802AC uses a 5 pin interface and provides 1 MByte of flash memory for the system BIOS This device can fill the 1 MB real mode memory map so only a portion its upper 256 MB is used The FW82802AC s 1 MB of memory space is segmented into sixteen parameter blocks of 64 KB each The C3PM powers up into real mode and the BIOS is eventually shadowed into system DRAM after booting through the BIOS Dynatem C3PM cPCI Pentium Processor Board User s Manual 9 Chapter 3 Hardware Description TP PD D D T AMA RIMI TO T THUHTUOUTOTUTTTTCTDUDUEHP A 1 The 630
15. d to the memory space or the I O space The PCI signals specific to the C3PM s 82546 are shown below Dynatem C3PM cPCI Pentium Processor Board User s Manual 7 Chapter 3 Hardware Description SSS ES SSS AE a TDR Intel 82546 Signal PCI Bus Connection PCI Bus Connection Rev A Rev B 3 6 PLX PCI6254 PCI cPCI Interface The PCI cPCI interface based on the PLX PCI 6254 on PWB 010 6057 002 offers the following features e 64 bit 33MHz 66MHz Asynchronous operation e KB FIFO for efficient PCI PCI bridging and speed conversion e Transparent and non transparent bridge operation e Usable in the cPCI system slot or a peripheral slot The block diagram of the PCI PCI interface is shown below 6300ESB IPMI amp Reset Input Output Controller Hot Swap Control Hub PCl interface CPCI P1 Connector PCI6254 SYSEN determines system slot or peripheral operation PCI cPCI Backplane Interface Block Diagram The is a universal bridge meaning its mode of operation is determined by the SYSEN signal on the cPCI backplane In this application the C3PM can be used without jumpers for the system slot or peripheral slot in a CompactPCI system The bridge senses the type of slot system or peripheral and configures itself as Transparent or Non Transparent respectively In the system slot the CPU is expected to operate as a host and the bridge operates in Transparent mode In the peripheral slot the CPU is part of an intelli
16. dia timers based on the 82C54 For further information see the documents referenced in Section 2 3 4 DRAM The C3PM supports a 72 bit wide DDR 266 memory interface with memory bandwidth of 2 1 GB s with ECC The module supports 512 MB of DRAM 3 5 Intel 82546EB Dual Gigabit Ethernet Controller The C3PM supports two 10 100 1000BaseTX channels accessible from the backplane The Intel 82546EB Dual Port Gigabit Ethernet Controller incorporates two full Gigabit Ethernet MAC and PHY layer functions on a single compact component The C3PM uses the PCI X interface of the ICH to control the 82546EB Therefore the front side data path to the dual Ethernet port controller is 64 bits at 66 MHz The Intel 82546EB offers the following features e 10 100 and 1000BaseTX support with auto negotiation e Dual 64KB configurable RX and TX packet FIFOs e 128 bit internal data path architecture for low latency data handling and superior DMA transfer rate performance e Built in Phyceiver e Serial EEPROM for non volatile Ethernet address storage Both 10 100 1000BaseTX ports of the 82546 device are brought out to the J2 backplane connector Optionally these two 1 Gb Ethernet ports are brought to industry standard RJ 45 connectors on Dynatem s rear I O plug in module X3PMRIO see Appendix D The Intel 82546 contains several PCI configuration registers It also contains a number of device registers for controlling the Ethernet operation that can be mappe
17. facing to industry standard cables The X3PMRIO is available for this purpose Here is a photo of the X3PMRIO J7 SATAO PB1 Reset Button J4 LANa J3 LANb 3 s 2 gt s s gt 3 hd s gt 3 gt gt 3 _ 2 s 3 J2 SVGA RPI RP2 RP h J1 USBO amp USBI BT1 Battery J6 COMI J5 COM3 a CR2032 Shunting JP1 grounds GPIO42 Shunting JP2 grounds GPIO43 Shunting JP3 write protects the BIOS on the C3PM Shunting JP4 grounds GPIO24 AKA BIT_PASS Pin outs for the X3PMRIO s connectors are found on the following pages Dynatem C3PM cPCI Pentium Processor Board User s Manual 25 Appendix D C3PMPTB Rear Plug in I O Expansion Module for the C3PM Signal names in blue italics were changed for C3RM Manual Rev 105 February 1 2008 COM1 RS 232 RP5 Installed COM1 RS 4xx RP4 amp RP6 Installed Do Received Data RxD Input Transmitted Data TxD Output 6 8 9 COM1 Connector J6 DB9M Connector The metal shell of the connector goes to chassis ground COM3 RS 232 RP2 Installed COM3 RS 4xx RP1 amp Ba aa a Dp 4 Received Data RxD Input a es ee NN ee oo E O O COM3 Connector J5 DB9M Connector The metal shell of the connector goes to chassis ground Serial ATA SATA 0 Connector J7 26 C3PM cPCI Pentium Processor Board User s Manual Dynatem Appendix D X3PMRIO Rear Plug in I O Expansion Module for the C3PM J4
18. fault setup read from flash instead of EEPROM Hit lt DEL gt to enter setup Please note however that EEPROM is still in unchanged at this stage the BIOS comes up to its flash default 2 Upon entering setup the BIOS can be modified to preferred configurations or left in default mode However the save and exit option MUST be used when exiting the setup menus to write the current setup to the EEPROM 3 Power off the card Reinstall JP3 On next power up the BIOS will read setup parameters from the EEPROM which is saved in step 2 above COM3 is accessed through USB port 2 through Silicon Laboratories CP2102 device since COM2 from the ICH is used for IPMI COM3 is configured as RS 232 or RS 4xx by two GPIO lines GPIO20 amp GPIO23 The board will come up with COM3 undriven so that there won t be any incompatibility problems with the user device after reset GPIO23 GPIO20 Mode selected RS422 driver RS422 COM3 232EN COM3 422EN receiver O default 1 default All off Tri stated Tri stated Tri stated 1 RS4xx output Enabled Enabled Tri stated buffer enabled 1 RS4xx output Enabled Tri stated Tri stated buffer disabled RP 1 RS232 Tri stated Tri Stated Enabled To operate in RS 4xx mode signal COM3 TE GPIO57 must be high just as COMI TE GPIO56 must be high in order for COMI to operate in RS 4xx mode These GPIO lines are routed from the 6300ESB ICH and can be programmed as described in Intel s Inte
19. gent subsystem and the bridge is configured in Non Transparent mode so that local resources will not be accessed by the system slot card Please see the figure below 8 C3PM cPCI Pentium Processor Board User s Manual Dynatem Chapter 3 Hardware Description 6300ESB i 6300ESB ICH i ICH Transparent Non Trans PCI Bridge PCI Bridge System Slot This drawing shows how the C3PM operates differently depending on whether it s in the system slot on the backplane denoted by a triangle or one of the remaining peripheral slots denoted by circles silkscreened on the backplane When in the system slot the six additional REQ GNT pairs and six additional clocks are routed to the backplane in compliance with the PICMG CompactPCI spec These additional CLK and REQ GNT lines are not used when the C3PM is installed in a peripheral slot They are in a tristate mode A transparent PCI bridge is meant to provide electrical isolation to the system It allows additional loads and devices to be attached to the bus and can also be used to operate dissimilar PCI Bus data widths and speeds on the same system For example a transparent bridge can allow several 32 bit 33 MHz PCI devices to attach to a 64 bit 66 MHz PCI X slot A non transparent PCI bridge offers address isolation in addition to electrical isolation Devices on both sides of the bridge retain their own independent Memory space and data from one side of the bridge is forw
20. is shown below The sections that follow describe the major functional blocks of the C3PM Intel Pentium M Processor 3 2 GB s System Bus E Addressing at 200 MHz Data at 400MT s SDRAM DDR 267 512 MB 2 136 GB s rmware Hu Rear 8 bit HI 1 5 266 MB s VGA Compact LPC Bus I 1 Flash lm m 1 Carrier COM2 64 bit PCI X 66 MHz Intel PLX6254 22046 PCI PCI Bridge p DualENET SATA 2x USB coms A RS232 422 485 05292 422748 kr na AAA In Ia i Compact PCI J1 1 i Compact PCI J2 LE bb m II m m m ae ear a cas TT a car as ec ca Dynatem C3PM cPCI Pentium Processor Board User s Manual 5 Chapter 3 Hardware Description LL 3 2 Processor The C3PM supports a Pentium M processor at 1 4 GHz The Intel Pentium M processor with 2 MB of L2 cache is meet the current and future demands of high performance low power embedded computing making it ideal for communications mobile applications vehicles and industrial automation applications While incorporating advanced processor technology it remains software compatible with previous members of the Intel microprocessor family e 400 MHz front side bus e 4MB of L2 cache for fast large table look ups routing tables e Advanced branch prediction Micro op fusion Hardware stack manager for faster processing e Second generation Streaming SIMD Extensions Streaming SIMD Extensions 2 capability adds 144 new instructions includi
21. l 6300ESB I O Controller Hub Datasheet 14 C3PM cPCI Pentium Processor Board User s Manual Dynatem Chapter 4 Installation AAA 4 3 Discrete I O vs COM1 Line Routing The C3PM uses optional O ohm resistors to select between discrete I O and full COMI support COMI RxD and TxD in RS 232 mode RS 4xx mode won t work as differential pairs are required are routed directly to the J2 backplane connector but the six additional handshaking lines can alternatively be used for discrete I O depending on how these 0 ohm resistors are populated These resistors CANNOT be modified by the customer without voiding the warranty unless permission is granted by Dynatem 800 543 3830 The photo below shows the solder side of the C3PM and the yellow dashed box indicates these 0 ohm optional resistors The drawing to the right of the photo corresponds to the resistor layout in the yellow box Green resistors route COMI lines and goldenrod resistors route GPIO lines when populated The optional resistors are horizontal to each other either R251 is populated or R52 R247 is populated or R248 etc The factory default option is to populate the goldenrod resistors for full GPIO support Not all lines must be used for COMI or for GPIO and the following table indicates the functionality routed by the various resistors Si ET FR_ WET a TH 9 yap a Dynatem C3PM cPCI Pentium Processor Board User s Manual 15 Chapter 4 Installation
22. ng 128 bit SIMD integer arithmetic and 128 bit SIMD double precision floating point operation e Fully compatible with existing Intel Architecture based software For further information on the Pentium M processor available from Intel Corporation search at http www intel com design intarch pentiumm pentiumm htm The Intel Pentium M processor was designed from the ground up with a new microarchitecture that delivers high performance with low power consumption With its 90 nm processing technology and 2 MB of L2 advanced transfer cache the Pentium M offers more performance per Watt The Pentium M also offers a dedicated hardware stack manager that employs sophisticated hardware control for improved stack management advanced branch prediction capability and a 400 MHz front side bus to the memory controller hub 3 3 Chipset The Intel 855GME Graphics Memory Controller Hub GMCH and Intel 6300ESB I O Controller Hub ICH chipset create an optimized integrated graphics solution with a 400 MHz system bus and integrated 32 bit 3D core at 133 MHz The 855GME GMCH provides a 266 MHz interface to DDR RAM 72 bits wide with ECC The C3PM can be populated with one or two banks of DRAM for 512 MB or 1 GB of total memory respectively The GMCH system memory architecture is optimized to maintain open pages up to 16 kB page size across multiple rows As a result up to 16 pages across four rows is supported To complement this the GMCH
23. on PICMG 2 0 R3 0 and other CompactPCI Specifications http www picmg org compactpci stm CompactPCISpecifications e The PCI PCI Bridge through which the C3PM accesses the backplane PCI bus is the PC16254 from PLX http www plxtech com products fastlane pci 254 asp e Silicon Laboratories CP2102 USB UART interface device for COM3 http www silabs com public documents tpub_doc dsheet Microcontrollers Interface en cp2102 pdf The following documents provide information on the PC architecture and I O e PCI Local Bus Specification Revision 2 2 http www pcisig com specifications e PCI X Specification Revision 1 0A http www pcisig com specifications e System Management Bus Specification SMBus Revision 1 1 http www smbus org specs e Universal Serial Bus Specification http www usb org developers The following documents cover topics relevant to the cPCI and can be purchased through PICMG http www picmg org v2internal specifications htm Dynatem C3PM cPCI Pentium Processor Board User s Manual 3 Chapter 2 Related Documents EEE EE FE A 4 C3PM cPCI Pentium Processor Board User s Manual Dynatem Chapter 3 Hardware Description 3 Hardware Description 3 1 Overview There are presently two revisions of the C3PM Rev A amp Rev B In this and subsequent chapters the differences between the two versions will be described where there are differences The block diagram of the C3PM
24. will tend to keep pages open within rows or will only close a single bank on a page miss The 855GME also has an advanced integrated graphical display controller The C3PM routes its VGA port through the J2 connector to the system backplane The X3PMRIO rear plug in card combines provides a high density DB 15 connector for the VGA port The 6300ESB I O Controller Hub ICH provides most of the C3PM s on board I O and it s the C3PM s PCI and PCI X expansion bridge The ICH is designed as a low power high performance I O hub that features e 64 bit 66 MHz PCI X expansion that is routed on the C3PM to the 82546 dual channel Fast Ethernet Controller 6 C3PM cPCI Pentium Processor Board User s Manual Dynatem Chapter 3 Hardware Description EEE na e 32 bit 33 MHz PCI bus that supports the PCI6254 PCI PCI bridge to the backplane e Two USB 2 0 compliant ports that are routed to the J2 connector to the backplane and to the optional X3PMRIO rear I O module where industry standard USB connectors are provided e Integrated IDE controller supports Ultra 100 DMA Mode Transfers for up to 100 MB sec read cycles and 88 88 MB sec write cycles for a CompactFlash drive on board e Serial ATA port providing a 150 MB sec data rate is routed through J2 e Standard PC functionality like a battery backed RTC and 256 bytes of CMOS RAM Power Management Logic Interrupt Controller Watchdog Timer Integrated 16550 compatible UART s and multime
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