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Errata Sheet

1. Errata Sheet 11 49 V1 1 2007 06 21 oo Infineon Errata Sheet XC167Cl 32F E ES BB BB Functional Problems Workaround 2 when stack modification method M1 is used To avoid generation of the unjustified PACER trap e use RETS to branch to the modified return address CSP IP after manipulation of the system stack In case the last subroutine call was only an intra segment CALL extend the last stack frame with CSP and e use a real return instruction e g RETS instead of the virtual RETV when the last executed call instruction was the last instruction of a code section followed by a data section This ensures that a valid instruction is located after the original CALL S instruction Workaround 3 when stack modification method M2 is used To avoid generation of the unjustified PACER trap e use RETI to branch to the modified return address CSP IP after manipulation of the system stack RETI does not affect the Return Stack In this case the PSW must be pushed on the system stack in addition to the components of the modified return address CSP and IP m g PUSH PSW push current contents of PSW PUSH Rx push return segment address CSPm PUSH Ry push return address IPm RETI branch return to CSPm IPm Workaround 4 After manipulation of the return address on the system stack perform a sequence of 6 CALL instructions followed by 6 return instructions This will clear the Return S
2. 1X3 to automatically use one of the local banks via the bank selection registers BNKSELO 3 i e the interrupting routine has a priority level gt 12 e Before the corresponding interrupt service routine is finished another interrupt request Task C occurs which is programmed with GPRSELx 00 to automatically use the global bank via the bank selection registers BNKSELO 3 i e the interrupting routine has a priority level gt 13 In this case service of this interrupt request for Task C is delayed until bit field PSW BANK becomes 00 after executing the RETI instruction at the end of the routine Task B using the local bank Errata Sheet 15 49 V1 1 2007 06 21 oo Infineon Errata Sheet XC167Cl 32F E ES BB BB Functional Problems Task A Task B Task C Task A Global Bank gt Local Bank ls Global Bank gt Global Bank nee z RETI nterupt l a baaa Task C ha a Register Bank Validation Ree _ finished SCXT CP RETI ee Task B y Register Bank Validation interrupted gt me Task C Delayed Figure 1 Example for Case 2 Interrupt Service for Task C delayed Workaround for Case 1 Do not write to the CP register i e modify the context of a global bank while a local register bank context is selected Workaround for Case 2 When using both local and global register banks via the bank selection registers BNKSELO 3 for interrupts on levels gt 12 ensure that there is no int
3. program security is always preceded by a programming or erase operation to the same area otherwise wrong data may be stored An erase operation to either area program security is always executed correctly independent of the preceding operation In other words e make sure that no erase program operation to the program flash or reset occurs between erasing and programming of an area in the security sector e make sure that no erase program operation to the security sector is executed between erasing and programming of an area in the program flash TwinCAN_AI D1 Reserved Bits in Registers of the TwinCAN Module Reserved bits in registers of the TwinCAN module are marked as 0 r or 1 r read only in the User s Manual Actually these bits are implemented as RAM read write bits that are initialized with the reset value documented in the User s Manual This means that these bits can be modified by software This will not present a problem as long as these bits when written by software are written with their specified reset values 0 or 1 respectively In this case they will always return their specified reset value when they are read by software There is only one exceptional case which is described as TwinCAN_AI 010 Reserved Bits in Register MSGARHn 15 13 No problem can occur in principle if these bits are ignored e g masked off when they are read CPU_X D1 Write Operations to Control Registers After write oper
4. Application Hints No speculative reads are performed in memory areas which are marked as O area This memory area includes e the SFR and ESFR space e g with buffers for received data from serial interfaces or A D results e the 4 Kbyte internal I O area 00 E000 0O EFFF including IIC and SDLM module e the 2 Mbyte external I O area 20 0000 3F FFFF including the TwinCAN module default from 20 0000 20 07FF It is therefore recommended to map devices which do not tolerate speculative reads into the 2 Mbyte external I O area 20 0000 3F FFFF For further special properties of the I O areas see section IO Areas 3 6 in chapter Memory Organization in the User s Manual FLASH_X H1 1 Access to Flash Module after Program Erase After the last instruction of a program or erase command the BUSY bit in register FSR is set to 1 status busy after a delay of one instruction cycle When polling the BUSY flag one NOP or other instruction which is not evaluating the BUSY flag must be inserted after the last instruction of a program or erase command No additional delay is required when performing the first operand read or instruction fetch access from the flash module after the BUSY bit has returned to 0 status not busy FLASH_X H2 2 Access to Flash Module after Shut Down When the flash is disabled by software shut down by writing bit PFMDIS 1 in register SYSCONS e and it is at some
5. for 3 ns before they are tristated This may result in undefined logic levels on the non multiplexed part of the external address bus during an internal LXBus cycle However no external chip select signal CSx or ALE RD WR strobe is active during an internal LXBus cycle Workaround Not needed if external circuitry does not evaluate levels on external address bus during internal LXBus cycles Errata Sheet 6 49 V1 1 2007 06 21 oo Infineon Errata Sheet XC167Cl 32F E ES BB BB Functional Problems CPU_X 002 Branch to wrong target after mispredicted JMPI After a JMPI is initially mispredicted according to the static branch prediction scheme of the C166S V2 code execution may continue at a wrong target address in the following situations Situation l e a memory write operation is processed by the DMU e followed by a MUL U e followed by the mispredicted JMPI Example 1 MOV mem Rwn MUL R13 R14 JMPI cc_NV R6 Situation Il e MUL U or DIV L U LU e followed by not mispredicted zero cycle jump e g JMPA JMPR JMPS bit ZCJ CPUCON1 0 1 e followed by the mispredicted JMPI Example 2a MULU R13 R14 JMPA cc V some target predicated not taken gt correct JMPI cc_NV R6 taken but predicted not taken It could be possible that the JMPI is at the jump target of the JMPA if it is taken Example 2b MULU R13 R14 JMPA cc NZ Jmpi addr predicted taken gt correct ree othe
6. 3 reserved bits MSGARHn 15 13 in the Message Object n Arbitration Register may be erroneously loaded with non zero values i e different from their reset values under an arbitration loss condition Workaround If the received identifier is checked by software the software should be written in a way that these bits have no impact on the decision e g by masking off the upper 3 bits FLASH _X 004 PACER Trap after Wake Up from Sleep Idle Mode An unexpected Program Access Error Trap flag PACER 1 in register TFR occurs after a wake up event from sleep or idle mode under the following conditions e bit field PFCFG 01 in register SYSCON1 i e the flash module is switched off during sleep or idle mode e a wake up event interrupt PEC transfer NMI occurs in a specific time window few clock cycles after execution of the IDLE instruction during the flash deactivation process e and the corresponding interrupt trap routine or the instruction following IDLE in case interrupts are disabled or the PEC source data are located in the internal flash Workaround 1 Do not switch off the flash module in sleep or idle mode i e leave bit field PFCFG 00 in register SYSCON1 default after reset This increases power consumption to a certain extent while reducing the time overhead for sleep idle mode entry and exit in clocking modes where the clock is derived from the VCO Workaround 2 In order to avoid the problem when PFCFG 0
7. CPU_X 002 or application hint BREAK_X H71 CPUCON2 reset recommended value 8FBB enables several performance features CPUCON1 reset recommended value 0 0 OXXX X111 only the 3 LSBs are performance related Bit Position Field Value Description Name CPUCON1 15 7 0 0 reserved CPUCON1 6 5 VECSC 00 scaling factor for vector table value depends on application 00 is compatible to C166 systems CPUCON1 4 WDTCTL 0 configuration for scope and function of DISWDT ENWDT instructions value depends on application 0 is compatible to C166 systems CPUCON1 3 SGTDIS O segmentation enable disable control value depends on application CPUCON1 2 INTSCXT 1 enable interruptibility of switch context CPUCON1 1 BP 1 enable branch prediction unit CPUCON1 0 ZCJ 1 enable zero cycle jump function CPU_X H2 Special Characteristics of I O Areas As an element of performance optimization the pipeline of the C166S V2 core may perform speculative read accesses under specific conditions In case the prediction for the speculative read was wrong the read to the actually required location is restarted While this method is uncritical e g for accesses to non volatile memories or SRAMs it may cause problems on devices which do not tolerate speculative reads e g FIFOs which are advanced on every read access Errata Sheet 28 49 V1 1 2007 06 21 oo Infineon Errata Sheet XC167Cl 32F E ES BB BB
8. ES BB BB Functional Problems 2 Functional Problems EBC X 003 TwinCAN Access with EBC enabled If the External Bus Controller EBC is enabled a read or write access to the TwinCAN module fails when an external bus access with TCONCSx PHA 00 precedes the TwinCAN access Workaround Since it is hard to predict the order of external bus and TwinCAN accesses in particular when PEC transfers are involved it is recommended to set bitfield PHA to 00 in all TCONCSx registers which are used for external bus accesses EBC _X 006 Visibility of internal LXBus cycles on external address bus When an external bus is enabled accesses to internal LXBus modules are to some extent reflected on those parts of the external address bus that is not multiplexed i e on those pins of Port 4 that are configured as segment address lines and on the pins of PORT1 P1L P1H if a non multiplexed external bus mode is enabled in one of the FCONCSx registers The effect is as follows a After an LXBus access e g to the TwinCAN module the address of the location accessed last on the LXBus remains visible on the non multiplexed part of the external address bus unless an external bus cycle immediately follows the LXBus cycle b During an internal LXBus access the external address bus is tristated Due to an internal race condition the pads on the non multiplexed part of the external address bus may already start to drive the LXBus address
9. details should be considered Errata Sheet 23 49 V1 1 2007 06 21 oo Infineon Errata Sheet XC167Cl 32F E ES BB BB Functional Problems e If hardware traps including NMI can occur add the corresponding interrupt vectors to PRAM and modify register VECSEG to point to the PRAM space e In order to support return to idle sleep mode after a PEC transfer e g a semaphore bit may be used This bit may be set to 1 before the IDLE instruction is executed All trap and interrupt service routines invoked after wake up from idle sleep should clear this bit to 0 After having returned to the program in the internal flash and having enabled the interrupt system this bit should be tested allow a sufficient time of e g 12 cycles for interrupt arbitration and if it is still at 1 i e no interrupts traps have occurred repeat the auxiliary routine that prepares for re entry into idle sleep mode ASC_X 001 ASC Autobaud Detection in 8 bit Modes with Parity The Autobaud Detection feature of the Asynchronous Synchronous Serial Interface ASC does not work correctly for 8 bit modes with even or odd parity The Autobaud Detection feature works correctly for 7 bit modes with even or odd parity and for 8 bit modes without parity GPT12E_ X 001 T5 T6 in Counter Mode with BPS2 1X When T5 and or T6 are configured for counter mode bit field TxM 001 in register GPT12E_TxCON x 5 6 and bit field BPS2 1X in register GPT12E_T6CO
10. executed after the interrupt system has been enabled and if the semaphore Errata Sheet 30 49 V1 1 2007 06 21 oo Infineon Errata Sheet XC167Cl 32F E ES BB BB Application Hints bit is still at 1 i e no interrupts traps have occurred disable interrupts and return to the IDLE instruction SLEEP_X H3 2 Clock system after wake up from Sleep Mode There are different wake up behaviors depending on the PLL control setting used in register PLLCON during entry into sleep mode and depending on whether the RTC is running on the main oscillator Note that in either case the VCO is turned off during sleep mode and does not contribute to any additional power consumption In bypass mode with VCO off PLLCTRL 00 the device will directly continue to run on the frequency derived from the external oscillator input after wake up from sleep If the RTC is running on the main oscillator the device is immediately clocked since the oscillator input XTAL1 is not turned off during sleep mode If the RTC was not running on the main oscillator the system will not be clocked until the amplitude on the external oscillator input XTAL1 exceeds the input hysteresis This requires typ a few ms depending on external crystal oscillator circuit With this mode there is no oscillator watchdog function and the system will not be clocked until the external oscillator input XTAL1 receives a clock that exceeds the input hysteresis In bypass m
11. interrupt request that has won interrupt priorization at the beginning of an ATOMIC EXTEND sequence is processed after the ATOMIC EXTEND sequence When an xx_IR or xx_lE flag is cleared within an ATOMIC EXTEND sequence the associated interrupt might still be acknowledged after the end of the ATOMIC EXTEND sequence Therefore e g the following sequence is not recommended if the intention is that no more Timer 2 interrupts can occur after the BCLR GPT12E_T2Ix instruction ATOMIC 3 BCLR GPT12E_T21IE clear Timer 2 interrupt enable flag NOP NOP Timer 2 interrupt might still occur after this instruction INT_X H002 Increased Latency for Hardware Traps When a condition for a HW trap occurs i e one of the bits in register TFR is set to 1 the next valid instruction that reaches the Memory stage is replaced with the corresponding TRAP instruction In some special situations described in the following a valid instruction may not immediately be available at the Memory stage resulting in an increased delay in the reaction to the trap request 1 When the CPU is in break mode e g single stepping over such instructions as SBRK Or BSET TFR x where x one of the trap flags in register TFR will have no immediate effect until the next instruction enters the Memory stage of the pipeline i e until a further single step is performed 2 When the pipeline is running empty due to mispredicted branches and a relatively slow program
12. later time enabled again by writing PFMDIS 0 e and the instruction immediately following the instruction which sets PFMDIS 0 is fetched or reads operands from internal flash then the PACER flag in register TFR is set and the BTRAP routine is entered Therefore it is recommended to insert 4 NOPs before the internal flash is accessed again after PFMDIS has been set to 0 1 this module is implemented in specific derivatives of the XC166 family Errata Sheet 29 49 V1 1 2007 06 21 oo Infineon Errata Sheet XC167Cl 32F E ES BB BB Application Hints FLASH_X H3 2 Read Access to internal Flash Module with modified Margin Level When the internal flash module is read e g for test purposes with modified margin level i e bitfield MARLEVSEL 0001 or 0100 in register MAR an additional wait state must be selected in bitfield WSFLASH in register IMBCTR This waitstate must be added to the number of flash waitstates that are required to match the flash access time to the CPU operating frequency FLASH_X H4 Minimum active time after wake up from sleep or idle mode If the flash module is automatically disabled upon entry into sleep or idle mode bit field PFCFG 01 in register SYSCON 1 sleep or idle mode should not be re entered before a minimum active awake time has elapsed Otherwise the current consumption during this sleep idle phase will be 1 mA above the specified limits of the Data Sheet Therefore e If co
13. table below Otherwise incorrect data may be read from the internal flash module or program or erase operations may fail if this condition is present while the respective operation is in progress e when the input low level on pin P9 4 CC2010 does not exceed the negative supply voltage Vggp as listed in the table below Otherwise an erase operation of the internal flash module may fail if this condition is present while an erase operation is in progress Conditions for Amplitude and Width of Input Signal No problem will occur for signals on pin P9 2 CC18IO CAN1_RxD with the following characteristics e for low or high pulses with an amplitude Vin lt Vppp 0 5V or Vin gt Vggp 0 5V and pulse width lt 100 ns and duty cycle DC lt 0 33 e g high pulses lt 100 ns with this amplitude are tolerated if the following low phase is gt 200 ns e for steady state signals or pulses gt 100 ns with an amplitude Vin lt Vppp 0 2V or Vin gt Vggp 0 2V No problem will occur for signals on pin P9 4 CC20I0 with the following characteristics e for low pulses with an amplitude Vin gt Vgcgp 0 5V and pulse width lt 1 us and duty cycle DC lt 0 33 e g low pulses lt 1 us with this amplitude are tolerated if the following high phase is gt 2 us e for steady state signals or low pulses gt 1 us with an amplitude Vin gt Vgcp 0 3V Typical overshoot undershoot after signal transitions is normally uncritical covered by duty cycle spec
14. 1 make sure that the wake up trigger only occurs after the device has completely entered sleep or idle mode If the RTC is used as wake up source check e g the RTC before entering sleep mode If the wake up trigger will occur soon either skip entry into sleep mode or extend the time for the next wake up If the RTC time interval is reprogrammed make sure that no interrupt occurs between reprogramming and entry into sleep mode Errata Sheet 22 49 V1 1 2007 06 21 oo Infineon Errata Sheet XC167Cl 32F E ES BB BB Functional Problems Workaround 3 In order to differentiate an unexpected PACER trap due to a wake up trigger in the critical time window from other events that can lead to a PACER trap set a semaphore bit before executing the IDLE instruction e g ATOMIC 2 BSET sema_ idle IDLE In the trap handler for the PACER trap if the semaphore bit is set and no other indications for the PACER trap are found e g error flags in register FSR are set clear the semaphore bit and the PACER flag and return from the trap handler with RETI The stack contains a valid return address in this case e g address of instruction following IDLE in case interrupts were disabled during wake up For PEC transfers during sleep or idle mode which will cause a PACER trap if they read data from flash automatic return to sleep idle mode is not accomplished with the concept described so far e In order to support return to idle sleep mo
15. CON Emulation control SCU WDTCON Watchdog timer properties SCU EXICON Ext interrupt control SCU EXISELO EXISEL1 Ext interrupt control SCU CPUCON1 CPUCON2 CPU configuration CPU EBCMODO EBCMOD1 EBC mode selection EBC TCONCSx EBC timing configuration EBC FCONCSx EBC function configuration EBC ADDRSELx EBC address window configuration EBC TwinCAN_AI 007 Transmit after Error During a CAN error transmission may stop after EOF or an error frame until a successful reception or a write access to the TwinCAN module Detailed Description In case of a CAN error and when there is no other activity on the CAN module e g frame reception or frame transmission on the other CAN node or write access to any CAN register the transmission of messages may stop even if some transmit requests are still set The CAN module will start transmitting immediately after a reception or a write access to the module Workarounds e Write periodically FFFF to one of the MSGCTRx registers as this value is having no effect on the register Errata Sheet 20 49 V1 1 2007 06 21 oo Infineon Errata Sheet XC167Cl 32F E ES BB BB Functional Problems e Incase writing to a CAN register shall be the exception use the last error code LEC interrupt This shall start writing to one of the MSGCTRx register FFFF in case the LEC value is unequal to 0 TwinCAN_AI 008 Double remote request After the transmission of the remote request TX
16. CU_X D7 TwinCAN_AI 007 Transmit after error former name TwinCAN2 007 TwinCAN_X 007 TwinCAN_AIl 008 Double remote request former name TwinCAN2 008 TwinCAN_X 008 TwinCAN_AIl 009 CPUUPD remote former name TwinCAN2 009 TwinCAN_X 009 TwinCAN_AIl 010 Reserved Bits in Register MSGARHn 15 13 FLASH_X 004 PACER trap after wake up from Sleep Idle mode ASC_X 001 ASC Autobaud Detection in 8 bit Modes with Parity Errata Sheet 2 49 V1 1 2007 06 21 Errata Sheet XC167CIl 32F E ES BB BB Cinfineon History List Change Summary Table 1 Functional Deviations cont d Functional Short Description Fixed Change Problem in step GPT12E_X 001_ T5 T6 in Counter Mode with BPS2 1X new Table 2 OCDS and OCE Modules Functional Short Description Fixed Change Problem in step OCDS_X 002 OCDS indicates incorrect status after break_now requests if PSW ILVL 2 CMCTR LEVEL OCE_X 001 Wrong MAC Flags are declared valid at Core OCE interface Table 3 AC DC Deviations AC DC Short Description Fixed Change Deviations in step FCPUR_X 1628 Frequency Limits for Flash Read Accesses BB see Data Sheet V1 0 and higher M40_WLE_X 001 Minimum Ambient Temperature for Flash Wordline Erase Command Table 4 Application Hints Hint Short Description Change CPU_X H1 Configuration of Registers CPUCON1 and CPUCON2 CPU
17. Infineon Errata Sheet V1 1 2007 06 21 Device XC167Cl 32F Marking Step E ES BB BB Package PG TQFP 144 7 P TQFP 144 19 This Errata Sheet describes the deviations from the current user documentation The module oriented classification and numbering system uses an ascending sequence over several derivatives including already solved deviations So gaps inside this enumeration can occur This Errata Sheet applies to all temperature SAB SAF SAK and frequency versions 20 40 unless explicitly noted otherwise Versions beginning from V1 0 apply to the current documentation rules Current Documentation e XC167CI 32F Data Sheet V1 1 2006 08 e XC167 32 User s Manual V1 0 Volume 1 System Units 2004 06 e XC167 32 User s Manual V1 0 Volume 2 Peripheral Units 2004 06 e C166S V2 User s Manual Core Instruction Set V1 7 2001 01 for viewing click on weblinks above and follow link to Documents Note Devices additionally marked with EES or ES or E followed by a 3 digit date code are engineering samples which may not be completely tested in all functional and electrical characteristics therefore they should be used for evaluation only The specific test conditions for EES and ES are documented in a separate Status Sheet Note For simplicity all versions are referred to by the term XC 167CI 32F throughout this document Contents SEGUON atte ete iwventscenthcdadbeead saad emateed wine de Bbw eek bee
18. N then edge detection for the following count input and control signals does not work correctly TSIN T6IN TSEUD T6EUD Note The configuration where T5 counts the overflow underflow events of T6 is not affected by this problem Workaround Do not set bit field BPS2 1X in register GPT12E_T6CON when T5 and or T6 are configured for counter mode Use only settings BPS2 OX when T5 and or T6 are configured for counter mode Errata Sheet 24 49 V1 1 2007 06 21 oo Infineon Errata Sheet XC167Cl 32F E ES BB BB OCDS and OCE Modules 3 OCDS and OCE Modules The following issues have been found in the OCDS and OCE modules Please see the debugger or emulator manufacturer s documentation whether or not these issues actually cause a problem or restriction when the respective tool is used OCDS_X 002 OCDS indicates incorrect status after break_now requests if PSW ILVL gt CMCTR LEVEL When the OCDS processes a break_now request while the CPU priority level in PSW ILVL is not lower than the OCDS break level in CMCTR LEVEL the actual break is delayed until either PSW ILVL or CMCTR LEVEL is reprogrammed such that CMCTR LEVEL gt PSW ILVL If in the meantime further debug events have occurred register DBGSR will still indicate the status of the first break_now request If e g a software break is executed the OCDS will accept this but register DBGSR will indicate the wrong cause of break Workarounds 1 If the applicati
19. ORed bitwise with the contents of OPSEN It is recommended to leave bit OPSEN 5 PFLSEN at its default value 0 Otherwise the program flash is deactivated when a breakpoint is hit i e it can not be read and it has to ramp up when program execution is resumed i e synchronization between software and peripherals is lost Errata Sheet 46 49 V1 1 2007 06 21 eo Errata Sheet Infineon XC167CI 32F E ES BB BB Documentation Update SCU_X D3 Register PLLCON after software reset Register PLLCON is not affected by a software reset i e the current clock configuration remains unchanged PLLCON may be reconfigured by software or an endless loop terminated by a watchdog timer reset may be used to force PLLCON to its hardware reset value SCU_X D5 VCO band after hardware watchdog reset in single chip mode From the falling edge of RSTIN until 2048 stable oscillator clocks after the rising edge of RSTIN always the lowest VCO band is selected After that for a hardware or watchdog timer reset in single chip mode PLL bypass mode with the lowest VCO band is selected during the internal reset phase PLLCON 2710 See also application hint POWER_X H2 2 SCU_X D6 Register Security Mechanism Unprotected Mode active until execution of EINIT instruction After reset the Unprotected Mode is selected by default bitfield SL 00 in register SCUSLS This allows the initialization software to handle all SFRs with or without reg
20. RQ is not cleared in the receive object if NEWDAT is set As a consequence the remote request is transmitted once again Workaround Clear NEWDAT after the reception of a data frame TwinCAN_AI 009 CPUUPD remote In case of a remote request to a standard message object which is chosen for transmission a transmit of the data frame takes place even if CPUUPD is currently set Detailed Description If a transmit message object gets a remote request and there is no other message object with higher transmit priority pending for transmission then the transmit object sends the data frame to answer the remote request even if CPUUPD is set Workaround This workaround is only required in systems where remote requests are used To answer remote requests the MMC bitfield in MSGFGCR has to be configured to a FIFO slave object instead of a standard message object for transmission To reach this goal the following settings for the corresponding message object are needed e bitfield MMC MSGFGCRHn 10 8 011 FIFO functionality enabled slave object e bitfield CANPTR MSGFGCRHn 4 0 n the CAN Pointer shall reference itself by referring to the message object number of this object e bit FD MSGFGCRLn 13 0 the CANPTR is updated after a correct reception Errata Sheet 21 49 V1 1 2007 06 21 oo Infineon Errata Sheet XC167Cl 32F E ES BB BB Functional Problems TwinCAN_AI 010 Reserved Bits in Register MSGARHn 15 13 The
21. T the Unsecured Mode is active and no unlock sequence is required Errata Sheet 39 49 V1 1 2007 06 21 oo Infineon Errata Sheet XC167Cl 32F E ES BB BB Application Hints If instead the CPUCON1 or CPUCON2 register must be modified using Secured Mode the following sequence is recommended Example MOV R4 8FBBH Value to be stored in register CPUCON2 EXTR 2 Access sequence in secured mode use EXTR 4 to avoid interrupts if interrupts are enabled at this time MOV SCUSLC 8E12H Command4 current password EDH MOV ZEROS SCUSLC Dummy read of SCUSLC control register to ensure Command 4 is in effect 1 before continuing MOV CPUCON2 R4 Access to CPUCON2 enabled by preceding Command4 MOV IDCHIP ZEROS Dummy write to a read only SCU register re enables secured mode RTC_X H1 1 Resetting and Disabling of the Real Time Clock The clock source for the RIC can be selected by software via bit REFCLK RTC_CON 4 e REFCLK 0 RTC count clock signal is foscaux input XTAL3 e REFCLK 1 RTC count clock signal is foscmain 32 input XTAL1 Register RTC_CON is not affected by a hardware software watchdog reset After power up it is undefined A reset of the RTC module is achieved by setting bit SYSCONO 15 RTCRST 1 This way register RTC_CON is set to 8003 RTC runs prescaler by 8 enabled bit REFCLK 0 The RTC clocking mode synchronous asynchronous is determine
22. V1 1 2007 06 21 oo Infineon Errata Sheet XC167Cl 32F E ES BB BB Deviations from Electrical and Timing Specification 4 Deviations from Electrical and Timing Specification M40_WLE_X 001 Minimum Ambient Temperature for Flash Wordline Erase Command When the Erase Wordline command is executed at low temperature data in other wordlines of the same physical 64 Kbyte sector may unintentionally be modified in addition The effect depends primarily on the ambient temperature and the internal CPU frequency and may vary from device to device Workarounds choices e Do not use the Erase Wordline Command below 20 C e Reduce the internal CPU frequency to 0 5 MHz when using the Erase Wordline Command below 20 C After the Erase Wordline Command has been started the CPU frequency may be increased again to the target value e Use the Erase Sector Command instead of the Erase Wordline Command Errata Sheet 27 49 V1 1 2007 06 21 oo Infineon Errata Sheet XC167Cl 32F E ES BB BB Application Hints 5 Application Hints CPU_X H1 Configuration of Registers CPUCON1 and CPUCON2 The default values of registers CPUCON1 and CPUCONZ2 have been chosen to provide optimized performance directly after reset It is recommended e not to modify the performance related parts of register CPUCON1 e not to modify register CPUCON2 except for test purposes or for enabling specific workarounds under special conditions see e g problem
23. X 009 Delayed Interrupt Service of Requests using a Global Bank Service of an interrupt request using a global register bank is delayed regardless of its priority if it would interrupt a routine using one of the local register banks in the following situations Case 1 e The Context Pointer CP is written to e g by POP MOV SCXT instructions within a routine that uses one of the local register banks bit field PSW BANK 10 or 11b e Then an interrupt request occurs which is programmed with GPRSELx 00 to automatically use the global bank via the bank selection registers BNKSELO 3 i e the interrupting routine has a priority level gt 12 Note that this scenario is regarded as untypical case because this would mean that the routine using one of the local banks modifies the CP contents of a global bank In this case service of the interrupt request is delayed until bit field PSW BANK becomes 00s e g by explicitly writing to the PSW or by an implicit update from the stack when executing the RETI instruction at the end of the routine using the local bank Case 2 see also Figure 1 e The Context Pointer CP is written to e g by POP MOV SCXT instructions within a routine Task A that uses a global register bank bit field PSW BANK 00 i e the context for this routine will be modified e This context switch procedure 19 cycles is interrupted by an interrupt request Task B which is programmed with GPRSELx
24. _X D2 144 Internal Pull up Devices active on pins P4 3 0 and P3 12 during Reset In addition to the pins mentioned in chapter 6 1 4 System Startup Configuration internal pull up devices are active on pins P4 3 0 during a hardware reset low level on pin RSTIN The pull ups are turned off after the rising edge on pin RSTIN on pin P3 12 during the internal reset phase of each reset including hardware software and watchdog timer reset The electrical characteristics of these internal pull up devices are described in section DC Characteristics of the Data Sheet by the parameters Level inactive hold current symbol p and Level active hold current symbol Lpa If any of these pins needs to be on a low level during reset external pull down devices that meet this specification must be used SCU_X D2 2 Functionality of register OPSEN When a breakpoint is hit the on chip peripherals selected in register OPSEN are stopped and placed in power down mode the same way as if disabled via register SYSCONS Registers of peripherals which are stopped this way can be read but not written A read access will not trigger any actions within a disabled peripheral The SYSCON3S bits return the shutdown status independently of the reason for the shutdown static shutdown via SYSCON3 or intermediate shutdown via OPSEN i e when SYSCONS is read via the debugger after a breakpoint has been hit it returns the contents of SYSCON3
25. _X H2 Special Characteristics of I O Areas FLASH_X H1 1 Access to Flash Module after Program Erase FLASH_X H2 2 Access to Flash Module after Shut Down FLASH_X H3 2 Read Access to internal Flash Module with modified Margin Level FLASH_X H4 Minimum active time after wake up from sleep or idle mode Errata Sheet 3 49 V1 1 2007 06 21 Cinfineon Errata Sheet XC167CIl 32F E ES BB BB History List Change Summary Table 4 Application Hints cont d Hint Short Description Change SLEEP_X H3 2 Clock system after wake up from Sleep Mode IDLE_X H1 Entering Idle Mode after Flash Program Erase ADC_X H1 Polling of Bit ADBSY BREAK_X H1 Break on MUL DIV followed by zero cycle jump OCDS_X H001_ Effect of Bit OCDSIOEN in Register EMUCON IIC_X H1 Maximum IIC Bus Data Rate at low fCPU IIC_X H2 Timing of Bit IRQD POWER_X H1 1 Initialization of SYSCON3 for Power Saving Modes POWER_X H2 2 Power Consumption during Clock System Configuration RSTOUT_X H1 RSTOUT driven by weak driver during HW Reset SCU_X H1 Shutdown handshake by software reset SRST instruction SCU_X H3 Effect of PLLODIV on Duty Cycle of CLKOUT SCU_X H4 Changing PLLCON in Emergency Mode SCU_X H5 Sleep Idle Power Down Mode not entered while PLLODIV OFh SCU_X H6 Interrupt request during entry into sleep mode SCU_X H7 VCO Configuration with Input Clock disconnected SCU
26. _X H8 PLL Bypass Mode with VCO on SCU_X H10 Register Security Mechanism usage with CPUCON1 and CPUCON2Z registers RTC_X H1 1 Resetting and Disabling of the Real Time Clock FOCON_X H1 Read Access to register FOCON OSC_X H001 Signal Amplitude on Pin XTAL1 TwinCAN_AI H2 Reading Bitfield INTID INT_X H1 Software Modifications of Interrupt Enable xx_IE or Interrupt Request xx_IR Flags INT_X HO02 Increased Latency for Hardware Traps new Errata Sheet 4 49 V1 1 2007 06 21 Cinfineon Errata Sheet XC167CIl 32F E ES BB BB History List Change Summary Table 5 Documentation Update Name Short Description Change INT_X D1 Interrupt Vector Location of CAPCOM Register 28 PORTS_X Internal Pull up Devices active on P4 0 3 and P3 12 during D2 144 Reset SCU_X D2 2 Functionality of register OPSEN SCU_X D3 Register PLLCON after software reset SCU_X D5 VCO band after hardware watchdog reset in single chip mode SCU_X D6 Register Security Mechanism Unprotected Mode active until execution of EINIT instruction FLASH_X D1 Interaction between Program Flash and Security Sector Programming TwinCAN_AI D1 Reserved Bits in Registers of the TwinCAN Module CPU_X D1 Write Operations to Control Registers ADC_X D3 ADC Sample Time with Improved Enhanced Timing Control ID Registers ID Registers Errata Sheet 5 49 V1 1 2007 06 21 oo Infineon Errata Sheet XC167Cl 32F E
27. ating after reset instead of being pulled high or low by an external pull device If used as inputs a series resistor will further reduce but can not under all circumstances fully exclude the risk in case the input levels described above are exceeded Furthermore the risk resulting from input signals exceeding these levels is reduced if the device is not operated at the upper limits of supply voltage temperature and frequency at the same time Errata Sheet 18 49 V1 1 2007 06 21 oo Infineon Errata Sheet XC167Cl 32F E ES BB BB Functional Problems SCU_X 011 Register Security Mechanism after Write Access in Secured Mode To modify an SFR that is protected by the register security mechanism a certain security level has to be selected and or a command sequence has to be executed prior to the write access to one of these registers Table 6 15 in the User s Manual volume System Units lists all registers protected by the security mechanism see copy of Table 6 15 below After selecting Secured Mode bitfield SL 01 in register SCUSLS a single command command4 enables one single write access to a protected register After this write access the protected registers are locked again automatically Exception After modification of registers CPUCON1 CPUCON2 EBCMODO EBCMOD1 TCONCSx FCONCSx ADDRSELx which are not part of the SCU all registers listed in Table 6 15 are not locked until the next write access to an SCU regi
28. ations to CPU core SFRs CSFRs that control important system parameters e g PSW DPPO 3 CPUCON1 2 SP etc see User s Manual chapter 4 for a complete summary of CSFRs internal control mechanisms e g pipeline stall ensure that the effect of the write operation has taken place when the following instruction is executed However for other SFRs not belonging to the CSFRs the effect of write operations may not yet be seen immediately within the next instruction This is because in general i e except for CSFRs the CPU is not able to recognize the need of holding the pipeline till Errata Sheet 48 49 V1 1 2007 06 21 eo Errata Sheet Infineon XC167CI 32F E ES BB BB Documentation Update the write is effective unless the write is followed by a read from the same address To ensure that in this case a write operation has been completed before making use of it it is recommended to make a read operation on the same memory location In addition there are other registers where a write operation triggers a state machine that may take several cycles to complete e g write to PLLCON SYSCONS3 Reading these registers immediately after a write usually returns the current status which may differ from the written value ADC_X D3 ADC Sample Time with Improved Enhanced Timing Control In enhanced mode bit MD 1 in register ADC_CTRO or in compatibility mode bit MD 0 with improved conversion and sample timing control
29. bear Page History List Change Summary 0 00 cece eee 2 Functional Problems 000 cee ete 6 OCDS and OCE Modules 0 00 ee 25 Deviations from Electrical and Timing Specification 27 Application Hints ae ee ere 28 Documentation Update 0 00 eee 46 Errata Sheet 1 49 V1 1 2007 06 21 Cinfineon Errata Sheet XC167CIl 32F E ES BB BB History List Change Summary 1 History List Change Summary from step E ES BA previous errata sheet V1 0 step E ES BB BB Table 1 Functional Deviations Functional Short Description Fixed Change Problem in step EBC_X 003 TwinCAN access with EBC enabled EBC_X 006 Visibility of internal LXBus cycles on external address bus CPU_X 002 Branch to wrong target after mispredicted JMPI CPU_X 003 Software Modification of Return Address on new System Stack in combination with RET RETP RETS instructions INT_X 007 Interrupt using a Local Register Bank during update execution of IDLE INT_X 008 HW Trap during Context Switch in Routine using new a Local Bank INT_X 009 Delayed Interrupt Service of Requests using a new Global Bank PORTS_X 012 1 Interference of Input Signals on POH 6 and P3 6 new with internal Flash SCU_X 010 Reset while PLL is not locked step E ES BA ES BA only BA SCU_X 011 Register Security Mechanism after Write Access in Secured Mode replaces S
30. bit ICST 1 in register ADC_CON1 the ADC sample time controlled via the 6 bit field ADSTC is defined as follows ts tac X 4 x lt ADSTC gt 2 instead of ts tg x 4 x lt ADSTC gt 1 This applies to the register description of the following registers e ADC_CON1 e ADC_CTR2 e ADC_CTR2IN The values and the formula for the sample time listed in chapter Conversion Timing Control and in particular in Table Improved Conversion and Sample Timing Control are correct ID Registers Register IDMANUF IDCHIP IDMEM IDPROG Device Step Address FO7E F07C FO7A F078 XC167CI 32F BB 1820 20024 30404 40404 Product and Test Engineering Group Munich Errata Sheet 49 49 V1 1 2007 06 21
31. crocontroller architectures that are optimized for real time applications the CPU operates in parallel to the interrupt system in order to minimize interdependencies resulting in delayed processing However in certain exceptional situations it is sometimes required by software to temporarily disable interrupts In the microcontrollers of the C166 and XC166 microcontroller families the interrupt system can be globally disabled with a single instruction e g via BCLR IEN clear IEN flag causes pipeline restart in C1l66S V2 core In the microcontrollers of the XC166 family with the C166S V2 core the pipeline side effects of the classic C166 core when globally disabling interrupts no longer need to be considered Nevertheless the special instruction sequences recommended to avoid these side effects of the C166 core will work without problems with the C166S V2 core Instead of globally disabling the interrupt system it might be appropriate in some cases to selectively clear an individual interrupt enable flag xx_IE e g via BCLR GPT12E T2IE clear Timer 2 interrupt enable flag Theoretically in the C166S V2 core an interrupt in this example from Timer 2 may still be accepted by the CPU for a few cycles after the BCLR GPT12E_T2IE instruction has been executed This is typically the case if the interrupt request occurs asynchronously to program execution i e if the software does not know when an event occurs and it is just abo
32. d by bit RTCCM SYSCONO 14 Note that register SYSCONO is not affected by a software or watchdog reset This means that when a software or watchdog reset occurred while the RTC module was in asynchronous mode selected by bit RTCCM SYSCONO 14 1 it will return to asynchronous mode after a RTC reset triggered by setting bit RTCRST SYSCONO 15 1 with a bit instruction For a software or watchdog reset that is followed by an initialization of the RTC module it is recommended to e select synchronous RTC clocking mode i e clear bit SYSCONO0 14 RTCCM 0 1 see CPU_X D1 2 see SCU_X 011 Errata Sheet 40 49 V1 1 2007 06 21 oo Infineon Errata Sheet XC167Cl 32F E ES BB BB Application Hints e reset the RTC module i e set bit RTCRST SYSCONO 15 1 This may be achieved with one word or bit field instruction e g EXTR 1 BFLDH SYSCONO 0COh 80h RTCRST 1 RTCCM 0 wait _accpos EXTR 1 JNB ACCPOS wait_accpos wait until bit ACCPOS 1 As a general recommendation bit REFCLK should be set to the desired value after any start up hardware software watchdog reset and in particular whenever the RTC module is reset by setting bit RTCRST SYSCONO 15 1 When the RTC module is not used and shall be disabled after a power on hardware reset the following steps are recommended 1 reset the RTC by setting bit RTCRST SYSCONO 15 1 2 clear the RTC run bit by setting bit RUN RTC_CON 0 0 3 d
33. de after a PEC transfer which is performed after the RETI instruction from the PACER trap routine is executed e g a semaphore bit may be used This bit may be set to 1 before the IDLE instruction is executed All trap except PACER and interrupt service routines invoked after wake up from idle sleep should clear this bit to 0 After having returned from the PACER trap routine to the program in the internal flash this bit should be tested allow a sufficient time of e g 12 cycles for interrupt arbitration and if it is still at 1 i e no interrupts traps have occurred repeat the IDLE instruction for re entry into idle sleep mode Workaround 4 Use an auxiliary sequence in internal PRAM that bridges the time until the flash is ready after wake up from sleep idle mode e g e Disable interrupts and execute the IDLE instruction to enter sleep mode from the internal PRAM After wake up the instruction following IDLE will be executed if no hardware trap or NMI has occurred e Wait until the internal flash is ready after wake up check register FSR before reading from the internal flash If the sequence in internal PRAM that includes the IDLE instruction is not CALLed from internal flash i e it is not terminated with a RETx instruction at least 8 instructions that do not read from the internal flash should be inserted after the IDLE instruction to avoid speculative prefetches e Enable the interrupt system again The following
34. de is executed from the internal flash after wake up at least 16 instructions should be executed from the internal flash before re entering sleep idle mode This ensures that the flash module is actually accessed after wake up since more instructions are required than can be stored in the prefetch queue e If code is executed from external memory or PRAM wait until the flash BUSY bit returns to 0 before re entering sleep idle mode e If PEC transfers with automatic return to sleep idle mode shall be triggered by the wake up event use e g the following procedure Use an auxiliary routine in internal flash with the required minimum active time after wake up from sleep or idle mode e g define a semaphore bit that is set to 1 before the IDLE instruction is executed All trap and interrupt service routines invoked after wake up from idle sleep should clear this bit to 0 disable interrupts execute the IDLE instruction if idle or sleep mode is terminated by an interrupt request the instructions following the IDLE instruction will be executed the interrupt request flags remain set if idle or sleep mode was terminated by an NMI the trap handler will be invoked enable interrupts to allow prioritization of requests for interrupt or PEC service the instructions following the IDLE instruction should test the flash BUSY bit in register FSR when the flash is ready BUSY 0 and at least 12 instructions have been
35. e internal system frequency at that time might not yet be the intended target frequency since the clock system requires some time to return to its previous state To avoid operation on a frequency that is different from the target frequency either do not enter sleep mode execute the IDLE instruction while interrupt requests can still occur or wait at the beginning of the interrupt service routine until the contents of register PLLCON has returned to the intended target configuration or if the interrupt service is not time critical disable interrupts IEN PSW 11 0 or select CPU priority level ILVL PSW 15 12 OF before executing the IDLE instruction The interrupt service will then be performed after the wake up from sleep mode has occurred and the interrupt system has been re enabled see also SLEEP_X H3 2 SCU_X H7 VCO Configuration with Input Clock disconnected The clock configuration where the input clock is disconnected from XTAL1 PLLCON PLLCTRL 10 was primarily implemented for test purposes Nevertheless it may be used in an application if certain limitations are observed Because the clock frequency is derived from the VCO running in unlocked mode on its base frequency it will vary to some extent with technology temperature and supply voltage When switching from a configuration where the VCO was running on a high frequency gt 100 MHz in locked mode i e from PLLCON PLLCTRL 11 or 013 to the clock configu
36. eet 8 49 V1 1 2007 06 21 eo Errata Sheet Infineon XC167CI 32F E ES BB BB Functional Problems e g stack models to perform branches within or between code segments Two methods basically exist for manipulations of the return address e M1 the return address contained in the last stack frame is directly modified SP 4 CSP gt CSP CSP value originally pushed is modified to CSP SP 2 IP gt IP IP value originally pushed is modified to IP m SP lt Top of System Stack gt e M2 an additional frame with a new return branch target address is pushed onto the system stack The original return address is still available on the system stack SP 4 CSP CSP value originally pushed on system stack by last CALLS SP 2 IP IP value originally pushed on system stack by last CALL S SP CSP CSP value additionally pushed on system stack SP 2 IP IP value additionally pushed on system stack SP lt Top of System Stack gt In order to optimize the execution speed of return instructions the C166S V2 core additionally stores mirrors the 24 bit return address information CSP IP r 1 6 of the last up to 6 subroutine calls invoked by CALLA R I S PCALL in a last in first out Return Stack see User s Manual IFU Block Diagram Whenever one of the return instructions RET RETS RETP is executed the information from the top of the Return Stack is used to already start fetching the return targe
37. ermined by the settings in register PLLCON In case the PLL was locked before entry into sleep mode emergency mode is entered This results in PLLODIV OF and bit SYSSTAT EM 1 This change of configuration will not be notified by the PLL Unlock OWD interrupt flag PLLIR This condition will remain until an external HW reset is applied or a wake up event from sleep mode with main oscillator off i e RTC not running on main oscillator occurs As an alternative switch to bypass mode with VCO on and PLL unlocked before entering sleep mode e g PLLCON 2000 After wake up PLLCON may be reconfigured to the desired PLL operating mode Errata Sheet 32 49 V1 1 2007 06 21 eo Errata Sheet Infineon XC167CI 32F E ES BB BB Application Hints IDLE_X H1 Entering Idle Mode after Flash Program Erase After a program erase operation idle mode should not be entered before the BUSY bit in register FSR has returned to 0 status not busy ADC_X H1 Polling of Bit ADBSY After an A D conversion is started standard conversion by setting bit ADST 1 injected conversion by setting ADCRQ 1 flag ADBSY is set 5 clock cycles later When polling for the end of a conversion it is therefore recommended to check e g the interrupt request flags ADC_CIC_IR for standard conversions or ADC_EIC_IR for injected conversions instead of ADBSY BREAK_X H1 Break on MUL DIV followed by zero cycle jump When a MUL or DIV instruction is im
38. errupt using a global register bank that has a higher priority than an interrupt using a local register bank Example 1 Local bank interrupts are used on levels 14 and 15 no local bank interrupts on level 12 and 13 In this case global bank interrupts on level 15 must not be used Example 2 Local bank interrupts are used on level 12 In this case no global bank interrupts must be used on levels 13 14 15 PORTS_X 012 1 Interference of Input Signals on P9 2 and P9 4 with internal Flash As specified in table DC Characteristics of the Data Sheet input signals may exceed the positive or negative supply voltages Vgsp or Vopp by up to 0 5V while during Overload Conditions Vin gt Vpppt 0 5V or Vin lt Vggp 0 5V the injected overload current must be limited to 5mA per pin 50 mA per device see section Operating Conditions Errata Sheet 16 49 V1 1 2007 06 21 oo Infineon Errata Sheet XC167Cl 32F E ES BB BB Functional Problems However two pins P9 2 CC18IO CAN1_RxD and P9 4 CC2010 have been identified that under exceptional conditions e g massive low frequency noise may cause side effects on internal flash read or erase operations before these overload limits are reached or exceeded depending on the amplitude and width of the respective input signal No problem will occur e when the input levels on pin P9 2 CC18I0 CAN1_RxD do not exceed the positive or negative supply voltages Vssp or Vppp as listed in the
39. executed while the global register bank is selected bit field BANK 00 in register PSW e The interrupting routine is using one of the local register banks BANK 10 or 113 and the local register bank is selected automatically via the bank selection registers BNKSELO 3 i e the interrupting routine has a priority level gt 12 e The system stack is located in the internal dual ported RAM DPRAM locations OF600 OFDFF e The interrupt is acknowledged during the first 8 clock cycles of the IDLE instruction execution Workaround 1 Disable interrupts either globally or only interrupts using a local register bank before execution of IDLE BCLR IEN Disable interrupts globally IDLE Enter idle or sleep mode BSET IEN After wake up re enable interrupts If an interrupt request is generated during this sequence idle sleep mode is terminated and the interrupt is acknowledged after BSET IEN Workaround 2 Do not use local register banks use only global register banks Errata Sheet 13 49 V1 1 2007 06 21 eo Errata Sheet Infineon XC167CI 32F E ES BB BB Functional Problems Workaround 3 Locate the system stack in a memory other than the DPRAM e g in DSRAM INT _X 008 HW Trap during Context Switch in Routine using a Local Bank When a hardware trap occurs under specific conditions in a routine using a local register bank the CPU may stall preventing further code execution Recovery from thi
40. ider the increased power consumption due to the potential frequency increase during these phases of operation Exception in bypass mode with VCO off in case 1 if the RTC is not running on the main oscillator and case in 2 the device stops until it again receives a clock from the oscillator RSTOUT_X H1 RSTOUT driven by weak driver during HW Reset A weak driver see specification in Data Sheet has been implemented on pin RSTOUT which is driven low while RSTIN is asserted low After the end of the internal reset sequence RSTOUT operates in default mode strong driver sharp edge mode i e POCON20 PDM3N 15 12 0000 The software setting POCON20 PDM3N 15 12 xx11 is not supported and should not be selected by software otherwise pin RSTOUT floats Errata Sheet 35 49 V1 1 2007 06 21 eo Errata Sheet Infineon XC167CI 32F E ES BB BB Application Hints SCU_X H1 Shutdown handshake by software reset SRST instruction In the pre reset phase of the software reset instruction the SCU requests a shutdown from the active modules equipped with shutdown handshake see section Peripheral Shutdown Handshake 6 3 3 in chapter Central System Control Functions in the User s Manual The pre reset phase is complete as soon as all modules acknowledge the shutdown state As a consequence e g the A D converter will only acknowledge the request after the current conversion is finished fixed channel single conversion mode or afte
41. ification see notes 1 and below Errata Sheet 17 49 V1 1 2007 06 21 Cinfineon Errata Sheet XC167Cl 32F E ES BB BB Functional Problems Table 6 DC Characteristics P9 2 and P9 4 Operating Conditions apply Parameter Symbol Limit Values Unit Notes Min Max Input low voltage on Vie SR 0 2 not V P9 2 Vis instead of affected 0 5 Input low voltage on Vie SR 0 5 not V for pulses with P9 2 Vis affected Tiow lt 100 ns and DC lt 0 33 Input high voltage on Vi SR not Vopp 0 2 V P9 2 Vins affected Input high voltage on Vin SR not Vopp 0 5 V for pulses with P9 2 Vins affected Thigh lt 100 ns and DC lt 0 33 Input low voltage on Vie SR 0 3 not V P9 4 Vis instead of affected 0 5 Input low voltage on Vi SR 0 5 not V for pulses with P9 4 Vis affected Tiow lt 1 HS and DC lt 0 33 1 For low pulses DC Tow Thignt Tiow Must be lt 0 33 This means e g low pulses lt 100 ns are tolerated if the following high phase is gt 200 ns 2 For high pulses DC Thigh Thight Tiow Must be lt 0 33 This means e g high pulses lt 100 ns are tolerated if the following low phase is gt 200 ns Using these pins as outputs is considered uncritical because the output signal is tightly coupled to the internal supply voltages Vssp Or Vppp If unused these pins should be switched to output by software If possible these pins should be left flo
42. isable the RTC module by setting bit RTCDIS SYSCON3 14 1 FOCON _X H1 Read access to register FOCON Bit FOTL and bit field FOCNT in register FOCON are marked as rh in the User s Manual i e they can not be modified by software If register FOCON is read directly after it was written the value read back from the positions of FOTL and FOCNT represents the value that was written by the preceding instruction but not the actual contents of FOTL and FOCNT In order to obtain correct values for FOTL and FOCNT either insert one NOP or other instruction that does not write to FOCON or read FOCON twice and discard the first result OSC_X H001 Signal Amplitude on Pin XTAL1 When XTAL1 is driven by a crystal or a ceramic resonator reaching an amplitude peak to peak of 0 4 x Vpn is sufficient When XTAL1 is driven by an external clock signal the levels V max 0 3 x Vpp and Vinc min 0 7 x V5p must be respected see Data Sheet section DC Parameters Errata Sheet 41 49 V1 1 2007 06 21 eo Errata Sheet Infineon XC167CI 32F E ES BB BB Application Hints TwinCAN_AI H2 Reading Bitfield INTID It is not recommended to use the information stored in bitfield INTID in register AIR BIR as it is updated with low priority within the CAN controller Instead similar information can be obtained from registers RXIPND and TXIPND INT_X H1 Software Modifications of Interrupt Enable xx_IE or Interrupt Request xx_IR Flags In mi
43. ister security mechanism identically Unprotected Mode remains effective until execution of the EINIT instruction After execution of the EINIT instruction Write Protected Mode becomes active bitfield SL 11 in register SCUSLS Only after execution of EINIT the security level can be changed to Secured Mode or Write Protected Mode by software FLASH _X D1 Interaction between Program Flash and Security Sector Programming The on chip Flash module of the XC 16x uses specific internal status information for the Program Flash area and for the Security Sector This internal status information is updated with an erase operation or a programming operation write page command After reset always the status information for the program flash is selected As documented in the User s Manual an area in the program flash or security sector must be erased before it is reprogrammed Errata Sheet 47 49 V1 1 2007 06 21 oo Infineon Errata Sheet XC167CIl 32F E ES BB BB Documentation Update Caution Writing to a flash page space for the 128 byte buffer more than once before erasing may destroy data stored in neighbor cells This is especially important for programming algorithms that do not write to sequential locations For the interaction of erase programming operations to the program or security areas the following additional rule must be considered To ensure correct programming make sure that a programming operation to either area
44. mediately followed by a falsely predicted conditional zero cycle jump JMPR or JMPA on any condition other than cc_UC and e either a break now request is set at the time the MUL DIV instruction is being executed i e a break request on operand address data task ID BRKIN pin etc is generated by one of the instructions may be up to four preceding MUL DIV e ora break before make request break on IP address is derived from the instruction immediately following the jump jump target or linear following address depending whether the jump is taken or not then the internal program counter will be corrupted equal to last value before jump which will lead to a false update of the IP with the next instruction modifying the IP This problem occurs for debugging with OCDS as well as with OCE Note The Tasking and Keil compilers including libraries do not generate this type of critical instruction sequence Workarounds choices For assembler programmers one of the following workarounds may be used 1 disable zero cycle operation for jumps when debugging code set CPUCON1 ZCJ to 0 or Errata Sheet 33 49 V1 1 2007 06 21 eo Errata Sheet Infineon XC167CI 32F E ES BB BB Application Hints 2 include a NOP after any MUL DIV instruction followed by a conditional jump JMPR JMPA or 3 do not set any break before make type breakpoints on the instruction following the jump or break now type breakpoin
45. memory with many wait states servicing of the trap is delayed by the time for the next access to this program memory even if vector table and trap handler are located in a faster memory However the situation when the pipeline prefetcher are completely empty is quite rare due to the advanced prefetch mechanism of the C166S V2 core Errata Sheet 44 49 V1 1 2007 06 21 oo Infineon Errata Sheet XC167Cl 32F E ES BB BB Application Hints 3 When the CPU is in a power saving state while the NMI trap request occurs the next instruction lt n 1 gt that would normally follow the IDLE instruction has to be fetched first and processed up to the Memory stage where it is cancelled If the internal flash was off during the power saving state and the IDLE instruction was executed from flash and or the vector table and trap handler are located in internal flash the ramp up time for the flash must be considered in addition To achieve the fastest possible response to hardware traps the instruction to enter the power saving state as well as the vector table and trap handler should be located in the internal PSRAM Errata Sheet 45 49 V1 1 2007 06 21 oo Infineon Errata Sheet XC167CIl 32F E ES BB BB Documentation Update 6 Documentation Update INT_X D1 Interrupt Vector Location of CAPCOM Register 28 The vector location for requests from CAPCOM Register 28 is xx 00FO not xx 00E0 as documented in User s Manual PORTS
46. n above When a RET or RETP instruction is executed after a modification of the system stack an intra segment branch is performed If the contents of the CSP register has not changed since the last CALL instruction e g no JMPS CALLS or interrupt has occurred then CSP CSPyo which is the same situation as already discussed in Case 1 before In case the last function was e g called with a CALLS instruction inter segment call the current contents CSP of the Code Segment Pointer CSP is different from the CSP value that has been originally pushed on the stack by the CALLS instruction e g Location Instruction C1 9876 CALLS CO 3456h inter segment call return addr CSP Cl IP 987A pushed on system stack by HW 3456 MOV Rx 5678h prepare intra segment branch CO 345A PUSH Rx push return addr IPm 5678 on system stack by SW CO 345C RET branch return to target Se addr IPm 5678 with CSPc CO C0 5678 lt target_instr gt continue at branch target C0 987A lt valid instr gt code or data located here must result in a valid instruction In the above example if the instruction fragment or data located at address CSP amp e IP m here CO 987A when decoded as instruction does not result in a valid instruction a PACER trap will be generated after the RET instruction is executed Workaround 1 Do not perform modifications of the return address on the system stack
47. n is RETS 2 address CSP6 lP top when the next return instruction is RET or RETP Errata Sheet 9 49 V1 1 2007 06 21 oo Infineon Errata Sheet XC167Cl 32F E ES BB BB Functional Problems where CSPiop CSP value on top of Return Stack CSP value originally pushed on system stack by last call instruction if no other return instruction has been executed else CSP value originally pushed on system stack by last nth call instruction if n other return instructions have been executed and no other call instruction has been executed Phop IP value on top of Return Stack IP value originally pushed on system stack by last call instruction if no other return instruction has been executed else IP value originally pushed on system stack by last nth call instruction if n other return instructions have been executed and no other call instruction has been executed e CSP current contents of CSP e valid instruction code or data decoded as instruction that does not access memory areas that will generate a PACER trap e g reserved memory areas disabled flash etc e Return Stack empty e g number of executed return instructions gt number of call instructions or 6 consecutive return instructions are executed Otherwise when no valid instruction is located at the address described above a PACER trap could be generated due to a speculative access instead of branching to the modified return address from the sys
48. ncy mode after clock failure entry into power saving modes is delayed If e g the IDLE instruction to enter sleep mode is executed in this state the peripherals are already stopped and the CPU goes into hold state but the internal clock system will not be switched off until the reconfiguration is complete Unless it is guaranteed that the clock system will become stable after a reconfiguration it is recommended to wait until the clock system is stable i e check for PLLODIV lt OF use a timeout limit in case a permanent clock failure is present before executing the IDLE or PWRDN instruction to enter the respective power saving mode SCU_X H6 Interrupt request during entry into sleep mode After the IDLE instruction has been executed in order to enter sleep mode SLEEPCON SYSCON1 1 0 01 clock system emergency mode with fycopase 16 will become active during the shut down phase before the clock is finally switched off under the following conditions e the clock system is not running in bypass mode PLLCTRL PLLCON 14 13 00 and e the RTC is not running on the clock derived from XTAL1 during sleep mode Errata Sheet 37 49 V1 1 2007 06 21 oo Infineon Errata Sheet XC167Cl 32F E ES BB BB Application Hints If an interrupt request from an internal or external peripheral module is generated during this time period sleep mode is not entered but instead the associated interrupt service routine is entered Th
49. ode with VCO on PLLCTRL 01 the device will directly continue to run on the frequency derived from the external oscillator input after wake up from sleep if the RTC continues to run on the main oscillator in sleep mode In case the PLL was locked before entry into sleep mode emergency mode is entered This results in PLLODIV OF and bit SYSSTAT EM 1 This change of configuration will not be notified by the PLL Unlock OWD interrupt flag PLLIR This condition will remain until an external HW reset is applied or a wake up event from sleep mode with main oscillator off i e RTC not running on main oscillator occurs If the RTC was not running on the main oscillator i e the main oscillator was off during sleep mode the device will wake up using the internal PLL base frequency from the VCO fbase 16 and will temporarily stay in emergency mode i e run on the frequency derived from the VCO until bit OSCLOCK in register SYSSTAT gets set to 1 It is not possible to switch to direct drive VCO bypass mode within this timeframe If bypass mode PLLCTRL 00g i e no oscillator watchdog support is required by an application after wake up from sleep it is therefore recommended to switch to Errata Sheet 31 49 V1 1 2007 06 21 oo Infineon Errata Sheet XC167Cl 32F E ES BB BB Application Hints bypass mode already before entry into sleep mode check PLLCON for its target value before executing the IDLE instruction to enter
50. on uses tasks with different levels and debugging is to take place using the OCDS break level feature e g only tasks up to a maximum level are halted higher level tasks aren t halted and the OCDS level is programmed in between there is no problem if e only classic hardware breakpoints IP address or software breakpoints are used i e no trigger on address data TASKID e no external pin assertions are used to trigger breaks e no direct writes to DBGSR DEBUG_STATE are used to force breaks 2 If break_now request sources are to be used the maximum level of the application PSW ILVL should always be lower than the programmed OCDS break level e g PSW ILVL lt 145 and CMCTR LEVEL 15 This means that all generated break_now requests by the OCDS will always be accepted independent of the CPU or interrupt priority OCE X 001 Wrong MAC Flags are declared valid at Core OCE interface In case a MAC instruction Co is directly followed by a MOV MSW data16 instruction the upper byte of data16 is output instead of the flags corresponding to the MAC instruction The bug was found with code COSHR 00001h MOV MSW 00100h other variations of datal6 Errata Sheet 25 49 V1 1 2007 06 21 oo Infineon Errata Sheet XC167Cl 32F E ES BB BB OCDS and OCE Modules Workaround Add a NOP instruction between the two instructions COSHR 00001h NOP MOV MSW 00100h other variations of datal6 Errata Sheet 26 49
51. r conversion of channel 0 auto scan single conversion mode If the Wait for Read Mode mode is selected bit ADWR 1 the ADC does not acknowledge the request if the conversion result from register ADC_DAT has not been read Therefore before the SRST instruction is executed it is recommended e g in the continuous fixed or auto scan conversion modes to switch to fixed channel single conversion mode ADM 00 and perform one last conversion in order to stop the ADC in a defined way In the auto scan conversion modes this switch is performed after conversion of channel 0 If a 0 to 1 transition is forced in the start bit ADST by software a new conversion is immediately started If the Wait for Read Mode is selected register ADC_DAT must be read after the last conversion is finished The external bus controller e g may not acknowledge a shutdown request if bus arbitration is enabled and the HOLD input is asserted low SCU_X H3 Effect of PLLODIV on Duty Cycle of CLKOUT When using even values 0 14 for the output divider PLLODIV in register PLLCON the duty cycle for signal CLKOUT may be below its nominal value of 50 This should only be a problem for applications that use both the rising and the falling edge of signal CLKOUT When using odd values 1 15 for PLLODIV where PLLODIV 15 OF is selected by hardware only during clock system emergency mode or reconfiguration the duty cycle for signal CLKOUT is on its nominal val
52. r code svs _jmpi_addr JMPI cc_NV R6 taken but predicted not taken Effect on tools In the Altium Tasking compiler V7 0 and above the problem is not present The result of a MUL DIV instruction is available through the MDL MDH SFRs These SFRs are not allocatable by the register allocator Therefore the compiler always needs a MOV instruction to transfer MDL H to a GPR This avoids the problem Errata Sheet 7 49 V1 1 2007 06 21 eo Errata Sheet Infineon XC167CI 32F E ES BB BB Functional Problems In the RT and FP libraries v7 0 and above the problem was not found Versions lower than v7 0 do not explicitly support the C166S V2 core In case optimizations are implemented in future versions which could cause this problem to occur also a workaround will be included All Keil C166 tool Versions compiler and libraries since V3 xx do not generate a MUL U or a DIV L U LU followed by either of the jump instructions JMPR JMPS JMPA JMPI Basically the support of the C166S V2 core requires anyway V4 21 or higher Workarounds Examples for program parts written in assembly language e generally disable overrun of pipeline bubbles by clearing bit CPUCON2 0VRUN CPUCON2 4 0 This will result only in a negligible performance decrease and will prohibit corruption of the target IP of the JMPI or e provide a NOP or any other suitable instruction between the MUL DIV instructions and the succeeding jump in the abo
53. ration with input clock disconnected from XTAL1 i e to PLLCON PLLCTRL 10 and a relatively small value is selected for the output divider PLLCON PLLODIV e g PLLODIV 0 this may temporarily lead to a master clock overdrive fmc gt 40 MHz or 20 MHz respectively In this case it is recommended to use an intermediate PLLCON setting e g PLLCON 2000 i e bypass mode with VCO running in unlocked mode on lowest VCO band and then wait 200 us until the VCO is definitely running on its base frequency before finally switching to the desired target configuration with input clock disconnected from XTAL1 PLLCON PLLCTRL 10 and setting PLLVB and PLLODIV to the desired target values Errata Sheet 38 49 V1 1 2007 06 21 oo Infineon Errata Sheet XC167Cl 32F E ES BB BB Application Hints SCU_X H8 PLL Bypass Mode with VCO on In bypass mode with VCO running as oscillator watchdog OWD PLLCON PLLCTRL 01 it is recommended to configure f to a value that does not allow the PLL to lock with fyco PLLCON PLLMUL 1 This can be achieved by using an appropriate VCO band in combination with PLLCON PLLMUL 0 e g PLLCON 2080 such that fin fogc PLLCON PLLIDIV 1 is lower than fyco pase See table below Otherwise when fj is at the transition between a lock and an unlock operation of the PLL the internal master clock fy may not reach the intended target frequency but is set to fogc PLLCTRL PLLIDIV 1 16 i e PLLODIV is set
54. refore after reading writing RTBO 3 either e add 5 NOPS or e read status register IIC_ST twice before evaluating the status of flag IRQD Errata Sheet 34 49 V1 1 2007 06 21 oo Infineon Errata Sheet XC167Cl 32F E ES BB BB Application Hints POWER_X H1 1 Initialization of SYSCON3 for Power Saving Modes For minimum power consumption during power saving modes all modules which are not required should be disabled in register SYSCONS i e the corresponding disable bits should be set to 1 including bits which are marked as reserved this provides compatibility with future devices since all SYSCONS3 bits are disable bits Reading these bits will return the written value as for peripherals without shut down handshake For peripherals equipped with peripheral shut down handshake reading allows to check their shut down status POWER_X H2 2 Power Consumption during Clock System Configuration In the following situations 1 after wake up from sleep mode until oscillator lock in case the main oscillator was turned off during sleep mode 2 after a clock failure PLL unlock or oscillator fail until clock reconfiguration by software the device is internally clocked by the VCO running on the base frequency of the currently selected VCO band divided by 16 This results in an operating frequency range of 1 25 11 25 MHz depending on the currently selected VCO band Systems designed for lower target frequencies should cons
55. s condition can only be made through a hardware or watchdog reset All of the following conditions must be present for this problem to occur e The routine that is interrupted by the hardware trap is using one of the local register banks bit field PSW BANK 10 or 11 e The system stack is located in the internal dual ported RAM DPRAM locations OF600 OFDFF e The hardware trap occurs in the second half load phase of a context switch operation triggered by one of the following actions a Execution of the IDLE instruction or b Execution of an instruction writing to the Context Pointer register CP untypical case because this would mean that the routine using one of the local banks modifies the CP contents of a global bank Workaround 1 Locate the system stack in a memory other than the DPRAM e g in DSRAM Workaround 2 Do not use local register banks use only global register banks Workaround 3 Condition b writing to CP while a local register bank context is selected is not typical for most applications If the application implementation already eliminates the possibility for condition b then only a workaround for condition a is required The workaround for condition a is to make sure that the IDLE instruction is executed within a code sequence that uses a global register bank context Errata Sheet 14 49 V1 1 2007 06 21 eo Errata Sheet Infineon XC167CI 32F E ES BB BB Functional Problems INT_
56. sleep mode See also SCU_X H5 e In PLL mode with input clock from XTAL1 disconnected PLLCTRL 10 the device will only wake up from sleep if the RTC was not running on the main oscillator i e when the main oscillator is off during sleep mode In this case the device will run using the internal PLL base frequency from the VCO f 16 until the amplitude on the external oscillator input XTAL1 exceeds the input hysteresis and then switch to fbase K with the output divider selected by PLLODIV If the RTC is running on the main oscillator the device will not wake up from sleep mode with this PLLCTRL setting It is therefore recommended to switch to bypass mode PLLCTRL 00 before entry into sleep mode check PLLCON for its target value before executing the IDLE instruction to enter sleep mode e In PLL mode with input clock from XTAL1 connected to the VCO PLLCTRL 11 if the RTC was not running on the main oscillator the device will wake up in emergency mode and run using the internal PLL base frequency from the VCO fbase 16 until the amplitude on the external oscillator input XTAL1 exceeds the input hysteresis Then the PLL resynchronizes to the target frequency determined by the settings in register PLLCON When bit OSCLOCK gets set in register SYSSTAT the output divider PLLODIV will be set to the target value If the RTC is running on the main oscillator the device will wake up and resynchronize to the target frequency det
57. ster i e a register which is different from the group CPUCON1 ADDRSELx Workaround In order to lock all registers again after a write access to the non SCU registers CPUCON1 ADDRSELx a dummy write access to an SCU register should be executed It is therefore proposed to use e g the read only register IDCHIP for this purpose The registers of the identification control block also belong to the SCU anda write access to these read only registers re enables secured mode Example MOV R4 2000H value to be stored in register EBCMODO EXTR 1 Access sequence in secured mode MOV SCUSLC 8E12H Command4 current password EDH OR EBCMODO R4 Access to EBCMOD enabled by preceding Command4 MOV IDCHIP ZEROS dummy write to a read only SCU register re enables secured mode Table 7 Registers Protected by the Security Mechanism Register Name Function Loc RSTCON Reset control SCU SYSCONO General system control SCU SYSCON 1 Power management SCU Errata Sheet 19 49 V1 1 2007 06 21 oo Infineon Errata Sheet XC167Cl 32F E ES BB BB Functional Problems Table 7 Registers Protected by the Security Mechanism cont d Register Name Function Loc PLLCON Clock generation control SCU SYSCON3 Peripheral management SCU FOCON Peripheral management CLKOUT FOUT SCU IMBCTR Control of internal instruction memory block SCU OPSEN Emulation control SCU EMU
58. t instruction When the actual return address from the system stack is available it is compared with the information from the Return Stack In case of a mismatch the instruction that was speculatively read with the address information obtained from the Return Stack is cancelled and a new fetch with the address from the system stack is started The Return Stack including the potential performance increase is not used in combination with interrupts traps and the corresponding RETI instruction The Return Stack can only provide a performance increase when identical return addresses are delivered by the Return Stack and by the system stack This is only the case when the system stack is not manipulated by software i e e the return address on the system stack is not directly modified by software method M1 e no additional return addresses are pushed on the system stack by software to perform special branches method M2 or RETI is used after pushing PSW to return from a subroutine call Otherwise Return Stack and system stack are no longer aligned and the comparison of the return addresses will also fail for all remaining Return Stack entries r 1 5 Problem Description When the return address on the system stack composed of CSP and or IP is modified by software and the Return Stack is not empty care must be taken that a valid instruction is also located at 1 address CSP iop IP top when the next return instructio
59. tack Then perform the return instruction that branches to the modified return address Workaround 5 If the modifications of the return instructions discussed in Workaround 2 4 can not be performed e g because the code is part of library functions or an operating system the PACER trap service routine should be modified To distinguish the unjustified PACER trap from other defined conditions for a PACER trap e g e first check bit DBER in register FSR for flash double bit errors e else perform a sequence of six CALL instructions followed by 6 return instructions to clear the Return Stack and then return from the PACER trap handler e g BCLR PACER clear PACER trap flag CALLS clear ret stackl clear Return Stack RETI return from PACER trap handler clear ret stacki CALLS clear ret _ stack2 Errata Sheet 12 49 V1 1 2007 06 21 oo Infineon Errata Sheet XC167Cl 32F E ES BB BB Functional Problems RETS Clear ret slacks CALLS clear ret _ stack6 RETS clear ret Stacks RETS INT_X 007 Interrupt using a Local Register Bank during execution of IDLE During the execution of the IDLE instruction if an interrupt which uses a local register bank is acknowledged the CPU may stall preventing further code execution Recovery from this condition can only be made through a hardware or watchdog reset All of the following conditions must be present for the problem to occur e The IDLE instruction is
60. tem stack Examples Case 1 see 1 in Problem Description above Usually a valid instruction will be located at address CSPio IPiop i e at the location after the original CALL instruction An exception is the case where the CALL instruction is the last instruction in a code section that is terminated with RETV virtual return no code generated and a data section directly follows this code section e g CALLS f no ret function modifying system stack does not return to following instruction RETV virtual return no code generated _proc_xy ENDP end of procedure xy _sec_c_xy ENDS end of code section xy _ bec d ab SECTION DATA begin of data section ab _ab array LABEL WORD next location used by locator this address is pushed on system stack by CALLS DW OFFFAh data located here decoded as instruction DW 0000h must result in a valid instruction Errata Sheet 10 49 V1 1 2007 06 21 re Errata Sheet Cinfineon_ XC167Cl 32F E ES BB BB Functional Problems FA FF 00 00 is decoded as JMPS OFFh 0000h gt access to FF 0000 will cause PACER trap when function f no ret executes RETS In the above example a PACER trap will be generated after the RETS instruction corresponding to the CALLS instruction at the end of function no_ ret is executed the speculatively prefetched instruction JMPS OFFh 0000h is trying to access a reserved memory area Case 2 see 2 in Problem Descriptio
61. to the maximum value of OF When a clock failure e g crystal break occurs the PLL may not switch to emergency mode and the device stops Table 8 Relation between maximum f and VCO Band Selection PLLCON PLLVB VCO base frequency fyco pase Maximum f 0 20 MHz lt 20 MHz 1 40 MHz lt 40 MHz 2 60 MHz lt 60 MHz SCU_X H10 Register Security Mechanism usage with CPUCON1 and CPUCON2 registers When using the register security mechanism in conjunction with protected registers CPUCON1 or CPUCON2 CPU pipeline effects must be taken into account When using Secured Mode bitfield SL 01 in register SCUSLS command 4 of the unlock sequence will update the SCUSLS register in the write back stage of the pipeline But the registers CPUCON1 and CPUCON2 belong to the class of registers known as CPU core SFRs CSFRs and updates to these registers occur one cycle earlier in the execute stage see Users Manual chapter 4 3 Instruction Processing Pipeline Attempting to write one of the CPUCONx registers immediately after command 4 of the unlock sequence will cause the write operation to the CPUCON x register to occur before the unlock sequence is in effect Therefore the CPUCONx register will not be updated as expected see also CPU_X D1 To avoid this effect it is generally recommended to initialize the CPUCON1 and CPUCONZ2 registers during software initialization before the EINIT instruction is executed Until EINI
62. ts shortly before or on the MUL DIV instructions OCDS_X H001 Effect of Bit OCDSIOEN in Register EMUCON XC16x devices in a 144 pin package have dedicated pins BRKIN and BRKOUT pin 144 and 143 Therefore it is not required to set bit OCDSIOEN 1 in register EMUCON to select the BRKIN BRKOUT functionality on these pins On the contrary it is recommended to leave bit OCDSIOEN 0 default after reset Otherwise the I O or alternate input functionality on P3 5 and P3 7 is affected P3 5 switched to output high P3 7 switched to input liC_X H1 1 Maximum IIC Bus Data Rate at low fopy The IIC bus module requires a minimum of 32 CPU clock cycles per bit Therefore the prescaler value BRP for the baudrate generator circuitry must fulfil the following criteria Mode 0 if PREDIV 00 then BRPmin 7 else BRPmin 0 Mode 1 if PREDIV 00 then BRPmax 20 else BRPmax 01 This means that e g the extended IIC bus data rate of 400 kbit s can not be used for clock frequencies fopy lt 12 8 MHz liC_X H2 Timing of Bit IRQD The Data Transfer Event Interrupt Request Flag IRQD in register IIC_ST is set to 1 after the acknowledge bit of the last byte has been received or transmitted If bit IC_CON INT 0 IRQD is automatically cleared to 0 by HW with a delay of 1 module clock cycle upon a complete read or write accesses to the buffers RTBO 3 according to the buffer size defined via bit field Cl in register IIC_CON The
63. uctions incl zero JNB GPT12E T2IE Next this or any other instruction reading T2IC assures T2IC is written by BCLR before being read by JNB Next BSET IEN globally enable interrupts again In case the above sequence is included in some sort of macro it may be desirable to prevent interrupts from inadvertently being globally re enabled e g by the following sequence JNB IEN int dis BCLR IEN BCLR GPT12E T2IE clear Timer 2 interrupt enable or request flag iu any number of other instructions incl zero JNB GPT12E T2IE Next this or any other instruction reading T2IC assures T2IC is written by BCLR before being read by JNB Next BSET IEN globally enable interrupts again JMPR cc_uc skip over Int dis BCLR GPT12E T2IE clear Timer 2 interrupt enable 4 or request flag Sere any number of other instructions incl zero JNB GPT12E T2IE skip over read T2IC not required unless interrupts are globally re enabled within the next few instructions skip over Errata Sheet 43 49 V1 1 2007 06 21 eo Errata Sheet Infineon XC167CI 32F E ES BB BB Application Hints This is also easy to implement as a macro in C define Disable One Interrupt IE bit if IEN IEN 0 IE bit 0 while IE bit IEN 1 else IE bit 0 while IE bit Note Due to optimization of the interrupt response time in conjunction with ATOMIC EXTEND sequences an
64. ue of 50 PLLODIV 0 2 4 6 8 10 12 14 Duty Cycle 45 33 33 40 42 86 44 44 45 45 46 13 46 67 Errata Sheet 36 49 V1 1 2007 06 21 oo Infineon Errata Sheet XC167Cl 32F E ES BB BB Application Hints SCU_X H4 Changing PLLCON in emergency mode While the clock system is in emergency mode e g after wake up from sleep or due to an external clock failure the clock output divider is set to 16 i e PLLODIV OF in register PLLCON Emergency mode is only terminated if the internal oscillator lock counter has received 2048 clock ticks from XTAL1 after wake up from sleep mode when the oscillator was off during sleep If PLLCON is written in emergency mode all settings except bypass modes PLLCTRL OX become effective immediately within a few clock cycles As long as the system clock is still derived from the VCO and if a relatively small value k is written to PLLODIV this results in the system running on an internal frequency of fyco k that may exceed the specified frequency limit for the device In general it is recommended to wait until PLLODIV lt OF before PLLCON is written Use a timeout limit in case a permanent clock failure is present SCU_X H5 Sleep idle Power Down Mode not entered while PLLODIV OF While the clock system is in reconfiguration e g after write to PLLCON or after wake up from sleep when an oscillator lock event occurs or during transition to emerge
65. ut to clear flag xx_IE when the interrupt request from source xx occurs Note In practice the normal case to disable an interrupt channel xx via BCLR xx_IE would be at the beginning of the interrupt service routine when the associated peripheral is finished e g has sent serial data stream Then either no more requests from this source occur for a certain period of time and or several instructions to restore the system state inserted by the compiler are executed 1 see Application Note ap16009 How to make instruction sequences uninterruptable on the Microcontroller internet pages of Infineon Technologies www infineon com c166 family follow link to Application Notes 16 bit Microcontrollers Errata Sheet 42 49 V1 1 2007 06 21 oo Infineon Errata Sheet XC167Cl 32F E ES BB BB Application Hints after BCLR xx_IE at the end of the interrupt service routine before the terminating RETI In this case interrupt requests from source xx are safely disabled The same effect will occur when an interrupt request flag xx_IR is cleared by software Therefore in the following examples both cases clearing xx_IE or xx_IR are discussed together With the following modified sequence no more Timer 2 interrupts can occur after BCLR GPT12E_T2xx has been executed BCLR IEN globally disable interrupts BCLR GPT12E T2IE clear Timer 2 interrupt enable 7 or request flag ae any number of other instr
66. ve cases To simplify place a NOP between any MUL DIV and a JMPR JMPS JMPA JMPI that might follow it Other branches CALLs jump on bit instructions do not need to be taken into account CPU_X 003 Software Modification of Return Address on System Stack in combination with RET RETP RETS instructions Introduction Upon subroutine calls instructions CALLA R I S PCALL or interrupts traps the return address and status information is saved on the system stack including e IP intra segment address of the next not executed instruction e CSP segment number of the next not executed instruction for inter segment CALLS instructions and interrupt traps only e PSW processor status word for next not executed instruction for interrupt traps only When the corresponding return instruction RET RETS RETP RETI is executed program execution normally continues at the return address popped from the system stack with the next instruction i e the instruction linearly following the subroutine call or the instruction following the one after which the interrupt trap occurred In case the return address on the system stack has been modified by software program execution will continue at this address instead of the address that was originally pushed on the system stack when the next return instruction is executed This method might be used e g by operating systems or by compilers in conjunction with specific options Errata Sh

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