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(USBa) in the RX630 Group

1. FIFO buffer status Ready for write accessi there is no data to be transmitted NRDY interrupt I NRDYSTS PIPEnNRDY bit An NRDY interrupt occurs 2 Example of data reception OUT token reception single buffer mode I USB bus OUT Token Packet Data Packet NAK Handshake FIFO buffer status 1 Ready for read access there is no space to receive data NRDY interrupt NRDYSTS PIPEnNRDY bit CRCE bit etc An NRDY interrupt occurs 3 Example of data reception PING token reception single buffer mode I USB bus PING Packet NAK Handshake FIFO buffer status 1 I I Ready for read access there is no space to receive data I 1 NRDY interrupt NRDYSTS PIPEnNRDY bit A An NRDY interrupt occurs _ Packet transmitted by the host device __ Packet transmitted by the function device Note 1 The handshake is not used in isochronous transfers Note 2 The PIPEnNRDY bit is set to 1 only while the PIPEnCTR PID 1 0 bits are set to 01b BUF response Note 3 The CRCE and the OVRN bits change only while the target pipe is set to isochronous transfers Figure 31 9 Timing of NRDY Interrupt Generation stENESAS Page 10 of 14 RENESAS TECHNICAL UPDATE TN RX A115A E Date Dec 12 2014 Page 1021 of 1681 Figure 31 10 is corrected as follows Before correction 1 Example of data transmission 1 USB bus IN Token Packet H Data Packet H ACK Handsha
2. Page 967 of 1681 The description column for DVSTCTRO RHST 2 0 bits in 31 2 3 is corrected as follows Before correction Bit Symbol Bit Name Description b2 to b0 RHST 2 0 USB Bus Reset Status b2 b1 b0 0 0 0 Communication speed not determined 1 0 0 USB bus reset in progress 0 1 0 Full speed connection After correction Bit Symbol Bit Name Description b2 to b0 RHST 2 0 USB Bus Reset Status b2 b1 b0 0 0 0 Communication speed not determined 0 1 0 USB bus reset in progress or full speed connection Page 967 of 1681 The following note for the DVSTCTRO WKUP bit in 31 2 3 is deleted Note 1 Only 1 can be written stENESAS Page 2 of 14 RENESAS TECHNICAL UPDATE TN RX A1 A E ate Dec 12 2014 e Pages 968 969 of 1681 The descriptions for registers CFIFO DOFIFO DIFIFO in 31 2 4 are corrected as follows Before correction Address es USBO CFIFO 000A 0014h USBO DOFIFO 000A 0018h USBO D1FIFO 000A 001Ch b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 bO FIFOPORT 15 0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b15tob0 FIFOPORT 15 0 FIFO Port The valid bits in a FIFO port register depend on the settings of the R W corresponding MBW and BIGEND bits as listed in Table 31 4 and Table 31 5 FIFOPORT 15 0 Bits FIFO Port Accessing the FIFOPORT 15 0 bits allows reading the received data from the FIFO buffer or writing the transmit data to the FIFO buffer
3. Each FIFO port register can be accessed only while the FRDY bit in each port control register CFIFOCTR DOFIFOCTR or D1FIFOCTR is 1 The valid bits in a FIFO port register depend on the settings of the corresponding MBW and BIGEND bits of port select register CFIFOSEL DOFIFOSEL or DIFIFOSEL as listed in Table 31 4 and Table 31 5 Table 31 4 Endian Operation in 16 Bit Access CFIFOSEL BIGEND Bit DOFIFOSEL BIGEND Bit D1FIFOSEL BIGEND Bit Bits 15 to 8 Bits 7 to 0 0 N 1 data N 0 data 1 N 0 data N 1 data Table 31 5 Endian Operation in 8 Bit Access CFIFOSEL BIGEND Bit DOFIFOSEL BIGEND Bit D1FIFOSEL BIGEND Bit Bits 15 to 8 Bits 7 to 0 0 Access prohibited 1 N 0 data 1 Access prohibited 1 N 0 data Note 1 Accessing an access prohibited area is not allowed stENESAS Page 3 of 14 RENESAS TECHNICAL UPDATE TN RX A1 A E ate Dec 12 2014 After correction 1 When the MBW bit is 1 Address es USBO CFIFO 000A 0014h USBO DOFIFO 000A 0018h USBO D1FIFO 000A 001Ch b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 Value after reset 0 Bit Symbol b15tob0 Bit Name FIFO Port Description This port is used for reading receive data from the FIFO buffer and R W writing transmit data to the FIFO buffer 2 When the MBW bit is 0 Address es USBO CFIFO 000A 0014h USBO DOFIFO 000A 0018h USB0 D1FIFO 000A 001Ch Value after reset Bit Symbol b7 tob0 L 7 0 Bit Name FIFO Port Descr
4. BRDYSTS PIPEnBRDY bit A BRDY interrupt occurs because the FIFO buffer becomes ready for read access 2 Example of data packet reception when BFRE 1 single buffer mode USB bus Token Packet lt Last gt Data Packet ACK Handshake I I FIFO buffer status Ready for reception Ready for read access I 1 BRDY interrupt BRDYSTS PIPEnBRDY bit The FIFO buffer becomes ready for read access 2 A BRDY interrupt occurs because 3 Example of packet transmission single buffer mode the transfer has ended al USB bus Token Packet Data Packet ACK Handshake FIFO buffer status Ready for transmission Ready for write access BRDY interrupt BRDYSTS PIPEnBRDY bit x1 4 A BRDY interrupt occurs because the FIFO buffer becomes ready for write access L Packet transmitted by host device LC Packet transmitted by function device Note 1 The ACK handshake is not used in isochronous transfers Note 2 The FIFO buffer becomes ready for read access under the following condition When a packet is received while no data remains unread in the FIFO buffer on the CPU side Note 3 A transfer ends under either of the following conditions 1 When a short packet including a zero length packet is received 2 When the number of packets specified in the transaction counter are received Figure 31 8 Timing of BRDY Interrupt Generation stENESAS Page 8 of 14 RENESAS TECHNICAL UPDATE TN RX A1 A E Date Dec 12 2
5. BUF Te LL wje alje lt USBbus O O oj gt llz lolz 2 2 DONS AON PID bit setting NAK NAK BUF BUF Token Token Token Token Token reception reception reception reception is not waited is not waited is waited is waited Interval counter started Figure 31 13 Relationship between Frames and Expected Token Reception when IITV 0 2tENESAS Page 13 of 14 RENESAS TECHNICAL UPDATE TN RX A115A E Date Dec 12 2014 Page 1040 of 1681 The descriptions for SOF Interpolation Function in 31 3 10 are corrected as follows Before correction 31 3 10 SOF Interpolation Function If data could not be received at intervals of 1 ms because an SOF packet was corrupted or missing the USB module interpolates the SOF The SOF interpolation operation begins when the USBE and SCKE bits in SYSCFG have been set to 1 and an SOF packet is received The interpolation function is initialized under the following conditions e Power on reset e USB bus reset e Suspended state detected The SOF interpolation operates as follows The interpolation function is not activated until an SOF packet is received e After the first SOF packet is received interpolation is carried out by counting 1 ms with an internal clock of 48 MHz e After the second and subsequent SOF packets are received interpolation is carried out at the previous reception interval e Interpolation is not carried out in the suspended state or while a USB bus reset is be
6. endian 0 little endian Data in address N 1 Data in address N 1 big endian Data in address N Data in address N 1 Bytes reversed 2tENESAS Page 4 of 14 RENESAS TECHNICAL UPDATE TN RX A1 A E Date Dec 12 2014 Page 974 of 1681 The note for the BCLR bit in registers CFIFOCTR DOFIFOCTR and DIFIFOCTR in 31 2 6 is corrected as follows Before correction Note 1 Only 0 can be read and 1 can be written After correction Note 1 This bit is read as 0 Page 974 of 1681 The following note for the BVAL bit in registers CFIFOCTR DOFIFOCTR and DIFIFOCTR in 31 2 6 is deleted Note 2 Only 1 can be written Page 981 of 1681 The notes for the value after reset of the INTSTSO register in 31 2 12 are corrected as follows Before correction b15 b14 b13 b12 b11 b10 b9 b amp b7 VBINT RESM SOFR DVST CTRT BEMP NRDY BRDY VBSTS DVSQ 2 0 VALID CTSQ 2 0 0 0 0 0 B Value after reset 0 Note 1 This bit is initialized to 0b by a power on reset and 1b by a USB bus reset Note 2 These bits are initialized to 000b by a power on reset and 001b by a USB bus reset Note 3 This bit is 1 when the USBO_VBUS pin input is high and 0 when the input is low After correction b15 b14 b13 b12 bit b10 b9 b b7 be b5 b4 b3 b2 bi DO VBINT RESM SOFR DVST CTRT BEMP NRDY BRDY VBSTS DVSQ 2 0 VALID CTSQ 2 0 ort 0 0 oo OOM 0 0 0 7 0 0 0 0 2 a j A 0 0 0 0 Value after reset 3 Not
7. the frame number SOFR interrupt timing e Isochronous transfer interval count If an SOF packet is missing when full speed operation is being used the FRMNUM FRNM 10 0 bits are not updated 2ENESAS Page 14 of 14
8. 014 Page 1019 of 1681 Figure 31 9 is corrected as follows Before correction 1 Example of data transmission single buffer mode USB bus IN Token Packet H NAK Handshake Buffer status Ready for write access there is no data to be transmitted NRDY interrupt change in o bit in PIPENRDY 2 Example of data reception OUT token reception single buffer mode 1 USB bus OUT Token Packet Data Packet NAK Handshake Buffer status Ready for read access there is no space to receive data NRDY interrupt change in corresponding bit in PIPENRDY CRC bit etc 3 Example of data reception PING token reception single buffer mode USB bus PING Packet NAK Handshake Buffer status Ready for read access there is no space to receive data NRDY interrupt change in corresponding bit in PIPENRDY J Packet transmitted by host device __ Packet transmitted by peripheral device Note 1 The handshake is not used in isochronous transfers Note 2 The PIPENRDY bit is set to 1 only while the PID bits for the target pipe are set to 1 Note 3 The CRC and OVRN bits change only while the target pipe is set to isochronous transfers Figure 31 9 Timing of NRDY Interrupt Generation stENESAS Page 9 of 14 RENESAS TECHNICAL UPDATE TN RX A1 A E Date Dec 12 2014 After correction 1 Example of data transmission single buffer mode x1 USB bus IN Token Packet NAK Handshake
9. Date Dec 12 2014 RENESAS TECHNICAL UPDATE 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan Renesas Electronics Corporation Product soya cu Document TN RX A115A E Rev Category No Corrections to Manual regarding the USB 2 0 Function Information Title Module USBa in the RX630 Group Category Technical Notification Apolicable Referenc RX630 Group User s Manual cai RX630 Group an Hardware Rev 1 60 R01UH0040EJ0160 This document describes corrections to section 31 USB 2 0 Function Module USBa in RX630 Group User s Manual Hardware Overall The following function name is corrected Before correction SOF interpolation function After correction SOF recovery function Page 963 of 1681 Note 1 is added to Table 31 1 as follows Item Specifications Features USB Device Controller UDC and transceiver for USB 2 0 are incorporated One port is provided Self power mode or bus power mode can be selected Programmable intervals for isochronous and interrupt transfers Full speed transfer 12 Mbps is supported 1 Control transfer stage control function Device state control function Auto response function for SET_ADDRESS request SOF recovery function Note 1 Low speed transfer 1 5 Mbps is not supported 2013 Renesas Electronics Corporation All rights reserved ad ENESAS Page 1 of 14 RENESAS TECHNICAL UPDATE TN RX A1 A E Date Dec 12 2014
10. access 1 1 1 BRDY interrupt nr S S change in corresponding 4 bit in PIPEBRDY i A The buffer becomes A BRDY interrupt is generated ready for read access because the transfer has ended 3 Example of packet transmission single buffer mode 4 USB bus Token Packet Data Packet ACK Handshake FIFO buffer status Ready for transmission Ready for write access BRDY interrupt L a SK change in corresponding bit in PIPEBRDY A BRDY interrupt is generated because the buffer becomes ready for write access C Packet transmitted by host device C Packet transmitted by peripheral device Note 1 The ACK handshake is not used in isochronous transfers Note 2 The FIFO buffer becomes ready for read access under the following condition When a packet is received while no data remains unread in the buffer in the CPU Note 3 A transfer ends under either of the following conditions 1 When a short packet including a zero length packet is received 2 When the number of packets specified in the transaction counter are received Figure 31 8 Timing of BRDY Interrupt Generation stENESAS Page 7 of 14 RENESAS TECHNICAL UPDATE TN RX A1 A E Date Dec 12 2014 After correction 1 Example of zero length packet reception or data packet reception when BFRE 0 single buffer mode 1 USB bus Token Packet Data Packet ACK Handshake FIFO buffer status Ready for reception Ready for read access BRDY interrupt
11. e 1 The value is 0 after the MCU is reset and the value is 1 after a USB bus reset Note 2 The value is 1 when the USBO_VBUS pin is high and the value is 0 when the USBO_VBUS pin is low Note 3 The value is 000b after the MCU is reset and the value is 001b after a USB bus reset Page 986 of 1681 The note for bits CRCE and OVRN of the FRMNUM register in 31 2 16 is corrected as follows Before correction Note 1 Only 0 can be written After correction Note 1 When setting each status to 0 write 0 to the bit that is cleared and write 1 to the other bit 2ENESAS Page 5 of 14 RENESAS TECHNICAL UPDATE TN RX A1 A E Date Dec 12 2014 Page 986 of 1681 The descriptions for the CRCE bit in 31 2 16 is corrected as follows Before correction On detecting a CRC error the USB module does not generate the internal NRDY interrupt request After correction The USB module generates an internal NRDY interrupt request when a CRC error is detected Page 991 of 1681 The note for bits SQSET and SQCLR of the DCPCTR register in 31 2 24 is corrected as follows Before correction Note 1 This bit is read as 0 Only can be written After correction Note 1 This bit is read as 0 Page 996 of 1681 Descriptions for the PPPEMAXP MXPS 8 0 bits in 31 2 27 are corrected as follows Before correction Specifies the maximum data payload maximum packet size for the selected pipe These bits should be set to the appropriate value for
12. each transfer type based on USB Specifications While MXPS 8 0 0 do not write to the FIFO buffer or set PID to BUF After correction Specifies the maximum data payload maximum packet size for the selected pipe These bits should be set to the appropriate value for each transfer type based on USB Specifications 2 0 Note that the maximum value for PIPE and PIPE2 is 256 While the MXPS 8 0 bits are 000h do not write to the FIFO buffer or do not set the PID 1 0 bits to 01b BUF ePages 998 1002 of 1681 The note for bits SQSET and SQCLR of the PIPEnCTR register in 31 2 29 is corrected as follows Before correction Note 1 Only 0 can be read and 1 can be written After correction Note 1 This bit is read as 0 2tENESAS Page 6 of 14 RENESAS TECHNICAL UPDATE TN RX A1 A E Date Dec 12 2014 Page 1017 of 1681 Figure 31 8 is corrected as follows Before correction 1 Example of zero length packet reception or data packet reception when BFRE 0 single buffer mode 4 USB bus Token Packet Data Packet ACK Handshake FIFO buffer status E Ready for reception Ready for read access BRDY interrupt change in Sa aneng i bit in PIPEBRDY A BRDY interrupt is generated because the buffer becomes ready for read access 2 Example of data packet reception when BFRE 1 single buffer mode USB bus Token Packet lt Last gt Data Packet ACK Handshake I I FIFO buffer status Ready for reception Ready for read
13. erval counter under the following conditions e Power on Reset The PIPEPERI IITV 2 0 bits are initialized Buffer memory initialization using the ACLRM bit The PIPEPERI IITV 2 0 bits are not initialized but the count value is initialized Setting the PIPEnCTR ACLRM bit to 0 starts counting from the value set in the PIPEPERI IITV 2 0 bits After correction 1 Counter Initialization The interval counter is initialized when the MCU is reset or when the PIPEnCTR ACLRM bit is set to 1 The PIPEPERI IUTV 2 0 bits are not initialized when the interval counter is initialized by using the ACLRM bit 2ENESAS Page 12 of 14 RENESAS TECHNICAL UPDATE TN RX A115A E Date Dec 12 2014 Page 1036 of 1681 The descriptions for When IITV 0 in 31 3 9 3 2 and Figure 31 13 are corrected as follows Before correction When ITV 0 The interval counting starts at the frame following the frame in which software has set the PID 1 0 bits for the selected pipe to BUF Te LL ufles uw lt USBbus O O oj gt llz lola 2 2 AOS ANOVAS PID bit setting NAK BUF BUF BUF Token Token Token Token Token reception reception reception reception is not waited is not waited is waited is waited Interval counter started Figure 31 13 Relationship between Frames and Expected Token Reception when IITV 0 After correction e When IITV 0 The interval counter starts when software has set the PID 1 0 bits for the selected pipe to
14. fer Auto Response Function The USB module automatically responds to a correct SET ADDRESS request If any of the following errors occurs in the SET ADDRESS request a response from the software is necessary Any transfer other than a control read transfer bnRequestType 00h Request error wIndex 00h Any transfer other than a no data control transfer wLength 4 00h Request error wValue gt 7Fh Control transfer of a device state error INTSTSO DVSQ 2 0 011b Configured For all requests other than the SET ADDRESS request a response is required from the corresponding software After correction 4 Control Transfer Auto Response Function The USB module automatically responds to a correct SET ADDRESS request If any of the following errors occurs in the SET _ADDRESS request a response from the software is necessary bmRequestType is not 00h Any transfer other than a control write transfer wIndex is not 00h Request error wLength is not 00h Any transfer other than a no data control transfer wValue is larger than 7Fh Request error The INTSTSO DVSQ 2 0 bits are 011b configured state Control transfer of a device state error For all requests other than the SET_ ADDRESS request a response is required from the corresponding software Page 1035 of 1681 The descriptions for 1 Counter Initialization in 31 3 9 3 are corrected as follows Before correction 1 Counter Initialization The USB module initializes the int
15. ing received The USB module supports the following functions based on the SOF packet reception These functions also operate normally with SOF interpolation if the SOF packet was missing Updating of the frame number e SOFR interrupt timing e Isochronous transfer interval count If an SOF packet is missing when full speed operation is being used the FRMNUM FRNM 10 0 bits are not updated After correction 31 3 10 SOF Recovery Function If data could not be received at intervals of 1 ms because an SOF packet was corrupted or missing the USB module recovers the SOF The SOF recovery operation begins when the USBE and SCKE bits in SYSCFG have been set to 1 and an SOF packet is received The recovery function is initialized under the following conditions e MCU reset e USB bus reset e Suspended state detected The SOF recovery operates as follows The recovery function is not activated until an SOF packet is received e After the first SOF packet is received recovery is carried out by counting ms with an internal clock of 48 MHz e After the second and subsequent SOF packets are received recovery is carried out at the previous reception interval e Recovery is not carried out in the suspended state or while a USB bus reset is being received The USB module supports the following functions based on the SOF packet reception These functions also operate normally with SOF recovery if the SOF packet was missing Updating of
16. iption This port is used for reading receive data from the FIFO buffer and R W writing transmit data to the FIFO buffer FIFO Port Bits Accessing the FIFO port bits allows reading the received data from the FIFO buffer or writing the transmit data to the FIFO buffer Each FIFO port register can be accessed only while the FRDY bit in each FIFO port control register CFIFOCTR DOFIFOCTR or D1FIFOCTR is 1 The valid bits in a FIFO port register depend on the settings of the corresponding MBW bit of the FIFO port select register CFIFOSEL DOFIFOSEL or DIFIFOSEL When the MBW bit is 1 16 bit width the data arrangement may differ from the data arrangement on the RAM depending on the value of the MDEB MDE 2 0 bits or the MDES MDE 2 0 bits and the setting of the BIGEND bit CFIFOSEL BIGEND DOFIFOSEL BIGEND or DIFIFOSEL BIGEND Table 31 4 lists the endian operation in 16 bit access Note that if the total number of transmit data bytes is odd access the L 7 0 bits in bytes when writing the last data When the MBW bit is 0 8 bit width access the L 7 0 bits in bytes Table 31 4 Endian Operation in 16 Bit Access CFIFOSEL BIGEND Bit MDEB MDE 2 0 bits DOFIFOSEL BIGEND Bit MDES MDE 2 0 bits 000b big endian D1FIFOSEL BIGEND Bit 0 little endian Bits 15 to 8 Data in address N 1 Bits 7 to 0 Data in address N Remarks Bytes reversed 1 big endian Data in address N Data in address N 1 111b little
17. ke Buffer status Ready for transmission Ready for write access there is no data to be transmitted BEMP interrupt change in corresponding bit in PIPEBEMP 2 Example of data reception USB bus OUT Token Packet Data Packet Maximum STALL Handshake Packet size over BEMP interrupt change in corresponding bit in PIPEBEMP L Packet transmitted by host device C Packet transmitted by peripheral device Note 1 The handshake is not used in isochronous transfers Figure 31 10 Timing of BEMP Interrupt Generation After correction 1 Example of data transmission 1 USB bus IN Token Packet Data Packet ACK Handshake FIFO buffer status Ready for transmission PEAN HE e transmitted BEMP interrupt l BEMPSTS PIPEnBEMP bit 4 A BEMP interrupt occurs 2 Example of data reception Data Packet Maximum USB bus OUT Token Packet packet size over STALL Handshake BEMP interrupt BEMPSTS PIPEnBEMP bit A BEMP interrupt occurs C Packet transmitted by the host device C Packet transmitted by the function device Note 1 The handshake is not used in isochronous transfers Figure 31 10 Timing of BEMP Interrupt Generation stENESAS Page 11 of 14 RENESAS TECHNICAL UPDATE TN RX A115A E Date Dec 12 2014 Page 1032 of 1681 The descriptions for 4 Control Transfer Auto Response Function in 31 3 6 1 are corrected as follows Before correction 4 Control Trans

(USBa) in the RX630 Group

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