Addendum to TC1766 User`s Manual V2.0
Contents
1. Page 23 91 The content rw of column Type in the last row of the table on top of the page for the Reserved bits must be changed to r Documentation Addendum 19 V2 0 2008 04 TC1766 Cinfineon CONFIDENTIAL User s Manual Peripheral Units Part Volume 2 Page 24 7 The ACRx GAIN setting which corresponds to the FAINxP and FAINxN values in Table 24 1 for Differential Measurement Mode Configuration 3 must be replaced as below Table 24 1 Conversion Results in the Different Measurement Modes Measurements ACRx ACR x FAINXP FAINxN ACRx Conversion ENP ENN GAIN Results Single ended 0 1 don t 0 00 768 Measurement care 33 256 Mode Configuration 1 0 01g 1023 3 0 0 Single ended 1 0 0 don t 00 256 Measurement 33 care 768 Mode Configuration 2 0 01g 0 3 3 1023 Differential 1 1 0 1 65 00 256 Measurement 0 33 0 Mode Configuration 3 1 65 0 768 3 3 0 1023 3 3 1 65 768 0 1 65 Oi 0 1 65 0 1023 3 3 1 65 1023 Documentation Addendum 20 V2 0 2008 04 Cinfineon Page 24 37 TC1766 User s Manual Peripheral Units Part Volume 2 The bit field description CRPRIO must be changed as follows CRPRIO 17 16 rwh Conversion Request Priority This bit field determines the priority of the conversion requests if more than one channel is requested2. Cinfineon meee User s Manual System Units Part Volume 1 Page 7 36 The following section must be added to the top of page 7 2 8 3 Application Hints Flash Error Handling The previous sections described shortly the functionality of error indicating bits in the flash status register FSR This section gives recommendations how these should be handled by customer software PFOPER DFOPER Operation Error Fault conditions ECC double bit error detected in Flash microcode SRAM during a program or erase operation in PFlash or DFlash This can be a transient event due to alpha particles or illegal operating conditions or it is a permanent error due to a hardware defect This situation will practically not occur These bits can also be set in case of uncritical errors that don t affect Flash operation This case is much more likely than real operation errors Attention these bits can also be set during startup New state If triggered by Flash operation this is aborted the BUSY flag is cleared and read mode is entered Proposed handling by software The DFOPER and PFOPER flags should be ignored for the possibility of flagging an error which is not related to a Flash write or erase operation By checking the result of an operation e g checking programmed data a real operation error can be easily determined When a real operation error is determined a reset should be applied before trying the operation again Note
3. Even when the flag is ignored it is recommended to clear it Otherwise all following operations including sleep could trigger an interrupt even when they are successful VER Verification Error Fault conditions This flag is a warning indication and not an error It is set when a program or erase operation was completed but with a suboptimal result This bit is already set when only a single bit is left over erased or weakly programmed which would be corrected by the ECC anyhow However excessive VER occurrence can be caused by operating the Flash out of the specified limits e g incorrect voltage or temperature A VER after programming can also be caused by programming a page whose sector was not erased correctly e g aborted erase due to power failure Under correct operating conditions a VER after programming will practically not occur A VER after erasing is not unusual Documentation Addendum 5 V2 0 2008 04 Cinfineon TONGE CONFIDENTIAL User s Manual System Units Part Volume 1 New state No state change Just the bit is set Proposed handling by software This bit can be ignored It should be cleared with Clear Status or Reset to Read In spec operation of the Flash memory must be ensured If the application allows timing and data logistics a more elaborate procedure can be used to get rid of the VER situation e VER after program erase the sector and program the data again
4. must be expected because of known physical effects New state No state change Just the bit is set Proposed handling by software This flag can be used to analyze the state of the Flash memory During normal operation it should be ignored In order to count single bit errors it must be cleared by Clear Status or Reset to Read after each occurrence Documentation Addendum 6 V2 0 2008 04 Cinfineon Teis User s Manual System Units Part Volume 1 Usually it is sufficient after programming data to compare the programmed data with its reference values ignoring the SBE bits When there is a comparison error the sector is erased and programmed again When programming the PFlash end of line programming or SW updates customers can further reduce the probability of future read errors by performing the following check after programming e Change the read margin to high margin 0 e Verify the data and count the number of SBEs When the number of SBEs exceeds a certain limit e g 10 in 2 MByte the affected sectors could be erased and programmed again e Repeat the check for high margin 1 e Each sector should be reprogrammed at most once afterwards SBEs can be ignored In case of EEPROM emulation using DFlash the verification of programmed data should be done with the normal read level and SBEs should be ignored When a comparison error is found the sector can usually not be erased because it contain
5. Clock Cycles Comments Notes PRAM Access MCLR PI MSET PI ST PI XCH PI Complex Maths MSETP U 11 oOo O On Page 10 111 the last row of footnote 7 must be changed to 32 x 32 bit multiply requires instruction MINIT 4 x MSTEP U 1 4 x 11 45 cycles Page 11 35 The first bulleted point must be changed to The activation of the interrupt corresponding to the current active channel On using the Interrupt Pointer defined in CHICROn INTP Documentation Addendum 13 V2 0 2008 04 Cinfineon TC1766 CONFIDENTIAL User s Manual Peripheral Units Part Volume 2 3 User s Manual Peripheral Units Part Volume 2 This section describes the updates for the Peripheral Units of the User s Manual Page 17 37 Table 17 8 should be replaced as below Table 17 8 ASCO ASC1 I O Control Selection and Setup Module Port Lines PISEL Register Input Output Control 1 0 Register Bits ASCO P3 0 RXDOA ASCO_PISEL RIS 0 P3_IOCRO PCO OXXX Input P3 0 RXDOA P3_IOCRO PCO 1X01 or Output 1X10 2 P3 12 RXDOB ASCO_PISEL RIS 1 P3_IOCR12 PC12 0XXXg Input P3 12 RXDOB P3_IOCR12 PC12 1X01 Output or 1X10 d P3 1 TXDOA P3_IOCRO PC1 1X01gor Output 1X10 P3 13 TXDOB P3_IOCR12 PC13 1X10 Output ASC1 P3 9 RXD1A ASC1_PISEL RIS 0 P3_IOCR8 PC9 0XXXg Input P3 9 RXD1A P3_IOCR
6. If the dynamic priority assignment is enabled the priority is automatically changed as a function of the gating inputs The priority of the channels is 00 Channel 0 before channel 1 01 Channel 1 before channel 0 10 Reserved 11 Reserved Page 24 50 24 51 The bit field description of CRRO AC and CRR1 AC must be changed as follows AC 26 24 rh Addition Count With the Automatic End Mode the compensation of input signal s period length variation acceleration deceleration is requested xxThis bit field indicates the number of additions of filter input values with remain to be executed before the next intermediate result register transfer occurs AC is loaded with the value of FCRn ADDL for a new addition sequence also when writing GCR RSTFn 1 Page 24 60 The content rw of column Type in the last row of the table on top of the page for the Reserved bits must be changed to r Documentation Addendum 21 V2 0 2008 04
7. purpose output P3_OUT P2 1X00 SSCO output Master SCLKO 1X01 Mode 1X10 Reserved 1X11 P3 3 General purpose input P3_IN P3 P3_IOCRO PC3 OXXX 5 SSCO input Master Mode MRSTO O General purpose output P3_OUT P3 1X00 SSCO output Slave MRSTO 1X01 Mode 1X10 Reserved 1X11 Documentation Addendum 9 V2 0 2008 04 TC1766 Cinfineon CONFIDENTIAL User s Manual System Units Part Volume 1 Table 9 13 Port 3 Functions cont d Port 1 0 Pin Functionality Associated Port I O Control Select Pin Reg Reg Bit Field Value 1 O Line P3 4 General purpose input P3_IN P4 P3_IOCR4 PC4 OXXXp SSCO input Slave Mode MTSRO O General purpose output P3_OUT P4 1X00 SSCO output Master MTSRO 1X01 Mode 1X10 Reserved 1X11 P3 5 General purpose input P3_IN P5 P3 IOCR4 PC5 OXXXp O General purpose output P3 OUT P5 1X00 SSCO output SLSO00 1X01 SSC1 output SLSO10 1X10 SSCO and SSC1 output SLSO00 AND 1X11 SLSO10 P3 6 General purpose input P3_IN P6 P3 IOCR4 PC11 OXXX O General purpose output P3_OUT P6 X 1X00 SSCO output SLSOO1 1X01 SSC1 output SLSO11 1X10 SSCO and SSC1 output SLSO01 AND 1X11 SLSO11 P3 7 General purpose input P3_IN P7 P3 IOCR4 PC7 OXXXp SSCO input SLSIO O General purpose output P3 OUT P7 1X00 SSCO output SLSO02 1X01 SSC1 output SLSO12 1X10
8. 3 Functions cont d Port I O Pin Functionality Associated Port I O Control Select Pin Reg Reg Bit Field Value 1 0 Line P3 13 General purpose input P3_IN P13 P3_I0CR12 PC13 OXXX O General purpose output P3 OUT P13 1X00 CAN node 0 output TXDCANO 1X01 ASCO output TXDOB 1X10 Reserved 1X11 P3 14 General purpose input P3_IN P14 P3 IOCR12 PC14 OXXX CAN node 1 receive input 0 RXDCAN1 CAN node 0 receive input 1 ASC1 output RXD1B O General purpose output P3_OUT P14 1X00 ASC1 output RXD1B 1X01 Synchronous Mode only 1X105 Reserved 1X11 P3 15 General purpose input P3_IN P15 P3 IOCR12 PC15 OXXX O General purpose output P3_OUT P15 1X00 CAN node 1output RXDCAN1 1X01 ASC1 output TXD1B 1X10 Reserved 1X11 1 The ALT1 and ALT2 for this pin are connected together There are no dependencies Either one can be chosen Y The port I O control values P3_IOCRx Py that are assigned to this reserved alternate output control selection should not be used Otherwise unpredictable output port line behavior may occur 3 The AND gate of ALT3 is located in the GPIO module Documentation Addendum 12 V2 0 2008 04 Cinfineon kuha User s Manual System Units Part Volume 1 Page 10 109 In Table 10 15 the number of clock cycles for the stated instructions must be corrected as below Table 10 15 Instruction Timing Instruction Number of
9. 8 PC9 1X01 0r Output 1X10 2 P3 14 RXD1B ASC1_PISEL RIS 1 P3_IOCR12 PC14 0XXXg Input P3 14 RXD1B P3_IOCR12 PC14 1X01 Output or 1X10 a P3 8 TXD1A P3_IOCR8 PC8 1X10 Output P3 15 TXD1B P3_IOCR12 PC15 1X10 Output 1 For possible PCx bit field combinations see Table 17 9 2 Applicable in Synchronous Mode only Page 18 16 The expression SLSOx must be replaced three times by SLSOn In the numbered paragraph 3 the expression SSSOTC INACT must be changed to SSOTC INACT Documentation Addendum V2 0 2008 04 Cinfineon Tee User s Manual Peripheral Units Part Volume 2 Page 18 24 The description for the Module Revision Number bit field for the ID register must be changed to MODREV defines the module revision number The value of a module revision starts with 10 first revision Page 18 34 The bit field description for bit TB_VALUE must begin with Register TB stores the data value Page 18 42 The content rw of column Type in the last row of the table on top of the page for the Reserved bits must be changed to r Page 19 4 The item Programmable upstream data frame length 16 or 12 bits must be moved from the second bullet as third item under the third bullet Low speed asynchronous serial reception on upstream channel Page 19 13 in the last bullet line on the bottom of th
10. Documentation Addendum V2 0 Apr 2008 1C1766 32 Bit Single Chip Microcontroller Microcontrollers Cnfineon Never stop thinking Edition 2008 04 Published by Infineon Technologies AG 81726 M nchen Germany Infineon Technologies AG 2008 All Rights Reserved Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics Beschaffenheitsgarantie With respect to any examples or hints given herein any typical values stated herein and or any information regarding the application of the device Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind including without limitation warranties of non infringement of intellectual property rights of any third party Information For further information on technology delivery terms and conditions and prices please contact your nearest Infineon Technologies Office www infineon com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Infineon Technologies Office Infineon Technologies Components may only be used in life support devices or systems with the express written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectivenes
11. O Bypass Mode PLL_CLC VCOBYP 1 Selecting the VCO band by programming PLL_CON VCOSEL Program the desired P N and K values PDIV NDIV and KDIV bit fields of register PLL_CLC to get a temporary fcpu value which is lower than the target frequency Connect the oscillator to the PLL PLL_CLC OSCDISC 0 Wait until the PLL becomes locked PLL_CLC LOCK 1 Disable the VCO Bypass Mode PLL_CLC VCOBYP 0 Wait for typically 5ms until supply ripple caused by increased supply current is faded away 9 Decrease K value step by step with wait phases in between until the targeted Jcpu is reached AUN 0 Y O Ol Page 6 12 The first line in the description for bit field LEDAT 31 0 must be corrected into LMB Data Bits 31 0 instead of LMB Bus Address Bits 31 0 The first line in the description for bit field LEDAT 63 32 must be corrected into LMB Data Bits 63 32 instead of LMB Bus Address Bits 31 0 Page 7 34 The note at the end of the page must be erased Note After the detection Page 7 35 The second sentence of the first paragraph must be erased With this features problematic Paragraphs 3 to 6 must be erased Since problematic Flash array bits until of Flash cells is close to the zero state 1 K value selection should result in a small change of fcpy when bypass mode is left to reduce supply ripple Documentation Addendum 4 V2 0 2008 04
12. Reserved 1X11 P3 8 General purpose input P3_IN P8 P3_IOCR8 PC8 OXXXp O General purpose output P3 OUT P8 1X00 SSCO output SLSO06 1X01 ASC1 output TXD1A 1X10 Reserved 1X11 Documentation Addendum 10 V2 0 2008 04 Cinfineon TC1766 User s Manual System Units Part Volume 1 Table 9 13 Port 3 Functions cont d Port 1I O Pin Functionality Associated Port I O Control Select Pin Reg Reg Bit Field Value 1 O Line P3 9 General purpose input P3_IN P9 P3_IOCR8 PC9 OXXXp ASC1 input RXD1A O General purpose output P3_OUT P9 1X00 ASC1 output Synchronous RXD1A 1X01 Mode only 1X10 Reserved 1X11 P3 10 General purpose input P3_IN P10 P3 IOCR8 PC10 OXXX SCU input REQO O General purpose output P3_OUT P10 1X00 Reserved 1X01 1X10 1X11 P3 11 General purpose input P3_IN P11 P3 IOCR8 PC11 OXXX SCU input REQ1 O General purpose output P3_OUT P11 1X00 Reserved 1X018 LUN TN P3 12 General purpose input P3_IN P12 P3_I0CR12 PC12 OXXX CAN node 0 receive input 0 RXDCANO CAN node 1 receive input 1 ASCO input RXDOB O General purpose output P3_OUT P12 1X00 ASCO output Synchronous RXDOB 1X01 Mode only 1X10 Reserved 1X11 Documentation Addendum V2 0 2008 04 Cinfineon TEUGE CONFIDENTIAL User s Manual System Units Part Volume 1 Table 9 13 Port
13. This is only recommended when there are more than 3 program VERs in the same sector When programming the DFlash in field EEPROM emulation ignoring program VER is normally the best solution because its most likely cause are violated operating conditions Take care that never a sector is programmed in which the erase was aborted In the EEPROM emulation the algorithm must ensure this e g by programming a marker after finishing successfully the erase e VER after erase the erase operation can be repeated until VER disappears Repeating the erase more than 3 times consecutively for the same sector is not recommended After that it is better to ignore the VER program the data and check its readability Again for EEPROM emulation its most likely cause are violated operating conditions Therefore it is recommended to repeat the erase at most once or ignore it altogether For optimizing the quality of Flash programming see the following section about handling single bit ECC errors Note Even when this flag is ignored it is recommended to clear it Otherwise all following operations including sleep could trigger an interrupt even when they are successful PFSBER DFSBER Single Bit Error Fault conditions When reading data or fetching code from PFlash or DFlash the ECC evaluation detected a single bit error SBE which was corrected This flag is a warning indication and not an error A certain amount of single bit errors
14. a source is used for the shift register bit SRH x during data frame transmission 00 SRHIx is taken from data register DD DDH x Olg Reserved 10 SRH x is taken from the ALTINH input line x 11 SRHIx is taken from the ALTINH input line x in inverted state Page 19 57 n the bit description of bit CSH SRL must be changed to SRH Documentation Addendum 16 V2 0 2008 04 Cinfineon TURP User s Manual Peripheral Units Part Volume 2 Page 19 65 The below five formulas must be changed as follows MSCO_FDR STEP fusco Ssys x 1 with n 1024 MSCO_FDR STEP 19 3 Baud rateyiscy fsys x ape ea aE 19 5 Baud rateyiscy fsys x Meee Rete 19 6 Baud rateusco fsys x O cou EERSTE 19 7 Baud rateusco fsys x MISCO FDA S TEE 19 8 DF x 1024 Page 19 68 In the bit description for bit SUSACK in the register description table Indicates state of SPNDACK signal must be changed to Indicates state of SPNDACK signal Page 19 69 The content rw of column Type in the last row of the table on top of the page for the Reserved bits must be changed to r Page 20 39 The bulleted points of Allocation Case 1 must be changed to e The upper three bits of MOIPRn MPN MPN 7 5 select the number k of a Message Pending Register MSPNDKk in which the pending bit will be set e The lower five bits of MOIPRn MPN MPN 4 0 select the bit position 0 31 in MSPNDk
15. aes awe 8 Page 9 47 9 Pai IA EA IIIA AA 13 A Aaaa 13 3 User s Manual Peripheral Units Part Volume 2 14 Pave E O 14 Pave ISSO tee gues radar ena ls ona ae oa 14 Pave T824 A route daten setae ESE Pee wee ee eke vad 15 Pave 18 34 A setae Enr Cee wee ed eke vad 15 Pa ge 18 42 acts cues ondaa ena lea rt de E wee ee eke va 15 Page T94 EIA 15 Page 19 13 15 Page 19 18 15 Page 19 19 15 Page 19 25 15 Page 19 26 15 PAIN A KA WA avd Ka 15 Page AOA errar aca dae oad CEN 16 Page lOO caress pireneana dees vate bey Saeed ee ad CE 16 Page A A vale WA oad Cow 17 Pave T9 68 sitive etuusourin dese vale bey Sour ewke dee oad Caw 17 Page 1000 creena esne sae O 17 o ET 17 Page 20 50 awit kee ea oe ee ee Re ee he we 17 Page 20 04 a wr hte a a A ew he EE OE oe eed 18 Page 20 06 AA ae oe ee ee he EE we eed 18 Page 2000 sac tae ds a eae hee ee ew Oe he ee ee ool eed 18 Page 20 113 a A AAA a wed 18 Page 21 29 21 34 18 Page A AAA ee AA AAA AA RON 18 Page 21 80 EEEH WAA 18 Page 21 102 18 Page 21 103 2sevovarade rindas a rik ika noera WEVE eae 19 Documentation Addendum 1 V2 0 2008 04 Cinf
16. e 21 102 Page 21 75 In Figure 21 50 the TCDMR text within the Transmission Status Control Registers block must be corrected to TCMDR Page 21 80 The content rw of column Type in the last row of the table on top of the page for the Reserved bits must be changed into r Page 21 102 The description of bit field BS should be extended in the following way 1 Adding the bit field combination 1101 14 bit offset address of Remote Window 2 Adding the following text after bit combination 1111 Do not use the values 1101 11105 and 1111 as buffer size BS for Small Transfer Windows Documentation Addendum 18 V2 0 2008 04 Cinfineon MECO User s Manual Peripheral Units Part Volume 2 Page 21 103 The bit description of AOFF should be extended at its end by the following text are not taken into account for further actions assuming the buffer size is configured correctly see Page 21 102 Page 22 164 The bit description of bit PLLCTR AEN must be changed as follows AEN 2 rw Automatic End Mode Enable With the Automatic End Mode the compensation of input signal s period length variation acceleration deceleration is requested Og Automatic End Mode is disabled lg Automatic End Mode is enabled Page 22 228 The content rw of column Type in the last row of the table on top of the page for the Reserved bits must be changed to r
17. e page DDL must be changed to DCL Page 19 18 DSS DC must be changed to DSS PFC at the first sentence of the Passive Frame Counter in Data Repetition Mode section Page 19 19 In the paragraph above Figure 19 12 ENSELL 0 must be changed to ENSELH 0 Page 19 25 In Table 19 6 column USR URR fourth line 010 must be changed to 011g Page 19 26 In the first paragraph OCSR URR must be changed to USR URR Page 19 34 In the paragraph above Figure 19 26 ISC SRDI and ISC CRDI must be changed to ISC SURDI and ISC CURDI Figure 19 26 must be updated with the following figure output signal on the right side Documentation Addendum 15 V2 0 2008 04 Cinfineon TURP CONFIDENTIAL User s Manual Peripheral Units Part Volume 2 ICR ISC Software ISR RDIE 00 E Software Data is received Set gt RDI Receive Data Data is received and gt Interrupt not equal 0014 Hardware to Int Comp Data is received in UD 3 Set MCA05820a_mod Figure 19 26 Receive Data Interrupt Control Page 19 47 The paragraph on the top of the page must be changed to The bit fields of the Downstream Select Data Source High Register DSDSH determine the data source for each bit in shift register SRH The register description table must be changed as follows SHx 2 x 1 rw Select Source for SRH x 0 15 2 x SHx determines which dat
18. ed by the below table Table 8 5 Possible Memory Accesses Memory Bit Byte Half word Word Double word rmw r Ww r Ww r Ww r Ww PMI SPRAM Y A Y Y Y 4 Y Y DMI LDRAM VY Y Vv Y Y A Vv Y Vv PMU ROM Y Y Y Y PFLASH Y VY Y Y Y Y DFLASH VY Y Y Vv VY VY OVRAM VY Y VY Y Y VY VY Y PCP CRAM Y Y Y Y PRAM VY VY Y Y 1 The module also supports LMB 2 Word and 4 Word Block read and write accesses 2 The module also supports FPI 4 Word and 8 Word Block read and write accesses Documentation Addendum 8 V2 0 2008 04 Cinfineon TONGE User s Manual System Units Part Volume 1 Page 9 47 Table 9 13 should be replaced as below Table 9 13 Port 3 Functions Port I O Pin Functionality Associated Port 1 O Control Select Pin Reg Reg Bit Field Value 1 0 Line P3 0 General purpose input P3_IN PO P3_IOCRO PCO OXXXp ASCO input RXDOA O General purpose output P3_OUT PO 1X00 ASCO output Synchronous RXDOA 1X01 Mode only 1X10 Reserved 1X11 P3 1 General purpose input P3_IN P1 P3_IOCRO PC1 OXXXp SCU input OSCBYP O General purpose output P3_OUT P1 1X00 ASCO output TXDOA 1X01 1X10 Reserved 1X11 P3 2 General purpose input P3_IN P2 P3 IOCRO PC2 OXXXp SSCO input Slave Mode SCLKO O General
19. for the pending bit to be set Page 20 50 The second sentence of paragraph 6 must be changed to Transmit acceptance filtering evaluates TXEN1 for each message object and a message object can win transmit acceptance filtering only if its TXEN1 bit is set Documentation Addendum 17 V2 0 2008 04 Cinfineon Tee CONFIDENTIAL User s Manual Peripheral Units Part Volume 2 Page 20 64 The first sentence of the page must be changed to Each of the two CAN nodes has a list that determines the allocated message objects Page 20 66 The first sentence of the page must be changed to When a message object n generates an interrupt request upon the transmission or reception of a message then the request is routed to the interrupt output line selected by the bit field MOIPRn TXINP or MOIPRn RXINP of the message object n Page 20 68 The bit field description of Message Index Mask must be replaced with Only those bits in MSPNDk for which the corresponding Index Mask bits are set contribute to the calculation of the Message Index Page 20 113 The content rw of column Type in the last row of the table on top of the page for the Reserved bits must be changed to r Page 21 29 21 34 At both pages the first bullet paragraphs from the top of the pages should be extended at its end by the following text are not taken into account assuming the buffer size is configured correctly see Pag
20. ineon TGH Table of Contents Page 22 164 19 Page 22 228 19 Page 23 91 19 Page 24 7 20 Page 24 37 21 Page 24 50 24 51 21 Page 24 60 outing ue e a e AA bi Dl AS 21 Documentation Addendum 2 V2 0 2008 04 Cinfineon TC Introduction 1 Introduction This document describes corrections changes and improvements for the TC1766 User s Manual V2 0 2007 07 the System Units Volume 1 and the Peripheral Units Volume 2 These changes will be included in the next update of the User s Manual The referenced documents to this addendum are located at the Internet page e www infineon com tc1766 e TC1766 User s Manual System and Peripheral Units V2 0 July 2007 Documentation Addendum 3 V2 0 2008 04 Cinfineon Tee CONFIDENTIAL User s Manual System Units Part Volume 1 2 User s Manual System Units Part Volume 1 This section describes the updates for the System Units of the User s Manual Page 3 19 Section 3 2 2 5 Setting up the PLL after Reset must be updated Points 1 to 7 of this section must be replaced by the following 9 points red text indicates the changes 1 Wait until the oscillator is running OSC_CON OSCR 1 Selection of the VC
21. s active data in other pages The emulation algorithm can mark the affected page as invalid and program the data to a following page As always the number of consecutive repetitions should be limited e g to 3 as protection against violated operating conditions To keep the EEPROM emulation alive even when wordline two consecutive pages even followed by odd pages oriented fails occur e g due to over cycling the algorithm can implement the following scheme for highest possible robustness e Before programming a page save the content of the other page on the same wordline in SRAM e Program the new page and compare the content with the reference data This can be done with normal read margins Ignore SBEs e Ifthe data comparison fails program this page and the saved content of the other page to a different wordline e This procedure can be repeated if the data comparison fails again The number of repetitions should be limited e g to 3 in case the programming fails because of out of spec operating conditions Due to the specificity of each application the appropriate usage and implementation of these measures together with the more elaborate VER handling must be chosen according to the context of the application Documentation Addendum 7 V2 0 2008 04 Cinfineon TC1766 CONFIDENTIAL Page 8 17 User s Manual System Units Part Volume 1 With the addition of possible memory access for OVRAM Table 8 5 must be replac
22. s of that device or system Life support devices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered 1C1766 32 Bit Single Chip Microcontroller Cinfineon Never stop thinking Cinfineon Teles TC1766 Documentation Addendum Revision History V2 0 2008 04 Previous Versions V1 0 V1 1 V1 2 Page Subjects major changes since last revision This is the first release that refers to the TC1766 User s Manual V2 0 July 2007 Trademarks TriCore is a trademark of Infineon Technologies AG We Listen to Your Comments Any information within this document that you feel is wrong unclear or missing at all Your feedback will help us to continuously improve the quality of this document Please send your proposal including a reference to this document to mcdocu comments infineon com gt Documentation Addendum V2 0 2008 04 Cinfineon MECO Table of Contents Table of Contents 1 Intr oducti n aberrante 3 2 User s Manual System Units Part Volume 1 4 Pag OIG ais RE a ee ee ee ware we we E 4 PaO 6 12 ayaa eae cute wa eed we alae oe ee we ew wee iaa we a ia 4 Page T 34 avec eran ite ea ed wa ae we ee we ee ee were we we E 4 Page A 4 Page 7 360 arre eee 5 Page BI AIKUWA paws era wee
Download Pdf Manuals
Related Search