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1. Table 4 1 Base Register Names and Locations BASE Not used 02H Not used 04H Command Register CR 06H Status Register SR 08H Background Running Pointer BRP Address of Program 0AH Insertion Running Pointer IRP Address of Program 0CH Reserved 0EH Low Priority Interrupt Queue Start Address Pointer 10H Reserved 12H High Priority Interrupt Queue Start Address Pointer 14H Reserved 16H Message Interrupt Queue Start Address Pointer 18H Reserved Status Report Queue Start Address Pointer 1 Reserved RT Simulation Table Address Register RTSTAD 20H Amplitude Register 22H Transformer Direct Coupling Register 24H Toggle Buffer Address Offset MSB I Global Enable 26H SET OF MESSAGES Start Address 28H Global RT Response Time Register us 2AH RT No Response Timeout Register 5 2CH HS Subaddress Register 2EH VXI IRQI Definition Register 30H VXI IRQ2 Definition Register 32H Reserved 34H IRQ Selection Register 36H Minor Frame Counter Register 38H Load Clock Register 3AH Load Clock LO Register 3CH Test and Set register TASR 3EH Service Request Queue Address Pointer SRQADSP 40H Cycling Interrupt Update Register 42H Monitor Current Address Register CAR 44H Monitor Trigger Occurrence Register TOR 46H Monitor Trigger Setup Pointer TSP 48H PRI Bus 1
2. Note For standard 32 bit clock modules the data buffer time tags are 2 words Table 5 3 Data Buffers 54 MODE COMMANDS In Bus Controller mode the VXI 2800 module can transmit all 1553 mode command messages For each mode command message data descriptor blocks pointed through the look up table allow the definition of interrupt requests or associated data word address storage If such a command is directed to an on board simulated RT the corresponding actions are made on the RT simulation table e Transmit RT status word last command word LS bit word e Inhibit or override inhibit LS transmitters Examples a Synchronise with Data Word The data is obtained from the data buffer pointed by the DDB b Transmit Last Command A DDB is analysed the data word transmitted is stored in the data buffer If the RT is simulated the last command word from the RT simulation table is transmitted Transmit Bit Word Similar to transmit last command d Transmit Vector Word Similar the transmit last command and then if the RT is simulated the service request bit in the RT status word is reset and the vector word is reset or updated with the next vector word in FIFO s if any UM10936 Revision C 45 5 5 INTERRUPT REQUESTS Three types of interrupt requests IRQ can be generated by the VXI 2800 module RQ L and IRQ H low priority and high priority are synchronisation interrupts defined
3. A24 A32 ON This bit defines if the A24 A32 memory is enabled for the card 1 enabled MODID A 1 in this bit indicates that the device is not selected via the P2 MODID line READY On power up or system reset this bit shall go to logic 0 On completion of the on board selftests of the resident modules this bit will be driven to logic 1 indicating it is ready for operation This bit is a logical AND of the four PASSED signals from each module slot PASSED On power up or system reset this bit shall go to logic 0 On completion of the on board selftests of the resident modules this bit will be driven to logic 1 if all modules have passed selftest This bit indicates that the system is ready and capable of operating This bit is a logical AND of the four PASSED signals from each module slot CONTROL REGISTER BIT NO 15 14 2 01 03 CONTENTS A24 A32 ON NOT USED SYSFAIL INH RESET A24 A32 ON Setting this bit to 1 will enable the A24 A32 memory At power up or system reset this bit will be set to 0 SYSFAIL INH Setting this bit to a 1 disables the device from driving the SYSFAIL line RESET Setting this bit to a 1 will force the device into a reset state OFFSET REGISTER This 16 bit read write register defines the base address of the A24 A32 memory For further details see the VXI specification UM10936 Revision C 17
4. MSB 1 globaltoggle enable 0 no toggle offset 15 bits MSB offset 15 14 0 For data buffer if the toggle feature is selected bit 15 1 the address of the toggle buffer is Buffer Address High Toggle Buffer Offset Buffer Address Low 15 bits For further details refer to paragraph 4 3 3 3 4 4 2 18 Set of Messages Start Address 26H This is the pointer of 256 word table reserved to the on board processor to compute the registers Set of Messages For further details refer to paragraph 4 5 2 4 4 2 19 Global RT Response Time Register 28H This is the response time for all the simulated RT s Different RT response time can be defined in the error description words LSB lus For some modes this global RT response time register is not programmable fixed at 4us e 1553 Mode without data If the value is less than 4 the on board processor selects 415 4 4 2 20 RT No Response Time Out Register 2AH The programmable RT no response time out defines the maximum RT response time allowed by the board to an RT before detecting NO RESPONSE LSB lus UM10936 Revision C 27 4 4 2 21 Reserved 2 4 4 2 22 VXI IRQI Definition Register 05 1014 D13 D12 DIO 0081007 006 DOS 1004 002 0 0 0 RK I2 LI LO V7 V6 V5 V4 V2 VI RK 1 Release On Acknowledge ROAK RK 0 Release On Read Access DC 1 Daisy Cha
5. 3 3 6 MODULE AND BUS CONFIG SELECT REGISTER This 16 bit read write register is used to select the bus coupling mode and module selection as follows BIT NO 15 4 03 02 01 00 CONTENTS NOT USED BUS CONF ENABLE BUS CONF MODULE SELECT MODULE SELECT Although the motherboard can have up to 4 modules only one module is visible from the VXI bus at any one time This multiplexing means that the A24 A32 memory space is always 2MBytes Setting these bits to 00 017 10 or 11 enables the module 0 1 2 3 respectively When a particular module is selected it s A24 A32 memory will become visible to the VXI bus and the module control register and clock will be accessible via the A16 registers Disabling a module via this register does not inhibit it s operation This is merely a method of accessing up to 4 modules whilst fixing the maximum memory space to 2Mbytes BUS If the BUS CONF bit is set to 0 the 1553 buses of module 0 and 1 and the 1553 buses of 2 and 3 will be connected together If this bit is set to 1 the four 1553 buses will be totally separate This allows the user to connect two buses together without external connections if it is desirable to have more than one module operating on the same dual redundant 1553 bus BUS CONF ENABLE The state of the BUS CONF bit will only change if this bit is also set when writing to the register This is done to allow easy module
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7. Mode and Broadcast commands handling Error Injection Data Words Transfers Data buffer simulation for simulated RTs Sub address based data buffer access offering the same powerful data buffering as in the bus controller mode All non transmitted data messages are monitored 1 4 4 Chronological Bus Monitor CM Features UM10936 Revision C Capture of all bus activity in chronological stack with time tagging of each message Comprehensive multi trigger facilities allowing selective capture and interrupts to be performed on complex data sequence Cyclical stack up to 2Mbyte with interrupt on completion of capture All 1553 errors detected 15 VXI 2800 MOTHERBOARD ARCHITECTURE The VXI 2800 motherboard is a standard VXI interface with high performance architecture and complex features Plugged into a VXI card cage it provides enhanced test and simulation functions for all modes of operation of a MIL STD 1553 bus Up to four modules can be fitted to the motherboard providing control of four separate MIL STD 1553 dual redundant buses 1553 MODULE BUS COUPLING LOGICAL ADDRESS AND A24 A32 SELECT Figure 1 1 VXI 2800 Motherboard Functional Block Diagram 16 16 REGISTERS As well as the standard VXI defined registers a number of user defined registers are available for reading the on board clocks of the module controlling the module access and defining the front panel bus architecture for the MIL
8. C Driver Library P N 1101616 01 to it s own folder Please follow on screen instructions when loading this software 81 2 Up grading Software It is advisable to check our web site at http www western av com to down load any up grades that may be made available for your unit and to see any new releases of support software 8 1 3 On line support If you have any problems with any software provided please contact by e mail at support western av com for prompt attention 8 1 4 Comments and suggestions If you find any errors or areas that are confusing in this manual we would like to hear from you Comments and suggestions can be made on line to support western av com please just reference this User Manual UM 10936 Rev C with your text You may also forward comments and suggestions by fax to 353 61 471675 UM10936 Revision C 71
9. TTT 000 gt Modulation Error XXXXXXXXXXXXX WWWWWWYYYYYYY WWWWWW Word Number For Modulation Error Y Y Y Y Y Y Y ERROR TYPE 0 0 0 0 0 00 Parity error 0 1 1 Il 95 54 53 52 SI 50 Synchro Pattern Error 0 B4 B3 B2 BI Manchester Bit Error 1 L4 L3 L2 LI LO Word Length Error Il TTT 001 gt Wrong Bus Error XXXXXXXXXXXXX 0000000000000 TTT 010 gt Both Bus Error XXXXXXXXXXXXX 0000000000000 TIT 011 gt Word Count Error XXXXXXXXXXXXX 000000PCCCCCC P Word Count Error Polarity 0 Word Count Error VE 1 Word Count Error VE CCCCCC Word Count Error Value Allows 64 Words TTT 100 gt Response Time Error XXXXXXXXXXXXX 00000000RRRRR RRRR Unique Response Time for simulated RT in uS TTT 101 Illegal Command Not applicable for BC Mode XXXXXXXXXXXXX 0000000000000 TTT 110 Extended Subaddress Not applicable for BC Mode XXXXXXXXXXXXX 0000000000000 111 Resync System Clock Not applicable for BC Mode XXXXXXXXXXXXX 0000000000000 UM10936 Revision C 36 NOTES NOTE 1 Word Number For the first word of the message command or status WWWWWwW 000000 2 Synchro Pattern Error Defines a specific synchro bit each Si defines the level for 500ns duration at least 1 bit of SS SO must be set S4 93 52 51 50 right synchro bit example false synchro bit example 55 50 011001 3 Manchester Bit Error B4 BO defines the bit pos
10. 02H Selective Capture Count Register SCCR This register will contain the number of messages to be stored when the monitor is in the Selective Capture Mode This value will be in the range 0000H 8000H 20000H 1 message 8000H Selective Capture Forever 04H Start Page Register SPR This register will contain the desired PAGE address for the start of the monitor stack area 06H Finish Page Register FPR This register will contain the desired PAGE address for the end of the monitor stack area This value must be greater than the Start Page Register value 08H Window Word Count Register This register will contain the word number in the specified message on which the window trigger test is to be carried out If this value is zero the test will be carried out on any word within the specified message 0AH Reserved Register 0CH Hardware Trigger Register D15 014 D13 012 DIO D09 D08 DOS D04 D02 DOI DOO 0 0 0 0 0 0 0 0 0 0 0 0 N P UM10936 P 1 The Monitor will wait for LO HI transition on the TRIG IN input before storing messages and searching for the software trigger condition N 1 The Monitor will wait for a HI LO transition on the TRIG IN input before storing messages and searching for the software trigger condition T 1 Monitor will generate a gt 1 5uS pulse on the TRIG OUT when the software trigger condition
11. 13 2 1 GENERAL ninni 13 2 2 INSTALLATION OE V X1I 2800 rinata iii 13 23 EM UBRO M 13 ZA SET ES Ty e eer o OP C b RP EO OE I 13 2 5 SPECIFIC MODULE FEATURES 14 2 5 1 Control Register 14 2 5 2 i qn AE E 14 2 5 3 Gounter FEedtures a cob rq iere ih ile 14 2 5 4 Trigeer In Features 14 2 5 5 Trigger Ont Features vases dp eta Eee ben es ont coul tee Rusts 14 2 0 eiie berba ee bre evento eb e Lega teo 15 2 6 1 Introduction 15 2 6 2 Electrical Characteristics iii 15 2 6 3 Qm oC TR 15 2 7 1553 3838 INTERFACE D 15 2 7 1 Introduction 15 2 7 2 Electrical Characteristics iii 15 VXI 2800 A16 INTERFACE 16 341 INTRODUGCTION ei 16 3 2 16 REGISTERS BASE ADDRESS SELECTION i 16 33 A16 REGISTERS DESCRIPTION eee iii iii ti iii 16 3 3 1 ID LOGICAL ADDRESS REGISTER 16 3 3 2 DEVICE TYPE REGISTER gir altere Re tere ia 17 3 3 3 STATUS 17 3 3 4 CONTROL REG
12. Base Address 28H This register will define the trigger data allocated to trigger 4 This value will be the range 1 to 4 Trigger 4 Pass Pointer Base Address 2AH This register will define the new trigger to be activated if this trigger condition passes This value will be the range to 5 Trigger 4 Fail Pointer Base Address 2CH This register will define the new trigger to be activated if this trigger condition fails This value will be the range 1 to 5 Trigger Stop Register Base Address 2EH This register will always be programmed to the value 6 This register is the STOP trigger sequence register Trigger Data 1 Trigger Data 1 Bit Mask Register Base Address 30H This register will define the bits to be ignored in the trigger bit pattern for trigger data 1 Any bit set in this register will be masked from the trigger test condition Trigger Data 1 Bit Pattern Register Base Address 32H This register will define the bit pattern required for trigger data 1 Trigger Data 1 Bus ID Word Type Mask Base Address 34H This register will define the Bus ID and Word Type bits to be ignored in the Bus ID Word Type Register 015 014 013 012 D11 DIO D07 DOS 004 D03 D02 DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 Both W bits 1 Ignore Word in trigger condition Both B bits 1 Ignore Bus ID in trigger cond
13. CODE COMMAND 0000H Illegal 0001H GO TO BCT MODE 0002H GO TO MRT MODE 0003H GO TO MON MODE 0004H Reserved 0005H Reserved 0006H Reserved 0007H Reserved 0008H Reserved 0009H Reserved 000AH Reserved 000BH Reserved 000CH LOAD CLOCK 000DH SELFTEST 000EH RUN MONITOR 000FH STOP MONITOR 0010H Reserved 7 2 1 Status Register SR This register contains a code reflecting the status of the board as shown in table 7 3 Table 7 3 Status Registers CODE COMMAND 0001H Reserved 0002H Reserved 0003H MONITOR IDLE 0004H Reserved 0005H Reserved 0006H Reserved 0007H MONITOR RUNNING 0008H Reserved 7 2 2 Transformer Direct Coupling Select Register If the LSB of this register is set to 0 the module will be configured for 1553 transformer coupling If the LSB this register is set to 1 the module will be configured for 1553 direct coupling 7 23 3 VXI IRQI Definition Register D15 D14 D13 D12 D11 DIO D09 D08 006 DOS 004 D03 D02 DOI DOO 0 0 0 RK DC 12 LO V7 V6 5 4 V3 V2 Vi VO RK 1 Release On Acknowledge ROAK RK 1 Release On Read Access RORA DC 0 Daisy Chain Disable 12 LO IRQ Level Level 000 Disable V7 VO IRQ Vector UM10936 Revision C 55 72 4 VXI IRQ2 Definition Register 015 D14 D13 D12 D11 DIO D09 008 007 DOS D
14. MRT mode as a comprehensive window monitor facility 2800 module can also act as a chronological monitor for bus event detection and message recording In this mode the VXI 2800 module can trigger on specific events and sequentially record time stamped messages on a stack The user can define the size and position of this stack NOTE When the VXI 2800 module is in this mode the BC MRT facility is not available All address pointers for the Bus Monitor are 16 bit words defining a PAGE address Each page is 32 bytes Example If a message pointer contains the value 2301H this indicates an absolute address of BASE 2301H x 20H BASE 46020H 7 2 BASE REGISTERS Table 7 1 Base Registers BASE REGISTER 00H Not used 02H Not used 04H Command Register CR 06H Status Register SR 08H Reserved 08H to 20H Reserved 22H Transformer Direct Coupling Select Register 24H to 2AH Reserved 2CH Reserved 2EH VXI IRQI Definition Register 30H VXI IRQ2 Definition Register 32H Reserved 34H IRQ Selection Register 36H Reserved 38H Load Clock HI Register 3AH Load Clock LO Register 3CH Reserved 3EH Reserved 40H Reserved 42H Current Address Register CAR 44H Trigger Occurrence Register TOR 46H Trigger Setup Pointer TSP UM10936 Revision C 54 Table 7 2 Command Registers
15. WESTERN AVIONICS MIL STD 1553 VXI MODULAR INTERFACE BOARD User Manual UM 10936 Rev C Western Avionics Ltd 13 14 Shannon Free Zone Co Clare Ireland 10 June 2002 1 N 4 GENERAL INFORMATION 6 1 1 INTRODUCTION ee Rr ve Ra Re eee ebd du 6 12 MANUAL DESCRIPTION rrr aaa 6 1 3 SYSTEM CHARACTERISTICS AND SPECIFICATIONS eese 7 14 CAPABILITIES D 7 1 4 1 7 1 4 2 Bus Controller BC Features With MRT Simulation and Data Monitoring 8 1 4 3 Multiple Remote Terminal MRT Features 8 1 4 4 Chronological Bus Monitor CM 8 1 5 VXI 2800 MOTHERBOARD ARCHITECTURE 9 1 0 AVG REGISTERS X RERO HO 9 17 COUPLING MATRIX 9 1 8 LOGICAL ADDESSS AND A24 A32 SELECT 9 1 9 VXI 2800 MODULE ARCHITECTURE 10 1 10 PROTOCOL MANAGEMENT UNIT retro eri 10 II I553INTEREACE cadi 10 1 12 FEATURES m 10 1 13 STORAGE RD VL 11 1 14 TOOLS AND TEST EQUIPMENT 11 1 15 SAFETY PRECAUTIONS 11 INSTALLATION AND PREPARATION FOR 5 0
16. 56 7 2 7 Current Address Register CAR 42 56 7 2 8 Trigger Occurrence Register TOR 44 ii 56 7 2 9 Trigger Setup Pointer LSP 409 de anta 56 7 291 TriggerSetup iaia a 57 73 DETAILED TRIGGER DESCRIPTION 58 TA STACK DATA FORMAT ii 69 7 4 1 Previous Address 69 7 4 2 Time Stamp E 69 7 4 3 JD site is 69 7 4 4 Next Address Pointer sigo eo OU ERE 70 7 4 5 RT Response Time 1 2 R H H 70 7 4 6 Flow 70 SOFTWARE TOOLS AND 5 71 3 1 INTRODUCTION 71 8 1 1 Loading Soft a scu ce lalla 71 8 1 2 71 8 1 3 On line SUPport ER 71 8 1 4 Comments and suggestions iii 71 UM10936 Revision C 4 FIGURE 1 1 TABLE 1 1 TABLE 1 2 FIGURE 1 2 FIGURE 4 1 TABLE 4 1 TABLE 4 2 TABLE 4 3 TABLE 4 4 TABLE 4 5 FIGURE 5 1 TABLE 5 1 FIGURE 5 2 TABLE 5 2 TABLE 5 3
17. status word 17 data word Y Y Y Y Y Y Y ERROR TYPE 0 0 0 0 0 0 0 Parity error 0 1 1 5 S4 53 52 SI 50 Synchro Pattern Error B3 B2 BI BO Manchester Bit Error L4 L3 L2 LI LO Word Length Error OWN TTT 001 gt Wrong Bus Error XXXXXXXXXXXXX 0000000000000 TTT 010 gt Both Bus Error XXXXXXXXXXXXX 0000000000000 TIT 011 gt Word Count Error XXXXXXXXXXXXX 000000PCCCCCC P Word Count Error Polarity 0 Word Count Error VE 1 Word Count Error VE CCCCCC Word Count Error Value Allows 64 Words TTT 100 gt Response Time Error XXXXXXXXXXXXX 00000000RRRRR RRRR Unique Response Time for simulated RT in uS See NOTE 4 in paragraph 5 5 2 TTT 101 Illegal Command XXXXXXXXXXXXX 0000000000000 TIT 110 gt Extended Subaddress XXXXXXXXXXXXX 0000000000000 TTT 111 gt Resync System Clock XXXXXXXXXXXXX 0000000000000 NOTES 1 No error 000 WWWWWW 111111 UM10936 Revision 51 6 6 INTERRUPTS CODING 6 6 1 Low and High Priority Interrupts two word code On data messages without error 0800H DDB ad DDB address On data messages with error DDB ad DDB address On mode commands without error 0900H DDB ad On mode commands with error 0D00H DDB ad 6 6 2 Message Interrupts or set of messages interrupt One word code equals message interrupt code in data descriptor block The code is pushed in queue only if the message
18. Days x 100 D Days H Hours 254 word 0000 MMMMMM SSSSSS M Minutes S Seconds 3 word 000000 MMMMMMMMMM M Milliseconds 4 word 00000 UUUUUUUUUUU U 0 5uS ticks If the MSB of the 1 word is set the card is not locked with the incoming IRIG B signal To Load the clock with a new value 1 Write the new value the module base registers Load Clock HGH LOW 1 word LL CC DDDDDDDD HHHH 2 word HH SSSSSSS LL Leap year 0 3 CC Days x 100 0 3 DDDDDDDD Days 0 66 in BCD HHHHHH Hours 0 23 in BCD MMMMMMM Minutes 0 59 in BCD SSSSSSS Seconds 0 59 in BCD To allow decoding of IRIG B the clock always adds 1 second to the programmed value Therefore the above time must be set to the desired time minus 1 second Leap year value should be 00 Leap year 01 1 year after leap year etc 2 Write the Load Clock command code into the command register 3 Now execute generate a command request write 0x0302 in control register If the 1 word is set to LL11111111111111 the free running clock will not be loaded The LL bits will be used to define the leap year and the clock will be forced into external sync mode If the 1 word is not set to LL11111111111111 the free running clock will be loaded and the clock will be forced into free running mode UM10936 Revision C 19 4 2800 MODULE OPERATION 41 INTRODUCTION The VXI 2800 modules provide Bus Controller BC Multi Remote Terminal
19. FIGURE 6 1 TABLE 7 1 TABLE 7 2 TABLE 7 3 TABLE 7 4 List of Figures amp Tables VXI 2800 MOTHERBOARD FUNCTIONAL BLOCK DIAGRAM 9 15 WAY CONNECTOR PINOUTS ca 12 1553 CONNECTOR PINOUTS xs 12 FRONT PANEL LAYOUT ucraini 12 ORGANISATION DIAGRAM IRAN ir 21 BASE REGISTER NAMES AND LOCATIONS 22 COMMAND REGISTER CR NE 23 STATUS REGISTER cis 23 INSTRUCTION SET BACKGROUND PROGRAM eese 24 REMOTE TERMINAL SIMULATION TABLE 31 BUS CONTROLLER ORGANISATION DIAGRAM iii 33 MESSAGE DESCRIPTOR BLOCK iaia 34 DATA BUFFERS SIMULATION AND MONITORING 39 DATA DESCRIPTOR BLOCK 40 DATA BUFFERS alla een 45 MULTIPLE REMOTE TERMINAL ORGANISATION DIAGRAM iii 48 BASE REGISTERS iuerre oE E EE EEKE EEE TERETERE EREK PPO 54 COMMAND REGISTERS a 55 STATUS REGISTERS ottico toes en eA eue gute Uv eie ues bie ii SER ete ere ERES 55 STACK DATA IS uir 69 UM10936 Revision C 5 1 GENERAL INFORMATION 11 INTRODUCTION The VXI 2800 is a VXI register based system for multiple chan
20. MRT and Chronological Bus Monitor CM functions either independently or simultaneously In order to run any of these functions information must be loaded into specific fixed register locations Base Registers Some of these registers contain pointers to other areas of memory registers The selection of these pointers is left up to the discretion of the user Therefore memory blocks can be positioned in the on board memory to suit user requirements This setup means that fixed position registers are minimal 42 CONVENTIONS 1 The architecture of all the 1553 modules is identical 2 BASE A24 A32 Base Address of the motherboard 3 The memory range BASE 10000H to End of Memory is reserved for the 1553 data blocks All other data must reside in the first 64Kbytes After a Power On On board processor doing its power on initialisation Then executing Self Test Then waiting for user command DSI per default insertion program is disabled 43 ORGANISATION DIAGRAM The organisation diagram figure 4 1 shows how the functional areas of the VXI 2800 module can be controlled 44 BASE REGISTERS The only fixed position registers are the Base Registers The Base Registers are the starting points for a description of operation of any of the three modes of operation BC MRT and CM They are located starting at the board Base Address UM10936 Revision C 20 59 xoo o PIEPUEIS 104 93oN
21. Reserved HS Data Reserved HS Reserved HS Reserved Note For standard 32 bit clock modules Figure 5 2 Data Buffers Simulation and Monitoring UM10936 Revision C 39 5 3 1 Look Up Table The sixth word of a message descriptor block points to a double word in the look up table that one contains the address of a LS data descriptor block An identical architecture is defined in MRT mode but using LS sub addresses identifiers to point into the look up table Look up Table Address Error Injection Word MRT only 02H DDB Address Ext Subaddress look up table address 5 3 2 Data Descriptor Block A data descriptor block is associated with each data message this 16 word set defines the data buffering and associated queue control information Interrupt selection is defined in the option mask word interrupt on correct or erroneous message or after a set of different messages priority of interrupt three different available one interrupt only per message The data word count contains the data word count expected by the user The VXI 2800 module processor compares this word count with real data word count transmitted on the bus and writes the difference if any in the data status report word This last word also contains the status flag of the transmission message received correct or with error message running The most significant byte of data buffer address can be used to enable toggled buffer control toggle on beginning of each mi
22. Start Register Base Address 60H This register defines the first trigger to be used in the trigger sequence This will be in the range to 5 UM10936 Revision C 65 Examples The first trigger used in the sequence is defined by the contents of the Trigger Start Register For these examples assume that the Trigger Start Register points to Trigger 1 value 1 Key TTR Trigger Type Register TDP Trigger Data Pointer TPP Trigger Pass Pointer TFP Trigger Fail Pointer TSR Trigger Stop Register Example 1 Find the word defined by Trigger Data 1 then save the number of messages defined by the PTC register TTRI 0001H 0001H 0005H 0001H gt TSR 0006H Find the message with word defined by the Trigger Data 2 followed by the Nth word within the message defined by the Trigger Data 4 Then save the number of messages defined by the PTC register Example 2 TIRI 0001H 0002 0002 0001H TTR2 0002H TDP2 0004H TPP2 0005H Rx 0001H TSR 0006H UM10936 Revision C 66 Example 3 Find the message with word defined by Trigger Data 4 followed by the Nth word within the message defined by Trigger Data 1 by Trigger Data 3 i e Trigger on specific 32 bit word TTRI 0001H 0004 0002 0001H ITR2 0002H TDP2 000 TPP2 0003H TFP2 0001H TTR3 000 TDP3 0003H TPP3 0005H 0001H TTR4 0006H Example 4 Find the me
23. an MBD to define the command word and the inter message gap No queue interrupt or buffer control is carried out The transmitted message will be the command word defined by the MDB followed by two data words Clock Value HI and Clock Value LO clock value at the end message on the bus This message type is only applicable if the module has a standard 32 bit binary clock The transmission of a Broadcast Synchronise with Data mode code using the 1553 mode with data broadcast message type will cause cycling interrupt to be generated if enabled and the associated data word defined in the data buffer will be stored in the cycling interrupt base register 40H 35 5 2 4 18 Message Error Phase Definition 06H The following word defines the location of errors that can be injected into the 1553 message D15 1014 D12 DII DIO D09 0081007 D06 DOS 104 002 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X XXX 000 Error Injection Disabled XXX 001 gt Inject Error in 1st BC TX Initial BC message XXX 010 gt Inject Error in 2nd BC TX 2nd BC TX HS RT RT XXX 011 gt Inject Error in 1st RT SIM Ist RT response XXX 100 gt Inject Error on 2nd RT SIM 2nd RT RT response 5 2 5 LS Message Error Description Word 08H The following word defines the errors that can be injected into the 1553 message 015 1014 D12 DIO 009 D07 D06 005 004 002 DO T T T X X X X X X X X X X X X X
24. be cleared in the control register 4 4 2 5 4 4 2 6 4 4 2 7 4 4 2 8 4 4 2 9 4 4 2 10 4 4 2 11 4 4 2 12 4 4 2 13 The background program can be interrupted by insertion command The insertion program cannot be interrupted by any other insertion command In this case the second insertion request will be delayed until the end of the first one Insertion program starting just before a minor cycle start will delay this IRP is updated by the on board processor after executing BC stop command Reserved 0CH LPIQAP 0EH Low priority interrupt queue start address Reserved 10H HPIQAP 12H High priority interrupt queue start address Reserved 14H MIQAP 16H Message interrupt queue start address Reserved 18H SRQAP IAH Status report queue start address Reserved ICH UM10936 Revision C 26 4 4 2 14 RTSTAD RT simulation table start address Contains the address of the RT Simulation Tables which defines the RT status when they are simulated 4 4 2 15 Amplitude Register 20H The least significant 8 bits of this register shall define the TX amplitude for the module 4 4 2 16 Transformer Direct Select Register 22H If the LSB of this register is set to 0 the module will be configured for 1553 transformer coupling If the LSB of this register is set to 1 the module will be configured for 1553 direct coupling 4 4 2 17 Toggle Buffer Address Offset 24H
25. has been detected C 1 Monitor will generate 21 515 pulse on the TRIG OUT when the post trigger message count has been reached Revision C 57 7 3 DETAILED TRIGGER DESCRIPTION The Bus Monitor has four triggers that can be set up to trigger on a wide variety of complex conditions Each trigger can be allocated one of four different data and error conditions If a trigger passes this condition it then moves on to the trigger defined by the Pass register If a trigger fails this condition it then moves on to the trigger defined by the Fail Register Each trigger 1s allocated a trigger type value from one to six and these are as follows Value 1 Value 2 Value 3 Value 4 Single Trigger Mode The Single Trigger Mode will search for the trigger data defined by the Trigger Data Pointer Register If this condition is TRUE for the incoming 1553 word the Single Trigger will branch to the trigger defined in the Pass Register If it fails it will branch to the trigger defined by the Fail Trigger Register Window Trigger The Window Trigger Mode will search for the trigger data defined by the Trigger Data Pointer Register within the first 1553 message it encounters If this condition is TRUE for a word within the incoming message the Window Trigger will branch to the trigger defined in the Pass Register If the value of the Window Word Count Register is non zero the Window Trigger will use this value to specify the word numbe
26. on Both Buses UM10936 Revision C 62 Trigger Data 2 Error Word Mask Register Base Address 44H This register will define if the Error Word Register is to be included in the trigger condition DIS D14 D13 012 011 DIO 009 008 D07 D06 DOS D04 D02 D01 DOO 0 0 D 0 0 0 0 0 0 0 0 0 0 0 0 0 D 1 Error condition disabled Trigger Data 2 Error Word Register Base Address 46H This register will define the Errors required in the trigger condition If more than one error is set the trigger condition will be a logical OR of the errors D15 014 D13 012 DIO 109 DOS D04 D02 DO DOO 0 0 0 Ig Sh 0 0 WC 0 0 TA Sy 0 Sy Sync Type Error Sh 1 Short Word Error TA 1 Terminal Address Error Lg 1 Long Word Error NR 1 No Response Error Mn 1 Manchester Error WC 1 Wordcount Error Py 1 Parity Error Trigger Data 3 Trigger Data 3 Bit Mask Register Base Address 48H This register will define the bits to be ignored in the trigger bit pattern for trigger data 3 Any bit set in this register will be masked from the trigger test condition Trigger Data 3 Bit Pattern Register Base Address 4AH This register will define the bit pattern required f
27. selection changes without the user having to remember the initial bus configuration Providing bit 3 is 0 the user can easily switch from module to module by writing values to the 2 LSBs without fear of disturbing the bus configuration MODULE CONTROL CLOCK HI READ REGISTER A write to this register controls the currently selected module as follows BIT NO 15 10 09 08 07 06 05 04 03 02 01 00 CONTENTS 0 1 1 0 0 0 2 VI 0 CO CO Clear gt Command Request Cl Clear gt Insertion Request VI Set gt Release VXII IRQ RORA V2 Set Release VXI2 IRQ RORA Example 0x0302 generates a command request whilst enabling the clock A read of this register will be the upper 16 bits of the selected module clock UM10936 Revision C 18 3 3 8 MODULE CLOCK HI LO READ REGISTER For standard 32 bit clock modules a read HI followed by a read LO will report the current value of the 32 bit clock For IRIG B type modules the clock read is done as follows These two registers are for reading the current value of the on board clock A read of the Clock HI will request the current value of the clock to be latched into the output buffer The user must wait a minimum time of gt 0 5uS before beginning to read the clock value to ensure latching has completed Four consecutive reads of the Clock LO location will return the clock value as 15 word CC DDDDDDD HHHHH C
28. the trigger type allocated to trigger 2 This value will be the range 1 to 6 Trigger 2 Data Pointer Base Address 1 8H This register will define the trigger data allocated to trigger 2 This value will be the range 1 to 4 Trigger 2 Pass Pointer Base Address This register will define the new trigger to be activated if this trigger condition passes This value will be the range to 5 Trigger 2 Fail Pointer Base Address This register will define the new trigger to be activated if this trigger condition fails This value will be the range 1 to 5 Trigger 3 Trigger 3 Type Register Base Address This register will define the trigger type allocated to trigger 3 This value will be the range 1 to 6 Trigger 3 Data Pointer Base Address 20H This register will define the trigger data allocated to trigger 3 This value will be the range 1 to 4 Trigger 3 Pass Pointer Base Address 22H This register will define the new trigger to be activated if this trigger condition passes This value will be the range to 5 Trigger 3 Fail Pointer Base Address 24H This register will define the new trigger to be activated if this trigger condition fails This value will be the range 1 to 5 UM10936 Revision C 60 Trigger 4 Trigger 4 Type Register Base Address 26H This register will define the trigger type allocated to trigger 4 This value will be the range 1 to 6 Trigger 4 Data Pointer
29. 04 D02 001 0 0 0 RK 12 Ll LO V7 V6 V5 V4 V3 V2 VI VO RK 1 Release On Acknowledge ROAK RK 1 Release On Read Access RORA DC 0 Daisy Chain Disable 12 10 IRQ Level Level 000 Disable V7 VO IRQ Vector 7 2 5 IRQ Selection Register D15 D12 0 DII D09 TRIGGER CONDITION DETECTED D08 D06 POST TRIGGER COUNT COMPLETE D05 D03 STACK PULL WRAP ROUND D02 D00 STACK HALF FULL Bl 1 IRQ on VXD BO 1 IRQ on VXII 7 2 6 Load Clock HI LO Registers 38H1 3AH See base register and clock description 7 2 7 Current Address Register CAR 42H IRQ Selection 0 BO IRQ Selection 0 BO IRQ Selection 0 BO IRQ Selection 0 BO This register contains the PAGE address of the current message being stored 7 2 8 Trigger Occurrence Register TOR 44H This register contains the PAGE address of the message that met the pre programmed trigger condition 7 2 9 Trigger Setup Pointer TSP 46H This register contains the absolute address of the trigger setup data UM10936 Revision C 56 7 2 9 1 Trigger Setup Data TSP Address 00H Post Trigger Count Register PTCR This register will contain the number of messages to be stored after the trigger condition is met This value will be in the range 0000H to 8000H 0000H Stop immediately after trigger message 8000H Capture Forever
30. 3 BSR 0004H XXXXH XXXX 16 bit signed branch to subroutine BRA 0006 XXXXH XXXX 16 bit signed branch JMP 0007H XXXXH XXXX 16 bit absolute address for jump RTS 0008 Return from subroutine RTI 0009H Return from insertion routine ENI 000 Enable program insertion DSI 000 Disable program insertion LOOP 000CH XXXXH Load loop counter with value XXXX DBNE 000DH XXXXH LOOP If lt gt O branch signed offset XXXX INITF 000EH XXXXH Initialise frame duration to XXXX LSB 1005 SWPSE 000 Wait for new on board start of frame HALT 0010H End of BC program SITL OOH XXXXH Set low priority IRQ Push XXXX on LO queue SITH 0012H XXXXH Set high priority IRQ Push XXXX on queue HWPSE 0013H wait for external Trig LO HI for new frame SMB 0014H XXXXH Send message XXXXH absolute address of MDB TRGOUT 0015H XXXXH Trig out to the XXXXH level UM10936 Revision C 24 e Instructions e NOP 1 2 3 e NOPx the user can replace one two or three instruction words e BSR BRA DNBE e The offset is defined in bytes count always even offset e BSR e 15 levels of subroutines available e TRGOUT e Instructions to put TRIGOUT at 0 if xxxx 0000H or 1 if xxxx 0001H e On power on the output is 0 level per default e LOOP xxxx e Load loop counter with value XXXX Only one level of loop e INITF xxxx XXXX Minor frame duration minor cycle
31. 4 Data N 3 Errors N 2 RT Response Time 1 LSB 0 5 uS N 1 RT Response Time 2 LSB 0 5 uS N Next Address Pointer 7 4 1 Previous Address Pointer The first word of each message will define the page address of the previous message The first message stored will set this pointer to 0000H 7 4 0 Time Stamp 1 2 3 4 These locations are the value of the IRIG B clock when the message started NOTE For standard 32 bit clock modules the time stamp 15 2 words 7 4 3 Data These words describe the previous DATA word TYPE BUS ID and associated errors as follows 015 014 013 012 D11 DIO D08 D07 DOS D04 D03 D02 DOO ED 0 0 Sh TI 70 WC BI BO NR TA Sy 0 ED Indicates last 1553 word in message Py 1553 data word had a Parity error Mn 1553 data word had a Manchester error Lg 1553 data word had too many bits Long Sh 1 1553 data word had too few bits Short UM10936 Revision C 69 describe the 1553 word type as follows WORD TYPE 0 0 Command Word 0 1 Status Word 1 0 Data Word 1 1 RT RT Command Word WC 1 Indicates 1553 message had a word count error Only set for last word BO Describe the bus the 1553 word was captured on as follows BUS ID 0 0 Illegal 0 1 Secondary 1 0 Primary 1 1 B
32. 442 9 Reserved iiie terc Rial ra atio eo 26 4 4 2 10 MIQAP 16H Message interrupt queue start address i 26 4 4 2 11 Reserved 1 is E iii 4 4 2 12 SRQAP IAH Status report queue start address 4 4 2 13 Reserved aie eredi iecit tee 442 14 RTSTAD RT simulation table start address 4 4 2 15 Amplitude Register OA sc 4 4 2 16 Transformer Direct Select Register 22H 4 4 2 17 Toggle Buffer Address Offset 24 4 4 2 18 Set of Messages Start Address 26H 4 4 2 19 Global RT Response Time Register 23 4 4 2 20 RT No Response Time Out Register 4 4 2 21 Reserved 20H ctor re 4 4 2 22 VXI IRQI Definition Register 4 4 2 23 Definition 4 4 2 24 IRQ Selection Register 2 4 4 2 25 Test and Set Register and SRQADP 3CH 4 4 2 26 Reserved 46H Ere PIER ana 4 4 2 27 PRI SEC 1553 RT TX Inhibit HI LO 48H 56H 4 5 REMOTE TERMINAL SIMULATION TABLE 4 5 1 Simulati
33. 553 RT TX inhibit bits 4AH PRI Bus 1553 RT TX inhibit bits LO 4CH SEC Bus 1553 RT TX inhibit bits 4EH SEC Bus 1553 RT TX inhibit bits LO UM10936 Revision C 22 442 Base Register Descriptions The Base Register functions are defined in the following paragraphs 4 4 2 1 Command Register CR 04H Prior to clearing the command request bit CO in the control register the user must first test that the command register is clear When the command register is clear the user can insert the next command to be executed After the command is loaded bit CO in the control register can be cleared When the command register clears the board is ready for a new command Refer to table 4 2 Table 4 2 Command Register CR CODE COMMAND 0000H Illegal 0001H GO TO BC MODE 0002H GO TO MRT MODE 0003H GO TO MON MODE 0004H BC COLD Start 0005H BC WARM Start 0006H BC STOP 0007H MRT COLD Start 0008H MRT WARM Start 0009H MRT STOP 000AH Illegal 000BH Illegal 000CH LOAD CLOCK 000DH SELFTEST 000EH RUN MONITOR 000FH STOP MONITOR 0010H Illegal 4 4 2 2 Status Register SR 06H The status register will contain a word reflecting the status of the board as shown in table 4 3 Table 4 3 Status Register CODE STATUS 0001H BC IDLE 0002H MRT IDLE 0003H MON IDLE 0004H BC RUNNING 0005H BC INSERTION RUNNING 8004H BC PAUSE
34. ADP in Base Registers and control the words pointed at are clear if these words are non zero the queue is full Reaching the end of the queue the user must restart at the beginning of the queue UM10936 Revision C 29 If several user CPUs can enter requests at the same time it is necessary to share control SRQADP using for example the TASR flag with a test and set instruction To enter a request a CPU must carry out the following procedure Test and set the TASR word MSB bit and a b If free SRQADP is read to define entry address in queue If the entry location defined by the SRQADP are clear the two words may be entered in the queue If these words are non zero the queue is full Increments the SRQADP if the end is reached reinitialise it to the beginning Resets the TASR If not free waits until free 4 4 2 26 Reserved 46H 4 4 2 27 PRISEC 1553 RT TX Inhibit HI LO 48H 56H HI RT 30 a RT17 RT16 LO RT15 RT14 RTO 0 enable the transmitter 1 disable the transmitter A bit set defines the specific RT transmitter as inhibited Initialisation by the user before cold start Disable enable by corresponding mode command messages The user can modify the inhibit bits in real time The receive function of the simulated RT is never disabled UM10936 Revision C 30 45 REMOTE TERMINAL SIMULATION TABLE For each RT 16 wor
35. D Background 8005H BC PAUSED Insertion 9004H EXECUTING SOFTWARE PAUSE SWPSE A004H EXECUTING HARDWARE PAUSE HWPSE 0006H MRT RUNNING 8006H MRT PAUSED 0007H MON RUNNING 0008H MON RUNNING XXX8H EXECUTING SELFTEST FINISHED SELFTEST UM10936 Revision C 23 The status register will contain the following information after completion of self test DIS 1014 D12 DIO 0081007 006 DOS 1004 002 1 0 0 LS 0 0 5 M4 2 1 0 0 0 LS 1 1553 Interface Test Failed LC 1 Local Clock Test Failed M5 1 Memory Test 5 Failed M4 1 Memory Test 4 Failed M3 1 Memory Test 3 Failed M2 1 Memory Test 2 Failed 1 Memory Test 1 Failed Several bits can be set simultaneously If no self test errors are detected the SYSFAIL LED will go out and the code in the status register will be 8008H 4 4 2 3 Background Running Pointer BRP 08H In the BC mode the Background Running Pointer BRP directs the firmware to the location of a background program which can be used to organise the message sequencing Before sending a BC start the user must initialise the BRP BRP is updated by the on board processor after executing a BC STOP command Table 4 4 is a list of the possible instructions with descriptions and examples Table 4 4 Instruction Set Background Program DELAY 0000H XXXXH XXXX Delay LSB of 10us 000 PC NOP2 0002H PC PC 2 NOP3 0003H PC PC
36. EGISTER DEVICE TYPE REGISTER STATUS CONTROL REGISTER OFFSET REGISTER DEVICE CLASS DEPENDANT REGISTERS NOT USED MODULE AND BUS CONFIG SELECT REGISTER NOT USED MODULE CONTROL CLOCK HI READ REGISTER MODULE CLOCK LO READ REGISTER NOT USED 331 ID LOGICAL ADDRESS REGISTER BIT NO 15 14 13 12 11 00 CONTENTS DEVICE CLASS ADDRESS SPACE MANUFACTURERS ID e The device class is register based and hence these bits will read as 11 e The address space will be one of 2 values depending on the state of the A24 A32 selection switch on the motherboard This field will read 01 defining A32 access or 00 defining A24 address space e The remaining 12 bits of this register will be the Western Avionics manufacturers ID code UM10936 Revision C 16 3 3 2 DEVICE TYPE REGISTER BIT NO 15 12 11 00 CONTENTS REQUIRED MEMORY MODEL CODE The required memory field will contain a value 0 15 defining the amount of A24 A32 memory space required by the motherboard This will always be set to define 2Mbytes However the actual number will be different for A24 and A32 bit selection For further details see the VXI specification The remaining 12 bits of this register will be the Western Avionics model code STATUS REGISTER BIT NO 15 14 13 04 03 02 01 00 CONTENTS 24 32 NOT USED READY PASSED NOT USED
37. ILITIES VXI 2800 is capable of the following functions 1 4 1 General Memory mapped real time VXI access Simultaneous control of up to four MIL STD 1553 dual redundant buses 2MByte of RAM per module Two VXI Vectored Interrupts 1553 data protocol managed by micro controller providing flexibility and extensibility Full Error Injection capability External Triggers Internal Self tests Standard single slot VXI board UM10936 Revision C 7 1 4 2 Bus Controller BC Features With MRT Simulation and Data Monitoring Bus Control Autonomous frame control using comprehensive set of instructions and message descriptor blocks Acyclic message insertion Error injection Frame frequency selection Inter message gap selection Response time out selection Bus events detection mask storage and reporting bus errors status word bits e Simultaneous MRT Simulation up to 31 e Data Words Transfers e Data buffer simulation for the BC and the simulated RT s Sub address based data buffer access with data descriptor blocks defining each bus message Multi buffering linked buffers frequency toggled buffers Vectored interrupts section two different interrupts with vector queues e Data status report Data buffer time tagging Simultaneous monitoring of all data buffers 14 3 Multiple Remote Terminal MRT Features Simulation Up to 31 RT simulations
38. ISTER levano 17 3 3 5 OFFSET REGISTER biblia idea ela 17 3 3 6 MODULE AND BUS CONFIG SELECT REGISTER 18 3 3 7 MODULE CONTROL CLOCK HI READ REGISTER 18 3 3 8 MODULE CLOCK READ REGISTER 19 2800 20 41 INTRODUCTION iaia 20 422 S 20 UM10936 Revision 2 43 ORGANISATION DIAGRAM rrr Rep ciale 20 4 4 REGISTERS scie io 20 4 4 1 Base Register Names and Locations eese 22 4 4 2 Register Descriptions uis se DHT et 23 4421 Command Register 04 23 442 2 Stat s Register SR 06H soie nei pen HI DP RD ela 23 4423 Background Running Pointer BRP 8 24 4424 Insertion Running Pointer 4 2 22 4044410 00000000000000000000000000000 000 0 0 50000000000 26 44 25 Reserved OCH icine OIL ETUR LER vecia 26 4 4 2 6 LPIQAP 0EH Low priority interrupt queue start address 26 44227 Reserved nina a Li rie ev ida 26 4 4 2 8 HPIQAP 12H High priority interrupt queue start address 26
39. ST After applying power to the 2800 or after re setting system self test will be performed The VXI 2800 will perform a system self test that tests the Bus Controller Multi Remote Terminal and Chronological Bus Monitor of any resident modules lasting approximately three seconds UM10936 Revision C 13 25 SPECIFIC MODULE FEATURES 2 5 1 Control Register Features This is a 16 bit write only register accessible from the VXI bus via the A16 registers This register is mapped into the memory field The features are as follows e Hardware reset e Firmware reset e Two prioritised interrupts to the local on board processor for indication and control e Acknowledge VXI 1 Interrupt e Acknowledge VXI 2 Interrupt 2 5 2 Clock features The local clock can be one of to types depending on the module firmware type used If the module firmware type is standard 32 bit clock then the format will be a 32 bit binary clock That will have an LSB of 10uS for BC MRT and MRT operations and 0 5uS for CHRON MON operations If the module firmware type is IRIG B then the clock format will be as follows 2 5 3 IRIG B Counter Features This 4 x 16 bit word counter can be setup to decode incoming IRIG B serial time code or programmed to free run This counter reports the date and time of day accurate to 0 5uS The value of this register can be read via dedicated registers in A16 address space When free running this counter can be pre set updated by t
40. STD 1553 buses 17 BUS COUPLING MATRIX This matrix allows the user to define the MIL STD 1553 buses as direct or stub coupled It also allows interconnections to be made between the buses This enables the MIL STD 1553 buses of two modules to be connected without the need of external coupling and interconnections Control of this matrix is achieved via the A16 user defined registers 18 LOGICAL ADDESSS AND A24 A32 SELECT The logical address 15 defined by two hexadecimal selection switches on the motherboard A third two way switch is provided for selecting the mode of access to the modules This allows the modules to reside in A24 or A32 space depending on the state of this switch These switches are labelled on the module cover panel UM10936 Revision C 9 19 2800 MODULE ARCHITECTURE Each module is a memory mapped 1553 interface with high performance architecture and complex features and provides enhanced test and simulation functions for all modes of operation of a MIL STD 1553 bus The host equipment defines in the on board RAM all configuration and data structures Protocol Management INTERFACE 1553 INTERFACE 1 10 PROTOCOL MANAGEMENT UNIT A micro controller based structure running at 40Mhz handles the management of the 1553 protocols for each of the operating modes BC MRT BM The micro controller works each of the 1553 command status and data words functions of its operating mode and the config
41. age status report will occur and a retry if selected BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 Bit 10 to 00 NOTE Wrong Both bus error No response error RT address error Transmission error Wrong sync error Status bits of RX status word not including address bits Transmission error includes Manchester error long or Short word error Parity error Word Count error and Late Response error UM10936 Revision C 34 5 2 3 Message Type Word 04H BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 to 8 BIT 07 BIT 06 BIT 05 BIT 04 BIT 03 BIT 02 BIT 01 BIT 00 NOTES UM10936 Revision C 1 1553 TX on PRI bus 1 1553 TX on SEC bus 0 0 11 10 09 08 0 0 0 0 1553 MODE WITHOUT DATA 0 0 0 1 1553 MODE WITH DATA 0 0 1 0 1553 RT RT 0 0 1 1 1553 BC RT RT BC 0 1 0 0 Reserved 0 1 0 1 Reserved 0 1 1 0 Reserved 0 1 1 1 Reserved 0 0 0 0 1553 MODE WITHOUT DATA BROADCAST 1 0 0 1 1553 MODE WITH DATA BROADCAST 1 0 1 0 1553 RT RT BROADCAST 1 0 1 1 1553 BC RT BROADCAST 1 1 0 0 Reserved 1 1 0 1 RX clock value BROADCAST 1 1 1 0 Reserved 1 1 1 1 Reserved 1 Extended Subaddress 1 Retry on EVENT 1 Interrupt on EVENT enabled 1 Interrupt on EVENT HI priority queue 0 LO priority If RETRY is enabled and IRQ on EVENT is disabled the RETRY will still take place Broadcast Receive Clock is a special message used for transmitting the 32 bit clock as data This message type only requires
42. and Synchronise with Data Word When receiving a broadcast mode command Synchronise with Data word the on board processor e Stores the data word value in the Cycling Interrupt Update Register in base registers and set the cycling IRQ e Accesses to a DDB to store the data word in a buffer and time tag the data buffer Uses the value of the data word which is for example the minor cycle number 0 to 7 to manage frequency toggling of the data buffers 6 7 4 Frequency Toggle The frequency toggle option works in the same manner as the BC mode except that the minor cycle number is given by the data word associated to the mode command synchronise with data word This mode command is due to circulate on the bus at the beginning of each minor cycle and toggles bank A or B are managed when this message occurs Minor Cycle 0 1 2 3 4 5 6 7 8 9 B frequency F Hz A B A F 2 Hz A B A F 4 Hz A A A F 8 Hz A A A 6 7 5 Programmable HS RI TI Time DDB When MRT mode these values have an offset of 18us For example if the user requires a TI time of 30us a value of 12 must be stored in the DDB word UM10936 Revision C 53 7 CHRONOLOGICAL BUS MONITOR MODE OF OPERATION 71 INTRODUCTION When acting in BC
43. ap Time e Gap between the two 1553 messages initiating a HS RT RT message e LSB lus 5 2 15 Status Word 1 ICH First RX Status Word in the message If the BC detects no response error this value will be updated with FFFFH 5 2 16 Status Word 2 Second RX Status Word in the message RT RT If the BC detects a no response error from the second RT this value will be updated with FFFFH UM10936 Revision C 38 53 DATA BUFFERS SIMULATION AND MONITORING The 2800 module processes all the data buffers running on the 1553 lines Data buffers to be issued by the BC or the simulated RTs are transmitted by the VXI 2800 module all others can be monitored A multiple data buffering structure is implemented Identical paths are used to access the data buffers whether they are transmitted received LS or HS These paths use a look up table and data descriptor block Refer to figure 5 2 Data Buffers Simulation and Monitoring LOOK UP TABLE LS TYPE DATA DESCRIPTOR BLOCK LS DATA BUFFERS Option mask Header Address M Tagi ime Tag 2 Reserved MRT Data Word Count Time Tag 3 Data descriptor Block Address Data Status Report Time Tag 4 Toggle Freq Buffer Addr High Data Buffer Address Low Data Link Pointer to another DDB Reserved Reserved Message Interrupt Code Set of Message Number Data
44. as follows By instructions in the BC instruction list In message descriptor block to report on bus events detection In data descriptor block to signal the transmission of message RQ M is a data message interrupt and occurs only when the transmission of a data buffer is correct and the requesting bit is set in the data descriptor block It can also be programmed to occur with the last message of a set of 2 to 16 messages set of messages option When setting an IRQ the VXI 2800 module pushes a vector code into queues each code defines the event origin of the IRQ Each queue must start at an address multiple of 200H The user must manage the reading pointer and erase with a 0000H value the codes after reading 5 5 1 Interrupt Coding 1 LO and priority interrupts two words Messages without error 0800H DDB Address Messages with error 0C00H DDB Address BC Event without RETRY 1000H Status Queue Address BC Event with RETRY 4000H Status Queue Address Send Interrupt SITL SITH 2000 SITL SITH Vector 2 Message Interrupts one word Message Interrupt Code from DDB Only if Message is Good 5 5 2 Set Message Interrupts When in a DDB bit 12 of the option mask word is set e The 10th word gives a set of message numbers 00H to FFH e The 12th word gives a message indicator e For each set the on board processor manages a set word register It makes OR with the message indicator in th
45. atus Word 1 ACH 38 3 2 16 Status Word 2 EH aaa 38 5 3 DATA BUFFERS SIMULATION AND e 39 5 3 1 LOOK Op Tale 40 5 3 2 Data Descriptor Block ilaele 40 5 3 2 1 Option NUUS PR 41 5322 Data Status Report 00LL s soto eec 41 UM10936 Revision 3 a N 8 5 3 2 3 Toggle Frequency and Buffer Address HI 08 41 5324 Link Pointer to New DDB 43 5 3 2 5 Address of Modify Word Value to Write 0EH 10H i 43 3 3 2 0 Extended Sub Addr SS nere ARR OR ri 43 5 3 3 Data BUI CUS oor EP 44 54 MODECOMMANDS 45 929 INTERRUPT 10 c eadi eiue se EEDE anei Eai aeaee eiin Enies 46 IIL 46 5 5 2 Sel Message INLEN TUDES Tono OD HORIS TORO ED ernia 46 3 3 3 Message Status Report Queue iii 47 MULTIPLE REMOTE TERMINAL MODE OF 48 6 1 INTRODUGTION oe 48 6 2 LOOK UPITABLES sci ici rinata ria 49 63 MODE COMMANDS SPECIFICATIONS 49 64 DATA WORDS STORAGE csie O 49 6 5 LS ERROR INJECTION DEFINITION 20 enne trennen inneren teen inneren 50 6 5 1 Global RT Erro
46. ding on the number of the running minor cycle and the frequency indicator of the message Minor Cycle 0 1 2 3 4 5 6 7 8 9 B frequency F F Hz B A A A F 2 Hz A A A F 4 Hz A F 8 Hz A A A A A A UM10936 Revision C 42 5 3 2 4 Link Pointer to New DDB 0CH If the message is good or bit 10 of the option mask is clear and bit 9 of the option mask is set the value in this location will replace the original DDB address in the look up table This feature defines a different DDB for the next occurrence of the same message 5 3 2 5 Address of Modify Word Value to Write 0EH 10H After the message is complete and bit 8 of the option mask is set the Value to write is written in the address defined by the contents of OEH Action is limited to the first 64K bytes of the memory 5 3 2 6 Extended Sub Address To enable the extended sub address feature see the MDB type word When enabled the value of the DDB address in the look up table is in fact a pointer for a further look up table called the extended look up table The on board processor uses the LS byte of the first data word received multiplied by four to calculate an offset in the extended look up table to find the true DDB address word Therefore the DDB and data buffer used is defined b
47. ds are used to define and store information concerning RTs The pointer to this table RTSTAD must be a multiple of 20H Refer to table 4 5 RTSTAD 00H Simulation Type word 02H RT Status Word 04H LS Last Command Word 06H LS Look up Table Address MRT Only 08H Reserved 0AH LS Mode Commands Look up table Address MRT Only 0CH Vector Word 0EH LS BIT Word RH 10H Reserved 12H Reserved 14H Reserved 16H Global RT Error Descriptor Word MRT Only 18H Not Used 1AH Not Used 1CH Not Used 1EH Not Used 20H RT1 1 1 3C0H 3E0H Only 3 words used Set all others to 0 Broadcast LS Look up Table B n Reserved Broadcast Broadcast LS Mode Commands Look up Table Address Table 4 5 Remote Terminal Simulation Table 4 5 1 Simulation Type Word BIT 15 1 RT simulated Bits BIT 14 1 Reserved 14100 BIT 13 1 Inhibit transmitter LS on primary bus are for BIT 12 1 Inhibit transmitter LS on secondary bus MRT BIT 7 1 Errors enabled on primary bus status word and data only BIT 6 1 Errors enabled on secondary bus Status word and data BITO 1 Enable global error injection other bits 0 Bits 7 and 6 Enable global RT errors defined in the RT simulation table as message per UM10936 Revision C message errors defined in the look up tables 81 4 5 2 Status Word Broadcast and message error bits are dynamically updated S
48. e set word register Then if the set word register is equal to FFFFH the on board processor sends message interrupt code defined in the 9th word of the DDB and resets the set word register It is possible to define sets from 2 to 16 messages The user initialises at 0 the set of messages table The 256 word set of messages table is pointed to by the set of Messages Start Address 26H in Base registers UM10936 Revision C 46 5 5 3 Message Status Report Queue At the end of a message if an event is detected and matches with the 1553 Event Masks of the MDB a Message Status Report is pushed in to the Message Status Report queue 2 words per report 1 1553 Messages Message Number MSB 0 EVENTS with EVENTS BIT 15 Wrong Both Buses Error BIT 14 NO RESPONSE Error BIT 13 RT ADDRESS Error BIT 12 TX Error Mn LG SH Py WC Late Resp BIT 11 SYNC Type Error Bit 09 0 Ist Status 1 2nd Status BIT 10 BITS 08 to 00 RX Status Bits UM10936 Revision C 47 6 MULTIPLE REMOTE TERMINAL MODE OF OPERATION 6 1 INTRODUCTION In Multiple Remote Terminal mode the VXI 2800 module can simulate up to 31 RTs After initialisation by the host the board is ready to listen to the bus activity and to respond to command words for the simulated RTs The description of the mode of operation uses tables similar to those defining the bus controller mode providing the same associated features multiple data buffer
49. ervice request bit automatically set by the request files and cleared by the TX vector word mode code command Busy bit can be set by user to disable data transmission 4 5 3 LS Last Command Word Automatically updated including broadcast So the TX last command mode code is correctly simulated 4 5 4 LS Bit Word For user purposes UM10936 Revision C 32 5 BUS CONTROLLER MODE OF OPERATION 5 1 INTRODUCTION In the Bus Controller mode the VXI 2800 module board runs a list of instruction pointed to by the Background Running Pointer defining the bus frame Each bus message is defined by a Message Descriptor Block MDD and the associated data is accessed through a Look Up Table LUT and Data Descriptor Blocks DDB the same way as in the Multi Remote mode Remote Terminals can simultaneously be simulated non simulated data buffers can be monitored An internal minor frame duration counter allows autonomous control of cycling frames Acrylic messages can be inserted on the host request Insertion instruction lists define sequences of messages to be inserted Refer to figure 5 1 Bus Controller Organisation Diagram BASE REGISTER Message Descriptor Block Message Number Background Program sag BRP hae Area LLL Address in LUT TELD 4 To 1553 LUT gt wane annn gt SMB 4 Insertion Pr
50. essages have been stored the next trigger is defined by the Pass register Therefore the two selective capture triggers allow the storage of a specific message or messages Value 6 Post Trigger Count Mode This mode is used as a terminator to the trigger sequence This mode simply stores the number of messages defined by the Post Trigger Count Register on the stack and then stops activity If the PTC is set to H8000 storage will continue until the board is commanded to halt NOTES This trigger mode always resides in the Trigger Stop Register and never in any other register This is trigger 5 and must always be pointed at as the last part of the trigger sequence Trigger 1 Trigger 1 type Register Base Address 0 This register will define the trigger type allocated to trigger 1 This value will be in the range to 6 Trigger 1 Data Pointer Base Address This register will define the trigger data allocated to trigger 1 This value will be the range 1 to 4 Trigger 1 Pass Pointer Base Address 12H This register will define the new trigger to be activated if this trigger condition passes This value will be the range to 5 Trigger 1 Fail Pointer Base Address 14H This register will define the new trigger to be activated if this trigger condition fails This value will be the range 1 to 5 UM10936 Revision C 59 Trigger 2 Trigger 2 Type Register Base Address 16H This register will define
51. for the Bus Controller of VXI 2800 Multiple Remote Terminal Mode of Operation contains information on the mode of operation for the Multiple Remote Terminals VXI 2800 Chronological Bus Monitor Mode of Operation contains information on the mode of operation for the Chronological Bus Monitor of VXI 2800 13 SYSTEM CHARACTERISTICS AND SPECIFICATIONS The characteristics and specifications of VXI 2800 are listed as follows e VXI Specifications Device Type VXI Register Based Instrument Module Size C size one slot wide VXI Compatibility Conforms to Revision 1 3 of VXI specification BITE 95 Confidence Level e Weight 1550 grams 3 4 165 e Power 5Vdc 3 6A max 12Vde 370mA max 12Vdc 15mA max e Cooling Requirements For 10 C temperature rise at maximum load Airflow 1 32 l s Backpressure 0 14 mm H O e Temperature Operating 0 C to 50 C Non operating 20 C to 70 C e Humidity 0 C to 29 C 95 RH 30 C to 40 C 75 RH e Mean Time Between Failure MTBF per MIL 217E Hours Temp Category 86 932 20 C GB Ground Benign e Front Panel 1553 Connectors Tri axial type CBBJR79 e Front Panel I O Connector 15 way sub miniature D type DB15 HF e LED Indicators FAIL Shows Status of Selftest RDY System Ready for Operation CH 0 Bus Traffic Present Bus 0 module CH 1 Bus Traffic Present Bus 1 module CH 2 Bus Traffic Present Bus 2 module CH 4 Bus Traffic Present Bus 3 module 14 CAPAB
52. for the trigger condition UM10936 D15 D14 013 D12 D11 DIO D08 DOS D04 D02 DOI DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 Wmsb WLsb BMsb BLsb 0 0 Trigger on Command 0 0 Illegal 0 1 Trigger on Status 0 1 Trigger Primary 1 0 Trigger on Data 1 0 Trigger on Secondary 1 1 Trigger on RT RT Transfer 1 1 Trigger on Both Buses Revision C 64 Trigger Data 4 Error Word Mask Register Base Address 5CH This register will define if the Error Word Register is to be included in the trigger condition D15 014 D13 012 DIO 109 DOS D04 D02 DO DOO 0 0 D 0 0 0 0 0 0 0 0 0 0 0 0 0 D 1 Error condition disabled Trigger Data 4 Error Word Register Base Address 5EH This register will define the Errors required in the trigger condition If more than one error is set the trigger condition will be a logical OR of the errors D15 014 D13 D12 DIO 109 D08 DOS D04 D02 DOI DOO 0 0 0 lg Sh 0 0 WC 0 0 NR TA 5 10 Sy 1 Sync Type Error Sh 1 Short Word Error TA 1 Terminal Address Error Lg 1 Long Word Error NR 1 No Response Error Mn 1 Manchester Error WC 1 Wordcount Error Py 1 Parity Error Trigger
53. he user The format of this clock is as follows The first 3 values will be the current clock time as decoded from the IRIG B time code The last 16 bit word will be a value 0 1999 defining the fraction of a millisecond with a resolution of 0 5uS per tick 15 word NO CC DDDDDDD HHHHH C Days x 100 D Days H Hours 254 word 0000 MMMMMM SSSSSS M Minutes S Seconds 34 word 000000 MMMMMMMMMM M Milliseconds 4 word 00000 UUUUUUUUUUU U 0 5uS ticks If the MSB of the 1 word is set the card is not locked with the incoming IRIG B signal 2 5 4 Trigger In Features Trigger In enters the board logic through the 15 way front panel connector and then an opto coupler So if the diode is powered there is a zero logic level and if the diode is not powered there is a high logic level So a rising edge on this logic level can be used for hardware starts of the frame hardware starts of the minor cycle or external trigger for the bus monitor 2 5 5 Trigger Out Features Trigger Out is in fact a bit in a register accessible by the on board processor to indicate to the external world that an event has been detected This event can be as follows Beginning of the minor cycle Beginning of message e Bus Monitor trigger detected Trigger Out exits the board through an opto coupler and the 15 way front panel connector UM10936 Revision C 14 2 6 VXIINTERFACE 2 6 1 Introduction The VXI interface of the VXI 2800 conform
54. his service request queue is 3 words long starting at the initial address in the service request queue address pointer SRQADP For a request two words are set in the queue as follows 1 RT number 000000000RRRRRIX RT address X Priority 1 1 2 Vector word Two different priorities are available X High priority X 1 Low priority Reading this FIFO the on board processor manages each RT two 32 word vector words FIFO s one per priority These vector words are then used by the RT simulation If an RT FIFO is not empty the on board processor reads it then writes the value in RT vector words RT Simulation Table and sets the service request bit in the status word If a Transmit Vector Word mode command message occurs the on board processor reads the RT FIFO s If empty the on board processor resets the service request bit and the vector word Otherwise the on board processor reads the FIFO s and writes this next value in the RT vector word High priority vector words are processed before low priority vector words The following 4Kbyte block after the service request queue is reserved for the individual RT requesting FIFO s managed by the on board processor cicci 5 SERVICE REQUEST QUEUE 003EH Di 0040H sirene ie P ES To enter a request in the User Requesting Queue the user must manage the current writing pointer SRQ
55. in Enable 12 10 IRQ Level level 000 disable 7 0 IRQ Vector 4 4 2 23 VXI IRQ2 Definition Register 30H DIS 1014 D12 DIO 0081007 006 DOS 1004 002 0 0 0 RK I2 LI LO V7 V6 V5 V4 V2 VI VO RK 1 Release On Acknowledge ROAK RK 0 Release On Read Access DC 1 Daisy Chain Enable L2 LO IRQ Level level 000 disable V7 V0 IRQ Vector 4 4 2 24 Selection Register 34H D15 014 D13 DI2 D11 DIO D08 005 004 D02 0 0 0 0 Cycling Message HI Queue LO Queue 0 B1 BO 0 B1 BO 0 B1 BO 0 D15 D12 0 DII DO9 Cycling minor cycle IRQ Selection BI B0 D08 D06 Message IRQ Selection BI B0 D05 D03 HI Queue IRQ Selection BI BO D02 D00 LO Queue IRQ Selection B1 B0 BI 1 IRQ on VXIIRQ2 B0 1 IRQ on VXI IRQI UM10936 Revision C 28 4 4 2 25 Test and Set Register and SRQADP These two words are used to automatically manage FIFO s of vector words for each simulated RT For simulated RTs the Service Request bit in the status word can be set and reset by the user The vector word can be initialised by the user After a Transmit Vector Word mode command message the on board processor automatically resets the service request bit and the vector word On the other hand a service request queue is defined to automatically queue words representing successive requests for the simulated RTs T
56. ing signalisation etc Refer to figure 6 1 the Multiple Remote Terminal Organisation Diagram The specifics of the MRT mode of operation mainly concern the following e The logical path to point into the look up tables e The errors injection capabilities BASE REGISTER RT Simulation DATA Table BUFFERS RTO BRP RTI RTO LS LUT Time Tag HI DDB Time Tag LO Illegalization Word a Options mask Data RX DDB Address Queues Address Data buffer Address HI RT30 TX Data buffer Address LO RTSTAD RT31 Broadcast Low High Priority Priority Interrupt Interrupt DATA BUFFERS RTO LS Mode Onli DDB k 10ns mas Code LUT p Time Tag HI Time Tag LO Message Message Tllegalization Word Data buffer Address Interrupt Status DDB Address Report BC MRT MRT Figure 6 1 Multiple Remote Terminal Organisation Diagram UM10936 Revision C 48 6 2 LOOK UP TABLES For each RT the 2800 module manages two different look up tables the address of these tables are obtained from the RT simulation tables These tables are as follows e LS Look up Table giving a descriptor for each LS sub address LS Mode Command Look up Table giving a descriptor for each LS mode code NOTE The T R bit of the Command word or Action word is used as an offset to point to the RX o
57. ion Table The following word defines the errors that can be injected into the message 015 1014 D12 DIO 009 0081007 106 005 004 002 DO T T T x x x x X X X X X X X X X TTT 000 gt Modulation Error XXXXXXXXXXXXX WWWWWWYYYYYYY WWWWWW Word Number For Modulation Error Y Y Y Y ERROR TYPE 0 0 0 0 0 0 0 Parity error 0 55 54 53 52 SI 50 Synchro Pattern Error 1 0 B4 B3 B2 BI BO Manchester Bit Error 1 1 L4 L3 L2 LI LO Word Length Error TTT 001 gt Wrong Bus Error XXXXXXXXXXXXX 0000000000000 TTT 010 gt Both Bus Error XXXXXXXXXXXXX 0000000000000 TTT 011 gt Word Count Error XXXXXXXXXXXXX 000000PCCCCCC P Word Count Error Polarity 2 Word Count Error VE 3 Word Count Error VE CCCCCC Word Count Error Value Allows 64 Words TTT 100 Response Time Error XXXXXXXXXXXXX 00000000RRRRR RRRR Unique Response Time for simulated RT in uS See NOTE 4 in paragraph 5 5 2 NOTE Global error injection is enabled disabled by the LSB bit of the simulation type word UM10936 Revision C 50 6 5 2 Message Error Injection Word Look up Table The following word defines the errors that can be injected into the message 015 1014 D12 DIO 009 D07 106 005 004 002 DO T T T x X X X X X X X X 0 X X X TIT 000 gt Modulation Error XXXXXXXXXXXXX WWWWWWYYYYYYY WWWWWW Word Number For Modulation Error 0
58. is correct Sets of Messages Same feature as for BC mode 6 6 3 Status Report Queue two words per report Code pushed into queue only if error on message and Interrupt on erroneous message not set in the DDB lst Word 2nd Word BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 to 0 UM10936 Revision C Pointer to the double word in look up table look up table address index Events Wrong Both Buses Error No Response Error RT Address Error TX Error Mn Lg Sh Py WC Late Response SYNC Type Error Not Used 52 6 7 SPECIFIC FUNCTIONS 6 7 1 Data Message Reception Each data message not transmitted by VXI 2800 module may be stored The path to access the data buffer is given by the RT look up table for messages BC lt gt RT Except for RT gt RT messages even if the RTs are simulated or not the path to point to the data buffer is always given by the transmitting RT look up table but the receiving RT look up table must point to a false DDB Received status words from RTs not simulated on board are stored in the associated disabled RT SIM table If an external RT fails to respond a value of FFFFH will be stored in the SIM table 6 7 2 Reception of Mode Commands Data Words For each mode command with data word message if the data word is not transmitted by the board it must be stored RT simulated or not The path for storing the data word is given by the RT mode command look up table 6 7 3 Comm
59. ition Trigger Data 1 Bus ID Word Type Register Base Address 36H This register will define the Bus ID and Word Type for the trigger condition 015 D14 013 012 D11 DIO D07 DOS 004 D03 D02 DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 WMsb WLsb BMsb BLsb 0 0 Trigger on Command 0 0 Illegal 0 1 Trigger on Status 0 1 Trigger on Primary 1 0 Trigger on Data 1 0 Trigger on Secondary 1 1 Trigger on RT RT Transfer 1 1 Trigger on Both Buses UM10936 Revision C 61 Trigger Data 1 Error Word Mask Register Base Address 38H This register will define if the Error Word Register is to be included in the trigger condition DIS D14 D13 012 D11 DIO 009 008 D07 D06 DOS D04 D02 D01 DOO 0 0 D 0 0 0 0 0 0 0 0 0 0 0 0 0 D 1 Error condition disabled Trigger Data 1 Error Word Register Base Address This register will define the Errors required in the trigger condition If more than one error is set the trigger condition will be a logical OR of the errors D15 014 D13 D12 DIO D09 D08 DOS D04 D02 DOI DOO 0 0 0 lg Sh 0 0 WC 0 0 NR TA Sy 10 Sy 1 Sync Type Error Sh 1 Short Word Error TA 1 Terminal Addre
60. ition in the word for the error 4 Word Length Error L4 LO defines the number of bits in the word This count has an offset of 1 such that a value of 01111 will result on a valid word with a data bit count of 16 e Wrong bus error RT response on the wrong bus e Both busses error RT response on both busses e Response time error RRRRR replaces the global RT response time LSB 1 uS e Illegal command Reserved for only 5 2 6 Address in Look Up Table OAH This will contain the address in the look up table for the DDB pointer See figure 5 1 5 2 7 Command Word 1 OCH First Command Word 5 2 8 Command Word 2 0EH Second Command Word RT RT 1553 5 2 9 Reserved 10H 5 2 10 Reserved 12H UM10936 Revision C 37 5 2 11 Retry Subroutine Absolute Address 14H On completion of a message if an Event defined by the Mask has occurred and the Retry Event is enabled the Subroutine defined by this absolute address will be called NOTES 1 The retry subroutine must be terminated by the RTS instruction to return execution back to the main background or insertion program 2 This feature can be used for immediate insertion of Acyclic messages or retry of the same message on the alternate bus 5 2 12 Reserved 16H 5 2 13 Inter message Gap Time 18H e Gap between the end of this message and the LS line and the beginning of the next one next MDB LSB 0 1 uS 5 2 14 HS RT RT Inter message G
61. nel dual redundant MIL STD 1553 applications The VXI board consists of a standard VXI mother board and front panel allowing up to four independent 1553 modules to be used in a variety of combinations to provide up to four Bus Controller Multi Remote Terminal with Monitoring functions or two Bus Controller Multi Remote Terminal and Chronological Bus Monitors on a single VXI card The VXI 2800 provides a powerful and intelligent interface between VXI based host equipment and the MIL STD 1553 data bus and provides comprehensive test and simulation functions for MIL STD 1553B systems 12 MANUAL DESCRIPTION The following paragraphs provide a general description of the manual layout and content Section 1 Section 2 Section 3 Section 4 Section 5 6 UM10936 Revision General Information contains a brief description of the manual and a general description of VXI 2800 This section also contains the architecture protocol management MIL STD 1553 interface information instrument specifications information concerning accessories furnished items and also safety precautions Installation and Preparation for Use contains instructions on installation preparation for use self test and reset of VXI 2800 Operation contains a functional description of 2800 and operating procedures necessary to run VXI 2800 Bus Controller Mode of Operation contains information on the mode of operation
62. nor frame or on multiple cycles of this minor frame This allows user software synchronised on the frame cycle to always access the correct buffer The set of message interrupt features provides the possibility to send an interrupt after the last message of the set of messages It is to be used when the frame sequence is not purely repetitive Up to 128 different sets of messages from 2 to 16 messages each can be defined Refer to table 5 2 Error injection on LS data words is defined in the message descriptor blocks Table 5 2 Data Descriptor Block DDB ADDRESS OPTION MASK 02H Header Address 1553 only 04H Data Word Count 06H Data Status Report 08H Toggle Frequency and Buffer Address HI 0AH Buffer Address LO 0CH Link Pointer to Address of another DDB 0EH Address of Modify Word 10H Value to Write 12H Message Interrupt Code 14H Set of Message Number 16H Message Indicator in the Set of Messages UM10936 Revision C 40 5 321 Option Mask 00H BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 09 BIT 08 BIT 07 BIT 06 BIT 05 BIT 04 to 00 1 Interrupt on Correct Message 1 Interrupt on Error Message 1 HI LO Priority Queue LO 1 HI 1 Interrupt on Set of Messages 1 Message Interrupt If Message Correct 1 Link only on Correct Message 1 Link to New DDB Enabled 1 Modify Word Enabled 0 0 0 Header Word Count 5 3 2 2 Status Re
63. ogram Queues Address RTSTAD i RT Simulation 4 Table DATA RTO BUFFERS RTI Time Tag HI DDB Time Tag LO Options mask Data buffer Address HI Data buffer Address LO Low High RT30 1553 LUT 4 4 Priority Priority gt a r Interrupt Interrupt Address from MDB Message Message Interrupt Status Report Note For IRIG B clock type modules the data buffer time tags are 4 words BEB BERBER MRT Figure 5 1 Bus Controller Organisation Diagram UM10936 Revision C 33 5 2 MESSAGE DESCRIPTOR BLOCK MDB Each bus message is defined by a message descriptor block as shown in table 5 1 Table 5 1 Message Descriptor Block MBD ADDRESS MESSAGE NUMBER 02H LS Event Mask 04H Message Type Word 06H LS Message Error Phase Definition 08H Ls Message Error Description Word 0AH Address in Look up Table 0CH Command Word 1 0EH Command Word 2 10H Action Word 1 12H Action Word 2 14H Retry Subroutine Absolute Address 16H Reserved 18H Inter message Gap Time 1AH Reserved 1CH Status Word 1 received 1EH Status Word 2 for RT RT received 5 2 1 Message Number 00H The number of the message is used in Message Status Report to identify messages 5 2 2 LS Event Mask 02H A logical AND is carried out with the LS event mask and the detected bus events If the result is lt gt 0 a mess
64. on Type Word 4 5 2 Status Word inerenti 4 5 3 LS Last Command WOE pae t eb qe 4 5 4 LS Bit wn 5 BUS CONTROLLER OF 2 2 33 5 1 INTRODUCTION eater co E EE EORR D RH WERTE RE 33 5 2 MESSAGE DESCRIPTOR BLOCK 34 5 2 1 Message 00 34 5 2 2 DS Event Mask 029 aisi toe iii i 34 5 2 3 Message Type 04H ero venta ai 35 5 2 4 LS Message Error Phase Definition 06 36 3 2 5 LS Message Error Description Word 08H 36 5 2 6 Address in LooksUp Table CIR Coated UM CUR ER REASONS 37 5 2 7 Command Word 1 ei tib ee E lee odiana 37 5 2 8 Command Word 2 37 5 2 9 Reserved E 37 9324103 Reserved 1D d Run oru SEU e ts slo de Eo lia 37 5 211 Retry Subroutine Absolute Address 14 38 2212 Reserved ioc onec tu 38 24413 Inter message Gap Time 18H 38 5 214 HS RT RT Inter message Gap Time 38 2 245 St
65. or trigger data 3 Trigger Data 3 Bus ID Word Type Mask Base Address 4CH This register will define the Bus ID and Word Type bits to be ignored in the Bus ID Word Type Register D15 014 D13 D12 DIO 109 D08 DOS D04 D02 DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 Both W bits 1 Ignore Word Type in trigger condition Both B bits 1 Ignore Bus ID in trigger condition Trigger Data 3 Bus ID Word Type Register Base Address 4EH This register will define the Bus ID and Word Type for the trigger condition D15 014 D13 D12 DIO 109 D08 DOS D04 D02 DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 UM10936 WMsb WLsb BMsb BLsb 0 0 Trigger on Command 0 0 Illegal 0 1 Trigger on Status 0 1 Trigger on Primary 1 0 Trigger on Date 1 0 Trigger on Secondary 1 1 Trigger on RT RT Transfer 1 1 Trigger on Both Buses Revision C 63 Trigger Data 3 Error Word Mask Register Base Address 50H This register will define if the Error Word Register is to be included in the trigger condition DIS D14 D13 012 011 DIO 009 008 D07 D06 DOS D04 D02 DO DOO 0 0 D 0 0 0 0 0 0 0 0 0 0 0 0 0 D 1 Error condition disabled Trigger Data 3 Error Word Register Base Address 52H This register will define the Er
66. oth Buses NR 1 Indicates that an RT failed to respond to a command No Response Only set for last word TA 1 Indicates that the RT status word did not match the address of the command word Terminal Address Error Sy 1 Indicates that the 1553 word did not have the correct SYNC type 7 4 4 Next Address Pointer This word will define the page address of the next message This value will be set to FFFFH for the last message after the post trigger count has expired and capturing has stopped 7 4 5 Response Time 1 2 These two locations will define the RT response times if any of the Status words in the message The second Response time is only applicable for 1553 RT RT transfers 7 4 6 Flow Diagram TRIGGER SETUP Base 46H Trigger STACK Setup Register PTCR SCCR SPR FPR etc UM10936 Revision C 70 8 SOFTWARE TOOLS AND SUPPORT 81 INTRODUCTION Western Avionics provides a complete suite of library functions in C source code together with a Windows Graphical User Interface GUI as standard for all PCI based products The Windows GUI utilises the driver library functions to provide commonality of approach in programming Up grades are made freely available on our web site 8 1 1 Loading Software Software is provided on a standard 3 25 floppy disk as a self loading file titled WIN3910 EXE Running this disk will load the Windows GUI P N 1L01675H01 in a single folder and
67. port 06H BIT 15 to 14 BIT 13 to 00 00 Good Message 01 Message Running 10 Error Message Signed Wordcount Error 00 No Wordcount Error NOTE The wordcount error is calculated as follows 1553 TX Wordcount Command Wordcount DDB Count Header Count 1553 RX Wordcount Wordcount Received DDB Count Header Count 5 3 2 3 Toggle Frequency and Buffer Address HI 08H The word 24H in Base Registers defines if the data buffer toggle feature is enabled and also the toggle offset MSB 1 global toggle enabled 0 no toggle offset 15 bits MSB OFFSET 15 14 0 UM10936 Revision C 41 The Sth word in DDB enables the toggle feature for the corresponding data buffer and the toggle frequency BIT 15 1 Enable toggle local BIT 14 to 11 0 BIT 10 to 08 Frequency indicator gt 000 FHz 001 F 2Hz 011 F 4Hz 111 F 8Hz BIT 07 to 00 Buffer Address When global toggle is enabled for a data buffer if the toggle feature is selected bit 15 1 the address of the toggle buffer is Buffer Address High Toggle Buffer Offset 15 bits Buffer Address Low DDB bitIS 1 4 Buffer Address Offset Buffer Buffer Bank A Bank B The toggle is synchronised on the minor frame counter register which is incremented on each minor cycle restart The on board processor stores the data buffer in bank depen
68. r Description Word RT Simulation Table seen 50 6 5 2 Message Error Injection Word Look up Table esee eene 5l 6 6 INTERRUPTS CODING eres cds too Ee vetoed Reve NE EP Ee ORENSE 52 6 6 1 Low and High Priority Interrupts two word code sesser 52 6 6 2 Message Interrupts or set of messages interrupt 52 6 6 3 Status Report Queue two words per report 52 6 7 SPECIFIC FUNCTIONS 53 6 7 1 Data Message Reception nennen nennen rene ree reet eene trt tret eret rentre trennen 53 6 7 2 Reception of Mode Commands Data Words 53 6 7 3 Mode Command Synchronise with Data 53 6 7 4 Frequency 53 6 7 3 Programmable HS RI TI Time DDB ii 53 CHRONOLOGICAL BUS MONITOR MODE OF OPERATION serrerrerrcreeerie see rie nie nienioniene 54 INTRODUCTION aio 54 7 2 5 oet niter ete MER oer e frd 54 7 2 1 Status Repisiei SR ecdesia eod 55 7 4 2 Transformer Direct Coupling Select Register esee 55 7 2 3 VAT TROL Definition Register iie pe obti Libia 55 7 2 4 VXI IRQ2 Definition Register 56 7 2 5 IRO Selection lalla 56 7 2 6 Load Clock HILO Registers 38 1
69. r TX block of the look up tables Each descriptor includes A Message Error Description or Illegalization word e A Data Descriptor Block Address or Extended sub address look up table address as for BC mode 63 MODE COMMANDS SPECIFICATIONS All illegal mode codes defined in the STANAG 3838 and MIL STD 1553 standard are automatically illegalized The error descriptor word allows illegalization of complementary mode codes Associated data words which are not obtained from the RT Simulation Tables can be obtained from or stored in memory using Data Descriptor Blocks For each mode code DDB can be used to define IRQ s 64 DATA WORDS STORAGE To avoid data buffers overwriting in memory when receiving a data message the VXI 2800 module does not store more data words than the number defined by Data Word Count 1 if no header option Data Word Count Header Word Count 1 if header option Data Word Count is defined in the DDB The extra word for LS messages will be the last received word of a message in excess of the DDB data word count UM10936 Revision C 49 65 LS ERROR INJECTION DEFINITION Error injection on status word and LS data words transmitted can be defined message by message using the message error descriptor word in the look up table or globally for all messages transmitted by an RT using global RT error injection word in each RT simulation table 6 5 1 Global RT Error Description Word RT Simulat
70. r within the message for the Trigger test to be carried out If this value is zero all words within the message will be tested The Window Trigger would normally be preceded by a Single Trigger The Single Trigger would define the specific 1553 command word then pass to the Window Trigger to define a specific bit pattern of a particular word within this message If the Window Trigger Fail Register points back to the Single Trigger requirements then the monitor will start again with the next 1553 message Reserved Selective 1 Trigger Mode The Selective 1 Trigger searches for a particular word as with the Single Trigger type However if the last word of a message is encountered before this trigger condition is met the message 15 not saved on the stack If this trigger condition is met it will branch to the trigger defined by the Pass Register UM10936 Revision C 58 Value 5 Selective 2 Trigger Mode This trigger type is the same as the Window Trigger with the following exceptions a If the specific word within the message is not found the message will not be stored on the stack and the next trigger is defined by the contents of the Fail Pointer Register When the trigger condition is found the message is stored on the stack If the number of selective messages defined by the Selective Capture Count Register have not been stored the next trigger is defined by the contents of the Fail Pointer Register When the programmed number of m
71. rors required in the trigger condition If more than one error is set the trigger condition will be a logical OR of the errors D15 014 D13 012 DIO D09 D08 DOS D04 D02 DOI DOO 0 0 0 lg Sh 0 0 WC 0 0 NR TA 5 10 Sy 1 Sync Type Error Sh 1 Short Word Error TA 1 Terminal Address Error Lg 1 Long Word Error NR 1 No Response Error Mn 1 Manchester Error WC 1 Wordcount Error Py 1 Parity Error Trigger Data 4 Trigger Data 4 Bit Mask Register Base Address 54H This register will define the bits to be ignored in the trigger bit pattern for trigger data 4 Any bit set in this register will be masked from the trigger test condition Trigger Data 4 Bit Pattern Register Base Address 56H This register will define the bit pattern required for trigger data 4 Trigger Data 4 Bus ID Word Type Mask Base Address 58H This register will define the Bus ID and Word Type bits to be ignored in the Bus ID Word Type Register D15 014 D13 012 DIO 109 DOS D04 D02 DO DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 Both W bits 1 Ignore Word Type in trigger condition Both B bits 1 Ignore Bus ID in trigger condition Trigger Data 4 Bus Word Type Register Base Address 5AH This register will define the Bus ID and Word Type
72. s to V XIbus specification IEC821 2 6 2 Electrical Characteristics 5V 12V and 12V e All driving and loading rules are respected 2 6 3 Capabilities The VXI 2800 module is used as 2Mbyte field R W Static DRAM 2Mbyte Read only 32 bit counter 16 address space Write only 16 bit register one 16 bit access The Control Register is mapped into the A16 address space 2 7 1553 3838 INTERFACE 2 7 1 Introduction The interface matches the MIL STD 1553 Standard 2 1 2 Electrical Characteristics The 1553 interface provides one dual redundant bus e Primary bus e Secondary bus The 1553 interface can be e Transformer coupled e Direct coupled UM10936 Revision C 15 3 2800 A16 INTERFACE OPERATION 31 INTRODUCTION The VXI 2800 A16 interface is responsible for defining the global options for the system and controlling access to the various resident modules All global setup and control is achieved via the A16 address space registers 32 A16 REGISTERS BASE ADDRESS SELECTION The address of the A16 registers are defined by the 8 bit selection switch as follows A16 BASE ADDRESS x 0x40 0xC000 Where V is the 8 bit value defined by the selection switch For example if the switch is set to OxAA the A16 registers base address will be OxEA80 0xEA80 0xAA X 0x40 0xC000 33 A16 REGISTERS DESCRIPTION The address of the A16 registers are as follows ID LOGICAL ADDRESS R
73. ss Error Lg 1 Long Word Error NR 1 No Response Error Mn 1 Manchester Error WC 1 Wordcount Error Py 1 Parity Error Trigger Data 2 Trigger Data 2 Bit Mask Register Base Address 3CH This register will define the bits to be ignored in the trigger bit pattern for trigger data 2 Any bit set in this register will be masked from the trigger test condition Trigger Data 2 Bit Pattern Register Base Address 3EH This register will define the bit pattern required for trigger data 2 Trigger Data 2 Bus ID Word Type Mask Base Address 40H This register will define the Bus ID and Word Type bits to be ignored in the Bus ID Word Type Register DIS D14 D13 012 011 DIO 009 008 D07 D06 DOS D04 D02 D01 DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 Both W bits 1 Ignore Word Type in trigger condition Both B bits 1 Ignore Bus ID in trigger condition Trigger Data 2 Bus ID Word Type Register Base Address 42H This register will define the Bus ID and Word Type for the trigger condition D15 D14 D13 D12 DIO D09 D08 DOS D04 D02 DO DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 WMsb WLsb BMsb BLsb 0 0 Trigger on Command 0 0 Illegal 0 1 Trigger on Status 0 1 Trigger on Primary 1 0 Trigger on Data 1 0 Trigger on Secondary 1 1 Trigger on RT RT Transfer 1 1 Trigger
74. ssage with word defined by Trigger Data 4 followed by the Nth word within the message defined by Trigger Data 1 Then selectively capture all messages with word defined by Trigger Data 3 followed by word within the message defined by Trigger Data 2 TTRI 0001H TDPI 0004H TPP 0002 000 TTR2 0002H TDP2 0001H TPP2 0003H TFP2 0001H PTTR3 0004H TDP3 0003H PP3 0004 TFP3 0003H PTTR4 0005H TDR4 0002H 0005 0003H TSR 0006H UM10936 Revision C Example 5 Find the message with word defined by Trigger Data followed by the Nth word within that message which does not meet the conditions of Trigger Data 2 TTRI 0001H TDP 0001H 0002 0001H TTR2 0002H TDP2 0002H TPP2 0001H 2 0004H Re 0006H UM10936 Revision C 68 74 STACK DATA FORMAT When the Bus Monitor is commanded to start all messages will be stored before the trigger condition is met Therefore all pre trigger data is captured The first captured message will start at the address defined by the Start Page Register All following messages will start on an even PAGE boundary The STACK data will wraparound after the Finish Page Register value has been exceeded The formats of the messages are shown in table 7 4 Table 7 4 Stack Data Format WORD No NAME 1 Previous Address Pointer 2 Time Stamp 1 3 Time Stamp 2 4 Time Stamp 3 5 Time Stamp 4 6 Data 7 Errors N
75. t LED Status Indicators RDY 4 cH 10 1553 Primary Secondary connectors typical for all 4 channels Table 1 1 15 Way I O Connector Pinouts PIN DESCRIPTION 1 TRIGGER OUT 0 2 TRIGGER OUT 1 3 TRIGGER OUT 2 4 TRIGGER OUT 3 5 TRIGGER IN 0 ANODE 6 TRIGGER IN 0 CATHODE 7 TRIGGER IN 1 ANODE 8 TRIGGER IN 1 CATHODE 9 TRIGGER IN 2 ANODE 10 TRIGGER IN 2 CATHODE 11 TRIGGER IN 3 ANODE 12 TRIGGER IN 3 CATHODE 14 NO CONNECTION 14 IRIG B INPUT 15 GROUND Table 1 2 1553 Connector Pinouts PIN DESCRIPTION INNER 1553 POSATIVE OUTER 1553 NEGATIVE CASE GROUND SHEILD Figure 1 2 Front Panel layout UM10936 Revision C 12 2 INSTALLATION AND PREPARATION FOR USE 21 GENERAL On delivery inspect the unit for possible damage If it is damaged notify the shipping company and contact your distributor or Western Avionics for details of return procedure When unpacking remove all protective covering and store covering as unit may need to be reshipped at a later date CAUTION 22 INSTALLATION VXI 2800 Prior to installing VXI 2800 into the rack ensure that all power has been removed from the rack 23 TURN ON Set mains power on rack to The VXI 2800 will perform system self test on the BC MRT and CM features of any resident modules lasting approximately three seconds 24 SELFTE
76. time e 10 us for the LSB the value for 20ms is e It must be initialised at the beginning of the background program e This instruction resets the minor frame counter register e SWPSE Software Pause e To be put at the end of each minor cycle instruction list with the minor frame duration utility to have automatic minor frame restart Examples INITF xxxx HWSPE waiting an external trig SWPSE JSR Minor Cycle 1 SWPE SWPSE BRA xxxx with Minor cycle X SMB xxxx SMB xxxx RTS LOOP 8 JSR Minor cycle SWPSE DBNE xxxx SITH BRA xxxx e Insertion Commands can be executed during SWPSE state UM10936 Revision C 25 4 4 2 4 HALT e On completion of this instruction the board will return to the BC idle state e To re start the board BC Cold Warm Start command register SITH xxxx SITL xxxx e The on board processor puts the value code xxxx in the cycling FIFO s gt High Priority L gt Low Priority HWPSE Hardware Pause e Restart by the external Trig In external CK e All the registers are not initialised e Used to synchronise messages of minor frames on external Trig In Example See SWPSE above Insertion Running Pointer IRP OAH The Insertion Running Pointer IRP has the same set of instructions as Instruction Set Background Program To initiate an insertion the user must first load the IRP with the address of the insertion program Then bit Cl can
77. uration tables in RAM The micro controller directly drives word by word the 1553 interface The micro controller management unit allows flexibility and expandability as well as for the bus control tasks as for the user interface 1 11 1553 INTERFACE The 1553 interface is a dual redundant interface which includes a standard dual redundant transceiver and a Manchester decoder encoder with full error detection and error injection capabilities Manchester bit error Synchronisation bit error Parity error Word length error Wrong bus error e Both bus error Response time error 112 FEATURES Memory mapped real time VXI interface e VXI Interface Slave A32 or A24 D16 2MByte of RAM Two Vectored VXI Interrupts 1553 data protocol managed by micro controller providing flexibility extensionibility Error Injection all 1553 lines External Triggers Internal Self tests UM10936 Revision C 10 113 STORAGE DATA As the VXI 2800 contains electrostatic sensitive devices ESD s special storage and handling is required Do not store near electrostatic electromagnetic magnetic or radiation fields 1 14 TOOLS AND TEST EQUIPMENT No special tools or test equipment is required to test the VXI 2800 1 15 SAFETY PRECAUTIONS Operating personnel must observe safety regulations at all times refer to the Safety Summary at the front of this manual WARNING UM10936 Revision C 11 NN g
78. y the value of the first 1553 RX data word offset gt Reserved MRT 02H DDB address UM10936 Revision C 43 5 3 3 Data Buffers Data buffers are pointed to by the buffer address word contained in the data descriptor blocks The address of the toggled buffer is calculated by adding the global toggle offset to the data buffer address value in the DDB The first two words of a data buffer are updated with the value of the local clock at the beginning of the message LS data buffers can be stored as follows e The standard way data words behind the time tag words e A particular way allowing the user to store header words of the data message in a different buffer from the following data words The header option and the number of header words are defined in the option mask Header Address Header Message K Data Message K Header Message 2 Data Message 2 Header Message 1 Header Word Data Message 1 Time Tag 1 2 Time Tag 3 Time Tag 4 Data Buffer Address Data Data Note For standard 32 bit clock modules Dat the data buffer time tags are 2 words DE ata UM10936 Revision C 44 DB ADDRESS 1553 BUFFER 00H Time Tag 1 02H Time Tag 2 04H Time Tag 3 06H Time Tag 4 08H Data 0AH Data 0CH Data 0EH Data 10H i with or without Header Word

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