Kontron User`s Guide
Contents
1. PEG TXP ii GND reo TXN il ew CT GND DE ume SEE GND MI PEG RXN 11 see TXP i2 ow PEG TXN 12 na 1 GND MI uomen MEE NM GND MI een o se6 mena oa reo TXN 13 na CT GND N se xp S GND NE xu se mena M ua PEG TXN i4 na 1 GND NM creen HEN GND Nee asia DO reais ow Dm PEG TXN 15 o A 1 GND ME Resi SERIE CLKREQ DE PEG RXN I5 PERDE NC MA w O ECTS 7 5 Plex Users Guide KTD NUS toa Page 49 Connector Signal Decir 8 2 PCIex4 J6 The PCIex4 4 lane PCI Express is avallable through a PCIe x16 slot and support PCIe 2 0 The slot can be used for external PCI Express cards inclusive graphics card The slot is located nearest the CPU of the board Maximum theoretical bandwidth using 4 lanes is 4 GB s Note Type Signal Signal Type Note ma 0 GND via 0 ohm __ o 12V O cHOV 12V _ 12v gt SS GND GND as SMB_CLK AC ag SMB_DATA No O E GND CC ma ea as 3V3 NO MEME NENNEN NC 133 mA SB3V3 WJ 0 0 av3 EZ WAKE OR EE w w EA SND TT as EBENE casca see me EMMA oreca Dm seco EO e A ee B16 A16 PEG RXP 0 SERE EN DENEN CLKREQ B17 A17 PEG RXN 0 ZEE NNI cp A3s BEEN PEGTXP 1 BERS o0 recu ABM o aw ERA non O2. ERA sn Dm me mor Elm seen E o ew gt gt gt gt gt se lo ERA memo Dm ee BEM w O rw mw ED ao 0 ww gt gt gt gt gt sea Dl nc RE Pre RxN 3 J O Des EA w DERA st Ne 2 oO wc 11 BEM _ O GND BEES 9 o0 w BEHESM we we ER o0 AR 00 ECTS 7 5 Plex Users Guide KIDENO SZT ECTS 7 5 Plex Users Guide KIDZNOC 208 Page 51 Connector Signal iDan 8 3 mPCIe connector J38 The mPCIe mini PCI Express port is PCIe 2 0 compliant and it supports USB port USBZ Header Pin Signal Description E a Pin Signal Description Type 1 Wake Wake event s 3 7 SS Peyo PWR 3 wc Ne 4 Gd Ground PWR 5 we we 6 1 5v Power 1 5v PWR loe I Na ope gee tafe ee e Ground nta ore li mea 12 ono PCIe pso 14 N C NC clock pis nc ne o i ICA IC E ELLE LMR W Disab Wireless 2 PE_RST PCIe reset 0 3 3 PCIe 23 PE RX IBF 24 Power 3 3V PWR receive receive 120_CIK 120 clock 0 3 3 fame aie lele eee E o rom m mnm Dn 98 around em NE Z W Power Power 3 3V 3V PURO Ground lie TAM 2 e ds cod croua rm 44 we ne 45 nc Im wc me 47 nc Nc 48 1 5v Power 1 5V PWR as mc ne 50 Gnd Ground em o
3. fo aw PHR ror apis For 33 3v Rp or apii or aw Pak apo tor c 850 FDS sv Pak anos For O anos cor aw ewm O avo ror amoo ror sv 1 0 BMR REO64 ror 5v erp E52 E53 E54 EOS E56 ENT E58 ES E60 E61 en EE Ran ELE Users Guide KTD NOS Rea Page 54 Connector Signal De REMES 8 5 1 Signal Description PCI Slot Connector SYSTEM PINS CLK Clock provides timing for all transactions on PCI and us an inp ur to every PCI device AIl other PCI signals exceor RST INTA TINIB INTER and INTD are sampled on the risingedge or CIK and all other timing parameters are defined with respect to this edge PCI operates ar 33MBz PME Power Management Event interrupt signal Wake up signal RST Reset is used to bring I specific regi ciers Sequencers and signals co a consistent state What effect RST has on a device beyond the PCI sequencer LS beyond the scope or this specification except Fer reset States Of trtegquired PCT coniiguration registers An im ISS cee ed al RI o tput signals must be driven Lo thelr benign state In general ihis means they must be asynchronously tri stated SERR open drain 15 float d REO and CND musti both los ri stated they Cannot be diiven low or Migh during reset To prevent AD C BE and PAR signals from floating during reset the General resource may drive these lines during re
4. o lt _ lt _ c pm o pm oo P12 FLS ETZ EI3 aw eng Gw ew NC HACES oco or mm wo o cmo en cw 1 REoo em sv 1 0 or a sor a eae cx eran ror ams em sw ror cre ear cx or avi ror amis pm sw p ror api ror cre pm cw sor mr _ pm 3 3v ror pevseLf pm cw __ ror roca ror FERRE _ en wo roc sm DO fem sor c seif or apra pin or api p ror apro o cw or ap ror ap en wo sor aps ror avos eng cw o ror api PWR 5v G 0 aor ack a pm ev PLS F16 RANY FIS FLO E20 ZA P22 T23 F24 525 F26 P27 E28 B He BEL BE RZE F34 ESS B36 Bow ESB F39 F40 EA F42 F43 F44 F45 F46 F47 F48 F49 T92 TSS F54 ESS F56 BSW E58 Hog F60 Bow Bas ELE E17 E18 ETO E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 ESI E32 E33 E34 ESO E36 E37 E38 E39 E40 E41 E42 E43 E44 E45 E46 E47 E48 E49 ns MEN sv 1 0 ewr Gwr0 1 amp OT Gao Pag mes 1 ano or 33 3v ar ando rompo apz6 ror aw e A4 For enre or Pew ana cor Ap20 aor enD PWR apie xor adro sor 33 3v BMR FRamsf ror _ GND BAR TRY ror aw ewm story sor av PMR spoE to sso amp
5. Not verified S5 GEOVA Available Temperature Sensor cable kit for System Fan Temperature Cruise selected im BIOS ECTS 7 5 Plex Users Guide KTD NUS Woo Page 44 Connector Signal Decir Based on Maxim DS18B20 Accurate to 0 5 C over the range of LO LO Too Feature connector 3 3V Pin 9 GND Pin 19 and GPIO16 Pin 29 MPE RRA 4 v WELLE Y qa M PR A i Gl I I YY Z m rpm m A PN1053 4925 Cable Temperature Sensor 44P 400 mm ECTS 7 5 Plex Users Guide Q FU H O gS GO IND KTD NiOie ZSS Page 45 Connector Signal Deramas ae GPIO in more details The GPIO s are controlled via the ITE IT8516F Embedded Controller Each GPIO has 100pr to ground clamping Diode to 3V3 and has multiplexed functionality Some pins can be DAC Digital to Analogue Converter output PWM Pulse Width Modulated signal output ADC Analogue to Digital Converter input TMRI Timer Counter Input WUI Wake Up Input RI Ring Indicator Input or some special function J D a Q H HH O ct O 5 Signal IT8516F pin name Type GP100 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIOLO R f LD GERI BCE ACEJE ae NTE eserved used for MOLTO GP1O12 GPIO13 GPIO14 GPIO15 GRE NOMS TMRI1 WUI3 GPC6 ET COS GPIO17 L80HLAT BAO WUI24 GPEO 04 04 IS IOS Feature Break out board O1 Optionally for Cable Temoste cue Senso PT Ae CET wy ey AM J Ax a gt CH S eae
6. RxD WEED ars o po Oo tx gt EMBA crs 1 _ po O DTR BERM Br t LER GND MEA sv l em 1 Note 1 The COM1 and COMA 5V supply is fused with a common 1 1A resettable fuse The typical definition of the signals in the COM ports is as follows Transmitted Data sends data to the communications link The signal is set to the marking state 12V on hardware reset when the transmitter is empty or when loop mode operation is initiated Recelved Data receives data from the communications link Data Terminal Ready indicates to the modem etc that the on board UART is ready to establish a communication link Data Set Ready indicates that the modem etc is ready to establish a communications link Request To Send indicates to the modem etc that the on board UART is ready to exchange data Clear To Send indicates that the modem or data set is ready to exchange data Data Carrier Detect indicates that the modem or data set has detected the data carrier RI Ring Indicator indicates that the modem has recelved a ringing signal from the telephone line Available cable kit DB9 adapter cables PN 821017 100 mm or PN 821016 200 mm O ECTS 7 5 Plex Users Guide KTD NUS SST Page 37 Connector Signal Decir 7 8 LPC Connector J29 The LPC connector is unsupported The connector is type Foxconn HCLIIOI PO cr similar Ioh Io Typ R Signal ISO Cs REG L FRAME LPC RST L
7. including circuits and or software described or contained in this manual in order to improve design and or performance Specifications listed in this manual are subject to change without notice KONTRON Technology assumes no responsibility or liability for the use of the described product s conveys no license or title under any patent copyright or mask work rights to these products and makes no representations or warranties that these products are free from patent copyright or mask work right infringement unless otherwise specified Applications that are described in this manual are for illustration purposes only KONTRON Technology A S makes no representatlon or warranty that such application will be suitable for the specified use without further testing or modification Life Support Policy KONTRON Technology s PRODUCTS ARE NOT FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL OF THE GENERAL MANAGER OF KONTRON Technology A S As used herein Life support devices or systems are devices or systems which a are intended for surgical implant into body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labelling can be reasonably expected to result in significant injury to the user A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to
8. 1 6 1 8 2 O Z Z 2 4 2 6 2 8 gt O 3 2 gt 4 gt 6 gt 8 4 0 4 Z 4 4 ECTS 7 5 Plex Users Guide KTD NUS Woo Page 42 Connector Signal Decime Notes Pull p TO SB3SV3 Pull up to on board Battery Not connected used for onboard feature Not supported BW ND HH Available cable kit PN 1052 5885 Cable Feature 44pol 1 tol 300mm ECTS 7 5 Plex Users Guide KTD NO Me Page 43 Connector Signal DSi ini co Signal Description CASE OPEN used to detect if the system case has been CASE Cem ocemec sxgmal s gustus 18 reacabls eo xv wey le used like a GPI when the Intruder switch is not required SMBC SUE Geo ei SMBD SMBUS Dota Signal S3 sleep mode active low output optionally used to S31 deactivate external system S5 sleep mode active low output optionally used to deactivate external system PoWeR OK signal is high if no power failures are PWR_OK dee ds moc che seme as thie O silcmal generated by ATX PSU ExTrerna l Scu OPERON For conne ting F terminal of an external primary cell battery 2 5 4 0 V terminal Het BAT connected co GND The external battery LS protected against charging and can be used with without the on board battery installed General Purpose Inputs Output These Signals may be controlled or monitored through the use of the KT API V2 Application Programming Interface Note GP1011 not available internaly used as 12V monitor
9. PCI SATA mSATA 8 1 PCIexl6 in x16 slot J7 The PCIex16 16 lane PCI Express is available through a PCIe x16 slot and support PCIe 2 0 The slot can be used for external PCI Express cards inclusive graphics card and dedicated TMDS passive card The slot is located nearest the edge of the board Maximum theoretical bandwidth using 16 lanes is 8 GB s Note Type Signal Signal Type Note RN PGND via O Ohm E ES E Do ax de gt ab Sie ik ae NEN sis Dara sense GND SCASCAUXSN o A ae mess Es Lo N SB3V3 WOJ 03 MAKE A gt gt MP M mm NC O ND o __ GND SCENE PCIE x16 CLKP 514 214 cie xie cinn E B15 ALS E A A GND B16 A16 Ro Sz a CLKREQ B17 A17 PEG RXN 0 un uu DO TERA ee ESTOS GND DEN ECTS 7 5 Plex Users Guide KT DANG ea 48 Connector Signal Definida CT GND EM epa Pp e GND EM noma A37 GND RJ 0GND GND REJ PEG RXP S A GND ai PEGRXNIS R GND EE GND SES GND NE sec ef GND NM rec ante RJ GND 4 6 GND om GND 247 see CLKREQ NI essa E ae GND W aw DT A5O NC EM GND GND AME PEG RXP 8 A GND ee PEG RXNIO Regi GND A55 O GD EEEE GND Rei PEGRXP 9 J NENNEN GND EE PEG RXN 9 o MD PEG TXP 10 DEEP PEG TXN 10 JD 0 JD GD E EE GND re xi E GND DE ue
10. PN 821042 Cable Front Panel Open End 300 mm ECTS 7 5 Plex Users Guide KTD NOS ROS Page 40 Connector Signal Definida 7 10 CPU System Fan Connectors J25 J24 The CPU Fan connector and the System Fan connector are identical 4 pin type connectors The type is Tyco 1470947 1 or similar Header Pin Signal Description Type gt TACHO Tacho signal I open drain Power 12V 4 en Ground PWR Signal Description UM PWM is output signal used to control the fan speed only for 4 wire Fans Tacho Tarcho input signal is used to monitor the rotation speed RPM Rotation Per Minute Prepared for to pulses per turn The CPU Fan BEN 1044 9447 can be premounted on the KTA75 Flex The fan is a 12V Ball Bearing type PWM O 100 control making speed in range 0 8000 RPM 10 Max startup PWM is 35 Power consumption up to 3 6W MTBF 70000 Hours 40 C ECTS 7 5 Plex Users Guide KTD NO 328 Page 41 Connector Signal De cm cc 7 11 Feature Connector J26 The Feature Connector is a 44 pin connector 2 mm pitch type Foxconn HS5422F or similar Pul Not 1 Ioh Io E E Ioh Io Not z 1 Signal PIN Signal 1 1 U D U D a DT Ut o REM oo 7 70 DEDI o W jm EB LE o com s m Pul I GE ol CEO CETO CEE E D 7 2 2 5 2 5 Z 7 2 D S 3 3 2 3 7 3 ES cup a cd 3 9 1 1 IL 1 1 ik 9 l 9 1 5 4 1 4 8 IL O IL 2 iL 4
11. Power Out lx PN 821401 Cable Bracket USB 10poled lx PN 1052 5818 SW Man amp Driver CD KA70M KTA75 ECTS 7 5 Plex Users Guide KTD gt NUS CC Page 59 Connector Signal De ini Appendix OS Setup Use the Setup exe files for all relevant drivers The drivers can be found on KTA7x Driver CD or they can be downloaded from the homepage http www kontron com For some OS like Win7 when installing OS via USB DVD USB Keyboard Mouse please connect the USB DVD USB Keyboard Mouse to USB2 0 ports only or disable USB3 0 in BIOS Corporate Offices Europe Middle East amp North America Asia Pacific Africa 14118 Stowe Drive 17 Building Bl ck Oskar von Miller Poway CA 92064 1 ABP Str 1 2007 188 Southern West 4th 85386 Eching Munich USA Ring Road Germany Tel 1 888 294 Beijing 100070 Dol 49 40 C1657 aces PUB Chana PE pupa Fax 41 858 677 Tel 86 10 63751188 Fax 49 0 8165 0898 Fax 86 10 83682438 Tt 219 rnfo8us kontron com info kontron cn info kontron com ECTS 7 5 Plex Users Guide
12. and optionally as a master Initialization Device select AES used as a chap select during configuration read and write transactions Device Select when actively driven Indicates the driving device has decoded aes address as the target of Ehe current access AS an inpur DEVSEL indicates whether any device on the bus has been selected Request indicates to the arbiter that this agent desires use of the bus Mails aS e pole Eo bd suena yet master has des om Nos macia MOUSE be tri stated while RST is asserted Grant indicates to the agent that access to the bus has been granted This TE E onm eo point Some ley master has es cm CONT mne must be ignored while RST is asserted While RST is asserted the arbiter must ignore all REQ lines since they are tri stated and do not contain a valid request The arbiter can only Perform arbitra Lion cues las idee A master must e ens c rs CNT while RST is asserted REOf and GNT are tri state signals due to power Sequencing requirements when 3 5V or 5 0V only add in boards are used with add in boards that use a universal I O buffer ERROR REPORTING PINS The error reporting pins are reguired by all devices and maybe asserted when enabled PERR SERR Parity error ie Only for the reporting Or data Parity rr ore Urina a eC I transactions except a Special Cycle The RES pin is cuU tained tims tare and must be driven active by the agent receiving data two clocks olloning the data when a data Ve
13. as type Pinrex 5SIZ2990 10GBE5 Or similar Two things should be considered 1 An onboard SPI flash coexists on the same interface lines You must disable this component with a 3 3V power connection to the ADDIN signal e g a short circuit jumper between pin 2 and 4 2 The four SPI lines are protected with an additional bus driver and the ISOLATE signal controls the output enable pin For normal operation this signal should be high Header Pin Signal Description Type ENE PWR 9 953 RE TE PWR 6 N C Not connected NC IRE NE 8 ISOLATE Disable the SPI interface 1 3 3 9 SPI MISO 10 3 3 PWR Signal Further description 3 3V Standby Voltage power line Normally output power but when Motherboard is turned off then the on board SPI Flash can be 3 3V power sourced via this pin The ISOLATE input active low is normally NC but must be connected to GND when loading SPI flash Power Supply to the Motherboard must be turned off when loading SPI flash The pull up resistor is connected via diode to 5VSB SOIL IPIE ECTS 7 5 Plex Users Guide KTOS N US me Page 36 Connector Signal BIS co 7 71 COM1 COM2 J23 J22 Two serial ports provide asynchronous serial communication via RS 232 interfaces The connector is type Pinrex 512 90 10GBE5 or similar The pinout of Serial ports COM1 and COM2 is as follows Note Ioh Iol Type Signal PIN Signal Type Ioh Iol Note DCD 1 2 DSR I
14. components like RAM mounted then relevant steps below can be skipped 1 Turn off the PSU Power Supply Unit Warning Turn off PSU Power Supply Unit befor configuring the board and do not hot plug power supply otherwise 2 Insert the DDR3 UDIMM 240 Pin module s Be careful to push it in the slot s before locking the tabs 3 Connecting Interfaces and PSU Insert all external cables for hard disk keyboard etc A display monitor must be connected in order to be able to change BIOS settings Connect a standard ATX BTX PSU to the board by the inserting power cables into 24 pin ATX and the 4 pin ATX 12V PWR plugs connectors 4 Power Button Turn on mains power to the PSU If board doesn t boot then PWRBTN IN must be toggled this is done by shorting pins 16 PWRBTN IN and pin 18 GND on the FRONTPNL connector see Connector description by use of a normally open switch etc 5 BIOS Setup Enter the BIOS setup by pressing the lt Del gt key during boot up Enter Exit Menu and Load Optimal Defaults Refer to the BIOS Configuration Setup section of this manual for details on BIOS Setup Note To clear all BIOS settings including Password protection activate Clear CMOS Jumper for 10 sec without power connected 6 Mounting the board to chassis It is recommended using screws with integrated washer and having diameter of approx 7mm Warning please notice that the board contains components on both sid
15. o mo em o gt gt gt e ne lese gt gt co n Note 1 Shared with Audio Stack connector in Rear IO area Signal Description Side speakers Surround Out Right Available cable kit AN PN 821043 Cable Audio Open End 300 mm ATL ECTS 7 5 Plex Users Guide KTD NUS ZSS Page 32 Connector Signal Decir 7 4 USB4 5 Connector J16 USB Ports 4 and 5 are available via Pin Row connector type Foxconn ROLLYSFERNPO or similar The USB4 port is controlled by a set of OHCI and EHCI controllers also shared by USB0 1 2 The USB5 port is controlled by a set of OHCI and EHCI controllers also shared by USB6 7 8 9 The OHCI controllers support USB1 1 Full Speed 12Mbps and Low Speed L SM5DS The EHCI controllers support USB2 0 High Speed 480Mbps j Description 5V always protected by separate 1A resettable fuse 5V always protected by separate 1A resettable fuse Notes In order to meet the requirements of USB standard the 5V input supply must be at least 5 00V The contacts for USB devices are protected and suitable to supply USB devices with a maximum input current of 1000mA Do not supply external USB devices with higher power dissipation through these pinsTo protect the external power lines of peripheral devices make sure that the wires have the right diameter to withstand the maximum available current to enclosure of the peripheral device fulfills the fire pr
16. zc euh Ex Tae TTE 1 TE AL VIE CZ LI LEJE LE ES M CZ Ris 55 a BIS a 3 3157 15 Tor r ney as Be nw wm S zy lo Thr Hdi TER Tad jud f at Jy WEM NN EDS 949 WSE Ta AN n Sat NY eh PN 820978 Feature BOB Break Out Board ETETO Plex Users Guide KTD NUS TEST Page 46 Connector Signal Decir 7 12 KBD MSE J27 Attachment of a PS 2 keyboard mouse can be done through the pinrow connector KBDMSE J27 type Molex 22 23 2061 or similar Both interfaces utilize open drain signalling with on board pull up The PS 2 mouse and keyboard is supplied from SB5V when in standby mode in order to enable keyboard or mouse activity to bring the system out from power saving states The supply is provided through a 1 1A resettable fuse Signal Signal Description Keyboard amp and mouse Connector KBDMSE Signal Description MSCLK Bi directional clock signal used to strobe data commands from to the PS 2 mouse Bi directional serial data line used to transfer data from or MSDA T commands to the PS 2 mouse KDBCLK Bi directional clock signal used to strobe data commands from to the PC AT keyboard KBDDAT Bi directional serial data line used to transfer data from or commands to the PC AT keyboard Available cable kit PN 1053 2384 Bracket Cable 6 Pin to PS2 Kbd Mse ECTS 7 5 Plex Users Guide KTD NUS mo Page 47 Connector Signal DEB 8 Slot Connectors PCI Express miniPCIe
17. 16 NG J36 CORE KBD MSE J27 DP1 J43 ETH1 USB6 USB12 J14 USB10 J15 Lineln ETH2 USB7 USB13 J14 USB11 J15 LineOut J8 USB8 DPO J4 DP2 J3 Mic USB9 J40 J20 KTD NUS ZST Page 19 Connector Signal Decimas 5 Connector Signal Definitions The following sections provide pin definitions and detailed description of all onboard connectors The connector definitions follow the following notation COM Description Name Shows the pin numbers in the connector Sal Cae AL The macmonic nane Or the signal ar the current pin Te notation 7 states that the signal s active lew S AI eroga Input AO Nato Ob one ds Pic ci e TOS PI MESININEUENSCUEZNE Obs lobe Open Diseia ODE S pitone sn Gurone DSO DEGFEC NERNN S aea ae Ouest villa compliance signals on two paired wires Dol Dicci Silene inc aut Galicia comal ome ne suey Signals on two paired wires D SXOR uiuere Siceneline inane Ouroms eomoimec DSO and DSI PWR IONS Supply Of cpronmpo Tere enee oa NES Pin Not Connected Aclelicional notations o 0 5 05 oignal volta e level e g d d opcs signal voltage decor os bo e Hev signal voltage level e g TO 1 8 Loja Lou Ion oe US eN AOS our or OE OA through a grounded load while the output voltage has high level Todos palesi Current In mA Cloro lero cud ouBobie pia rom a VCC connected load while the output voltage has low level The abbreviation tbd is used for specificatio
18. 2 USB3 0 Connectors USB10 USB11 USB12 USB13 J15 J15 J14 J14 The USB3 0 connectors are based on standard USB3 0 connectors type Lotes ABA USB 104 K01 or similar Thease 4 USB3 0 ports are controlled by the xHCI controllers supporting USB3 0 USB2 0 and USB 1 1 Super Speed 5 0Gbps High Speed 480Mbps Full Speed 12Mbps and Low Speed 1 5Mbps USB Ports 10 and 11 mounted on top of the DP 2 port Note Type Signal IN Signal Type Note Lars eue b 5V SB5V MINI CND O T a amp USI METE SB5V ER Guo NEN DU EE pe mm Um Signal Description UOB TOT VOROS RX TOF RXTOS PXO T TU USEM USBL ROGER qoo oc i Differential pair works as Data Address Command Bus 5V supply for external device SB5V is supplied during powerdown to allow wakeup on device activity Protected by current limited power distribution switch 1A for each DOUE 5V SB5V ECTS 7 5 Plex Users Guide KTD NOS E Page 24 Connector Signal Deramas ERa USB Ports 12 and 13 mounted on top of the DP 0 port Note Type Signal IN Signal Type Note WW A NEA P END EE c gt E D E a gt gt E E L IGND JE RX13 TX13 ERI PWR KEK A Signal Description WSELZE USB IOS IZ RX pi TIL USBL USBI OS PAET RXI eles ete EXIF Differential pair works as Data Address Command Bus 5V supply for external device SB5V is supplied during powerdown to allow wakeup on dev
19. 460H APU 35W palcos MG NM Cs esa Duel Cone Ss coz aaa Copos Compatible with Existing 32 Bit x86 and 64 bit AMD64 Code Base AMD64 64 bit ISA High Performance Floating Point Unit SSE 4 1 amp 4 2 EE LO gil ABS QE MA Secure advanced Virtualization Features 64 bit DDR3 SDRAM Controller 1333MT s 666MHz PC3 10800 7 GQ ORI SOON ECCO Compi rant Wael VEDERE ii Rs as SIDA pe cio ion Nor In DRE moecwules not validated PCIe Technology Integrated Memory Controller Integrated Graphics AMD Radeon HD 7000G Series ene solte c Dedicated graphics memory controller 2D Acceleration Features Open GL 4 2 amp 2 0 DirectX 11 compliant 3D Acceleration Features Adaptive Anti Aliasing Shader Model 5 Motion Video Acceleration Features Dedicated hardware UVD 3 for H 264 Me Divx and MPEG decode nai rapa nda ae Some eme Eroe ora supported on DisplayPort Interface Digsoley Rome Ll Support DVI HDMI via passive adapter ECTS 7 5 Plex Users Guide KT Dente wae System Specifications Companion AMD A75 Hudson Fusion Controller Hub Device Unified Media Interface UMI 5 0 GT s IX dE lpge1cess 2 0 Cine roler Ci Ose PUS C On Tr oier USE Con ve Oul dice altel wie USER SMBUS e omiso lle SATA Controller with RAID 0 1 10 support High Definition Audio Real Time Clock RTC Integrated Clock controller DTE 0 eee noe Memory Memory controller is integrated in the AMD eTrinity FS1r2 UIC pain Pro eso IPSC LURES Bee Cometa erica E DEC
20. 5a ve nc 52 3 3V Power 3 3V PWR ECTS 7 5 Plex Users Guide KITD NO SC 20 Page 52 Connector Signal De ini 8 4 mSATA mPCIe Connector J43 da The mSATA mPCIe interface comply with SATA 3 0 and it supports USB port USB2 Header Pin Signal Description Type Pin Signal Description Type 1 Wake Wake event E 2 Sic Or Ponce PWR pe gt epa es ses ar ce e pae Dame ee sen ein we ue EEE oso 14 wc xe asf ca Ground E ie we foe LIN a Wireless 19 W Disable 0 5 disable SAS Se IO Power 3 3V receive AA SRI RE Gnd Ground receive S ATA E M SEA xe TAC DES data transmit S ATA SIA TUE Greene ensima se FIE DIS IE OI aa ae ae Ta EN M GS Sel SATA ee me FE ee SLE som Ga Ground ena SOM Power 3 3V PWR EB SE pe sp 30 uses EA Gs E E m par ES mau ES EN ZER z ES ECTS 7 5 Plex Users Guide KGB NOS ET Page 53 Connector Signal Decime 8 5 PCI slot connectors J18 amp J28 KTA75 Flex support 2 PCI slots PCIO PCI1 J18 J28 Terminal Note Type Signal a inos EBM Ka S FO F02 FQ3 F04 F05 FO6 FO F08 BOS BAe Signal Type Note rRsr Of nov ewm ms o or o 45v pak iwm 1 iw 1 5v mr ae sv 1 0 BAR C EO1 EZ EOS E04 E05 E06 EQ E08 HO ELO NC
21. Connector J17 The KTA75 boards are designed to be supplied from a standard ATX or BTX power supply Use of BTX supply is not required for operation but may be required to drive high power PCIe cards ATX BTX Power Connector J17 3V3 12 Pay 11 lhi 10 0000191 e o aleje e e e o e e o e Note 1 5V supply is not used on board See chapter Power Consumption regarding input tolerances on 3 3V 5V SB5V 12 and 12V also refer to ATX specification version 2 2 Signal Description P OK MOI 1S E exse o ds nes ond dos esee nba lO vie persi sup ly m to andicate Chat he sVDC and 13 5 PC ur PuES are above che Undervolleage thresholds of the power supply When this signal is asserted high there should be sufficient energy stored by the converter t guarantee Continuous power operation within specification Conversely when the output voltages fall below the undervoltage threshold or when mains power has been removed tor a EMME smi turc mdi ong so that power Sli operation 5 no longer ene cum c co E OR cromada Pe desassercca ro al low Ss eae he recommended Seo ee a ramas casacca Om das I ON Ms COM signal esee provided in the ATX12V Power SupplyDesign Guide It is strongly recommended to use an ATX or BTX supply in order to implement the supervision of the 5V and 3V3 supplies These supplies are not supervised on board PS_ON Active low open drain signal from the board to the power supply to turn on
22. E SW powerdown to allow wakeup on USB device activity Protected by individual resettable 1A fuse Notes In order to meet the requirements of USB standard the 5V input supply must be at least 5 00V The contacts for USB devices are protected and suitable to supply USB devices with a maximum input current of 1000mA Do not supply external USB devices with higher power dissipation through these ECTS 7 5 Plex Users Guide KTD NUS ZE Page 27 Connector Signal Decime pinsTo protect the external power lines of peripheral devices make sure that the wires have the right diameter to withstand the maximum available current to enclosure of the peripheral device fulfills the fire protecting conditions of IEC EN 60950 ECTS 7 5 Plex Users Guide KTD NUS O Page 28 Connector Signal Decir 6 5 Audio Interface J40 The on board Audio circuit based on Via VT1708S implements 7 1 2 Channel High Definition Audio with UAA Universal Audio Architecture featuring five 24 bit stereo DACs and three 20 bit stereo ADCs The Following Audio connector is available in IO Area Audio Speakers Line in and Microphone are available in the stacked audiojack connector type Lotes ABA JAK 028 K03 Signal Type Note Signal Description Eroni Pi Speaker PEONES OUTS wie lect Front Speakers Speaker PRONTA l ECTS 7 5 Plex Users Guide KTD NOS ZST Page 29 Connector Signal DEBET 7 Pin Connectors 7 1 DC Power ATX BTX
23. Green Speaker Pink Mic Audio Audio Pin header J41 Line out Line in Durr ound Cmeouc 2 DE Ma Caf BAGS each IS ONE Microphone MICI SPDIF OUT electrical Interface only LAN Two RJ45 connectors J8 in REAR 10 area 2 10 100 1000mbite DAN c Cea eta Ucing Intelile Pearsonville xGB PCI Express Ethernet controller WGI211ATSLJXZ PXE Netboot supported Wake On LAN WOL supported USB MUSAS AS O DIS EIS c 0 Axe UOB OTa Erone panel T COn e CEO o ZS 0 a MUSE een NU E onne rodas AZ USB2 0 USB stack JO in REAR IO area gt USB 2 507 U E a Qr Richie USE eese T dia TR EART ve USB 2 0 U e 0 leme Dels Steck gls lin REAREN SE O aim ee so DE lx USB 2 0 in mSATA mPCIe socket J43 Serial 2x RS232 pin header 12V 12V supply generated by driver DOME cala eai CON soin UL COM Zoe S an Mon uU 7 HZ esum e 20 ECTS 7 5 Plex Users Guide KTD NOE RES System Specifications FAN CPUFAN 4 pin row J25 12V PWM SYSFAN 4 pin row J24 12V PWM IE ile 6 Pili exor Ifagioo heel Mouse 282 calle Kite abate dede Sues 27 Kbd Mse Power 1x 4 pole Internal connector J19 ATX core power Pug 12V Single Supply Max 260W lx 24 pole connector J17 ATX BTX power Battery Exchangeable 3 0V Lithium battery for on board Real Time Clock and CMOS RAM Manufacturer Panasonic Part number CR 2032L BN CRADSAN BN e CR 72067 SER Approximate 6 years retention Current draw is 4 pA when PSU is disconnected and 0 pA in SOME ere CAUTI
24. IONS 1 ov ana DRESS 1 25 SDRAM not verified specifications Supports DDR3 UDIMM 240pin Using up to 8GB DRAM technology DIDIRS LISS JE QI s MC 351060107090 3129090 From 1GB to 2x 8GB maximum 16GB in total Notes Less than 4GB displayed in System Proportii o nc INE Shared Video Memory PCI resources is subtracted Rec oppone Flash SENIO sil Miles seo Cell Suse OS c BIOS Security Intel Integrated TPM 1 2 support NoE Sine SS 2 MRS INPS SINO KT Feature Connector Embedded IS Mica Ses CPTO IAC EDO IE MIHI e MES Possible I gt GPTO expansion Software Watchdog Audio Audio 7 1 Channel High Definition Audio Codec using the VIA VT1708S codec Seriel A exec SUP EG I ATA lx mSATA J39 mechanically sharing space with mPCle slot ISO o EN Wee ee ROMERO AS o pole solace O USE HOD IED or RoT SUSA IAN AUDIO Line MIC PCT DOGE CIRO ESPOSA RES ub COTES m zbie 3382 Controlle i ECTS 7 5 Plex Users Guide KIDO E System Specifications PCIe Ieri preo cd ON MON Ix PCI Expreso xI olot In mechanically xlo sito E Jos gie TOT ota Sie 1x mPCIe mSATA J43 mechanically sharing between mSATA and mPCIe The mSATA interface will be selected when a mSATA card are inserted into the mPCIe socket J43 Dot ere eye o exe Dits play e ore eon ceo RE ARCORE PL DP1 J43 DES DPO J4 Opre rono ole Onea acia dba a Saa T Or E Opt rona My Ao OO eroe TBI Audio 3x Audiojacks stack J40 in REAR IO area IGR Blue Line In
25. N US ARA Page 56 Connector Signal DSi imi con to the operating system does so anytime SERR is sampled asserted INTERRUPT PINS OPTIONAL Interrupts on PCI are optional and defined as level sensitive asserted low negative true using open drain output drivers The assertion and deassertion of INTx is asynchronous to CLK A device asserts its INTx line when requesting attention from its device driver Once the IN signal is assediare asserted until the device driver clears the pending request When the request is cleared the device deasserts its INTx signal PCI defines one interrupt line for a single function device and up to four int o rrupt lines For a multi function device or connector For a single function device only INTA may be used while the other three interrupt lines have no meaning INTA aceea A dle used CO ea Aa Lala oe MOBELZEUMCE Te be dentes rullino nd eS s mulcei funcectcion device ECTS 7 5 Plex Users Guide KTD NUS O Page 5 7 Connector Signal Decimas 8 6 SATAO SATA1 SATA2 SATA3 SATA4 amp SATA5 J12 J13 J9 J11 J10 J39 The six SATA ports comply with SATA 3 0 and supports IDE emulation mode AHCI Advanced Host Controller Interface 1 3 mode and RAID mode RAID 0 RAID 1 and RAID10 across all 6 ports The SATA 3 0 supports transfer rates up to 6 Gbit s but also SATA 1 0 and SATA 2 0 transfer rates are supported 1 5 Gbit s and 3 0 Gbit s respectively The S ATA i
26. ON Danger of explosion if the battery is incorrectly replaced Replace only with the same or equivalent type recommended by the manufacturer Dispose of used batteries accordance Sins GUSERONS s Speaker On board Speaker Piezo On board speaker Electromagnetic Sound Generator like Ay con RY OSTE ECTS 7 5 Plex Users Guide KT Dente E System Specifications Environme Neal Operating ORC OC per aena Ee pe ebbe ibo eol ae aan JE Le the customer s responsibility to provide sufficient airflow around each of the components to keep them within allowed temperature range 10 90 relative humidity non condensing otorage OC qoc des oe oc ete meras cara y special nie saio oil on board RAS a Sia Board with battery has been verified for storage temperature down to 40 C by Kontron 5 95 relative humidity non condensing Electro Static Discharge ESD Radiated Emissions EMI All Peripheral interfaces intended for connection to external equipment are ESD EMI protected ENSC LiCl 2 8 2000 SD ida ENSS022 908 class B Cenerilc Emission Standard Safety AN SOS 1s 2006 lil 82009 Aa ZOMO BEA ZIO IEC Oe S10 exe 2 CSA C2252 Nos S0G5 0 1 Product Category Information Technology Equipment Including Electrical Business Equipment Product Category CCN NWGQ2 NWGOS Eile number Jed 94252 Jt 94 2 52 CE I Theoretical MTBF S14 614 153 436 homes E 40 0 7 699 Recetr ic ion ol lazardonE NI S
27. PC AD3 SMB CLK O Ne G 0 AAA l FJ po ECTS 7 5 Plex Users Guide KID NO m a Page 38 Connector Signal Deramas cc 7 9 Front Panel Connector J5 The Front Panel connector is a 24 pin connector type Wieson G2120HT0038 016 or similar rg rg rg zi O A A A SES AGND MECZE ft PWR AI PT Tt LL LL Bl DO ct DOBE i E N N J AS 0 O ct KTA 7 5 7 EIS Users Guide KTD NOS Ca Page 39 Connector Signal De Massas Description 5V supply for external devices SIMON abs Ssijoollasel during powerdown to allow wakeup on USB device activity Protected by independed resettable 1 1A fuse Universal Serial Bus Po 0 Differentials Bus EE B0 USBO USBO pensa sea cde Mmi e Jus Universal Serie Bus Port 1 Bitrerencaa ls EEE USB1 USB1 Data Address Command Bus Maximum load as IA aie wSilimcg IIDC Conmmeceeic vo 25 li USMC Crimp Siglas ls USO SUSE ny SATA LED SERRE Ce ED ceo sto melo Role le when passive SUS LED Suspend Mode LED active high signal Output 3 3V ni via 4700 Power Button In Toggle this signal low to start the ATE ATX BTX PSU and boot the board Reset Input When pulled low for a minimum 16ms the RSTIN reset process will be initiated The reset process continues even though the Reset Input is kept low Note In order to meet the requirements of USB standard the 5V input supply must be at least 5 00V Available cable kit
28. cause the failure of the life support device or system or to affect its safety or effectiveness ECTS 7 5 Plex Users Guide KTD N0876 0 General Informate KONTRON Technology Technical Support If you have questions about installing or using your KONTRON Technology Product then check this User s Manual first you will find answers to most questions here To obtain support please contact your local Kontron Sales Partner or Kontron Field Application Engineer FAE Before Contacting Support Please be prepared to provide as much information as possible CPU Board KTATS Flex P N i NIBININNINIKHI 66110000 1 Type and P N Part Number find label like Prod code 440 S N III MIHI REINO UNII 01148401 2 S N Serial Number find label like Configuration if relevant 1 CPU Type and Clock speed 2 DRAM Type and Size 3 BIOS Revision find the version info in the BIOS Setup Menu 4 BIOS Settings different than Default Settings System if relevant 1 08 Operating System Make and Version 2 Driver Version numbers Graphics Network and Audio etc 3 Attached Hardware Harddisks CD Rom Display Panels etc ECTS 7 5 Plex Users Guide KTD N0876 0 General Informate Warranty KONTRON Technology warrants its products to be free from defects in material and workmanship during the warranty period If a product proves to be defective in material or workmanship during the warranty period KONTRON Tech
29. em Fan Connectors J25 ULA orinar 40 B GENESACOMIEGCOE J20 airline bibi bra RES e da 41 IS SAA ES ee RE mu xS PU NN RENS 46 Slot Connectors PCI Express miniPCIe PCI SATA b Bae ce nee eee DE iran 4 POr elo xn ZR SLOC OD saran ee ee eli 47 PCIex4 IL d 49 nP CONNECTED A930 3 885 5 3 2 AA A do e d d rident 5 od MES mecis Connector qud assi 5 2 9 5 E P 4c rar te ER TP a aaa a 52 ETE Ss FLS Users Guide Table of Contents PES PCI slot Connectors JLS amp 3429 rro AA SD 8 6 SATAO SATA1 SATA2 SATA3 SATA4 amp SATA5 J12 J13 J9 J11 J10 i39 DJ AppPendi s Mating COND OCOT ibas ess ESA e fo Roc nao AR ahead 29 ETE US CTI Users Guide KTD N0876 0 General Information Document Revision History Date Rev PS uu od Mar 21 2013 osi me voy Vere Lo OA ys Eles Copyright Notice Copyright 2013 KONTRON Technology A S ALL RIGHTS RESERVED No part of this document may be reproduced or transmitted in any form or by any means electronically or mechani cally for any purpose without the express written permission of KONTRON Technology A S ECTS 7 5 Plex Users Guide KTD N0876 0 General Informate Trademark Acknowledgement Brand and product names are trademarks or registered trademarks of thelr respective owners Disclaimer KONTRON Technology A S reserves the right to make changes without notice to any product
30. er Converters it is possible to implement a mix of DP VGA HDMI and DVI D outputs and still support 3 independt display configuration Avallable DP adapters 1 DP to VGA DP to HDMI DP CO DV I PN 1045 5779 EN 1045 5791 PN 1045 5780 DP Extention Cable g In order to prevent mechanical conflicts the above DP adapters can be connected to DP 0 DP 1 and DP 2 via the 1051 7619 Cable DP Extender cable 200mm The DP to VGA adapter is an active converter meaning that seen from the graphics controller it looks like a DP The HDMI and DVI converters are passive converters meaning that they inform the graphics controller about its type and the graphics controller then replace the DP signals with TMDS signals used in HDMI and DVI The HDMI interface supports the HDMI 1 4a specification including audio codec Limitations to the resolution apply 2048x1536 VGA 1920x1200 HDMI and DVI 4 independt simultaneously displays without using PCIe Graphics cards is a possible configuration under the following conditions 1 A PCIe DP passive card must be used in the outermost PCIe slot 2 All DP must be converted to DP DVI D or DP HDMI via passive adapters like above adapters Restriction only one adapter can be HDMI type 3 Two of the panels must have the same timing meaning two display monitors have to be exact same type ECTS 7 5 Plex Users Guide KTD NUS ZST Page 23 Connector Signal Decime 6
31. es make sure that the wires have the right diameter to withstand the maximum available current to enclosure of the peripheral device fulfills the fire protecting conditions of IEC EN 60950 ECTS 7 5 Plex Users Guide KT DENG Ro System Specifications For USB2 0 cabling it is required to use only HiSpeed USB cable specified in USB2 0 standard on Twisted Power Pair Polyvinyl Chloride PVC Jacket Red Veus Black Power Ground Outer Shield gt 65 Interwoven Tinned Copper Braid Inner Shield Aluminum Metallized Polyester HEH T Twisted Signaling Pair White D Green D 28 AWG Tinned Copper Drain Wire For USB3 0 cabling it is required to use only HiSpeed USB cable specified in USB3 0 standard UTP Signal Pair TO 19233 W DUC SDP Signal Pair Braid Power Jacket SDP Signal Pair Ground P 59 Plex Users Guide KTD N0876 0 Connectors hoes 101 4 Connectors Locations 4 1 KTA75 Flex Topview mSATA mPCle J43 EU y DALGGKAGGA AB si r a Dr power E Power J19 SATA4 SATA2 SATAO ATX BTX ATX core power SATA5 SATA3 SATA1 Feature J26 e IE LPC J29 mPCle J38 4 iz ci MANI MAT Rote Es E d gi NER NE COMI J23 med x 5 CPUFan J25 Ly SysFan J24 Frontpanel J5 COM2 J22 PClex4 J6 II x1 6 slot ae n e PClex16 J7 HE ir Ri epr x16 slot PCI 32b J18 PCI 32b J28 DM e NE AlwaysOn J37 p ClearCMOS J34 USB4 5 J
32. es of the PCB which can easily be damaged if board is handled without reasonable care A damaged component can testi in Meine or MO videro ele cull De mor use INI ex Users Guide KTD NOQS m 2 2 Requirements IEC60950 Users of KTA75 should take care when designing System Specifications chassis interface connectors in order to fulfil the IEC60950 standard When an interface or connector has a VCC or other power pin which is directly connected to a power plane like the VCC plane To protect the external power lines customer has to take care about Tele tae uices leve available power That the enclosure of the peripheral device fulfils of the peripheral devices the suitable rating to withstand the maximum the fire protecting requirements of IEC60950 Lithium battery precautions CAUTION Danger of explosion if battery is incorrectly re placed Replace only with same or equivalent type recommended by manufacturer Dispose of used batteries according to the manuracrurer 5 rnstruce TIONES ATTENTION Risque d explosion avec l change inad quat de la batterie Remplacement seulement par le m me ou un type quivalent recommand par le producteur L vacuation des batteries usag es conform ment des indications du fabricant ADVARSEL Lithiumbatteri Eksplosionsfare ved fejlagtig h ndtering Udskiftning m kun ske med batteri af samme fabrikat og type Lev r det brug
33. ibes the KTA75 Flex family of boards made by KONTRON Technology A S These board will also be denoted KTA75 within this Users Guide The KTA75 is designed to support the listed APU variants uPGA 722pin processors and AMD A75 Fusion Controller Hub FCH A75 on a Flex form factor See the chapter System Specifications for more specific details APU variants AMD PN Processor data R 464L RE464LDEC44HJE ASA O ALS oll IN 60 RE460HDEC44HJE INCH O ECO 1 Sou RE272FDEC23HJE 2 7 GHz Dual Core 35W RE268DDEC23HJE 2 5 GHz Dual Core 35W Ersan h AMD R Garies 1640 The 4 versions have the same type of active CPU cooler the cooler is by default not premounted but can be ordered with this obtion Use of this Users Guide implies a basic knowledge of PC AT hard and software This manual is focused on describing the KTA75 board s special features and is not intended to be a standard PC AT textbook New users are recommended to study the Installation Procedure stated in the following chapter before switching on the power All configuration and setup of the CPU board is either done automatically or manually by the user via the BIOS setup menus Only exceptions are the Clear CMOS jumper and the Always On jumper ECTS 7 5 Plex Users Guide KTO NO m System Specifications 2 Installation Procedure 2 1 Installing the Board To get the board running follow these steps If the board shipped from KONTRON has already
34. ice activity Protected by current limited power distribution switch 1A for each PORES 5V SB5V Notes In order to meet the requirements of USB standard the 5V input supply must be at least 5 00V The contacts for USB devices are protected and suitable to supply USB devices with a maximum input current of 1000mA Do not supply external USB devices with higher power dissipation through these pinsTo protect the external power lines of peripheral devices make sure that the wires have the right diameter to withstand the maximum available current to enclosure of the peripheral device fulfills the fire protecting conditions of IEC EN 60950 ECTS 7 5 Plex Users Guide KID NOO EST Page 25 Connector Signal Decir 6 3 Ethernet Connectors ETH1 ETH2 J8 The KTA75 supports two 10 100 1000Mb Ethernet RJ45 connetors in a stacked dual LAN connector type Ude RMT 123AGF1F or sililar Both ports are driven by Intel Pearsonville WGI211AT PCI Express control les Ethernet connector 1 ETH1 is mounted above Ethernet connector 2 ETHZ Note LED N o ie ERRO bloc entes ralis LED Lights when ETH2 Link Flashing when activity lt A PSSE OI MDIO MDIO y MD IS MIDA MIEI MDT MDI3 A ISS In order to achieve the specified performance of the Ethernet port Category 5 twisted pair cables must be used with 10 100MB and Category 5E 6 or 6E with 1Gb LAN networks Signal Description MDI mode f
35. irst pair in 1000Base T i e the BI DA pair Phenom BATE AM 0 7 VOB MDI crossover mode acts as the BI DB pair receive pair Lia JE OO exe ne MDI 1 MDI mode second pair in 1000Base T i e the BI DB pair ji receive pair in 10 100Base T ECTS 7 5 Plex Users Guide KTD N00 20 Page 26 Connector Signal Decimas MDC IET MD Crossover modes cete as tme Bil DA oe ege ena erae pole in 10 100Base T mode cnird pair SS T i e che BIDO pair crossover modes acts es te BI DD pair mode fourth A MOSS i e the BI DDI Pair OYOSSOwer mode acts as che BI DC Dexr Note MDI Media Dependent Interface 6 4 USB x4 Stack Connector USB6 USB7 USB8 USB9 J20 USB Ports 6 7 8 and 9 are mounted in a single stack in the IO Area type Foxconn UB11123 Q8DF 4F or similar The USB ports are controlled by a single set of OHCI and EHCI controllers also shared by USB5 The OHCI controllers support USBl 1 Full Speed 12Mbps and Low Speed 1 5Mbps The EHCI controllers support USB2 0 High Speed 480Mbps Note Type Signal PIN Signal Type Note i 9 3 4 E __Q a gw PWR 5v sssv MZ cD PWR e A O eee ER av gt 0 mst0 3 3 usss uses BSIO 3 8 0 de DI A GEEK umi ART sv sesv MEN gt a psio 3 3 uss9 uses DSTO 3 3 Signal Description Differential pair works as Data Address Command Bus 5V supply for external devices SB5V is supplied during Shu SI
36. kontron za pz za A i e 4 7 Z iy S W f PG 4 Cee z A A 4 pn A 4 SA Table of Contents Table of Contents Br E N HS D OY OI N W w G OY O O OO 099999111 N oO A C N FF CO Y OO OO A CO aro obrero O PPE YNY s in L1atLoH PIOSSOD S uasa EA REOR ded RO m A da bI A EA 6 Inca lino Ene LO Lessa SEE SS arredo S Eu E 6 Requitrenents JROCO0 930 20 oa a WEG A A A A AAA RA a z SS 7 ORAZ Gp OL IC ete cease eee oe dera rico 8 COMPONERNE Mein Cele soe bees pt 8 Aliado Les Bce Diag saran 14 Doe PO ACIDA ee LORO 15 Contiene a OO ET 245 3 2229 2 24 2 E E E ee 18 ANEXOS E LS SENI isla a ae org E ie E a E ee ee eae es 18 Connescof Signal DEFTOATEDOOS scan das 9 4 9 eds 19 PASZE COZ 225230923 4 54x23 924 40 3 23 24 5 24 20 DisplayPort DPO DPI DP2 do IA J44 ub exu Eras woe dace X dedo Maas Se 20 USB3 0 Connectors USBIO USBIIZUSBIZ2 USBIS J157 J157 J147 TIA cion 23 Ethernet 4 ORMSCROF ZEDBISEIHE2 JO sii nati ia AR 25 USB x4 Stack Connector USBO6 USBIZUSBS USES9 020 z essaie ac REG 26 Lili Inf AO sori 28 Eun MS sali d nudno TRAF Connector dud seat abeo oe ce are REB b ROS CR REGEL PRO dll UBI O CISSE LS iena ati a2 tibet area td Hoo Ca V Le 34 DPI Connector 4021 sapete i 20 COMIACOME IM 3 5 murs e RUE rei hse eee be xb wi dS bi DPC CONAS OCOr a apatia ee 37 Erone Padel VISO 25 Loser ED PESO AD 38 CPU Syst
37. loves S sio PAR Parity is even parity across AD 31 00 and C BE 3 0 Parity generation is required by all PCI agents PAR is stable and valid one clock after the address phase For data phases PAR Ts stable and valid one clock after either IRDY is asserted on a write transaction or TRDY is asserted on a read transaction Once PAR is valid it remains valid until one clock after the completion of the current data phase PAR has the same timing as ADIDI 00l Dout it i gt delay by one colo ck The mater diives PAR for address and write data phases the target drives PAR for read data phases INTERFACE CONTROL PINS FRAME Cycle Frame 1s driven by the current master to am mecate ihe beginning and duration of an access FRANEK 1s asserted to indicate a bus transaction ais beginning While FRAME is asserted data transfers continue When FRAME is deasserted the transaction is in the final data phase or has completed IRDY Int ato Ready Indicates Ehe initiating agents bus masters ability To complete the current data phase ol the transaction IR 15 used in con une on with TRD A Jata phase is completed on amy Clock Doch IRDY and TRDY are sampled asserted During a write IRDY indicates that valid data aus present on AD 3s 00 During a read dt indicates the master s prcpared to accept data Wail cy loes are Insented Uni Dorth IRD ana TRDY are asserted together Target Ready indicates the target agent s selected de
38. nology will at its sole option repair or replace the product with a similar product Replacement Product or parts may include remanufactured or refurbished parts or Components The warranty does not cover l Damage deterioration or malfunction resulting from A Accident misuse neglect fire water lightning or other acts of nature unauthorized product modification or fallure to follow instructions supplied with the product B Repair or attempted repair by anyone not authorized by KONTRON Technology C Causes external to the product such as electric power fluctuations or fallure D Normal wear and tear E Any other causes which does not relate to a product defect 2 Removal installation and set up service charges Exclusion of damages KONTRON TECHNOLOGY LIABILITY IS LIMITED TO THE COST OF REPAIR OR REPLACEMENT OF THE PRODUCT KONTRON TECHNOLOGY SHALL NOT BE LIABLE FOR 1 DAMAGE TO OTHER PROPERTY CAUSED BY ANY DEFECTS IN THE PRODUCT DAMAGES BASED UPON INCON VENIENCE LOSS OF USE OF THE PRODUCT LOSS OF TIME LOSS OF PROFITS LOSS OF BUSINESS OPPORTUNITY LOSS OF GOODWILL INTERFERENCE WITH BUSINESS RELATIONSHIPS OR OTHER COMMERCIAL LOSS EVEN IF ADVISED OF THEIR POSSIBILITY OF SUCH DAMAGES 2 ANY OTHER DAMAGES WHETHER INCIDENTAL CONSEQUENTIAL OR OTHERWISE 3 ANY CLAIM AGAINST THE CUSTOMER BY ANY OTHER PARTY ECTS 7 5 Plex Users Guide KTD N0876 0 Introducir 1 Introduction This manual descr
39. ns which are not available yet or which are not sufficiently specified by the component vendors KTD NUS mo Page 20 Connector Signal Decimas 6 Rear IO Connectors 6 1 DisplayPort DPO DP1 DP2 J3 J4 J44 The DP DisplayPort connectors are based on standard DP type Foxconn 3VD11203 H7AB 4H or similar Pin Signal Description Type Note IT ooo mm ooo p eo a aa ab FE E des Internally pull down 1Mohm Aux channel on pin es selected as 15 Contato a Aa default when NC BBE hanne lon ora LI5 17 ALE LUB adapter used 3 3V Comune Not used O Internally connected to GND 15 AU Col a a AUX channel used by DP p Clk DDC Clk used by HDMI ECU EN ECTS 7 5 Plex Users Guide KTD NUS POST Page 21 Connector Signal Decimas m SASA AUX channel used by DP DDC para used os HDMI Data JE Internally pull down 100Kohm PWR Same as GND PWR Fused by 1 5A resetable PTC fuse Common Cor DIO meen DEI Note To protect the external power lines of peripheral devices make sure that the wires have the right diameter to withstand the maximum available current to enclosure of the peripheral device fulfills the fire protecting conditions of IEC EN 60950 ECTS 7 5 Plex Users Guide KTD NOS Goa Page 22 Connector Signal Deramas The 3 DisplayPorts DPO DP1 and DP2 can be used in 3 independt display configurations By use of DP Adapt
40. nterface is available through standard L type connector 7 pore Header Pin Signal Description Type 1 end Ground PWR com ome pe positive com pomme oe negative Ground DEM a negative EIENEW WEN positive Available cable kit PN 821035 Cable SATA 500mm ECTS 7 5 Plex Users Guide KTD NO SC M Page 58 Connector Signal De cmd co Appendix Mating Connectors The Mating connectors Cables are connectors or cable kits which are fitting the On board connector Onboard Connectors Mating Connectors Connector Manufacturer P N Manufacturer P N DLLO ABA USB 104 ETHI ETH2 RMT RMT 123AGF1F ze mmer Audio stack J40 Lotes A OS KOS 44206 5557 ABA POW 003 SOU 2045 USBA USB5 meme Tot jeu Foxconn HS1105F RNP9 RNP9 Pinrex S12 96 10GBE5 512 90 90635 COMI COM2 UU JJ Pinrex Hr Molex Ha ape ire Bosse on ci BO PO G2120HT0038 MM 47054 CPU Fan System Fan Ia ZS eo 1470947 1 Molex 1000 Pinrex mole NE Don Connex SIETE Feature J26 e al B md A 1 G Foxconn H85422F 0 Cable amp Driver Kit KTA70M KTA75 PN 826600 R11 contains 2x PN 621017 Cable COM 2 54mm 100mm lx PN 1052 5885 Cable Feature 44pol 1 tol 300mm 1x PN 1053 2384 Bracket Cable 6 Pin to PS2 Kbd Mse lx PN 821042 Cable Front Panel Open End 1x PN 821043 Cable Audio Open End ox PN 821035 Cable SATA 500mm lx PN 1052 5814 Cable ATX Power for KTA70M lx PN 1027 3669 Cable
41. otecting conditions of IEC EN 60950 ECTS 7 5 Plex Users Guide KT DENG RES Connector Signal Dei Available cable kit PN 821401 Bracket Dual USB Cable O e Y RT S ELE Users Guide KTD NUS SST Page 34 Connector Signal Decimas 7 5 Jumper area J34 J35 J36 J37 The KTA75 has a jumper area containing pin connectors 2 54mm pitch for up to four jumpers but normally only one jumper is used jumper in the J34 pin 2 3 position as indicated below Jumper in Pin Jumper in E Js position 1 2 P 2 z position 2 3 Always On EN A Normal Clear CMOS Clear CMOS WSUS PANICO Shore crente 336 Front Right Front Left test Not mounted Loss Ss E Clear CMOS is used to erase all customised BIOS settings located in the CMOS RAM storage If the board has a booting problem or is unstabile then Clearing CMOS by moving the Jumper from default position to the Clear CMOS position for approx 10 sec might solve the problem Audio Short Circuit Test is only used in manufacturing test No jumper should be installed Warning Don t leave the Clear CMOS jumper in position 1 2 otherwise 1f power is disconnected the battery will fully deplete within a few weeks ECTS 7 5 Plex Users Guide KTD NUS ZET Page 35 Connector Signal Decimas 7 6 SPI Connector J21 The RIA 5 provides one synohronous Tull duplex SPL serial Peripheral Interface Bus in a l0 pin header connector The connector
42. rity rror AES detected The minimim duration or PERR Iis one clock for each data phase that a data parity error He detected If sequential data phases each have a data parity error the PERR signal will be asserted for more than a single clock PERR must be driven high for one clock before being tri stated as with all sustained tri state signals There are no special conditions when a data parity error may be lost or when reporting of an error may be delayed An agent cannot report a PERR Until it has claimed the access by asserting DEVSELE for a target and completed a data phase or as the Master Cr che current EOOMSASEWONE System Error lo or repoiling address parli errors data parle errors on Ehe special Cycle command or any other system error where the result will be Catastrophic TF am agent does mor want a non maskable interrupt NME to be generated a different reporting mechanism is required SERRE 1S pure open drain and is actively den for a single POI clock by rhe agent reporting Ehe error Wee eme S TS FS syneheomous to the clock and meets Ehe setup amd Hold times of all bused signals However the restoring of SERR to the deasserted state is accomplished by a weak pullup same value as used for s t s which is provided by the system designer and not by Ehe sSougqnalimg agent or central resource bI Sape take two Fo three clock periode to fully restore SERRA The agent chat reports SERRAS KTA 7 5 7 EIS Users Guide KTO
43. rt up to 4 USB3 0 devices The OHCI controllers support USBl 1 Full Speed 12Mbps and Low Speed l1 5MDDS The EHCI controllers support USB2 0 High Speed 480Mbps The xHCI controllers support USB3 0 USB2 0 and USB 1 1 Super Speed 5 0Gbps High Speed 480Mbps Full Speed 12Mbps and Low Speed 1 5Mbps Legacy Keyboard Mouse and wakeup from sleep states are supported Over current detection on all USB ports except USB2 sl USB standard Connector HOT Note 1 Locas USBO USB2 0 USB1 1 Frontpanel J5 Held ENCI EI Premtpaner o KE U P 088240 AUS EMS mPCIe J38 OFICER SERCA No over Current detection USB3 USB2 0 USB1 1 mSATA mPCIe J43 OHCI1 EHCI1 No over current detection USE uem v eres di Elm mom ugs OECD er eC dE USB2 0 USB1 1 Pin row J16 QUINA EC GE US BERO U BITI USS Cuec stack OC 2 2 AO Rear IO USB USE SS USE 0 08 USB c 0 cial stack ei 0 EMS LS USBI Left Rear IO JL USL USES O USIEZ 0 US USES o ciel steel alle Z EL J14 USEI Rao e cO 3 Notes In order to meet the requirements of USB standard the 5V input supply must be at least 5 00V The contacts for USB devices are protected and suitable to supply USB devices with a maximum input current of 1000mA ECTS 7 5 Plex Users Guide KID NO 420 System Specification Do not supply external USB devices with higher power dissipation through these pinsTo protect the external power lines of peripheral devic
44. set bus parking but only co a logic low level they may mot be driven high RST may be asynchronous to CLK when asserted or deasserted Although asynchronous deassertion is guaranteed to be a clean bounce free edge Except for configuration accesses only devices that are required to boot the system will respond after reset ADDRESS AND DATA AD 31 00 Address amd Data are malelolexed On che same PCI pins A bus EE ens section consists OF an address phase followed by one or more data phases PCI supports both read and write bursts The address phase Ias the clock cycle in which FRAME 1s asserted During the address phase AD 31 00 contain a physical address 32 bits For 1 0 this ns al ByEe address on configuration and memory vt Gis a DWORD address During data phases Ap 07 00 contain Ehe least significant byte iso eno Alb SRS A contain che MIS SET significant bre meo Nete daa dE stable and valid when IRDY is asserted and read data is stable and valid when TRDY is asserted Data is transferred during those clocks where both IRDY and TRDY are asserted C BE 3 0 Bus Command and Byte Enables are multiplexed on the same PCT pins DUring the address phase of a transaction C BE 3 0 define the bus command During the data phase C BE 3 0 are used as Byte Enables The Byte Enables are valid for the entire data phase and determine which byte lanes carry meaningful data C BE 0 applies to byte O 1sb and C BE 3 ape lie to
45. te batteri tilbage til leverandgren VARNING Explosionsfara vid felaktigt batteribyte Anv nd samma batterityp eller en ekvivalent typ som rekommenderas av apparattillverkaren Kassera anvant batteri enligt fabrikantens instruktion ANNO lex VORSICHT Explosionsgefahr bei unsachgem fem Austausch der Batterie Ersatz nur durch den selben oder einen vom Hersteller empfohlenen gleichwertigen Typ Entsorgung gebrauchter Batterien nach Anga ben des Herstellers PRECAUCION Peligro de explosi n si la bater a se sustituye incorrectamente Sustituya solamente por el mismo o tipo equivalente recomendado por el fabricante Disponga las bater as usadas seg n las instrucciones del fabricante ADVARSEL Eksplosjonsfare ved feilaktig skifte av batteri Benytt samme batteritype eller en tilsvarende type anbefalt av apparatfabrikanten Brukte batterier kasseres 1 henhold til fabrikantens instruksjoner VAROITUS Paristo vor rajahtea Jos s on virheellisesti asennettu Vaihda paristo ainoastaan lalteval mistajan suosittelemaan tyyppiln Havita kaytetty paristo valmistajan ohjeiden mukaisesti Users Guide KTO O m System Specifications 3 System Specifications 3 1 Component main data The table below summarizes the features of the KTA75 Flex embedded motherboards Form O di 2286 mn S ok AO JE CIELO ocessor AMD eTrinity FP2 processor Quad Core 2 3 GHZ with R 464L APU 35W Quad Core 1 9 GHz with R
46. the power supply outputs Signal must be pulled high by the power supply ECTS 7 5 Plex Users Guide KTO NO Page 30 Connector Signal Deramas co 7 2 DC Power Internal Connector J19 The KTA75 Flex has an internal power input connector for supplying voltage in the range from 11 4V to 12 6V The power connector is a 4 pin 12V ATX connector type Lotes ABA POW 003 K02 or similar Header Pin Signal Description Power supply ENSE BER ad Power supply a qoum Power suppty Warning Hot Plugging power supply is not supported Hot plugging might damage the board Note 1 Use of the 4 pin ATX 12V Power Connector is required for operation of all KTQ67 board versions Notes To protect the external power lines of peripheral devices make sure that the wires have the right diameter to withstand the maximum available current to enclosure of the peripheral device fulfills the fire protecting conditions of IEC EN 60950 Alternatively the DC Power External Connector can be used ECTS 7 5 Plex Users Guide KTD NUS ZST Page 31 Connector Signal Decimas 7 3 Audio Header Connector J41 The Audio Header connector is a 26 pin connector type Molex 87832 2620 or similar Note Type Signal PIN Signal Type Note 20 EN czs our PWR 3 4 AAGND PWR c ORO pr EN HE gt 10 EE ao stpr ovr 1 MERRER 5 000 ao em saw gt gt aco em 15 16 E Se ie 1 mel gt gt MEE uw gt gt gt
47. uec seo A eo acds am che KTAJ 5 ramal are ROHS EOM compliant Capa cule On bale doni None ibn peo Mono Only Japanese brand Solid capacitors rated for 100 C used on board ANA SEE Connector J for BIOS Recovery Clear CMOS J34 Always On J37 ECTS 7 5 Plex Users Guide KT DENG Fea System Specifications OB WANNOWE 52 eco Ai planned Wanaaws 6 82 and OA DNE Windows XP 32 bit DOS Windows Embedded 7 ECTS 7 5 Plex Users Guide KTDS EU UE System Specifications 3 2 KTA75 Flex Block Diagram eTrinity WE APU PCIe x16 xl6slot Dual Channel Processor 722pin 1x PCIe x4 x16 3x DP DisplayPort uPGA slot 1 2 1x mPCIe w USB USB2 0 1x mPCIe mSATA w USB USB2 0 4x USB3 0 USB2 0 2x PCI 32bit 33MHz 10x USB2 0 VIA Audio Codec A75 2x 10 100 Gbe FCH Intel SPI BIOS Flash L 6x SATA SATA3 0 2x Fan CPU System RAID 0 1 10 1x mSATA mSATA shared with mPCIe TPM Infineon socket Feature connector SMBus I2C GPIO DAC ADC PWM COM ASS L Embedded GPIO expansion up Controll to 152 6 pin PS 2 er Intruder ECTS 7 5 Plex Users Guide KTO NO m a System Specifications 3 3 USB ports overview The KTA75 board contains two pairs of EHCI Enhanced Host Controller Interface and OHCI Open Host Controller Interface in order to support up to 10 USB1 1 USB2 0 devices and further more two xHCI Extensible Host Controller Interface to suppo
48. vice s ability to complete the current data phase of the transaction IRDY s used in Som ua Otaola with IRD VA Olea pha e as comesleres om emy eee lora WED ECTS 7 5 Plex Users Guide KTO NO fe EM Page 55 Connector Signal De ibm co STOP LOCK IDSEL DEVSEL ARBITRATION PINS BUS MASTERS ONLY REQ GNT and IRDY are sampled asserted During a read TRDY indicates that valid data iS present en VAD ses During a write Te indicates they targer as prepared to accept data Wait cycles are inserted until both IRDY and TRDY are asserted together Stop Indicates Ehe Current Larger s requesting the Master to stop the SUER ENEREEEMSGCE LONE Lock indicates an atomic operation that may reguire multiple transactions to complete When LOCK is asserted non exclusive transactions may proceed to an address char I9 not currently locked A grant tO Start ce ils aci mem om P l doces not Ec as an ee control or TTO oom oS or OE FE obralhnea under Stes ovn protocol Vin ConjJunctiom wika CNTRO Ie ds poo sie For different agents to use PCI while a single master retains ownership of LOCK If a device implements Executable Memory it should also Implement LOCK and guarantee complete access exclusion in that memory A target of am access that shoperte ROCK MUSE Provide lt lu cion eo a minimim ede 6 bytes aligned Host bridges that have system memory behind them should implement LOCK as a target from the PCI bus point of view
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