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TOSHIBA - DigChip

1. Symbol Name Address 7 6 5 4 3 2 1 0 PRRUN T5RUN T4RUN P1RUN PORUN T1RUN TORUN R W R W Timer 0 0 0 0 0 0 0 TRUN Control 20H Prescaler and Timer Run Stop CONTROL 0 Stop and Clear 1 Run Count up 22H TREGO 8bit Timer Prohibit W Register 0 RMW Undefined 23H TREG1 8bit Timer Prohibit W Register 1 RMW Undefined T10M1 10 0 PWMM1 PWMMO T1CLKO TOCLK1 TOCLKO W 8bit Timer 24H TMOD SourceCLK Prohibit 0 0 0 0 0 0 0 0 and MODE RMW 00 8 bit Timer 00 00 TOOTRG 00 TIO Input 01 16 bit Timer 01 28 1 PWM 01 01 10 8 bit PPG 10 2 1 10 9T16 10 14 11 8 bit PWM 11299 41 11 61256 11 0116 DBEN 0 TFFAIE 5 R W W R W 8bit Timer 0 0 0 0 0 TFFCR pass 25H 1 Double 00 Invert 1 TFF1 0 Inverted Buffer 01 Set TFF1 Invert by Enable 10 Clear TFF1 Enable Timer 0 11 Don t care TREG2 dud 26H R W Can read double buffer values i 2 Undefined TREG3 aoe 27H R W Can read double buffer values Undefined FF2RD DB2EN PWMOINT PWMOM T2CLK1 T2CLKO PWMOS1 PWMOSO R W 5 2 0 0 0 0 0 0 0 rohibi PWMO MUDE pne TFF2 output 1 Double 0 Overflow 0 00 P1 fc 4 00 26 1 value Buffer Interrupt Mode 01 PA fc 16 01 27 1 Enable 1 Compare 1 Timer 10 P16 fc 64 10 28 1 Match Mode 1
2. Symbol Name Address 7 6 5 4 3 2 1 0 PO7C 5 04 P03C PO2C POIC POOC 02H W POCR PORTO Prohibit Control RMW 0 o o 0 0 0 0 0 0 IN 1 OUT When external access set as AD7 0 and cleared to O P17C P16C P15C P14C P13C P12C P11C P10C 04H W PICR PORTI Prohibit Control RMW 0 o o 0 0 0 0 0 lt lt Refer to the P1FC gt gt P27F P26F P25F P24F P23F P22F P21F P20F 05H W PIFC PORTI Prohibit Function RMW 0 o o 0 0 0 0 0 P1FC P1CR 00 IN 01 OUT 10 AD15 8 11 A23 16 P27C P26C P25C P24C P23C P22C P21C P20C 08H W P2CR PORT2 Prohibit Control RMW 0 o o 0 0 0 0 0 lt lt Refer to the P2FC gt gt P27F P26F P25F P24F P23F P22F P21F P20F 09H W P2FC PORT Prohibit Function RMW 0 o o 0 0 0 0 0 P2FC P2CR 00 IN 01 OUT 10 A7 0 11 A23 16 P37C P36C P35C P34C P33C P32C OAH W P3CR PORTS Prohibit Control RMW 0 0 o 0 0 0 0 IN 1 OUT P37F P36F P35F P34F P32F P31F P30F PORT3 a E P3FC Prohibit Function iit 0 0 0 0 0 0 0 0 PORT 0 PORT PORT PORT PORT 0 PORT PORT 1 RAS 1 RW 1 BUSAK 1 BUSRQ 1 HWR 1 WR 1 RD P42C PAC P40C OEH W PACR PORTA Prohibit Control RMW 0 0 0 0 IN 1 OUT P42F PAF 40 10H W PORT4 Prohibit Function RMW 0 0 0 0 PORT 1 CS CAS Note With the TMP96C141A TMP96C141A TMP96C041A which requires an exter
3. The names of input output pins and their functions are described below Table 2 2 Pin Names and Functions Pin Name SUITE 1 0 Functions of Pins P00 P07 8 0 Port 0 1 0 port that allows 1 0 to be selected on a bit basis ADO AD7 Tri state Address data lower 0 7 for address data bus P10 P17 0 Port 1 1 0 port that allows 1 0 to be selected on a bit basis AD8 AD15 8 Tri state Address data upper 8 15 for address data bus A8 A15 Outpu Address 8 to 15 for address bus P20 P27 0 Port 2 1 0 port that allows selection 011 0 on a bit basis with pull down resistor A0 A7 8 Outpu Address 0 7 for address bus A16 A23 Outpu Address 16 23 for address bus P30 Outpu Port 30 Output port RD Outpu Read Strobe signal for reading external memory P31 Outpu Port 31 Output port WR Outpu Write Strobe signal for writing data on pins ADO 7 P320 0 Port 32 1 0 port with pull up resistor HWR Outpu High write Strobe signal for writing data on pins AD8 15 3 p 0 Port 33 1 0 port with pull up resistor WAIT Input Wait Pin used to request CPU bus wait P34 0 Port 34 1 0 port with pull up resistor TD WH RW RAS TS BUSRQ 1 Bus request Signal used to request high impedance for ADO 15 A0 23 RD WR HWR R W RAS 050 CS1 and 652 pins For external DMAC P35 0 Port 35 1 0 with pull up resistor Sam
4. 1 Port Symbol Name Address 7 6 5 4 3 2 1 0 07 06 05 04 P03 02 P01 P00 R W PO PORTO 00H Input mode Undefined P17 P16 P15 P14 P13 P12 P11 P10 R W P1 PORTI 01H Input mode 0 0 0 0 0 0 0 0 P27 P26 P25 P24 P23 P22 P21 P20 R W P2 PORT2 06H Input mode 0 0 0 0 0 0 0 0 P37 P36 P35 P34 P33 P32 P31 P30 R W P3 PORT3 07H Input mode Output mode 1 1 1 1 1 1 1 1 42 40 R W P4 PORT4 OCH Input mode 0 1 1 P53 P52 P51 P50 P5 PORT5 R Input mode P67 P66 P65 P64 P63 P62 P61 P60 R W P6 PORT6 12H Input mode 1 1 1 1 1 1 1 1 P73 P72 P71 P70 R W P7 PORT 13H Input mode 1 1 1 1 P87 P86 P85 P84 P83 P82 P81 P80 R W P8 PORTS 18H Input mode 1 1 1 1 1 1 1 1 P95 P94 P93 P92 P91 P90 R W P9 PORT9 19H Input mode 1 1 1 1 1 1 Note When P30 pin is defined as RD signal output mode 1 clearing the output latch register P30 to 0 outputs the RD strobe from P30 pin for PSRAM even when the internal address is accessed If the output latch register P30 remains 1 the RD strobe is output only when the external address is accessed 162 Read Write R W R Ww Prohibit RWM Either read or write is possible Only read is possible Only write is possible Prohibit Read Modify Write Prohibit RES SET TSET CHG STCF ANDCF ORCF XORCF Instruction TOSHIBA CORPORATION 2 O Port Control 1 2 TMP96C141AF
5. Overflow interrupy Compare and match interrupt Control double buffer Disable enable PWM timer Flip flop3 TFF3 output value TO3 Figure 3 8 5 8 Bit PWM1 Mode Control Register TOSHIBA CORPORATION 75 96 141 PFFCR 002AH FF3C1 bit Symbol FF3CO Read Write After reset 00 Don t care 01 Set TFF3 Function 10 Clear TFF3 11 Don t care FF3TRG1 FF3TRGO FF2C1 FF2CO FF2TRG1 FF2TRGO Disable TFF3 inverted 00 Don t care 100 Disable TFF2 inverted Invert by match 2 01 TFF2 101 Invert by match Set by match gt 10 Clear TFF2 110 Set by match Clear by match 111 Clear by match clear by overflow clear by overflow 11 Don t care set by overflow set by overflow Select PWM timer F F2 TFF2 trigger Disable TFF2 trigger Invert by compare and match Set by compare and match Clear by 2n overflow Clear by compare and match Set by 2n overflow Control PWM timerF F2 TFF2 Don t care Set TFF2 to 1 Clear TFF2 to 0 Don t care Select PWM timer L F F3 TFF3 trigger Disable TFF3 tri Invert by compare and match Set by compare and match Clear by 2n 1 overflow Clear by compare and match Set by 2 overflow Control PWM timerF F2 TFF2 Don t care Se
6. Symbol Name Address 7 6 5 4 3 2 1 0 BR1CK1 BR1CKO BR153 BR152 BR151 BR150 R W R W 0 0 0 0 0 0 0 BRICR Baud Rate 57H Control 00 40 fc 4 Set frequency divisor Tm 01 2 10 16 Fix at O 0 10 48 ic 64 1 prohibited 11 032 c 256 ODE1 ODEO Special R W ODE Open Drain 58H 0 0 Enabig 1 P93 1 P90 Open drain Open drain 7 A D Converter Control Symbol Name Address 7 6 5 4 3 2 1 0 EOCF ADBF REPET SCAN ADCS ADS ADCH1 ADCHO R R W AD A D Converter MOD Mode reg SER 0 0 0 0 0 0 0 0 1 1 Repeat 1 Scan 1 Slow End Busy riide moda mod 1 START Analog Input Channel Series 1 ADRO1 ADROO AD Result AD Reg 0 low BN i REGOL Undefined 1 1 1 1 1 1 ADR09 ADR08 ADRO7 ADR06 ADR05 ADR04 ADRO03 ADRO2 AD Result 61H R AD Reg 0 high REGOH Undefined 1 ADR11 ADR10 AD Result AD Reg 1 low 62H REGIL Undefined 1 1 1 1 1 1 ADR19 ADR18 ADR17 ADR16 ADR15 ADR14 ADR13 ADR12 AD Result 63H R AD Reg 1 high REG1H Undefined 1 ADR 1 ADR20 AD Result AD Reg 2 low em REG2L Undefined 1 1 1 1 1 1 ADR29 ADR28 ADR27 ADR26 ADR25 ADR24 ADR23 ADR22 AD Result 65H R AD Reg 2 high REG2H Undefined 1 ADR31 ADR30 AD Result AD Reg 3 low gori n REGSL Undefined 1 1 1 1 1 1 ADR39 ADR38 ADR37 ADR36 ADR35 ADR34 ADR33 ADR32 AD AD Result 67H R REG3H Reg 3 high Undefined Data to be stored in A D Conversion Result Reg Low are the lower 2 bits of the conversion result The contents of the lower 6 bits of this regis
7. 5 1 TFFSCO 2 4 CAPIT4 EQSTA EQ4T4 TFFACO 0039H Read Write After reset 00 Invert TFF5 TFFA invert trigger 00 Invert TFF4 01 Set 5 0 Disable trigger i01 Set Function 10 Clear 5 21 Enable trigger 210 Clear 4 3 11 don t care invertwhen Invertwhen invertwhen Invertwhen Alwaysreadas 11 0 ithe UC value the UC the UC Always read as 11 don t care is loaded to 5 is loaded to matches imatches 11 2 1 5 4 A Timer 4 4 control Inverts the TFF4 value software inversion Sets TFF4 to 1 Clear TFF4 to 0 Don t care Always read as 11 L gt Timer flip flop 4 TFF4 invert trigger Trigger disable Invert prohibition Trigger enable Invert permission CAP2T4 Invert when the up counter value is loaded to CAP2 CAP1T4 Invert when the up counter value is loaded to 1 5 4 Invert when up counter matches TREGS EQ4TA Invert when up counter matches TREG4 Los Timer flip flop 5 TFF5 control Inverts the TFF5 value software inversion Set TFF5 to 1 Clear TFF5 to 0 Don t care Always read as 11 Figure 3 9 5 16 Bit Timer 4 F F Control TAFFCR TOSHIBA CORPORATION 89 96 141
8. e bit Symbol P37F P36F P35F p32F P3IF P3OF o 1 9 9 o 0 PORT 0 0 PORT 0 PORT 10 0 PORT 0 PORT 1 RAS 1 RAW i11 BUSAK 1 BUSRQ 1 HWR 1 WR HERD P30 RD function setting BUSRQ setting P3FC lt P34F gt EE P3CR P34C 0 BUSAK setting P3FC lt P35F gt WE P3CR lt 35 gt 0 output Always RD output for pseudo SRAM for external access RD output only P31 WR function setting 1 R W setting lt P36F gt 1 EE P3CR lt P36C gt l Sie X 2 HWR setting lt gt 1 0 lt 2 gt 1 P3CR lt P37C gt SCRSESZE P3CR P32C 1 0 output output WR output only for external access Note When P33 WAIT is used as a WAIT pin set P CR P33C to 0 and Chip Select Wait control register 32 Figure 3 5 8 Registers for Port 3 TOSHIBA CORPORATION 96 141 3 5 5 Port 4 40 42 In addition to functioning as general purpose port Port 4 is a 3 bit general purpose I O port O setona Port 4 also functions as a chip select output signal CSO to bit basis using control register PACR and function register CS2 or CASO to CAS2 PAFC Resetting does the following Sets the P40 and P42 ou
9. TOSHIBA CORPORATION 149 96 141 3 13 3 Operation The watchdog timer generates interrupt INTWD after the detecting time set in the WDMOD WDTP1 O gt register and outputs a low level signal The watchdog timer must be zero cleared by software before an INTWD interrupt is generated If the CPU malfunctions runaway due to causes such as noise but does not execute the instruction used to clear the binary counter the binary counter overflows and an INTWD interrupt is generated The CPU detects malfunction runaway due to the INTWD Interrupt and it is possible to return to normal oper Example Clear the binary counter WDCR 0 1 0 0 1 1 1 ation by an anti malfunction program By connecting the watchdog timer out pin to peripheral devices resets a CPU malfunction can also be acknowledged to other devices The watchdog timer restarts operation immediately after resetting is released The watchdog timer stops its operation in the IDLE and STOP modes In the RUN mode the watchdog timer is enabled However the function can be disabled when entering the RUN mode 0 Write clear code 4EH Q Set the watchdog timer detecting time to 218 fc WDMOD e 1 0 1 Disable the watchdog timer WDMOD lt 0 WDCR e epoxy 1 0 0 Set IDLE mode WDMOD 0 1 0 WDCR lt 1 0 1 1 0 0 Executes HALT command X X X Clear WDTE to 0 1 Write disable code B1H X Disables WDT and
10. BUSAK 1 Bus acknowledge Signal indicating that ADO 15 AO 23 RD WR HWR RAW RAS CSO CS1 652 pins are at high impedance after receiving BUSRQ For external DMAC P36 2 0 Port 36 1 0 port with pull up resistor R W Outpu Read write 1 represents read or dummy cycle 0 write cycle P37 4 0 Port 37 1 0 port with pull up resistor RAS Outpu Row address strobe Outputs RAS strobe for DRAM P40 0 Port 40 1 0 port with pull up resistor CSO 1 Outpu Chip select 0 Outputs 0 when address is within specified address area CASO Outpu Column address strobe 0 Outputs CAS strobe for DRAM when address is within specified address area Note With the external DMA controller this device s built in memory or built in cannot be accessed using the BUSRQ and BUSAK pins 4 TOSHIBA CORPORATION 96 141 A Number of Pins 1 0 Functions P41 0 Port 41 1 0 port with pull up resistor CS1 1 Output Chip select 1 Outputs 0 if address is within specified address area CAS1 Output Column address strobe 1 Outputs CAS strobe for DRAM if address is within specified address area P42 0 Port 42 1 0 port with pull up resistor CS2 1 Output Chip select 2 Outputs 0 if address is within specified address area CAS2 Output Column address strobe 2 Outputs CAS
11. Figure 3 10 1 Port 6 PG Circuit TOSHIBA CORPORATION 103 96 141 PG1M PGITE PATO CCWO PGOM PGOTE 004EH Read Write R W After reset 0 0 0 0 0 0 0 0 PG1 write PG1 PG1 mode PGO write PGO PGO mode PGO mode Rotaing excitation trigger imode Rotaing excitation trigger 0 8bit 0 20 Bbit sdirection 0 Function write 0 Normal 9 d write i0 Normal H 1 2excitation i H 2excitation AES rotation 0 disable rotation 0 disable 1 4bit 2121 3 1 4bit 11 1 2 write Reverse 1 enable 1 Reverse 1 enable 221 excitation Do write i excitation rotation rotation iss PGO Trigger input enable Trigger input disable to PGO Trigger input enable to PGO 1 or 2 excitation full step 1 2 excitation half step PG mode PGO stepping motor control Rotaing direction control Normal rotation PG mode Reverse rotation 8 bit write 4 bit write PG mode Only shifter alternate register can be written Figure 3 10 2a Pattern Generation Control Register PGO1CR 104 TOSHIBA CORPORATION 96 141 PGO1CR bit Symbol t OCCWi PGIM PGITE PATO i CCWO PGOM PGOTE PG1write 1 iPG1 mode PG1 iPGO write 0 mode PGO mode Rota
12. TOSHIBA CORPORATION 19 96 141 3 High Speed Micro DMA Start Vector When the CPU reads the interrupt vector after accepting an inter rupt it simultaneously compares the interrupt vector with each channel s micro DMA start vector bits 4 to 8 of the interrupt vec DMAOV 007CH DMA1V 007DH DMA2V 007EH DMA3V 007FH 4 Notes Micro DMAO Start Vector tor When both match the interrupt is processed in micro DMA mode for the channel whose value matched If the interrupt vector matches more than one chan nel the channel with the lower channel number has a higher priority read modify write is not possible 7 4 3 2 1 0 bit Symbol DMAOV8 DMAOV7 DMAOV6 DMAOV5 DMAO0V4 Read Write W After reset 0 0 0 0 0 Micro DMA1 Start Vector read modify write is not possible 7 5 4 3 2 1 bit Symbol DMA1V8 DMA1V7 DMA1V6 DMA1V5 DMA1V4 Read Write W After reset 0 0 0 0 0 Micro 2 Start Vector read modify write is not possible 7 5 4 3 2 1 0 bit Symbol DMA2V8 DMA2V7 DMA2V6 DMA2V5 DMA2V4 Read Write W After reset 0 0 0 0 0 Micro DMAS Start Vector read modify write is not possible 7 5 4 3 2 1 bit Symbol DMA3V8 DMA3V7 DMA3V6 DMA3V5 DMA3V4 Read Write W After reset 0 0 0 0 0 The instruction execution unit and the bus interface unit of this CPU operate independently of each other Therefore if the i
13. on bit basis 21 7 v P8CR write ux Function control on bit basis P8FC write 5 Programmable e pull up Output latch A 5 P8 write Selector __ 4 1 P82 04 gt P83 TOS Timer F F OUT B P86 TO6 TO4 Timer 4 TOS Timer 5 B TO6 Timer 6 lt 1 Selector P8 read S Aj L 2 Figure 3 5 17 Port 8 P80 P86 TOSHIBA CORPORATION 41 96 141 2 42 mJ Internal data bus Reset Direction an INTO pin for external interrupt request input Port 87 is a general purpose port and also used as control on bit basis P8CR write 5 pe P h Programmable pull up L1 P87 INTO Output latch P8 write INTO interrupt lt gt lt 0 gt Figure 3 5 18 Port 87 TOSHIBA CORPORATION TMP96C141AF Port 8 Register P8 bit Symbol 0018H Read Write After reset P8CR bit Symbol 1 PBSC 2 P84C P83C P82C PBIC PB0C 001 i Read Write After reset Function fo After reset Read modify write is iQ PORT 0 PORT HM TOS 1 04 prohibited for registers P8CR and P8FC Setting P82 as TO4 P8FC lt 82 gt P8CR lt 82 gt Setting P83 as TO5 P8FC lt 8 gt P8CR lt P83C gt gt
14. 0 8V CL50pF However CL Input Level 152 High 2 4V High O 8Vcc 0 2Vcc Except for ADO 015 100pF for ADO 015 ADO 023 ALE RD WR HWR RAW CLK RAS CASO CAS2 Low 0 45V ADO AD15 TOSHIBA CORPORATION 96 141 1 Read Cycle 0 23 Port Input RAS ADO 15 ALE TOSHIBA CORPORATION 153 96 141 2 Write Cycle X1 Port Output 154 TOSHIBA CORPORATION 4 4 A D Conversion Characteristics TMP96C141AF TMP96C141AF Vec 5V 10 TA 20 70 C Symbol Parameter Min Typ Max Unit VREF Analog reference voltage Veo 15 Voc Voc AGND Analog reference voltage Vss Vss V VAIN Analog input voltage range 55 Voc IREF Analog current for analog reference voltage 0 5 15 mA Low speed conversion mode 1 5 TBD 0 Error 4 fc High speed conversion mode 33 0 TBD 16 0 Quantize error of lt 16MHz uy a LSB 30 5 LSB not included Low speed conversion mode 41 5 TBD 4 0 16 lt fc High speed conversion mode 4 0 TBD 38 0 20MHz 4 5 Serial Channel Timing Interface Mode Vec 5V 10 TA 20 70 C 1 SCLK Input Mode Variable 16MHz 20MHz Symbol Parameter Unit Min Max Min Max Min Max SCLK cycle 16x 1 0 8 Us loss Ou
15. INTT IPWIC 5 IT5M2 R W 0078H O 0 0 0 5 1 IPW1M2 1 0 IPWOC IPWOM2 IPWOM 1 IPWOMO IT5MO INTTR7 TREG7 1 7 IT7M2 IT7M1 IT7MO IT6C IT6M2 1 6 1 IT6MO INTET7 76H d 207 RW _ 0 0 0 O0 0 1 0 i 9 0 INTTXO INTRXO ITXOM2 ITXOM1 ITXOMO RW Ww 4 TREG4 114 ITAM2 1 4 1 ITAMO RW 0 0 0 0 INTTR6 TREG6 IRXOC IRXOM2 IRXOM1 IRXOMO 0 0 2 250 2 AQ fo o o0 o 0 0 o i o 0 0 0 W Ji Function Write Prohibits interrupt request Sets interrupt request level to 1 Sets interrupt request level to 2 Sets interrupt request level to 3 Sets interrupt request level to 4 Sets interrupt request level to 5 Sets interrupt request level to 6 Prohibits interrupt request Function Read Indicates no interrupt request 1 Indicates interrupt request Function Write Clears interrupt request flag Interrupt source bit Symbol Read Write lt After reset TOSHIBA CORPORATION TMP96C141AF 2 External Interrupt Control Interrupt Input Mode Control Register NMIREE 007BH Rea
16. Setting P90 as Open drain output 0 CMOS output Open drain output Setting P93 as Open drain 0 CMOS output Open drain output Port 3 11 11 Port 9 Open Drain Enable Register ODE 124 TOSHIBA CORPORATION 96 141 3 11 2 Configuration Figure 3 11 12 shows the block diagram of the serial channel O Serial clock generation circuit 1 1 BROCR lt BROCK1 0 gt Timer 0 comparator output i 1 t 1470 4 gt 5 2 SIOCLK 172 016 i v 1878 fc 64 gt 5 24774 P 18732 6256 9 i au Baudrate 4 SCOMOD i 1 i 141 fc 2 generator lt 5 1 0 gt 1 L 1 1 1 1 INTRXO INTTXO Lo xd Transmission counter 16 Receive SCOMOD Serial channel counter WU interrupt 16 control RXDCLK TXDCLK SCOMOD lt RXE gt gt Receive Transmission control control SCOCR PE EVEN Parity control There isn t in channel 1 Shared by P90 Shared by P91 TI SCOCR lt OERR gt PERR FERR LL Internal bus Figure 3 11 12 Block Diagram of the Serial Channel 0 TOSHIBA CORPORATION 125 TMP96C141AF Figure 3 11 13 shows the block diagram of the serial channel 1 Sandager Serial clock generation circuit BRICR lt BRICK1 0 gt TOOTRG Timer 0 comparator output po
17. TOSHIBA CORPORATION 4 Application of PG and Timer Output As explained in Trigger signal from timer the timing to shift PG and invert TFF differs depending on the mode of timer An application to operate PG while operating an 8 bit timer in Se TMP96C141 AF PPG mode will be explained below To drive a stepping motor in addition to the value of each phase PG output synchronizing signal is often required at the timing when excitation is changed over In this application port 6 is used as a stepping motor control port to output a synchro nizing signal to the TO1 pin shared by P71 TREG1 TO1 P71 ee 0 P60 PGO1 P61 nc c cer wes 02 P62 63 Figure 3 10 13 Output Waveforms of 4 Phase 1 Step Excitation Setting example 7 6 5 4 3 2 1 0 TRUN lt 0 0 TMOD lt e 1 0 X X X X 0 1 TFFCR x X X 0 0 1 1 X TREGO e x TREG e x P7CR lt x X X X o S 1 P7FC lt x X X X 1 X P6CR lt 1 1 1 1 P6FC lt 1 1 1 1 PGOICR lt 0 0 0 1 PGOREG TRUN lt e 1 X EE I 21 1 Note no change TOSHIBA CORPORATION Stop timer 0 and clears it to zero Set timer 0 and timer 1 in PPG output mode and selects T1 as the input clock Enable TFF1 inversion and sets TFF1 to 1 Set the duty of TO1 to TREGO Set th
18. bO b7 b3 b6 b2 b5 b1 00 P60 1 5 b1 b4 b7 b3 b6 b2 01 P61 PG02 P62 b6 b2 b5 b1 b4 bo b7 b3 P63 57 b3 b6 b2 b5 b1 b4 bO T Initial value of PGOREG lt 11001000 Note bn denotes the initial value of PGOREG lt b7 b6 b5 b4 b3 b2 b1 bO Normal Rotation Trigger signal from timer 00 60 51 b5 b2 b6 b3 b7 PGO1 P61 BS 52 b6 b3 b7 bO b4 b1 PGO2 P62 b6 b3 b7 bO b4 b1 b5 b2 PGO3 P63 b7 50 54 b1 b5 b2 b6 b3 1 Initial value of PGOREG 10001100 Q Reverse Rotation Figure 3 10 11 Output Waveforms of 4 Phase 1 2 Step Excitation Normal Rotation and Reverse Rotation 112 TOSHIBA CORPORATION initialization for 4 phase 1 2 step excitation is as follows By rearranging the initial value b7 b6 b5 b4 b3 b2 b1 bO to b7 b3 b6 b2 b5 b1 b4 bO the consecutive 3 bits are set to 1 and other bits are set to 0 positive logic For example 07 b3 b6 are set to 1 the ini tial value becomes 11001000 obtaining the output waveforms as shown in Figure 3 10 11 To get an output waveform of negative logic set val ues 1s and 05 of the initial value should be inverted For Shifter alternate register bus Internal TMP96C141AF example to change the output waveform shown in Fig ure 3 10 11 into negative logic change the initial value to 00110111 The operation will be explaine
19. 151 BRICK1 150 After reset Fix at 0 00 4TO fc 4 1 01 2 fc 16 1 10 78 fc 64 1 11 4732 19 256 Setting of the Divided frequency Setting of the divided frequency of baud rate generator 16 divided Don t set 2 to 5 divisions Selecting the input clock of baud rate generator Internal clock T0 fc 4 Internal clock T2 fc 16 Internal clock 8 fc 64 Internal clock 732 fc 256 Note use baud rate generator set TRUN lt PRRUN gt to 1 putting the prescaler in RUN mode Figure 3 11 8 Baud Rate Generator Control Register Channel 0 BROCR 7 6 5 4 3 2 1 0 T 16 mes 19 met 19 Transmission SC1BUF 0054H 7 6 5 4 3 2 1 0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 Receiving Figure 3 11 9 Serial Transmission Receiving Buffer Registers Channel 1 SC1BUF TOSHIBA CORPORATION 123 96 141 0 PORT 0 PORT 0 PORT 4 TxD1 2 1 SCLKO 2 1 SCLK1 Prohibit Read modify write Note The TMP96CM40 and TMP96PM40 have register P92F The TMP96C141 does not In other wordes SCLK 0 cannot be specified 0 Port output SCLK1 channel 1 output Figure 3 11 10 Port 9 Function Register P9FC P93 90 0 CMOS 0 CMOS 1 1 OPEN Drain Drain
20. 6 control TO6 TIS FIF Control T5MOD y CAES lt gt hi 7 CAP34M1 M0 4116 Selector 16 bit up counter OR g zi UC5 3 oo LA shift A TRUN lt TSRUN gt trigger wo TSMOD lt T6CLK1 0 gt 22 Match Match Comparator detection detection CP6 Selector Register buffer 6 T45CR lt DB6EN gt Upper byte Lower byte Upper byte Lower byte d Internal bus 5 Figure 3 9 2 Block Diagram of 16 Bit Timer Timer 5 86 TOSHIBA CORPORATION 96 141 TAMOD CAP2T5 0038H Read Write After reset TACLK TACLKO TFF5 invert trigger 0 Disable trigger Function 1 Enable trigger Invert Invert UC value is up counter loaded to matches CAP2 TREGS when the whenthe 20 Soft Capture timing 1 UC4 Timer4 source clock Capture 00 Disable Clear 00 TI4 iNTAoccursatriseedge Enable 01 57 01 811 INT4 occurs at rise edge i 410 4 10 ri41 INT4 occurs at fall edge 11 gT16 11 TFF1T i INT4 occurs at rise edge 11 don t care Timer 4 input clock External clock T14 1 8 fc 4TA 32 fc 4T16 128 fc Clear by match with 5 Figure 3 9 3 16 Bit Timer Mode Controller Register T4MOD 1 2 TOSHIBA CORPORATION 87 96 141 TAMOD 0038H bit Symbol CAP2TS E
21. According to the setting of SCOCR and SC1CR SC1 0 the above baud rate gen erator clock internal clock 1 500 Kbps fc 16 MHZ or the match detect signal from timer O will be selected to generate the basic clock SIOCLK amp Receiving Counter The receiving counter is a 4 bit binary counter used in asynchronous communication UART mode and counts up by SIOCLK clock Sixteen pulses of SIOCLK are used for receiving one bit of data and the data bit is sampled three times at 7th 8th and 9th clock With the three samples the received data is evaluated by the rule of majority For example if the sampled data bit is 1 O and 1 at 7th 8th and 9th clock respectively the received data is evaluated as 1 The sampled data O and 1 is evaluated that the received data is Receiving Control 1 VO interface mode channel 1 only When in SCLK1 output mode with the setting of SC1CR lt IOC gt O RxD1 signal will be sampled at the rising edge of shift clock which is output to SCLK pin When in SCLK input mode with the set ting SC1CR IOC 1 RxD1 signal will be sampled at the rising edge or falling edge of SCLK input according to the setting of SCICR SCLKS register 128 TOSHIBA CORPORATION 2 Asynchronous Communication UART mode The receiving control has a circuit for detecting the start bit by the rule of majority When two or more O are detected
22. Cycles counter overflow time of the above output waves are listed below 16MHz 20MHz 1 024msec 0 819msec 914 4 096msec 3 27 7msec 16 16 38 msec 13 11 msec 102 TOSHIBA CORPORATION 96 141 3 10 Stepping Motor Control Pattern Generation Port the PG port The TMP96C141AF has two channels PGO and PG1 of 4 bit PGO and PG1 can be used independently hardware stepping motor control pattern generation herein All PG operate in the same manner except the following after called PG which actuate in synchronization with the 8 points and thus only the operation of PGO will be explained bit 16 bit timers The PG PGO and PG1 are shared in 8 bit below O ports P6 Differences between PGO and PG1 Channel 0 PGO is synchronous with 8 bit timer O or timer 1 16 bit timer 5 to update the output PGO PG1 The PG ports are controlled by control registers PGO1CR and can select either stepping motor control mode Trigger Signal from Timer 4 from Timer 5 or pattern generation mode Each bit of the P6 can be used as M b Y 7 P63 PG03 m P67 PG13 1 2 excitation 1 2 excitation av SA03 b6 62 02 L9 PG02 P66 PG12 Reverse Rotaion Em 55 o e eeo dic 01 Li P65 PG11 Internal Bus b4 00 60 00 P64 PG10
23. PG 03 P63 lt gt PG 10 P64 PATTERN PG 11 P65 gt GENERATOR 12 P66 1 13 P67 lt gt 0 70 lt gt 8BIT TIMER TIMER 0 8BIT TIMER TIMER 1 TO2 P72 TO3 P73 INTS TI5 P81 T TIMER TO4 P82 MER 4 TOS P83 INT6 TI6 P84 16 TIMER INT7 TI7 P85 TIMER 5 TO6 P86 INTO P87 1KB RAM 32KB ROM TMP96CM40 or 32KB PROM 96 40 INTERRUPT CONTROLLER WATCH DOG TIMER PORTO PORT 1 PORT 2 PORT 3 CS WAIT CONTROLLER 3 BLOCK VCC 2 VSS 3 1 2 CLK 00 07 0 07 gt 10 17 AD8 AD15 A8 A15 lt gt P20 P27 0 7 16 23 P30 RD P31 WR P32 HWR P33 WAIT P34 BUSRQ lt gt P35 BUSAK lt gt P36 R W gt P37 RAS t gt P40 CS0 CASO P41 CS1 CAS1 gt 42 52 52 Figure 1 TMP96C141AF Block Diagram TOSHIBA CORPORATION TMP96C141AF 2 Pin Assignment and Functions 2 1 Pin Assignment The assignment of input output pins for TMP96C1 41 AF their Figure 2 1 shows pin assignment of TMP96C141AF name and outline functions are described below ANO P50 73 72 AN1 P51 74 71 AN2 P52 75 70 AN3 P53 76 69 VCC 77 68 VREF 78 67 AGND 79 66 VSS 80 65 1L 1L 1L 1E 1E 1E 1E 1E 1E 1E PGOO P60 1 64 PG01 P61 2 OG 1 63 PGO2 P62
24. Right shifts WA six times and writes 0 in upper bits Writes contents of WA in memory at FF10H When the analog input voltage of ANO AN2 pins is A D converted in high speed conversion channel scan repeat mode INTEOAD lt 1 0 0 ADMOD lt x X 1 1 0 1 1 0 Note change 3 13 Watchdog Timer Runaway Detecting Timer The TMP96C144AF is containing watchdog timer of Runaway detecting The watchdog timer WDT is used to return the CPU to the normal state when it detects that the CPU has started to malfunction runaway due to causes such as noise When the 144 Disable INTAD Start the A D conversion of analog input channels ANO AN2 in the high speed scan repeat mode watchdog timer detects a malfunction it generates a non maskable interrupt to notify the CPU of the malfunction and outputs O externally from watchdog timer out pin WDTOUT to notify the peripheral devices of the malfunction Connecting the watchdog timer output to the reset pin internally forces a reset TOSHIBA CORPORATION 96 141 3 13 1 Configuration Figure 3 13 1 shows the block diagram of the watchdog timer WDT WDTOUT RESET WDMOD RESET INTWD lt zie WDTOUT Watchdog timer out control WDMOD WDTP1 0 e Selector enable fyg4 Reset Watchdog timer 22 stage binary counter lt WDTE gt Stop or Idle mode Watchdog timer
25. ey 0 Soft iCapture timing Capture 00 Disable 22 INT6 occurs at rise edge Function edont 01 76 174 sere INT6 occurs at rise edge 10 6 2 INT6 occurs at fall edge 11 1 1 INTA occurs at rise edge 11 065 Clear TSCLK1 TSCLKO Timer 5 source clock Enable 00 T16 01 gT1 10 gT4 11 gT16 Timer 5 input clock 1 8 fc T4 32 fc 716 128 fc Clear disable External clock T14 Clear by match with TREG7 Figure 3 9 6 16 Bit Timer Mode Control Register TBMOD 1 2 90 TOSHIBA CORPORATION 96 141 0048 TSCLK1 2 TSCLKO After reset 0 Soft iCapture timing Capture 00 Disable 11 don t INT6 occurs at rise edge 01 T167 1171 care i 22 INT6 occurs at rise edge 10 67 Tey i INT6 occurs at fall edge o INT4 occurs at rise edge Timer 5 Capture timing Timer 5 source clock 2 00 T16 01 T1 10 974 i 11 gT16 Capture disable CAP3 at TI6 rise CAP4 at TI7 rise CAP3 at Tl6 rise at 6 fall CAP3 at TFF1 rise CAP4 at fall gt Software capture Capture control INT4 Control Interrupt occurs at the rise edge of TI6 INT6 at the rise edge of TI6 INT6 input Al
26. 16 bit 00 2WAIT 00 8000H register Enable only 1 CAS2 Bus 01 1WAIT 01 400000H 1 8 bit 10 1WAIT n 10 800000H Bus 11 OWAIT 11 C00000H ote With only block 2 enable 16 bit data bus 2 wait mode after reset 49 96 141 Table 3 6 2 Dynamic Bus Sizing Operand Operand Memory CPU Address CPU Data Data Size Start Address Data Size D15 D8 D7 DO 2n 4 0 8 bits 2n 0 XXXXX b7 b0 8 bits even number 16 bits 2n 0 m 07 00 2n 1 8 bits 2n 4 1 XXXXX 07 00 odd number 16 bits 2 1 57 00 8 bits 2n 0 XXXXX b7 b0 2n 0 2n 1 XXXXX b15 b8 even number 16 bits 2n 0 b15 b8 b7 b0 16 bits 8 bits 2n 1 XXXXX b7 b0 2n 1 2n 42 XXXXX b15 b8 odd number 2n41 b7 b0 XXXXX 2 2 015 b8 2n 0 XXXXX b7 b0 an 1 XXXXX b15 b8 si 1 1 even number Pt sua 2 0 b15 08 b7 00 16 bits 2n 42 031 024 023 016 32 bits 2n 1 XXXXX b7 b0 2n 42 XXXXX 15 b8 2n 1 8 bits 2n4 3 XXXXX 023 016 odd number 2n44 XXXXX 031 024 21 1 07 00 XXXXX 16 bits 2n4 2 b23 b16 b15 b8 2n44 XXXXX 031 024 Xxxxx During a read data input to the bus is ignored At write the bus is at high impedance and the write strobe signal remains non active 50 TOSHIBA CORPORATION 3 6 2 Chip Select Image An image of the actual chip select is shown below Out of the whole memory area address areas that can be spe
27. One Shot Pulse Output with Delay TOSHIBA CORPORATION 96 141 Setting Example output 2ms one shot pulse with 3ms delay to the external trigger pulse to pin Keep counting Free running Main setting Count with T4M0D lt 0 1 gt Load the up counter value into CAP1 at the rise edge of T14 pin input T4FFCR e 1 1 0 0 0 0 1 0 gt Clear TFF4 to zero Disable TFF4 inversion P8CR lt 1 lect P82 as the TO4 pin P8FC lt x X X 1 X X see INTE45 lt 1 1 0 0 Enable INT4 and disables INTTR4 and INTTR5 INTET54 lt 1 0 0 0 1 0 0 0 TRUN lt 1 X 1 Start timer 4 Setting of 4 TREG4 lt CAP1 3ms T1 65 lt TREG4 2ms T1 T4FFCR lt 1 1 o Enable inversion when the up counter value matches TREG4 or 5 INTET54 lt 1 1 0 qc c9 Enable INTTR5 Setting of 5 T4FFCR lt 200 vom Disable inversion when the up counter value matches TREG 4 or 5 4 lt 1 027 ues com Disable INTTR5 Note x don tcare no change When delay time is unnecessary invert timer flip flop inversion should be enabled when the up counter UC4 value when the up counter value is loaded into capture register matches TREGS and disabled when generating the interrupt 1 CAP1 and set the CAP1 value plus the one shot pulse INTTR5
28. SCLK1 0 Serial clock 1 0 1 WDTOUT 1 Output Watchdog timer output pin NMI Non maskable interrupt request pin Interrupt request pin with falling edge nput Can also be operated at rising edge by program CLK Output Clock output Outputs X1 4 clock Pulled up during reset EA 1 ini External access 0 should be inputted with TMP96C141AF 1 with TMP96CM40F TMP96PM40F ALE 1 Output Address latch enable RESET 1 Input Reset Initializes LSI With pull up resistor X1 X2 2 0 Oscillator connecting pin VCC 2 Power supply pin 5V VSS 3 GND pin 0V ote Pull up pull down resistor can be released from the pin by software 6 TOSHIBA CORPORATION 3 This section describes in blocks the functions and basic oper ations of the TMP96C141AF device Check the chapter Guidelines and Restrictions for proper care of the device 3 1 CPU The TMP96C141AF device has a built in high performance 16 bit CPU For CPU operation see TL CS 900 CPU in the book Core Manual Architecture User Manual This section describes CPU functions unique to TMP96C141AF that are not described in that manual 3 1 1 Reset To reset the TMP96C141AF the RESET input must be kept at for at least 10 system clocks 10 states 1us with a 2 2 system clock within an operating voltage range and with a stable oscillation When reset is accepted the CPU sets as follows Program counter PC to 8000H TOSHIBA CORPORATION TMP9
29. enables acceptance of maskable interrupts with a priority of 3 or greater and non maskable interrupts which are set in the interrupt controller The DI instruction TOSHIBA CORPORATION IFF lt 2 0 gt 7 operates in the same way as the El 7 instruc tion Since the priority values for maskable interrupts O to 6 the DI instruction is used to disable maskable interrupts to be accepted The El instruction becomes effective immediately after execution With the TLCS 90 the El instruction becomes effective after execution of the subsequent instruction In addition to the general purpose interrupt processing mode described above there is also a high speed micro DMA processing mode High speed micro DMA is a mode used by the CPU to automatically transfer byte or word data It enables the CPU to process interrupts such as data saves to built in I Os at high speed Figure 3 3 1 is a flowchart showing overall interrupt processing 10 96 141 General purpose interrupt processing Interrupt Processing Read Interrupt vector V Clear interrupt request F F YES high speed start vector match NO Data transfer by micro DMA PUSH PC PUSH SR SR IFF2 02 Accepted COUNT e COUNT 1 Micro DMA interruput processing level 1 SR lt SYSM gt lt 1 Note1 YES PC lt 8000H Note1 In read only mode always branches to NO Interrupt processing without conditional
30. gt 1 50 50 0 Port P41 1 CS1 CAS1 0 Port P42 gt 1 652 92 Note output chip select signal 50 50 to 52 52 set the corresponding bits of the control register PACR and the function register to PAFC The BOCS B1CS and B2CS registers of the chip select wait controller are used to select the CS CAS function Figure 3 5 10 Registers for Port 4 TOSHIBA CORPORATION 35 96 141 3 5 6 Port 5 P50 P53 Port 5 is a 4 bit input port also used as an analog input pin P5 000DH 4 lt C Port 5 2 P50 P53 2 Port 5 read ANO AN3 5 w Qo E Conversion channel jr converter selector LJ AD read Figure 3 5 11 Port 5 Port 5 Register 7 6 5 4 3 2 1 0 bit Symbol 7 7 52 51 50 Read Write After reset Input mode Note The input channel selection of A D Converter is set by A D Converter mode register ADMOD2 36 Figure 3 5 12 Registers for Port 5 TOSHIBA CORPORATION 3 5 7 Port 6 60 P67 Port 6 is an 8 bit general purpose I O port I O can be set on bit basis Resetting sets Port 6 as an input port and connects a pull up resistor It also sets all bits of the output latch to 1 In TMP96C141AF assigned to P60 to P63 PG1 to P64 to P67 Writing 1 in the addition to functioning as a general purpose I O port Port 6 also functions as a pat
31. 20 Ports 90 and 93 44 TOSHIBA CORPORATION 96 141 2 Ports 91 94 RXDO 1 input pins for serial channels Programmable pull up C P91 RXDO P94 RXD1 Figure 3 5 21 Ports 91 and 94 Ports 91 and 94 are I O ports and also used as RXD Direction control on bit basis n P9CR write Output latch 5 B P9 write Selector Internal data bus P9 read A RxDO RxD1 lt 3 Port 92 CTS SCKLO for serial channelO additionally the CTSO pin and also as a SCKLO I O pin Port 92 is an I O port It is also used as a CTS input pin Reset E Direction control on bit basis 1 P9CR write Direction control on bit basis Programmable ull up P92 CTSO SCLKO P9FC write 5 Output latch P9 write SCLKO OUT c S Selector Internal data bus Selector 4 P9 Read A SCLKO IN CTSO Figure 3 5 22 Port 92 TOSHIBA CORPORATION 45 96 141 4 Port 95 SCLK an SCLK I O pin for serial channel 1 Port 95 is a general purpose I O port It is also used as data bus Internal Output latch Reset Direction control on bit basis A P9CR write Function control on bit basis P9FC write S Selector P9 write SCLK OUT
32. In SCLK output mode synchronous clock is output from SCLK pin and the data is shifted in the receiving buffer 1 whenever the receive interrupt flag INTES1 E Saas en gt w Timing to shift data in the receiving buffer 2 INTRX1 Figure 3 11 21 Receiving Operation in I O Interface Mode SCLK Output Mode In SCLK input mode the data is shifted in the receiving data will be shifted in the receiving buffer 2 SC1BUF at buffer 1 when SCLK input becomes active while the the timing shown below and INTES1 IRX1C will be set receive interrupt flag INTES1 lt IRX1C gt is cleared by read again to generate INTRX interrupt ing the received data When 8 bit data is received the pues do d ddp SCLK input x LI SCLKC 1 Falling edge mode RxD X ei Timing to shift data Generate in the receiving 7 buffer 2 eo RS Figure 3 11 22 Receiving Operation in I O Interface Mode SCLK Input Mode Note For data receiving the system must be placed in the receive enable state SCMOD RXE 1 134 TOSHIBA CORPORATION 2 1 7 bit UART Mode The 7 bit mode can be set by setting serial channel mode register SCOMOD lt SM1 0 SC1MOD lt SM1 O gt to 01 In this mode a parity bit can be added and the addi tion of a parity bit can be enabled or disabled by serial channel control register SCOCR PE SC1CR PE
33. When reset A D conversion channel register will be ini tialized to ADMOD lt ADCH1 0 00 so that ANO pin will be selected The pins which are not used as analog input channel can be used as ordinary input port P5 7 Starting A D Conversion A D conversion starts when A D conversion register ADMOD ADS is written 1 When A D conversion starts A D conversion busy flag ADMOD lt ADBF gt which indicates A D conversion is in progress will be 8 set to 1 A D Conversion Mode Both fixed A D conversion channel mode and A D conversion channel scan mode have two conversion modes i e single and repeat conversion modes In fixed channel repeat mode conversion of specified one channel is executed repeatedly In scan repeat mode scanning from ANO lt lt gt ANS is executed repeatedly A D conversion mode is selected by ADMOD REPET SCAN TOSHIBA CORPORATION TMP96C141AF A D Conversion Speed Selection There are two A D conversion speed modes high speed mode and low speed mode The selection is executed by ADMOD lt ADCS gt register When reset ADMOD lt ADCS gt will be initialized to 0 so that high speed conversion mode will be selected A D Conversion End and Interrupt A D conversion single mode ADMOD lt gt for A D conversion end will be set to 1 ADMOD ADBF flag will be reset to and INTAD interrupt will be enabled when A D conver sion of specified
34. control register C Internal bus Figure 3 13 1 Block Diagram of Watchdog Timer TOSHIBA CORPORATION 145 96 141 watchdog timer is 22 stage binary counter which uses fc 2 as the input clock There are four outputs from the binary counter 2164 218 tc 220 tc and 2 fc Selecting one of the outputs with the WDMOD register generates a watch dog interrupt and outputs watchdog timer out when an over flow occurs Since the watchdog timer out pin WDTOUT outputs 0 due to a watchdog timer overflow the peripheral devices can WDT Counter n WDT Interrupt WDT Clear Soft ware be reset The watchdog timer out pin is set to 1 by clearing the watchdog timer by writing a clear code 4EH in the WDCR reg ister In other words the WDTOUT keeps outputting 0 until the clear code is written The watchdog timer out pin can also be connected to the reset pin internally In this case the watchdog timer out pin WDTOUT outputs O at 8 to 20 states 800ns to 2us Q 20 2 and resets itself a A Clear code of write BERE WDTOUT R Figure 3 13 2 Normal Mode Over flow WDT Counter n LR oui ee WDT Interrupt WDTOUT Internal Reset Figure 3 13 3 Reset Mode 146 TOSHIBA CORPORATION 3 13 2 Control Registers Watchdog timer WDT is controlled by two control registers WDMOD and W
35. lt 4 1 0 00 Capture function is disabled Disable is the TOSHIBA CORPORATION e When TAMOD lt 12 1 02 T5MOD lt CAP34M1 O gt 01 Data is loaded to CAP1 CAPS at the rise edge of TIA pin also used as P80 INT4 and TI6 pin also used as P84 INT6 input while data is loaded to 2 at the rise edge of TI5 pin also used as P81 INT5 and pin also used as P85 INT7 input Time difference measurement When TAMOD lt 12 1 0 T5MOD lt 4 1 0 10 Data is loaded to at the rise edge of T14 pin input and to CAP3 at the rise edge of TI6 while to CAP2 CAP4 at the fall edge Only in this setting interrupt INT4 INT6 occurs at fall edge Pulse width measurement e When TAMOD lt 12 1 02 T5MOD lt 4 1 0 gt 11 Data is loaded to CAP1 at the rise edge of timer flip flop TFF1 while to 2 CAP4 at the fall edge Besides the value of up counter can be loaded to capture registers by software Whenever O is written in TAMOD CAPIN T5MOD lt CAP31N gt the current value of up counter will be loaded to capture register CAP1 CAP3 It is necessary to keep the prescaler in RUN mode TRUN lt PRRUN gt to be 1 amp Comparator These are 16 bit comparators which compare the up counter UC4 UC5 value with the set value of TREG4 TREGS TREG6 TREG7 to detect the match When a match is detected the comparators generat
36. program branch RETI Instruction POP SR POP PC End Figure 3 3 1 Interrupt Processing Flowchart TOSHIBA CORPORATION 3 3 1 General Purpose Interrupt Processing When accepting an interrupt the CPU operates as follows 1 The CPU reads the interrupt vector from the interrupt controller When more than one interrupt with the same level is generated simultaneously the interrupt controller generates interrupt vectors in accordance with the default priority which is fixed as follows the smaller the vector value the higher the priority then clears the inter rupt request 2 The CPU pushes the program counter and the status register to the system stack area area indicated by the system mode stack pointer 8 The CPU sets a value in the CPU interrupt mask register IFF2 to O gt that is higher by 1 than the value of the accepted interrupt level However if the value is 7 7 is Set without an increment 4 The CPU sets the SYSM flag of the status register to 1 and enters the system mode 5 The CPU jumps to address 8000H interrupt vector then starts the interrupt processing routine In minimum mode all the above processing is completed in Seas 1 515 20 2 In maximum mode it is com pleted in 17 states TOSHIBA CORPORATION TMP96C141AF Bus Width of Stack Interrupt Processing State Number Area MAX mode Min mode 8 bit 23 19 16 bit 17 15 To return to the
37. variable duty at fixed interval output mode 8 bit interval timer mode 70 Figure 3 8 1 is a block diagram of 8 bit PWM timer tim ers 2 and 3 PWM timers consist of an 8 bit up counter 8 bit com parator and 8 bit timer register Two timer flip flops TFF2 for timer 2 and TFF3 for timer 3 are provided Input clocks 1 P4 and P16 for the PWM timers can be obtained using the built in prescaler PWM timer operating mode and timer flip flops are con trolled by four control registers POMOD P1MOD PFFCR and TRUN TOSHIBA CORPORATION TMP96C141AF TRUN lt PRRUN gt fc 2 PWM dedicated prescaler gP1 gP4 gP16 F F2 PWM2 OUT fc 4 fc 16 fc 64 POMOD PWMOM gt TFF2 T02 TRUN lt PORUN gt Y Selector PFFCR lt FF2C1 0 gt gP1 PFFCR lt FF2TRG1 0 gt P16 gt control Overflow bod Interrupt control POMOD lt PWMOINT gt 2 8 bit timer register TREG2 Shift trigger Register buffer Register write POMOD lt DB2EN gt Internal bus Figure 3 8 1 Block Diagram of 8 Bit PWM Timer O Timer 2 Note Block diagram for 8 bit PWM timer 1 timer 3 is the same as the above diagram TOSHIBA CORPORATION 71 96 141 Prescaler Generates input clocks dedicated to PWM timers by further dividing the fundamental clock fc after it has been divided by 2 fc 2 Since the registe
38. 1 200 0 300 14 745600 3 76 800 19 200 4 800 1 200 T 6 38 400 9 600 2 400 0 600 T C 19 200 4 800 1 200 0 300 Transfer rate in I O interface mode is 8 times as fast as the values given in the above table TOSHIBA CORPORATION 127 96 141 Table 3 11 2 Selection of Transfer Rate 1 When Timer 0 Input Clock 1 is Used Unit Kbps 12 288MHz 12MHz 9 8304MHz 8MHz 6 144MHz 96 76 8 62 5 48 48 38 4 31 25 24 32 31 25 16 24 192 12 192 96 12 9 6 6 9 6 48 6 48 3 48 24 How to calculate the transfer rate when timer 0 is used Transfer rate fc TREGO x 8 x 16 T Input clock of timer O Ti fg T4 32 T16 1 128 When timer input clock 1 is used Note Timer 0 match detect signal cannot be used as the transfer clock in I O interface mode Q Serial Clock Generation Circuit This circuit generates the basic clock for transmitting and receiving data 1 VO interface mode channel 1 only When in SCLK output mode with the set ting of SC1CR lt lOC gt 0 the basic clock will be generated by dividing by 2 the output of the baud rate generator as described before When in SCLK input mode with the setting of SC1CR IOC 1 the rising edge or falling edge will be detected accord ing to the setting of SC1CR SCLKC regis ter to generate the basic clock 19 Asynchronous Communication UART mode
39. 7 Interrupt request signal Interrupt Je level detect POS HE then 1 Interrupt request flip read D3 D4 Interrupt request clear Dn 3 Interrupt request V read V A0H V INTRXO INTTXO INTRX1 INTTX1 INTT3 INTTR4 INTTRS 6 INTTR7 INTAD Interrupt 05 vector D6 generation D7 D8 DMAIV DMA2V DMA3V High speed micro DMA channel priority encoder Highest priority ch 0 uring IOLE During STOP HALT release High speed micro DMA request High speed micro DMA channel specification Figure 3 3 3 1 Block Diagram of Interrupt Controller TOSHIBA CORPORATION 17 TMP96C141AF 1 Interrupt Priority Setting Register 18 INTEOAD 45 67 10 54 50 INTES1 Address IADC IADM2 IADM1 IADMO Read modify write prohibited 10M2 10M 1 10 0 5 15 15 2 INT4 15 1 ISMO 14C 14M2 14M1 14M0 0072H 0 0 INTT3 Timer3 PWM 1 intra timers ITIM2 ITIM1 ITIMO 16M2 0 0 ice 0 i 0 16M1 16M0 i 0 4 0 2 Timer2 PWMO0
40. 9 11 Programmable Pulse Generation PPG Output Waveforms 96 TOSHIBA CORPORATION 96 141 When the double buffer of TREG4 is enabled in this at match with TREGS This feature makes easy the handling of mode the value of register buffer 4 will be shifted in TREG4 low duty waves Match with 4 M MENS Up counter Q4 Up counter Q2 Match with TREG5 Shift into the TREG5 TREG4 value to be compared Register buffer Q2 Q3 Write into the TREG4 Figure 3 9 12 Operation of Register Buffer Shows the block diagram of this mode TRUN lt T4RUN gt selector 16 Bit up counter F F F F Selector clear 4 5 116 TO4 PPG output TOS Selector TREG4 WR gt Register buffer 4 45 lt 4 gt internal bus Figure 3 9 13 Block Diagram of 16 Bit PPG Mode TOSHIBA CORPORATION 97 96 141 4 98 Application Examples of Capture Function The loading of up counter UC4 values into the cap ture registers CAP1 and CAP2 the timer flip flop TFF4 inversion due to the match detection by comparators CP4 and the output of TFF4 status to TO4 pin can be enabled or disabled Combined with inter rupt function they can be applied in many ways for example One shot pulse output from external trigger pulse Q Frequency measurement Pulse width measurement Time
41. 96 40 96 40 1 0 DRVE 0 DRVE 1 DRVE 0 DRVE 1 PO Input mode ADO 7 Output mode X X Output P1 Input mode AD8 15 Output mode A8 15 X X Output po Input mode PD PD PD PD Output mode AO 7 A16 23 PD Outpu PD Output P30 RD P31 WR Outpu 1 Output Output Input mode PU PU rcd Output mode PU Input mode PU PU Output mode PU Outpu Input mode PD PD P42 CS2 CAS2 Output mode PD Outpu P5 Inpu P6 Input mode PU PU Output mode PU Outpu p7 Input mode PU PU Output mode PU Outpu Input mode PU PU E Output mode PU Outpu Input mode PU PU P87 INTO Output mode PU Outpu P9 Input mode PU PU Output mode PU Outpu NMI Inpu Input Input WDTOUT Output Output Outpu ALE Output 0 20 CLK Output 1 RESET Input Input Input EA Input Input Input X1 Input 2 Output ile EE nput for input mode input pin is invalid output mode output pin is at high impedance Input nput enable state Input gate in operation Fix input voltage to or 1 so that input pin stays constant Output Output state PU Programmable pull up pin Fix the pin to avoid through current since the input gate operates when a pull up resistor is not set PD Programmable pull down pin Fix the pin like a pull up pin when a pull down resistor is not set nput gate disable state No through current even if the is set to high impedance x Cannot set Note Port regi
42. A D converter with 4 channel analog input that features shared by input only P5 and so can be used as input port 10 bit successive approximation Internal bus A D converter mode register ADMOD ADCH EOCF ADBF REPET SCAN ADCS ADS converter control circuit interrupt Analog input AN3 P53 O gt 2 conversion result register AN1 P51 gt ADREGO to ADREG3 ANO P50 O gt D A converter Figure 3 12 1 Block Diagram of A D Converter This A D converter does not have a built in sample and hold circuit Therefore when A D converting high frequency signals connect a sample and hold circuit externally Note TOSHIBA CORPORATION 139 96 141 ADBF REPET SCAN ADCS ADS ADCH1 ADCHO ADMOD 005 AID AID Repeat scan Analog Input conversion conversion mode mode conversion conversion CnannelSelect End Flag BUSY Flag Speed Start 20 Single 1 END 1 BUSY mode 20 Fixed 20 High conversion unction it Repeat channel speed Start mod mode 1 Channel 21 Low Always 22 Scan speed ireadas 1 0 1 gt 2 0 1 gt 2 gt Start A D conversion Note Always 0 when data is read conversion speed selection A D High speed convers
43. DMACn DMACn 1 if DMACn 0 then INT Fixed address mode MPs 1 0 to I O DMADn DMASn DMACn DMACn 1 if DMACn 0 then INT Read only mode seeesesss for DRAM refresh Dummy DMASn Reads4bytes 1 64s 16 states 1 6 14 states DMASn DMASn 4 Increments lower word only 1 4us DMACn DMACn 1 1 0 Counter mode mm 4 for interrupt counter 11 states DMASn lt DMASn 1 n6 1 DMACn 0 then INT 1 1455 1 state 100ns This condition is 16 bit bus width and O wait of source destination address space Note n corresponds to high speed UDMA channels 0 DMADn DMASn Post increment Increments register value after transfer DMADn DMASn Post decrement Decrement register value after transfer All address space the space for system mode can be for transfer mode control accessed by high speed uDMA Do not use undefined codes TOSHIBA CORPORATION 15 96 141 Usage of read only mode DRAM refresh When the hardware configuration is as follows DRAM mapping size 1MB DRAM data bus size 8 bits DRAM mapping address range 100000H to 1FFFFFH Set the following registers first refresh is performed automatically Register initial value setting LD XIX 100000 LDC DMASO XIX LD A 00001010B LDC DMAMO mapping start address o
44. Direction of transmission transmission rate 9600 bps fc 12 288 2 TOSHIBA CORPORATION 135 96 141 Note 136 Main setting 7 6 5 4 3 2 1 P9CR lt x X 7202 es 0 SCOMOD 0 1 X 1 0 0 SCOCR lt x 0 1 X X X 0 BROCR 0 x 0 1 0 1 0 TRUN lt 1 X INTESO lt 1 1 0 Interrupt processing Acc lt SCOCR and 00011100 Check for error If Acc 0 then ERROR Acc SCOBUF Read the received data Note x don tcare no change Mode 3 9 bit UART Mode The 9 bit UART mode can be specified by setting SCOMOD lt SM1 0 SC1MOD lt SM1 O gt to 11 In this mode parity bit cannot be added For transmission the MSB 9th bit is written in SCMOD lt TB8 gt while in receiving it is stored in SCCR RB8 For writing and reading the buffer the MSB is read or written first then SCOBUF SC1 BUF Select P91 RxD as the input pin Enable receiving in 8 bit UART mode Add an odd parity Set transfer rate at 9600 bps Start the prescaler for the baud rate generator Enable interrupt and sets interrupt level 4 Wake up function In 9 bit UART mode the wake up function of slave controllers is enabled by setting SCOMOD lt WU gt SC1MOD WU to 1 The interrupt INTRX1 INTRXO occurs only when RB8 1 Master Slave 1 Slave 2 Slave 3 TxD pin of the slave controllers must be in open drain output mode Figure 3 11 23 Serial Link Usin
45. Generation 1 PG1 output latch register Shift alternate register 1 Reading the P6 that is set to the PG port allows to read out For the PG mode 4 bit write register Prohibit Read modify write Figure 3 10 4 Pattern Generation 1 Register PG1REG 106 TOSHIBA CORPORATION 96 141 reme Rd Read Write R W R W EE Ln ger do 150 Fixat 0 DB4EN T45CR PGOT DB6EN 003AH PG1 Shift PGOShift Double buffer X Alwa s trigger trigger 0 Disable i read 0 8 bit timer 0 8 bit timer 1 Enable 0 trigger trigger 0 1 timer Double Double 1 16 bit timer 1 16bit timer buffer of buffer of trigger trigger TREG6 TREG4 timer5 Double buffer control Disable Enable DB6EN Double buffer of TREG6 DB4EN Double buffer of TREG4 El cu Selecting PGO shift trigger 8 bit timer trigger timer 0 1 16 bit timer trigger timer 4 8 bit timer trigger timer 0 1 16 bit timer trigger timer 5 Figure 3 10 5 16 bit Timer Trigger Control Register 45 Write 0 to this bit when this register is modified TOSHIBA CORPORATION 107 96 141 8 Bit timer timer 0 1 A DEDE EE Select gt 60 Port60 63 BS 16 Bit timer 4 PGOT A PG1 Port64 67 Select gt 16 Bit timer 5
46. Lower 2 bits of A D result for AN2 are stored 7 6 5 4 3 2 1 bit Symbol ADR29 ADR28 ADR27 ADR26 ADR25 ADR24 ADR23 ADR22 Read Write R After reset Undefined Function Upper 8 bits of A D result for AN2 are stored 7 6 5 4 3 2 1 0 bit Symbol ADR31 ADR30 arcc c Read Write R After reset Undefined 1 1 1 1 1 1 Function Lower 2 bits of A D result for AN3 are stored 7 6 5 4 3 2 1 bit Symbol ADR39 ADR38 ADR37 ADR36 ADR35 ADR34 ADR33 ADR32 Read Write R After reset Undefined Function Upper 8 bits of A D result for AN3 are stored Figure 3 12 3 2 A D Conversion Result Register ADREG2 3 TOSHIBA CORPORATION 3 12 1 Operation 5 1 Analog Reference Voltage High analog reference voltage is applied to the VREF pin and low analog reference voltage is applied to AGND pin The reference voltage between VREG and AGND is divided by 1024 using ladder resistance and com 6 pared with the analog input voltage for A D conversion Analog Input Channels Analog input channel is selected by ADMOD lt ADCH1 O gt However which channel to select depends on the operation mode of the A D converter In fixed analog input mode one channel is selected by ADMOD lt ADCH1 0 among four pins ANO to ANS In analog input channel scan mode the number of channels to be scanned from ANO is specified by ADMOD lt ADCH1 0 such as gt AN1 ANO gt AN1 AN2 and ANO gt AN1 AN2 gt ANS
47. Operation of 8 bit timer timerQ Figure 3 7 4 Timer Operation Control Register TRUN 58 TOSHIBA CORPORATION 96 141 10 1 Read Write After reset Function Prohibit Read Modify Write Operation mode 01 16bit Timer 10 8bit PPG 11 8bit PWM 10 0 PWMM1 PWMMO Source clock of timer1 i 00 TOOTRG i 01 gT1 10 gT16 D 11 91256 PWM cycle 00 8bit Timer 00 01 26 1 i 10 27 1 11 28 1 TICLKO TOCLK1 TOCLKO Source clock of timer0 00 TIO 01 10 T4 i 11 TIG Input clock of timer 0 External Input TIO 11 Prescaler 4 Prescaler T16 Prescaler TMOD lt 10 1 0 gt 01 Overflow output of timer 0 Comparator output of timer 0 16 bit timer mode Set the operation mode of 1 r timerO and 1 00 Two 8 bit timers WimerOandtimer1 01 16 bit timer 10 8 bit PPG output 41 8 bit PWM output timer0 8 bit timer timer 1 Figure 3 7 5 Timer Mode Control Register TMOD TOSHIBA CORPORATION 59 TMP96C141AF TFFCR 0025H Read Write After reset TFF1CO Double 00 Invert UNE SUE utter inversion i 0 Disable 0 1 trigger source Function iV f Ni
48. P1 0 25us and compare interrupt Sets 40us 0 25us in timer register Enables INTT2 and sets interrupt level 4 Starts PWMO counting Table 3 8 2 Interrupt Cycle and Input Clock Selection using 8 Bit Timer Mode Input Clock eae aa Resolution ome Resolution 1 4 fc 0 25ps 64us 0 255 0 2us 51 25 0 25 16 fc 116 2565 116 0 85 204 85 0 85 16 64 fc 4 5 102445 4us 3 2us 819 2us 3 26 Note generate interrupts in 8 bit timer mode bit 5 interrupt control bit lt PWM01NT gt lt PWM1NT gt of POMOD P1MOD must be set to 1 TOSHIBA CORPORATION 81 96 141 Generating a 50 square wave value to the timer output pin TO2 To generate a 5096 square wave invert the timer flip Example To output a 3 0us square wave at fc flop at a fixed interval and output the timer flip flop 16MHz from 2 pin set register as fol lows TRUN lt X Es 0 Stops PWMO and clears it to 0 POMOD x 0 1 1 0 0 X X Sets 8 bit timer mode and selects P1 0 25us as the input clock TREG2 lt 0 0 0 0 0 PFFCR 1 P7CR lt x X X X 1 0 Sets 3 0us 0 25ps 2 6 in the timer register Clears TFF2 to 0 and inverts using comparator output 2 Sets P72 as the TO pin P7FC lt x X X X TRUN lt 1 X gt Stes C3 ET Note don t care no change Sup ET fag tf a op TRUN Up counter y 02
49. RD WR fall 1 5x 50 44 25 ns 12 toa RD WR rise A0 23 Hold 0 5x 20 11 5 ns 13 tapi 15 Valid gt D0 15 input 3 0x 45 143 105 ns 14 m 23 Valid sD0 15 input 3 5x 65 154 110 ns 15 RD RD fall sD0 15 input 2 0x 50 75 50 ns 16 tar RD Low width 2 0x 40 85 60 ns 17 HR RD rise gt D0 15 Hold 0 0 0 ns 18 trac RD gt 0 15 output x 15 48 35 ns 19 tww WR Low width 2 0x 40 85 60 ns 20 tow 00 15 Valid WR rise 2 0x 50 75 50 ns 21 twp WR rise gt D0 15 Hold 0 5x 10 21 15 ns 22 m 23 Valid WAIT input 1WAIT n mode 3 5x 90 129 85 ns 23 m 15 Valid WAIT input 1WAIT n mode 3 0x 80 108 70 ns 24 tow RD WR fall WAIT Hold 1WAIT mode 2 0x 0 125 100 ns 25 A0 23 Valid PORT input 2 5x 120 80 36 ns 26 A0 23 Valid PORT Hold 2 5x 50 206 175 ns 27 top WR rise PORT Valid 200 200 200 ns 28 A0 23 Valid RAS fall 1 0 40 23 10 ns 29 ASRL AQ 15 Valid RAS fall 0 5x 15 16 10 ns 30 trac RAS fall D0 15 input 2 5x 70 130 86 ns 31 RAS fall gt A0 15 Hold 0 5x 15 16 10 ns 32 tras RAS Low width 2 0x 40 85 60 ns 33 RAS High width 2 0x 40 85 60 ns 34 I CAS fall RAS rise 1 0x 35 28 15 ns 35 RAS rise CAS rise 0 5x 25 6 0 ns 36 tecp RAS fall CAS fall 1 0x 40 23 10 ns 37 teac CAS 1811500 15 input 1 5x 65 29 10 ns 38 teas CAS Low width 1 5x 30 64 40 ns AC Measuring Conditions Output Level High 2 2V
50. TMP96C141AF and even parity or odd parity is selected by SCOCR EVEN SC1CR EVEN when PE is set to 1 enable Setting example When transmitting data with the following format the control registers should be set as described below Channel 0 is explained here even CD of transmission transmission rate 2400 bps fc 12 288 2 f 6 5 4 3 2 1 0 P9CR lt x X 1 lt X X X X 1 SCOMOD e x 0 x 0 1 0 1 SCOCR lt x 1 1 X X X 000 BROCR lt 0 X 1 0 0 1 0 1 TRUN 1 X INTESO lt 1 1 0 0 SCOBUF e x x Note x don tcare change 3 2 8 bit UART Mode The 8 bit UART mode can be specified by setting SCOMOD lt SM1 0 SC1MOD lt SM1 O gt to 10 In this mode parity bit can be added the addition of a parity bit is enabled or disabled by SCOCR PE Select P90 as the TxD pin Set 7 bit UART mode Add an even parity Set transfer rate at 2400 bps Start the prescaler for the baud rate generator Enable interrupt and sets interrupt level 4 Set data for transmission SC1CR lt PE gt and even parity or odd parity is selected by SCOCR lt EVEN gt SC1CR EVEN when PE is set to 1 enable Setting example When receiving data with the following format the control register should be set as described below ef
51. X o4 yos Y oe y yo o2 y o Y o5 Y oe X yox o2 Comparator timing Match detect UC clear We eae i zc EE MT TO2 1 55 fc 16MHz gt Figure 3 8 11 Square Wave 50 Duty Output Timing Chart 82 TOSHIBA CORPORATION 96 141 This mode is as shown in Figure 3 8 12 below fc 2 Prescaler 8 bit up counter Clear UC2 UC3 Clock control IT POMOD T2CLK 1 0 gt PIMOD T3CLK1 0 Timer F F 8 bit comparator TO2 TO3 2 control M PFFCR lt FF2C1 0 gt PFFCR lt FF3C1 0 gt PFFCR lt FF2TRG1 0 gt PFFCR lt FF3TRG1 0 gt 8 bit timer register TREG2 TREG3 Interrupt INTT2 TREG2 3 WR INTT3 control Register buffer POMOD DB2EN PIMOD lt DB3EN gt POMOD PWMOINT gt Register write lt gt Internal bus Figure 3 8 12 Block Diagram of 8 Bit Timer Mode TOSHIBA CORPORATION 83 96 141 3 9 16 Bit Timer The TMP96C141AF has two timer 4 and timer 5 multifunc tional 16 bit timer event counter with the following operation modes 16 bit interval timer mode 16 bit event counter mode 16 bit programmable pulse generation PPG mode Frequency measurement mode Pulse width measurement mode Time differential measurement mode 84 Timer event counter consists of 16 bit up counter two 16 bit timer registers two 16 bit
52. can be set on a Port 1 is an 8 bit general purpose I O port I O can be set on a bit basis using control register POCR to 0 and sets Port O to bit basis using control register P1CR and function register input mode P1FC Resetting resets all bits of output latch P1 control reg In addition to functioning as a general purpose port ister P1CR and function register P1FC to O and sets Port 1 to Port 0 also functions as an adaress data bus ADO to 7 To input mode access external memory Port O functions as an address data In addition to functioning as a general purpose port bus AD 7 and all bits of the control register are Port 1 also functions as an address data bus AD8 to 15 or an cleared to O adaress bus A8 to 15 With the TMP96C141AF TMP96C041AF which comes With the TMP96C141AF TMP96C041AF which comes with an external ROM Port always functions as an address with an external ROM Port 1 always functions as an address data bus ADO to 7 regardless of the value set in control regis data bus AD8 to 15 regardless of the value set in control reg ter POCR ister P1CR Reset Reset Direction control Direction control on bit basis on bit basis A P1CR write bus bus POCR write Function control on bit basis data Output F latch Port 0 P00 P07 AD0 AD7 data P1FC write Output Port 1 latch P10 P17 L Output buf
53. denoted Figure 3 11 1 Data Formats 116 TOSHIBA CORPORATION The serial channel has buffer register for transmitting and receiving operations in order to temporarily store trans mitted or received data so that transmitting and receiving operations can be done independently full duplex However I O interface mode serial clock pin is used for both transmission and receiving the channel becomes half duplex The receiving data register is of a double buffer structure to prevent the occurrence of overrun error and provides one frame of margin before CPU reads the received data The receiving data register stores the already received data while the buffer register receives the next frame data By using CTS and RTS there is no RTS so any one port must be controlled by software it is possible to halt data send until CPU finishes reading receive data every time a frame is received Handshake function In the UART mode a check function is added not to start the receiving operation by error start bits due to noise The channel starts receiving data only when the start bit is TOSHIBA CORPORATION TMP96C141AF detected to be normal at least twice in three samplings When the transmission buffer becomes empty and requests the CPU to send the next transmission data or when data is stored in the receiving data register and the CPU is requested to read the data INTTX or INTRX interrupt occurs Besides i
54. difference measurement One Shot Pulse Output from External Trigger Pulse Set the up counter UCA in free running mode with the internal input clock input the external trigger pulse from 4 pin and load the value of up counter into capture register CAP1 at the rise edge of the T14 pin Then set to TAMOD lt CAP12M1 O gt 01 When the interrupt INT4 is generated at the rise edge of TI4 input set the CAP1 value c plus a delay time to TREG4 d and set the above set value c d plus a one shot pulse width p to TREGS c d p When the interrupt INT4 occurs the TAFFCR lt EQ4T4 gt register should be set that the TFF4 inversion is enabled only when the up counter value matches TREGA or TREGS When interrupt INTTR5 occurs this inversion will be disabled E Set the counter in free running mode Count clock EO c internal clock c d p 4 pin input external trigger pulse ihe Load the up counter value into Capture t Register 1 CAP1 INT4 occurred Match with TREG4 Match with TREG5 Timer output pin 4 Delay time L t 1 1 1 Inversion i enable L 1 L 1 1 1 1 1 1 1 Disables inversion caused by loading of the up counter value into CAP1 Inversion enable INTTR5 occurred i Pulse width cus d D 1 gt lt gt p Figure 3 9 14
55. during 3 samples it is recognized as start bit and the receiving operation is started Data being received is also evaluated by the rule of majority Receiving Buffer To prevent overrun error the receiving buffer has a double buffer structure Received data is stored one bit by one bit in the receiving buffer 1 shift register type When 7 bits or 8 bits of data are stored in the receiving buffer 1 the stored data is transferred to another receiving buffer 2 SCOBUF SC1BUF generating an interrupt INTRXO INTRX1 CPU reads only receiving buffer 2 SCOBUF SC1BUF Even before the CPU reads the receiving buffer 2 SCOBUF SC1BUF the received data can be stored SIOCLK 15 16 17 2 3 4 5 6 TMP96C141AF the receiving buffer 1 However unless the receiving buffer 2 GCOBUF SC1BUF is read before all bits of the next data are received by the receiving buffer 1 an over run error occurs If an overrun error occurs the contents of the receiving buffer 1 will be lost although the contents of the receiving buffer 2 and SCOCR RB8 SC1CR RB8 are still preserved The parity bit added in 8 bit UART mode and the most significant bit MSB in 9 bit UART mode are stored in SCOCR lt RB8 gt SC1CR lt RB8 gt When in 9 bit UART mode the wake up function of the slave controllers is enabled by setting SCOMOD lt WU gt SC1MOD WU to 1 and interrupt INTRXO INTRX1 occurs only when SCOCR lt RB8 gt SC1CR RB8
56. equal a parity error occurs Framing error lt FERR gt The stop bit of received data is sampled three times around the center If the majority is O a framing error occurs Receiving Mode 9 Bit 8 Bit Parity 8 Bit 7 Bit Parity 7 Bit Interrupt timing Center of last bit Bit 8 Center of last bit parity bit Center of stop bit Framing error timing Center of stop bit Center of stop bit Center of stop bit Parity error timing Center of last bit Bit 8 Center of last bit parity bit Center of stop bit Overrun error timing Center of last bit Bit 8 Center of last bit parity bit Center of stop bit Note period of transfer rate Transmitting Framing error occurs after an interrupt has occurred Therefore to check for framing error during interrupt operation it is necessary to wait for 1 bit Mode 9 Bit 8 Bit Parity 8 Bit 7 Bit Parity 7 Bit Interrupt timing Just before last bit is transmitted lt TOSHIBA CORPORATION 131 96 141 2 VO Interface mode SCLK output mode Immediately after rise of last SCLK signal See Figure 3 11 19 Immediately after rise of last SCLK signal rising mode or immediately after fall in falling mode See Figure 3 11 20 Timing used to transfer received data to data receive buffer 2 SC1BUF that is immediately after last SCLK See Figure 3 11 21 Timing used to transfer recei
57. for setting transfer source destination addresses However the TL CS 900 has only 24 adaress pins for output A 16M byte space is available for the high speed micro DMA Also in normal mode operation the all address space in other words the space for system TMP96C141AF mode which is set by the CS WAIT controller can be accessed by high speed micro DMA processing There are two data transfer modes one byte mode and one word mode Incrementing decrementing and fixing the transfer source destination address after transfer can be done in both modes Therefore data can easily be transferred betweenl O and memory and between I Os For details of transfer modes see the description of transfer mode registers The transfer counter has 16 bits so up to 65536 trans fers the maximum when the initial value of the transfer counter is 0000H can be performed for one interrupt source by high speed micro DMA processing A the data transferred by the uDMA function the transfer nter was decreased When this counter is O H the processor operates gen eral interrupt processing At this time if the same channel of interrupt is required next interrupt the transfer counter starts from 65536 Interrupt sources processed by high speed micro DMA processing are those with the high speed micro DMA start vectors listed in Table 3 3 1 1 state Note 1 Note 2 Note 3 Note 3 Note 3 DM1 DM2 DM3 DM4 DM5 DM
58. gt gt 5 Setting P84 as TO6 P8FC lt P86F gt P8CR lt P86C gt Note P80 TI4 P81 T15 P84 TI6 P85 TI7 pins do not have a register changing PORT FUNCTION Therefore this is the same as P70 TIO pin When P87 INTO pin is used as an INTO pin set PBCR lt P87C gt to 0 and IIMC IOIE to 1 Figure 3 5 19 Registers for Port 8 TOSHIBA CORPORATION 43 96 141 3 5 10 Port 9 90 P95 Resetting resets the function register value to 0 and sets Port 9 is a 6 bit general purpose I O port I Os canbe setona bits to ports bit basis Resetting sets Port 9 to an input port and connects a pull up resistor It also sets all bits of the output latch registerto 1 Port 90 93 TXDO TXD1 1 In addition to functioning as a general purpose I O port Port 9 Ports 90 and 93 also function as serial channel TXD can also function as an for serial channels 0 and 1 Writing output pins in addition to I O ports 1 in the corresponding bit of the port 9 function register POFC They have a programmable open drain function enables this function Reset Direction control on bit basis P9CR write bus data DoH gt P ch Programmable 5 pull up Selector P90 TXDO E P9 write P93 TXD1 TxD0 TxD1 8 Open drain possible ODE lt ODE1 0 gt 5 Bjal 41 Selector P9 read lt Figure 3 5
59. input 0 8bit write Rotation 0 4bit Step input 1 4bit write 1 Reverse 1 8bit Step enable 1 4bitwrite 1 Reverse 1 8bit Step enable Rotation 1 Enable Rotation 1 Enable 5 Watch Dog Timer Symbol Name Address 7 6 5 4 3 2 1 0 WDTE WDTP1 WDTPO WARM HALTM1 HALTMO RESCR DRVE R W 1 0 0 0 0 0 0 0 WD Watch Dog MOD Timer Mode SCH 00 2 6 tc Warming up Mode 1 Connect 4 518 00 RUN Mode internally 1 WDT 01 2 tc Time 520 2914 01 STOP Mode WDT out Enable 10 2 fc 0 27 4 STOP 11 22 1 25 Mode pin to Mode 11 Don t care Reset Pin Watch Dog _ Timer W WDCR Control PDH Register WDT Disable Code 4EH WDT Clear Code 168 TOSHIBA CORPORATION TMP96C141AF 6 Serial Channel 1 2 Symbol Name Address 7 6 5 4 3 2 1 0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RBO Serial TB7 TB6 5 TB4 TB3 TB2 TB1 0 Sp eur Channel R Receiving W Transmission Buffer Undefined RB8 EVEN PE OERR PERR FERR R R W R Cleared to 0 by reading R W Serial 0 0 0 0 0 0 0 0 SCOCR Channel 0 51H 1 Error Control Receiving Parity 1 Parity 0 SCLKO 1 Input data bit 8 Enable Overrun Parity Framing i 1 Even 15 Note AS TB8 CTSE RXE WU SM1 SMO 561 SCO R W Sco Serial
60. is set to 1 Transmission Counter Transmission counter is a 4 bit binary counter which is used in asynchronous communication UART mode and like a receiving counter counts by SIOCLK clock generating every 16 clock pulses 9 10 11 12 13 14 15 16 Figure 3 11 14 Generation of Transmission Clock Transmission Controller 1 VO interface mode channel 1 only In SCLK output mode with the setting of SC1CR IOC 0 the data in the trans mission buffer are output bit by bit to TxD1 pin at the rising edge of shift clock which is output from SCLK1 pin In SCLK input mode with the setting SC1CR IOC 1 the data in the trans mission buffer are output bit by bit to TxD1 TOSHIBA CORPORATION pin at the rising edge or falling edge of SCLK input according to the setting of SC1CR lt SCLKC gt register xX Asynchronous Communication UART mode When transmission data is written in the transmission buffer sent from the CPU trans mission starts at the rising edge of the next TxDCLK generating a transmission shift clock TxDSFT 129 96 141 Handshake function Serial channel O has a CTSO pin Using this pin data can be sent in units of one frame thus overrun errors can be avoided The handshake function is enabled disabled by SCOMOD lt CTSE gt When the CTSO pin goes high after completion of the current data send data send is halted until the CTSO pin goes lo
61. level can be measured from the dif ference between the first C2 and the second C1 at the second INT4 interrupt Time Difference Measurement This mode is used to measure the difference in time between the rising edges of external pulses input through and Keep the 16 bit timer event counter Timer 4 count ing free running with the internal clock and load the value into at the rising edge of the input pulse to T14 Then the interrupt INT4 is generated Similarly the UC4 value is loaded into 2 at the rising edge of the input pulse to TI5 generating the inter rupt INT5 The time difference between these pulses can be obtained from the difference between the time counts at which loading the up counter value into CAP1 and CAP2 has been done TOSHIBA CORPORATION 101 96 141 Count clock TD TUIL internal clock 4 pin input TIS pin input Loading UC16 into CAP1 Loading UC16 into CAP2 INT1 INT2 Time difference 1 4 Figure 3 9 18 Time Difference Measurement 5 Different Phased Pulses Output Mode When the value in up counter UC4 and the value in TREGA TREGS5 match the value TFF4 TFF5 is inverted In this output mode signals with any different phase can be and be used by 16 bit timer 4 outputted by free running up counter UCA Match with TREG4 Match with TREG5 TO4 TOS Figure 3 9 19 Phase Output
62. lt DB2EN gt Internal bus Figure 3 8 9 Block Diagram of PWM Timer Mode PWMO In this mode enabling double buffer is very useful The Using double buffer makes handling small duty waves register buffer value shifts into TREG2 when a 27 1 overflow easy is detected when double buffer is enabled Match with TREG2 2n 1 Up counter Q1 Up counter Q2 overflow Shift from register buffer TREG2 Compared value Register buffer Register buffer write Figure 3 8 10 Register Buffer Operation TOSHIBA CORPORATION 79 96 141 Example To output the following PWM waves to 2 1525 31 75us TRONS lt umo de VES 0 PMO 0 0 0 0 0 0 1 TREG2 lt 0 0 1 1 1 1 0 0 POMOD lt 1 0 0 0 0 0 1 0 1 1 1 P7CR lt x X X X 1 P7FC lt x X X X 1 TRUN X 1 Note don t care no change using PWMO at fc 16 2 To implement 31 75us PWM cycle by 9 P1 0 25us fc 16 2 31 75 0 25us 127 27 1 Consequently set n to 7 Since the low level cycle 15us for 9 P1 0 25us 15us 0 25 60 8CH set the 3CH in TREG2 Stops PWMO and clears it to 0 Sets PWM 27 1 mode input clock 1 overflow interrupt and disables double buffer Writes 3CH Enables double buffer Sets TFF2 and a mode where TFF2 is set by compare and match and cleared by overflow Sets P72 as t
63. mode 0 counter overflow occurs Up counter UCO is cleared when 2n 1 counter overflow occurs For example when n 6 6 bit PWM will be output while when n 7 7 bit PWM will be output To use this PWM mode the following conditions must be satisfied This mode is valid only for timer O In this mode maxi mum 8 bit resolution of PWM pulse can be output PWM pulse is output to TO1 pin also used as P71 when using timer O Timer 1 can also be used as 8 bit timer Set value of timer register Set value of 2 1 Timer output is inverted when up counter UCO matches the set value of timer register TREGO or when 2n 1 n 6 7 or 8 specified by TO1MOD PWMO 1 Set value of timer register 0 counter overflow TREGO and UCO match 2n 1 overflow interrupt INTTO TO1 tpwm PWM cycle Figure 3 7 13 8 Bit PWM Waveforms TOSHIBA CORPORATION 67 96 141 Figure 3 7 14 shows the block diagram of this mode TO1 TRUN TORUN gt TIO gt 8 bit up counter TFFCR 1 gt lt TFF1C1 0 cl TFF 0 14 gt Selector UC 0 TFF1IS 716 2n 1 TMOD lt 10 1 0 gt 11 TMOD TOCLK1 0 overflow TMOD control PWMM 1 0 Overflow Comparator gt 0 Selector ift trigger TREGO WR Register buffer TFFCR gt Internal bus Figure 3 7 14 Block Diagram of 8 Bit PWM Mode In this mode the value of
64. not have a built in ROM CS2 setting enabled when 10000H to SFFFFFH is accessed for the TMP96CM40 TMP96PM40 which has built in ROM PROM Setting bits to 01 enables setting for all CS s blocks and outputs a low strobe signal CSO CASO CS2 CAS2 from chip select pins when 400000H to TFFFFFH is accessed Setting bits to 10 enables them 800000H to BFFFFFH is accessed Setting bits to 11 enables them when C00000H to FFFFFFH is accessed TOSHIBA CORPORATION Table 3 6 1 Chip Select Wait Control Register TMP96C141AF TOSHIBA CORPORATION Code Name Address 7 6 5 4 3 2 1 BOE B0SYS BOCAS BOBUS BOW1 BOWO B0C1 BOCO 0 0 0 0 0 0 0 0 Bocs 5 0068H control 1 CS CAS 1 SYSTEM 0 CS0 0 16 bit 00 2WAIT 00 7FOOH 7FFFH register Enable only 1 CASO Bus 01 WAIT 01 400000H 1 8 bit 10 1WAIT n 10 800000H Bus 11 OWAIT 11 C00000H 1 15 5 B1CAS B1BUS Biwi B1WO B1C1 B1C0 Blockt W W W W W W W W 0 0 0 0 0 0 0 pics 0069H E 3 control 1 CS CAS 1 SYSTEM 0 CS1 0 16 bit 00 2WAIT 00 480H 7FFFH register Enable only 1 CAS1 Bus 01 1WAIT 01 400000H 1 8 bit 10 1WAIT n 10 800000H Bus 11 OWAIT 11 C00000H B2E 25 5 B2CAS B2BUS B2W1 B2W0 B2C1 B2C0 Block W W W W W W W W 1 0 0 0 0 0 0 pocs CS WATT O06AH 2 control 1 CS CAS 1 SYSTEM 0 Cg2 0
65. ouput ins max 10 35 m sog Input Leakage Current 0 02 Typ 0 0 lt Vi Vec 10 Output Leakage Current 0 05 Typ 10 02 lt 4 lt 0 2 Current RUN 26 Typ mA tose 16MHz lis 3 1 7 Ty n STOP Ta 20 70 C 0 2 Typ 50 pA 0 2 lt VinS Vec 0 2 STOP Ta 0 50 C 10 pA 0 2 lt VinS Ve 0 2 gue esee T v ete R RST RESET Pull Up Register 50 150 KQ C10 Pin Capacitance 10 pF tosc 1MHz VTH RESET NM INTO B 04 1 0 RK Pull Down Up Register 50 150 KQ Note is guaranteed for a total of up to 8 ports TOSHIBA CORPORATION 151 96 141 4 3 Electrical Characteristics TMP96C141AF 5V 10 Ta 20 70 C AMHz 20MHz Variable 16MHz 20MHz No Symhol Parameter Unit Min Max Min Max Min Max 1 tosc Osc Period x 50 250 62 5 50 5 2 te CLK width 2x 40 85 60 ns 3 tak 23 Valid gt CLK Hold 0 5x 20 11 5 ns 4 m CLK Valid gt A0 23 Hold 1 5x 70 24 5 ns 5 ni 0 15 Valid ALE fall 0 5x 15 16 10 ns 6 tla ALE fall A0 15 Hold 0 5x 15 16 10 ns 7 lu ALE High width x 40 23 10 ns 8 tic ALE fall RD WR fall 0 5x 30 1 5 ns 9 m RD WR rise ALE rise 0 5x 20 11 5 ns 10 tact A0 15 Valid RDAWR fall 25 38 25 ns 11 tach AQ 23 Valid
66. pin state when the bus is released is written amp Watch Dog Timer When the bus is released both internal memory and internal I O cannot be accessed But internal I O cantinues to operate So the watch dog timer contin ues to run Therefore be carefull about the bus releas ing time and set the detection timer of watch dog timer Watch Dog Timer The watch dog timer starts operation immediately after the reset is released When the watch dog timer is not used set watch dog timer to disable CPU High SpeeduDMA Only the LDC cr LDC r instruction can be used to access the control register like transfer source address register DMASn in the CPU TOSHIBA CORPORATION
67. register buffer will be shifted in Use of the double buffer makes the handling of small duty TREGO if 2 1 overflow is detected when the double buffer of waves easy TREGO is enabled Match with TREGO Up counter 9 Up counter Q2 2n 1 overflow Shiftinto TREGO TREG 0 value to be compared Register buffer Q2 Q3 A TREGO register buffer write Figure 3 7 15 Operation of Register Buffer Example To output the following PWM waves to TO1 pin at fc 16MHz To realize 63 5us of PWM cycle by 9T1 O 5us 16MHZ mL p ae 63 5us O 5ys 127 27 1 msi Consequently n should be set to 7 63 545 As the period of low level is 36us for 1 O 5us set the following value for TREGO is 54s 22 e 68 TOSHIBA CORPORATION MSB LSB 7 6 5 4 3 2 1 0 TRUN X 0 Stop timer 0 and clear it to 0 TMOD lt 1 1 1 0 0 1 TREGO lt 0 1 0 0 1 0 0 0 TFFCR lt x X X X 1 0 1 X Write 48H Clears TFF1 enables the inversion and double buffer TMP96C141AF Set 8 bit PWM mode cycle 2 1 and select T1 as the input clock P7CR lt x X X X 1 Set P71 as the TO1 pin P7FC lt x X X X 1 TRUN lt 1 X 1 Start timer 0 counting Note don t care no change Table 3 7 3 PWM Cycle and the Setting of 2 1 Counter PWM Cycle fc 16MHz PWM Cycle 20 MHz grt 914 9716 ort 4 9 16 254 31 5 31 7kHz 126 7 9kH
68. strobe for DRAM if address is within specified address area P50 P53 4 Input Port 5 Input port ANO AN3 Input Analog input Input to A D converter VREF 1 Input Pin for reference voltage input to A D converter AGND 1 Input Ground pin for A D converter P60 P63 4 0 Ports 60 63 1 0 ports that allow selection of 1 0 on a bit basis with pull up resistor PG00 Output Pattern generator ports 00 03 P64 P67 4 0 Ports 64 67 1 0 ports that allow selection of 1 0 on a bit basis with pull up resistor PG10 PG13 Output Pattern generator ports 10 13 P70 0 Port 70 1 0 port with pull up resistor T10 Input Timer input 0 Timer 0 inpu P71 0 Port 71 1 0 port with pull up resistor T01 Output Timer output 1 Timer 0 or 1 output P72 0 Port 72 1 0 port with pull up resistor T02 Output PWM output 2 8 bit PWM timer 2 output P73 0 Port 73 1 0 port with pull up resistor T03 Output PWM output 3 8 bit PWM timer 3 output P80 0 Port 80 1 0 port with pull up resistor Input Timer input 4 Timer 4 count capture trigger signal input INT4 Input Interrupt request pin 4 Interrupt request pin with programmable rising falling edge P81 0 Port 81 1 0 port with pull up resistor Input Timer input 5 Timer 4 count capture trigger signal input 5 Input Interrupt request pin 5 Interrupt request pin with rising edge P82 0 Port 82 1 0 port with pull up resistor T04 Output Timer output 4 Timer 4 output pin P83 0 Port 83
69. write 79 e P30 RD Output buffer P31 WR c QJ Reset Direction control on bit basis P3CR write 8 Function control 9 on bit basis oO Programmable P3FC write H e4 E Pch SU UP c S 5 5 TC Output gt 2 gt P32 HWR c t BICAK S B i Output buffer P35 BUSAK P36 R W P3 write P37 RAS HWR BUSAK R W RAS s 4 MM lt rN P3 read Figure 3 5 6 Port 3 P30 P31 P32 P35 P36 P37 30 TOSHIBA CORPORATION TMP96C141AF data bus Internal Internal Reset Direction control on bit basis D P3CR write P3 write Bea Internal Programmable pull up 1 1 P33 WAIT Output buffer P3 read WAIT Reset Direction control on bit basis P3CR write 2 Function O 1 control on bit basis S Ex P3FC write P ch Programmable pull up Internal P3 read BUSRQ 7 Figure 3 5 7 Port 3 P33 P34 _ P34 BUSRQ TOSHIBA CORPORATION 31 TMP96C141AF P3 0007H Read Write P3CR 000AH Read Write P3FC 000BH Read modify write is prohibited for registers P3CR and P3FC Port 3 Register After reset bit Symbol P37C After reset CHICO zx cars b Macon A Port 3 Function Register
70. 0 0 0 0 0 0 0 0 MOD RA g 22 00 Unused 00 TOO Trigger Transmission 1 CTS 1 Receive 1 Wakeup 01 UART 01 Baud rate generator data bit 8 Enable Enable Enable 10 UART 8bit 10 Internal clock 1 11 UART 9bit 11 Don t care BROCK1 BROCKO BR053 BR052 BR051 BR050 R W R W 0 0 0 0 0 0 0 BROCR Baud Rate 53H Control 00 0 fc 4 P Set frequency divisor E 01 92 fc 16 Fix at 0 0 10 05 fc 64 1 prohibited 11 032 1 256 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RBO Serial TB7 TB6 TB5 TB4 TB3 TB2 TB1 0 R Receiving W Transmission Buffer Undefined RB8 EVEN PE OERR PERR FERR SCLKS 10C R R W R Cleared to 0 by reading R W 0 0 0 0 0 0 0 Serial SCICR Channel 1 55 UST i 0 SCLK1 SUD Receiving 4 1 Parity F 1 Input data bit 8 1 Even Enable Overrun Parity Framing 1 pin 8 RXE WU SM1 5 0 561 SCO R W BE aoe 0 0 0 0 0 0 0 0 MOD PER 00 l O Interface 00 TOO Trigger Transmission Fix at 0 1 Receive 1 Wakeup 01 UART 01 Baud rate generator data bit 8 Enable Enable 10 UART 8 bit 10 Internal clock 1 11 UART 9bit 11 Don t care TOSHIBA CORPORATION 169 TMP96C141AF Serial Channel 2 2
71. 1 Don t care 11 Don t care Interrupt FF3RD DB3EN PWM INT PWM1M T3CLK1 T3CLKO PWM1S1 PWM1S0 R W mon d 0 0 0 0 0 0 0 rohibi EIMOU RMW TFF3 output 1 Double 0 Overflow 0 00 4 00 26 1 value Buffer Interrupt Mode 01 P4 fc 16 01 27 1 Enable 1 Compare 1 Timer 10 P16 fc 64 10 28 1 Match Mode 11 Don t care 11 Don t care Interrupt TOSHIBA CORPORATION 165 96 141 Timer Control 2 4 Symhol Name Address 7 6 5 4 3 1 0 FF3C1 FF3C0 FF3TRG1 FF3TRGO FF2C1 FF2C0 FF2TRG1 FF2TRGO W R W W R W 0 0 0 0 0 0 0 PFFCR B 2AH 00 Don t care 00 Prohibit TFF3 00 Don t care 00 Prohibit TFF2 Control 01 Set TFF3 Inverted 01 Set TFF2 Inverted 10 Clear TFF3 01 Invert if matched 10 Clear TFF2 01 Invert if matched 11 Don t care 10 Set if matched 11 Dont care 10 Set if matched Clear if overflowed Clear if overflowed 11 Clear if matched 11 Clear if matched set if overflowed set if overflowed 30H TREGAL 16 bit Timer Prohibit W Register 4L RMW Undefined 31H TREG4H 16 bit Timer Prohibit W Register 4H RMW Undefined 32H TREG5L 16 bit Timer Prohibit W Register 5L RMW Undefined 33H TREG5H 16 bit Timer Prohibit W Register 5H RMW Undefined capiL Capture 34H R Register 1L Undefined CAPIH _ Capture 35H R Register 1H U
72. 1 0 port with pull up resistor T05 Output Timer output 5 Timer 4 output pin TOSHIBA CORPORATION 96 141 Number of Pins 1 0 Functions P84 0 Port 84 1 0 port with pull up resistor 1 Input Timer input 6 Timer 5 count capture trigger signal input INT6 Input Interrupt request pin 6 Interrupt request pin with programmable rising falling edge P85 0 Port 85 1 0 port with pull up resistor 7 1 Input Timer input 7 Timer 5 count capture trigger signal input INT Input Interrupt request pin 7 Interrupt request pin with rising edge P86 3 0 Port 86 1 0 port with pull up resistor 06 Output Timer output 6 Timer 5 output pin P87 0 Port 87 1 0 port with pull up resistor INTO Input Interrupt request 0 Interrupt request pin with programmable level rising edge P90 4 0 Port 90 1 0 port with pull up resistor TXDO Output Serial send data 0 P91 3 0 Port 91 1 0 port with pull up resistor RXDO Input Serial receive data 0 P92 7 0 Port 92 1 0 port with pull up resistor CTSO Input Serial data send enable 0 Clear to Send P93 0 Port 93 1 0 port with pull up resistor TXD1 Output Serial send data 1 P94 P 0 Port 94 1 0 port with pull up resistor RXD1 Input Serial receive data 1 P95 0 Port 95 1 0 port with pull up resistor
73. 10 11 12 1 level priority can be set 3 halt modes RUN IDLE STOP The information contained herein is presented only as guide for the applications of our products No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others These TOSHIBA products are intended for usage in general electronic equipments office equipment communication equipment measuring equipment domestic electrification etc Please make sure that you consult with us before you use these TOSHIBA products in equip ments which require high quality and or reliability and in equipments which could have major impact to the welfare of human life atomic energy control spaceship traffic signal combustion control all types of safety devices etc TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA TOSHIBA CORPORATION 1 TMP96C141AF SCLK1 P95 INTA TI4 P80 ANO P50 AN1 P51 AN2 P52 AN3 P53 VREF AGND 10 BIT 4CH A D CONVERTER 00 P90 RXDO P91 50 P92 lt gt SERIAL I O CH 0 TXD1 P93 1 SERIAL I O RXD1 P94 lt gt een eer P PG 02 P62 lt gt
74. 3 1 1 62 03 63 4 61 PG10 P64 5 60 PG11 P65 6 59 PG12 P66 7 58 PG13 P67 8 57 0 70 9 1 56 1 71 10 1 55 2 72 11 1 54 TO3 P73 12 53 4 4 80 13 QFP80 52 5 5 81 14 51 TO4 P82 15 50 TOS P83 16 1 49 INT6 TI6 P84 17 48 INT7 TI7 P85 18 47 6 86 19 46 INTO P87 20 45 NMI 21 44 WDTOUT 22 1 43 RESET 23 42 24 i 41 VSS 25 40 X1 26 39 X2 27 38 EA 28 37 TXDO P90 29 36 RXDO P91 30 35 CTSO P92 31 34 TXD1 P93 32 33 Note Because the TMP96C141AF has an external ROM P00 to P17 pins are fixed to ADO to AD15 P30 to RD and P31 to WR Figure 2 1 Pin Assignment 80 pin QFP PA2 CS2 CAS2 41 51 51 50 50 P37 RAS P36 R W _ P35 BUSAK P34 BUSRQ P33 WAIT P32 HWR P31 WR P30 RD P27 A7 A23 P26 A6 A22 P25 A5 A21 P24 A4 A20 P23 A3 A19 P22 A2 A18 P21 A1 A17 P20 A0 A16 VSS P17 AD15 A15 P16 AD14 A14 P15 AD13 A13 P14 AD12 A12 P13 AD11 A11 P12 AD10 A10 P11 AD9 A9 P10 AD8 A8 P07 AD7 POG AD6 5 05 P04 AD4 P03 AD3 P02 AD2 PO1 AD1 POO ADO VCC ALE P95 SCLK1 P94 RXD1 TOSHIBA CORPORATION 96 141 2 2 Pin Names and Functions
75. 4 Input Fixed ANO AN3 Port6 P60 P67 8 0 T Bi PG00 PGO3 PG10 PG13 Port7 P70 1 0 T Bi T10 P71 0 T Bi TO1 P72 0 T Bi TO2 P73 0 T Bi TO3 Port P80 0 T Bi 14 4 P81 0 T Bi T15 INT5 P82 0 T Bi T04 P83 0 T Bi TO5 P84 0 T Bi T16 INTG P85 0 T Bi T17 INT7 P86 0 T Bi 06 P87 0 T Bi INTO Port9 P90 0 i Bi TXDO P91 0 Bi RXDO P92 0 T Bi CTSO P93 0 T Bi TXD1 P94 0 T Bi RXD1 P95 0 T Bi SCLK1 TOSHIBA CORPORATION 23 96 141 Resetting makes the port pins listed below function as e POO PO7 general purpose O ports e P10 P17 I O pins programmable for input or output function as e P30 input ports e P31 To set port pins for built in functions a program is required ADO 8 AD15 RD WR Bus release function The TMP96C141AF has the internal pull up and pull Since the TMP96C144AF has an external ROM some ports are permanently assigned to the CPU down resistors to fix the bus control signals at bus release Table 3 5 1 shows the pin condition at bus release BUSAK L Pin state at bus release Pin Name Port mode Function mode P00 P07 t status change these pins are not Hz These pins are Hz AD8 AD15 P30 RD These pins are Hz P31 WR Hz status after these pins are driven to high level P32 HWR The output buffer is OFF after these pins are drinen high P37 RA
76. 6 DM7 DM12 DM13 DM14 DM15 DM16 1 2 ALE ADO 15 Mee ere imeem 0 15 40 15 00 15 0 15 00 15 16 23 pry sourceboares 55142007 ve RD pa WR HWR Note 1 Note 2 9 2 xS High Speed cycle COUNT 0 DM23 DM24 CED V DO 15 4 0 15 Gab x ext area is 8bit address area is 8bit TOSHIBA CORPORATION This is added 2 states the case of the bus width of source address This is added 2 states the case of the bus width of destination High Speed cycle COUNT 0 Note4 Note3 This may be a dummy cycle with instruction queue buffer This is added 2 states the case of the bus width of stack address area is 8bit 96 141 The following timing chart is a high speed uDMA cycle of the Transfer Address Increment mode the other mode exe 2 Register Configuration CPU Control Register ChannelO DMASO DMADO DMACO DMAMO Channel1 DMAS1 Channel2 Channel3 DMAS3 DMAD3 DMAC3 lt 8bit lt 1 6bit 325 Transfer source address register 0 Transfer destination address register O Transfer counter register O Transfer mode register 0 Transfer source addres
77. 6C141AF e Stack pointer XSP for system mode to 100H e SYSM bit of status register SR to 1 Sets to system mode e FF2 to O bits of status register to 111 Sets mask register to interrupt level 7 MAX bit of status register to O Sets to minimum mode Bits RFP2 to 0 of status register to 000 Sets register banks to 0 When reset is released instruction execution starts from address 8000H CPU internal registers other than the above are not changed When reset is accepted processing for built in I Os ports and other pins is as follows Initializes built in I O registers as per specifications Sets port pins including pins also used as built in I Os to general purpose input output port mode sets I O ports to input ports Sets the WDTOUT pin to Watchdog timer is set to enable after reset Pulls up the CLK pin to 1 Sets the ALE pin to 0 96 141 3 2 Memory Figure 3 2 is a memory map of the TMP96C1 41 AF 000000H 000080H 000100H 000480H 008000H 008200H 010000H FFFFFFH Note Internal 1 0 Internal RAM 1K byte Interrupt entry area 32entries x 16 byte Direct area n m ND 64K byte area nn External memory 16M byte 16M byte area R R R R R8 16 48 16 system mode side to 100H Internal area The start address after reset is 8000H Resetting
78. 9 B 5 gl4 rogrammable ull up Selector E P9 read SCLKIN Figure 3 5 23 Port 95 P95 SCLK1 46 TOSHIBA CORPORATION w After reset bitSymboi _ P9SC 1 P93C 1 2 ee Port 9 I O setting DCE DCE P9 0019H Port 9 Function Register gt 5 104 i 3 After reset Note Only the TMP96CM40 TMP96PM40 TMP96C141A TMP96C041A have register P92F That is SCLKO cannot be specified for the TMP96C141 iQ PORT iQ PORT 0 PORT i0 PORT 1i SCLK1 HITXDI i1 SCLKO H1 TxDO P90 TxDO output setting Note P9FC lt P90F gt P9CR lt 0 gt 1 P93 TxD1 output setting Note P9FC lt P93F gt 1 P9CR lt P93C gt 1 P95 SCLK output setting Note Tosetthe TxD pin to open drain write 1 in bit 0 for TxDO pin or bit 1 for TxD1 pin ofthe ODE register P91 RXDO P94 RXDI pins do not have a register changing PORT FUNCTION Therefore this is the same as P70 TIO pin Figure 3 5 24 Registers for Port 9 TOSHIBA CORPORATION TMP96C141AF 47 96 141 3 6 Chip Select Wait Control TMP96C144AF has a built in chip select wait controller used to control chip select CSO CS2 pins wait WAIT pin and data bus size 8 o
79. C Output Data Output Enable STOP Input Data 1 Programmable Pull Down Resistance Input Enable 222_ i P5 ANO 3 Analog input channel select Analog input Input Input Data Input Enable P87 INTO vcc Output Data Output Enable se 4 Programmable STOP VCC pull Up Resistance Input Data lt 1 0 Schmitt P90 TXDO P93 TXD1 VCC Output Data Open Drain Enable STOP 4 Programmable VCC Pull Up Resistance 1 0 Input Data Input Enable TOSHIBA CORPORATION 175 96 141 NMI a m Input Schmitt e WDTOUT WDTOUT pop d our e CLK VCC VCC internal CLK P ch OUT STOP N ch internal reset Test circuit EA AM8 16 Input VCC P ch internal ALE OUT N ch e RESET 100kQ vcc Input Schmitt WDTOUT reset enable 176 TOSHIBA CORPORATION 96 141 e X1 X2 e VREF AGND clock oscillator STOP VREF Ladder Resistance A D Converter E NER AGND GND TOSHIBA CORPORATION 177 96 141 7 Guidelines and Restrictions 1 178 Special Expression Explanation of a built in I O register Register Symbol lt Bit Symbol gt ex TRUN lt TRUN gt Bit TORUN of Register TRUN Q Read Modify and Write Instruction An instruction whic
80. C00000H Note 1 After reset only B After reset the program starts in 16 bit data bus 2 wait state 2 is set to enable Note 2 These registers can be accessed only in system mode Note 3 TMP96C1444 for internal RAM less is 7FFFH TOSHIBA CORPORATION 173 96 141 6 Port Section Equivalent Circuit Diagram STOP This signal becomes active 1 when the hold mode Reading The Circuit Diagram setting register is set to the STOP mode and the CPU Basically the gate singles written are the same as executes the HALT instruction When the drive enable bit DRIVE is set to 1 however STP remains at 0 th for the stan MOS IC 2 m on The input protection resistor ranges from several tens of The dedicated signal is described below ADO AD7 P1 AD8 15 A8 15 P2 2 23 7 Output Data Output Enable STOP Input Data vo UNS 1 I N ch Programmable 1 Pull Down Input Enable SEES Resistance 2 only PORT2 P30 RD P31 WR VCC Output Data OUT STOP e P32 37 P40 41 P6 P80 86 P91 92 P94 95 vcc Output Data 4 Programmable VCC Pull Up Output Enable Resistance STOP Input Data TRY Input Enable 1 0 174 TOSHIBA CORPORATION TMP96C141AF e P42 CS2 CAS2 VC
81. DCR 1 Watchdog Timer Mode Register WDMOD Setting the detecting time of watchdog timer lt WDTP gt This 2 bit register is used to set the watchdog timer interrupt time for detecting the runaway This register is initialized to WOMOD WDTP1 0 00 when reset and therefore 2 fc is set The number of states is approximately 32 768 Q Watchdog timer enable disable control register lt WDTE gt When reset WDMOD WDTE is initialized to 1 enable the watchdog timer e Disable control wDMD lt 0 X x WR 1 0 1 1 0 0 0 1 Enable control Set WDMOD WDTE to 1 Watchdog timer clear control The binary counter can be cleared and resume WDCR 0 1 0 0 1 1 1 0 TOSHIBA CORPORATION TMP96C141AF To disable it is necessary to clear this bit to 0 and write the disable code B1H in the watchdog timer control register WDCR This makes it difficult for the watchdog timer to be disabled by runaway However it is possible to return from the disable state to enable state by merely setting lt WDTE gt to 1 Watchdog timer out reset connection lt RESCR gt This register is used to connect the output of the watchdog timer with RESET terminal internally Since WDMOD lt gt is initialized to 0 at reset a reset by the watchdog timer will not be performed Watchdog Timer Control Register WDCR This register is used to disable and clear the binary cou
82. Figure 3 10 9 Output Waveforms of 4 Phase 2 Step Excitation Normal Rotation The operation when channel 0 is selected is 1 step excitation will be selected when only one bit is set explained below to 1 during the initialization of PG while 4 phase 2 step The output latch of PGO also used as P6 is shifted excitation will be selected when two consecutive bits are at the rising edge of the trigger signal from the timer to be set to 1 output to the port The value in the shift alternate registers are ignored The direction of shift is specified by PGO1CR when the 4 phase 1 step 2 step excitation mode is lt CCWO gt Normal rotation PGOO PG01 PG02 gt selected when lt CCWO gt is set 0 reverse rotation Figure 3 10 10 shows the block diagram PGOO lt 01 lt PGO2 lt when 1 Four phase PGO Output latch Shift alternate Register L PG03 P63 bus _ PG02 P62 1 P61 5 01 E b4 PGoo P60 _ is showing to shift the signal at the rising edge of trigger signal from timer Figure 3 10 10 Block Diagram of 4 Phase 1 Step Excitation 2 Step Excitation Normal Rotation TOSHIBA CORPORATION 111 96 141 4 Phase 1 2 Step Excitation phase 1 2 step excitation when channel 0 is selected Figure 3 10 11 shows the output waveforms of 4 Trigger signal from timer
83. ION 96 141 4 8 Timing Chart for Interface Mode CLK tscv SCLK OUTPUT DATA TxD tsRD tHSR INPUT DATA gt lt TOSHIBA CORPORATION 157 96 141 4 9 Timing Chart for Bus Request BUSRQ BUS Acknowledge BUSAK note CLK gt lt iBRC BUSRQ tcBAL ADO AD15 A0 A23 50 52 RAS CASO CAS2 RD WR HWR ALE Variable 16MHz 20MHz Symhol Parameter Unit Min Max Min Max Min Max BUSRQ setup time for CLK 120 120 120 ns tCBAL CLK BUSAK falling edge 1 5x 120 214 195 ns CBAH CLKBUSAK rising edge 0 5x 40 71 65 ns Output buffer is off to BUSAK 0 80 0 80 0 80 ns tana BUSAK output buffer is on 0 80 0 80 0 80 ns Note 1 The Bus will be released after the WAIT request is inactive when the BUSRQ is set to 0 during Wait cycle Note 2 This line only shows the output buffer is off states They don t indicate the signal levels are fixed After the bus is released the signal level is kept dynamically before the bus is released by the external capacitance Therefore to fix the signal level by an external resistance under the bus is releasing the design must be carefully because of the level fix will be delayed The internal programmable pull up pull down resistance is switched active by the internal signal 158 TOSHIBA CORPORATION TMP96C141AF 4 10 Interru
84. QST5 TFF5 invert trigger 0 Disable trigger 1 Enable trigger Invert Invert when the when the UC value is up counter loaded to matches CAP2 TREGS don t CAPIIN CAP12M1 i CAP12MO TACLK1 2 TACLKO 0 Soft iCapture timing 1 0 4 Timer 4 source clock Capture 00 Disable P Clear INTAoccursatriseedge Enable eas 01 57 01 gT1 INT4 occurs at rise edge 10 4 10 ZI INTA occurs at fall edge i HITEET INT4 occurs at rise edge care Capture timing of timer4 Capture control Capture disable CAP1 at TIA rise 4 control Interrupt occurs at the rise edge 4 1 2 at TI5 rise input CAP1 at TIA rise at the fall edge of 4 INT 2 at 4 fall Interrupt occurs at TFF1 rise at the rise edge A CAP2 at TFF1 fall of 4 1 input Software capture The up counter4 value is loaded to CAP1 software capture Always read as 1 I Timer flip flop 5 TFF5 invert trigger Trigger disable Invert Prohibition Trigger enable Invert permission CAP2T5 Invert when the up counter value is loaded to CAP2 EQ5T5 Invert when the up counter matches TREG5 Figure 3 9 4 16 Bit Controller Register T4MOD 2 2 88 TOSHIBA CORPORATION 96 141 BH TAFFCR bit Symbol
85. Registers for Port 2 28 TOSHIBA CORPORATION 3 5 4 Port 3 P30 P37 Port 3 is an 8 bit general purpose port can be set on a bit basis but note that P30 and P31 are used for output only I O is set using control register PSCR and function register P3FC Resetting resets all bits of output latch P3 control register P3CR bits and 1 are unused and function register to 0 Resetting also outputs 1 from P30 and P31 sets P32 to P37 to input mode and connects a pull up resistor In addition to functioning as general purpose port Port also functions as an I O for the CPU s control status sig nal TOSHIBA CORPORATION TMP96C141AF With the TMP96C141AF when P30 pin is defined as RD signal output mode lt P30F gt 1 clearing the output latch register P30 to 0 outputs the RD strobe used for the pseudo static RAM from the P30 pin even when the internal address area is accessed If the output latch register lt P30 gt remains 1 the RD strobe signal is output only when the external address area is accessed With the TMP96C141AF TMP96C041AF which comes with an external ROM Port 30 outputs the RD signal P31 the WR signal regardless of the values set in function registers P30F and P31F 29 96 141 Reset For TMP96C141AF mode Function control on bit basis E i
86. S T These pins are added in the internal resistor of pull up It s no relation for the value of output latch P36 RAW P40 50 50 T P41 CS1 CAS1 P42 52 52 T 97 P20 P27 The output buffer is OFF after these pins are drinen high A16 A23 T These pins are added in the internal resistor of pull down P42 CS2 CAS2 It s no relation for the value of output latch 9 P42 has the resistor of programmable pull down but when the bus are released 42 pin is added a resistor of pull That is when it is used for bus release BUSAK 0 the pins of below need pull up or pull down resistor for an external circuit PO ADO7 TMP96C141AF a 00 07 ADO 7 10 17 AD8 15 P20 P27 Internal A16 23 pull down P30 RD P31 WR P32 HWR 6 9 Internal pull up P37 RAS P4 P10 P17 AD8 AD15 P30 RD up P31 WR When the bus is released both internal memory and internal I O cannot be accessed But the internal I O continues to run Therefore be careful about releasing time and set the Setection time WDT Address Data bus ADO 15 Higher address bus A16 23 System control bus Figure 3 5 Example of external bus interface using bus release function 24 TOSHIBA CORPORATION 96 141 3 5 1 Port 0 POO P07 3 5 2 Port 1 P10 P17 Port O is an 8 bit general purpose I O port I O
87. SCLK Input Mode Connection 132 TOSHIBA CORPORATION 96 141 Transmission time the CPU writes data in the transmission buffer When all data is output INTES1 lt ITX1C gt will be set to generate In SCLK output mode 8 bit data and synchronous clock interrupt are output from TxD pin and SCLK pin respectively each Timing to write transmission data SCLK output LA L4 LA TxD bito X bit TXDSFT ux ss c sU b ITX1C a est interrupt requ Figure 3 11 19 Transmitting Operation in I O Interface Mode SCLK Output Mode In SCLK output mode 8 bit data are output from TxD1 When all data are output INTES1 lt ITXIC gt will be set pin when SCLK input becomes active while data are to generate INTTX1 interrupt written in the transmission buffer by CPU SCLK input c LET Ru um SCLKC 0 Rising edge mode SCLK inpu put 5 1 Falling edge mode TxD bito X bit bits X bite X bit7 TxDSFT A INTTX1 interrupt request Figure 3 11 20 Transmitting Operation in Interface Mode SCLK Input Mode TOSHIBA CORPORATION 133 96 141 Receiving IRX1C is cleared by reading the received data When 8 bit data are received the data will be trans ferred in the receiving buffer 2 SC1BUF at the timing shown below and INTES1 lt IRX1C gt will be set again to generate INTRX1 interrupt
88. Supplement 1 Supplement 2 Access priority is highest for built in I O then built in memory and lowest for the chip select wait controller External areas other than CSO to CS2 are accessed in 16 bit data bus 0 wait mode When using the chip select wait controller do not specify the same address area more than once However when addresses 7FOOH 7FFFH for CSO and 480H 7FFFH for CS1 are specified in other words specifications overlap only the CSO setting pin is active TOSHIBA CORPORATION 51 96 141 3 6 3 Example of Usage nected to the TMP96C144AF In this example a ROM is con Figure 3 6 1 is an example in which an external memory is con nected using 16 bit Bus a RAM is connected using 8 bit Bus D Q n E cs Upper byte D Q __ ROM Figure 3 6 1 Example of External Memory Connection ROM 16 bits RAM and 8 bits TMP96C141 Address bus CS Lower byte ROM OE Resetting sets pins CSO to CS2 to input port mode CSO low due to an internal pull down resistor The program used to and CS1 are set high due to an internal pull up resistor CS2 set these pins is as follows EQU OEH EQU 10H BOCS EQU 68H B1CS EQU 69H B2CS EQU LD BOCS 90H CS0 8 bits 2WAIT 7FOOH 7FFFH LD B1CS 9CH CS1 8 bits OWAIT 480H 7EFFH LD B2CS 84H CS2 16 bits 1WAIT 8000H 3FFFFFH LD P4CR 07H CSO CS1 CS2 o
89. TFH DMA3V8 DMA3V7 DMA3V6 DAM3V5 DMA3V4 DMA3V request Prohibit Vector RMW W 0 0 0 0 0 IOIE W W W 0 0 0 78H Interrupt Input m 0 INTO IIMC Prohibit Mode Control RMW 1 INTO edge 1 Operate inut mode even at p 1 INTO NMI rise enable level edge mode 172 TOSHIBA CORPORATION 9 Chip Select Wait Controller TMP96C141AF Symbol Name Address 7 6 5 4 3 2 1 0 BOE BOSYS BOCAS BOBUS BOW1 BOWO B0CO W W W W W W W W Block 0 CS WAIT 68H 0 0 0 0 0 0 0 0 B0CS Prohibit control RMW an 00 2WAIT 00 7FOOH 7FFFH register 105 1 5 0 050 0 16bit Bus 01 1WAIT 01 400000H Enable only 1 CASO 1 8bit Bus 10 1WAIT n 10 800000H 11 OWAIT 11 C00000H B1E 15 5 B1CAS B1BUS B1W1 1 0 B1C1 B1C0 W W W W W W W W Block 1 CS WAIT 69H 0 0 0 0 0 0 0 0 B1CS Prohibit control RMW S 00 2WAIT 00 480H 7FFFH register 105 1 SYSTEM 0 51 0 16bit Bus 01 1WAIT 01 400000H Enable only 1 CAS1 1 8bit Bus 10 1WAIT n 10 800000H 11 0 11 C00000H 2 25 5 B2CAS B2BUS B2W1 B2W0 B2C1 B2C0 W W W W W W W W Block 2 CS WAIT 0 0 0 0 0 0 0 0 B2CS Prohibit f z control RMW a 00 2WAIT 00 8000H register 65 1 5 5 0 052 0 16bit Bus 01 1WAIT 01 400000H Enable only 1 CAS2 1 8bit Bus 10 1WAIT n 10 800000H 11 0WAIT 11
90. TOSHIBA TLCS 900 Series TMP96C141AF CMOS 16 bit Microcontroller TMP96C141AF 1 Outline and Device Characteristics The TMP96C141AF is high speed advanced 16 bit microcon troller developed for controlling medium to large scale equip ment The TMP96C144 AF is housed in an 80 pin flat package Device characteristics are as follows 1 Original 16 bit CPU TL CS 90 instruction mnemonic upward compatible 16M byte linear address space General purpose registers and register bank system 16 bit multiplication division and bit transfer arithmetic instructions High speed micro DMA 4 channels 1 6us 2 bytes 20 2 2 Minimum instruction execution time 200ns Q 20MHz 3 Internal RAM 1K byte The information contained here is subject to change without notice Internal ROM None 4 External memory expansion Can be expanded up to 16M bytes for both programs and data e Can mix 8 and 16 bit external data buses Dynamic data bus sizing 8 bit timers 2 channels 8 bit PWM timers 2 channels 16 bit timers 2 channels Pattern generators 4 bits 2 channels Serial interface 2 channels 10 bit A D converter 4 channels Watchdog timer Chip select wait controller 3 blocks 3 Interrupt functions 3 CPU interrupts SWI instruction privileged violation and Illegal instruction 14 internal interrupts external interrupts 14 I O ports 15 Standby function 5 6 7 9 9
91. TREG7L 62H ADREG1L 3H 23H TREG1 43H TREG7H 63H ADREG1H 4H P1CR 24H TMOD 44H CAP3L 64H ADREG2L 5H P1FC 25H TFFCR 45H CAP3H 65H ADREG2H 6H P2 26H TREG2 46H CAP4L 66H ADREG3L P3 27H TREG3 47H CAP4H 67H ADREG3H 8H P2CR 28H POMOD 48H T5MOD 68H BOCS 9H P2FC 29H 00 49H T5FFCR 69H B1CS AH P3CR 2AH PFFCR 4AH 6AH B2CS BH P3FC 2BH 4BH 6BH CH P4 2CH ACH PGOREG 6CH DH P5 2DH ADH PG1REG 6DH EH 2EH 4EH PGO1CR 6EH FH 2FH 4FH 6FH 10H P4FC TREG4L 50H SCOBUF 70H INTEOAD 11H TREG4H 51H SCOCR INTE45 12H P6 32H TREGSL 52H SCOMOD INTE67 13H P7 33H TREG5H 53H BROCR 73H INTET10 14H P6CR 34H CAP1L 54H SC1BUF INTEPW10 15H P7CR 35H CAP1H 55H SC1CR 75H INTET54 16H PeFC 36H CAP2L 56H SC1MOD 76H INTET76 17H P7FC 37H CAP2H 57H BRICR 77H INTESO 18H P8 38H TAMOD 58H ODE 78H INTES1 19H P9 39H TFF4CR 59H 79H 1AH P8CR T45CR 5AH 1BH P9CR 3BH 5BH 7BH IIMC 1CH P8FC 3CH 5CH WDMOD DMAOV 1DH P9FC 3DH 5DH WDCR DMA1V 1EH 3EH 5EH ADMOD DMA2V 1FH 3FH DMA3V TOSHIBA CORPORATION 161 96 141
92. TTO INTT1 E Figure 3 9 16 Frequency Measurement For example if the value for the level 1 width of of the 8 bit timer is set to 0 5 sec and the differ ence between CAP1 and CAP2 is 100 the frequency will be 100 0 5 sec 200 Hz TOSHIBA CORPORATION amp Pulse Width Measurement This mode allows measuring the H level width of an external pulse While keeping the 16 bit timer event counter counting free running with the internal clock input the external pulse is input through the pin Then the capture function is used to load the UCA values into and 2 at the rising edge and falling edge of the Count clock internal clock 4 external pulse Loading UC16 into CAP1 Loading UC16 into CAP2 4 96 141 external trigger pulse respectively The interrupt INT4 occurs at the falling edge of T14 The pulse width is obtained from the difference between the values of CAP1 and 2 and the internal clock cycle For example if the internal clock is 0 8 microseconds and the difference between CAP1 and 2 is 100 the pulse width will be 100 x 0 8 80 microseconds Figure 3 9 17 Pulse Width Measurement Only in this pulse width measuring mode TAMOD lt 12 1 O gt 10 external interrupt INT4 occurs at the falling edge of TIA pin input In other modes it occurs at the rising edge The width of L
93. Up counter This is an 8 bit binary counter which counts up by the input clock pulse specified by TMOD The input clock of timer O is selected from the external clock from T10 pin and the three internal clocks T1 8 fc 4 32 fc and 9T16 128 fc according to the set value of TMOD register The input clock of timer 1 differs depending on the operation mode When set to 16 bit timer mode the overflow output of timer O is used as the input clock When set to any other mode than 16 bit timer mode the input clock is selected from the internal clocks T1 8 fc 6 T16 128 fc and 1256 2048 fc as well as the comparator output match detection signal of timer O according to the set value of TMOD register Example When TMOD lt 10 1 gt 01 the over flow output of timer O becomes the input clock of timer 1 16 bit timer mode When TMOD lt T10M1 0 00 and TMOD lt T1CLK1 0 gt 01 T1 8 fc becomes the input of timer 1 8 bit timer mode Operation mode is also set by TMOD register When reset it is initialized to TMOD TO1M1 O gt 00 whereby the up counter is placed in the 8 bit timer mode The counting and stop and clear of up counter can be controlled for each interval timer by the timer operation control register TRUN When reset all up counters will be cleared to stop the timers TOSHIBA CORPORATION Note Timer register This is an 8 bit register for setting an interval time Wh
94. WMOM T2CLK T2CLKO POMOD bit Symbol 0028H Read Write 4 0 2 00 050 00 After reset Flip flop 1 Double nA NM 00 gP1 fc 4 00 26 1 F2 i wo i 91 spa fc 16 01 271 Y interrupt 1 Tim 1 Function loutput i Enable iE Mer i 10 16 4 64 10 28 1 21 compare mode data amp match 11 Don t care 11 Don t care interrupt Read modify write is prohibited Select PWMO cycle P1 fc 4 4 fc 16 g P16 fc 64 Don t care MEE PWM timer Flip flop2 TFF2 output value TO2 Figure 3 8 4 8 Bit PWMO Mode Control Register 74 TOSHIBA CORPORATION TMP96C141AF 0029 FF3RD Read Write After reset Flip flop F F3 output data Function Read modify write is prohibited DB3EN Buffer3 Enable H T3CLK1 T3CLKO PWM1S1 PWMISO 11 Double 20 2 1 Compare 00 26 1 i 01 27 1 10 28 1 11 Don t care 00 gP1 fc 4 01 gP4 fc 16 10 gP16 fc 64 11 Don t care 0 PWM overflow mode interrupt mode and match interrupt Select 1 cycle 26 1 27 1 28 1 Don t care Select PWM 1 input clock 00 P1 fc 4 4 PA fc 16 4 P16 fc 64
95. WOMO 0 0 0 0 0 RW w 0 0 0 0 0 0 0 0 5 IT5M2 5 1 ITSMO ITAC IT4M2 IT4M1 ITAMO RW w 0 0 0 0 0 0 0 0 INTTR7 7 INTTR6 TREG6 IT7C IT7M2 IT7M IT7MO IT6C IT6M2 IT6M1 IT6MO RW 1 w 6 0 t 0 0 ITX0M2 0 0 E 0 0 0 0 0 0 INTTX1 INTRX1 ITX1C ITX1M2 ITX1M1 ITX1MO IRX1C IRX1M2 IRX1M1 IRX1MO ITX0M 1 ITXOMO IRXOC IRXOM2 IRXOM1 IRXOMO 0 Function Write Prohibit interrupt request Set interrupt request level to 1 Set interrupt request level to 2 Set interrupt request level to 3 Set interrupt request level to 4 Set interrupt request level to 5 Set interrupt request level to 6 Prohibit interrupt request TOSHIBA CORPORATION 171 96 141 Interrupt Control 2 2 Symbol Name Address 7 6 5 4 3 2 1 0 uDMAO start vector DMA 0 7CH DMAOV8 DMAOV DMAOV6 DAMOVS DMAOVA DMAOV request Prohibit Vector RMW W 0 0 0 0 0 start vector DMA 1 01 8 DMAiV DMAiV6 DAMIV5 DMAIV4 DMA1V request Prohibit Vector RMW W 0 0 0 0 0 start vector DMA 2 TEH DMA2V8 DMA2V7 DMA2V6 DAM2V5 DMA2V4 DMA2V request Prohibit Vector RMW W 0 0 0 0 0 uDMAS start vector DMA 3
96. al purpose I O port Port 70 also functions as an input clock pin TIO Port 5 Reset P7CR write P7 write Direction control on bit basis TMP96C141AF 71 as an 8 bit timer output TO1 Port 72 as a PWMO output TO2 and Port 73 as a PWM1 output pin Writing 1 in the corresponding bit of the Port 7 function register P7FC enables output of the timer Resetting resets the function regis ter P7FC value to O and sets all bits to ports S P ch Programmable pull up 70 TIO 3 a Selector P7 read A TIO lt o Reset n Direction control on bit basis c i A 2 P7CR write E Function control on bit basis A P7FC write S Programmable P ch Output latch 1 pull up D A S P7 write Selector 71 73 TO1 TO3 Timer F F OUT 1B 101 Timer 1 TO2 Timer 2 Timer 3 E Selector P7 read TOSHIBA CORPORATION Figure 3 5 15 Port 7 39 TMP96C141AF Port 7 Register Read Write 00139 fcn Sc i P72C 7C 7 0015H H Port 7 I O setting op Port 7 Function Register 1 output 7 i 6 i 5 i 4 3 3 i H 0017H i After reset 0 0 i 0 PORT 0 PORT 0 PORT bins H TO3 1 02 1 70 Read modify write is Setting P71 as 1 P7FC lt P71F gt 1 P7CR
97. ation Set an initial value Start timer 0 equal to the trigger signal of timer flip flop TFF1 TFF4 TFF5 and TFF6 and differs as shown in Table 3 10 1 depending on the operation mode of the timer Table 3 10 1 Select of Trigger Signal TFF1 Inversion PG Shift 8 bit timer mode Selected by TFFCR lt TFF1IS gt when the up counter value matches TREGO or TREG1 value 16 bit timer mode When the up counter value matches with both TREGO and TREG1 values The value of up counter TREG1 28 TREGO output mode When the up counter value matches with both TREGO and TREG1 When the up counter value matches TREG1 value PPG cycle PWM output mode When the up counter value matches TREGO value and PWM cycle Trigger signal for PG is not generated Note shift PG TFFCR lt TFF1IE gt must be set to 1 to enable TFF1 inversion Channel 1 of PG can be synchronized with the 16 bit timer Timer 4 Timer 5 In this case the PG shift trigger signal from the 16 bit timer is output only when the up counter UC4 UC5 value matches TREGS TREG When using a trigger signal from Timer 4 set either 114 TAFFCR lt 5 4 gt or TAMOD lt EQ5ST5 gt to 1 and a trigger is generated when the value UC4 and the value TREG5 match When using a trigger signal from Timer 5 set TSFFCR EQ7T6 to 1 Generates a trigger when the value in UC5 and the value TREG7 match
98. capture registers one of them applies double buffer two comparators capture input con troller and timer flip flop and the control circuit Timer event counter is controlled by four control regis ters TAMOD T5MOD TAFFCR TSFFCR TRUN and T45CR Figure 3 9 1 and 2 show the block diagram of 16 bit timer event counter timer 4 and timer 5 TOSHIBA CORPORATION 96 141 Internal bus 5 Upper byte Lower byte Upper i Lower byte Capture register 1 Capture register 2 CAP1 CAP2 T LA Trigger TAMOD CAP2T5 05 5 gt TAFFCR T4MOD lt CAPIIN gt Software Capture gt F is 4 is control od TAMOD 5 lt 12 1 0 gt 16 bit up counter MO 4T16 e Selector vm 4 gt A TRUN lt T4RUN gt trigger gt gt nd TAMOD TACLK1 0 gt 22 Match Match detection detection Selector fone 5 TREG4 WR Register buffer4 T45CR lt DB4EN gt Upper byte Lower byte Upper byte Lower byte Internal bus Figure 3 9 1 Block Diagram of 16 Bit Timer Timer 4 TOSHIBA CORPORATION 85 96 141 f Internal bus 5 Upper byte Lower byte Upper byte Capture register 3 CAP3 Trigger Lower byte TSMOD lt CAP3IN gt TSFFCR Software Capture Capture Timer
99. channel ends in fixed conversion channel mode or when A D conversion of the last channel ends in channel scan mode A D conversion repeat mode For both fixed conversion channel mode and con version channel scan mode INTAD should be disabled when in repeat mode Always set the INTEOAD at 000 that disables the interrupt request Write 0 to ADMOD lt REPET gt to end the repeat mode Then the repeat mode will be exited as soon as the conversion in progress is completed Storing the A D Conversion Result The results of A D conversion are stored in ADREGO to ADREGS registers for each channel In repeat mode the registers are updated whenever conversion ends ADREGO to ADREGS3 are read only registers Reading the A D Conversion Result The results of A D conversion are stored in ADREGO to ADREGS registers When the contents of one of ADREGO to ADREGG registers are read ADMOD lt EOCF gt will be cleared to 0 Setting example When the analog input voltage of the ANG pin is A D converted and the result is stored in the memory address FF10H by A D interrupt INTAD routine 143 96 141 Main setting r INTEOAD lt 1 1 0 L ADMOD lt x X 0 0 0 1 1 1 INTAD routine WA ADREG3 WA gt gt 6 00FF10H lt WA Enable INTAD and sets interrupt level 4 Specify AN3 pin as an analog input channel and starts A D conversion in high speed mode Read ADREG3L and ADREG3H values and writes to WA 16 bit
100. cified are divided into four parts Addresses from 000000H to 3FFFFFH are divided differently 7FOOH to 7FFFH is specified for CSO 480H to 7FFFH for C81 and 8000H to 3FFFFFH for CS2 The reason is that a device other than ROM i e RAM or I O might be connected externally The addresses 7FOO to 7FFFH 256 bytes for 50 are mapped mainly for possible expansions to external I O The addresses 480H to 7FFFH approximately 31K TMP96C141AF bytes for CS1 are mapped there mainly for possible exten sions to external RAM The addresses 8000H to 3FFFFFFH approximately 4Mbytes for CS2 are mapped mainly for possible extensions to external ROM After reset CS2 is enabled in 16 bit bus and 2 wait With the TMP96C141AF which does not have a built in ROM the program is externally read at address 8000H in this setting 16 bit bus 2 wait With the TMP96CM40F TMP96PMAOF which has a built in ROM addresses from 8000H to FFFFFH are used as the internal ROM area CS2 is disabled in this area After reset the CPU reads the program from the built in ROM in 16 bit bus O wait mode CS0 CST CS2 000000H 7 00 B1C1 0 00 8000H 0 00 400000H B2C1 0 00 800000H BOC1 0 01 B1C1 0 01 B2C1 0 01 C00000H 0 10 B1C1 0 10 B2C1 0 10 FFFFFFH BOC1 0 11 B1C1 0 11 B2C1 0 11 Mainly for 1 0 Mainly for RAM Mainly for ROM
101. d Write After reset 0 Function Read modify write is prohibited NM INTO input enable Note 1 INTO To INTO edge mode gt INTO level Can be operated in NMI rising edge input enable mode NMI rising edge enable E l INTO disable P87 function only 1 Input enable 0 Interrupt request generation at falling edge zl Note The INTO can also be used for standby release as described later Even if the pin is not used for standby release setting this register to 0 maintains the port function during standby mode Interrupt Pin name E Rising and falling um EE edges Interrupt request generation at rising falling edge r INTO level enable L 0 Rising edge detect interrupt 1 High level interrupt Setting of External Interrupt Pin Functions EN Falling edge Setting method IIMC lt NMIREE gt 0 IIMC lt NMIREE gt 1 P87 Risingedge T Level IIMC lt IOLE gt 0 lt IOIE gt 1 IIMC lt IOLE gt 1 lt IOIE gt 1 Fa Rising edge T4MOC lt CAP12M1 0 gt 0 00r0 1 or 1 1 X Falling edge lt 12 1 0 gt 1 0 20 Rising edge _ PE zz E Falling edge Rising edge T5MOC lt CAP34M1 0 gt 0 0 0r 0 1 or 1 1 T5MOD lt CAP34M1 0 gt 1 0 P85 F Rising edge
102. d below for channel O The output latch of PGO shared by P6 and the shifter alternate register SAO for Pattern Generation are shifted at the rising edge of trigger signal from the timer to be output to the port The direction of shift is set by PGO1CR lt CCWO gt Figure 3 10 12 shows the block diagram PGO Output PGO3 P63 PGO2 P62 PGO1 P61 PGOO P60 isshowing to shift the signal at the rising edge of trigger signal from the timer Figure 3 10 12 Block Diagram of 4 Phase 1 2 Step Excitation Normal Rotation TOSHIBA CORPORATION 113 96 141 Setting example drive channel 0 PGO by 4 phase 1 2 step excitation normal rotation when 7 6 5 4 3 2 1 0 TRUN lt X 0 0 0 X X 0 1 TFFCR x X X 0 0 1 0 TREO e P6CR lt 1 1 1 P6FC lt 1 1 1 PGOICR lt 0 0 1 1 PGOREG lt 1 1 0 0 0 0 0 TRUN lt 1 1 Note x don t care no change 3 Trigger Signal From Timer The trigger signal from the timer which is used by PG is not timer O is selected set each register as follows Stop timer 0 and clears it to zero Set 8 bit timer mode and selects 1 as the input clock of timer 0 Clear TFF1 to zero and enables the inversion trigger by timer 0 Set the cycle in timer register Set P60 P63 bits to the output mode Set P60 P63 bits to the PG output Select PGO 4 phase 1 2 step excitation mode and normal rot
103. e an interrupt INTT4 INTTS INTTG INTT7 respectively The up counter UC4 UC5 is cleared only when UC4 UC5 TRUN e x 0 INTET54 lt 1 1 0 0 1 0 0 T4FFCR lt 1 1 0 0 0 0 1 T4M0D lt 0 0 1 0 0 1 01 10 11 IREBE e TRUN 1 X 4 qe s Note don t care no change 2 16 bit Event Counter Mode In 16 bit timer mode as described in above the timer can be used as an event counter by selecting the external clock 4 TI6 pin input as the input clock To read the value of the TOSHIBA CORPORATION TMP96C141 AF matches TREG5 TREG The clearing of up counter UC4 UC5 be disabled by setting TAMOD lt CLE gt T5MOD CLE 0 Timer Flip Flop TFF4 TFF6 This flip flop is inverted by the match detect signal from the comparators and the latch signals to the cap ture registers Disable enable of inversion can be set for each element by TAFFCR lt 2 4 CAP1T4 EQSTA EQ4T4 gt T6FFCR lt CAP4T6 6 EQ7T6 EQGT6 TFF4 TFF6 will be inverted when OO is written in T4FFCR lt TFF4C1 O gt T6FFCR lt TFF6C1 O gt Also it is set to 1 when 10 is written and cleared to O when 10 is written The value of TFF4 TFF6 can be output to the timer output pin TO4 also used as P82 and TO6 also used as P86 Timer Flip Flop TFF5 This flip flop is inverted by the match detect signal from t
104. e cycle of TO1 to TREG1 Assign P71 as T01 Assign P60 63 as PGO Set PGO in 4 phase 1 step excitation mode Set an initial value Start timer 0 and timer 1 115 96 141 3 11 Serial Channel as well as for I O extension The TMP96C141AF contains two serial I O channels for full The serial channel has the following operation modes duplex asynchronous transmission UART e O interface mode Mode O To transmit and receive I O data as well as channel 1 only the synchronizing signal SCLK for extending 1 Note TMP96C141AF TMP96C041 AF TMP96CMAOF TMP96PMAOF with Channel and 1 r Mode 1 7 bit data Asynchronous transmission L Mode 2 8 bit data UART mode channel 0 and 1 L Mode 3 9 bit data In mode 1 and mode 2 a parity bit can be added Mode Figure 3 11 1 shows the data format for one frame in 3 has wake up function for making the master controller start each mode slave controllers in serial link multi controller system Mode 0 1 0 interface mode Transfer direction Mode 1 7 bit UART mode confor Vor 2 2 Mode 2 8 bit UART mode fes Y e OE Mode 3 9 bit UART mode th COGO GC When bit 8 1 address select code is denoted When bit 8 0 data is
105. e memory address of each timer register is as fol lows TREGO 000022H TREG1 000023H All registers are write only and cannot be read Comparator A comparator compares the value in the up counter with the values to which the timer register is set When they match the up counter is cleared to zero and an interrupt signal INTTO INTT1 is generated If the timer TOSHIBA CORPORATION the register buffer as well as the timer register while wnen lt DBEN gt 1 only the register buffer is written flip flop inversion is enabled the timer flip flop is inverted at the same time Timer flip flop timer F F TFF1 The status of the timer flip flop is inverted by the match detect signal comparator output of each interval timer and the value can be output to the timer output pins 1 also used as P71 A timer E F is provided for a pair of timer O and timer 1 and is called TFF1 TFF1 is output to TO1 pin 57 96 141 TSRUN TARUN PIRUN 2 TIRUN TORUN R W After reset 0 0 0 Prescaler amp Timer Run Stop CONTROL Function 0 Stop amp Clear 1 Run Count up Stop and clear Count PRRUN Operation of prescaler T5RUN Operation of 16 bit timer timer5 TARUN Operation of 16 bit timer timer4 P1RUN Operation of PWM timer PWM 1 timer3 PORUN Operation of PWM timer PWMO timer2 TIRUN Operation of 8 bit timer timer1 TORUN
106. ed 43H TREG7H 1901 prohibit W Register 7H RMW Undefined Capture CAP3L Register 3L Hh i Undefined Capture CAP3H Register 2H 45H R Undefined Capture PAPAE Register 4L j Undefined Capture Register 4H xd Undefined CAP34M1 CAP34M0 CLE T5CLK1 T5CLKO R W W 16bit Timer 5 0 0 0 0 0 0 0 0 EMOD ru d d d Capture Timing Source Clock MODE 0 Soft 00 Disable 1 UC5 00 Invert 6 Capture 01 16 T T17 T Clear 01 Set TFF6 1 Don t care 10 16 T 116 4 Enable 10 Clear TFF6 11 TFF1 T TFF1 1 11 Don t care TOSHIBA CORPORATION 167 96 141 Timer Control 4 4 Symbol Name Address 7 6 5 4 3 2 1 0 CAP4T6 CAP3T6 EQ7T6 EQ6T6 TFF6C1 TFF6CO R W W 16bit Timer 5 0 0 0 0 0 0 T5FFCR Flip flop 49H Control TFF6 Invert Trigger A 4 2 0 Trigger Disable 10 Clear TFFG 1 Trigger Enable 1 panied 4 Pattern Generator Symbol Name Address 7 6 5 4 3 2 1 0 ACH PGO03 PG02 PG01 PG00 SA03 SA02 SA01 SA00 PGOREG PGO Register Prohibit W R W RMW 0 0 0 0 Undefined 4DH PG13 PG12 PG11 PG10 SA13 SA12 SA11 SA10 PGIREG PG1 Register Prohibit W R W RMW 0 0 0 0 Undefined PAT1 CCW1 PG1M PGITE PATO CCWO PGOM PGOTE R W 4EH 0 0 0 0 0 0 0 0 PEDLER EOST cond T 0 Normal PG1 trigger 0 Normal PGO trigger 0 8bit write Rotation 0 4bit Step
107. en the set value of timer registers TREGO 1 matches the value of up counter the comparator match detect signal becomes active If the set value is OCH this signal becomes active when the up counter overflows Timer register TREGO is of double buffer structure each of which makes a pair with register buffer The timer flip flop control register TFFCR lt gt bit controls whether the double buffer structure in the Up counter Comparator CPO Timer registers 0 TREGO Shifttrigger Register buffers 0 Internal bus TMP96C141AF TREGO should be enabled or disabled It is disabled when lt DBEN gt 0 and enabled when they are set to 1 In the condition of double buffer enable state the data is transferred from the register buffer to the timer regis ter when the 2 1 overflow occurs in PWM mode or at the PPG cycle in PPG mode Therefore during timer mode the double buffer cannot be used When reset it will be initialized to lt DBEN gt 0 to dis able the double buffer To use the double buffer write data in the timer register set DBEN to 1 and write the following data in the register buffer Matching detection of PPG 21 1 overflow of PWM TREGO WR TFFCR lt DBEN gt Figure 3 7 3 Configuration of Timer Register 0 Timer register and the register buffer are allocated to the same memory address When lt DBEN gt 0 the same value is written in Th
108. ent counter set the prescaler in RUN mode Stop timer 4 Set P80 to input mode Enable INTTR5 and sets interrupt level 4 while disables INTTR4 Disable trigger Select T14 as the input clock Set the number of counts 16 bits Start timer 4 3 16 bit Programmable Pulse Generation PPG Output flip flop TFF4 that is to be enabled by the match of the Mode up counter UCA with the timer register TREG4 or 5 and to be output to TO4 also used as P82 In this Since both timers operate in exactly the same way mode the following conditions must be satisfied timer 4 is used for the purposes of explanation The PPG mode is obtained by inversion of the timer Set value of TREG4 lt Set value of TREGS 6 5 4 3 2 1 0 TRUN X 0 zs Stop timer 4 TREG4 e 2 E is i Set the duty 16 bits TRE e i i x d t Set the cycle 16 bits T45CR lt 0 X X X d e 1 Double buffer of TREG4 enable Changes the duty and cycle at the interrupt INTTR5 T4FFCR lt 1 1 0 0 1 1 0 0 Set the mode to invert at the match with TREG4 TREGS and also sets TFF4 to 0 T4M0D 0 0 1 0 0 1 Select internal clock for input disables the capture function 01 10 11 lt M 58 Assign P82 as TO4 P8FC lt x AX X 1 X X TRUN lt 1 X 1 m6 VEM um Start timer 4 Note x don t care no change Match with TREG4 interrupt INTTR4 Match with TREG5 interrupt INTTR5 4 pin Figure 3
109. erate timer 1 interrupt at constant intervals using timer 1 INTT1 first stop timer 1 then set the operation mode input clock and a cycle to TMOD and TREG1 register respectively Then enable interrupt INTT1 and start the counting of timer 1 Example To generate timer 1 interrupt every 40 microseconds at fc 16 MHz set each register in the following manner imer 1 and clear it to 0 e 8 bit timer mode and select 0 55 16MHz as the input clock e timer register at 40us 1 50H e INTT1 and set it to Level 5 Start imer 1 counting Table 3 7 1 8 Bit Timer Interrupt Cycle and Input Clock Input Clock eed ane Resolution peepee Resolution 1 8 fc 0 55 1285 0 56 0 4us 102 405 0 405 914 32 fc 2 5 51235 2 1 65 409 605 1 6us 116 128 fc 8 5 2 048ms 8 5 6 46 1 6385 6 46 91256 2048 128 5 32 708ms 1285 102 4us 2 6215 1285 Note input clock of time O and timer 1 are different from as follows Timer 0 T10 input 1 9T4 9T16 Timer 1 Match Output of Timer 0 611 116 1256 TOSHIBA CORPORATION 61 96 141 Q Generating a 50 duty square wave pulse TO1 pin at fc 16MHZ set each register in the following procedures Either timer O or The timer flip flop TFF1 is inverted at constant inter timer 1 may be used but this example uses vals and its status is output to timer outp
110. erface mode is controlled by the serial control register SCICR Serial transmission mode Interrupt when data are received Interrupt only when RB8 1 don t care 0 disable Receive enable Transmission data bit 8 Figure 3 11 6 Serial Mode Control Register Channel 1 SC1MOD TOSHIBA CORPORATION 121 96 141 t OERR PERR FERR SCLKS iem Received Parity Parity 0 i 0 SCLK1 0 data 0 Odd addition 1 i Baud rate Bit8 i 1 Even 0 Disabl E Ci igenerator Function 1 Enabl EM 1 1 SCLK1 1 SCLK1 Overrun Parity Framing eb E input 3 CL Select I O interface input clock Note 0 Baud rate generate SCLK1 Pin input Note1 Forchannel 0 fix this bit to 0 Edge selection in SCLK pin input mode Transmits and receives _ data at raise edge of SCLK Transmits and receives i data at fall edge of SCLK Framing error flag Zero Parity error flag when read Overrun error flag Enable parity addition Even Parity Receiving data bit 8 Note As all error flags are cleared after reading do not test only a single bit with a bit testing instruction Figure 3 11 7 Serial Control Register Channel 1 SC1CR 122 TOSHIBA CORPORATION 96 141 BRICKO BR1S3 BR1S2
111. f an overrun error parity error or framing error occurs during receiving operation flag SCOCR SC1CR lt OERR PERR FERR gt will be set The serial channel 0 1 includes a special baud rate gen erator which can set any baud rate by dividing the frequency of four clocks 0TO 2 9T8 and 9132 from the internal pres caler shared by 8 bit 16 bit timer by the value 2 to 16 In I O interface mode it is possible to input synchronous signals as well as to transmit or receive data by external clock 3 11 1 Control Registers The serial channel is controlled by three control registers SCOCR SCOMOD and BROCR Transmitted and received data is stored in register SCOBUF 117 96 141 Note SCOMOD 0052H After reset Function Transfer data Bit 8 t Hand shake 0 0 CTS i disable HRCIS S enable EP Receive disable Receive enable There is SC1MOD 56H in Channel 1 iReceiving Wake up Serial transmission Function i Function imode 90 Can not be used 10 disable 01 7 bit UART Enable 110 8 bit UART 41 9 bit UART 00 Serial transmission clock UART Serial transmission mode Receiving Function 0 Serial transmission clock UART 90 TOO Trigger 01 baud rate generator 10 Internal clock 1 111 don t care Timer 0 match detect signal Baud rate generator Internal clock 1 don t care Ca
112. f which can be operated independently The cascade connection allows these timers to be used as 16 bit timer The following four operating modes are provided for the 8 bit tim ers 8 bit interval timer mode 2 timers 16 bit interval timer mode 1 timer 8 bit programmable square wave pulse generation PPG variable duty with variable cycle output mode 1 timer 8 bit pulse width modulation PWM variable duty with con 54 stant cycle output mode 1 timer Figure 3 7 1 shows the block diagram of 8 bit timer timer O and timer 1 Each interval timer consists of an 8 bit up counter 8 bit comparator and 8 bit timer register Besides one timer flip flop TFF1 is provided for pair of timer O and timer 1 Among the input clock sources for the interval timers the internal clocks of T1 T4 16 and 256 are obtained from the 9 bit prescaler shown in Figure 3 7 2 The operation modes and timer flip flops of the 8 bit timer are controlled by three control registers TMOD TFFCR and TRUN TOSHIBA CORPORATION TMP96C141AF TRUN TORUN gt TFFCR TFF1C1 02 RUN Clear TIO 8 bit Select stalai eor UCO mm T16 128 fc Over TMOD lt TOCLK1 0 gt lt 1 0 1 0 gt comparator INTTO PPGTR 8 bit timer PWMTRG register TREGO Select TREG WR d A Register buffer TFFCR lt DBEN
113. fer AD8 AD15 A8 A15 PO write Interna P1 write N t a P1 read Internal Figure 3 5 1 Port 0 Figure 3 5 2 Port 1 TOSHIBA CORPORATION 25 TMP96C141AF 26 PO bit Symbol Port O Register P04 0000H Read Write R W zm After reset Input mode Output latch register becomes undefined POCR bit Symbol 7 06 POSC 4 P02C POIC 0002H Read Write After reset 0 V d 0 ode BO 6 90 be Function 0 IN 1 OUT At external access Port 0 becomes AD7 0 and POCR is cleared 100 1 0001H Read Write After reset P1CR bit Symbol P17C P16C P15C P14C P13C P12C 0004H Read Write After reset 0 0 i1 0 i o i o i o o o Function P17F lt See PIFC below gt gt P16F P1SF P14F P13F After reset 023 100 5 Q0 3 9 Function PIFC PTCR 00 IN 01 OUT 10 AD15 8 11 A15 8 Read modify write is prohibited for registers POCR P1CR and P1FC 0 1 Input port aderen bus 1 Output port Note lt gt isbit X in register PIFC lt gt register PICR Figure 3 5 3 Registers for Ports O and 1 TOSHIBA CORPORATION 3 5 3 Port 2 20 P27 Port 2 is an 8 bit general pu
114. g Wake Up Function TOSHIBA CORPORATION 96 141 Protocol amp The master controller transmits one frame data including the 8 bit select code for the slave control Select the 9 bit UART mode for master and slave lers The MSB bit 8 lt TB8 gt is set to 1 controllers Set SCOMOD lt WU gt SC1MOD WU bit of each slave controller to 1 to enable data receiving Select code of slave controller Each slave controller receives the above frame and amp The master controller transmits data to the specified clears WU bit to O if the above select code matches slave controller whose SCOMOD lt WU gt SC1MOD its own select code WU bit is cleared to The MSB bit 8 lt TB8 gt is cleared to O N Data The other slave controllers with the lt WU gt bit remain The slave controllers WU 0 can transmit data ing at 1 ignore the receiving data because their to the master controller and it is possible to indicate MSBs bit 8 or lt RB8 gt are set to 0 to disable the the end of data receiving to the master controller by interrupt INTRXO INTRX1 this transmission TOSHIBA CORPORATION 137 96 141 Setting Example link two slave controllers serially the internal clock 91 fc 2 as the with the master controller and use transfer clock TxD RxD RxD TxD Ma
115. gt 1 Set 2 Clear F F control 3 Invert i Software trigger mer F F TOI TRUN lt TIRUN gt EA TMOD lt T10M1 0 gt gt o Ii 1 L TFFCR TFFIE2 D Selector RUN cl y Clear 8 bit up counter TFFCR lt TFFIIS gt UC1 TMOD lt TICLK1 0 gt 8 bit comparator CP1 TMOD lt T10M1 0 gt 8 bit timer register TREG1 Figure 3 7 1 Block Diagram of 8 Bit Timers Timers O and 1 TOSHIBA CORPORATION 55 96 141 56 Prescaler This 9 bit prescaler generates the clock input to the 8 bit timers 16 bit timer event counters and baud rate generators by further dividing the fundamental clock fc after it has been divided by 4 fc 4 Among them 8 bit timer uses four types of clock 1 9 T4 16 and 9T256 This prescaler can be run or stopped by the timer operation control register TRUN lt PRRUN gt Counting starts when PRRUN is set to 1 while the prescaler is cleared to zero and stops operation when lt PRRUN gt is set to 0 Resetting clears PRRUN to O which clears and stops the prescaler Cycle input 16MHz 20MHz 1 8 fc 0 5 us 0 45 4 32 fc 2 05 1 65 1 16 128 fc 8 0 us 6 4us 1256 2048 fc L 128 us x1 1024s TO T 972 974 4T8 T16 9732 1256 Tp 0 2 3 4 5 6 7 8 Oscillator circuit 9 bit prescaler run stop amp clear TRUN lt PRRUN gt Figure 3 7 2 Prescaler Q
116. gt e 5 PG1T Figure 3 10 6 Connection of Timer and Pattern Generator 1 Pattern Generation Mode In this mode set PGO1CR lt PGOM gt and lt PG1M gt to 1 and PGO1CR COCWO and lt CCW1 gt to 0 The output of this pattern generator is output to port 6 PG functions as a pattern generation according to the setting ER since port and functions be switched on bit basis using of PGO1CR lt PAT1 gt PATO gt In this mode writing from CPU is port function control register any port pin can be executed only on the shifter alternate register Writing a new assigned to pattern generator output data should be done during the interrupt operation of the timer Figure 3 10 7 shows the block diagram of this mode for shift trigger and a pattern can be output synchronous with the timer 108 Trigger Signal from Timer Timer interrupt Writing data to 5403 00 on Timer Interrupt Shift alternate register output Shifting data from SA03 00 5403 00 to 03 00 output PG03 00 Example of pattern generation mode TOSHIBA CORPORATION 96 141 Shift alternate register PG03 893 ERN BUS3 PGO2 02 1 2 SA02 01 01 bus Internal 5 01 051 T gt lt gt 5 00 BUSO 00 INJ Shift due to the shift trigger from timer Figure 3 10 7 Pattern Generation Mode Block Diagram PGO In this
117. h CPU executes following by one instruction 1 CPU reads data of the memory 2 CPU modifies the data 3 CPU writes the data to the same memory ex1 SET TRUN set bit3 of TRUN ex2 INC1 100H increment the data of 100H The representative Read Modify and Write Instruction in the TL CS 900 SET imm mem RES imm mem CHG imm mem TSET imm mem INC imm mem DEC imm mem RLD A mem ADD imm reg 1 state One cycle clock divided by 2 oscillation frequency is called 1 state ex The case of oscillation frequency is 20MHz Guidelines EA Fix these pins or GND unless changing voltage Q Warming up Counter The warming up counter operates when the STOP mode is released even the system which is used an external oscillator As a result it takes warming up time from inputting the releasing request to outputting the System clock High Speed uDMA DRAM refresh mode When the bus is released BUSAK O for waiting to accept the interrupt DRAM refresh is not performed because of the high speed uDMA is generated by an interrupt Programmable Pull Up Down Resistance The programmable pull up down resistors can be selected ON OFF by program when they are used as the input ports The case of they are used as the out put ports they cannot be selected ON OFF by pro gram Bus Releasing Function Refer to the Note about the Bus Release in 3 5 Func tions of Ports because the
118. he 02 pin Starts PWMO counting Table 3 8 1 PWM Cycle and 2 1 Counter Setting 16MHz 20MHz Formula P1 gP4 P16 1 gP4 16 26 1 26 1 Pn 15 8usec 63 0usec 252usec 12 6usec 50 4usec 201 63kHz 16kHz 3 9kHz 79 2 20kHz 4 9kHz 2 4 2 1 Pn 31 8 127 Ousec 508 25 4580 101 6usec 406 31kHz 7 9kHz 1 9kHz 89kHz 9 8kHz 2 5kHz 29 4 28 1 63 8psec 255 0psec 1020 51 0psec 204 0psec 816usec 16kHz 3 9kHz 0 98kHz 20kHz 4 9kHz 1 2kHz 80 TOSHIBA CORPORATION 8 bit timer mode Both PWM timers can be used independently as 8 bit interval timers Since both timers operate in exactly the same way PWMO timer 2 is used for the purposes of explanation TMP96C141AF Generating interrupts at a fixed interval To generate timer 2 interrupt INTT2 at a fixed interval using PWMO timer first stop PWMO then set the oper ating mode input clock and interval in the POMOD and TREG2 registers Next enable INTT2 and start counting PWMO Example To generate a timer 2 interrupt every 4045 at fc 16MHz set registers as follows TRUN E X 0 POMOD lt x 0 1 1 0 0 X TREG2 lt 1 0 1 0 0 0 0 INTEPW10 lt 1 1 0 TRUN lt 1 X 1 Note don t change Select an input clock using the table below Stops PWMO and clears it to 0 Sets 8 bit timer mode and selects
119. he comparator and the latch signal to the capture register CAP2 TFF5 will be inverted when OO is written in TAFFCR lt TFF5C1 O gt T6FFCR lt TFF6C1 O gt Also it is Set to 1 when 10 is written and cleared to 0 when 10 is written The value of TFF5 can be output to the timer output pin TO5 also used as P82 Note This flip flop TFF5 is contained only in the 16 bit timer 4 1 16 bit Timer Mode Timer 4 and 5 operate independently Since both timers operate in exactly the same way timer 4 is used for the purposes of explanation Generating interrupts at fixed intervals In this example the interval time is set in the timer register TREG6 to generate the interrupt INTTR5 Stop timer 4 Enable INTTR5 and sets interrupt level 4 Disables INTTRA Disable trigger Select internal clock for input and disable the capture function Set the interval timer 16 bits Start timer 4 counter first perform software capture once and read the captured value The counter counts at the rise edge of TIA TI6 pin input TI4 TI6 pin can also be used as P80 INT4 and P84 INT6 Since both timers operate in exactly the same way timer 4 is used for the purposes of explanation 95 96 141 7 6 5 4 3 2 1 0 TRUN 25 X 0 m e 7 P8CR lt 0 INTET54 lt 1 1 0 0 1 0 0 0 T4FFCR e 1 1 0 0 0 1 1 T4M0D lt 0 0 1 0 0 1 0 0 TRE e TRUN lt 1 X 1 Note When used as an ev
120. ing Xexcitation trigger mode Rotaing excitation trigger 0 8bit erection p bu US 20 Bbit direction D Function write 0 Normal x ud i write 0 4 i rotation 28997 disable rotationi disable 1 4bit 1 1 2 1 4bit M 112 152 EN 1 Reverse 1 enable 1 Reverse 21 enable write i excitation write i excitation rotation rotation PG1 trigger input enable Trigger input disable to PG1 1 2 excitation half step PG mode PG1 stepping motor control Rotaing direction control Normal rotation PG mode Reverse rotation 8 bit write 4 bit write PG mode Only shifter alternate register can be written Figure 3 10 2b Pattern Generation Control Register PGO1CR TOSHIBA CORPORATION 105 96 141 7 6 5 4 3 2 1 0 PGOREG bit Symbol PG03 PG02 PG01 PG00 SA03 SA02 SA01 SA00 004CH Read Write W R W After reset 0 0 0 0 Undefined Function Pattern Generation 0 PGO output latch register Shift alternate register 0 Reading the P6 that is set to the PG port allows to read out For the PG mode 4 bit write register Prohibit Read modify write Figure 3 10 3 Pattern Generation 0 Register PGOREG 7 6 5 4 3 2 1 0 PG1REG bit Symbol PG13 PG12 PG11 PG10 SA13 SA12 SA11 SA10 004DH Read Write W R W After reset 0 0 0 0 Undefined Function Pattern
121. ion mode 160 states 20 5 16MHz conversion ended Figure 3 12 2 A D Control Register 140 TOSHIBA CORPORATION ADREGOL 0060H ADREGOH 0061H ADREGIL 0062H ADREG1H 0063H TMP96C141AF 7 6 5 4 3 2 1 0 bit Symbol ADRO1 ADROO Read Write R After reset Undefined 1 1 1 1 1 1 Function Lower 2 bits of A D result for ANO are stored 7 6 5 4 3 2 1 0 bit Symbol ADR09 ADRO8 ADRO7 ADR06 ADRO5 ADRO4 ADRO3 ADRO2 Read Write R After reset Undefined Function Upper 8 bits of A D result for ANO are stored 7 6 5 4 3 2 1 0 bit Symbol ADR11 ADR10 Read Write R After reset Undefined 1 1 1 1 1 1 Function Lower 2 bits of A D result for AN1 are stored 7 6 5 4 3 2 1 0 bit Symbol ADR19 ADR18 ADR17 ADR16 ADR15 ADR14 ADR13 ADR12 Read Write R After reset Undefined Function Upper 8 bits of A D result for 1 are stored Figure 3 12 3 1 A D Conversion Result Register ADREGO 1 TOSHIBA CORPORATION 141 96 141 ADREG2L 0064H ADREG2H 0065H ADREG3L 0066H ADREG3H 0067H 142 7 6 5 4 3 2 1 0 bit Symbol ADR21 ADR20 Read Write R After reset Undefined 1 1 1 1 1 1 Function
122. l register TRUN lt T4RUN T5RUN gt When clearing is enabled up counter UC4 UC5 will be cleared to zero each time it coincides matches the TREG4 Upper 8 bits Lower 8 bits 000031H 000030H TREG6 Upper 8 bits Lower 8 bits 000041H 000040H TREGA and TREG6 timer register is of double buffer structure which is paired with register buffer The timer control register T45CR DBAEN DB6EN gt controls whether the double buffer structure should be enabled or disabled disabled when lt DB4EN DB6EN gt 0 while enabled when lt DB4EN DB6EN gt 1 When the double buffer is enabled the timing to transfer data from the register buffer to the timer register is at the match between the up counter UC4 UC5 and timer register TREGS TREGT When reset it will be initialized to lt DB4EN DB6EN gt 0 whereby the double buffer is disabled To use the double buffer write data in the timer register set lt DB4EN DB6EN gt 1 and then write the following data in the register buffer TREGA TREG6 and register buffer are allocated to CAP 1 Upper 8 bits Lower 8 bits 000035H 000034H CAP 3 Upper 8 bits Lower 8 bits 000045H 000044H Capture Input Control This circuit controls the timing to latch the value of up counter UC4 UC5 into CAP1 2 timer register TREG5 TREG7 The clear enable disable is set by TAMOD CLE and T5MOD CLE If c
123. learing is disabled the counter operates as a free running counter Timer Registers These two 16 bit registers are used to set the interval time When the value of up counter UC4 UC5 matches the set value of this timer register the comparator match detect signal will be active Setting data for timer register TREG4 TREG5 TREG6 and TREG7 is executed using 2 byte date trans fer instruction or using 1 byte date transfer instruction twice for lower 8 bits and upper 1 bits in order TREGS Upper 8 bits Lower 8 bits 000033H 000032H TREG7 Upper 8 bits Lower 8 bits 000043H 000042H the same memory addresses 000030 000031 0000400H 000041H When lt DB4EN DB6EN gt 0 same value will be written in both the timer register and register buffer When lt DB4EN DB6EN gt 1 the value is written into only the register buffer Capture Register These 16 bit registers are used to hold the values of the up counter Data in the capture registers should be read by a 2 byte data load instruction or two 1 byte data load instruc tion from the lower 8 bits followed by the upper 8 bits CAP 2 Upper 8 bits Lower 8 bits 000037H 000036H CAP 4 Upper 8 bits Lower 8 bits 000047H 000046H The latch timing of capture register is controlled by regis ter TAMOD lt 12 1 0 gt T5MOD lt 4 1 O gt e When TAMCD lt 12 1 0 gt T5MOD
124. lt P71C gt EN Setting P72 as TO2 P7FC lt 72 gt 1 P7CR lt P72C gt Setting P73 as P7FC lt P73F gt 1 P7CR lt 73 gt 1 prohibited for registers P7CR and P7FC Note P70 TIO pin does not have a register changing PORT FUNCTION For example when it is used as an input port P70 the input signal for P70 is inputted to 8bit Timer 0 as a timer input 0 TIO Figure 3 5 16 Registers for Port 7 40 TOSHIBA CORPORATION 3 5 9 Port 8 P80 P83 Port 8 is an 8 bit general purpose I O port I O be set on a bit basis Resetting sets Port 8 as an input port and connects a pull up resistor It also sets all bits of the output latch register P8 to 1 In addition to functioning as a general purpose port Port 8 also functions as an input for 16 bit timer 4 and 5 TMP96C141AF clocks an output for 16 bit timer F F 4 5 and 6 output and an input for INTO Writing 1 in the corresponding bit of the Port 8 function register P8FC enables those functions Resetting resets the function register P8FC value to O and sets all bits to ports 1 P80 P86 Reset cm Direction control on bit basis A P ch P8CR write Programmable pull up rr 5 h P80 TI4 INT4 Qutputiate P81 TIS INTS S B P84 TIG INT6 P8 write P85 TI7 INT7 LI lt Selector z P8 read A TI4 TIS 3 6 TI7 Reset m v Direction control
125. main routine after completion of the inter rupt processing the RETI instruction is usually used Executing this instruction restores the contents of the program counter and the status registers Though acceptance of non maskable interrupts cannot be disabled by program acceptance of maskable interrupts can priority can be set for each source of maskable inter rupts The CPU accepts an interrupt request with a priority higher than the value in the CPU mask register IFF2 to O gt The CPU mask register IFF2 to O is set to a value higher by 1 than the priority of the accepted interrupt Thus if an inter rupt with a level higher than the interrupt being processed is generated the CPU accepts the interrupt with the higher level causing interrupt processing to nest The CPU does not accept an interrupt request of the same level as that of the interrupt being processed Resetting initializes the CPU mask registers IFF2 to 0 to 7 therefore maskable interrupts are disabled The addresses 008000H to 0081FFH 512 bytes of the TLCS 900 are assigned for interrupt processing entry area 96 141 Table 3 3 1 TMP96C141AF Interrupt Table Default Priority Type Interrupt Source Start Address Mo OMA Start Vector 1 Reset or SW10 instruction 0000 8000 2 INTPREV Privileged violation o
126. match detect PWM2n 1overflow lt DB2EN gt lt DB3EN gt Figure 3 8 3 Structure of Timer Registers 2 and 3 The timer register and register buffer are allocated to the same memory address When lt DB2EN gt lt DBS3EN gt 0 the same value is written to both register buffer and timer register When lt DB2EN gt lt 1 the value is written to the register buffer only Memory addresses of the timer registers are as follows TREG2 000026 TREGS 000027H Both timer registers are write only however register buffer values can be read when reading the above addresses amp Comparator Compares the value in the up counter with the value in the timer register TREG2 TREGO9 When they match TOSHIBA CORPORATION the comparator outputs the match detect signal A timer interrupt INTT2 INTT3 is generated at compare and match if the interrupt select bit lt gt lt PWMI1NT gt of the mode register POMOD P1MOD is set to 1 In timer mode the comparator clears the up counter to O at compare and match It also inverts the value of the timer flip flop if timer flip flop invert is enabled Timer flip flop The value of the timer flip flop is inverted by the match detect signal comparator output of each interval timer or 2 1 overflow The value can be output to the timer output pin 2 also used as P72 P78 73 96 141 FF2RD DB2EN PWMOINT P
127. me 00 RUN mode watchdog even in Function 10 220 fc 0 216 ffc 01 5 0 mode timer STOP 2256 1 218 10 IDLE mode output to mode Detection time 11 Don t care RESET pin internally When STOP mode is released by other than a reset the system clock output starts after allowing some time for warm ing up set by the warming up counter fro stabilizing the bulit in oscillator To release STOP mode by reset it is necessary to allow the oscillator to stabilize To release standby mode a reset or an interrupt is used To release IDLE or STOP mode only an interrupt by the NMI or INTO pin or a reset can be used The details are described below Standby Release by Interrupt Interrupt Level Standby Mode Interrupt Mask IFF2 to 0 lt Interrupt Request Level Interrupt Mask IFF2 to 0 Interrupt Request Level Can be released by any interrupt Can only be released by INTO pin RUN After standby mode is released interrupt processing starts Processing resumes from address next to HALT instruction IDLE Can only be released by NMI or INTO pin After standby mode 4 is released interrupt processing starts STOP T Note T TOSHIBA CORPORATION 21 96 141 Table 3 4 1 Pin States in STOP Mode 96C141AF
128. n not be used Interrupt when data are received Interrupt only when RB8 1 don t care Receive Disable Receive Enable Hand shake function CTS Pin enable Disable always Transferable Transmission data bit 8 Figure 3 11 2 Serial Mode Control Register Channel 0 SCOMOD 118 TOSHIBA CORPORATION 96 141 SCOCR bit Symbol OERR PERR FERR verd Received Parity Parity data 20 addition Bit8 11 10 Disable Function 11 Enable 2 Overrun Parity Framing ere error flag Parity error flag 9 Overrun error flag Cleared to Zero when read Enable parity addition 0 Prohibition disable Permission enable gt Addition check of even parity 0 Odd parity Even parity gt Receving data bit 8 Note Serial control register for channel 1 is SC1CR 65H As all error flags are cleared after reading do not test only a single bit with a bit testing instruction Figure 3 11 3 Serial Control Register Channel SCOCR TOSHIBA CORPORATION 119 96 141 BROCR bit Symbol BROCKO BROS3 BROS2 BROSI BROSO 0053 Read Write R W After reset 0 00 gT0 fc 4 01 gT2 fc 16 10 4T8 fc 64 11 732 256 Function Setting of the Divided fre
129. nal ROM PORTO functions as ADO AD7 PORT1 AD8 to AD15 P30 the RD signal P31 the WR signal regardless o TOSHIBA CORPORATION the values set POCR P1CR P1FC P30 F and P31F 163 96 141 Port Control 2 2 Symbol Name Address 7 6 5 4 3 2 1 0 P67C P66C P65C P64C P63C P62C P61C P60C 14H W P6CR PORT6 Prohibit Control RMW 0 0 0 0 0 0 0 0 0 IN 1 OUT P73C P72C PC P70C 15H W P7CR PORT Prohibit Control RMW 0 0 0 0 0 IN 1 OUT P67F P66F P65F P64F P63F P62F P61F P60F 16H W P6FC PORT6 Prohibit Function RMW 0 0 0 0 0 0 0 0 0 PORT 1 PG1 OUT 0 PORT 1 PGO OUT P73F P72F P71F PORT P7FC Prohibit Function TM 0 9 0 PORT 0 0 1 103 1 T02 1 TO1 P87C P86C P85C P84C P83C P82C P81C P80C W P8CR PORTS Prohibit Control RMW 0 0 0 0 0 0 0 0 IN 1 OUT P95C P94C P93C P92C P91C P90C 1BH PORTS Prohibit Control RMW 0 0 0 0 0 O IN 1 0UT P86F P83F P82F PORTS 1CH W W W P8FC Prohibit Function RMW 0 0 PORT 0 0 PORT 1 706 1 105 1 T04 P95F P93F P92F POOF PORTS 1DH W W W W POFC Prohibit Function 0 0 0 0 RMW 0 PORT 0 PORT 0 PORT 0 PORT 1 SCLK1 1 TxD1 1 SCLKO 1 TxDO 164 TOSHIBA CORPORATION 3 Timer Control 1 4 96 141
130. ndefined cape Capture 36H R Register 2L Undefined 2 Capture 37H R Register 2H Undefined CAP2T5 EQ5T5 CAP1IN 12 1 12 0 CLE T4CLK1 T4CLKO R W W R W 16 bit Timer 4 0 0 0 0 0 0 0 ee on TFF5 INV TRG 0 Soft Capture Timing 1 UC4 Source Clock UE 0 TRG Disable Capture 00 Disable Clear 00 TM 1 TRG Enable 1 Dontcae 01 14 T T15 7 Enable 01 rl 10 114 T T14 JL 10 914 11 TFF1 T TFF1 4 11 9116 166 TOSHIBA CORPORATION Timer Control 3 4 TMP96C141AF Symbol Name Address 7 6 5 4 3 2 1 0 TFF5C1 TFF5CO CAP2T4 CAP1T4 EQ5T4 EQ4T4 TFF4C1 TFF4CO W R W W 16bit Timer 4 0 0 0 0 0 0 0 0 T4FFCR Flip flop 39H Control 00 Invert TFF5 TFFA Invert Trigger Source Clock 01 Set TFF5 0 Trigger Disable 00 Invert 10 Clear TFF5 1 Trigger Enable 01 Set 11 Don t care 10 Clear TFF4 11 Don t care PG1T PGOT DB6EN DB4EN R W R W 0 0 0 0 0 T45CR T4 T5 Control 3AH PGI shift PGO shift na mere trigger trigger Sie 0 0 Timer 0 1 0 Timer 0 1 5 1 Timer 5 1 Timer 4 40H 1001116 prohibit W Register 6L RMW Undefined pd 41H 1001 17 prohibit W Register 6H RMW Undefined 42 trea7 Obit Timer prohibit W Register 7L RMW Undefin
131. nly mode for DRAM refresh Q Timer Setting Set the timers so that interrupts are generated at intervals of 62 5us or less Interrupt controller setting Set the timer interrupt mask h other interrupt mask Write the above timer interrupt vector value in the High Speed start vector register DMAOV Operation description The DRAM data bus is an 8 bit bus and the micro DMA is in read only mode 4 bytes so refresh is per formed four times per interrupt When a 512 refresh 8ms DRAM is connected DRAM refresh is performed sufficiently if the micro DMA is started every 15 625us x 4 62 4us or less since the timing is 15 625us refresh Overhead Each processing time by the micro DMA is 1 8 18 states 20MHz with an 8 bit data bus In the above example the micro DMA is started every 62 5us 1 8us 62 5us 0 029 thus the overhead is 2 996 3 3 3 Interrupt Controller Figure 3 3 3 1 is a block diagram of the interrupt circuits The left half of the diagram shows the interrupt controller the right half includes the CPU interrupt request signal circuit and the HALT release signal circuit Each interrupt channel total of 20 channels in the inter rupt controller has an interrupt request flip flop interrupt prior 16 ity setting register and a register for storing the high speed micro DMA start vector The interrupt request flip flop is used to latch interrupt requests from peripheral devices The flip flo
132. nstruc tion used to clear an interrupt request flag of an interrupt is fetched before the interrupt is generated it is possible that the CPU might execute the fetched instruction to clear the interrupt request flag 20 while reading the interrupt vector after accepting the inter rupt If so the CPU would read the default vector and start the interrupt processing from the address 80A0H To avoid this make sure that the instruction used to clear the interrupt request flag comes after the DI instruction TOSHIBA CORPORATION 3 4 Standby Function When the HALT instruction is executed the TMP96C141AF enters RUN IDLE or STOP mode depending on the contents of the HALT mode setting register TMP96C141AF other built in circuits halt Power consump tion is reduced to 1 10 or less than that dur ing normal operation 3 STOP All internal circuits including the built in oscil 1 Only the CPU halts power consumption lator halt This greatly reduces power con remains unchanged sumption The states of the port pins in STOP mode can be set as listed in Table 3 4 2 IDLE Only the built in oscillator operates while all 1 using the I O register WDMOD DRVE bit 7 6 5 4 3 2 1 WDMOD Bit Symbol WDTE WDTP1 WDTPO WARM HALTM1 HALTMO RESCR DRVE 005 Read Write RW After reset 1 0 0 0 0 0 0 0 1 WDT 00 216 fc Warming up Standby mode 1 Connects 1 Drive pin Enable 01 21 tc ti
133. nter of the watchdog timer function Clear WDMOD lt WDTE gt to 0 Write the disable code B1H counting by writing clear code 4EH into the WDCR reg ister Write the clear code 4EH 147 96 141 005 148 bit Symbol WDTE WDTP WDTPO WARM HALTMO HALTMO RESCR DRVE WDT control 00 216 fc 201 218 fc 1 Enable 10 220 fc 11 222 fc Select detecting time Warming Standby mode Uptime i 200 RUN mode i Internally Drive the i connects pin i WDT out to i STOP mode 0 24 fc 21 218 fc 111 Don t care the reset pin DRVE explanation by stop mode Watchdog timer out control Connects WDT out to a reset RUN mode Only the CPU stops STOP mode All circuits stop Don t care Select the detecting period of watchdog timer 214 fc approx 1 0ms 16MHz 216 fc approx 4 1ms 16MHz 216 fc approx 4 1ms 16MHz 218 fc approx 16ms 16MHz 220 fc approx 66ms 16MHz 222 fc approx 262ms 16MHz Disable Enable Figure 3 13 4 Watchdog Timer Mode Register TOSHIBA CORPORATION 96 141 pv bit Symbol WDCR Read Write 005DH poen B1H WOT disable code 4EH WDT clear code Function Disable clear WDT Disable code 4EH Clear code Others Figure 3 13 5 Watchdog Timer Control Register
134. op and clear of the up counter can be con trolled for each PWM timer using the timer operation control register TRUN Resetting clears all up counters and stops timers Timer registers Two 8 bit registers used for setting an interval time When the value set in the timer registers TREG 2 and 3 matches the value in the up counter the match detect signal of the comparator becomes active Timer registers TREG2 and TREGS are each paired with register buffer to make a double buffer structure TOSHIBA CORPORATION Note TREG2 and TREGS are controlled double buffer enable disable by POMOD lt DB2EN gt and P1MOD lt DBSEN gt disabled when lt DB2EN gt lt DB3EN gt 0 enabled when lt DB2EN gt lt DBS3EN gt 1 Data is transferred from register buffer to timer when a 2 1 overflow occurs in the PWM mode or when compare and match occurs in 8 bit timer mode That is with a PWM timer the timer mode can be operated Up counter Timer register TREG2 3 Write Internal bus Shift trigger Register buffer Selector wwe c c TREG2 3 WR TMP96C141AF in double buffer enable state unlike timer mode for timers O and 1 At reset lt 2 gt lt gt is initialized to O to dis able double buffer To use double buffer write the data in the timer register at first then set lt DB2EN gt lt gt to 1 and write the following data in the reg ister buffer 8 bit
135. ower 8 bits of the timer interrupt cycle are set by the timer register TREGO and the upper 8 bits are set by TREG1 Note that TREGO always must be set first Writing data into TREGO disables the comparator tem porarily and the comparator is restarted by writing data into TREG1 Setting example generate an interrupt INTT1 every 0 5 seconds at fc 16 2 set the following values for timer registers TREGO and TREG When counting with input clock of 116 8us 16 2 0 5 sec 8us 62500 F424H Therefore set TREG1 F4H and TREGO 24H respectively Value of up counter UC1 UCO Timer 0 comparator match detect signal The comparator match signal is output from timer O each time the up counter UCO matches TREGO where the up counter UCO is not to be cleared With the timer 1 comparator the match detect signal is output at each comparator timing when up counter TREG1 values match When the match detect signal is output simultaneously from both com parators of timer O and timer 1 the up counters UCO and UC1 are cleared to 0 and the interrupt INTT1 is generated If inversion is enabled the value of the timer flip flop TFF1 is inverted Example When TREG1 and TREGO 80H 0000H 0080H 0180H 0280H 0380H 0480H s keea Interrupt INTT1 Timer output TO1 Inversion Figure 3 7 9 Output Timer by 16 Bit Timer Mode 8 bit PPG Programmable Pulse Generation Out
136. p is cleared to 0 at reset when the CPU reads the interrupt channel vector after the acceptance of interrupt or when the CPU executes an instruction that clears the interrupt of that channel writes O in the clear bit of the interrupt priority setting register For example to clear the INTO interrupt request set the register after the as follows INTEOAD Zero clears the INTO Flip Flop The status of the interrupt request flip flop is detected by reading the clear bit Detects whether there is an interrupt request for an interrupt channel The interrupt priority can be set by writing the priority in the interrupt priority setting register e g INTEOAD INTE45 etc provided for each interrupt source Interrupt levels to be set are from 1 to 6 Writing O or 7 as the interrupt priority dis ables the corresponding interrupt request The priority of the non maskable interrupt NMI pin watchdog timer etc is fixed to 7 If interrupt requests with the same interrupt level are gen erated simultaneously interrupts are accepted in accordance with the default priority the smaller the vector value the higher the priority The interrupt controller sends the interrupt request with the highest priority among the simultaneous interrupts and its vector address to the CPU The CPU compares the priority value IFF2 to O set in the Status Register by the interrupt request signal with the priority value sent if the latte
137. pattern generation mode only writing the output mode Accordingly the data shifted by trigger signal from a latch is disabled by hardware but other functions do the same timer must be written before the next trigger signal is output operation as 1 2 excitation in stepping motor control port TOSHIBA CORPORATION 109 96 141 2 Stepping Motor Control Mode Figure 3 10 8 and Figure 3 10 9 show the output uf waveforms of 4 phase 1 excitation and 4 phase 2 excita p 4 phase 1 Step 2 Step Excitation tion respectively when channel 0 PGO is selected Trigger signal from timer b4 b7 b6 b5 b4 PG00 P60 b5 b4 b7 b5 PGO1 P61 ii PG02 P62 b6 b5 b4 b7 b6 pGo3 97 56 b5 b4 b7 1 Initial value of PGOREG lt 0100 x x x x Note bn indicates the initial value of PGOREG lt b7 b6 b5 b4 x x xx Normal Rotation Trigger signa from timer b5 b6 b7 b4 b6 b7 b4 b5 PGO2 P62 b6 b7 b4 b5 b6 PGO3 P63 b7 b4 b5 b6 b7 4 Initial value of PGOREG lt 0100 x x x x Q Reverse Rotation Figure 3 10 8 Output Waveforms of 4 Phase 1 Step Excitation Normal Rotation and Reverse Rotation 110 TOSHIBA CORPORATION 96 141 Trigger signal from timer PGOO P60 24 d b6 b5 b4 PGO1 P61 54 b7 b6 b5 PG02 P62 bS b4 b7 b6 PG03 P63 57 56 b5 b4 b7 5 Initial value of PGOREG lt 0100 x xx x
138. pe 3 2524 i i i 5 UART Tofu 45 2 2 SIOCLK 72 416 5 e e 1878 64 2 p i 28 1 4732 1256 gt i i 1 Baudrate ___ C1MOD generator 5 sciMOD 11 4 2 lt 5 1 0 gt lt 5 1 0 gt i 1 Ointerface mode 1 i SCLK1 CEL 2 input 1 Shared byP95 1 4 sciMOD lt loc gt SCLK1 O Output INTRX1 INTTX1 Shared A by P95 A x Receive SC1MOD Serial channel Transmission Counter WU gt interrupt counter UART only 16 control UART only 16 RXDCLK TXDCLK SCIMOD Receive Transmission lt RXE gt control control SCICR lt PE gt EVEN RxDO Receive buffer1 Shift register Shared by P94 1 Shared by P93 IH SCICR lt OERR gt lt PERR gt lt FERR gt 4 Internal bus Figure 3 11 13 Block Diagram of the Serial Channel 1 126 TOSHIBA CORPORATION Baud Rate Generator Baud rate generator comprises a circuit that gener ates transmission and receiving clocks to determine the transfer rate of the serial channel The input clock to the baud rate generator TO fc 4 2 fc 16 8 fc 64 or 32 fc 256 is generated by the 9 bit prescaler which is shared by the timers One e UART mode Transfer rate e O interface mode Transfer rate Input clock of ba
139. pt Operation Voc 5V Ta 25 C unless otherwise noted E 20 NT 5 10 15 20 25 5 10 15 20 25 fosc MHz fosc MHz Figure 5 1 Vcc fosc TYPICAL CURVE Figure 5 2 fosc Icc TYPICAL CURVE Vcc V Figure 5 3 Icc TYPICAL CURVE lo mA 0 1 2 3 4 5 Vour V 1 40 10 30 zer 20 20 30 1 2 3 4 5 Vour V lon mA Figure 5 4 loL TYPICAL CURVE Figure 5 5 Vour TYPICAL CURVE TOSHIBA CORPORATION 159 TMP96C141AF 5 Table of Special Function Registers SFRs SFR Special Function Register The special function registers SFRs include the ports and peripheral control registers allocated to the 128 byte addresses from 000000H to 00007FH Configuration of the table 160 TOSHIBA CORPORATION 1 V O port 2 VO port control 3 Timer control 4 Pattern Generator control 5 Watch Dog Timer control 6 Serial Channel control 7 A D converter control 8 Interrupt control 9 9 Chip Select Wait Control 7 bit Symbol Read Write 7 nitial value afrer reset Remarks Table 5 Register Address 96 141 Address Name Address Name Address Name Address Name 000000H PO 20H TRUN 40H TREG6L 60H ADREGOL 1H P1 21H 41H TREG6H 61H ADREGOH 2H POCR 22H TREGO 42H
140. put mode Square wave pulse can be generated at any frequency and duty by timer O and timer 1 The output pulse may be either low active or high active In this mode timer 1 cannot be used Timer 0 outputs pulse to TO1 pin also used as P70 In this mode a programmable square wave is gener ated by inverting timer output each time the 8 bit up counter UCO matches the timer registers TREGO and TREG1 However it is required that the set value of TREGO is smaller than that of TREG1 Though the up counter UC1 of timer 1 is not used in this mode UC1 should be set for counting by setting TRUN lt T1RUN gt to 1 Figure 3 7 11 shows the block diagram for this mode TOSHIBA CORPORATION 96 141 TREGO and UCO match Interrupt INTTO TREG1 and UCO match Interrupt INTT1 TO1 Figure 3 7 10 8 Bit PPG Output Waveforms TOI TIO gt TRUN lt TORUN gt 71 gt 14 gt Selector 6116 gt 8 bit TFFCR lt TFFIIE gt 1 up counter UCO Inversion TMOD TOCLK1 0 INTTO INTT1 TREG 0 eso Shift trigger Register buffer TFFCR lt DBEN gt Figure 3 7 11 Block Diagram of 8 Bit PPG Output Mode TREG 1 T Internal bus TOSHIBA CORPORATION 65 96 141 When the double buffer of TREGO is enabled in this Use of the double buffer makes easy handling of low du
141. quency Setting of the divided frequency of baud rate generator 16 divisions Don t set 2 to 15 divisions Selecting the input clock of baud rate generator Internal clock T0 fc 4 Internal clock 72 fc 16 Internal clock 8 fc 64 Internal clock 732 fc 256 Note As all error flags are cleared after reading do not test only a single bit with a bit testing instruction Figure 3 11 4 Serial Channel Control Channel 0 BROCR 7 6 5 4 3 2 1 0 TB7 TB6 185 4 TB3 TB2 TB1 0 Transmission SCOBUF 50H 7 6 5 4 3 2 1 0 RB RB6 RB5 RB4 RB3 RB2 RBI RBO Receiving Figure 3 11 5 Serial Transmission Receiving Buffer Registers Channel 0 SCOBUF 120 TOSHIBA CORPORATION 96 141 bit Symbol Ld SC1MOD 0056H data Transfered Fix at 0 Receiving Wake Serial Transmission Function Function imode Bit 8 3 0 1 Receive Serial Transmission iclock UART 0 TOO Trigger 1 Baud rate generator 10 Internal clock 1 Ht don t care Receive 0 disable 00 interface disable 1 enable 01 10 at mode 7 Bit UART 8 Bit UART Enable 4 9 Bit UART Serial transmission clock For UART 00 Timer 0 match detect signal Baud rate generator Internal clock 1 don t care Note The clock selection for the I O int
142. r 16 bits for any of the three block address areas 3 6 1 Control Registers Table 3 6 1 shows control registers One block address areas are controlled by 1 byte CS 5 WAIT control registers BOCS B1CS and B2CS Registers can be written to only when the CPU is in system mode There are two CPU modes system and normal The reason is that the settings of these registers have an important effect on the system 1 Enable Control register bit 7 BOE B1E and B2E is a master bit used to specify enable 1 disable 0 of the setting Resetting BOE and B1E to disable 0 and B2E to enable 1 2 System only specification 6 Control register bit 6 BOSYS B1SYS and B2SYS is used to specify enable disable of the setting depend ing on the CPU operating mode system or normal Setting this bit to O enables setting Address space for CS Wait state Bus size etc regardless of the CPU operating mode setting it to 1 enables setting in sys tem mode but disables setting in normal mode Resetting clears bit 6 to O Bit 6 is mainly used when external memory data should not be accessed in normal mode i e for system mode only memory data for the operating system 3 _ CS CAS Waveform select Control register bit 5 BOCAS B1CAS and B2CAS is used to specify waveform mode output from the chip select pin CSO CASO CS2 CAS2 Setting this bit to 0 specifies CSO to CS2 waveforms setting it to 1 specifies CASO to CAS2 wa
143. r SWIT 0010 8010 3 INTUNDEF Illegal instruction or SWI2 0020H 8020H 4 SWI 3 Instruction 0030H 8030H 5 Non SWI 4 Instruction 0040H 8040H 6 Maskable cwi Instruction 0050H 8050H 2 7 SWI 6 Instruction 0060H 8060H 8 SWI 7 Instruction 0070 8070 9 NMI Pin 0080H 8080H 08H 10 NTWD Watchdog timer 0090H 8090H 09H 11 INTO pin 00 0 80A0H OAH 12 NT4 pin 00B0H 80 0 OBH 13 NT5 pin 00C0H 80 C0H OCH 14 NT6 pin 00DO0H 80DO0H 15 NT7 00E0H 80 0 OEH Reserved 00 0 80FO0H OFH 16 INTTO 8 bit timer 0 0100 8100 10 17 8 bit timer 1 0110 8110 18 2 8 bit timer 2 PWMO 0120 8120H 12H 19 INTT3 8 bit timer 3 PWM1 0130H 8130H 13H 20 INTTR4 16 bit timer 4 TREG4 0140 8140 14H 21 INTTR5 16 bit timer 4 TREG5 0150H 8150 15H 22 INTTR6 16 bit timer 5 TREG6 0160H 8160H 16H 23 INTTR7 16 bit timer 5 TREG7 0170H 8170H 17H 24 INTRXO Serial receive Channel 0 0180H 8180 18H 25 INTTXO Serial send Channel 0 0190H 8190H 19H 26 INTRX1 Serial receive Channel 1 01 0 81 0 27 Serial send Channel 1 01 0 81 0 1 28 INTAD A D conversion completion 01 COH 81 0 1CH Reserved 01D0H 81D0H 1DH Reserved 01E0H 81 0 1EH Reserved 01 0 81 1FH 3 3 2 High Speed Micro DMA In addition to the conventional interrupt processing the TLCS 900 also has a high speed micro DMA function When an inte
144. r is higher the interrupt is accepted Then the CPU sets a value higher than the priority value by 1 in the CPU SR IFF2 to O gt Interrupt requests where the priority value equals or is higher than the set value are accepted simultaneously during the previous interrupt routine When interrupt processing is completed after execution of the RETI instruction the CPU restores the priority value saved in the stack before the interrupt was generated to the CPU SR IFF2 to 0 The interrupt controller also has four registers used to store the high speed micro other DMA start vector These are O registers unlike other DMA registers DMAS DMAD DMAM and DMAC they can be accessed in either normal or system mode Writing the start vector of the interrupt source for the micro DMA processing see Table 3 3 1 enables the corre sponding interrupt to be processed by micro DMA processing The values must be set in the micro DMA parameter registers e g DMAS and prior to the micro DMA processing TOSHIBA CORPORATION TMP96C141AF Interrupt controller Interrupt request flip flop NMI Interrupt vector V read Interrupt request F F Interrupt request signal to CPU Priority encoder 1 an Highest A priority interrupt 4 levelselect C Interrupt vector read CPU interrupt enable RESET flag on CPU side IFF2 0 El 1
145. r used to control the prescaler is the same as the one for other timers the prescaler cannot be operated indepen dently The PWM timer uses three input clocks 1 P4 and 16 Like the 9 bit prescaler described in the 8 bit timer section this prescaler can be counted stopped using bit 7 lt PRRUN gt of the timer operation control register TRUN Setting PRRUN to 1 starts counting setting it to O zero clears and stops counting Resetting clears PRRUN to 0 which clears and stops the prescaler Dedicated Prescaler Cycle Oscillator circuit 12 16MHz 20MHz P1 4 250ns 200ns 16 fc 116 800ns 16 64 fc Aus 3 2usc gP4 gP16 1 2 3 4 Prescaler run stop amp clear TRUN lt PRRUN gt Figure 3 8 2 Prescaler Q Up counter An 8 bit binary counter which counts up using the input clock specified by PWM mode register POMOD or P1MOD The input clock for the PWMO PWMI is selected from the internal clocks 1 4 and 16 PWM dedi cated prescaler output depending on the value set in the POMOD P1MOD register Operating mode is also set by POMOD and P1MOD registers At reset they are initialized to POMOD lt PWMOM gt and P1MOD lt PWM1M gt thus the up counter is in PWM mode PWM mode the up counter is cleared when a 2 1 overflow occurs in timer mode the up counter is cleared at compare and 72 match Count st
146. rpose I O port I O can be set on bit basis using the control register P2CR and function register P2FC Resetting resets all bits of output latch P2 control regis ter P2CR and function register P2FC to O It also sets Port 2 to TMP96C141AF input mode and connects a pull down resistor To disconnect the pull down resistor write 1 in the output latch In addition to functioning as a general purpose I O port Port 2 also functions as an address data bus AO to 7 and an address bus 16 to 23 Ma Reset Direction control on bit basis P2CR write gt Function control 2 on bit basis m A v P2FC write 9 Output I P ort2 Output bufer A0 A7 A16 A23 2 P2 write N ch Programmable pull down mr P2 read Figure 3 5 4 Port 2 TOSHIBA CORPORATION 27 96 141 ECHN NN N 0006H R W Input mode Output latch register is cleared 0 Port 2 Control Register el P2CR P27C P26C P25C P24C P23C P22C 2 P20C 0008H P2FC bit Symbol P27F P26F 25 0009H After reset Function Read modify write is Port 2 function setting prohibited for registers P2CR and P2FC address bus A7 0 address bus A23 16 Note lt P2XF gt is bit X in register P2FC lt P2XC gt in register P2CR To set as an address bus A23 16 set P2FC after setting P2CR Figure 3 5 5
147. rrupt is accepted in addition to an interrupt vector the CPU receives data indicating whether processing is high speed micro DMA mode or general purpose interrupt If high speed micro DMA mode is requested the CPU performs high speed micro DMA processing 12 The TLCS 900 can process at very high speed com pared with the TL CS 90 micro DMA because it has transfer parameters in dedicated registers in the CPU Since those dedicated registers are assigned as CPU control registers they can only be accessed by the LDC privileged instruction TOSHIBA CORPORATION 1 High Speed Micro DMA Operation High speed micro DMA operation starts when the accepted interrupt vector value matches the micro DMA start vector value set in the interrupt controller The high speed micro DMA has four channels so that it can be set for up to four types of interrupt source When a high speed micro DMA interrupt is accepted data is automatically transferred from the transfer source address to the transfer destination address set in the control register and the transfer counter is decremented If the value in the counter after decrementing is other than O high speed micro DMA processing is completed If the value in the counter after decrementing is O general purpose interrupt processing is performed In read only mode which is provided for DRAM refresh the value in the counter is ignored and dummy read is repeated The 32 bit control registers are used
148. s register 1 Transfer destination address register 1 Transfer counter register 1 Transfer mode register 1 Transfer source address register 2 Transfer destination address register 2 Transfer counter register 2 Transfer mode register 2 Transfer source address register 3 Transfer destination address register 3 Transfer counter register 3 Transfer mode register 3 These Control Registers cannot be set only LCD cr r instruction cept the Read only mode is same as this Condition MIN mode 16bit Bus width for 16M Byte O wait Use only lower 24 bits 1 65536 14 TOSHIBA CORPORATION TMP96C141AF 8 Transfer Mode Register Details DMAMO 3 0 0 0 0 Mode Note When specifying values for this register set the upper 4 bits to 0 execution time Min 20M Hz p 2 0 byte transfer 1 word transfer 0 0 0 7 Transfer destination address INC mode for I O to memory 16 states DMADn lt DMASn DMACn DMACn 1 1 65 if DMACn 0 then INT 0 16 states DMADn lt DMASn DMACn DMACn 1 if DMACn 0 then INT 0 1 2 Transfer destination address DEC mode for 1 0 to memory 1 6 ys 0 1 0 7 Transfer source address INC mode for I O to memory 16 states DMADn DMASn DMACn DMACn 1 1 645 if DMACn 0 then INT 0 1 1 Transfer source address DEC mode forl O to memory 16 states DMADn lt DMASn
149. sets IDLE mode 1 Set the standby mode amp Set the STOP mode warming up time 2164 WDMOD e 1 0 1 Executes HALT command 150 X X Set the STOP mode Execute HALT instruction Set the standby mode TOSHIBA CORPORATION 4 Electrical Characteristics 4 1 Absolute Maximum TMP96C144AF TMP96C141AF Symbol Parameter Rating Unit Voc Power Supply Voltage 0 5 6 5 V VIN Input Voltage 0 5 Vec 0 5 V gt 01 Output Current total 100 mA Output Current total 100 mA PD Power Dissipation Ta 70 C 600 mW T SOLDER Soldering Temperature 10s 260 C TSTG Storage Temperature 65 150 20 Operating Temperature 20 70 it 4 2 DC Characteristics TMP96C141AF Voc 5V 10 Ta 20 70 C Typical values are for Ta 25 C V 5V Symbol Parameter Min Max Unit Test Condition VIL Input Low Voltage AD0 15 0 3 0 8 V VILI P2 P3 P4 P5 P6 P7 P8 P9 0 3 0 3 Vec V VIL2 RESET NMI INTO P87 0 3 0 25 V VIL3 EA 0 3 0 3 V VIL4 x1 0 3 0 2Vo V V IH Input High Voltage AD0 15 22 0 3 V V IH1 P2 P3 P4 P5 P6 P7 P8 P9 0 7 Voc Vec 0 3 V V IH2 RESET NMI INTO P87 0 75Voc Ve 0 3 V V IH3 EA Vec 0 3 Vec 0 3 V V IH4 X1 0 8 Voc Vec 0 3 V VOL Output Low Voltage 0 45 V 10L 1 6mA V OH Output High Voltage 24 V LOH 400A V 0H1 0 75 0 V LOH 100pA V OH2 0 9V V LOH 20pA DR
150. sets the stack pointer XSP on the Figure 3 2 Memory Map TOSHIBA CORPORATION 3 8 Interrupts The TLCS 900 interrupts are controlled by the CPU interrupt mask flip flop IFF2 to O and the built in interrupt controller The TMP96C141AF have altogether the following 23 interrupt sources TMP96C141AF A fixed individual interrupt vector number is assigned to each interrupt source six levels of priority variable can also be assigned to each maskable interrupt Non maskable inter rupts have a fixed priority of 7 When an interrupt is generated the interrupt controller Interrupts from the Interrupts from built in 1 5 14 Software interrupts privileged violations and Illegal undefined instruction execution Interrupts from external pins NMI INTO and INT4 to 7 6 sends the value of the priority of the interrupt source to the CPU When more than one interrupt is generated simulta neously the interrupt controller sends the value of the highest priority 7 for non maskable interrupts is the highest to the CPU The CPU compares the value of the priority sent with the value in the CPU interrupt mask register IFF2 to 0 If the value is greater than that of the CPU interrupt mask register the interrupt is accepted The value in the CPU interrupt mask reg ister IFF2 to 0 be changed using the EI instruction con tents of the El num IFF 2 0 num For example programming El
151. ster Slave 1 Select code Select code 00000001 00001010 Since serial channels O and 1 operate in exactly the channel 0 is used for the purposes of explanation same e Setting the master controller Main setting P9CR lt x X 0 P9FC m _ g Select P90 as TxD pin and P91 as RxD pin INTESO lt 1 1 0 0 1 1 0 1 Enable INTTXO and sets the interrupt level 4 Enable INTRXO and sets the interrupt level 5 SCOMOD lt 1 0 1 0 1 1 1 0 Set 01 fc 2 as the transmission clock in 9 bit UART mode SCOBUF lt 0 0 0 0 0 0 0 1 Set the select code for slave controller 1 INTTXO interrupt SCOMOD 0 Set TB8 to 0 SCOBUF e 4 P Set data for transmission e Setting the slave controller 2 Main setting P9CR lt Select P91 as RxD pin and P90 as TxD pin open drain output P9FC lt ODE lt lt Enable and INTTXO lt Set WU to 1 in the 9 0 UART transmission mode with transfer clock 1 fc 2 INTESO SCOMOD gt x gt lt hoa xe tme O XxX X INTRXO interrupt Acc SCOBUF If Acc Select Code Then SCOMOD4 o WS CD Clear WU to 0 138 TOSHIBA CORPORATION 96 141 3 12 Analog Digital Converter Figure 3 12 1 shows the block diagram of the A D con The TMP96C141AF contains a high speed analog digital con Verter The 4 channel analog input pins ANS to ANO are verter
152. sters are used for controlling programmable pull up pull down If a pin is also used for an output function e g TO1 and the output function is specified whether pull up or pull down is selected depends on the output function data If a pin is also used for an input function whether pull up or pull down is selected depends on the port register setting value only 22 TOSHIBA CORPORATION 3 5 Functions of Ports The TMP96CMAOF TMP96PMAOF has 65 bits for I O ports The TMP96C141AF TMP96C041AF has 47 bits for I O ports because Port1 P30 and P31 are dedicated pins for ADO to 7 AD8 to 15 RD and WR TMP96C141 AF These port pins have I O functions for the built in CPU and internal I Os as well as general purpose port func tions Table 3 5 lists the function of each port pin Table 3 5 Functions of Ports T With programmable pull up resistor With programmable pull down Port Name Pin Name E of Direction R Direction Setting Unit Pin Name for Built in Function Porto P00 P07 8 0 Bi ADO AD7 Porti P10 P17 8 0 Bi AD8 AD15 8 A15 Port2 P20 P27 8 0 Bi AO A7 M6 A23 Port 3 P30 1 Output Fixed RD P31 Output Fixed WR P32 0 Bi HWR P33 0 T Bi WAIT P34 0 T Bi BUSRQ P35 0 Bi BUSAK P36 0 Bi RW P37 0 T Bi RAS Port 40 0 Bi CS0 CASO P41 0 Bi 051 CAST 42 0 l Bi CS2 CAS2 Port5 P50 P53
153. t Trigger iTrigger 10 8 bit 10 8 bit 20 Disable Timer Trigger Timer Trigger 1 Enable 0 1 0 1 i Double pouble 16bit 11 11600 bufferof buffer of Timer Trigger Timer Trigger TREGE t TREGA XTimer 5 Timer 4 Double buffer countrol DB6EN Double buffer of TREG6 DB4EN Double buffer of TREG4 Figure 3 9 9 16 Bit Timer Timer 4 5 Control Register 45 bit Symbol PRRUN TSRUN TARUN PIRUN PORUN 2 TIRUN TORUN TRUN 0020H Prescaler amp Timer Run Stop CONTROL 0 Stop amp Clear 1 Run Count up Operation of 16 bit timer timer4 Stop and clear Count STOP and clear Count Figure 3 9 10 Timer Operation Control Register TRUN TOSHIBA CORPORATION 93 96 141 Up counter UC4 UC5 UC4 UC5 is a 16 bit binary counter which counts up according to the input clock specified by TAMOD lt T4CLK1 O gt or TBMOD T5CLK1 O gt register As the input clock one of the internal clocks T1 8 fc e T4 32 fc and T16 128 fc from 9 bit prescaler also used for 8 bit timer and external clock from TI4 pin also used as P80 INT4 pin or TI6 also used as P84 INT6 pin can be selected When reset it will be initialized to lt T4CLK1 0 T5CLK1 O gt 00 to select TIA TIO input mode Counting or stop and clear of the counter is controlled by timer operation contro
154. t 10 Clear 10 Disable 0 Timer 0 1 Enable 11 don tcare 4 Enable Do Always read as TFF1IS 21 Timer 1 Select inverse signal of timer F F1 Don t care excep in 8 bit timer mode gt Inversion by 16 bit timer mode PPG mode 0 match Inversion by Inversion by signal match signal match signal of each timer 0 and timer 1 1 Inversion by timer1 match signal Inversion of Timer F F1 TFF1 Disable invert invert the value of TFF1 software inversion Disable double Buffer Enable double Buffer Figure 3 7 6 Timer Flip Flop Control Register TFFCR Inversion by match and overflow signal of timer 0 60 TOSHIBA CORPORATION The operation of 8 bit timers will be described below 1 8 bit timer mode Two interval timers O 1 can be used independently as 8 bit interval timer All interval timers operate in the same manner and thus only the operation of timer 1 will be explained below MSB LSB 7 6 5 4 3 2 1 0 TRUN 528 X 0 TMOD lt 0 0 X X 0 1 TREG1 lt 0 1 0 1 0 0 0 0 INTETIO lt 1 1 0 1 TRUN lt 1 X 1 Note x don t care no change Use the following table for selecting the input clock Stop Set th Set th Enabl TMP96C141 AF Generating interrupts in a fixed cycle To gen
155. t TFF3 to 1 Clear TFF3 to 0 Don t care Figure 3 8 6 8 Bit PWM F F Control Register 76 TOSHIBA CORPORATION 96 141 TRUN PORUN TIRUN TORUN 0020H TSRUN T4RUN P1RUN ee Read Write 7 i 6 RW oo i After reset Prescaler amp Timer Run Stop CONTROL 0 Stop amp Clear 1 Run Count up Function 8 bit timer timer0 operation Stop amp clear Count Stop amp clear Count Stop amp clear Count Stop amp clear Count Stop amp clear Count Stop amp clear Count Figure 3 8 7 Timer Operation Control Register TRUN TOSHIBA CORPORATION 77 96 141 The following explains PWM timer operations 1 PWM timer mode Both PWM timers can output 8 bit resolution PWM independently Since both timers operate in exactly the same way PWMO is used for purposes of explanation PWM output changes under the following two condi tions Condition 1 e TFF2 is cleared to O when the value in the up counter UC2 and the value set in the TREG2 match TFF2 is set to 1 when a 2 1 counter overflow n 6 7 or 8 occurs Condition 2 e TFF2 is set to 1 when the value in the up counter UC2 and the value set in TREG2 match TFF2 is cleared to O when a 2 1 counter over flow n 6 7 or 8 occurs The up counter UC2 is cleared by a 2 1 coun
156. ter overflow The PWM timer can output O96 10096 duty pulses because a 2 1 counter overflow has a higher priority That is to obtain 096 output always low the mode used to set TFF2 to 0 due to overflow PFFCR lt FF2TRG1 0 1 0 must be set and 2 1 value for overflow must be set in TREG2 To obtain 10096 out put always high the mode must be changed PFFCR lt FF2TRG1 O gt 1 1 then the same operation is required PWM timing n TRITT mer Ac o Match detect eee A detail 2n 1overflow M counter clear Match detect Overall timing 2n 1overflow Note Timer F F output TO2 TO3 Figure 3 8 8 Output Waves in PWM Timer Mode Note above waves are obtained in a mode where the is set by a match with the timer register TREG and reset by an overflow 78 TOSHIBA CORPORATION 96 141 Figure 3 8 9 is a block diagram of this mode Clock control EN POMOD T2CLK1 0 gt 8 bit up counter UC2 POMOD lt PWM0S1 0 gt 2n 1overflow control overflow overflow 8 bit comparator CP2 PFFCR lt FF2TRG1 0 gt PFFCR lt FF2C1 0 gt TO2 F F control 8 bit timer register TREG2 Shift trigger 59 T Interrupt Register buffer control POMOD lt PWMOINT gt B Selctor Y A TREG2 WR 5 POMOD
157. ter are always read as 1 170 TOSHIBA CORPORATION 96 141 8 Interrupt Control 1 2 INTE Een s 70H OAD lop Prohibit RMW INTerrupt INTE45 Enable 71H 4 5 Prohibit RMW INTerrupt 7 INTE67 Enable a 6 7 Prohibit RMW INTerrupt 7 INTET10 Enable Timer 1 0 Prohibit RMW INTE UN 74H PW10 2425 Prohibit RMW INT errupt 75H INTET54 Enable na Treg 5 4 Prohibit 9 RMW INTerrupt H INTET76 Enable 76 Treg 7 6 Prohibit 3 RMW INTerrupt INTESO Enable dp Serial 0 Prohibit eria RMW INTerrupt Enable Serial 1 TRES Prohibit RMW symbol Name Address 7 e s 4 3 To To Function Read Function Write 0 Indicate no interrupt request Clear interrupt request flag INTAD IADC IADM2 1 1 IADMO 10 J0M2 10 1 0 INT4 2 RW 0 0 0 6 RW 0 0 0 UC 17 2_ UM 7 17 0 0 RW w gor c 0 20 50 1 0 4 0 5 60 0 1 INTTO Timer 0 ITIC 2 ITiM1 ITIMO ITOC ITOM2 ITOM1 ITOMO W 0 0 0 INTT3 Timer 3 PWM1 INTT2 Timer 2 0 IPW1C IPW1M2 IPW1M1 IPW1MO IPWOC IPWOM2 IPWOM1 IP
158. tern generator PGO PG1 output PGO is data bus Internal TOSHIBA CORPORATION PGO 1 Reset Direction control on bit basis P6CR write Function control on bit basis P6FC write 5 Output latch S Selector I P6 write gt gt 5 B 4 lt Selector P6read Figure 3 5 13 Port 6 corresponding bit of the port 6 function register P6FC enables PG output Resetting resets the function register P6FC value to 0 and sets all bits to ports Programmable pull up Port6 P60 P67 00 13 37 TMP96C141AF 38 Port 6 Register 6 bit Symbol 0012H Read Write After reset P6CR Ud METRE E DNE P67C P65C PEAC P63C P62C 6 6 L gt Port6i O setting Input Output P6FC 0016H bit Symbol P65F P64F P63F P62F Read Write Read modify write is prohibited for registers Port 6 function setting P6CR and P6FC 0 General purpose port Stepping motor control Pattern generation port Figure 3 5 14 Registers for Port 6 TOSHIBA CORPORATION 3 5 8 Port 7 P70 P73 Port 7 is a 4 bit general purpose I O port I O can be set on bit basis Resetting sets Port 7 as an input port and connects a pull up resistor In addition to functioning as a gener
159. th parity However parity can be added only in 7 bit UART or 8 bit UART mode With SCOCR lt EVEN gt SC1CR EVEN register even odd parity can be selected For transmission parity is automatically generated according to the data written in the transmission buffer SCBUF and data are transmitted after being stored in SCOBUF TB7 SC1BUF lt TB7 gt when in 7 bit UART mode while in SCMOD lt TB8 gt SCMOD lt TB8 gt when in 8 bit UART mode PE and EVEN must be set before transmission data are written in the transmission buffer For receiving data is shifted in the receiving buffer 1 and parity is added after the data is transferred in the receiving buffer 2 GCOBUF SC1 BUF and then com pared with SCOBUF RB7 SC1BUF RB7 when in 7 Generating Timing 1 UART mode TMP96C141AF bit UART mode and with SCOMOD RB8 SC1MOD RB8 when in 8 bit UART mode If they are not equal a parity error occurs and SCOCR lt PERR gt SC1CR lt gt flag is set Error Flag Three error flags are provided to increase the reliabil ity of receiving data 1 Overrun error lt OERR gt If all bits of the next data are received in receiving buffer 1 while valid data is stored in receiving buffer 2 SCBUF an overrun error will occur Parity error lt PERR gt The parity generated for the data shifted in receiving buffer 2 SCBUF is compared with the parity bit received from RxD pin If they are not
160. tput Data rising edge of SCLK tscy 2 5x 50 137 100 ns tous SCLK rising edge output data hold 5x 100 212 150 ns lucn SCLK rising edgeinput data hold 0 0 0 ns tsap SCLK rising edge effective data input 5x 100 587 450 ns 2 SCLK Output Mode Variable 16MHz 20MHz Symbol Parameter Unit Min Max Min Max Min Max SCLK cycle programmable 16x 8192x 1 512 0 8 409 6 uS toss Output Data rising edge of SCLK tscy 2x 150 705 590 ns tons SCLK rising edge output data hold 2x 80 45 20 ns lucn SCLK rising edge input data hold 0 0 0 ns tsap SCLK rising edge effective data input tscy 2x 150 705 590 ns 4 6 Timer Counter Input Clock TIO 4 TI5 6 Vec 5V 10 TA 20 70 C Variable 16MHz 20MHz Symbol Parameter Unit Min Max Min Max Min Max tyck Clock cycle 8x 100 600 500 ns Low level clock pulse width 4x 40 290 240 ns tVCKH High level clock pulse width 4x 40 290 240 ns TOSHIBA CORPORATION 155 96 141 4 7 Interrupt Operation Vec 5V 10 Ta 20 70 C Variable 16MHz 20MHz Symbol Parameter Unit Min Max Min Max Min Max tina NMI INTO Low level pulse width 4x 250 200 ns NMI INTO High level pulse width 4x 250 200 ns tinreL 4 Low level pulse width 8x 100 600 500 ns INT4 INT7 High level pulse width 8x 100 600 500 ns 156 TOSHIBA CORPORAT
161. tput latch registers to 1 Resets all bits of the P42 output latch register the control register PACR and the function register PAFC to O Sets P40 and P41 to input mode and connects a pull up resistor Sets P42 to input mode and connects a pull down resistor TOSHIBA CORPORATION 33 TMP96C141AF 34 data bus Internal data bus Internal Reset Direction control on bit basis PACR write Function control on bit basis A Programmable write P ch pull up Output buffer P4 read Direction control on bit basis n PACR write Function control on bit basis write Output buffer Selector 4 P4 write Programmable pull down P4 read Figure 3 5 9 Port 4 0 P41 CS1 CAS1 P42 CS2 CAS2 TOSHIBA CORPORATION TMP96C141AF Port 4 Register p 000CH read write 4 Input mode After reset H EE i 0 Pull down 1 1 Pull up e bit Symbol 000EH Read Write After reset i O setting 0 Input 1 Output Port 4 Function Register P4FC bit Symbol 0010H Read Write After reset Function Read modify write is not possible for P4CR or P4FC 0 Port P40
162. ty mode the value of register buffer will be shifted in TREGO each waves when duty is varied time TREG1 matches UCO Match with TREGO and up Counter Up counter Up counter Q Match with TREG 1 Shift from register buffer TREG O Value to be compared Registe buffer Q Q3 TREG 0 register buffer write Figure 3 7 12 Operation of Register Buffer Example Generating 1 4 duty 50KHz pulse fc 16 2 za snos 20 5 Calculate the value to be set for timer register TREG1 40 28H and then duty to 1 4 tx 1 4 To obtain the frequency 50KHz the pulse cycle t 20us x 1 4 5us should be t 1 50KHz 20ys O 5us 10 Given 9 1 0 5us 16 2 Therefore set timer register 0 TREGO to TREGO 10 20us F 0 5us 40 OAH Consequently to set the timer register 1 TREG1 to 7 6 5 4 3 2 1 0 TRUN oo X 0 0 Stop timer 0 and clear it to 0 TMOD 1 0 X X X X 0 1 Set the 8 bit PPG mode and select 11 as input clock TREGO 0 0 0 0 1 0 1 0 Write OAH TREG1 0 0 1 0 1 0 0 0 Write 28H TFFCR 1 o 1 1 X Sets TFF1 and enables the inversion and double buffer enable gt Writing 10 provides negative logic pulse LER ai ce cwn ce Pel we Set P71 as TO1 pin P7FC lt x X X X 1 TRUN 1 X 1 1 Start timer 0 and timer 1 counting Note x don t care no change 66 TOSHIBA CORPORATION 96 141 4 8 bit PWM Output
163. ud rate generator Frequency divisor of baud rate generator TMP96C141AF of these input clocks is selected by the baud rate genera tor control register BROCR BR1CR lt BROCK1 0 O gt The baud rate generator includes a 4 bit frequency divider which divides frequency by 2 to 16 values to determine the transfer rate How to calculate a transfer rate when the baud rate generator is used is explained below T 16 Input clock of baud rate generator Frequency divisor of baud rate generator The relation between the input clock and the source clock fc is as follows 0 fc A 2 fc 16 018 fc 64 132 10 256 Accordingly when source clock is 12 288 MHz input clock is T2 fc 16 and frequency divisor is 5 the transfer rate in UART mode becomes as follows Transfer rate fc 16 16 5 12 288 x 106 16 5 16 9600 bps Table 3 11 1 shows an example of the transfer rate in UART mode Also with 8 bit timer O the serial channel can get a transfer rate Table 3 11 2 shows an example of baud rate using timer O Table 3 11 1 Selection of Transfer Rate 1 When Baud Rate Generator is Used Unit kbps Input Clock fc Mhz P oTo T2 8 132 fc 4 fc 16 fc 64 fc 256 Divisor 9 830400 2 76 800 19 200 4 800 1 200 T 4 38 400 9 600 2 400 0 600 T 8 19 200 4 800 1 200 0 300 T 0 9 600 2 400 0 600 0 150 12 288000 5 38 400 9 600 2 400 0 600 T A 19 200 4 800
164. ue of timer flip flop TFF1 can be inverted inde pendent of timer operation Writing 00 into TFFCR TFF1C1 0 memory address 000025h of bit 3 and bit 2 inverts the value of TFF1 Initial setting of timer flip flop TFF1 The value of TFF1 can be initialized to 0 or 1 inde pendent of timer operation For example write 10 in TFFCR TFF1C1 0 to clear TFF1 to 0 while write 01 in TFFCR TFF1C1 O to set to 1 Note The value of timer register cannot be read 16 bit timer mode A 16 bit interval timer is configured by using the pair of timer O and timer 1 To make a 16 bit interval timer by cascade connecting timer O and timer 1 set timer O timer 1 mode register TMOD lt T10M1 O gt to 0 1 When set in 16 bit timer mode the overflow output of timer O will become the input clock of timer 1 less of the set value of TMOD T1CLK1 O gt Table 3 7 2 shows the relation between the cycle of timer inter rupt and the selection of input clock Table 3 7 2 16 Bit Timer Interrupt and Input Clock Interrupt Cycle Interrupt Cycle Input Clock at 16MHz Resolution at fc 20MHz Resolution 8 fc 0 55 32 786ms 0 55 0 45 26 214ms 0 45 914 32 fc 245 131 0725 25 1 65 104 857ms 1 6us 116 128 fc 8us 524 288ms 8us 6 45 419 430ms 6 46 TOSHIBA CORPORATION 63 96 141 64 l
165. ut pin TO1 timer 1 Example To output a 3 0us square wave pulse from 7 6 5 4 3 2 1 0 TRUN fm X 0 Stop timer 1 and clear it to 0 TMOD 0 0 X X 0 1 EIE Set the 8 bit timer mode and select 9T1 0 55 fc 16MHz as the input clock TREG1 lt 0 0 0 0 0 0 1 1 Set the timer register at 3 0us 911 2 3 TFFCR lt 1 0 1 1 Clear to 0 and set to invert by the match detect signal from timer 1 P7CR lt x X X X 1 Select P71 as 01 pin P7FC lt x X X X 1 i TRUN 1 X Start timer 1 counting Note x don t care no change ded ET SEE EL TRUN lt 1 gt 7 2 Up counter BIT1 BITO 0 1 2 3 a 1 2 3 0 1 2 3 0 Comparator timing a Comparator output matching detect UC clear ce ee lt 12 1 55 16MHz Figure 3 7 7 Square Wave 50 Duty Output Timing Chart 62 TOSHIBA CORPORATION Making timer 1 count up by match signal from timer O comparator Comparator output Timer 0 match Timer 0 up counter when TREGO 5 Timer 1 up counter 1 when TREG1 2 TMP96C141AF Set the 8 bit timer mode and set the comparator out put of timer O as the input clock to timer 1 v d 1 Timer 1 match output Figure 3 7 8 Timer 1 Count Up by Timer 0 Output inversion with software The val
166. utput mode setting LD P4FC 07H 52 TOSHIBA CORPORATION 3 6 4 How to Start with 8 Bit Data Bus Resetting sets the CS2 pin low due to an internal pull down resistor memory access starts in 16 bit data bus 2 wait B2CS EQU 6 ORG 8000H LDX B2CS 9CH After reset the program reads the LDX B2CS 9CH instruction in 16 bit data bus mode LDX is a 6 byte instruc tion the 2nd 4th and 6th bytes are handled as dummies i e only codes in the 1st 3rd and 5th bytes are actually used Even if starting in 8 bit data bus mode it is possible to pro gram so that the LDX instruction is executed and the block 2 Address latch TLCS 900 TMP96C141 A15 DQ G A8 AD8 15 DQ j G 0 D7 ADO 7 ALE oe TOSHIBA CORPORATION EPROM TMP96C141AF mode To start in 8 bit data bus mode a special operation is required Operation is as described in the example below CS2 register address RESET address CS2 8 bit OWAIT 8000H area 8000H SFFFFFH is accessed in 8 bit data bus mode without any problem The above program does not include setting the P42 52 pin to output add a program to set the PACR and P4FC registers as required Operation after reset TLCS 900 8000H 8001H 8002H 8003H 8004H 8005H LDX 9 don t care 53 96 141 3 7 8 bit Timers The TMP96C141AF contains two 8 bit timers timers 0 and 1 each o
167. ved data to data receive buffer 2 SC1BUF that is immediately after SCLK See Figure 3 11 22 Transmission interrupt timin k SCLK input mode SCLK output mode Receiving interrupt timing SCLK input mode 3 11 3 Operational Description This mode is used to increase the number of I O pins for trans mitting or receiving data to or from the external shifter register 1 Mode I O interface mode This mode includes SCLK output mode to output syn chronous clock SCLK and SCLK input mode to input external synchronous clock SCLK Output Input extension extension TMP96C141 Shift register 96 141 Shift register lt B TxD SI C RxD QH C D D lt SCLK SCK E SCLK CLOCK lt F F Port RCK G Port gt S L G lt 74 595 TC74HC165 or the like the like Figure 3 11 17 Example of SCLK Output Mode Connection Output port Input port extension extension TMP96C141 Shift register TMP96C141 Shift register A B B TxD gt si RxD lt QH D D SCLK SCK E SCLK CLOCK Fl Fl lt RCK G Port S L G lt H poor TC74HC595 or TC74HC165 or the like the like External clock External clock Flgure 3 11 18 Example of
168. veforms Resetting clears bit 5 to 0 4 Data bus size select Bit 4 BOBUS B1BUS and B2BUS of the control reg 48 ister is used to specify data bus size Setting this bit to O accesses the memory in 16 bit data bus mode set ting it to 1 accesses the memory in 8 bit data bus mode Changing data bus size depending on the access address is called dynamic bus sizing Table 3 6 2 shows the details of the bus operation Wait control Control register bits 3 and 2 BOW1 0 B1W1 0 B2W1 0 are used to specify the number of waits Setting these bits to OO inserts a 2 state wait regardless of the WAIT pin status Setting them to 01 inserts a 1 state wait regardless of the WAIT status Setting them to 10 inserts a 1 state wait and samples the WAIT pin status If the pin is low inserting the wait maintains the bus cycle until the pin goes high Setting them to 11 com pletes the bus cycle without a wait regardless of the WAIT pin status Resetting sets these bits to 00 2 state wait mode Address area specification Control register bits 1 and O BOC1 0 B1C1 0 B2C1 0 are used to specify the target address area Setting these bits to 00 enables settings CS output Wait state Bus size etc as follows CSO setting enabled when 7FOOH to 7FFFH is accessed CS1 setting enabled when 480H to 7FFFH is accessed CS2 setting enabled when 8000H to SFFFFFFH is accessed for the TMP96C144 which does
169. w 96 141 again Interrupts are generated requests the next send data to the CPU Though there is no RTS pin a hand shake function can be easily configured by setting any port assigned to the RTS func tion The RTS should be output High to request data send halt after data receive is completed by a software in the RXD interrupt routine TxD RxD CTS Sender RTS any port Receiver Figure 3 11 15 Handshake Function Timing to write ET transmission buffer Send is suspended CTS from 1 to 2 13 14 15 16 SIOCLK TxDCLK w He Note 1 If the CTS signal falls during transmission the next data is not sent after the completion of the current transmission Note 2 Transmission starts at the first TXDCLK clock fall after the CTS signal falls Figure 3 11 16 Timing of CTS Clear to Send 130 TOSHIBA CORPORATION Transmission Buffer Transmission buffer SCOBUF SC1 BUF shifts to and sends the transmission data written from the CPU from the least significant bit LSB in order using transmission shift clock TxDSFT which is generated by the transmis sion control When all bits are shifted out the transmis sion buffer becomes empty and generates interrupt Parity Control Circuit When serial channel control register SCOCR lt PE gt SC1CR PE is set to 1 it is possible to transmit and receive data wi
170. ways read as 1 The up counter 5 value is loaded to CAP3 Figure 3 9 7 16 Bit Timer Control Register 5 2 2 TOSHIBA CORPORATION 91 96 141 T5FFCR bit Symbol 5 4 6 CAP3T6 EQ7T6 EQ6T6 TFF6C1 TFF6CO 0049H Read Write After reset iTFF6 invert trigger 100 Invert TFF6 0 Disable trigger i01 Set TFF6 11 Enable trigger 10 Clear TFF6 1 211 care invertwhen Invertwhen Invertwhen invertwhen Function ithe UC value the UC value the UC ithe UC UK Always read as tis loaded to is loaded to i matches matches 1 7 TREG6 Timer flip flop 6 TFF6 control Inverts the 4 value software inversion Sets TFF6 to 1 Clear TFF6 to 0 Don t care Always read as 11 Timer flip flop 6 TFF6 invert trigger Trigger disable Invert prohibition Trigger enable Invert permission CAP4T6 Invert when the up counter value is loaded to CAP3TG Invert when the up counter value is loaded to CAP3 EQ7T6 Invert when up counter matches TREG7 EQ6T6 Invert when up counter matches TREG6 Figure 3 9 8 16 Bit Timer 5 F F Control TBFFCR 92 TOSHIBA CORPORATION 96 141 T45CR_ bit symbol i PGOT DB6EN DB4EN Read Write After reset 003AH HENCE shift PGOshif
171. width p to TREG5 when the interrupt INT4 occurs The TFF4 TOSHIBA CORPORATION 99 96 141 internal clock Count clock c c 4 pin input external trigger pulse Load the up counter value into Capture Register 1 CAP1 INT4 occurred Load the up counter value into Match with TREG5 INTTR5 occurred Capture Register 2 CAP2 Inversion Timer output pin TO4 Enables inversion caused by loading of the up counter value into CAP1 p Pulse width Disables inversion caused by loading of the up counter value into CAP2 Figure 3 9 15 One Shot Pulse Output without Delay Q Frequency Measurement The frequency of the external clock can be measured in this mode The clock is input through the TI4 pin and its frequency is measured by the 8 bit timers Timer O and Timer 1 and the 16 bit timer event counter Timer 4 The TI4 pin input should be selected for the input clock of Timer 4 The value of the up counter is loaded Count clock internal clock C1 Loading UC16 into CAP1 Loading UC16 into CAP2 into the capture register CAP1 at the rise edge of the timer flip flop TFF1 of 8 bit timers Timer O and Timer 1 and into 2 at its fall edge The frequency is calculated by the difference between the loaded values in CAP1 and CAP2 when the interrupt INTTO or INTT1 is generated by either 8 bit timer 1 TN
172. z 0 50usec 1 9kHz 252usec 39 0kHz 100psec 10 0kHz 0 40msec 2 4kHz 2 1 63 5 15 7kHz 254 3 9kHz 1 01usec 0 98kHz 50 8usec 19 7kHz 203 4 9kHz 0 81msec 1 2kHz 2 1 127usec 7 8kHz 510msec 1 9kHz 2 04usec 0 49kHz 102usec 9 80kHz 408 5 2 4kHz 1 63msec 0 61kHz 5 Table 3 7 4 shows the list of 8 bit timer modes Table 3 7 4 Timer Mode Setting Registers Register Name TMOD TFFCR Name of Function in T10M PWMM T1CLK TOCLK TFF1IS 2 Upper Timer Lower Timer Timer F F Invert Funcion Timer Mode PWMO Cycle Input Clock Input Clock Signal Select External clock 16 bit timer mode 01 914 116 00 01 10 11 Lower timer match External clock y 0 Lower timer output bitti 9T1 16 91256 914 16 8 bit timer x 2 channels 00 00 01 10 11 00 01 10 11 1 Upper timer output External clock 8 bit PPG x 1 channel 10 914 16 00 01 10 11 External clock P 28 914 16 E 8 bit PWM x 1 channel 11 01 10 11 00 01 10 11 8 bit timer x 1 channel 11 a 2 Output disabled Note don t care TOSHIBA CORPORATION 69 96 141 3 8 8 Bit PWM Timer The TMP96C141AF TMP96CMAOF TMP96PMAOF has two built in 8 bit PWM timers timers 2 and 3 They have two operating modes 8 bit PWM pulse width modulation

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