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1. 25 2 0 WRITE OPERATION E 28 29 SITATE MACHINE eto orent etia 31 3 SH 4 BUS STATE CONTROLLER SDRAM 34 4 SDRAM CONTROLLER DIFFERENCES BETWEEN 5 77505 7751 37 OVERVIEW E 37 4 2 BUS STATE CONTROLLER REGISTER 4 8 8 39 4 2 1 BUS CONTROL REGISTER 1 BOR 1 iasacivesespuduxkavicu 39 42 2 BUS CONIROEREGISIER 2 BORZ 39 423 WAIT CONTROL REGISTER 1 WCR1 39 424 WAIT CONTROL REGISTER 2 WCR2 39 4 2 5 WAIT CONTROL REGISTER 40 4 2 6 INDIVIDUAL MEMORY CONTROL REGISTER 4 4 0 40 4 2 1 PCMCIA CONTROL REGISTER 41 4 2 8 REFRESH TIMER CONTROL STA
2. 72 6 2 1 SETUP AND HOLD PARAMETERS 72 6 2 2 WAIT STATE PARAMETERS bisscncccsccdceccvcecctcececdccscccncdecdsancctsaacceiacseccucaesesanjaesacanccecasacdecvacacdewetereecceseeace 74 6 2 3 AUTO REFRESH INTERVAL PARAMETERS RR DR RR RR 75 6 2 4 C OCK OUALITY PARAMETERS 76 6 3 PRODUCING THE INITIALISATION 77 6 3 1 EXAMPLE SDRAM INITIALISATION CODE Ra Ra use aua 78 tote 0 79 8 Mmmm 79 SE F080 Rev 2 0 32 bit SH 4 Page 4 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 1 SDRAM Introduction 1 1 DRAM History For many years the Dynamic Random Access Memory DRAM has been the standard by which computer memory systems have been designed During this time DRAM architectures have found their way into virtually every market segment from low end personal computers to supercomputer systems costing millions of do
3. 5 2 7 2 TRAS 2 5 2 8 3 TcH TCL SE F080 Rev 2 0 Page 3 32 bit SH 4 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 5 3 1 GENERAL BUS LOADING OUTPUT BUFFER TIMING cccccccccncecccccacencecuacuncecuecuacenceceeneecuacuneeceanenueceaneas 64 5 3 2 GENERAL BUS LOADING INPUT SIGNAL TIMING ccccccccccsccncccccccncencecuacencecuenuacennuncecuecuacuaeeneaeaneneaneas 65 5 3 3 CLOCK CONNECTION GUIDELINES nnmnnn nnmnnn nnne 65 5 3 31 CLOCK TOPOLOGY a cuo aedes Fasc Clive Decus diva van aliu 65 5 3 3 2 1 0000 00000 66 5 3 3 3 CHARACTERISTIC IMPEDANCE 7 4 4 4 esse esses seres assesses ese 67 59 54 e 67 SPON PACK ENG Wi RU 68 6 WORKED EXAMPLE EDS2516ACTA 7A CONNECTED TO 2X256 MBIT 64 MBYTES SDRAM 100 MHZ BUS 69 PHYSICAL CONNECTION M CE E UR VER 69 6 2 TIMING CHECK 2 44
4. 6 1 29 PRECHA GE 7 1 9 LOCKED INTERFACE 7 1 4 9 Ted 9 1 6 INDIVIDUAL BYTE ENABLES ciu E Cus 11 1 7 TWO REFRESH MODES M 12 1 8 MARKING OF SDRAMS cssccsesccnsccnssnseescnssccsencanscnssecesecansonsencaeecansonsansaesonssonsease 12 2 THEORY OF SDRAM ERE SEE E 13 SE F080 Rev 2 0 32 bit SH 4 Page 1 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 21 OVERVIEW ee eee eee een ere ce ee ne 13 2 2 POWER ON SEQUENCE 0 c ccsnccesscneceneecnsccnseessensseneeonsecnseonsenssenseonssonseonsenssenseneness 14 2 3 COMMAND OPERATION 2 1 11 11 15 2 4 PRECHARGE OPERATIONS 2 222 20 2 5 MODE REGISTER 21 2 6 ACTV COMMAND SEQUENCE 2 1 25 2 7 READ OPERATION
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6. e 7 Access time from CLK Tac 5 4 gt tCYC EROR ET Data output hold time Input setup time Tsi 1 5 gt tCYC txxS This value is typically 1 5n for SH4 however 1ns is safe Input hold time to use CAS latency 2 The idle settings of other CS areas CLK data low NN _ gt A3W 1 tCYC must be adjusted to meet this An idle setting of 0 might be possible in WCR1 for area CLK data high EM luz gt CS3 Table 6 2 Setup and Hold parameters The SDRAM side of the table shows what value the SDRAM needs and the SH 4 section shows the value that the SH 4 can provide from the equation using values from the databook In all cases the values can be met which means that all data in out operations and command issuance SE F080 Rev 2 0 32 bit SH 4 Page 72 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 to the SDRAM can be performed correctly There are 2 notes which have been included which are as follows The CLK to low impedance time will depend on CAS latency settings and hold time of other devices in the system We will assume a worst case CAS latency of 2 which assuming a system worst case system hold of 2ns gives 12ns margin Following a SDRAM access the SDRAM will hold the data bus for maximum 5 4ns If other devices in the system can assert low impedance on the bus within 5 4ns an idle cycle will be required in WCRI for area 3 We will assume that ot
7. Rev 2 0 32 bit SH 4 Page 51 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 5 2 5 5 tLZ tLZ is the minimum delay to the data bus being driven during a read This parameter will always be met unless there are other devices in the system which are likely to drive the databus long beyond the end of their bus cycle It is generally recommended that when very slow devices are connected to the system idle cycles are configured or buffers inserted to avoid holding the databus for too long In most systems there will be a worst case data bus hold time following a read and as long as this is less than a bus cycle tLZ will always be met This is especially the case as the fastest the data bus will be driven by the SDRAM will occur during a RAS Down read which still has to wait for the CAS latency time Tcas 2 or3 before it drives the bus The actual equation to meet is SDRAM SH 4 ttz lt Tcas 1 tcyc system worst case databus hold time Tcas settings are made in register WCR2 9 2 9 6 tHZ tHZ is the maximum data bus hold time of the SDRAM following a read This is parameter 1s also important to consider when designing the system to avoid data bus collisions The worst case here 15 an SDRAM read followed by a write from the SH 4 Because there is no minimum delay time specified for output data during a write 1f tHZ 1s greater than zero then it 1s necessary to insert some idle cycles normally 1 Hence idle cy
8. Ld ME 0 1 Table 2 3 Sequential and interleave burst Bits 6 4 Bits 6 4 define the CAS latency on read cycles which can be 1 2 or 3 CAS latency one is mentioned because of historical reasons The latest SDRAMs do not support CAS latencies of 1 The remaining entries in the latency mode are undefined The CAS latency determines the number of clocks that elapse between the time the column is accessed and the time the data appears on the output pins A latency of 2 would mean that the column would be accessed and the data made available two clocks later Conversely a CAS latency of 3 means that data is not available until three clocks after the column 15 accessed Figure 2 4 shows how data output 15 affected by each CAS latency SE F080 Rev 2 0 32 bit SH 4 Page 23 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 CAS latency contral Pulse generator Read bus mainan Dout CL 1 Through Through Dout Through Dout Figure 2 4 Output effected on CAS Latency Bit 7 Keep this bit Low at the mode register set cycle If this pin is high the vender test mode is set Bits 13 8 Bits 13 8 define the write mode SDRAMs offer two types of write modes a burst read can either be followed by a single write or a burst write The amount of data transferred on a burst write is defined by mode register bits 2 0 If the processor generates a burst re
9. SE F080 Rev 2 0 32 bit SH 4 Page 71 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 6 2 Timing Check Through this section each of the timing parameters described earlier in this application note will be satisfied and the appropriate SDRAM control registers values will be derived The already discussed timing sheet in section 5 2 9 Timing Sheet SH7750S and 256 Mbit SDRAM contains already all timing information equation and register settings for this working example and should be used as quick interface timing guide for different SDRAMs Only the parameters which specify an equation to meet will be considered as all other parameters have already been met The first decision to be made has already happened the bus frequency will be 100 MHz and hence the cycle time will be 10ns For the purpose of brevity cycle time of 10ns will be used which also provides a small amount of extra margin for timing calculations The EDS2516ACTA 7A grade is capable of running at 133 MHz with CAS latency 2 or 3 A CAS latency of 2 is chosen which improves in general the overall performance This gives us our next initialisation value CAS latency 2 WCR2 A3W 0102 Note Each bus frequency has a different set of timing parameters Make sure that the correct figures from the databook are used during the timing check In this case the 100 MHz bus figures have been used 6 2 1 Setup and Hold parameters Item SDRAM o
10. Meet Timing Constraint is TRUE if the SH 4 meets the SDRAM timing SE F080 Rev 2 0 32 bit SH 4 Page 62 http www hitachi eu com 9 Y HS A q ce P S SUIT s WWHOS PHS 18843 woy apop Sys Ul 185 jou 8 e amp HEA suajawesed pue dnas 19 WHOS Jo uibua ysung snoaue 33siy PUA sep Ka ODO 810 y WHOS 10 ypa sng Jaye Aejap abieysaid 109 Jaysiiay OF shumas J38j 013u07 Sng FHS ajqissod DADA gt 9849 02 12842 aas OO 12842 01285 aas IO 49849 uopoes aes Dc gt DADO AMD 0 49849 aas gt 0 0000079 aes 42842 aas Ib 420 gt 9A9 amp Odi g 80 5 18845 998 ael gt 02 78 9 gt 87 aaLswal gt 09 sau gt VO seundnes yvw 2A21 zO ZCHHIAILLANIEW gt 50 lt 2 2560 TOES 581245 0195 eoi cc ON OE co N e c CN D9ESL eo 2 Ww
11. This can between two and three clock cycles 11 Then the data enters the output buffers where it remains until the data mask signals DOML DOMHBH are asserted 12 The data to be driven onto the output pins Figure 2 7 shows a flow chart of a READ operation The numbers shown correspond to those in the block diagram in figure 2 7 SE F080 Rev 2 0 32 bit SH 4 Page 27 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 5 set column address Latch column address and BS T Decode column address 8 Select data line 9 and latch read data Latch for latency control 11 Put data to output buffer Tack Figure 2 7 READ Operation Flow Chart 2 8 Write Operation As mentioned in the section 2 7 Read Operation all data cycles start with execution of the ACTV command which is generated by the state machine whenever CS and RAS along with a valid address are asserted simultaneously There are two types of read followed by write operations as defined by bits 13 8 of the mode register One is a burst read followed by a burst write where the burst length size 1s defined by bits 2 0 of the mode register The other is a burst read followed by a single write where only the burst read length size is defined in the mode register The subsequent write is always a single write effectively bypassing the burst length size of the mode register In this mode if a multiple transfe
12. 10 dnjas indui ybiy 110 8181 01412 moj 110 8121 01412 1xeu jsed pjou ejep 430 2 jo Buisu woy 558228 81543 4 GUT 3d OS HITACHI EUROPE LTD Version App 92 2 0 5 3 Other loading issues 5 3 1 General bus loading output buffer timing The standard test condition for all SH 4 AC characteristics 15 30 pF In fact it is possible to load most pins not including CKIO up to 80 pF The penalty you pay is slower rise times and hence delayed output signals This has an impact on the output signal timing The diagram below shows the timing deration vs output load for the SH 4 This factor must be applied to all pin timings where 30 pF load is exceeded In general the recommendation is to have only SDRAM and buffers directly connected to the SH 4 busses to avoid more than 30 pF load This will ensure that bus timings are as easy as possible to meet The table below shows example load capacitance values for the SH 4 SDRAM FLASH buffers and a LCD controller You can see that a typical system with 2pcs FLASH 2pcs SDRAM and an LCD controller could easily impose a load of over 40 pF on for example the address bus 4ns 3ns 2ns 11 Ons 30pF 55pF 80 Figure 5 5 Timing deration versus load capacitance SE F080 Rev 2 0 32 bit SH 4 Page 64 http www hitachi eu com HITACHI EUROPE
13. After the ACTV command is executed a basic read operation begins by the assertion of CAS and CS along with valid address The WE signal is inactive at this time A low in address bit ATO indicates a read command READ A high on address bit A10 indicates a read with auto precharge READA The read operation 1s responsible for outputting data onto the data bus after the ACTV command has been executed Figure 2 6 shows a block diagram of a read operation The numbers shown throughout the diagram correspond to the numbered sequence explained below Row address buffer 3 Row address decoder Word line driver Data line Column address buffer Column address counter olumn address decoder Gu t Sense amplifier and bus To column decoder of another bank C To column decoder of another bank To sense amplifier and bus of another bank Figure 2 6 Read Operation Block Diagram Read Command Sequence On a read cycle ACTV command is responsible for performing steps 1 through 4 as explained in section 2 6 The column address is latched three SE F080 Rev 2 0 32 bit SH 4 Page 26 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 clocks after the row address The assertion of CAS and CS along with valid address causes the state machine to transition to the READ state Steps 5 through 12 relate to the execution of the READ command and corresp
14. Cy lt lt Figure 1 1 DRAM Cell 1 2 2 Sense Amplifier After the charge on the BL bit line becomes a newer potential value the sense amplifier will detect the voltage difference between the bit line pairs and then force the voltages on the two line to reach the saturated Vcc and Ground potential It s a kind of splitting between the original dual 1 2 Vcc voltage lines At this moment the content inside the DRAM storage cell 1s detected and will be sent out to the output ports However the voltage potential in the cell capacitor is damaged changing from Vcc or Gnd to 1 2 0 1V potential 1 2 3 Bit Restoring After the data of cell is sensed and latched by the sense amplifier the BL bit line will be latched and hold as the original cell binary state if logical 1 Vcc bit line BL will charge cell capacitor and pull up its voltage to 18 logical 0 Gnd the cell capacitor C will be discharged and its potential would be pulled down to ground potential This operation is quite helpful while in the charge sharing of the cell capacitor the voltage potential has been changed The original digit of the cell capacitor becomes recovery before the end of the access cycle because of its latched data line 1 2 4 Write and Refresh The previous discussion is only focused on the reading action of the DRAM bit cell If we want to perform the writing on the bit cell it 1s quite easy to acc
15. Page 56 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 5 2 6 12 Tsrx Isrex Tsrx is the self refresh exit time and Isrgx is the self refresh exit to command input delay Tsrx is not really of interest because Isrex 15 much greater typically 7 vs cycle and hence meeting Isrex will satisfy both requirements So basically the important parameter to meet 15 the minimum number of cycles between exiting self refresh and the first command The SH 4 hardware manual provides a single diagram showing entry and exit from self refresh mode and it can be seen that a number of wait cycles as specified by MCR TRC are inserted Hence the equation to meet 15 SDRAM SH 4 Isrex lt 5 2 6 13 Tcke This is the time it takes the SDRAM to disable the clock following de assertion of CKE Since the SH 4 does not issue any commands following de assertion of CKE entry to self refresh mode this parameter is always met 5 2 6 14 Tmrd is the minimum delay between a MRS and ACTV command Following an SDRAM mode register set cycle the number of wait states before the next command can be issued is fixed The hardware user manual shows the same timing for a PRE PALL and PRE MRS The wait after the precharge select bank is always 3 cycles and the wait after the PALL MRS is always 4 cycles Hence the equation to satisfy Tmrd is SDRAM SH 4 Tmrd lt 4 The following parameters do not have PC100 symbols
16. SH 4 pins are the 2 SDRAMs and a buffer This will reduce the load on most pins to 2 x 5 pF 3 pF track capacitance Approx 15 pF total with 7cm of tracking This 15 particularly important for the CKIO connection and will ensure good rise and fall times when combined with a good clock layout In this case all of the signals from the SDRAM will connect directly to the SH 4 The most important item to check when checking the physical connection is the address multiplexing The table below shows how the address lines will be connected during the RAS ACTV command and CAS read write command phases of an access SE F080 Rev 2 0 32 bit SH 4 Page 69 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 Note that because the total memory is organised as a 32 bit word the SDRAM address connections are shifted by 2 bits 8 bits x 2 32 bits which means AO and 1 are left unconnected on the SH 4 If a 64 bit interface were selected then the address connections are shifted by a further one bit Table 6 1 below shows the required address multiplexing _ cycle CAS cycle Address Pins BANK select address 1 0 af a A2 IE A10 Address precharge setting Address Table 6 1 Address multiplex table The table was derived as follows The device has a 9 bit column address which are the lowest 9 bits of the address corresponds to 512 columns and these must connect proper
17. a READA command can be executed which auto precharges the bank for the next operation while the current read operation is still in progress thereby hiding some of the precharge latency If the read operation is a full page burst execution of the BST command causes the machine to terminate the burst and transition to the ROW ACTIVE state If the read cycle is allowed to complete and no follow on cycle is detected the machine returns to the ROW ACTIVE state The READ SUSPEND state is entered by a high to low transition on the CKE signal and is identical to CLOCK SUSPEND state During this state the retrieved data is continually output until the low to high transition on CKE causing the machine to return to the READ state The machine transitions to the WRITE state by execution of the WRIT command The WRITE state is very similar to the READ state The WRITE SUSPEND state performs the same function as CLOCK SUSPEND This is also true for the READA SUSPEND and WRITA SUSPEND States If no other cycles are pending once either a read or write cycle finishes the machine automatically returns to the ROW ACTIVE state However execution of either a PRE or PALL command from either the READ or WRITE state causes the machine to transition to the PRECHARGE state The difference between the READ and READA state 1s that once the cycle is completed in the READ or WRITE state an explicit PRE or PALL command must be executed in order for the machine to perform a pr
18. a simplified diagram of the main state machine Transitions between states are defined by the commands listed in the section 2 3 Command Operations DESL NOP SELFX BST PRE PALL SELF BST Write Xy suspend WRITA CKE4 Write suspend CKEf E 5 Conditional transition Automatic transition SAPNIOL A Figure 2 10 State Diagram SE F080 Rev 2 0 32 bit SH 4 Page 31 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 After the device is powered up and the mode register is programmed PALL command is executed which causes the machine to transition to the PRECHARGE state where a precharge operation is performed on all internal banks Once the precharge operation is completed the machine automatically transitions to the IDLE state Refresh power down and mode register operations can be performed while the machine is in the IDLE state Execution of the SELF command causes the machine to transition to the SELF REFRESH state It is necessary for CKE to transition from high to low in order to enter the SELF REFRESH state While in the SELF REFRESH state the memory array is in low power mode An internal refresh counter allows data integrity to be maintained Execution of the SELFX command which occurs when the CKE signal switches from low to high causes the machine to return to the IDLE state As stated in section 2 3 Command Operation low power mod
19. be considered and designed for A suitable textbook see reference section of this application note should be consulted for the details There are also several good modelling tools available which can help optimise the design of transmission lines This can help you produce an optimal CKIO layout first time round The basic idea of the CKIO connection is that the wavefront of the clock edge should be transmitted to each of the receive points with minimum distortion and skew To help ensure this following points should be followed as closely as possible 5 3 3 1 Clock topology Since the wavefront of a signal will travel along a transmission line here the PCB track with a finite velocity the time delay will depend on the length of the track Because there will usually be at least two receive points and hence the clock track always has point where the clock track splits and connects each of the receive points Always try to keep the direction changes to SE F080 Rev 2 0 32 bit SH 4 Page 65 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 less than 45 degrees It is also recommended that length of each of the branches 15 as small as possible The distance from the send point to each of the receive points should be equal Often this 15 not possible with a direct track so sometimes a Zig Zag is needed to increase the track length to match the other branches Note that this 1s also very important when
20. below Row address buffer D 3 Row address decoder MU Word line driver Data line Column address buffer Column address counter Column address decoder 4 memory call Sense amplifier and 1 bus Word line To column decoder of another bank MESA Output buffer TOTEM Input buffer af another bank sense amplifier and I bus of another bank Figure 2 8 Write Operation Block Diagram The simultaneous assertion of RAS and CS causes execution of the ACTV command Steps 1 4 in figure 2 8 represent execution of the ACTV command and are explained in the ACTV Command Sequence section Write Command Sequence The column address 15 latched three clocks after the row address The assertion of CAS and CS along with valid address causes the state machine to transition to the WRITE state Steps 5 11 relate to the execution of the WRIT command This numbered SE F080 Rev 2 0 32 bit SH 4 Page 29 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 sequence corresponds to that in figures 2 8 and 2 9 The physical location in the SDRAM where each step is performed is shown in figure 2 8 Figure 2 9 is a flow chart of the WRIT command 5 The column address is set based on the state of address inputs 8 0 Address bits A12 and A13 are used for the bank select Address bit A10 determines whether the command executed is a write WRIT or a write with auto precharge W
21. can be executed during normal operation The SELF command is restricted to refresh operations in low power clock suspend mode mode The REF command can only be entered when the state machine is in the idle state that 1s refresh operations cannot commence until all current cycles have completed Each SDRAM row require a refresh cycles every 64 ms Internally execution of the REF command performs the same function as a CAS before RAS refresh used in standard DRAMs Refresh addresses and bank selects are provided by an on chip refresh counter Therefore no external address 15 required as indicated in table 2 1 by an X don t care representing the address bus In addition each bank 1s precharged after a refresh operation Hence the PRE and PALL commands need not be executed after a refresh operation The REF command cannot be interrupted A refresh operation is always allowed to complete after which the state machine returns to the idle state CKE Current state Command n 1 n CS HAS CAS WE Address Active Glock suspend mode entry H L H x x x Any Clock suspend L L gt x x Clock suspend Clock suspend mode exit L H gt x x Idle Auto refresh command REF H H L L L H x Self refresh entry SELF H L L L L H Power down entry H L L H H H x H L H gt Self refresh Self refresh exit SEL FEX L H L H H H L H H x x Power down Power down exit L H L H H H L H H x x x Note H Livi x V or V Table 2 2 CKE Truth
22. can now define the RTSCR setting also The settings are as follows bits 15 8 Reserved 0 Compare Match Flag 0 Status flag Don t care Compare Match Interrupt Enable Set to 0 to disable it Clock Select Bits 0 0 1 Refresh count clock 1s CKIO 4 Refresh Count Overflow Status Flag Don t care Refresh Counter Overflow Interrupt Enable Set to 0 to disable it Refresh Count Overflow Limit Select Don t care 6 2 4 Clock quality parameters Ok This value is target characterized SDRAM unit SH4 unit tCKOH2 uses midpoint threshold uses midpoint threshold tCKOL2 Table 6 7 Clock quality parameters As mentioned in the clock connection guidelines section of this application note clock rise and fall time is highly dependent on the target system The rise time of an unloaded CKIO pin is much less than Ins however the test condition of 1 30 pF gives a guaranteed maximum rise time of 3ns Following the guidelines in the clock connection guidelines will ensure optimum rise and fall times however in cases of heavy CKIO loading external PLL buffering will be required and is which finally guarantees that the tT of the SDRAM 15 met In this example the CKIO pin is connected to 2 SDRAMs and a standard buffer This will reduce the load approx 15 pF total including tracking and will help produce a good CKIO risetime SE F080 Rev 2 0 32 bit SH 4 Page 76 http www hitachi eu com HITACHI EUROPE LTD Version
23. is the address which defines the write value to the SDMR SE F080 Rev 2 0 32 bit SH 4 Page 77 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 SDRAM is ready for use The code to perform this procedure using the previously calculated values is as follows 6 3 1 Example SDRAM initialisation code include iodetine Hh 7750S standard HEW IO define file define SDMR VAL 0x008C Burst length 8 32byte 32bit CAS latency 2 sequential wrap type define SDMR3 volatile char 0 940000 SDMR VAL Address calculation for MRS command define RTPWD1 0 500 Refresh controller access password for RTCSR RTCNT or RTCOR define RTPWD2 0 400 Refresh controller access password for RFCR er void sdram setup void BSC BCRI BIT DRAMTP 2 Area 3 SDRAM Area 2 SRAM a BSC WCR1 BIT A3IW 1 one idle cycles for area 3 BSC WCR2 BIT A3W 2 CAS latency for area 3 2 cycles BSC MCR BIT RASD 1 RAS Down mode enabled BSC MCR BIT MRSET 0 Enable output of PALL command BSC MCR BIT TRC 1 3 cycles RAS precharge after refr BSC MCR BIT TPC 1 2 cycles RAS precharge period e BSC MCR BIT RCD 1 2 cycles RAS CAS delay ui BSC MCR BIT TRWL 1 2 cycles write precharge delay T BSC MCR BIT TRAS 0 4 TRC interval at end of refresh BSC BIT 8223 32bit wide SDRAM bus T BSC MCR BIT AMXEXT 1 AMX setting for 2x256 Mbit SDRAM ua BSC BIT AMX 6 column 13
24. life support systems Buyers of Hitachi s products are requested to notify the relevant sales office when planning to use the products in MEDICAL APPLICATIONS Copyright Hitachi Ltd 2002 All rights reserved SE F080 Rev 2 0 32 bit SH 4 Page 80 http www hitachi eu com
25. most cases this can be set to 0 Bits 10 8 Controls the number of idle cycles inserted following an access to CS area 2 The hold time of SDRAM by definition is very short less than 1 CKIO cycle so in most cases it can be set to 0 4 2 4 Wait Control Register 2 WCR2 Bits 15 13 Sets the CAS latency of CS area 3 when SDRAM is enabled CAS latency 1s effectively the number of clock cycles after a read command that the first data can be strobed in SE F080 Rev 2 0 32 bit SH 4 Page 39 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 by the SH 4 This can be set from 1 5 cycles or 2 3 cycles when RAS Down mode is enabled Other settings are not guaranteed Note that the CAS latency setting must be the same value as written to the SDMR internal SDRAM register to ensure correct sampling of read data Bits 11 9 Sets the CAS latency of the CS area 2 when SDRAM is enabled Note that when areas 2 amp 3 are used as SDRAM RAS Down mode 15 not supported 4 2 5 Wait Control Register 3 WCR3 WCR3 has no effect upon the operation of SDRAM 4 2 6 Individual Memory Control Register MCR MCR is a 32 bit read write register that can be used to specify RAS and CAS timing address multiplexing and refresh control for SDRAM in Area 2 and 3 Bit 29 28 27 26 20 24 23 22 21 20 19 18 reas MET Tac 1 D 1 Robo Bit 15 14 13
26. none of these parameters need to be met 5 2 7 Auto refresh interval timing When the SDRAM is in normal operation auto refreshes are issued by the BSC to keep the memory cells refreshed Each refresh command will refresh one row at a time The refresh works by reading the data into the sense amps and then without outputting them moving them back into the memory cells An internal counter inside the SDRAM controls the actual row being refreshed The particular row number being refreshed 1s not of interest as long as every row 1s refreshed within the refresh period When RAS Down mode is used there is an additional restraint on the refresh period as described below 5 2 7 1 15 the longest period any row can go without refreshing to guarantee data integrity Because each refresh cycle will only refresh one row the Refresh Time Constant Register RTCOR and the Refresh Timer Control Status Register RTSCR must be configured to give a refresh period Tras as follows SDRAM SH 4 trer gt tarer 2 no rows see below if RAS Down mode is used 5 2 7 2 Tras 2 When the high speed RAS Down mode is enabled instead of the SDRAM state machine normally being in the idle state it remains in the row active state where possible This significantly speeds up accesses to the same row as an ACTV command 1 not necessary The side effect however 15 that 1t is possible that a ROW can be active for a very long time As
27. of the SH 4 buffer provides this functionality already Further impedance added to the clock line would degrade the wavefront of the clock edge too much Receive point termination should also not be used as the SDRAMs include built in guaranteed voltage clamps Further parallel termination resistive or R C filter would impose too much additional load on the CKIO pin especially in the case of pure resistive and would also impede the voltage level of the wavefront as it reaches the receive point Clamp termination at the SDRAM end should not be necessary as SDRAMs SE F080 Rev 2 0 32 bit SH 4 Page 67 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 have built in clamp diodes however it 15 recommend that any other loads such as buffers are checked for tolerance to over voltage and where necessary clamp protected As the reflections from each of the receive points will be combined at the T point a single wavefront is transmitted back to the CKIO pin This wavefront will then absorbed by the impedance of the CKIO output buffer preventing further reflections Clock send point SH4 Clock load SDRAM Zo 30ohms Figure 5 8 Clock wiring with no termination required 9 3 3 5 Track length The overall track length of the CKIO net should always be kept as short as possible The delay times are important but in addition PCB tracks also have a capacitance value which is generally proportional to length This can
28. so as reference the Elpida SDRAM notation is used 5 2 6 15 Igp is the last data out to precharge minimum delay This defines the minimum delay between the last read data being output by the SDRAM and the next PRE command Note that this 1s generally a negative parameter which means the precharge can be issued before the last data has been clocked out The SH 4 BSC will always issue the precharge after the last data has been sampled so this parameter will be met 5 2 6 16 lapr Iapr defines the minimum delay between the last read data being output by the SDRAM and the next ACTV command The next ACTV command following sampled data will happen following a precharge in a RAS Down mode read or following the RAS precharge period MCR TPC in the case of auto precharge read The worst case when RAS Down 15 disabled MCR RASD 0 and hence the following equation needs to be satisfied SDRAM SH 4 Iarr lt MCR TPC SE F080 Rev 2 0 32 bit SH 4 Page 57 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 5 2 6 17 lcpp Icpp defines the delay between CS being negated and SDRAM command reception being disabled This will always be 0 as when CS is high this constitutes a DESL or deselect Hence this parameter will always be met 5 2 6 18 Ipsw These parameters define the timing of PWRDN power down and BST burst stop commands Since none of these commands are issued by the SH 4 BSC
29. sometimes be as much as 1 pF per 30mm This should be considered when calculating the total load on the CKIO pin It is also very important that any reflected signals arrive back at the CKIO pin before the end of the rise fall time of the clock This is so that the internal PLL feedback signal is not falsely clocked The result is the total distance from the CKIO send point to each of the receive points these should all be equal distance away must be less than 50mm and as low as 25mm if possible This is anyhow a good recommendation as 1s it will keep the delays clock skew down to a few hundreds of picoseconds SE F080 Rev 2 0 32 bit SH 4 Page 68 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 6 Worked Example EDS2516ACTA 7A connected to 2x256 Mbit 64 Mbytes SDRAM 100 MHz bus frequency In this example 2 x 16 bit wide SDRAMs are connected to the SH7750S with a bus clock frequency of 100 MHz The SDRAMs used are Elpida EDS2516ACTA 7A It is a 133 MHz device with a CAS latency 2 3 and has a capacity of 256 Mbit SDRAM organised as 4194304 x 16 bit x 4 bank This worked example is split into 3 sections Physical connection Timing Check and software initialisation Only the SDRAM area 3 will be initialised here and all other areas settings have been left as default 6 1 Physical connection The system bus in this example will be partitioned such that the only devices connected directly to the
30. the machine automatically returns to the IDLE state Precharge and burst stop operations cannot be executed from the IDLE state hence execution of these commands while in the IDLE state has no effect on the state machine Read and write cycles each begin with execution of the ACTV command which causes the machine to transition to the ROW ACTIVE state While in the ROW ACTIVE state the row address is latched and decoded The correct row is then initialised While in the ROW ACTIVE state another ACTV command can be executed as long as the access is to another bank Accesses to the same bank are unnecessary and illegal If the CKE signal switches from high to low at any time during the ROW ACTIVE state the machine transitions to the CLOCK SUSPEND state While in the CLOCK SUSPEND state the machine ignores all inputs The SE F080 Rev 2 0 32 bit SH 4 Page 32 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 current operation is not lost but rather is held active and commences following a low to high transition on CKE This transition causes the machine to return to the ROW ACTIVE state Once the correct row has been initialised the assertion of CAS causes the machine to execute one of the following four commands READ READA WRIT WRITA Execution of the READ command causes the machine to transition to the READ state While in the READ state many transitions can occur If the following cycle is another read to the same bank
31. the operation The table below provides a functional summary of the groups of signals present on a typical SDRAM The Pin arrangement section of the SH 4 HW manual also provides a useful guide to which pins are used for the SDRAM and other memory type interface SDRAM SH4 Purpose Notes PT Signal CKIO Provides clock to the SDRAM state machine rising Critical signal Clock edge triggered routing important CKE Clock enable freezes operation of SDRAM Heed CUNO down PLL conn P a Chip Select Multiplexed address input also forms part of settings command word during ACTV discussed below Bank select effectively an upper address omma bank specification Row address strobe latches row address CAS uw Column address strobe latches column address also issues read write RD WR Selects either read or write from CAS during cycle eme res tom CAS dum eade DQ 0 N ETE Datainput output DOM 0 N Data qualifier masks Specifies which bytes should be written Ig iiie _ write VDD Q foe nn Powersupply VSS Q Power supply ground E Table 5 1 Interface SH 4 and SDRAM Most of the signals above are analogous to a SRAM DQ or data lines are the data input output port DOM are similar to the HWR LWR or HBS LBS data masks and the WE 1 a read write strobe CS 1s a chip select and the CLK CKE lines are clock control for the SDRAM as it 1s essentia
32. time for CKE when the clock is suspended These setup times have got different naming in the SDRAM data sheet however the same value Hence it will be references as Tsi The parameter will depend on the CKIO cycle time and maximum output delay time from the SH 4 BSC The equations that must be satisfied are as follows SDRAM SH 4 tADRESS SETUP SDRAM lt tcyc twep1 tcHIP SELECT SETUP SDRAM lt tcyc trasp etc Note Since in the SH 4 datasheet all output delays are identical and in the SDRAM datasheet all input setup times are identical only one of these equations needs to be calculated to be sure of meeting all SDRAM setup parameters 5 2 5 4 Thi tXXH are the input hold times of the SDRAM control signals such as CS ADDR RAS CAS BS amp DQM the input hold time for write data and the input setup time for CKE when the clock is suspended This parameter will depend on the CKIO cycle time and minimum output hold time from the SH 4 BSC The equations that must be satisfied are as follows SE F080 Rev 2 0 32 bit SH 4 Page 50 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 SDRAM SH 4 HOLD SDRAM lt twpp SELECT HOLD SDRAM lt tcsp etc Note Since in the SH 4 datasheet all output delays are identical and in the SDRAM datasheet all input hold times are identical only one of these equations needs to be calculated to be sure of meeting all SDRAM hold time parameters SE F080
33. to wrap around to its starting address The same data 15 again output until the BST command is executed READ The read command specifies the column address corresponding to the row address executed by the previous ACTV command The READ command 15 optimised for single read accesses When the READ command 1 executed data is available a set number of clocks later as defined by the CAS latency mode in the mode register Latencies of 2 and 3 cycles are supported Another READ or READA command can be executed while the current READ command 15 in progress causing the state machine to transition so that a new row address can be processed However execution of either the WRIT or WRITA commands during execution of a READ command causes termination of the read operation and allows the write operation to begin In addition execution of either the PRE or PALL commands during execution of a READ command also causes termination of the read operation and allows a precharge operation to begin After completion of a READ command the output buffers are high impedance If the CKE signal is driven low during execution of the READ command the data 1s held and continues to be output until CKE is driven high READA The READA command is executed when it 1s necessary to read the memory array and at the same time perform a precharge operation This command only works when the burst length size 1s programmed to 2 4 or 8 Single transfer read cycles and full page b
34. 12 11 10 9 8 7 6 5 4 3 2 0 Name Table 4 3 WCR3 Register Bit 31 RASD Controls RAS Down mode operation A normal SDRAM access consists of a row address followed by a column address which are multiplexed on the same address bus in turn These two cycles specify a complete address and are necessary for most random accesses In the case of an access to the same row as before and internal comparator can force the BSC to inhibit the ROW address thereby speeding up the access by tRCD This effectively means the SDRAM state machine is normally in the row active state rather than the idle state This mode can only be used when area 3 1s the only SDRAM area RAS Down mode is recommended for maximum performance Also when RASD bit is set to 1 in MCR pipelined access is performed between an access by the CPU and an access by the DMAC or in the case of consecutive accesses by the DMAC to provide faster access to synchronous DRAM As synchronous DRAM is internally divided into four banks after a READ or WRIT command 15 issued for one bank it 1s possible to issue a PRE ACTV or other command during the CAS latency cycle or data latch cycle or during the data write cycle and so shorten the access cycle Bit 30 MRS Mode Register Set Two commands can be issued to the SDRAMs manually by writing to a special area H FF90XXXX The command which 1 sent upon the write depends on the setting of the MRS bit If 1t is set to 0 then an
35. AS Down mode is off this parameter can never be violated because a precharge will automatically be issued after each read write and hence the row will be deselected When RAS Down mode is on it 15 possible that the same row may be active for a SE F080 Rev 2 0 32 bit SH 4 Page 54 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 long time e g Idle loop software and hence you must take care that a command 15 issued within this period The way this is normally done is by adjusting the refresh period to Tras See the Refresh settings section for details 5 2 6 5 Tdpl This is the last data write to precharge This specifies the minimum delay from when the last data being written is latched to the next precharge command which will happen when RAS Down mode in enabled The reason for this recovery time is that following latching of the write data it takes the SDRAM some time before the data is finally written to the internal DRAM cell This setting is controlled by the three MCR TRWL bits The equation to be satisfied are as follows SDRAM SH 4 lt tcyc MCR TRWL 9 2 6 6 Tdal This is the last data write recovery time until next ACTV This specifies the minimum delay from when the last data being written is latched to the next ACTV command The worst case condition for this is after a write RAS Down off or RAS Down on with different row access following Since between the last data
36. App 92 2 0 6 3 Producing the initialisation code The above sections have proved that the electrical timing of the SDRAM can be met and consequently derived the values that need to be initialised into the BSC The next step is to produce the initialisation code for the SDRAM based on these values The initialisation flow used in this application note 1s the one recommended in the HW manual Normally the SDRAM is the only RAM available in the system so until the SDRAM 1s initialised stack cannot be used Since C compilers have the possibility to use the stack care must be taken if the code is written in C Function calls are using the stack and therefore not allowed expect the RAM of the operand cache 1s available during booting The alternative and more often seen method 1s to write your own code in assembler For this example C code is used using the SH 7750S IO definition file that 1s generated by Hitachi Embedded Workshop HEW This file describes the peripheral IO registers as bit fields and hence produces very readable code It also means that only the required bits are modified with others being left to their present value Hence each modified bit field will generate a read modify write mask operation Write only registers or password protected cannot be used manipulated in this way hence the SDMR and refresh registers are initialised using a full register load The initialisation sequence is as follows Initialise BCRI to define memor
37. CKIO using PLL 5 3 3 3 Characteristic impedance The approximate output impedance of the CKIO pin is close to 30ohms during the rising edge approx 10 ohms for falling edge The rising edge is most important because it 1s this that the SDRAM state machine and SH 4 PLL are synchronous to To optimise the propagation of the clock edge wavefront travelling out towards the clock loads the characteristic impedance of the clock line should be as close to 30ohms as possible also Any break in the characteristic impedance will cause reflections For this reason vias should be avoided where possible Because there will be a T point where the clock track splits the wavefront at this point 1s confronted with parallel loads To maintain as closely as possible the 30ohm transmission line impedance the impedance of the clock branches when paralleled together should equal 30 ohms Ie Each branch should have a characteristic of 90o0hms if possible where 3 loads exist This is not a rule that must be followed precisely however better signal integrity will be achieved 1f this implemented Your PCB manufacturer will be able advise on the capabilities of your PCB process 5 3 3 4 Termination Various types of termination are available for transmission lines In the case of the SH 4 driving the CKIO line it is recommended that no termination should be used The reason for this is that series termination at the send point is not needed as the internal impedance
38. Device SDRAM Controllers It should be noted that the need to issue two reads or two writes to complete a 32 byte access does not impose any bus overhead compared with a burst read write issued from a single command as with the 7750S The reason for this is that the SDRAM accesses are pipelined so that the total number of bus cycles does not change The below diagram shows this Note that in particular the two READ commands signified by CAS low SE F080 Rev 2 0 32 bit SH 4 Page 37 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 TR TRW Tel Te2 Te3Tc4 Tdl Td Tas Td Td Td8 CKI yw ie ds Addre pes Eur 715 oo T BENE 12 m EB LI di RAS T Ul 7750 UEan aman as ana Data x32 Jad d dw 2 3 Figure 4 1 77505 amp 7751 SDRAM 32byte Burst Read from 32 bit Wide Memory SH 4 Bus State Controller Registers relating to SDRAM When SDRAM 15 used with the SH 4 several BSC registers must be configured before the normal SDRAM operations can be performed Below there is a summary table showing which registers need to be configured in order to access SDRAM Details of each register can be found in the relevant SH 4 Hardware user manual SE F080 Rev 2 0 32 bit SH 4 Page 38 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 BSC Regist
39. HITACHI EUROPE LTD Version App 92 2 0 APPLICATION NOTE SH 4 Interface to SDRAM Introduction This application note has been written to aid designers connecting Synchronous Dynamic Random Access Memory SDRAM to the Bus State Controller BSC of SH7750S and SH7751 The application note starts with the principles of SDRAMs This gives us the foundation to explain the details of the slight different BSC of these products After a presentation of the physical connections and the timings an example closes the discussion For designers who wish to set up the BSC as quickly as possible it is recommended that the section Worked Example EDS2516ACTA 7A connected to 2x256 Mbit 64 Mbytes SDRAM 100 MHz bus frequency is used as the starting point More detailed information can be gathered from the other sections when necessary Contents 1 SDRAM INTRODUCTION S FER cane 5 JRANCBISIORY 5 12 PRAM CEL saccade E 5 12 THE BASIO CELE cT 5 1 2 2 6 1 2 9 RESTORING aonaran SERE ROG x RATEN CE RU GR RD ER RE RR RD E RE RR ow 6 1 2 4 WRITE AND nhau aeu RR IRR SR
40. LTD Version App 92 2 0 Input men Bandwidth Capacitance Capacitance requirement test condition q SH4 7750 10pF Max 30 800F SDRAM 1 Device FLASH 1pc LCD controller Tyo 50 ROOM 3pF 10cm Table 5 4 Example load drive capacitances of different devices 5 3 2 General bus loading input signal timing In the case of the SH 4 some of the setup times specified in the AC characteristics are 1 5ns longer for the QFP package than the BGA package The reason for this is extra capacitance of the leadframe of the QFP package Care should be taken that the correct figures are used from the data book As a general note most sampled signals such as and BREQ are single latched What this means is that if the setup and hold times are violated the behaviour of the bus state controller can be a predictable Therefore the designer must develop hardware that provides a CKIO synchronous input to these pins This will ensure that setup and hold times are always met and hence metastability will be avoided 5 3 3 Clock connection guidelines The load on the CKIO pin should be as low as possible to improve the CKIO rise fall times As mentioned in the timing analysis clock quality part of this application not the CKIO signal routing 1 perhaps the most critical of any of the SH 4 connections with regard to timing Since the CKIO frequency is very high transmission line effects must
41. O out2 Burst length 4 out 1 out 3 Burst Length LIA LI LI LI LUI LI LI LILI LI LI LI LI Lo Roo Active Read Command 7 X X X X LC Row C ol umn Address XX _ L BL 1 out Se BL 2 out O out 1 Dout BL 4 out O out 2 out 1 out 8 out out Z out 4 out 6 out 1 out 3 out 5 out BL full page out out4 out6 outs out 256 out 1 ees oo cs out 1 out 3 out 5 out 7 out O BL Burst lenath CAS latency 2 Figure 1 3 SDRAM CAS Latency and Burst Length 1 6 Individual Byte Enables Typical SDRAMs offered as 8 and 16 bit device that supports byte selected writing In the case of 8 bit devices DQM 1 used to support byte write operations This signal performs the byte mask function The signal controls one byte of data DQM is active when D7 DO are written In the case of 16 bit devices DQMU and DQML are used to support byte write operations These signals perform the byte mask function Each signal controls one byte of data DQML controls when D7 DO are written and determines when D15 D8 are written Without these SE F080 Rev 2 0 32 bit SH 4 Page 11 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 signals a typical byte write would require a word 16 bit read then a byte mask followed by a word write 1 7 Two Refresh Modes SDRAMs support two types of refresh mechanisms auto refresh a
42. RITA On write cycles SDRAMs can accept a new column address on every clock as long as the row 15 active Simultaneous with the column address being driven the SDRAM accepts the write data which enters the on chip input buffer 6 The column address is latched and routed through the burst counter to the column decoder If the operation is a read followed by write whether or not the burst counter is activated depends on the state of the burst length size and opcode entries in the mode register The write data 1s latched at this time 7 The address enters the column address decoder The decoder determines which column is activated 8 The correct data line 15 activated based on the column address decode 9 Step 9 occurs at the same time as step 5 The SDRAM accepts the write data which enters the on chip input buffer 10 Step 10 occurs at the same time as step 6 The write data 1s latched internally at this time 11 The write data is written to the memory cell Figure 2 9 shows a flow chart of a WRITE operation The numbers shown correspond to those in the block diagram in figure 2 8 Set column address Latch column address and BS 7 Decode column address B Open bus and data line 1 Write data to a memory cell Figure 2 9 Write Operation Flow Chart SE F080 Rev 2 0 32 bit SH 4 Page 30 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 2 9 State Machine Figure 2 10 is
43. TUS REGISTER eere nnne 41 4 2 9 REFRESH COUNT REGISTER RFCR 4 0 4 2444 80688 42 4 2 10 REFRESH TIMER COUNTER REGISTER 42 4 2 11 REFRESH TIME CONSTANT REGISTER 42 4 2 12 SYNCHRONOUS DRAM REGISTER 2 amp 3 SDMR2 3 42 5 CONNECTING THE SH 4 DIRECTLY TO 44 mi PHYSICALCONNEGTION 44 5 1 1 ADDRESS MUETIPEEXING Ga ed aO Bid RUE 45 SE F080 Rev 2 0 32 bit SH 4 Page 2 http www hitachi eu com Version App 92 2 0 HITACHI EUROPE LTD 5 2 1 5 2 2 5 2 3 5 2 4 5 2 5 5 2 5 1 5 2 5 2 5 2 5 3 5 2 5 4 5 2 5 5 5 2 5 6 5 2 6 5 2 6 1 5 2 6 2 5 2 6 3 5 2 6 4 5 2 6 5 5 2 6 6 5 2 6 7 5 2 6 8 5 2 6 9 5 2 6 10 5 2 6 11 5 2 6 12 5 2 6 13 5 2 6 14 5 2 6 15 5 2 6 16 5 2 6 17 5 2 6 18 5 2 7 AUTO REFRESH INTERVAL TIMING 5 2 7 1 5 2 8 CLOCK QUALITY PARAMETERS 5 2 8 1 0 2 8 2 5 2 9 TIMING SHEET SH7750S AND 256 SDRAM 5 3 OTHER LOADING ISSUES lcpp98 lgsH amp lgsw TREF
44. Table 128 Mbit SDRAM SELF Like the REF command the SELF command can only be executed when the state machine is in the idle state Negation of the CKE signal indicates that the clock has been suspended This low power mode can be used when the SDRAM will be idle for long periods of SE F080 Rev 2 0 32 bit SH 4 Page 19 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 time and is ideal for battery powered devices The SELF command is necessary since during low power mode the clock is suspended hence the REF command cannot be issued Low power mode greatly reduces the amount of current usage During normal operation a typical SDRAM can use 120 mA However during low power mode where the device refreshes itself only 4 mA of current are consumed The SELF command continues execution as long as the CKE signal is low SELFX Transition of the CKE signal from low to high causes execution of the SELFX command terminating the self refresh operation As shown in table 2 2 there are two conditions under which the SELFX command 1s executed If CKE switches from low to high and the CS signal is also high the SELFX command is executed regardless of the state of the remaining pins and the state machine returns to the idle state If CS is low at the time of the CKE transition the other control signals must be sampled in the states shown in order for the SELFX command to execute All other commands are illegal at this time The transi
45. Tras defines the maximum time a row can be active without a precharge provision must be made that a command must be issued to the SDRAM within this time The easiest and safest way of doing this 1s to set the refresh period to less than Tras Hence when RAS Down mode is used the following equation must also be satisfied SDRAM SH 4 Tras gt tAREF SE F080 Rev 2 0 32 bit SH 4 Page 58 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 5 2 8 Clock Quality Parameters The SDRAMs are normally clocked by the SH 4 CKIO output pin There are several parameters defined in the SDRAM datasheet which need to be met by the this clock The specification of the clock requirements for SDRAMs is very tough to meet This comes from the PC market place where usually dedicated devices are used to provide extremely high quality clock signals The SH 4 has a built in PLL phase locked loop which is used to match the phase of the buffered CKIO with the internal clock which in some cases is able to drive the CLK input on the SDRAM directly It is important to study the clock loading carefully however as applying maximum load to the CKIO pin will mean that some of the SDRAM clock parameters will be difficult to meet particularly when the CKIO frequency is very high In these cases clock buffering may be necessary and to reduce the skew to a minimum a PLL buffer must be used Several reference designs are available from Hitachi which give ex
46. a precharge operation to begin Unlike the READ command where a subsequent READ command 15 allowed as long as it 1s to the opposite bank execution of a subsequent WRIT or WRITA command while the write operation is in progress causes the operation to be terminated and a new write operation to begin SE F080 Rev 2 0 32 bit SH 4 Page 17 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 WRITA The WRITA command is executed when it is necessary to write the memory array and at the same time perform a precharge operation This command only works when the burst length size is programmed to 2 4 or 8 Single transfer write cycles and full page bursts cannot be executed using the WRITA command Execution of the WRITA command allows the active bank to be precharged prior to completion of the write operation Overlapping the actual access with the precharge operation helps hide the latency required while the data flows from the input pins through the sense amplifiers to the array and increases the overall throughput for that bank Unlike the WRIT command which can be easily terminated the WRITA command cannot be interrupted Execution of the READ READA WRIT WRITA PRE or PALL commands while the write with auto precharge operation 1s in progress are illegal If the CKE signal is driven low during execution of the WRITA command the data 1s held in the input latches and all input pins are ignored until 15 driven high ACTV T
47. ad followed by a single write cycle and the mode register is programmed in burst write mode A13 A8 0 the controller must reprogram the mode register before allowing the write cycle to complete This is because the burst write is represented by only one assertion of the WEZ signal for one clock as opposed to four separate WE assertions as would occur in a standard DRAM A burst read followed by a single write can be useful in graphics applications For example a burst read can be used to refresh the video screen and single writes can be used to update specific portions of the screen This mode can also be used to support a CPU with a write through primary cache where each write to the primary cache is also driven onto the external bus SE F080 Rev 2 0 32 bit SH 4 Page 24 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 2 6 ACTV Command Sequence The simultaneous assertion of RAS and CS causes execution of the ACTV command The ACTV command is executed on both read and write operations and performs the following functions 1 Sets the row address as determined by the state of the address inputs 2 Latches the row address and bank select signals The appropriate bank select is determined by the state of the highest order address bit 3 Decodes the row address The row address is first multiplexed with the refresh address counter after which it enters the row address decoder of the enabled bank In a 128 Mb
48. all bank precharge occurs If it 1s set to 1 then mode register set command is sent along with set value which is encoded into the lower address bits SE F080 Rev 2 0 32 bit SH 4 Page 40 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 Bit 29 27 TRC2 TRC0 These bits set the number of wait cycles following a refresh cycle auto or self to allow for the refresh to complete Settings are 0 3 6 9 12 etc Bits 21 19 TPC2 TPC0 RAS Precharge Period These bits specify the minimum number of cycles until the next bank active command is output after precharging Valid settings are normally 1 8 or 2 3 when RAS Down mode is enabled See bit 31 Bits 17 16 RCD1 RCD0 RAS CAS delay This sets the number of cycles after ROW address has been issued that a column address can be issued Ie Read Write Settings of 2 4 cycles are valid or 2 3 cycles in the case of RAS Down mode bit 31 By adding the RAS CAS delay tRCD to CAS latency the random access read time can be calculated Bits 15 13 TRWL2 TRWLO These bits set the SDRAM write to precharge delay time Basically the write operation has to complete internally before a precharge can be issued This setting forces the BSC to wait following a write command Valid settings are 1 5 cycles or 1 2 cycles in RAS Down mode see bit 31 Bits 12 10 TRAS2 TRASO Auto refresh delay These bits define how long the BSC will wai
49. ample usage of PLL buffering in large systems To aid the understanding of the clock parameters the diagram below has been included Because different voltage threshold levels are used for different tests in many cases more margin is often available when performing the timing calculations tcKOL2 tckor tr Figure 5 3 CKIO output and CKE input timing 9 2 8 1 tT tr is the required input clock rise fall time Actually in the case of SDRAM the most important parameter is the clock rise time as the state machine and hence sampling is synchronous to this edge Most SDRAMs are tested using tr Ins so most SDRAM parameters assume the condition tr Ins also In the case where the rise time is longer than Ins sometimes deration factors sometimes called transient time compensation are added The factors added 1f at all depend on the manufacturer This makes it more difficult to meet some of the SDRAM parameters particularly the ones classified under the Setup and hold time parameters SE F080 Rev 2 0 32 bit SH 4 Page 59 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 For example in some cases tr 2 0 5 ns or tr tf 2 1 ns should be added to the parameter For example if the rise fall time is 4ns the above equations give 3ns and 1 5ns additional time to some parameters In this case many parameters can not be met The test condition for the SH 4 CKIO output buffer is 30 pF load whic
50. an only be executed during a full page burst cycle Execution of this command is illegal during execution of any other burst operation Execution of the BST command causes the output buffers to become high impedance The full page burst 15 useful for high speed graphics applications such as reading video from memory and mapping it to the screen If the system is designed so that not all of the full page burst transfers are required to complete the screen update operation the burst can be terminated as necessary by execution of the BST command A full page burst that has been terminated cannot be restarted where it left off Rather the burst counter is reset Therefore if the full page burst mode 15 used for a normal CPU operation such as refilling a cache and the BST command is executed during the burst there is no way to restart the burst Either the entire burst cycle can be re executed or smaller bursts to those locations not yet accessed can be executed to retrieve the entire full page burst data For this option the mode register must be reprogrammed with a burst length value other than full page before subsequent SE F080 Rev 2 0 32 bit SH 4 Page 16 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 burst cycles can be executed The BST command is required to terminate the full page burst even if the burst 15 allowed to complete Failure to execute the BST command at the end of a completed burst causes the burst counter
51. and attempt to meet them by equating them to the SH 4 BSC parameters Below 15 a description of each of the parameters specified by a typical SDRAM As there are many timing diagrams required to illustrate these parameters it is recommended that a copy of your SDRAM datasheet is consulted whilst this section of the application note 15 read At the end of section 5 2 there is a timing exel sheet which summarises all related timings equations and results It gives you a easy to handle timing sheet for a quick and comprehensive timing check The type of timing analysis to be made depends on the parameter being checked It can be useful to differentiate between the four types of timing parameters specified by the SDRAM which must be met by the SH 4 BSC These are as follows SE F080 Rev 2 0 32 bit SH 4 Page 47 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 5 2 1 Setup and Hold times Because the SDRAM 1s a state machine state transition commands must be provided by the SH 4 BSC Each state transition occurs on the rising edge of CKIO and hence the command word 1s sampled on the positive edge of CKIO Any signal that is sampled has an associated setup and hold time so these parameters must be met In addition any read or write will involve sampling of data either by the SH 4 BSC or the SDRAM This also happens on the positive edge 5 2 2 Wait states The wait state control within the SH 4 BSC essentially sets the s
52. ans it is the minimum time following a precharge that data should be written Since following a precharge the minimum delay before data can be written by the SH 4 15 Tpc min 1 RAS CAS delay min 2 3 cycles and Troh is minimum 3 this value is always met 9 2 6 9 Tccd Tccd is the minimum delay between column to column commands Effectively this specifies the minimum delay between a read write and the next read write As this parameter is normally specified at 1 cycle and the fastest the SH 4 can issue to column commands is the case of the 7751 burst access Here a read write will be followed by another read write 4 cycles later Hence meeting Tccd always happens 5 2 6 10 Tdwd Tdqm This is the write command to data in latency and the DQM to data in latency Since a write consists of both the write command and DQM to specify which bytes within the word must be written these parameters can be grouped together So together these define the delay between a write operation and write data being latched The SH 4 always assumes this delay to be 0 Ie Data is latched upon the write command This is normal for all normal SDRAMs so this parameter is met 5 2 6 11 Tdgz Tccz is the minimum delay between valid DQM and reading valid data Since during a read the SH 4 will assert all DQMs when the read command 1s issued this parameter will always be met as it is less than or equal to the CAS latency SE F080 Rev 2 0 32 bit SH 4
53. being written and the next ACTV command being issued a precharge is required this value should be met by the sum of two values In addition to the MCR TRWL bits as above the settings of the MCR TPC bits must be considered The equation to be satisfied are as follows SDRAM SH 4 Tdal lt tcyc MCR TRWL MCR TPC 5 2 6 7 Tre Trc is the minimum row cycle time This specifies both the minimum time between a REF ACTV command and the next REF ACTV command Because the refresh interval will typically be more than hundreds of microseconds and Trc is typically 70ns REF REF will always be met The fastest two ACTV command or ACTV to REF can be issued will be in the case of two consecutive auto precharge single reads Since the time for this 15 RAS CAS delay min 2 CAS latency min 2 Burst length min 4 Precharge typ 2 10 CKIO cycles and Trc 1s typically 70ns and so this 1s fine also The only issue here is the time from REF to ACTV Since an ACTV can be output at the beginning of a normal read write there must be sufficient delay following the REF command The setting for this time 15 defined by MCR TRAS The following equation must then be satisfied SDRAM SH 4 Tre lt MCR TRAS SE F080 Rev 2 0 32 bit SH 4 Page 55 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 5 2 6 8 Troh This value is the delay between a precharge command and high impedance of the data bus This me
54. bit row 4 bank BSC BIT RFSH 0 switch refreshing off for now TT BSC BIT RMODE 0 Select auto refreshing not self BSC RTCSR WORD RTPWD1 amp 0x0008 Overflow compare match interrupt disabled clock bus phi 4 count limit dont care BSC RTCNT RTPWD1 amp 0 Clear timer counter BSC RTCOR RTPWD1 amp 1 Set compare match value to 1 decimal This will enable 8 fast refreshes 7 BSC RTCNT RTPWD2 amp 0 Set refresh count to 0 ar Assume 200us idle time for SDRAM has been satisfied by power on reset SDMR3 0 Precharge all banks PALL BSC MCR BIT RFSH 1 enable refreshing ay while BSC RTCNT lt 8 wait for 8 auto refreshes 47 BSC MCR BIT MRSET 0 Enable output of MRSET command SDMR3 0 Trigger MRSET command oy BSC RTCOR RTPWD1 amp 195 Set compare match value to 195 dec This returns the interval to normal SDRAM now set up T4 SE F080 Rev 2 0 32 bit SH 4 Page 78 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 7 Summary The application note shows in detail all important aspects of interfacing SDRAMs to SH 4 From understanding how the SDRAMs works the physical connection and the timing consideration to writing the initialization code for SH 4 This also forms the base for interfacing new products of the SH 4 familiy the SH775xR will allow higher data bandwidth due to higher frequency 8 References SH7751 Hardware Manual V2 0 Hi
55. c is not specified in the manual Hence it follows that a selection of a right external PLL is difficult Don t use PLL circuit 2 when using a external PLL DLL Circuit This feature is available for SH7751 with CKIO of 66 MHz As with the PLL circuit 2 the DLL circuit coordinates the phases of the bus clock and CKIO pin output clock Starting and stopping are controlled by the frequency control register 2 setting The main difference with the PLL circuit 2 1s the stabilisation time for the clock output from the CKIO pin at startup of 6 CKIO cycle PLL circuit 2 is automatically switched off when the DLL bit is set in the register Figure 5 4 shows a block diagram of it DLL circuit PLL circuit 2 Figure 5 4 DLL and PLL2 circuit SH7751 SE F080 Rev 2 0 32 bit SH 4 Page 60 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 9 2 8 2 Tclk Tclk 1s the minimum cycle time for the SDRAM input clock Hence it also specifies the maximum frequency the SDRAM can operate at Since virtually all SDRAM recommended for design in 1s at least PC100 specification even with the fastest CKIO clock this parameter can be met 5 2 8 3 Tch Tcl Tch are the minimum clock high low times required by the SDRAM Note that the voltage threshold for this measurement is 1 4V The SH 4 BSC specification provides two values based on both the normal LVTTL thresholds and 1 5V 2 The 1 5V thresh
56. cles must be taken into consideration in this equation SDRAM SH 4 tuz lt idle cycle setting tcyc SE F080 Rev 2 0 32 bit SH 4 Page 52 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 Tpr Tpe Tr Trw Tet Te 4 i ms ol B nid Pracherge sal E HR Addr B o 1 atwo RASOI RASO RAS RAS E l rice lid DQMn area 063 00 063 00 DACO DACO B Figure 5 2 Combined SDRAM and SH 4 Timings SH 4 Timings SH 4 HW Manual Synchronous DRAM Normal Read Bus Cycle PRE ACT READCommands Burst RCD 1 0 01 TPC 2 0 011 RCD 1 CAS Latency 3 SE F080 Rev 2 0 32 bit SH 4 Page 53 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 5 2 6 SDRAM Wait State parameters All of the wait state parameters are controlled by adjusting the BSC registers The goal is to minimise all register values to minimum wait times whilst still meeting every timing parameter As before tcyc CKIO period 5 2 6 1 Trrd Trrd is the minimum delay between RAS and the next RAS cycle Ie The minimum time period between two ACTV commands of different banks A typical value for this parameter is 20ns Since the SH 4 will always perform a read or write following an ACTV before issuing the next ACTV even with CKIO 100 MHz
57. clock ratios The setting of the RAS Down mode goes with the pipeline access mode Pipelined access 15 performed between an access by the CPU and an access by the DMAC or in the case of consecutive accesses the DMAC to provide faster access to synchronous DRAM As synchronous DRAM is internally divided into two or four banks after READ or WRIT command 15 issued for one bank it is possible to issue a PRE ACTV or other command during the CAS latency cycle or data latch cycle or during the data write cycle and so shorten the access cycle SE F080 Rev 2 0 32 bit SH 4 Page 36 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 4 SDRAM Controller differences between 5 77505 8 7751 4 1 Overview The SH7750S amp SH7751 have very similar BSC SDRAM control features however there is one significant difference between the two devices for the basic SDRAM bus cycle This is that the burst length of SDRAM When you connect SDRAM to the 7751 with 32 bit bus your should set a burst length of 4 as compared with 8 for the 7750 This means 2 reads or 2 writes are required to complete a 32 byte access compared to 1 for the 7750S for example to fill or write back a cache line 7150 7151 SDRAM Burst length 32bit width IR SDRAM Burst length 64 bit width Number of READ WRIT commands for burst access Burst access size cache line size 32byte 32byte Table 4 1 Summary of Differences between SH 4
58. connected to the 7751 is half that of the 7750 however a burst access is still 32bytes See SDRAM Controller differences between 77505 amp 7751 in the next section for details SE F080 Rev 2 0 32 bit SH 4 Page 35 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 In most cases the cache will be switched on and operates with a write back policy This ensures maximum CPU FPU performance and will mean the SDRAM is accessed using the high efficiency burst access In the case of a read cache miss the first access will be to the missed data and the rest of the 32byte block will be read in wrap around mode This increases the efficiency during a cache fill when the missed data is not aligned to a 32 byte boundary 32 byte boundary data is also written in wrap around mode The basic memory storage technology inside SDRAM is DRAM and hence memory cells need to be refreshed There are two refreshing options available both of which are supported by the SH 4 The selection of the refresh mode is controlled by the RMODE bit in the MCR mode control register Auto refresh is a command which 1 issued by the BSC Included in the BSC 1s a refresh timer which issue a REF command on a compare match The user needs to configure this timer such that each row will be refreshed within a certain period eg 64ms In most cases the lost bandwidth from refresh cycles can be ignored fraction of a percent In addition it 1s
59. cycles to 2 cycles when using a lower bus frequency This can compensate for the lower bus frequency and provide a reasonable random access read time SE F080 Rev 2 0 32 bit SH 4 Page 49 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 5 2 5 SDRAM Setup and Hold parameters Note In all cases tcyc CKIO period Eg 100 MHz 10ns 83 MHz 12ns 66 MHz 151 56 MHz 18ns and 50 MHz 20ns For better imagniation you can find most timing values also indicated in the timing diagram Figure 5 2 5 2 5 1 Tac Tac is the access time of read data from the rising edge of the clock This means it 15 the maximum delay to valid data from a rising edge Note that this parameter 15 not related to CAS latency This parameter can be used to calculate setup time for read data for the SH 4 Because the data is sampled on the following rising edge 1 CKIO cycle later the SH 4 equation and hence condition to meet 15 SDRAM SH 4 Tac lt tCYC tRDS 9 2 5 2 Toh Toh 15 the read data output hold time It specifies the minimum time that the SDRAM will hold valid data following the rising edge of a read cycle This equates directly to the SH 4 BSC required read data hold time Hence the following condition must be satisfied SDRAM SH 4 Toh gt tRDH 9 2 9 3 Tsi is the input setup times of the SDRAM control signals such as CS ADDR RAS CAS BS amp DQM the input setup time for write data and the input setup
60. dresses Burst mode reduces CPU bus usage since only one address needs to be generated rather than a specific address for every data location requested The responsibility for determining the first SE F080 Rev 2 0 32 bit SH 4 Page 9 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 address and the size of the burst as well as possibly generating the subsequent addresses falls on the memory controller If multiple burst lengths are supported the complexity of the memory controller is greatly increased SDRAMs have an on chip burst counter which can be programmed based on the burst length requirements of a given cycle The on chip burst counter accepts the first address of the burst cycle and increments in a particular sequence based on that address The burst length is specified by programming the mode register after power up If multiple burst lengths are required in a system the mode register can be reprogrammed prior to the execution of the new burst cycle The device must be in the idle state each time a mode register set MRS operation is executed No additional SDRAM control logic is required to support multiple burst lengths The SDRAM handles this internally based on information programmed into the mode register The mode register contains the basic operating characteristics of the SDRAM Four burst lengths are supported 2 4 8 and full page For example a four cycle burst means that the processor generate
61. e can be used during long latency I O operations Low power mode is also very useful in battery operated devices The AUTO REFRESH state is entered by execution of the REF command which is used to refresh the array during normal operation The REF command can only be executed during the IDLE state assuring that a refresh operation cannot occur while any cycles are in progress Once the refresh operation is completed the machine automatically transitions to the PRECHARGE state before returning to the IDLE state Transition to the POWER DOWN state causes all input circuits to the memory array to become high impedance effectively cutting off the array from the rest of the device No refresh operations are performed while the machine is in the POWER DOWN state The transition of CKE from high to low along with other input conditions causes the PWRDN command to execute as shown in table 2 1 The machine can remain in the POWER DOWN state for an indefinite amount of time A low to high transition on CKE along with other input states causes execution of the PWRDNX command allowing the machine to return to the IDLE state On power up the mode register is programmed after all internal banks are precharged Once the machine enters the IDLE state for the first time execution of the MRS command causes the machine to transition to the MODE REGISTER SET state While in this state the address bus is used to program the register After the operation 15 completed
62. e high and low times and voltage threshold levels It is also very important to consider the rest of the system here as the CKIO frequency and quality 15 often limited by other devices connected to the SH 4 local bus and the PCB layout Probably the most important and usually first decision to be made 15 the choice of bus clock frequency In the case of a 200 MHz feasible with 77508 and package BGA likely choices are 100 Mhz CKIO CPU 2 or 66 MHz CKIO CPU 3 For a 167 MHz SH 4 such as the SH7751 likely choices are 83 MHz CKIO CPU 2 or 55 MHz CKIO CPU 3 Choice of system bus speed is extremely important in all systems Performance requirements generally mean high speed and many factors require lower speed such as EMC EMI timing problems power dissipation and other limiting factors such as peripheral ICs Note that the SH 4 supports dynamic clock scaling so low power can achieved by modifying the CPU BUS PERIPHERAL clock when the system 15 in idle state Generally higher clock frequencies mean higher performance and this 1s especially the case where pure bandwidth is concerned However in the case where several random accesses may occur or when a read cache miss occurs the time to first access 1s often the key factor Note that sometimes it is possible depending on SDRAM settings to reduce the CAS latency from 3 SE F080 Rev 2 0 32 bit SH 4 Page 48 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0
63. e programmability offered by SDRAMs allows the processor to know how long it will take to retrieve the data once the memory cycle has been initiated For example assuming a SDRAM has an initial read delay of 70 ns and operates at a clock frequency of 100 MHz This means that once the memory is accessed data will be available 7 clock cycles cc later 7 cc x 10 ns cc 70 ns During that 7 clock cycle the processor can perform other activities returning only when the data 1s available SE F080 Rev 2 0 32 bit SH 4 Page 7 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 Although the same basic naming convention is used for both DRAM and SDRAM RAS CAS WE etc they do not have the same meaning In an SDRAM these signals are interpreted as bits of an opcode forming the SDRAM command set These commands are listed below and are discussed in the section Theory of SDRAM Operation synchronous DRAM pipeline standard DRAM E Add 1 pers on ve E wee pes Figure 1 2 shows an example of SDRAM pipelining compared with a standard DRAM SE F080 Rev 2 0 32 bit SH 4 Page 8 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 synchronous DRAM pipeline Standard DRAM zm 1 Figure 1 2 SDRAM Pipelining compared with a standard DRAM 1 4 Sp
64. echarge operation Whereas in the READA or WRITA state the transition occurs automatically upon completion of the operation SE F080 Rev 2 0 32 bit SH 4 Page 33 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 3 SH 4 Bus State Controller SDRAM Overview The SH 4 series have been designed to provide a direct interface to SDRAM Once the BSC has been correctly configured the user simply treats the memory area as RAM and can perform read write accesses of 8 16 32 64 bit amp 32 byte without being concerned by the physical width of the connected SDRAM The control logic of the SDRAM interprets transitions on the external pins as commands which are in turn used to transition the state machine The SH 4 supports a sub set of these possible SDRAM commands Furthermore two chip select areas are supported each providing a 26 bit area which provides a maximum configuration of 128 Mbytes 2 x 2726 SDRAM total Where only one area is used then CS area 3 should be chosen as it does support RAS Down mode It is not possible to select area 2 as SDRAM area alone The supported bus widths for SDRAM are 64 or 32 bit for the 7750 and 32 bit only for the 7751 The real performance of SDRAM is realised when performing burst accesses For the SH 4 all burst accesses are of length 32 bytes This corresponds to 4 words with the bus in 64 bit mode or 8 words when the bus 15 set to 32 bit mode Looking to the rest of the SH 4 archi
65. ecuted PRE The PRE and PALL commands both perform the precharge operations the PRE command precharges a single bank while PALL precharges both banks As shown in table 2 1 the simultaneous assertion of RAS and WEZ during normal execution denotes a precharge operation During normal operation address bit A12 and A13 15 used to select which bank 15 precharged Address bit 10 indicates whether the PRE or PALL operation is executed Subsequent cycles cannot be executed while the PRE command is being executed and the precharge operation is in progress After the operation is completed the state machine switches to the idle state Only then the ACTV for a follow on cycle can be executed PALL Execution of the PALL command causes control logic to initiate a precharge operation to both banks of the SDRAM simultaneously During a PALL operation address bit A12 13 are ignored Address bit A12 and 13 indicates whether the PRE or PALL operation is executed Subsequent cycles cannot be executed while the PALL command is being executed and the SE F080 Rev 2 0 32 bit SH 4 Page 18 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 precharge operation is in progress After the operation is completed the state machine switches to the idle state Only then can the ACTV for a follow on cycle be executed REF The SDRAM architecture supports two types of refresh modes which are defined by the REF and SELF commands Only the REF command
66. ed If CS is sampled high during any rising clock edge the information on the external pins 1 ignored After the device is powered up the mode register can be programmed The mode register is undefined on power up Therefore cycle behaviour is also undefined until this register is programmed since the contents of the mode register determines the characteristic of each cycle In addition to power up the mode register can be programmed during normal operation whenever the state machine is in idle state in order to change the operating characteristic of the device The mode register Figure 2 3 15 indicated by the MRS command and is listed in the table shown in section mode register The mode register is programmed by driving certain values onto the address pins while the main control signals are all driven low as shown In the SDRAM architecture the assertion of RAS is completely separate from the assertion of CAS and has its own command Whenever a cycle is initiated from the idle state the first command to be executed is the ACTV command With the exception of precharge and refresh operations RAS is only asserted during the ACTV command At the time the ACTV command is executed the SDRAM has no idea what type of data operation is to be performed Its only function is to prepare the given row for a memory access The assertion of CAS causes the various read or write commands to be executed which typically occur two cycles after RAS asser
67. ed and the input states are provided to the state machine Because an SDRAM 15 pipelined a given SE F080 Rev 2 0 32 bit SH 4 Page 13 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 cycle may or may not begin at the same time as its corresponding address is latched The external signals of an SDRAM do not directly control the internal circuits Rather the state of the inputs on any given clock causes transitions in the main state machine which in turn determines the type of cycle to be run 2 2 Power On Sequence The power on sequence for the SDRAM products 1s defined by the JEDEC standards committee 1 Apply power and start clock Attempt to maintain NOP condition at the inputs 2 Maintain stable power stable clock and NOP input conditions for a minimum of 200 microseconds 3 Issue precharge command PALL for all banks of the device 4 Issue 8 or more auto refresh REF commands 5 Issue mode register set MRS command to initialise the mode register The following figure 2 2 shows a timing diagram of the power up sequence Power 3 3 volts v LC 200us dg Trsa Clock Command NOP Address BankSel DOML DOMU Precharge all banks 8 or more REF Mode Start of commands register operation set Figure 2 2 Typical power up sequence SE F080 Rev 2 0 32 bit SH 4 Page 14 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 2 3 C
68. er Width Relevance to SDRAM control Specifies RAS amp CAS timing address multiplexing and refresh control critical SDRAM configuration No effect on SDRAM area Controls refreshing settings Refresh timer counter Refresh compare match register inside the SDRAM inside the SDRAM Counts the number of refreshes issued Table 4 2 SH 4 Bus State Controller Registers related to SDRAM Note The refresh control registers are all password protected to reduce the chance of accidental writes special value must be included in the upper bits to allow a write value to be latched 4 2 Bus State Controller Register 4 2 1 Bus Control Register 1 BCR1 Bits 4 2 Controls the memory type of CS area 2 amp 3 Note that the BSC will allow SDRAM in area 2 amp 3 area 3 alone or neither It is not possible to select SDRAM memory type just for area 2 Hence always use area 3 1f only one area of SDRAM 1s used 4 2 2 Bus Control Register 2 BCR2 Bit 0 Controls the use of D51 to D32 These bits function as a port 1f set to 1 In this mode 64bit bus width 1s illegal Note the width settings defined in area 2 amp 3 are ignored when SDRAM is enabled The MCR register setting controls the width for the SDRAM areas 4 2 3 Wait Control Register 1 WCR1 Bits 14 12 Controls the number of idle cycles inserted following an access to CS area 3 The hold time of SDRAM by definition is very short less than 1 CKIO cycle In
69. g on the design of the memory system The processor generates an address which 1s latched resulting in the assertion of RAS and CAS RAS must be held active throughout the entire access meaning that the DRAM cannot accept new address and control information during this time This non pipelined approach can have a very negative effect on the overall performance of a system To solve this problem memory systems have become increasingly complex with a form of pipelining being implemented by multiple banks which switch at different times in order to hide these inherent latencies One bank of is accessed then another and so on four way interleaved memory system can offer some performance boost but large amounts of real estate are normally required to facilitate this In addition DRAM control logic complexity is greatly increased Herein lies the biggest advantage of the SDRAM architecture All control signals are sampled on the rising edge of the clock Control signals such as RAS and CAS need only be asserted for one clock meaning that the processor need only drive address and control signals for as long as it takes for this information to be recognised by the SDRAM controller Unlike standard DRAMs where CAS could not be asserted on consecutive clocks the SDRAM can accept a new column address on every clock allowing for a memory system which can meet the throughput requirements of today s high speed microprocessors Th
70. gram below shows the address bank select and precharge select bits during a SH7750 32 bit wide SDRAM burst read Note that the Bank bits remain static through the RAS amp CAS phases and the precharge bit represents an address when RAS is asserted and part of the command word precharge select during the CAS cycle SE F080 Rev 2 0 32 bit SH 4 Page 46 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 TR TRW Tc2 Tc4 Tdl Td2 d Td4 Td5 Td6 Td7 Td8 TEH HH HHHH zur Address Precharge select Figure 5 1 Timing diagram address and precharge bits Clearly providing the correct address multiplexing setting 1s important The address multiplexing is controlled by setting the AMX bits in the MCR memory control register On the SH 4 there are 4 AMX bits AMX 3 0 and AMXEXT The SH 4 Hardware user manual provides SDRAM multiplexing tables in the appendix For each design it 15 recommended that the address multiplexing is double checked so that all of the signals are correctly output during both RAS and CAS cycles 5 2 Timing Check Performing a timing analysis between a SDRAM and the BSC initially seems very difficult especially following a look at timing diagrams There are many parameters to analyse and meet however the task is not so much difficult as lengthy The method of timing analysis used within this application note 1s to take each of the SDRAM parameters in turn
71. gs is an iterative process It 1s best to start with the smallest setting first and work upwards TRC is increments in values of 3 so 3 1s the minimum setting As this delay is only inserted during a refresh cycle not providing an optimal setting here is not significant TRAS is a constant 4 to 11 TRC and as TRC 15 already 3 the minimum setting can be made and Trcd 1s easily met TRWL has to be increased to 2 to satisfy Tdpl so the following settings in the MCR have been derived MCR Register bits CKIO cycles MCR TPC 001 MCR TRWL 001 MCR TRC 001 owo Table 6 4 MCR settings SE F080 Rev 2 0 32 bit SH 4 Page 74 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 So far we have defined most of MCR and the settings are summarised in the diagram below 30 27 20 24 23 22 20 18 17 asn VRSET me mo tect Tre RCOO Pitot oti o O O TU 2 TRA TRAS2 TRAS1 TRASO 521 520 AMEXT ANDO RMODET EDO xo Table 6 5 Memory Control Register MCR The remaining settings not described above are as follows RAS Down This will enable the high speed access mode MRSET This is used during the initialisation See the code later for details SZ Memory width setting This 1s 32 bits 7 11 as mentioned i
72. h Timer Control Status Register RTSCR Note The password upper 8 bits of 16 bit word to write to this register is B 10100101 H A5 Bit 7 CMF Indicates a RTCNT RTCOR compare match Does not need to be initialised during SDRAM configuration SE F080 Rev 2 0 32 bit SH 4 Page 41 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 Bit 6 CMIE Compare match interrupt enable Should normally be set to 0 Bits 5 3 CKS2 5 Clock prescaler configuration bits These bits set the division ration of the refresh counter clock which 1s derived from CKIO Bit 2 OVF Overtlow flag which can be configured to be set following 512 or 1024 refreshes Bit 1 OVIE Interrupt control bit Enables or disables the interrupt after 512 or 1024 refreshes as set by bit below Normally this bit and hence interrupts 15 disabled as refreshing is taken care of by the refresh timer hardware Bit 0 LMTS Specifies whether OVF flag is set following 512 or 1024 refreshes 4 2 9 Refresh Count Register RFCR Note The password upper 6 bits of 16 bit word to access this register is B 101001 H A4 Bits 9 0 RFCR 9 0 This register keeps a count of number of refreshes and clears itself when 512 or 1024 as set by RTCSR LMTS Generally this register is not of interest apart from during initialisation when a pre set number of refreshes need to be waited for 4 2 10 Refresh Timer Coun
73. h gives a guaranteed rise and fall time of 4ns Because the slew rate and hence rise fall time is almost completely dependent on the target it is important to design the clock distribution very carefully Track length characteristic impedance and track topolgy are all important however the single most important factor for rise and fall time 1s load capacitance Halving the load capacitance can halve the rise time so this should be taken into consideration during design In the case of the SH 4 7750 a second CKIO output is available which can make design easier Please note that the PLL does not phase compensated CKIO2 It is important to match the loads on CKIO amp CKIO2 for minimum skew The 7750 hardware manual details the internal connections of the CKIO CKIO2 pins in the appendix As clock distribution design is a very specialised skill it is highly recommended that the designer characterises his own CKIO rise fall time for the actual target being used The quality of CKIO rise fall also influence the setup and hold times and it is recommend to read in this context chapter Hold Time consideration using slew rate Some further details on clock design are provided in the Clock connection guidelines section of this application note PLL Circuit 2 PLL circuit 2 coordinates the phases of the bus clock and the CKIO pin output clock Starting and stopping is controlled by a frequency control register setting The PLL2 characteristi
74. h signals actually get presented on the address bus during the RAS and CAS cycle The so called mapping here is 12 9 The fourth column shows the SDRAM address pins The important features are as follows RAS Cycle A25 A12 These are the upper 12 bits which specify the row address SE F080 Rev 2 0 32 bit SH 4 Page 45 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 BAI BAO The bank select bits decide which of the four banks 1s selected CAS Cycle 11 These are the lower 9 bits of the address which select the column address 10 10 becomes the Precharge Select bit This bit does not specify any address information Instead it makes up part of the command word The level of the precharge select bit defines whether an auto precharge or standard read write is performed Auto precharge accesses are always used on the SH 4 unless RAS Down mode is enabled The bank bits decide which of banks 15 selected Note The bank select bits do not change from the RAS to the CAS cycle This effectively means these bits are not multiplexed Note that the same address line is output during the RAS and CAS cycle Summing the address lines together over the RAS and CAS cycle for the 128 Mbit x16 device mentioned you get Total address bits 12 Row 9 Column 2 Bank select 23 bits Total capacity 2 23 8M words device is organised x16 16 Mbytes The timing dia
75. he ACTV command is executed any time a read or write operation 1s to be performed The ACTV command is responsible for latching and decoding the row address and activating the appropriate row in the array The ACTV command is unaware of the type of operation to be performed and does not require this information in order to complete Once the ACTV command is complete a read write or precharge operation can be performed and the corresponding column address driven A subsequent ACTV command is allowed while the current ACTV command is in progress as long as the access 15 to the opposite bank In most SDRAM devices there are more rows as columns in the memory array Therefore additional address bits are required to adequately decode the row address relative to the column address For example in a 128 Mbit SDRAM with a 16 bit data bus twelve address bits A11 0 are required to decode one of rows while only nine address bits 8 0 are required to decode one of 512 columns During the ACTV command the address bits A12 and A13 are used as a bank select while bits 11 0 determine the row address During column address generation address bits A12 and A13 1s also used as a bank select but only address bits 8 0 are required for the column address On read cycles address bit 10 is used to determine whether the READ or READA command 1 executed On write cycles address bit A10 1s used to determine whether the WRIT or WRITA command is ex
76. he processor must spend increasing amounts of time waiting for data 1 2 DRAM Cell 1 2 1 The Basic Cell The basic DRAM cell 1s comprised of a transistor as a switch and a capacitor as a data storage element The digit that is saved in the storage cell 1s determined as logic 0 or 1 by the voltage potential stored inside the capacitor C If the voltage stored is Vcc then it means a logic 1 If the potential is ground then the logic 0 is inside Reading of the storage cell is activated by a WORD LINE and a pair of BIT LINES The WORD LINE controls the switch of the transistor T to turn on in order to let the charge on the capacitor pass to the bit line BL The charge on the capacitor C and the Bit line BL will share together to form a new voltage potential Before the open of transistor T the bit lines BL and need to be precharged to the same voltage level 1 2Vcc After the transistor T is opened bit line BL will get a new voltage potential due to the voltage sharing no matter that the C 1s with Vcc or with Ground potential Then the bit line pairs that carry differential voltages will be connected to the sense amplifier circuit to determine if 0 or exists in that cell SE F080 Rev 2 0 32 bit SH 4 Page 5 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 Word Line WL Bit Line BL Sense Amplifier Bit Line BL Tran sistor Mood see y 1 2
77. her devices in the system can assert the databus within 5 4ns of being selected so the idle cycle setting is 1 for area 3 This gives us the initialisation value for WCR2 0 Idle cycle insertion WCRI A3IW 001 If there isn t a device which can assert the bus faster then 5 4ns also the idle cycle setting of 0 for area 3 might be possible SE F080 Rev 2 0 32 bit SH 4 Page 73 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 6 2 2 Wait State Parameters The wait state parameters can be controlled by adjusting the BSC registers The goal is to minimise all register values to minimum wait times whilst still meeting every timing parameter Note that in some cases multiple parameters depend on a single register setting In this case the smallest value which meets all of parameters should be chosen Only the parameters that an equation has been specified for are considered as the rest have already been met SDRAM Unit SH4 Unit Note Tred gt tCYC MCR RCD ns MCR RCD 2 Trp gt tCYC MCR TPC ns Yes MCR TPC 2 Tdpl gt tCYC MCR TRWL 20 Yes MCR TRWL 2 MCR TRAS 0 Tre 60 ns gt tCYC MCR TRAS 70 ns Yes amp MCR TRC 23 A Tdal 4 MCR TPC 4 Yes TPC TRWL 2 ISREX 3lcyc Yes MCR TRC 3 Tmrd 2 4 _ on SH4 Yes IAPR 2 Yes MCR TPC 2 Table 6 3 Wait State Parameters Deriving the various MCR settin
78. is from a design standpoint The controller can manage the mode register so that when a memory cycle occurs where the burst length is different from that of the previous cycle the controller can insert an MRS cycle and reprogram the mode register accordingly The controller set the burst length at power up and leave it For processor cycles that require more data than the set burst length the controller can perform as many bursts as it takes to supply the processor with the correct amount of data For example assume the burst length 1s set to two transfers and the processor requires a four transfer burst The controller can perform a two transfer burst then another This approach would require the controller to SE F080 Rev 2 0 32 bit SH 4 Page 21 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 generate the first address for the second burst During single transfer cycles the controller can simply ignore data from the second transfer AG CAS latency E length ofofo R 0 Sequential interleave DESEE 2 R 8 R R_ Burst read and burst write 1 Burst read and single write Full page R Reserved inhibit I m n n 1 m n ER Figure 2 3 Mode Register 128 Mbit SDRAM Regardless of the size of the burst cycle requested the SDRAM always transfers the
79. it SDRAM the row address decoder is responsible for taking the 14 bit input and determining which of the 4k rows in one of the four banks 15 activated The lower bits are used to activate the actual row A0 A11 while the address bits A12 and A13 determines the bank The state of the address bits bank select bits causes only one bank to be activated thereby reducing power consumption 4 Activates the appropriate line driver based on the row address decode The next figure shows a flow diagram of the ACTV command Refer to section 2 3 Command Operation for more information on the ACTV command 1 Set row address Latch row address and BS 3 Activate bank row address 4 Activate word line Figure 2 5 ACT Command Flow Chart 2 Read Operation data cycles start with execution of the ACTV command which is generated by the state machine whenever CS and RAS along with valid address are asserted simultaneously The SDRAM commands are defined in table 2 1 After execution of the ACTV command the array still does not know 1f the pending cycle will be a read a read with auto precharge a write or a SE F080 Rev 2 0 32 bit SH 4 Page 25 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 write with auto precharge Which subsequent command is executed depends on the state of address bit A10 as well as the WEZ signal These parameters are defined along with the assertion of CAS
80. lit Bank Architecture The internal memory array of the SDRAM consists of four separate banks Which bank is selected depends on the state of the two highest order address bits In a 128 Mbit SDRAM this would be A12 and A13 The four bank scheme maximises bandwidth since each bank can be accessed independently of the other Once a given row in a given bank has been selected it can be held active and accessed on every clock cycle by simply supplying a new column address In addition if data from four different rows is requested and the rows are in separate banks much of the precharge can be hidden One bank can be accessed while the others are being precharged This approach mimics a four way interleaved memory scheme Once the row of each bank has been activated alternate column accesses can occur every clock cycle effectively causing the device to ping pong between banks This 15 because transition intervals are much faster between rather than within banks In addition multiple physical banks of devices are not needed reducing the amount of space required and simplifying the memory control logic 1 5 Programmability In order to retrieve memory data at the highest possible rate the processor architectures implement burst mode E g the processor can initiate a burst for a cache line fill In a burst cycle the processor generates only the first address of the read or write sequence requiring the memory chip itself to generate the remaining ad
81. llars The main advantage of a DRAM 1s the package densities which can be attained due to the fact that single memory cells are represented by a single transistor and capacitor as opposed to a series of transistors These densities allow for large amounts of memory to be represented by relatively few components Advances in semiconductor process technology have caused package densities to increase by a factor of 1000 since the modern DRAM architecture was first introduced in the late 1970s from 16 kbit devices then to 512 Mbit devices today Although package and process technologies have improved the basic architecture of the DRAM has not changed since it was first introduced A 2 bit DRAM 1s typically organised as 27 2 rows by 27 2 columns The rows are addressable using the Row Address Select RAS signal and the columns are addressable using the Column Address Select CAS signal More importantly the speed with which data can be retrieved from a DRAM has not kept pace with increases in microprocessor speeds This is no easy task since in some cases microprocessor speeds have increased by an order of magnitude just since the late 1980s A finite period of time is required by the DRAM to access the requested location once the address and proper control signals have been asserted Over the years various flavours of the basic DRAM architecture have been introduced in order to help reduce these access times However the end result has been that t
82. lly a synchronous state machine The address lines coupled with the bank select and RAS CAS lines are slightly more complex They provide the full address over two phases This is described in the next section SE F080 Rev 2 0 32 bit SH 4 Page 44 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 5 1 1 Address Multiplexing To keep the pin count low on SDRAMs the address is multiplexed Eg in the case of a 128 Mbit x16 SRAM device a 23 bit address would be required however only 12 address bits and 2 bank selects are provided by the SDRAM To provide the complete address to the SDRAM a RAS and CAS phase are required The table below shows how this is split for a typical 128 Mbit device Gabi 4x126MbE steal 5 7750 tem nal SDRAM RAS CAS nal Functon zs pus serere Ani 0 _ ks Bii 2 pedum mari _ pu pe _ ps je _ ps a pn _ pl _ x 16 15 14 13 A12 d x OX Table 5 2 Table showing address multiplexing during RAS amp CAS cycle The first column represents the physical pins of the SH 4 in this case a 7750 operating with a 64 bit wide bus Hence A2 A0 on the SH 4 are unused The second and third columns shows whic
83. ly during the CAS cycle The box shows the first 9 bits of the address correctly connecting during the CAS cycle with SH 4 A2 A10 connecting to SDRAM AO 8 The 13 bit row address the next 13 higher bits of the address corresponds to 8192 rows will be output during the RAS cycle SH 4 A11 A23 must be output to SDRAM AO A12 as shown by the box on the RAS column Next the two bank bits the highest two address bits corresponds to 4 banks must connect correctly to the SH 4 A24 A25 and this must happen during both RAS and CAS cycles Finally the address precharge bit must be correctly output during the CAS cycle On this SDRAM A10 is the address precharge bit so this must be correctly output from the SH 4 A12 This bit makes up part of the command word and differentiates between a precharge or RAS Down access SE F080 Rev 2 0 32 bit SH 4 Page 70 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 The table above matches the SH 4 7750S multiplex setting AMX 6 AMXEXT 1 This gives us the AMX settings in the MCR Multiplex setting AMX AMXEXT 1 MCR AMX 1105 for the representation of the bit settings in the BSC the assumption 15 made that the register are declared 1n C structures MCR AMEXT 15 The resulting connection between the SH 4 and the SDRAMs will be as follows SDRAM 1 Upper 16 bits SDRAM 2 4 7 7505 Lower 16 bits 32 bit bus m Figure 6 1 Physical connection
84. n the worked example title RFSH This enables refreshing and is demonstrated in the attached code RMODE This is used for putting the SDRAM into self refresh and is not used in this example The above basic MCR setting will be used in the code example along with the bits with an asterisk to initialise the SDRAM controller 6 2 3 Auto Refresh Interval parameters There are two constraints on the refresh time here and the lowest of the two must be chosen The maximum row active time Tras here is 120us and the self refresh command period 1s as follows tarer trer 2 no rows 64ms 2 13 7 8125 us As this value is smaller this is the value we must use for the refresh generator To calculate the values needed for the refresh registers the first thing to define 1s how many CKIO cycles fit into 7 8 us This is 7 8125us 10ns 781 25 781 cycles when rounded down Because the smallest prescaler value the refresh counter can be driven with is CKIO 4 this corresponds to a refresh time constant register RTCOR setting of 781 4 195 Hence setting for refresh time constant register RTCOR 195d SE F080 Rev 2 0 32 bit SH 4 Page 75 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ME asij CKS0 ove ove 5 SENE o o o ojojoixog 1 0 1 Table 6 6 RTSCR setting From here we
85. nd self refresh The state of the signal determines which type 15 used For normal operation where the signal is asserted and the clock 15 enabled CKE 1 auto refresh can be used Auto refresh contains an on chip refresh counter and 15 similar to a typical refresh cycle No external addresses are required When the SDRAM is in low power mode CKE negated and the clock disabled self refresh mode can be used allowing the SDRAM to refresh itself In low power mode the SDRAM requires only 4 mA of current in order to refresh itself 1 8 Marking of SDRAMs On top of each SDRAM package there should always be printed the partname followed by the production date and the three most important timing parameters CL tRCD and tRP CL defines the number of cycles between the latching of RAS and CAS command The time tRCD is valid just for read access and defines the number of cycles between the CAS command is latched and the first data are bursted out of the SDRAM And finally tRP defines the number of necessary precharge cycles The timing parameters are printed on the chip and are expressed in cycle on e g 2 2 2 SE F080 Rev 2 0 32 bit SH 4 Page 12 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 2 Theory of SDRAM Operation 2 1 Overview This section explains the basic theory of operation of SDRAMs focusing on those areas of the architecture unique to the SDRAM Those areas of the architecture that are the
86. number of data items as defined in the mode register For example if the mode register is set to a burst length size of four and the processor requires only a single data transfer the SDRAM still transfers four data items It 1s up to the controller to assure that the remaining three data transfers are ignored by the processor Mode register bits 2 0 define the burst length size Burst lengths of 2 4 8 and full page are supported Those entries marked R are reserved and equate to an illegal opcode which if used can cause unpredictable device behavior A full page burst length size can only occur when sequential burst mode is used Bit 3 Bit 3 defines the burst type e Sequential burst mode means that each transfer of a given burst resides at a sequential address The burst counter advances sequentially and the data 1s returned The counter simply starts at the address defined by the processor and wraps around until all of the data 1s transferred e Interleave burst mode not supportet by SH4 allows support of the Intel sub block ordering protocol where one of four burst sequences can occur based on the value of the starting address Interleave mode affects the way address bits AO and are incremented in the SDRAM controller Table 2 3 shows each of these sequences SE F080 Rev 2 0 32 bit SH 4 Page 22 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 Burst xai Burst length 4 Starting Ad
87. old timing should be used for this equation as follows SDRAM SH 4 lt 1 SDRAM SH 4 tcc lt tckoro S F080 Rev 2 0 32 bit SH 4 Page 61 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 5 2 9 Timing Sheet 5 77505 and 256 Mbit SDRAM The following timing sheet table xx enables you to do all the timing related calculation in a quick and easy way The applied timings rules are already discussed in the past sections You could overtake this example into your own exel sheet The exel sheet is devided in four main parts the SDRAM the SH7750S the Equation and the SH 4 Bus State Controller Settings The SDRAM timings e g Tckl or Tac should be referred in the latest data sheet and entered into the columns Min ns or Max ns The same have to be done with the SH7750S timings like tCYC or tAD The register settings in part SH 4 Bus State Controller Settings are the result of the discussion in the past section Overtake these settings and adapt it to your requirements The column possible values Unit indicates you the allowed settings The part Equations lists all the formulas necessary to check and guarantee the SDRAM timings on the left hand side with the timings of the SH 4 on the right The column Meet Timing Constraint compares then the SH 4 resulting timings of the column Result with the minimal or maximal SDRAM timings The entry in column
88. ommand Operation One significant difference between standard DRAMs and SDRAM architecture is the way in which internal accesses are executed In standard DRAMs the toggling of the external pins has a direct effect on the internal memory array In a SDRAM the input signals are routed to a control logic block within the device which functions as the input to a state machine Transitions in the state machine control the actual memory access This approach allows pipelining of accesses to the SDRAM For example in a standard DRAM once RAS 15 asserted the memory array cannot be accessed again until RAS is negated and a fixed precharge time has elapsed In addition on same page accesses CAS can only be asserted at intervals of two or more clocks depending on the CAS precharge time In a SDRAM a second RAS can be asserted within two clocks of the first RAS as long as the access is to the opposite bank Once RAS 1s asserted for a given bank CAS can be asserted within two clocks after which CAS can be asserted every clock thereafter as long as the subsequent accesses are to the same row The control logic interprets transitions on the external pins as commands which are in turn used to transition the state machine Underneath table is the command truth table for a 128 Mbit SDRAM Note that the CKE input must be high for normal operation of the device In addition the CS input must be asserted in order for any of the inputs to be recognis
89. omplish that work Just simply place the data on the bit lines BL BL through the another two lines that are connected to the bit SE F080 Rev 2 0 32 bit SH 4 Page 6 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 lines When the voltages on the bit lines approach the saturated Vcc and Gnd potential the sense amplifier will automatically save the data into the storage cell as the restoring process goes Due to the fact that there is some leakage current existing on the capacitor of the DRAM cell the bit data cannot be always kept in the cell for a long time without losing voltage potential It 1s necessary that the content of the bit cell 1 kept being updated periodically We call that work as refreshing The way to refresh the bit cell is quite similar to read the data from the cell Just open all the word lines and let the sense amplifier do the restoring work on every cell 1 2 5 Precharge It is very important that the bit lines of the DRAM are kept in the potential of 1 2Vcc This is called as precharging of the DRAM Precharging the bit lines to 1 2Vcc is the most fundamental step for all the commands or operations of the DRAM Before reading or writing the bit cell the bit lines need to be precharged 1 3 Clocked Interface Because of the basic architecture of the DRAM once the processor has requested data it must wait for a certain length of time until data returns This can take some clock cycles dependin
90. ond to the numbered sequence in figures 2 6 and 2 7 5 The column address is set based on the state of address inputs A8 AO0 Address bit A12 and A13 are the bank select Address bit 10 determines whether the command is a standard read command READ or a read with auto precharge READA During read cycles SDRAMs can accept new column address every clock as long as the row 15 active 6 The column address is latched and routed through the burst counter to the column decoder Whether or not the burst counter is activated depends on the state of the burst length size entry in the mode register When the burst length is 2 4 or 8 the data output buffer shown in step 11 of figure 2 6 automatically switches to the high impedance state in the next cycle after the last burst data has been transferred When the burst length is full page and the last data has been transferred the wrap around nature of the burst counter causes the data to be repeatedly output until the burst stop BST command 15 executed 7 The address enters the column address decoder The decoder determines which one of the 512 columns is activated 8 The correct data line is activated and data retrieved from the memory array 9 Data 15 routed through the sense amplifiers and internal I O bus 10 The data enters the CAS latency control latch where it 1s latched the appropriate number of cycles based the CAS latency setting programmed into the mode register
91. possible to put the SDRAM into Self Refresh mode The important difference here is that the SH 4 BSC does not need to issue refresh commands as the SDRAM refreshes itself automatically This 15 generally used to support system power down where the SH 4 can disable the clock standby mode but the SDRAM contents are not lost It should be noted however that when the SDRAMs set to self refresh they not accessible Special should be taken that no access to SDRAM is made in cases where self refresh mode is used le Exit from standby mode via interrupt which means the exception handling routine must be in valid memory The performance of SDRAM can further be enhanced using of RAS down mode Note that this mode is only possible when area 3 only is used SDRAMs are addressed with a row and a column address Higher speed accesses can be performed within the same row because it 1s not necessary to change the column address This is the principle of RAS Down mode When it 15 enabled a row comparator within the BSC automatically checks the current row address to the requested access row address If there is a miss different row access then a standard access consisting of row column is performed However if there is a row hit same row access th an access without the row cycle is made In a typical SDRAM configuration this means a saving of 2 CKIO cycles MCR RCD 2 which translates to 4 or 6 processor cycles depending on the
92. r write cycle is generated by the processor such as in a burst write back of the primary cache one of two actions can be taken Upon decoding the incoming cycle the controller can e Reprogram the mode register to accept a burst write perform the cycle and then again reprogram the mode register to accept only single cycle writes or e Accept the burst write and generate four single write cycles to the SDRAM Although the mode register need not be reprogrammed it is necessary for the controller to generate subsequent addresses to the SDRAM In addition the controller must be prepared to increment memory addresses either in sequential fashion or conform to the interleaved subblock ordering protocol not supported by SH 4 In this case reprogramming the mode register 15 the more efficient solution A basic write operation begins by the assertion of CAS and CS along with valid address The WEZ signal is also asserted at this time A low on address bit A10 indicates a write WRIT command while a high indicates a write with auto precharge WRITA SE F080 Rev 2 0 32 bit SH 4 Page 28 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 The write operation is responsible for accepting data from the data bus and writing it to the memory array after the ACTV command has been executed Figure 2 8 15 a block diagram of a write operation The numbers shown throughout the diagram correspond to the numbered sequence explained
93. ress bus rather than the data bus The Mode Register Set command is issued to the SDRAM manually by writing to a special area H FF90XXXX when the MRS bit in the MCR 1 set to 1 The set value for the SDMR 15 encoded into the lower address bits as follows If the value to be set is X and the SDMR address 15 Y the value X 1s written in the SDRAM mode register by writing at address X Y Since for 32 bit bus AO of SDRAM 15 connected to A2 of the processor and Al of SDRAM is connected to A3 of the processor X value must be shifted two bits right before being added to Y For the SH 4 the Y value for SDRAM Area 3 is H FF940000 and in Area 2 is H FF900000 Similar procedure is possible with 64 bit bus However it 15 more simple to reference the SH 4 Hardware Manual It contains already all possible combination which could be set for SDRMR see Table 4 5 Bus Width CAS Latency Area 2 Area 3 Az 1 290004 94004 2 4008 3 H FFS4n0C0CC 4 1 00 2 S001 10 2401 10 3 H FF 001 90 40190 Table 4 5 possible SDMR settings SE F080 Rev 2 0 32 bit SH 4 Page 43 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 5 Connecting the SH 4 directly to SDRAM 5 1 Physical connection Like all memories SDRAMs require some method of specifying an address when reading writing data and control lines to co ordinate
94. s the first address and the SDRAM generates the remaining three addresses The full page option is very useful when refilling a cache after it has been flushed and also for high bandwidth graphics applications where large amounts of data are required at one time such as updating an on screen image The on chip burst counter and the mode register greatly simplify SDRAM controller logic SDRAMs also support a programmable CAS latency of either 1 2 or 3 The CAS latency of is mentioned because of historical reason Nowadays CAS latency of 2 or 3 are state of the art The CAS latency determines the number of clock cycles which elapse between the time data is requested and the time it is transferred to the data outputs The higher the number the longer it takes to retrieve the first data item However higher clock rates demand more delay Therefore a CAS latency of 3 can support faster clock rates CAS latency only applies to the first access of a data read Subsequent pipelined accesses to the same row can occur at the rate of one every clock Figure 1 3 shows the burst lengths supported and the different CAS latencies SE F080 Rev 2 0 32 bit SH 4 Page 10 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 CAS Latency CLK LI LILI LILI LI LI 1 RED Active Read Commancl Row Column Address CL out 0 out 2 aut 1 out 3 Dout 4 CL 2 out 1 out 3 outO out2 CL CAS latency EL 3 out
95. same as a standard DRAM cell structure sense amp structure etc are not covered The figure 2 1 shows a functional block diagram of a 128 Mbit Elpida SDRAM lt CLE CONTROL WEs CARE RAS 6 COM MAN DECODE BANE 71 REFRESH m MODE REGISTER COUNTER 1 MEMORY 1 DOM 4 090 2048 x 4 DATA OUTPUT REGISTER i 1 1 1 WO GATING 090 DOM MASE LOGIC 093 1 1 1 1 1 i i 1 1 1 1 READ DATA LATCH AO AT 1 ADDRESS t i cO WRITE DRIVERS 5 BAG BA 1 REGISTER DGIE DATA F INFUT 1 REGISTER COLUMN DECODER COLUMN ADDRESS COUNTER Figure 2 1 Functional Block Diagram of a 128 Mbit SDRAM from Elpida The CS input must be sampled low for either the row or column address to be latched When the processor is not driving valid address and cycle information CS should be negated so that all inputs are ignored To minimise pin count the SDRAM implements a multiplexed address bus As with a standard DRAM row address is presented to the input pins in one clock and column address two or three clocks later The time between the assertion of RAS and the assertion of CAS 15 defined as tRCD RAS to CAS delay time The address is latch
96. st instruction that should be executed on power up This allows the internal SDRAM state machine to precharge all banks then move automatically to the idle state where an MRS command can be executed Execution of either the READA or WRITA command executes the appropriate cycle along with a precharge to the same bank at the end of the operation Because the precharge operation consumes some number of cycles the READA and WRITA commands perform the precharge during the actual cycle effectively hiding some of the precharge operation latency The number of cycles required to perform a precharge is defined in the AC characteristics section of the device datasheet 2 5 Mode Register The mode register 1s unique to the SDRAM architecture and is a key feature that distinguishes it from the standard DRAM architecture The mode register contains the parameters under which the device operates The size of the mode register is equivalent to the number of address pins on the device and is written during a Mode Register Set MRS cycle which is generated whenever all the control inputs are low Valid address is driven onto A13 A0 and the mode register 15 written The mode register must be reprogrammed whenever any of the parameters change Therefore systems that require multiple burst length sizes such as those having different data and instruction cache line widths may require an MRS cycle each time the burst length changes There are two ways to deal with th
97. t following an refresh command Valid setting are 4 11 although the actual delay used 15 added to the TRC value which is set by bits 29 27 Bits 8 7 571 SZ0 Here the width of the SDRAM interface is defined These bits take priority over the setting in BCR2 For the 7750 a setting of 64 or 32bits 1s valid and for the 7751 32 bits 1s the only supported SDRAM area width Bits 6 3 AMXEXT AMX2 AMYXO The address multiplexing is controlled by these bits During the RAS cycle the upper address bits are shifted down by the number of column bits so that they appear at the portion of the address bus connected to the SDRAM During the CAS cycle no multiplexing occurs The setting of these 4 bits depends on the organisation of the SDRAM connected The SH 4 Hardware User Manual provides SDRAM multiplexing tables in the appendix or you can refer to the Address Multiplex Guide in this application note Bit 2 RFSH Refresh control This bit switches on or off the refreshing of the SDRAMs Bit 1 RMODE This bit controls the refreshing mode When this bit is set to 1 self refresh mode is entered It basically issues a SELF command which also drives the clock enable signal to the SDRAMs During this state the SDRAMs do not exist in the memory map so it is important to execute this code from a different area eg FLASH 4 2 7 PCMCIA Control Register PCR PCR has no effect upon the operation of SDRAM 4 2 8 Refres
98. tachi Ltd Technical Note Clock wiring between SH 4 and SDRAM Hitachi Ltd SH7750 SH7750S Hardware Manual V5 0 Hitachi Ltd High Speed Digital Design A Handbook of black magic Howard Johnson Martin Graham ISBN 0 13 395724 SE F080 Rev 2 0 32 bit SH 4 Page 79 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 When using this document keep the following in mind This document may wholly or partially be subject to change without notice All rights are reserved No one is permitted to reproduce or duplicate in any form the whole or part of this document without Hitachi s permission Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during the operation of the user s unit according to this document Circuitry and other examples described herein are meant only to indicate the characteristics and performance of Hitachi s semiconductor products Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples therein No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi Ltd MEDICAL APPLICATIONS Hitachi s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi s sales company Such use includes but is not limited to use in
99. tate transition timing This means all wait state controls specify an integer number of clock cycles In all cases the clock used for timing calculations 1s the bus clock or CKIO and hence the values are multiples of the CKIO period Some values are given in cycles for a particular frequency eg 66 100 MHz In the case when a specification is not available within the SDRAM datasheet for your chosen clock frequency the next highest frequency condition specification should be chosen Eg Use 100 MHz figures if you are designing with an 83 MHz bus when the SDRAM does not specify a 83 MHz test condition Most of the SDRAM datasheet parameters fall into this category In general the parameters to be met here are minimum values and hence the wait states must be increased until the parameter 1s met or exceeded 5 2 3 Auto Refresh interval timing When the SDRAM is active the task of refreshing the DRAM cells is controlled by the refresh timer within the BSC When the internal timer makes a compare match the SH 4 BSC will issue the relevant commands to perform an auto refresh How often this needs to be done needs to be calculated and the appropriate refresh controller registers must be configured 5 2 4 Clock Quality The clock speed for SDRAM 15 very fast This means a strong clock drive is required so that the clock provided is close to 50 duty and has good rise and fall times The parameters of interest here are rise amp fall times worst cas
100. tecture the 32 byte burst length 1s mirrored in the cache line length store queues and the DMAC The SDRAM commands in the following table indicates in which situations burst accesses are supported SE F080 Rev 2 0 32 bit SH 4 Page 34 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 Internal access type Cache mode SDRAM access Commands SH7750 64 Commands SH775x 1 32 bit data bit data bus bus Random read non cached single read amp M ACTV Read ReadA amp M 32 byte burst ReadA ACTV Read ReadA 32 byte burst ACTV ReadA ACTV Read ReadA DMAC single read single read ACTV ReadA amp M ACTV Read ReadA amp M Table 3 1 SH 4 SDRAM command ACTV Active command ReadA 4 times read with precharge WriteA 4 times write with precharge Read 4 times read Write 4 times write M DOM signal masking 1 used for single read ore write These accesses are always made via the cache using burst mod Note that the burst length of the SDRAM is set at startup and does not change during SH 4 operation What this means is that all SDRAM accesses are made using a burst type cycle In the case of a single read or write the wanted data 1s strobed in using the signals This means in the case of a byte write to SDRAM for example one DOM 1s active for one of the cycles only which means no other data 15 overwritten The SDRaM burst length setting when
101. ter Register RTCNT Note The password upper 8 bits of 16 bit word to access this register is B 10100101 H A5 Bits 7 0 RTCNT 7 0 This register is the actual refresh timer counter It is 8 bits wide When RTCNT RTCOR a refresh cycle request is made and RFCR 15 incremented 4 2 11 Refresh Time Constant Register RTCOR Note The password upper 8 bits of 16 bit word to access this register is B 10100101 H A5 Bits 7 0 RTCOR 7 0 This register is the 8 bit compare match value register When RTCNT RTCOR a refresh cycle request is made and RFCR 1s incremented 4 2 12 Synchronous DRAM Mode Register 2 3 SDMR2 3 The SDRAM mode register is a configuration register that physically resides within each SDRAM It controls CAS latency burst length and wrap type of the SDRAM CAS latency must be set to the same value in the MCR and specifies how many clocks after a READ data is output Burst length is the number of data frames that will be read written in each access Table 4 4 shows the burst length required by the SH 4 Depending on which device and what bus width is used a different value will need to be set SE F080 Rev 2 0 32 bit SH 4 Page 42 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 Device Configuration Burst length 5 77505 32bit bus 8 SH7750S 64bit bus SH7751 32bit bus Table 4 4 Required Burst Length Setting for SDMR Writing to mode register uses the add
102. this parameter will always be met 5 2 6 2 rcd Tred is the delay between the RAS and CAS cycle or minimum delay between ACTV and READ WRIT The setting of MCR RCD controls this value Hence the equation to meet 15 SDRAM SH 4 Tred lt tcyc MCR RCD 0 2 6 3 Trp This is the minimum row precharge time It specifies the minimum delay between a PRE command and the next ACTV This value will need to be considered for the following cases End of auto precharge read write where an implicit precharge 15 executed and in the case of the PRE command being output Eg In the case of a row change during RAS Down access In both cases the setting of MCR TPC is key Therefore there 15 one equation correct for both situations SDRAM SH 4 Trp lt MCR TPC 5 2 6 4 Tras 1 Tras 1s one of the few parameters that specifies a minimum and a maximum time In the case of the minimum value it gives the minimum time between ACTV and the next PRE This value will be governed by how quickly a full read or write with ROW and COLUMN address can be executed following the previous one Since the time between consecutive full read writes 1s RAS CAS delay min 2 CAS latency min 2 Burst length min 4 8 CKIO cycles and typical Tras requirement is 50ns even at CKIO 100 MHz this parameter is always met In the case of the maximum value of Tras this defines the maximum time a row can be active without a precharge When R
103. tion The following table 2 1 lists the SDRAM commands SE F080 Rev 2 0 32 bit SH 4 Page 15 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 CKE AQ Command symbol n 1n CS RAS CAS WE ATZAT13 A10 to A11 lanore command DESL H x H x x x x operation x H H H x x Burst stop in full page BST H x L H H L x x Column address and read command READ H x H L H Vv L V Read with auto precharae READ A H x L H L H V H V Column address and write command WRIT H x L H L L V L V Write with auto pre charge WRIT A H x L H L L 1 H V Row address strobe and bank active H x L L H H Frecharge select bank PRE H x L L H L L x Frecharge all bank FALL H L L H L x H x Refresh REF SELF H V L L L H s x x Mode register set MRS H L L L L V Note H L V x V orV V Valid address input Table 2 1 SDRAM Command List DESL DESL is the default command executed by the state machine whenever CS is sampled high The state of the external pins is ignored Execution of this command causes the state machine to remain in its current state NOP No Operation is similar to DESL except that CS 1s asserted causing the control logic to sample each of the external pins If all the control signals are negated as shown in table 2 1 a NOP command is decoded The command has no effect on the internal operation of the state machine and any cycles in progress are allowed to continue BST The BST command c
104. tion of CKE from low to high can occur at any time leaving the refresh counter in an undefined state Therefore when exiting from low power mode 4096 cycles of auto refresh REF are required to update the refresh counter PWRDN The PWRDN command can be executed when the state machine is in the IDLE state causing the device to suspend all operation and enter power down mode The PWRDN command is executed under one of two conditions If the CKE signal switches from high to low and CS is high PWRDN is executed If the signal switches from high to low and CS 15 low other inputs are also sampled and must be in the correct states as shown in table 2 2 in order for PWRDN to execute While in power down mode all input circuits to the array are high impedance No self refresh cycles are performed while in power down mode PWRDNX The device can remain in power down mode for an indefinite amount of time There are two conditions under which the PWRDNX command is executed both require a transition from low to high on the CKE signal Sampling the CS signal high during the transition causes execution of the PWRDNX command If the CS signal is sampled low during the CKE transition additional inputs must be in the correct state as shown table 2 2 order for the PWRDNX command to execute Execution of the PWRDNX command causes the machine to return to the IDLE state MRS The MRS command is executed on power up or whene
105. ursts cannot be executed using the READA command Execution of the READA command allows the active bank to be precharged prior to completion of the read operation Overlapping the actual access with the precharge operation helps hide the latency required while the data flows through the sense amplifiers to the output pins and increases the overall throughput for that bank Unlike the READ command the READA command is not terminated by execution of the WRIT WRITA PRE or PALL commands while the read with auto precharge operation is in progress If the CKE signal is driven low during execution of the READA command the data 1s held and continues to be output until CKE is driven high WRIT The write command specifies the column address corresponding to the row address executed by the previous ACTV command Write cycles can be either single transfer or burst transfer Multiple back to back burst accesses to different rows of the same bank are better facilitated using the WRITA command If the signal 15 driven low during execution of the WRIT command the data 1s held in the input latches and all input pins are ignored until 15 driven high Execution of either a READ or READA command while the write operation is in progress causes the write operation to be terminated and the read operation to begin In addition execution of either a PRE or PALL command while the write operation is in progress causes the write operation to be terminated and
106. ver the controller needs to change the operating parameters of the device The MRS command initialises the mode register The mode register maintains the operating characteristics of the device such as burst length size CAS latency write mode etc The mode register is defined at the beginning of the command operation figure 2 3 2 4 Precharge Operations Precharge operations can be performed on both read and write cycles The operation in turns off the word line in the selected array to store full level data in the memory cells Then it SE F080 Rev 2 0 32 bit SH 4 Page 20 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 precharges the bit lines to VDD 2 by shorting them together in preparation for the next active cycle There are three precharge options Precharge a single bank Precharge all banks simultaneously Execute a read or write command with auto precharge Execution of the PRE command precharges a single bank as determined by the state of the highest order address bit When precharging a single bank the state of the second highest order address bit must be low The precharged bank 1s selected via the bank select bits A12 and 13 Execution of the PALL command precharges all banks simultaneously For this command the state of the second highest order address bit must be high The state of the highest order address bit is irrelevant since all banks are to be precharged A PALL command is the fir
107. y type Ie Area 3 will be SDRAM Initialise BCR2 to define memory widths Initialise WCR1 2 amp 3 to define idle cycles CAS and also wait states for non SDRAM areas Initialise the refresh controller RTCSR RFCR RTCNT amp RTCOR Note that refreshing will not take place yet because it has not been enabled in the MCR Initialise the MCR with the wait state settings as derived above Note that bits 30 MRS 2 RFSH amp 2 RMODE should be set to 0 to disable mode register set 1 e enable PALL and refreshing Next the PALL precharge all command should be sent to the SDRAM in area 3 This is done by writing a byte to address H 940000 SDMR value shifted left by 2 bits Eight REF auto refresh commands should now be sent to the SDRAM This is done by reducing the refresh interval to a minimum and waiting until the refresh count register RFCR is greater than 7 The refresh control bit MCR RFSH must be set to one prior to this to enable refreshing Next the MRS mode register set command should be sent to the SDRAM This initialises the internal configuration register SDMR of each of the SDRAMs connected To do this bit MCR MRS is set to 1 followed by a write to a special address according to CAS latency bus width and chip select area In this case the CAS latency 15 2 the bus width 15 32 bits and the chip select area 1s 3 Hence a byte 1s written to H FF94008C Note that the actual value written does not matter it
108. you consider any reflected waves as these must also meet each other at the T point on the way back to the SH 4 The diagram below shows an example of this topology SDRAM 1 SDRAM 2 Length 1 Yo 90ohms Buffer Length 1 Zo 90ohms th 1 a eng 3 Zo 90ohms Length 14 Zo 30ohms CKIO Send point Figure 5 6 Example CKIO layout 5 3 3 2 CKIO load The CKIO pin is tested with a load of 30 pF The guaranteed maximum rise and fall time over the complete operating specification for this condition is 4ns The actual figure will be better and with a smaller CKIO load capacitance and good layout 1 2ns 15 achievable It is therefore recommended that the CKIO loading should be very carefully considered at the beginning of the design and if necessary buffering should be included In general 3 loads with good PCB tracking can give a rise fall time of around 2ns however to achieve fast rise and fall times with large CKIO loads it will be necessary to include CKIO buffering When the skew must be kept to a minimum it 18 important to use a PLL phase locked loop buffer An example connection 15 show below SE F080 Rev 2 0 32 bit SH 4 Page 66 http www hitachi eu com HITACHI EUROPE LTD Version App 92 2 0 m NE MN c Phase VCO CKIO SDRAM SH4 Notes Length 15 90 90 90 300hms ZO line impedance Try to keep load of each branch similar Figure 5 7 Buffering of

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