SuperH Family E10A-USB Emulator Additional Document for Users
Contents
1. N w NC 31 RESETP Output User reset GND 32 GND NC 333 GND Output GND 34 GND gt a D q TCK Input 35 NC 18 GND 36 GND Notes 1 Input to or output from the user system 2 The slash means that the signal is active low 3 The emulator monitors the GND signal of the user system and detects whether or not the user system is connected 4 The ASEMDO pin must be 0 when the emulator is connected and 1 when the emulator is not connected respectively 1 When the emulator is used ASEMDO 0 2 When the emulator is not used ASEMDO 1 To allow the ASEMDO pin to be GND by connecting the user system interface cable connect pin 22 directly to the ASEMDO pin Do not ground the pin Edge of the board H UDI port connector top view connected to the connector au 0202020202020902 900000000 Pin 1 mark M2 6 x 0 45 e 21 59 37 61 43 51 GB Pattern inhibited area H UDI port connector top view H UDI port connector front view Figure 1 1 Pin Assignments of the H UDI Port Connector 36 Pins Note The signal names are standard for the SH7700 series MPU pins For the MPU pin names and recommended circuits contact Renesas Technology Corp via the sales office RENESAS Input Pin No Signal Output 1 TCK Input 2 TRST Input 3 TDO Outpu 4 ASEBRKAK_ 2 Outpu 5 TMS Input 6 TDI Input 7 RESETP 2 Outpu User reset 8 N C2. Internal I O break condition Breaks when the internal I O is accessed LDTLB instruction break condition Breaks when the LDTLB instruction is executed Count Breaks when the conditions set are satisfied the specified number of times Note This condition cannot be used for the MPU that does not incorporate the X Y RAM 17 RENESAS Note When X Y RAM is accessed from the PO space the I bus must be selected and when accessed from the P2 space the L bus must be selected When cache fill cycle is acquired the I bus must be selected Table 2 3 lists the combinations of conditions that can be set under Break Condition 1 2 3 Table 2 3 Dialog Boxes for Setting Break Conditions Type Bus Address Data State Bus Bus ASID Condition Count Internal LDTLB Condition Condition Condition Bus Condition I O Instruction Dialog Box Address Data ASID Status Count Break Break Break Condition 1 O O O O O X X dialog box Break Condition 2 O X O O X X X dialog box Break Condition 3 X X X X xX O O dialog box Notes 1 These functions cannot be used for the MPU that does not incorporate the MMU in SH 3 2 O Can be setin the dialog box X Cannot be set in the dialog box 3 For Break Condition 2 X bus and Y bus conditions cannot be specified 2 2 2 Trace Functions The emulator supports the trace functions listed in table 2 4 Table 2 4 Trace Functions Function Internal Trace AUD Trace Branch tr
3. 1 2 Connecting the Emulator with the User System To connect the E10A USB emulator hereinafter referred to as the emulator the H UDI port connector must be installed on the user system to connect the user system interface cable When designing the user system refer to the recommended circuit between the H UDI port connector and the MPU In addition read the E10A USB emulator user s manual and hardware manual for the related device Table 1 2 shows the type number of the emulator the corresponding connector type and the use of AUD function Table 1 2 Type Number AUD Function and Connector Type Type Number Connector AUD Function HS0005KCU02H 36 pin connector Available HS0005KCU01H HS0005KCU02H 14 pin connector Not available The H UDI port connector has the 36 pin and 14 pin types as described below Use them according to the purpose of the usage 1 36 pin type with AUD function The AUD trace function is supported A large amount of trace information can be acquired in realtime The window trace function is also supported for acquiring memory access in the specified range memory access address or memory access data by tracing 2 14 pin type without AUD function The AUD trace function cannot be used because only the H UDI function is supported For tracing only the internal trace function is supported Since the 14 pin type connector is smaller than the 36 pin type 1 2 5 the area where the connector is installed on the u
4. the L bus must be selected When a cache fill cycle is acquired I bus must be selected 2 Address setting when X Y bus is selected To trace both the X Y bus when the X Y bus is accessed at the same time the X bus condition must be set in channel A and the Y bus condition must be set in channel B 22 RENESAS c Software Trace Function Note This function can be supported with SHC C compiler manufactured by Renesas Technology Corp including OEM and bundle products V7 0 or later When a specific instruction is executed the PC value at execution and the contents of one general register are acquired by trace Describe the Trace x function x is a variable name to be compiled and linked beforehand For details refer to the SHC manual When the load module is downloaded on the target system and is executed while a software trace function is valid the PC value that has executed the Trace x function the general register value for x and the source lines are displayed To activate the software trace function select the Software trace check box in the AUD function group box of the Trace mode page Notes on AUD Trace 1 When the trace display is performed during user program execution the mnemonics operands or source is not displayed The AUD trace function outputs the differences between newly output branch source addresses and previously output branch source addresses The window trace function outputs the di
5. Condition 2 Break Condition 2 gt 1 Measurement is started from the satisfaction of the condition set in Break Condition 2 to the satisfaction of the condition set in Break Condition 1 RENESAS 27 Perfomance Analysis Condition Mode Nomai Bek o Channel 1 Elapsed time z Channel 2 Number of execution states tsi Channel 3 Branch instruction counts 0 Channel 4 Disabled O Figure 2 4 Performance Analysis Dialog Box b Measurement range One of the following ranges can be specified This depends on the item selected for Mode in the Performance Analysis dialog box 1 From the start to the end of the user program execution When Normal Break is selected for Mode 2 From the satisfaction of the condition set in Break Condition 1 to the satisfaction of the condition set in Break Condition 2 When Break condition 1 gt 2 is selected for Mode 3 From the satisfaction of the condition set in Break Condition 2 to the satisfaction of the condition set in Break Condition 1 When Break condition 2 gt 1 is selected for Mode In the second and third ranges PA 1 start point and PA 1 end point are displayed on the Action part in the Break condition sheet of the Eventpoint window For measurement tolerance e The measured value includes tolerance e Tolerance will be generated before or after a break For details see table 2 9 28 RENESAS Notes 1 When the second and third ranges are spec
6. T 9 GND 11 UVCC Outpu 10 12 GND and 13 14 GND 3 Output Notes 1 Input to or output from the user system 2 The slash means that the signal is active low 3 The emulator monitors the GND signal of the user system and detects whether or not the user system is connected 4 The ASEMDO pin must be 0 when the emulator is connected and 1 when the emulator is not connected respectively 1 When the emulator is used ASEMDO 0 2 When the emulator is not used ASEMDO 1 To allow the ASEMDO pin to be GND by connecting the user system interface cable connect pin 9 directly to the ASEMDO pin Do not ground the pin Pin 1 mark H UDI port connector top view H UDI port connector 23 0 6 x 2 54 15 24 top view ies ILL Pin 1 mark Unit mm Figure 1 2 Pin Assignments of the H UDI Port Connector 14 Pins Note The signal names are standard for the SH7700 series MPU pins For the MPU pin names and recommended circuits contact Renesas Technology Corp via the sales office RENESAS 15 Recommended Circuit between the H UDI Port Connector and the MPU 1 5 1 Recommended Circuit 36 Pin Type Connection between the H UDI and AUD port connectors and the MPU in each device differs depending on the internal circuit of MPU in use The following shows examples however for pull up pull down and required logic ICs contact Renesas Technology Corp via the sales office Figure 1 3 sh
7. by refreshing the Memory window etc after Go execution However no break will occur at this address When the program halts with the break condition the mark disappears 2 2 5 Notes on Setting the Break Condition Dialog Box and the BREAKCONDITION_ SET Command When Go to cursor Step In Step Over or Step Out is selected the settings of Break Condition 2 are disabled Break Condition 2 is disabled when an instruction to which a BREAKPOINT has been set is executed Accordingly do not seta BREAKPOINT to an instruction which satisfies Break Condition 2 When a Break Condition is satisfied emulation may stop after two or more instructions have been executed If a PC break address condition is set to the slot instruction after a delayed branch instruction user program execution cannot be terminated before the slot instruction execution execution stops before the branch destination instruction For the MPU that supports the performance function Break Condition 1 2 is used as the measurement range in the performance measurement function when PA 1 start point and PA 1 end point are displayed on the Action part in the Break condition sheet of the Eventpoint window This applies when the Break Condition is displayed with the BREAKCONDITION_DISPLAY command in the command line function In this case a break does not occur when Break Condition 1 2 is satisfied A break will not occur with the execution counts specified
8. device differs depending on the internal circuit of the MPU in use The following shows examples however for pull up pull down and required logic ICs contact Renesas Technology Corp via the sales office Figure 1 5 shows a recommended circuit for connection between the H UDI and AUD port connectors 14 pins and the MPU when the emulator is in use Notes 1 Sections surrounded with dashed lines mean examples They may require logic ICs 2 Do not connect anything to the N C pins of the H UDI port connector 3 The ASEMD0 pin must be 0 when the emulator is connected and 1 when the emulator is not connected respectively 1 When the emulator is used ASEMDO 0 2 When the emulator is not used ASEMDO 1 Figure 1 5 shows an example of a circuit that allows the ASEMD0 pin to be GND 0 whenever the emulator is connected by using the user system interface cable When the ASEMD0 pin is changed by switches etc ground pin 9 Do not connect this pin to the ASEMD0 pin When a network resistance is used for pull up it may be affected by a noise Separate TCK from other resistances The pattern between the H UDI port connector and the MPU must be as short as possible Do not connect the signal lines to other components on the board For the pin processing in cases where the emulator is not used refer to the hardware manual of the MPU The signal names in figures are standard they may differ depending on the MPU in u
9. in the Trace type group box of the Trace mode page This function traces and displays the branch instructions The branch source address and branch destination address for the eight latest branch instructions are displayed See figure 2 1 Trace mode Page Notes 1 If an interrupt is generated at the program execution start or end including a step operation the emulator address may be acquired In such a case the following message will be displayed Ignore this address because it is not a user program address 4k EML 2 If acompletion type exception occurs during exception branch acquisition the next address to the address in which an exception occurs is acquired 3 Trace information cannot be acquired for the following branch instructions e The BF and BT instructions whose displacement value is 0 e Branch to H A0000000 by reset 4 The internal trace acquisition is not available when User is selected in the UBC mode list box of the Configuration dialog box In this case close the Trace window 2 2 3 Notes on Using the JTAG H UDI Clock TCK and AUD Clock AUDCK Set the JTAG clock TCK frequency to lower than the frequency of the peripheral module clock CKP Set the AUD clock AUDCK frequency to 1 MHz or higher and 50 MHz or lower If the frequency is outside the ranges the emulator will not operate normally 2 2 4 Notes on Setting the Breakpoint Dialog Box 1 When an odd address is set the next lo
10. EAKPOINT is equal to a branch instruction In some DSP repeat loops branch instructions cannot be set For these cases do not set BREAKPOINTS Refer to the hardware manual of the target MPU for details For the MPU that incorporates the MMU in SH 3 when the Normal option is selected in the Memory area group box in the General page of the Configuration dialog box a BREAKPOINT is set to a physical address or a virtual address according to the MMU status during command input when the VPMAP_SET command setting is disabled The ASID value of the PTEH register during command input is used When VPMAP_SET command setting is enabled a BREAKPOINT is set to a physical address into which address translation is made according to the VP_MAP table However for addresses out of the range of the VP_MAP table the address to which a BREAKPOINT is set depends on the MMU status during command input Even when the VP_MAP table is modified after BREAKPOINT setting the address translated when the BREAKPOINT is set valid For the MPU that incorporates the MMU in SH 3 when the Physical option is selected in the Memory area group box in the General page of the Configuration dialog box a BREAKPOINT is set to a physical address A BREAKPOINT is set after disabling the MMU upon program execution After setting the MMU is returned to the original state When a break occurs at the corresponding virtual address the cause of termination displayed in the status
11. Electronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics C 7 D Po on lt D D tENESAS SuperH Family E10A USB Emulator Additional Document for User s Manual Supplementary Information on Using the SH 3 core _custom_SoC Renesas Microcomputer Development Environment System SuperH Family E10A USB for SH 3 core _custom_SoC HS0770KCU01HE Renesas Electronics Rev 1 00 2004 12 Keep safety first in your circuit designs Renesas Technology Corp puts the maximum effort into making semiconductor products better and more reliable but there is always the possibility that trouble may occur with them Trouble with semiconductors may lead to personal injury fire or property damage Remember to give due consideration to safety when making your circuit designs with appropriate measures such as i placement of substitutive auxiliary circuits ii use of nonflammable material or iii prevention against any malfunction or mishap Notes regarding these materials These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp product best suited to the customer s applicat
12. To our customers Old Company Name in Catalogs and Other Documents On April 1 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 1 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http Awww renesas com inquiry 2CENESAS 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is gra
13. X Y RAM and U RAM areas is counted more than the actual number of cycles and counts Branch count The counter value is incremented by 2 This means that two cycles are valid for one branch 31 RENESAS Notes 1 In the non realtime trace mode of the AUD trace normal counting cannot be 2 performed because the generation state of the stall or the execution cycle is changed 2 Since the clock source of the counter is the CPU clock counting also stops when the clock halts in the sleep mode Displaying the measured result The measured result is displayed in the Performance Analysis window or the PERFORMANCE_ANALYSIS command with hexadecimal 32 bits Note Ifa performance counter overflows as a result of measurement will be 3 32 displayed Initializing the measured result To initialize the measured result select Initialize from the popup menu in the Performance Analysis window or specify INIT with the PERFORMANCE_ANALYSIS command RENESAS SuperH Family E10A USB Emulator Additional Document for User s Manual Supplementary Information on Using the SH 3 core custom _SoC Publication Date Rev 1 00 December 24 2004 Published by Sales Strategic Planning Div Renesas Technology Corp Edited by Technical Documentation amp Information Department Renesas Kodaira Semiconductor Co Ltd 2004 Renesas Technology Corp All rights reserved Printed in Japan Renesas Tech
14. ace Supported eight branches Supported Range memory access trace Not supported Supported Software trace Not supported Supported 18 RENESAS Table 2 5 shows the type numbers that the AUD function can be used Table 2 5 Type Number and AUD Function Type Number AUD Function HS0005KCU01H Not supported HSO005KCU02H Supported AUD Trace Functions This function is operational when the AUD pin of the device is connected to the emulator Table 2 6 shows the AUD trace acquisition mode that can be set in each trace function Note that the AUD trace acquisition mode cannot be used for the MPU that does not incorporate the AUD function Table 2 6 AUD Trace Acquisition Mode Type Mode Description Continuous Realtime trace When the next branch occurs while the trace information is trace occurs being output all the information may not be output The user program can be executed in realtime but some trace information will be lost Non realtime trace When the next branch occurs while the trace information is being output the CPU stops operations until the information is output The user program is not executed in realtime Trace buffer Trace continue This function overwrites the latest trace information to store full the oldest trace information Trace stop After the trace buffer becomes full the trace information is no longer acquired The user program is continuously executed 19 RENESAS To set the AUD trace acquisition m
15. and algorithms please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products Renesas Technology Corp assumes no responsibility for any damage liability or other loss resulting from the information contained herein Renesas Technology Corp semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake Please contact Renesas Technology Corp or an authorized Renesas Technology Corp product distributor when considering the use of a product contained herein for any specific purposes such as apparatus or systems for transportation vehicular medical aerospace nuclear or undersea repeater use 6 The prior written approval of Renesas Technology Corp is necessary to reprint or reproduce in whole or in part these materials 7 If these products or technologies are subject to the Japanese export control restrictions they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination Any diversion or reexport contrary to the export control laws and regulations of Japan and or the country of destination is prohibited Please contact Renesas Technology Corp for further details on these materials or the products contained therein Contents Section 1 Connecting the Emulator with the User System e
16. ator is activated Do not use the activation method described in step 12 for section 3 11 in the Debugger Part of the SuperH Family E10A USB Emulator User s Manual 2 2 1 Break Condition Functions The emulator can set three types of conditions under Break Condition 1 2 3 Table 2 2 lists these conditions of Break Condition Table 2 2 Types of Break Conditions Break Condition Type Description Address bus condition Address Breaks when the address bus value or the program counter value matches the specified value Data bus condition Data Breaks when the data bus value matches the specified value Byte word or longword can be specified as the access data size X Bus or Y Bus condition Address Breaks when the X Bus or Y Bus address bus or data bus and Data matches the specified value Bus state condition There are two bus state condition settings Bus State Read Write condition Breaks when the RD or RDWR signal level matches the specified condition Bus state condition Breaks when the operating state in a bus cycle matches the specified condition Types of buses that can be specified are listed below e L bus CPU ALL Indicates an instruction fetch and data access including a hit to the cache memory e L bus CPU Data Indicates a data access by the CPU including a hit to the cache memory e bus CPU DMA Indicates a CPU cycle when the cache memory is not hit and a data access by the DMA
17. bar and the Output window is ILLEGAL INSTRUCTION not BREAKPOINT For the MPU that incorporates the MMU in SH 3 when the Virtual option is selected in the Memory area group box in the General page of the Configuration dialog box a BREAKPOINT is set to a virtual address A BREAKPOINT is set after enabling the MMU upon program execution After setting the MMU is returned to the original state When an ASID value is specified the BREAKPOINT is set to the virtual address corresponding to the ASID value The emulator sets the BREAKPOINT after rewriting the ASID value to the specified value and returns the ASID value to its original value after setting When no ASID value is specified the BREAKPOINT is set to a virtual address corresponding to the ASID value at command input For the MPU that incorporates the MMU in SH 3 an address physical address to which a BREAKPOINT is set is determined when the BREAKPOINT is set Accordingly even if the VP_MAP table is modified after BREAKPOINT setting the BREAKPOINT address remains unchanged When a BREAKPOINT is satisfied with the modified address in the VP_MAP 25 7 ENESAS 13 table the cause of termination displayed in the status bar and the Output window is ILLEGAL INSTRUCTION not BREAKPOINT If an address of a BREAKPOINT cannot be correctly set in the ROM or flash memory area a mark will be displayed in the BP area of the address on the Source or Disassembly window
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20. e general registers and part of the control registers as shown in table 2 1 The initial values of the actual SH 3 core _custom_SoC registers are undefined when the emulator is not connected When the emulator is initiated from the workspace a value to be entered is saved in a session Table 2 1 Register Initial Values at Emulator Link Up Register Emulator at Link Up RO to R14 H 00000000 R15 SP H A0000000 RO_BANK to R7_BANK H 00000000 PC H A0000000 SR H 700000F0 GBR H 00000000 VBR H 00000000 MACH H 00000000 MACL H 00000000 PR H 00000000 SPC H 00000000 SSR H 000000F0 RS H 00000000 RE H 00000000 MOD H 00000000 AOG A1G H 00000000 AO A1 H 00000000 X0 X1 H 00000000 Yo Y1 H 00000000 Mo M1 H 00000000 DSR H 00000000 Note These registers are displayed on the MPU that incorporates the DSP in SH 3 2 The emulator uses the H UDI do not access the H UDI 13 RENESAS 3 Low Power States Sleep Software Standby and Module Standby For low power consumption there are sleep software standby and module standby states When the emulator is used only the sleep state can be cleared with either the normal clearing function or with the STOP button and a break will occur Notes 1 The memory must not be accessed or modified in sleep state 2 Do not modify the register value to enter the low power states in the IO window or Memory window it should be modif
21. ee 1 1 1 Components of the Emulator eee cece cceeeeeeeeeeeeeeeeeeeseseaecaecaecaecsaeeeseseeeseeeeseenas 1 1 2 Connecting the Emulator with the User System eesecssecsee cesses seeeeaeesnereneeees 2 1 3 Installing the H UDI Port Connector on the User System 00 eee eee eeeeeeeereeeeeeeeeees 3 1 4 Pin Assignments of the H UDI Port Connector oo eee eecceeeceseceecssecseesseeceeeaeeeneeees 3 1 5 Recommended Circuit between the H UDI Port Connector and the MPU ee 6 1 5 1 Recommended Circuit 36 Pin Type eee eeceeecesecesecssecseeceeeseeeeeeeseeeeeaees 6 1 5 2 Recommended Circuit 14 Pin Type eee ee ceeecesecssecseeceeeceeeeeeeeeenseeeseeaees 9 Section 2 Software Specifications when Using the SH 3 core _ ISU COTE SOG a eadiead seats eae E E 13 2 1 Differences between the SH 3 core _custom_SoC and the Emulator ccceeeeeeeeee 13 2 2 Specific Functions for the Emulator when Using the SH 3 core _custom_SoC 17 221 Break Condition PUNCH ONS si sccscccsssessceccessssesvecivensseestevstectessaterscessates esteuasaeebvaesbes 17 2 2 2 APACE FUNCHONS ssrin saute E E EEEE E EEE e EEEE K EEEE 18 2 2 3 Notes on Using the JTAG H UDI Clock TCK and AUD Clock AUDCK 24 2 2 4 Notes on Setting the Breakpoint Dialog BOX sssesssssesssreessereereserrrerrsrreresreeresen 24 2 2 5 Notes on Setting the Break Condition Dialog Box and the BREAKCONDITION_ SET Command 2 0 0 cceecceeeseeeeeeceseeeeeseeeeeen
22. ereees 26 2 2 6 Note on Setting the UBC_MODE Command eee eeeeeecceeneeceeeceeneecneeeeneeeens 26 2 2 7 Performance Measurement Function eseesceceeeceseeceeeeeenceceeeeeenaeceeeeeneeenees 27 RENESAS RENESAS Section 1 Connecting the Emulator with the User System 1 1 Components of the Emulator The E10A USB emulator supports the SH 3 core _custom_SoC Table 1 1 lists the components of the emulator Table 1 1 Components of the Emulator Classi Quan fication Component Appearance tity Remarks 1 HSO005KCU01H Depth 65 0 mm Width 97 0 mm Height 20 0 mm Mass 72 9 g or HSO005KCU02H Depth 65 0 mm Width 97 0 mm Height 20 0 mm Mass 73 7 g Hard Emulator box ware User system interface 9 1 14 pin type cable Length 20 cm Mass 33 1 g User system interface pg g1 36 pin type cable oo Length 20 cm Mass 49 2 g only for HSOOO5KCU02H USB cable 1 Length 150 cm Mass 50 6 g Soft E10A USB emulator 1 HSO005KCU01SR ware setup program CSD SuperH Family HS0005KCU01HJ E10A USB Emulator HS0005KCU01HE User s Manual Supplementary HS0770KCU01HJ Information on Using HS0770KCU01HE the SH 3 core _ custom_SoC and Test program manual HS0005TM01HJ and for HSOOO05KCU01H HS0005TM01HE and HS0005KCU02H provided on a CD R Note Additional document for the MPUs supported by the emulator is included Check the target MPU and refer to its additional document RENESAS
23. fferences between newly output addresses and previously output addresses If the previous branch source address is the same as the upper 16 bits the lower 16 bits are output If it matches the upper 24 bits the lower 8 bits are output If it matches the upper 28 bits the lower 4 bits are output The emulator regenerates the 32 bit address from these differences and displays it in the Trace window If the emulator cannot display the 32 bit address it displays the difference from the previously displayed 32 bit address 3 If the 32 bit address cannot be displayed the source line is not displayed In the emulator when multiple loops are performed to reduce the number of AUD trace displays only the IP counts up In the emulator the maximum number of trace displays is 65534 lines 32767 branches However the maximum number of trace displays differs according to the AUD trace information to be output Therefore the above pointers cannot be always acquired The AUD trace acquisition is not available when User is selected in the UBC mode list box of the Configuration dialog box In this case close the Trace window Do not use the AUD full trace mode for the VIO function Ifacompletion type exception occurs during exception branch acquisition the next address to the address in which an exception occurs is acquired 23 RENESAS Internal Trace Function This function is activated by selecting the Internal trace radio button
24. ied in the user program 4 Reset Signals The reset signals are only valid during emulation started with clicking the GO or STEP type button If these signals are enabled on the user system in command input wait state they are not sent to the MPU Note Do not break the user program when the reset signal is being low A TIMEOUT error will occur 5 Direct Memory Access Controller DMAC The DMAC operates even when the emulator is used When a data transfer request is generated the DMAC executes DMA transfer 6 Memory Access during User Program Execution When a memory is accessed from the memory window etc during user program execution the user program is resumed after it has stopped in the emulator to access the memory Therefore realtime emulation cannot be performed The stopping time of the user program is as follows Environment Host computer 800 MHz Pentium HD JTAG clock 10 MHz TCK clock When a one byte memory is read from the command line window the stopping time will be about 45 ms Note that however the time differs depending on the MPU because it is the reference value 7 Memory Access during User Program Break The emulator can download the program for the flash memory area refer to section 6 22 Download Function to the Flash Memory Area in the Debugger Part of the SuperH Family E10A USB Emulator User s Manual Other memory write operations are enabled for the RAM area Therefore an operation such as memor
25. ified execute the user program after the measurement start condition is set to Break Condition 1 or Break Condition 2 and the measurement end condition to Break Condition 2 or Break Condition 1 2 Step operation is not possible when Break condition 1 gt 2 or Break condition 2 gt 1 is selected for the PERFORMANCE_SET command or in Mode of the Performance Analysis dialog box 3 When Break condition 1 gt 2 or Break condition 2 gt 1 is selected in Mode of the Performance Analysis dialog box specify one or more items for measurement When there is no item the error message Measurement item does not have specification Please set up a measurement item will be displayed When no item is specified for the PERFORMANCE_SET command the settings of Break condition 1 gt 2 or Break condition 2 gt 1 will be an error c Measurement item Items are measured with Channel to 4 in the Performance Analysis dialog box Maximum four conditions can be specified at the same time Table 2 8 shows the measurement items Options in table 2 8 are parameters for lt mode gt of the PERFORMANCE_SET command They are displayed for CONDITION in the Performance Analysis window 29 2tENESAS Table 2 8 Measurement Item Selected Name Option Disabled None Elapsed time AC Number of execution states VS Branch instruction counts BT Number of execution instructions DSP instruction execution counts DI Devices incorp
26. ill occur if the TLB exception handler does not operate correctly When TLB miss exception is disable is selected the program does not jump to the TLB exception handler even if a TLB exception occurs Therefore if the TLB exception handler does not operate correctly a Communication Timeout error will not occur but the memory contents may not be correctly displayed Loading Sessions e Information in JTAG clock of the Configuration dialog box cannot be recovered by loading sessions Thus the TCK value will be 0 312 MHz IO Window When the SH 3 core _custom_SoC is used no I O register file is provided for accessing the internal I O registers in the IO window To obtain the I O register file contact Renesas Technology Corp via the sales office e Display and modification Do not change values of the User Break Controller because it is used by the emulator when EML is specified in the UBC mode list box in the Configuration dialog box e Do not change the value of the frequency change register in the IO window or Memory window it must be changed in the user program 15 RENESAS e Verify In the IO window the verify function of the input value is disabled 14 Illegal Instructions If illegal instructions are executed by STEP type commands the emulator cannot go to the next program counter ztENESAS 2 2 Specific Functions for the Emulator when Using the SH 3 core _custom_SoC A reset must be input when the emul
27. ion they do not convey any license under any intellectual property rights or any other rights belonging to Renesas Technology Corp or a third party Renesas Technology Corp assumes no responsibility for any damage or infringement of any third party s rights originating in the use of any product data diagrams charts programs algorithms or circuit application examples contained in these materials All information contained in these materials including product data diagrams charts programs and algorithms represents information on products at the time of publication of these materials and are subject to change by Renesas Technology Corp without notice due to product improvements or other reasons It is therefore recommended that customers contact Renesas Technology Corp or an authorized Renesas Technology Corp product distributor for the latest product information before purchasing a product listed herein The information described here may contain technical inaccuracies or typographical errors Renesas Technology Corp assumes no responsibility for any damage liability or other loss rising from these inaccuracies or errors Please also pay attention to information published by Renesas Technology Corp by various means including the Renesas Technology Corp Semiconductor home page http www renesas com When using any or all of the information contained in these materials including product data diagrams charts programs
28. ki shi Kanagawa 211 8668 Japan REJ10B0165 0100
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30. nted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document
31. ode click the Trace window with the right mouse button and select Setting from the pop up menu to display the Acquisition dialog box The AUD trace acquisition mode can be set in the AUD mode1 or AUD mode2 group box in the Trace mode page of the Acquisition dialog box Acquisition Trace mode Window trace AUD Branch trace Trace type AUD C Internal trace AUD function V Branch trace IV Window trace V Channel A I Channel B Software trace AUD mode AUD mode Realtime trace Non realtime trace AUD mode2 Trace continue Trace stop AUD trace display range Start pointer D 255 End pointer po ome Figure 2 1 Trace mode Page When the AUD trace function is used select the AUD function radio button in the Trace type group box of the Trace mode page 20 RENESAS a Branch Trace Function The branch source and destination addresses and their source lines are displayed Branch trace can be acquired by selecting the Branch trace check box in the AUD function group box of the Trace mode page The branch type can be selected in the AUD Branch trace page Acquisition Trace mode Window trace AUD Branch trace V Acquire subroutine branch instruction trace V Acquire exception branch instruction trace oree Figure 2 2 AUD Branch trace Page b Window Trace Function Memory access in the specified
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33. on the execution of the multi step instruction 2 2 6 Note on Setting the UBC_MODE Command In the Configuration dialog box if User is set while the UBC mode list box has been set the STEP type commands that use Break Condition 2 for implementation cannot be used 26 RENESAS 2 2 7 Performance Measurement Function The emulator supports the performance measurement function However the performance measurement function cannot be used in some MPUs 1 Setting the performance measurement conditions To set the performance measurement conditions use the Performance Analysis dialog box and the PERFORMANCE_SET command When any line on the Performance Analysis window is clicked with the right mouse button the popup menu is displayed and the Performance Analysis dialog box is displayed by selecting Setting Note For the command line syntax refer to the online help a Specifying the measurement start end conditions The measurement start end conditions are specified in the Mode drop down list box in the Performance Analysis dialog box Three conditions can be set as shown in table 2 7 Table 2 7 Conditions Specified in Mode Item Description Normal break Measurement is started by executing a program and ended when a break condition is satisfied Break Condition 1 gt 2 Measurement is started from the satisfaction of the condition set in Break Condition 1 to the satisfaction of the condition set in Break
34. only be measured Cacheable area instruction access cycle CIC Devices incorporating the cache function can only be measured Cacheable area data access cycle CDC Devices incorporating the cache function can only be measured Access counts other than instruction data NAM Devices incorporating the cache function can only be measured Non cacheable area access counts NCN Devices incorporating the cache function can only be measured Non cacheable area instruction access counts NCIN Devices incorporating the cache function can only be measured Non cacheable area data access counts NCDN Devices incorporating the cache function can only be measured Cacheable area access counts CN Devices incorporating the cache function can only be measured Cacheable area instruction access counts CIN Devices incorporating the cache function can only be measured Cacheable area data access counts CDN Devices incorporating the cache function can only be measured Each measurement condition is also counted when conditions in table 2 9 are generated Table 2 9 Performance Measurement Conditions to be Counted Measurement Condition Notes No caching due to the settings of TLB cacheable bit Counted for accessing the cacheable area Cache on counting Accessing the non cacheable area is counted less than the actual number of cycles and counts Accessing the cacheable
35. orating the DSP function can only be measured Instruction data conflict cycle MAC Other conflict cycles than instruction data OC Exception interrupt counts EA Data TLB miss cycle MTS Devices incorporating the MMU function can only be measured Instruction TLB miss cycle ITS Devices incorporating the MMU function can only be measured Interrupt counts INT Number of BL 1 instructions BL1 Number of MD 1 instructions MD1 Instruction cache miss counts IC Data cache miss counts DC Instruction fetch stall IF Data access stall DA Instruction cache miss stall ICS Data cache miss stall DCS Cacheable access stall CS X Y RAM access stall XYS Devices incorporating the X Y memory can only be measured URAM access stall US Devices incorporating the U memory can only be measured Instruction data access stall cycle MA Other access cycles than instruction data NMA Non cacheable area access cycle NCC Devices incorporating the cache function can only be measured Non cacheable area instruction access cycle 30 NCI Devices incorporating the cache function can only be measured RENESAS Table 2 8 Measurement Item cont Selected Name Non cacheable area data access cycle Option NCD Devices incorporating the cache function can only be measured Cacheable area access cycle CC Devices incorporating the cache function can
36. ows a recommended circuit for connection between the H UDI and AUD port connectors 36 pins and the MPU when the emulator is in use Notes 1 Sections surrounded with dashed lines mean examples They may require logic ICs 2 Do not connect anything to the N C pins of the H UDI port connector 3 The ASEMDO0 pin must be 0 when the emulator is connected and 1 when the emulator is not connected respectively 1 When the emulator is used ASEMDO 0 2 When the emulator is not used ASEMD0O 1 Figure 1 3 shows an example of a circuit that allows the ASEMD0 pin to be GND 0 whenever the emulator is connected by using the user system interface cable When the ASEMD0 pin is changed by switches etc ground pin 22 Do not connect this pin to the ASEMDO0 pin 4 When a network resistance is used for pull up it may be affected by a noise Separate TCK from other resistances 5 The pattern between the H UDI port connector and the MPU must be as short as possible Do not connect the signal lines to other components on the board 6 For the pin processing in cases where the emulator is not used refer to the hardware manual of the MPU 7 The signal names in figures are standard they may differ depending on the MPU in use RENESAS When the circuit is connected as shown in figure 1 3 the switches of the emulator are set as SW2 and SW3 1 For details refer to section 3 8 Setting the DIP Switches in the Debugger Part of the Supe
37. rH Family E10A USB Emulator User s Manual H UDI port connector 36 pin type GND GND GND AUDATA1 GND AUDATA2 AUDATA2 GND AUDATA3 AUDATA3 GND AUDSYNG AUDSYNG GND GND GND GND GND GND GND TDO GND ASEBRKAK GND UVCC GND RESET RESETP GND GND GND N C ASEMDO User system For pin names and examples of recommended circuits of the MPU in use contact Renesas Technology Corp via the sales office Figure 1 3 Recommended Circuit for Connection between the H UDI Port Connector and MPU when the Emulator is in Use 36 Pin Type RENESAS Figure 1 4 shows a circuit for connection when the SH7705 is in use VccQ 3 3 V I O power supply Pulled up at 4 7 kQ or more all VecQ VecQ VccQ VccQ H UDI port connector 36 pin type SH7705 GND AUDCK GND AUDATAO AUDATAO GND AUDATA 1 AUDATA1 GND AUDATA2 AUDATA2 GND AUDATA3 AUDATA3 GND AUDSYNG AUDSYNG GND N C GND N C GND TCK TCK GND TMS aNd TRST TRST GND TDI GND TDO GND ASEBRKAK ASEBRKAK GND UVCC GND RESET RESETP GND GND N C ASEMDO User system Note This is an example when SH7705 is used For differences and notes on the MPU in use contact Renesas Technology Corp via the sales office Figure 1 4 Circuit for Connection between the H UDI Port Connector and MPU when the SH7705 is in Use 36 Pin Type RENESAS 1 5 2 Recommended Circuit 14 Pin Type Connection between the H UDI and AUD port connectors and the MPU in each
38. range can be acquired by trace Two memory ranges can be specified for channels A and B The read write or read write cycle can be selected as the bus cycle for trace acquisition Setting Method i Select the Channel A and Channel B check boxes in the AUD function group box of the Trace mode page Each channel will become valid ii Open the Window trace page and specify the bus cycle and memory range that are to be set for each channel 21 RENESAS Acquisition Trace mode Window trace AUD Branch trace Channel Read Write C Read C Wite Read Write Start address HO End address HO Bus state L bus bus Y bus bus Channel B Read Write C Read C Write Read Write Start address H0 End address HO Bus state L bus C X bus Y bus Fbus Figure 2 3 Window trace Page Notes 1 When the L bus or I bus radio button is selected the following bus cycles will be traced e L bus A bus cycle generated by the CPU is acquired A bus cycle is also acquired when the cache has been hit e J bus A bus cycle generated by the CPU or DMA is acquired A bus cycle is not acquired when the cache has been hit The address information acquired by the I bus is 28 bits and the upper 4 bits are displayed as The source cannot be displayed in the Trace window When X Y RAM is accessed from the PO space the I bus must be selected and when accessed from the P2 space
39. se RENESAS When the circuit is connected as shown in figure 1 5 the switches of the emulator are set as SW2 1 and SW3 1 For details refer to section 3 8 Setting the DIP Switches in the Debugger Part of the SuperH Family E10A USB Emulator User s Manual H UDI port connector 14 pin type TRST ASEBRKAK TMS TDI User system Note For pin names and examples of recommended circuits of the MPU in use contact Renesas Technology Corp via the sales office Note Figure 1 5 Recommended Circuit for Connection between the H UDI Port Connector and MPU when the Emulator is in Use 14 Pin Type 10 RENESAS Figure 1 6 shows a circuit for connection when the SH7705 is in use VccQ 3 3 V I O power supply Pulled up at 4 7 KQ or more all VecQ VecQ VecQ VecQ VecQ VccQ H UDI port connector 14 pin type SH7705 TCK GND TRST TDO ASEBRKAK TCK TRST ASEBRKAK TMS TMS TDI RESET RESETP N C User system Note This is an example when SH7705 is used For differences and notes on the MPU in use contact Renesas Technology Corp via the sales office Figure 1 6 Circuit for Connection between the H UDI Port Connector and MPU when the SH7705 is in Use 14 Pin Type 11 RENESAS RENESAS Section 2 Software Specifications when Using the SH 3 core _custom_SoC 2 1 Differences between the SH 3 core _custom_SoC and the Emulator 1 When the emulator system is initiated it initializes th
40. ser system can be reduced RENESAS 1 3 Installing the H UDI Port Connector on the User System Table 1 3 shows the recommended H UDI port connectors for the emulator Table 1 3 Recommended H UDI Port Connectors Connector Type Number Manufacturer Specifications 36 pin connector DX10M 36S Hirose Electric Co Ltd Screw type DX10M 36SE Lock pin type DX10G1M 36SE 14 pin connector 2514 6002 Minnesota Mining amp 14 pin straight type Manufacturing Ltd Note When designing the 14 pin connector layout on the user board do not place any components within 3 mm of the H UDI port connector When designing the 36 pin connector layout on the user board do not connect any components under the H UDI connector 1 4 Pin Assignments of the H UDI Port Connector Figures 1 1 and 1 2 show the pin assignments of the 36 pin and 14 pin H UDI port connectors respectively Note Note that the pin number assignments of the H UDI port connector shown on the following pages differ from those of the connector manufacturer RENESAS Input Input Signal Output 1 Note No Signal Output AUDCK Output 19 TMS Input GND 20 GND AUDATAO Output 212 TRST Input GND GND AUDATA1 Output 23 TDI Input GND 24 GND AUDATA2 Output 25 TDO Output GND 26 GND AUDATA3 Output 27 ASEBRKAK Output GND 28 GND ol a NJ o oa aAlw rn N AUDSYNC Output 29 UVCC Output GND 30 GND
41. west even address is used 2 A BREAKPOINT is accomplished by replacing instructions of the specified address 24 Accordingly it can be set only to the internal RAM area However a BREAKPOINT cannot be set to the following addresses e An area other than CSO to CS6 and the internal RAM e An instruction in which Break Condition 2 is satisfied e A slot instruction of a delayed branch instruction e An area that can be only read by MMU Note This only applies to the MPU that incorporates the MMU in SH 3 During step operation BREAKPOINTS are disabled Conditions set at Break Condition 2 are disabled when an instruction to which a BREAKPOINT has been set is executed Do not seta BREAKPOINT to an instruction in which Break Condition 2 is satisfied RENESAS 1 1 1 0 N When execution resumes from the address where a BREAKPOINT is specified single step operation is performed at the address before execution resumes Therefore realtime operation cannot be performed When a BREAKPOINT is set to the slot instruction of a delayed branch instruction the PC value becomes an illegal value Accordingly do not set a BREAKPOINT to the slot instruction of a delayed branch instruction When a BREAKPOINT is set to the cacheable area the cache block containing the BREAKPOINT address is filled immediately before and after user program execution Note on DSP repeat loop For the MPU that incorporates the DSP in SH 3 a BR
42. y write or BREAKPOINT should be set only for the RAM area ztENESAS 8 10 1 ee 12 13 Cache Operation during User Program Break When cache is enabled the emulator accesses the memory by the following methods e At memory write Writes through the cache then writes to the memory e At memory read Does not change the cache write mode that has been set Therefore when memory read or write is performed during user program break the cache state will be changed Port The AUD and H UDI pins are multiplexed in some MPUs Pin functions that are multiplexed with the H UDI pin cannot be used when the emulator is used Pin functions that are multiplexed with the AUD pin can be used when the AUD pin of the MPU is not connected to the emulator UBC When User is specified in the UBC mode list box in the Configuration dialog box the UBC can be used in the user program Do not use the UBC in the user program because it is used by the emulator when EML is specified in the UBC mode list box in the Configuration dialog box Memory Access during Break In the enabled MMU for the MPU that incorporates the MMU in SH 3 when a memory is accessed and a TLB error occurs during break it can be selected whether the TLB exception is controlled or the program jumps to the user exception handler in TLB Mode in the Configuration dialog box When TLB miss exception is enable is selected a Communication Timeout error w
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