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Correction for Incorrect Description Notice RL78/G1A Descriptions in

1. c 2013 Renesas Electronics Corporation All rights reserved Page 6 of 26 234 NESAS RENESAS TECHNICAL UPDATE TN RL A018A E Date Sep 24 2013 Correct Table 11 3 A D Conversion Time Selection 4 4 4 8 bit A D Converter When there is stabilization wait time hardware trigger wait mode except second and subsequent conversion in sequential conversion mode and conversion of channel specified by scan 1 2 and 3 in scan mode Nole 1 A D Converter Mode Register Conversion Number of Number of Stabilization Stabilization Wait Time Conversion Time Selection 0 ADMO Clock fan Stabilization Conversion Wait Time AVoo 1 610 36 V AVoo 1 610 3 6 V AVoo 1 810 36 V AVpo 2410 36 V AVon 2 7 to 36 V FR1 FRO LV1 Wait Clock Clock Conversion fcuk 1 MHz fck 2 4MHz fox 8 MHz fox 16 MHz fa 32 MHz Time Normal 1 fcix 32 4 fa 1316 fcx Setting Setting Setting Setting 41 125 us number prohibited prohibited prohibited prohibited foux 16 Of T Sof 41 25 8 20 625 ys sampling foux 8 clock 332c 41 5 us 20 75 ys 10 375 ps fcu 6 11 fao 250 fcux 31 25 us 15 625 us 7 8125 us fouk 5 209 fc x 25 125 us 13 0625 ws 6 53125 us fok 4 168 fcik 42 us 21 us 10 5 us 5 25 us foux 2 86 fcik 21 5 us 10 75 4s 5 375 us 2 6875 us fcil 43o 43 us 10 75 4s 5 375 us 2 6875 us Setting prohibited Normal 2 foix 32 53 faD 1754 fox Settin
2. 1388 fcix 1158 fcik 928 fcLk 468 fcLk Setting prohibited Setting prohibited Setting prohibited Setting prohibited 230 25 V 230 5 11525 ws 231 us e 115 5 ps 57 75 1s 173 5 s V 86 75 ps 43 375 jg e 14475 ys Note 2 72375 5 Note2 36 1875 us 116 ps 58 1s Note 2 Note 2 58 5 ps te 29 25 g 29 us 14 625 ps e 238 fcuk RENESAS 29 75 us 14 875 s V Setting prohibited Page 4 of 26 RENESAS TECHNICAL UPDATE TN RL A018A E Date Sep 24 2013 Correct Table 11 3 A D Conversion Time Selection 2 4 2 12 bit A D Converter When there is stabilization wait time hardware trigger wait mode except second and subsequent conversion in sequential conversion mode and conversion of channel specified by scan 1 2 and 3 in scan mode Note 1 A D Converter Mode Regis Conversion Numberof Numberof Stabilization Stabilization Wait Time Conversion Time Selection ADMO Clock fax Stabilization Conversion WaitTime AVDD 1 6t036V AVDD 16t036V AVDD 18t036V AVDD 241036V AVDD 271036V FRO LV1 Wait Clock Clock Conversion fCLK 2 1 MHz fCLK 4MHz f CLK 8MHz CLK 16 MHz fCLK 32 MHz Time Normal 1 fcix 32 54f 1732 fcx Setting Setting Setting Setting 54 125 us number prohibited prohibited prohibited prohibited fcu 16 ofl g68 fou 54 25 ws 27 125 us
3. fou 2 164 fa L 20 5 ws 10 25 ws 5 125 us fox 29 fork 82 fouk L 10 25 4s 5 425 us Setting prohibited Low volta fcux 32 15 fex 63f 2031 fox Setting Setting Setting Setting 63 46875 5 ge 1 number prohibited prohibited prohibited prohibited fok 16 on 1023 foi 63 9375 us 31 96875 sampling fc 8 clock 519 fax 64 875 ys 32 4375 5 1621875 js fcu 6 33fa 393 f k 49 125 us 24 5625 ps 12 28125 ps fouk 5 330 fcux 41 25 us 20 625 ps 10 3125 ys SP fouK 4 267 fouk 66 75 ws 33 375 us 16 6875 5 9 8 34375 ps V fcu 144 fou 35 25 s 117 625 ws 8 8125 5 4 40625 se foux 1 78ffox 78 ps 195 5 9 75 us 4875 s Setting prohibited Low volta fcux 32 21715 6952c Setting Setting Setting Setting 217256 ge number prohibited prohibited prohibited prohibited fok 16 oi 9480 foik 217 5 1s 10875 18 sampling Note 2 Note 2 fouk 8 clock 1744 foux 218 us 109 us 545 1s fcux 6 187 fo 1310 fox 163 75 1s 81 875 us NO 40 9375 gt fork 5 1093 tcux 136 625 1s 68 3125 us 34 15625 s V fouk 4 876 fc x 109 5 ws 54 75 us 27 375 1g 8 foux 2 442o 55 25 ps 27 625 1g 13 8125 c e fei 225 foix 28 125 1s 14 0625 s V Setting prohibited Note 2
4. main mode 1 8 V lt Voo lt 3 6 V 0 125 External main system clock frequency 2 7 V lt Voo lt 3 6 V 1 0 2 4 V lt Voo lt 2 7 V 1 0 1 8 V lt Voo lt 2 4 V 1 0 1 6 V lt Voo lt 1 8 V 1 0 fexs 32 External main system clock input high level width low level width exu tex 2 7 V lt Voo lt 3 6 V 24 2 4 V lt Voo lt 2 7 V 30 1 8 V lt Voo lt 2 4 V 60 1 6 V lt Voo lt 1 8 V 120 13 7 TIOO TIO1 TIO3 to TIO7 input high level width low level width 1 fuck 10 TOOO0 TO01 TO03 to TO07 output frequency HS high speed main mode 2 7 V lt EVopo 3 6 V 1 8 V EVppo lt 2 7 V 1 6 V EVppo lt 1 8 V LV Low voltage main mode 1 6 V lt EVppo 3 6 V LS low speed main mode 1 8 V EVppo 3 6 V 1 6 V EVppo lt 1 8 V PCLBUZO PCLBUZ1 output frequency HS high speed main mode 2 7 V lt EVbppo lt 3 6 V 1 8 V lt EVppo lt 2 7 V 1 6 V lt EVppo lt 1 8 V LV Low voltage main mode 1 8 V lt EVppo lt 3 6 V 1 6 V lt EVppo lt 1 8 V LS low speed main mode 1 8 V lt EVbppo 3 6 V 1 6 V lt EVppo lt 1 8 V PO BR PM RHR MO HR OO mM A Interrupt input high level width low level width INTPO 1 6 V lt Voo lt 3 6 V INTP1 to INTP11 1 6 V lt EVppo lt 3 6 V Key in
5. sampling fouk 8 clock 436 feuk 54 5 4s 2725 s 13 625 1s fork 6 11 fac 328 fou 41 us 20 548 10 25 us fork 5 274 fc k 34 25 us 17 125 us 8 5625 us fouK 4 220 fc k 55 uS 275 s 189 75 s 6 875 4S fork 2 112 fcik 28 1s 14 us 7 us 8 5 us foux 1 2 fork 56 fc k 56 us 14 us 7 us 3 5 us Setting prohibited Normal 2 fck 32 58 fcuk 66f 2170 fax Setting Setting Setting Setting 67 8125 us aa prohibited prohibited prohibited prohibited Oo 62 4 812 fork 16 Sani 1114 feux 69 625 s 34 8125 us fcu 8 dock 586 foix 73 25 ws 36 625 us 18 3125 us fouk 6 23 fao 454 fcLk 56 75 us 28 375 us 14 1875 us fou 5 388 foik 48 5 us 2425 ws 12 125 us fouK 4 322 foLk 80 5 ps 40 25 ps 20 125 ws 10 0625 js fcu 2 190 fc k 47 5 us 23 75 us 11 875 us 5 9375 us foix 1 29 feck 95 fck 95 us 23 75 ws 11 875 6 5 9375 us Setting prohibited Low volta foux 32 15 fcik 76fa 2447 fax Setting Setting Setting Setting 7646875 us ge 1 number prohibited prohibited prohibited prohibited fok 16 on 12311 fox 76 9375 ps 38 46875 ps sampling foux 8 clock 623 foux 77 875 us 389375 5 1946875 s fcu 6 33 fac 471 foLk 58 875 us 29 4375 jg 1471875 s V fcu 5 395 fcik 49 375 us 246875 je 1234
6. 26 RENESAS RENESAS TECHNICAL UPDATE TN RL A018A E Date Sep 24 2013 Correct eunnoi urey M AC eunnoau Buisseooud 1dnuelu v o eulnos ure Figure 12 84 Flowchart of UART Transmission in Continuous Transmission Mode Starting UART communication el i For the initial setting refer to Figure 12 78 SAU default setting Select buffer empty interrupt Set data for transmission and the number of data Clear communication end flag Setting transmit data Storage area Transmission data pointer Number of communication data and Communication end flag are optionally set on the internal RAM by the software Enables interrupt Clear interrupt request flag XXIF reset interrupt mask XXMK and set interrupt enable El Writing transmit data to Read transmit data from storage area and write it 2 pos to TXDq Update transmit data pointer Communication starts by writing to SDRmn 7 0 TXDap SDRmn 7 0 Wait for transmit completes When transfer end interrupt is generated it moves to interrupt processing routine Buffer empty transfer end interrupt lt 3 gt If transmit data is left read them from storage area then write into TxDq and update transmit data pointer and No number of transmit data Numberof 7 O If no more transmit data clear MDmn bit if it s set If not communication data 0 finish Yes 7 Writing transmit data
7. 5 5 Forced termination by software before reading the data flash memory Resume DMA transfer after the data flash memory has been read B Access the data flash memory by using the newest data flash library C Insertion of NOP Insert an NOP instruction immediately before the instruction that reads the data flash memory lt Example gt MOVW HL addr16 Reads RAM NOP Insert NOP instruction before reading data flash memory MOV A DE Read data flash memory Page 15 of 26 RENESAS TECHNICAL UPDATE TN RL A018A E Date Sep 24 2013 If a high level language such as C is used however the compiler may generate two instructions for one code In this case the NOP instruction is not inserted immediately before the data flash memory read instruction Therefore read the data flash memory by A or B above Remarks 1 n DMA channel number n 0 1 2 fcu CPU peripheral hardware clock frequency Page 16 of 26 c 2013 Renesas Electronics Corporation All rights reserved 7tENESAS RENESAS TECHNICAL UPDATE TN RL A018A E Incorrect 10 29 3 DC Characteristics Ta 40 to 85 C 1 6 V lt AVpp lt Vpp lt 3 6 V 1 6 V lt EVppo S Voo S 3 6 V Vss EVsso 0 V 1 5 Note 3 Specification under output current where the duty lt 70 Ih rrent value that h han h ratio lower than 70 can Icul with the following expression when changing th rati n26 TA 40 to 85 C 1 6 V lt AVpp S Voo S 3 6 V 1 6
8. 7FFBH 32 K 4 bytes 0 to BFFBH 48 K 4 bytes 0 to FFFBH 64 K 4 bytes Other than above Setting prohibited Other than above Setting prohibited c 2013 Renesas Electronics Corporation All rights reserved Page 14 of 26 7tENESAS RENESAS TECHNICAL UPDATE TN RL A018A E Incorrect 9 25 4 3 Procedure for accessing data flash memory The data flash memory is initiall fterar n n nn a d read or programmed To a he memor rform the following pr re 1 Write 1 to bit O DFLEN of the data flash control register DFLCTL 2 Wait for the setup to finish for software timer etc The time setup takes differs for each main clock mode Setup time for each main clock mode HS High speed main 5 us LS Low speed main 720 ns LV Low voltage main 10 us 3 After the wait the data flash memory can be accessed Cautions 1 Accessing the data flash memory is not possible during the setup time 2 Before executing a STOP instruction during the setup time temporarily clear DFLEN to 0 c 2013 Renesas Electronics Corporation All rights reserved 7tENESAS Date Sep 24 2013 Correct The data flash memory is stopped after a reset ends To access the data flash make initial settings according to the following procedure 1 Set bit 0 DFLEN of the data flash control register DFLCTL to 1 lt 2 gt Wait for the setup to finish for software timer et
9. Register Conversion Number of Number of Stabilization Stabilization Wait Time Conversion Time Selection 0 ADMO Clock fan Stabilization Conversion Wait Time AVoo 1 6 to 36 V AVoo 1 610 3 6 V AVoo 1 810 36 V AVoo 2 410 36 V AVon 2 7 to 36 V FR1 FRO LV1 Wait Clock Clock Conversion fci 1 MHz fck 2 4MHz fek 8 MHz fox 16 MHz fa 32 MHz Time Normal 1 fcix 32 41h 1316 fcx Setting Setting Setting Setting 41 125 us number prohibited prohibited prohibited prohibited foux 16 Of T Sof 41 25 8 20 625 ys sampling foux 8 clock 332c 41 5 us 20 75 ys 10 375 ps fcLk 6 11 fan 250 fcux 31 25 us 15 625 us 7 8125 us fouk 5 209 fc x 25 125 us 13 0625 ws 6 53125 us fcLk 4 168 fcik 42 us 21 us 10 5 us 5 25 us foux 2 86 fcik 21 5 us 10 75 4s 5 375 us 2 6875 us fcuk 1 43 fcx 43 us 10 75 us 5 375 us 2 6875 us Setting prohibited Normal 2 fc 32 53f 1754 fox Setting Setting Setting Setting 54 8125 us number prohibited prohibited prohibited prohibited foux 16 of aoee 56 625 s 28 3125 js sampling foik 8 clock 482 cux 60 25 ws 30 125 ws 15 0625 us fok 6 23 fao 376 fak 47 us 23 5 us 11 75 us fcu 5 323 fouk 40 375 s 20 1875 us 10 09375 js fouK 4 270 fcuk 33 75 ws 16 875 us 8 4375 ps
10. V lt EVppo S Vpp S 3 6 V Vss EVsso 0 V 2 5 Note 3 Specification under conditions where the duty factor is 70 Ih t rrent val hat has changed the d ratio lower than 70 can can alcul with the following expression when changing th rati n26 c 2013 Renesas Electronics Corporation All rights reserved 7tENESAS Date Sep 24 2013 Correct Note 3 Specification under conditions where the duty factor lt 70 The output current value that has changed to the duty factor 7096 the duty ratio can be calculated with the following expression when changing the duty factor from 70 to n Note 3 Specification under conditions where the duty factor lt 70 The output current value that has changed to the duty factor 7096 the duty ratio can be calculated with the following expression when changing the duty factor from 70 to n Page 17 of 26 R R RENESAS TECHNICAL UPDATE TN RL A018A E Incorrect 11 29 4 AC Characteristics TA 40 to 85 C 1 6 V lt AVpp lt 3 6 V 1 6 V lt EVpDo lt VDD 3 6 V Vss EVsso 0 V Instruction cycle minimum instruction execution time Conditions Main system HS high speed main mode clock fmain mode 2 7 V lt Vo lt 3 6 V 0 03125 Date Sep 24 2013 2 4 V lt Vo 27V 0 0625 LV Low voltage main mode 1 6 V lt Voo lt 3 6 V 0 25 LS low speed main mode 1 8 V lt Voo lt 3 6 V 0 125
11. lt Vo lt 2 0 Vete C 30 pF Rb 5 5 KQ Slp hold time from SCRp1 27 V lt EVo o lt 3 6 V 2 3 V lt Vo x 2 7 V Co 30 pF Ro 2 7 KQ 1 8 V lt EVppo lt 3 3 V 1 6 V lt Vo lt 2 0 V 96 Co 30 pF Ro 5 5 KQ Delay time from SCKp4 to SOp output ete 27 V lt EVo00 lt 3 6 V 2 3 V lt Vo x 2 7 V Co 30 pF Ro 2 7 KQ 1 8 V lt EVon lt 3 3 V 1 6 V lt Vo lt 2 0 VNe e8 Cb 30 pF Ro 5 5 KQ Slp setup time to SCKpy 5 2 7 V lt EVppo lt 3 6 V 2 3 V lt Vo lt 2 7 V Co 30 pF Rb 2 7 KQ 1 8 V EVppo lt 3 3 V 1 6 V lt Vo lt 2 0 VNe e8 Co 30 pF Rb 5 5 KQ Slp hold time from SCKp4 ee 27 V lt EVoo lt 3 6 V 2 3 V lt Vo x 2 7 V Co 30 pF Ro 2 7 KQ 1 8 V lt EVppo lt 3 3 V 1 6 V lt Vo lt 2 0 Vote 6 Cb 30 pF Ro 5 5 KQ Delay time from SCKp1 to SOp output e 2 7 V lt EVoo lt 3 6 V 23 V lt Vo x 2 7 V Co 30 pF Ro 2 7 KQ 1 8 V lt EVon lt 3 3 V 1 6 V lt Vo lt 2 0 VF C 30 pF Re 5 5 KQ c 2013 Renesas Electronics Corporation All rights reserved RENESAS Page 24 of 26 RENESAS TECHNICAL UPDATE TN RL A018A E Date Sep 24 2013 13 29 6 1 A D converter characteristics Addition When AVperj AVgeee ANIO ADREFP1 0 ADREFPO 1 AVner 7 AVrerm ANI1 ADREFM 1 target pin ANI2 ANI12 Ta 40 to 85 C 2 7 AVngep S AVp
12. pF Ro 2 7 KQ 121 479 479 Slp hold time from SCKp1 e 2 7 V lt EVooo lt 3 6 V 23V lt Vo x 2 7 V Co 20 pF Rb 2 7 KQ Delay time from SCKpl to SOp output 4 2 7 V EVppo lt 3 6 V 23V lt Vo x 2 7 V Co 20 pF Rb 2 7 KQ Slp setup time to SCKpJ ete 5 2 7 V lt EVop0 8 6 V 23V lt Vo x 2 7 V Cb 20 pF Ro 2 7 KQ Slp hold time from SCKpv ete 2 7 V lt EVooo lt 3 6 V 23V lt Vo x 2 7 V Co 20 pF Rb 2 7 KQ Delay time from SCKp1 to SOp output e e Correct 2 7 V lt EVop0 8 6 V 23V lt Vo lt 2 7 V Co 20 pF Ro 2 7 KQ 7 Communication at different potential 2 5 V CSI mode master mode SCKp internal clock output corresponding CSIOO only Ta 40 to 85 C 2 7 V lt EVppo lt Vppx 3 6 V Vss EVsso 0 V Parameter SCKp cycle time Conditions 2 7 V EVppo lt 3 6 V 2 3 V x Vo x 27 V Co 20 pF Rb 2 7 KQ tkcy1 gt 2 fcLK HS Note 1 LS Note 2 MIN MAX MIN MAX SCKp high level width 2 7 V lt EVooo lt 3 6 V 23V lt Vo x 2 7 V Co 20 pF Rb 2 7 KQ tkcv 2 120 tkcvi 2 120 tkcvi 2 120 SCKp low level width 2 7 V lt EVop0 lt 8 6 V 23V lt Vo lt 2 7 V Cb 20 pF Ro 2 7 KQ tkcvi 2 10 tkcvi 2 50 tkcy1 2 50 Slp setup time to SCKpt 4 2 7 V EVppo lt 3 6 V 23V lt Vo
13. 0 or DAPmn 1 and CKPmn 1 The Slp hold time becomes from SCKp when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 7 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKpt when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 8 C is the load capacitance of the SCKp and SOp output lines c 2013 Renesas Electronics Corporation All rights reserved Page 20 of 26 234 NESAS RENESAS TECHNICAL UPDATE TN RL A018A E Date Sep 24 2013 Incorrect Correct Notes 1 HS is condition of HS high speed main mode Notes 1 HS is condition of HS high speed main mode 2 LS is condition of LS low speed main mode 2 LS is condition of LS low speed main mode 3 LV is condition of LV low voltage main mode 3 LV is condition of LV low voltage main mode 4 When DAPmn 0 and CKPmn rDAPmn 1 and CKPmn 1 The SI u 4 Transfer rate in the SNOOZE mode MAX 1 Mbps time becomes to SCKp when DAPmn 0 and CKPmn 1 or DAPmn 1 5 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slp setup and CKPmn 0 time becomes to SCKp when DAPmn 0 and CKPmn 1 or DAPmn 1 and When DAPmn z 0 and CKPmn rDAPmn z 1 and CKPmn 1 The Sip hold CKPmn 0 time becomes from SCKp when DAPmn 0 and CKPmn 1 or DAPmn 1 6 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slip hold and CKPmn 0 time becomes from SCKp when D
14. 3 V 1 6 V lt Vo lt 2 0 V 96 Co 30 pF Ro 5 5 KQ Delay time from SCKp4 to SOp output ete 27 V lt EVo00 lt 3 6 V 2 3 V lt Vo x 2 7 V Co 30 pF Ro 2 7 KQ 1 8 V lt EVon lt 3 3 V 1 6 V lt Vo lt 2 0 VNe e8 Cb 30 pF Ro 5 5 KQ Slp setup time to SCKpy 5 2 7 V lt EVppo lt 3 6 V 2 3 V lt Vo lt 2 7 V Co 30 pF Rb 2 7 KQ 1 8 V EVppo lt 3 3 V 1 6 V lt Vo lt 2 0 VNe e8 Co 30 pF Rb 5 5 KQ Slp hold time from SCKp4 ee 27 V lt EVoo lt 3 6 V 2 3 V lt Vo x 2 7 V Co 30 pF Ro 2 7 KQ 1 8 V lt EVppo lt 3 3 V 1 6 V lt Vo lt 2 0 Vote 6 Cb 30 pF Ro 5 5 KQ Delay time from SCKp1 to SOp output e 2 7 V lt EVoo lt 3 6 V 23 V lt Vo x 2 7 V Co 30 pF Ro 2 7 KQ 1 8 V lt EVon lt 3 3 V 1 6 V lt Vo lt 2 0 VF C 30 pF Re 5 5 KQ c 2013 Renesas Electronics Corporation All rights reserved RENESAS Page 23 of 26 R RENESAS TECHNICAL UPDATE TN RL A018A E Correct Date Sep 24 2013 8 Communication at different potential 1 8 V 2 5 V CSI mode master mode SCKp internal clock output 2 2 Ta 40 to 85 C 1 8 V lt EVppox Vpp x 3 6 V Vss EVsso 0 V Parameter Slp setup time to SCKpt Nee Conditions 2 7 V lt EVo o lt 3 6 V 2 3 V lt Vo x 2 7 V Co 30 pF Re 2 7 KQ 1 8 V EVppo lt 3 3 V 1 6 V
15. 375 ps fc 4 319 foik 79 75 1s 39 875 us 19 9375 s 9 96875 js OP fcu 2 167 fc k 41 75 1s 20 875 us 104375 16 521875 us fcu 91 fox 91 us N 22 75 ps 11 375 us 5687545 Setting prohibited Low volta fo k 32 230 fa 7368 fak Setting Setting Setting Setting 230 25 ps V ge 2 number prohibited prohibited prohibited prohibited of fok 16 8688 fciK 230 5 ps 115 25 is sampling foik 8 clock 1848 fcix 231 ps 115 5 g V 57 75 ys foux 6 187 fro 1388 foux 173 5 ps 86 75 ye 43375 oP foux 5 1158 fci 144 75 jg 2 72375 us Ne 36 1875 pe fouK 4 928 fci 116 5 5g g efe 29 jg Note foux 2 468 fcik 58 5 ps 2925 g V 14 605 1 OP fcu 238 fc k 29 75 s 14 875 6 Setting prohibited Note Note 2 c 2013 Renesas Electronics Corporation All rights reserved Page 5 of 26 234 NESAS RENESAS TECHNICAL UPDATE TN RL A018A E Date Sep 24 2013 Incorrect Table 11 3 A D Conversion Time Selection 4 4 4 8 bit A D Converter When there is stabilization wait time hardware trigger wait mode except second and subsequent conversion in sequential conversion mode and conversion of channel specified by scan 1 2 and 3 in scan mode Nole 1 A D Converter Mode
16. APmn 0 and CKPmn 1 or DAPmn 1 and KPmn 1 Th CKPmn 0 im t mes from SCKp when DAPmn 0 and CKPmn 1 7 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to or DAPmn 1 and CKPmn z O SOp output becomes from SCKp1 when DAPmn 0 and CKPmn 1 or DAPmn 7 Cisthel capacitan fth tput lines 1 and CKPmn 0 Iransfer rate in the SNOOZE m MAX 1 Mb 8 C is the load capacitance of the SOp output lines c 2013 Renesas Electronics Corporation All rights reserved Page 21 of 26 7tENESAS R R RENESAS TECHNICAL UPDATE TN RL A018A E Incorrect Date Sep 24 2013 7 Communication at different potential 2 5 V CSI mode master mode SCKp internal clock output corresponding CSIOO only Ta 40 to 85 C 2 7 V lt EVppo lt Vppx 3 6 V Vss EVsso 0 V Parameter SCKp cycle time Conditions 2 7 V EVppo lt 3 6 V 2 3 V x Vo x 27 V Co 20 pF Rb 2 7 KQ tkcy1 gt 2 fCLK HS Note 1 LS Note 2 LV Note 3 MIN MAX MIN MAX MIN MAX SCKp high level width 2 7 V lt EVop0 8 6 V 23V lt Vo x 2 7 V Cb 20 pF Ro 2 7 KQ tkcvi 2 120 tkcvi 2 120 tkcv 2 120 SCKp low level width 2 7 V lt EVo00 lt 3 6 V 23V lt Vo x 2 7 V Co 20 pF Rb 2 7 KQ tkcvi 2 10 tkcvi 2 50 tkcy1 2 50 Slp setup time to SCKpT 2 7 V lt EVooo 8 6 V 2 3 V x Vo x 2 7 V Cb 20
17. Date Sep 24 2013 RENESAS TECHNICAL UPDATE 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan Renesas Electronics Corporation Product Document Category U MCU No TN RL A018A E Rev 1 00 Correction for Incorrect Description Notice Information Title RL78 G1A Descriptions in the Hardware User s Manual Cat Technical Notification Rev 1 10 Changed ategory Lot No Applicable RL78 G1A Reference po reos ee Hardware Product R5F10E Alllots Document R01UH0305EJ0110 Mar 2013 This document describes misstatements found in the RL78 G1A User s Manual Hardware Rev 1 10 RO1UH0305EJ0110 Corrections Applicable Item Applicable Page 11 2 Configuration of A D Converter Pages 363 Incorrect descriptions revised 11 3 2 A D converter mode register 0 ADMO Pages 371 to 375 ncorrect descriptions revised mem 126 Operation oi UART UARTO to UART2 Pages 528 Incorrect descriptions revised Communication Pages 539 JI ipti i 12 6 1 UART transmission Pages 539 ncorrect descriptions revised 13 5 16 Communication operations Page 637 Incorrect descriptions revised 17 3 4 Port mode registers 0 to 2 7 12 15 PMO to ME f PM2 PM7 PM12 PM15 Pages 746 Incorrect descriptions revised 18 3 3 SNOOZE mode Page 767 Incorrect descriptions revised 22 3 1 1 Flash memory CRC control register sat CRCOCTL Pages 808 Incorrect descriptions revised Document Improvement The above co
18. MO er 0 FRO LV1 Normal 1 Conversion Clock lio foik 32 foik 16 foik 8 fcLk 6 fcLk 5 foik 4 foik 2 Number of Stabilization Wait Clock foik 1 2 fck Number of Conversion Clock 54 fap number of sampling clock 11 fav Stabilization Wait Time Conversion Time 1732 fcix Stabilization Wait Time Conversion Time Selection AVDD 161036 V AVDD 161036 V AVDD 18103 6V AVDD 241036 V AVDD 271036 V 868 fcLk 436 fcLK 328 fcLk 274l fcuk 220 fc k 112 fcik fex 1 MHz Setting prohibited fex 4MHz Setting prohibited fok 8 MHz Setting prohibited fok 16 MHz Setting prohibited fou 32 MHz 54 125 us 54 25 us 27 125 us 54 5 us 27 25 us 13 625 us 41 us 20 5 us 10 25 us 34 25 us 17 125 us 8 5625 4s 55 us 27 5 us 13 75 us 6 875 us 28 us 14 us 7 us 3 5 us 56 fc k 56 us 14 us 7 us 3 5 us Setting prohibited Normal 2 Low volta ge 1 fcu 32 foik 16 fcLk 8 fcLk 6 foik 5 foik 4 foik 2 58 fcLk fcu 1 foik 32 foik 16 foik 8 foik 6 fcu 5 fcu 4 fcu 2 fcu 1 29 fck 15 foi 66 fap number of sampling clock 23 fab 76 fap number of sampl
19. Subsystem clock fsus operation 1 8 V lt Voo lt 3 6 V 28 5 In the self programming HS high speed main mode 2 7 V lt Vo lt 3 6 V 0 03125 2 4 V lt Voo 27V 0 0625 mode LV Low voltage main mode 1 8 V lt Voo lt 3 6 V 0 25 LS low speed main mode 1 8 V lt Voo lt 3 6 V 0 125 External main system clock frequency 2 7 V lt Voo lt 3 6 V 1 0 2 4 V lt Voo lt 2 7 V 1 0 1 8 V lt Voo lt 2 4 V 1 0 1 6 V lt Voo lt 1 8 V 1 0 fexs 32 External main system clock input high level width low level width texH tEXL 2 7 V lt Voo lt 3 6 V 24 2 4 V lt Voo lt 2 7 V 30 1 8 V lt Voo lt 2 4 V 60 1 6 V lt Voo lt 1 8 V 120 13 7 TIOO TIO1 TIO3 to TIO7 input high level width low level width 1 fuck 10 TOOO0 TO01 TO03 to TO07 output frequency HS high speed main mode 2 7 V lt EVopo 3 6 V 1 8 V lt EVppo lt 2 7 V 1 6 V lt EVppo lt 1 8 V LV Low voltage main mode 1 6 V lt EVbppo lt 8 6 V LS low speed main mode 1 8 V lt EVppo lt 3 6 V 1 6 V lt EVppo lt 1 8 V PCLBUZO PCLBUZ1 output frequency HS high speed main mode 2 7 V x EVop0 lt 3 6 V 1 8 V lt EVppo lt 2 7 V 1 6 V lt EVppo lt 1 8 V LV Low voltage main mode 1 8 V lt EVppo lt 3 6 V 1 6 V E
20. Vppo lt 1 8 V LS low speed main mode 1 8 V lt EVppo 3 6 V 1 6 V EVppo lt 1 8 V PO RY PO AIN RR OO pM A Interrupt input high level width low level width INTPO 1 6 V lt Voo lt 3 6 V INTP1 to INTP11 1 6 V lt EVppo lt 3 6 V Key interrupt input high level width low level width KRO to KR9 1 8 V EVppo lt 3 6 V 1 8 V lt AVop x 3 6 V 1 6 V EVppo lt 1 8 V 1 6 V lt AVop lt 1 8 V RESET low level width c 2013 Renesas Electronics Corporation All rights reserved RENESAS Page 18 of 26 R R RENESAS TECHNICAL UPDATE TN RL A018A E Correct TA 40 to 85 C AVpp lt Vpp lt 3 6 V 1 6 V lt EVDDo lt VDD lt 3 6 V Vss EVsso 0 V Conditions Instruction cycle minimum instruction execution time Main system HS high speed main mode clock fmain mode 2 7 V xVop 36 V 0 03125 Date Sep 24 2013 2 4 V lt Voo 27 V 0 0625 LV Low voltage main mode 1 6 V lt Voo lt 3 6 V 0 25 LS low speed main mode 1 8 V lt Voo lt 3 6 V 0 125 Subsystem clock fsus operation 1 8 V lt Voo lt 3 6 V 28 5 In the self programming mode HS high speed main mode 2 7 V lt Voo lt 3 6 V 0 03125 2 4 V lt Voo 27V 0 0625 LV Low voltage main mode 1 8 V lt Voo lt 3 6 V 0 25 LS low speed
21. c The time setup takes differs for each flash operation mode for the main clock lt Setup time for each flash operation mode gt HS High speed main 5 us LS Low speed main 720 ns LV Low voltage main 10 us 3 After the wait the data flash memory can be accessed Cautions 1 Accessing the data flash memory is not possible during the setup time 2 Transition to the STOP mode is not possible during the setup time To enter the STOP mode during the setup time clear DFLEN to 0 and then execute the STOP instruction 3 The high speed on chip oscillator should be kept operating during data flash rewrite If it is kept stopping operate the high speed on chip oscillator clock HIOSTOP 0 and execute the data flash library after 30 us have elapsed After initialized the data flash memory can be read by using a CPU instruction or can be read written by using a data flash library If the DMA controller operates when the data flash memory is accessed however follow one of these procedures A Suspending forcibly terminating DMA transfer Before reading the data flash memory suspend DMA transfer of all the channels used After setting the DWAITn bit to 1 however wait at least for the duration of three clocks fcik before reading the data flash memory After reading the data flash memory lift the suspension of transfer by clearing the DWAITn bit to 0 Or forcibly terminate DMA transfer in accordance with the procedure in 15
22. d interrupt servicing is carried out When vectored interrupt servicing is carried out HS High speed main mode 4 99 to 9 44 us 7 clocks HS High speed main mode 4 99 to 9 44 us 1 clocks LS Low speed main mode 1 10 to 5 08us 7 clocks LS Low speed main mode 1 10 to 5 08us 1 clocks LV Low voltage main mode 16 58 to 25 40 us 7 clocks LV Low voltage main mode 16 58 to 25 40 ys 1 clocks When vectored interrupt servicing is not carried out When vectored interrupt servicing is not carried out HS High speed main mode 4 99 to 9 44 us 7 clocks HS High speed main mode 4 99 to 9 44 us 1 clocks LS Low speed main mode 1 10 to 5 08u s 7 clocks LS Low speed main mode 1 10 to 5 08p s 1 clocks LV Low voltage main mode 16 58 to 25 40us 7 clocks LV Low voltage main mode 16 58 to 25 40us 1 clocks 8 22 3 1 1 Flash memory CRC control register CRCOCTL Symbol lt 7 gt 6 Symbol lt 5 4 3 2 1 0 7 gt 6 5 4 3 2 1 0 cRCoCTL CRCOEN o FEAS FEA4 FEA3 FEA2 FEA1 FEAO CRCOCTL CRCOEN oo FEA5 FEA4 FEA3 FEA2 FEA1 FEAO CRCOEN Control of CRC ALU operation CRCOEN Control of CRC ALU operation 0 Stop the operation Stop the operation 1 Start the operation according to HALT instruction execution Start the operation according to HALT instruction execution FEAO High speed CRC operation range FEAO High speed CRC operation range 0 to 3FFBH 16 K 4 bytes 0 to
23. ddress FFF27H After reset OOH R W Symbol 7 6 5 4 3 2 1 0 Address FFF2CH Afterreset QOH R W 7 6 5 4 3 2 1 0 Address FFF2FH Afterreset QOH R W Symbol PM12 Symbol 7 6 5 4 3 2 1 0 0 Output mode output buffer on 1 Input mode output buffer off c 2013 Renesas Electronics Corporation All rights reserved Page 12 of 26 a34 NESAS RENESAS TECHNICAL UPDATE TN RL A018A E Date Sep 24 2013 Correct Figure 17 5 Format of Port Mode Register PMO to PM2 PM7 PM12 PM15 Address FFF20H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 Address FFF21H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM1 1 PM16 PM15 PM14 PM13 PM12 PM11 PM10 1 pme pms pms pma pwz PM Pano Address FFF22H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 Address FFF27H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 Address FFF2CH After reset FFH R W Symbol 7 PM12 Address FFF2FH After reset FFH R W Symbol 7 6 5 4 3 2 1 0 l O mode selection for Pmn KRk pin n 0 to 7 m 0 to 2 7 12 15 k 0 to 9 0 Output mode output buffer on 1 Input mode output buffer off c 2013 Renesas Electronics Corporation All rights reserved Page 13 of 26 234 NESAS RENESAS TECHNICAL UPDATE TN RL A018A E Date Sep 24 2013 Incorrect Correct 7 18 3 3 SNOOZE mode Transition time from SNOOZE mode to normal operation Transition time from SNOOZE mode to normal operation When vectore
24. ew de eunnoi Bursseooud 1dnueju uljnos urey 6 For the initial setting refer to Figure 12 78 Select buffer empty interrupt Set data for transmission and the number of data Clear communication end flag Storage area Transmission data pointer Number of communication data and Communication end flag are optionally set on the internal RAM by the software Clear interrupt request flag XXIF reset interrupt mask XXMK and set interrupt enable El Writing transmit data to Read transmit data from storage area and write it TXDq it d inter TXDap SDRmn 7 0 to q Update transmit data pointer Communication starts by writing to SDRmn 7 0 Wait for transmit completes When transfer end interrupt is generated it moves to interrupt processing routine 3 Buffer empty transfer end interrupt then rite int r ter an Number of number of transmit data communication data gt 0 to SIOp SDRmniz 0 4 Subtract 1 from number of transmit data Yes r MDmn0 bit to 0 RETI No Check completion of transmission by Transmission completed verifying transmit end flag Yes Write MDmn0 bit to 1 Disable interrupt MASK Communication continued Yes No Write STmn bit to 1 Clear SAUmEN bit of the PERO register to 0 End of communication c 2013 Renesas Electronics Corporation All rights reserved Page 9 of
25. fouk 8 clock 1744 foux 218 us 109 us 545 1s fcux 6 187 fo 1310 fox 163 75 1s 81 875 us NO 40 9375 gt fork 5 1093 tcux 136 625 1s 68 3125 us 34 15625 s V fouk 4 876 fc x 109 5 ws 54 75 us 27 375 1g 8 foux 2 442o 55 25 ps 27 625 1g 13 8125 c e fei 225 foix 28 125 1s 14 0625 1s Setting prohibited Note 2 c 2013 Renesas Electronics Corporation All rights reserved Page 7 of 26 234 NESAS RENESAS TECHNICAL UPDATE TN RL A018A E Date Sep 24 2013 Incorrect Correct 3 12 6 Operation of UART UARTO to UART2 Communication e 32 pin products e 32 pin products Unit Channel Used as CSI Used as UART Used as Simplified Pc 0 0 CSI00 1 2 3 1 0 1 CSI21 Unit Channel Used as CSI Used as UART Used as Simplified c 0 0 2 3 1 UART2 supporting LIN bus UART2 supporting LIN bus c 2013 Renesas Electronics Corporation All rights reserved Page 8 of 26 7tENESAS RENESAS TECHNICAL UPDATE TN RL A018A E Date Sep 24 2013 Incorrect 4 12 6 1 UART transmission Figure 12 84 Flowchart of UART Transmission in Continuous Transmission Mode Starting UART communication t I SAU default setting eunnoj ur
26. g Setting Setting Setting 54 8125 us number prohibited prohibited prohibited prohibited foux 16 pan 906 fox 56 625 s 28 3125 js fcu 8 dock 482 fox 60 25 ws 30 125 us 15 0625 us fcu 6 23 fao 376 fuk 47 us N 23 5 us 11 75 4s fcu 5 323 fouk 40 375 s 20 1875 us 10 09375 s fouK 4 270 fcuk 33 75 ws 16 875 us 8 4375 js fou 2 164 fa L 20 5 ws 10 25 ws 5 125 us fouK 1 29 fouk 82 foux L 10 25 8 15 125 us Setting prohibited Low volta fcux 32 15 fex 63f 2031 fox Setting Setting Setting Setting 63 46875 5 ge 1 number prohibited prohibited prohibited prohibited fok 16 on 1023 foi 63 9375 us 31 96875 sampling foux 8 clock 519 foux 64 875 ys 32 4375 5 16 21875 5 fcu 6 33fa 393 f k 49 125 us 24 5625 ps 12 28125 ps fouk 5 330 fcux 41 25 us 20625 ps 10 3125 ys SP fouK 4 267 fouk 66 75 ws 33 375 us 16 6875 5 9 8 34375 ps V fcu 144 fou 35 25 1s 117 625 ws 8 8125 us 4 40625 use foux 1 78ffox 78 ps 195 5 9 75 us 4875 s Setting prohibited Low volta fc k 32 217f 6952 fcx Setting Setting Setting Setting 21725 Pus ge number prohibited prohibited prohibited prohibited f fcu 16 8480ffx 217 5 1s 10875 18 sampling Note 2 Note 2
27. ing clock 33 fab 2170 fcix 1114 foik 586 fcuk 454 fcuk 388 fcLk 322 fcuk 190 fcik Setting prohibited Setting prohibited Setting prohibited Setting prohibited 67 8125 ps 69 625 ys 34 8125 ps 73 25 g V 36 625 Ls 18 3125 us 56 75 js 28 375 us 14 1875 us 48 5 ps 24 25 us 12 125 us 40 25 ps 20 125 us 10 0625 ys 23 75 11 875 us 5 9375 us 95 fc k 2447 fcux 1231 fcik 623 fcuk 471 fcuk 395 fc k 319 fc k 167 fcLk 95 LS Note 2 Setting prohibited Setting prohibited 11 875 s V Setting prohibited 5 9375 us Setting prohibited Setting prohibited 7646875 ws 769375 ps 38 46875 ps 77 875 us 38 9375 js 1946875 ys 58 875 us 294375 ps 1471875 s V 49 375 us 24 6875 1s 1234375 ys 79 75 eX 39 875 us 19 9375 e V 9 96875 s 41 75 1s 20 875 us 10 4375 ps 521875 js Ve 91 fcuk Note 2 91 us 22 75 ys 11 375 us 56875 s Setting prohibited Low volta ge2 fcu 32 foik 16 fcLk 8 foik 6 foik 5 foik 4 foik 2 fcu 1 c 2013 Renesas Electronics Corporation All rights reserved 230 fan number of sampling clock 187 fab 7368 fc 3688 fcix 1848 fcix
28. p S VppS 3 6V Vss OV AVss OV Reference voltage AVrerp Reference voltage AVrerm OV HALT mode Parameter Conditions Resolution Overall error 12bit resolution ADTYP 0 12bit resolution 12bit resolution 12bit resolution 12bit resolution 12bit resolution Conversion time Zero scale error 125 Full scale error Integral linearity error Differential linearity error Analog input voltage Note1 2 3 Note1 2 3 Notes 1 TYP Value is the average value AVpp AVrerp 3V Ta 25 C MAX Values are mean 30 in normal distribution 2 This value based on the characterization results is not subject to production testing 3 Excludes quantization error 1 2 LSB Caution 1 Attention must be paid to noise input to each power supply and ground lines The reference voltage line of AVrerp is separated from the other power supply lines for noise countermeasures Caution 2 Please make sure that pulses whose voltage suddenly change such as digital pulses are not input or output to a pin adjacent to the pin whose value is being A D converted and P20 to P27 P150 to P154 c 2013 Renesas Electronics Corporation All rights reserved Page 25 of 26 234 NESAS RENESAS TECHNICAL UPDATE TN RL A018A E Incorrect 14 30 3 1 Pin characteristics TA 40 to 105 C 2 4 V lt AVpp S Voo 3 6 V 2 4 V EVppo S Vpp S 3 6 V Vss EVsso 0 V Note 3 S
29. pecification under output current where the duty lt 70 Ih rrent val hat h han h ratio lower than 70 can alcul with the following expression when changing th rati n Ta 40 to 105 C 2 4 V lt AVpp Vpp 3 6 V 2 4 V lt EVppo S Vpp S 3 6 V Vss EVsso 0 V Note 3 Specification under output current where the duty lt 70 Th t rrent val hat h han he d ratio lower than 70 can can alcul with the following expression when changing th rati n 15 30 4 AC Characteristics Ta 40 to 105 C 2 4 V S AVpp 3 6 V 2 4 V lt EVppos Voo lt 3 6 V Vss EVsso 0 V c 2013 Renesas Electronics Corporation All rights reserved 7tENESAS Date Sep 24 2013 Correct Note 3 Specification under conditions where the duty factor lt 70 The output current value that has changed to the duty factor gt 70 the duty ratio can be calculated with the following expression when changing the duty factor from 70 to n Note 3 Specification under conditions where the duty factor lt 70 The output current value that has changed to the duty factor gt 70 the duty ratio can be calculated with the following expression when changing the duty factor from 70 to n Ta 40 to 105 C AVpp lt VppS 3 6 V 2 4 V lt EVppos Vop 3 6 V Vss EVsso 0 V Page 26 of 26
30. r DAPmn 1 and CKPmn 1 The Slp hold time becomes from SCKp when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 7 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKpt when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 8 C is the load capacitance of the SCKp and SOp output lines Correct 2 During communication at same potential CSI mode master mode SCKp internal clock output corresponding CSIOO only Ta 40 to 85 C 2 7 V lt EVppo Voo lt 3 6 V Vss EVsso 0 V Parameter Conditions Hs Note ps nete py Nees MIN MAX MIN MAX MIN MAX SCKp cycle time 2 VxEVopx3 6V kc 2 2 f k 83 3 250 500 Note4 SCKp high low level width 2 7 V lt EVpp lt 3 6 V tkcvi 2 tkcvi 2 tkcvi 2 10 50 50 Slp setup time to SCKpT 2 7 V x EVoo lt 3 6 V 33 110 110 Note 5 Slp hold time from SCKp 2 7 V lt EVoo lt 8 6 V 10 10 10 Note 6 Delay time from SCKp to C 20 pF Note Note 7 SOp output Notes 1 HS is condition of HS high speed main mode 2 LS is condition of LS low speed main mode 3 LV is condition of LV low voltage main mode 4 The fMCL must also be 24MHz or less 5 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slp setup time becomes to SCKp when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 6 When DAPmn 0 and CKPmn
31. rrections will be made for the next revision of the User s Manual Hardware c 2013 Renesas Electronics Corporation All rights reserved Page 1 of 26 7tENESAS RENESAS TECHNICAL UPDATE TN RL A016A E Date Sep 24 2013 Corrections in the User s Manual Hardware Corrections and Applicable Items for corrections 3 12 6 Operation of UART UARTO to UART2 Page 528 Page 8 Communication 12 6 1 UART transmission Page 539 Pages 9 10 13 5 16 Communication operations Page 637 Page 11 17 3 4 Port mode registers 0 to 2 7 12 15 PMO Eq to PM2 PM7 PM12 PM15 Page 746 pages tee Te 18 3 3 SNOOZE mode Page 767 Page 14 22 3 1 1 Flash memory CRC control register Eq CRCOCTL Page 808 Page 14 9 25 4 3 Procedure for accessing data flash memory Page842__ Pages 15 16 Incorrect Bold with underline Correct Gray hatched Revision History RL78 G1A User s Manual Hardware Rev 1 10 Correction for Incorrect Description Notice Document Number TN RL A018A E Sep 9 2013 First edition issued No 1 to 15 in corrections This notice c 2013 Renesas Electronics Corporation All rights reserved Page 2 of 26 234 NESAS RENESAS TECHNICAL UPDATE TN RL A018A E Incorrect 1 11 2 Configuration of A D Converter 9 AVREFP pin This pin inputs an external reference voltage AVREFP If using AVREFP he side reference vol fth D converter and ADREFPO bits of A D converter m register 2 ADM2 1 The analog signal
32. s input to ANI2 to ANI12 and ANI16 to ANI30 are converted to digital signals based on the voltage applied between AVREFP and the side reference voltage AVREFM AVSS In addition to AVREFP it is possible to select AVDD or the internal reference voltage 1 45 V as the side reference voltage of the A D converter he ADREFP1 c 2013 Renesas Electronics Corporation All rights reserved 7tENESAS Date Sep 24 2013 Correct 9 AVREFP pin This pin inputs an external reference voltage AVREFP If using AVREFP as the side reference voltage of the A D converter set the A D converter mode register 2 ADM2 ADREFP1 bits to 1 and ADREFPO bits to 0 The analog signals input to ANI2 to ANI12 and ANI16 to ANI30 are converted to digital signals based on the voltage applied between AVREFP and the side reference voltage AVREFM AVSS In addition to AVREFP it is possible to select AVDD or the internal reference voltage 1 45 V as the side reference voltage of the A D converter Page 3 of 26 RENESAS TECHNICAL UPDATE TN RL A018A E Incorrect 2 11 3 2 A D converter mode register 0 ADMO Table 11 3 A D Conversion Time Selection 2 4 Date Sep 24 2013 2 12 bit A D Converter When there is stabilization wait time hardware trigger wait mode except second and subsequent conversion in sequential conversion mode and conversion of channel specified by scan 1 2 and 3 in scan mode e A D Convert er Mode Regis AD
33. terrupt input high level width low level width KRO to KR9 1 8 V EVppo lt 3 6 V 1 8 V lt AVop lt 3 6 V 1 6 V EVppo lt 1 8 V 1 6 V lt AVop lt 1 8 V RESET low level width c 2013 Renesas Electronics Corporation All rights reserved RENESAS Page 19 of 26 RENESAS TECHNICAL UPDATE TN RL A018A E Date Sep 24 2013 12 29 5 1 Serial array unit Incorrect 2 During communication at same potential CSI mode master mode SCKp internal clock output corresponding CSIOO only Ta 40 to 85 C 2 7 V lt EVppo Voo lt 3 6 V Vss EVsso 0 V Parameter Conditions SCKp cycle time 2 7 V lt EVon lt 3 6V Ikcriz A fak 83 3 250 500 Note 4 SCKp high low level width 2 7 V lt EVoo lt 3 6 V tkcy1 2 tkcvi 2 tkcvi 2 10 50 50 Slp setup time to SCKp 2 7 V lt EVo0 lt 3 6 V 33 110 110 Note 5 Slp hold time from SCKp 2 7 V lt EVoo x 3 6 V 10 10 10 Note 6 Delay time from SCKp to C230 pF te SOp output Notes 1 HS is condition of HS high speed main mode 2 LS is condition of LS low speed main mode 3 LV is condition of LV low voltage main mode 4 The value must also be 2 fCLK or more 5 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slp setup time becomes to SCKp when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 6 When DAPmn 0 and CKPmn 0 o
34. to No lt 2 gt mDq SDRmn 0 MDmn 1 OOO 5 Yes paca Sets communication Subtract 1 from number of transmit data Clar MDmnO BS completion interrupt flag RETI lt 6 gt No Check completion of transmission by Transmission completed verifying transmit end flag Write MDmn0 bit to 1 Disable interrupt MASK Yes Communication continued No Write STmn bit to 1 Clear SAUmEN bit of the PERO register to 0 End of communication c 2013 Renesas Electronics Corporation All rights reserved Page 10 of 26 RENESAS RENESAS TECHNICAL UPDATE TN RL A018A E Date Sep 24 2013 Incorrect Correct 5 13 5 16 Communication operations Note The wait time is calculated as follows Note The wait time is calculated as follows IICWLO setting value IICWHO setting value 4 clocks fcuk te x 2 IICWL ing value IICWH ing value 4 x fork tr x 2 clock Page 11 of 26 c 2013 Renesas Electronics Corporation All rights reserved 7tENESAS RENESAS TECHNICAL UPDATE TN RL A018A E Date Sep 24 2013 Incorrect 6 17 3 4 Port mode registers 0 to 2 7 12 15 PMO to PM2 PM7 PM12 PM15 Figure 17 5 Format of Port Mode Register PMO to PM2 PM7 PM12 PM15 Address FFF20H After reset OOH R W Symbol 7 6 5 4 3 2 1 0 pmo Address FFF21H After reset OOH R W Symbol 7 6 5 4 3 2 1 0 Address FFF22H After reset OOH R W Symbol 7 6 5 4 3 2 1 0 A
35. x 2 7 V Co 20 pF Rb 2 7 KQ 121 479 479 Slp hold time from SCKp1 ee 2 7 V lt EVop0 lt 8 6 V 23V lt Vo x 2 7 V Cb 20 pF Ro 2 7 KQ Delay time from SCKp to SOp output 4 2 7 V lt EVp00 lt 3 6 V 23V lt Vo x 2 7 V Co 20 pF Rb 2 7 KQ Slp setup time to SCKp4 ee 2 7 V lt EVooo 8 6 V 2 3 V x Vo x 2 7 V Cb 20 pF Ro 2 7 KQ Slp hold time from SCKpJ e5 2 7 V EVppo lt 3 6 V 23V lt Vo x 2 7 V Co 20 pF Rb 2 7 KQ Delay time from SCKp1 to Note 5 SOp output 2 7 V EVppo lt 3 6 V 23V lt Vo x 2 7 V Co 20 pF Rb 2 7 KQ c 2013 Renesas Electronics Corporation All rights reserved RENESAS Page 22 of 26 R RENESAS TECHNICAL UPDATE TN RL A018A E Incorrect Date Sep 24 2013 8 Communication at different potential 1 8 V 2 5 V CSI mode master mode SCKp internal clock output 2 2 Ta 40 to 85 C 1 8 V lt EVppox Vpp x 3 6 V Vss EVsso 0 V Parameter Slp setup time to SCKpt Nee Conditions 27 V lt EVo o lt 3 6 V 2 3 V lt Vo x 2 7 V Co 30 pF Ro 2 7 KQ HS Note 1 LS Note 2 MIN MAX MIN MAX 1 8 V EVppo lt 3 3 V 1 6 V lt Vo lt 2 0 Vete C 30 pF Rb 5 5 KQ Slp hold time from SCRp1 27 V lt EVo o lt 3 6 V 23 V lt Vo x 2 7 V Co 30 pF Ro 2 7 KQ 1 8 V lt EVppo lt 3

Correction for Incorrect Description Notice RL78/G1A Descriptions in

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