AVR-TLCD-128CAN development board Users Manual
Contents
1. o gt lt x E 4 7 f 2 Cif EUN C35 HIGH VOLTAGE POWER SUPPLY CIRCUIT AVR TLCD 128CAN should be powered by 4 5VAC or 6 9VDC The board power consumption at 8 VDC the consumption is about 20 mA RESET CIRCUIT AVR TLCD 128CAN reset circuit is realized with MCP130T which on power failure or if you apply low level at EXT 3 resets the MCU CLOCK CIRCUIT Quartz crystal 8 MHz is connected to AT9OCAN128 pin 24 XTAL1 and pin 23 XTAL2 Quartz crystal 32 768 kHz is connected to AT90CANI128 pin 19 TOSC1 PG4 and pin 18 TOSC2 PG3 and supplies the internal Asynchronous Timer Counter Timer Counter2 asynchronous operation JUMPER DESCRIPTION devices the bus it 18V E Enables 18 V power supply for the 128 and all other Default state is closed CAN T This jumper assures correct work of the CAN At each end of umm should be closed This means that if you have only two devices with CAN the jumpers of both devices should be closed If you have more than two devices only the two end devices should be closed CAN to TD1 PD5 CAN to RD1 PD6 Default state is closed CAN CTRL If this jumper is closed the MCU controls the CAN Default state is closed 1 WP E ig vow Enables the Write Protect input signal to the 128 Brad Default state is closed CP E Enables the Card Pr2. AVR TLCD 128CAN development board Users Manual Rev A July 2008 Copyright c 2008 OLIMEX Ltd All rights reserved INTRODUCTION AVR TLCD 128CAN adds cool LCD and touchscreen interface to your next project There is AT9OCAN128 on board with all microcontroller pins available for plug in additional boards BOARD FEATURES MCU AT9OCAN128 128KB Flash memory 4096B RAM 4096 EEPROM TOUCH SCREEN LCD 160x160 dots B W 81x60 mm view area Stainless steel front panel 102x85 mm 4x3 35 with easy to mount x4 3 mm fixing screws JTAG connector for programming and debugging with AVR JTAG L or AVR JTAG USB connector for programming with AVR PG1 or AVR GP2 SD MMC card connector CAN driver and connector UEXT connector for connection to other Olimex modules like MOD MP3 MOD NRF24Lx MOD GPS and many others 8MHBHzcrystal Extension connectors for all AT9OCAN128 ports 4 5 6 0 battery connector PCB FR 4 1 5 mm 0 062 soldermask silkscreen component print Dimensions 102x85 mm 4 x 3 35 ELECTROSTATIC WARNING The AVR TLCD 128CAN board is shipped in protective anti static packaging The board must not be subject to high electrostatic potentials General practice for working with static sensitive devices should be applied when working with this board BOARD USE REQUIREMENTS Cables Hardware Software 1 8 meter USB A B cable to connect AVR JTAG USB to USB h
3. This is the serial data input for the shift register UEXT 246 8 10 m seem 5 TXD Output Transmit Data This is the output data line for the UART RXD Input Receive Data This is the input data line for the UART SCL I O Serial Synchronization Clock This is the synchronization clock for the data transfer through I2C interface This could be either input or output depending on whether the MCU is master or slave SDA I O Serial Data This pin is data input or output depending on the data flow direction for the I2C interface MISO I O Master In Slave Out This pin could be either data input MCU is master or data output MCU is slave The signal is pat of the SPI interface MOSI I O Master Out Slave In This pin is be used for communication through SPI interface and it is either data output from the MCU when it is master or data input for the MCU when it is slave SCK I O Serial Synchronization Clock This is the synchronization clock for the data transfer through the SPI interface It could be either input or output depending on whether the MCU is master or slave PWR ELEM Signal Name At the PWR pin should be applied voltage 4 5VAC or 6 9 VDC CAN Signal Name GND CANL CANH CANL and CANH are either deferential input or differential output depending on the function of the SN65FVD230 CAN controller receiving or transmitting data SD MMC card slot I 14
4. LQXM ACE be xa Em LOd LLNI VOS 4 Odd OLNIMIOS 8 0 era 98 84 olVizod ZAd LLNUEOI si lt 21 29 921 ed 00 S3d GINI 2 90 vAd PLNI GE90 Ad LNIV VEOO 1812 9Qv ovd Z3d ONIV OMOX S asid 84 sav svd L3d OQd 0QX L N 44 cavievd 8H 5 q 69 2501 E d 4 Laviivd pOd LOSOL 4 E od Veo 22 xi 0 9SO MSY Am Wm QGA9SOT3H H1d ZOLYSH A WL uS AGE 953 Ove cv SIG N3 ACE L1 100 LO en ceo Age O ZAGAHSINS 7419 NYO eB pamer 9 1966 2 VN S 90 Ste 5 sg gt peu Q O 89 Z oly edo 9zo i L8SNL me kl A82 8V 9 91 cle TASS 2 Y ASL z LX4 N 2 NR QA9 OVAG Y 2 ccs TT S eel qNO ray no Ni gj BOARD LAYOUT extension CAN AVR TLCD 128x Rev A N A gt
5. m o Signal Name EUN Signal Name CS SD Output Chip Select SD The signal on this pin enables or disables the SD MMC MOSI Output Master Out Slave In As the access to the memory is via SPI interface this is data output from the MCU which is master and input for the memory card which is slave SCK Output Serial Synchronization Clock This is the synchronization clock for the data transfer MISO I O Master In Slave Out As the access to the memory card is via SPI interface this is data input for the MCU which is master and data output from the memory card which is slave WP E Input Write Protect Enable This signal is input for the MCU CP E Input Card Present Enable This signal is input for the MCU EXT 2 4 8 10 12 14 16 18 20 22 24 26 sene om CNN NONE 7 _ p esee e emer S em 14 m B em 4 MECHANICAL DIMENSIONS 0 00 mm 3 50 81 50 mm 85 00 102 00 98 40 DISPLAY 160x160 3 60 mm 02 00 mm All measures are in mm AVAILABLE DEMO SOFTWARE You could find information about AVR TLCD 128CAN demo software at www olimex com dev ORDER CODE AVR TLCD 128CAN assembled and tested no kit no soldering required How to order You can order to us directly or by any of our distributors Check our web www olimex com dev for more info P f 9 All boards produced by Olimex are RoHS compliant Revisi
6. Bytes 4K Bytes or 8K Bytes o In System Programming by On Chip Boot Program CAN UART o True Read While Write Operation 4K Bytes EEPROM Endurance 100 000 Write Erase Cycles 4K Bytes Internal SRAM AT9OCAN32 64 128 Up to 64K Bytes Optional External Memory Space Programming Lock for Software Security JTAG IEEE std 1149 1 Compliant Interface Boundary scan Capabilities According to the JTAG Standard Programming Flash Hardware ISP EEPROM Lock amp Fuse Bits Extensive On chip Debug Support CAN Controller 2 0A amp 2 0B ISO 16845 Certified 15 Full Message Objects with Separate Identifier Tags and Masks Transmit Receive Automatic Reply and Frame Buffer Receive Modes 1Mbits s Maximum Transfer Rate at 8 MHz Time stamping TTC amp Listening Mode Spying or Autobaud Peripheral Features Programmable Watchdog Timer with On chip Oscillator 8 bit Synchronous Timer Counter O o 10 bit Prescaler o External Event Counter o Output Compare or 8 bit PWM Output 8 bit Asynchronous Timer Counter 2 o 10 bit Prescaler o External Event Counter o Output Compare or 8 Bit PWM Output o 32Khz Oscillator for RTC Operation Dual 16 bit Synchronous Timer Counters 1 amp 3 o 10 bit Prescaler Input Capture with Noise Canceler External Event Counter 3 Output Compare or 16 Bit PWM Output Output Compare Modulation 8 channel 10 bit SAR ADC o 8 Single ended Channels o 7 Differential Channels o 2 Diffe
7. esent input signal to the AT9OCAN128 Default state is closed TD1 PD5 When in position 1 2 shorted outputs the TD1 signal to the ET controller When in position 2 3 shorted EXT 12 is connected Default position is 1 2 shorted RD1 PD6 When in position 1 2 shorted inputs the RD1 signal from the EF controller When in position 2 3 shorted EXT 13 is connected Default position is 1 2 shorted INPUT OUTPUT Power on red LED with name PWR_LED connected to EXT 1 and EXT 2 Accelerometer SMB380 Touchscreen LCD PCO919WEO7 EXTERNAL CONNECTORS DESCRIPTION ICSP 246 8 10 1 73 5 7 9 Input Programming Data In This is used for data input while programming the MCU through ICSP PDO OutputProgramming Data Out This pin is used for daa output while programming the MCU through ICSP SCK Input Serial Synchronization Clock This pin is input for the MCU while programming cae Signal Name 246 8 10 eer pope 03879 7 3 3V Re S f TCK Input Test Clock This allows shifting of the data in on the TMS and TDI pins It is a positive edge triggered clock with the TMS and TCK signals that define the internal state of the device TDO OutputTest Data Out This is the serial data output for the shift register Data is shifted out of the device on he negative edge of the TCK signal TMS Input Test Mode Select The TMS pin selects the next state in the TAP state machine TDI Input Test Data In
8. on history REV A created July 2008 Disclaimer 2008 Olimex Ltd All rights reserved Olimex logo and combinations thereof are registered trademarks of Olimex Ltd Other terms and product names may be trademarks of others The information in this document is provided in connection with Olimex products No license express or implied or otherwise to any intellectual property right is granted by this document or in connection with the sale of Olimex products Neither the whole nor any part of the information contained in or the product described in this document may be adapted or reproduced in any material from except with the prior written permission of the copyright holder The product described in this document is subject to continuous development and improvements All particulars of the product and its use contained in this document are given by OLIMEX in good faith However all warranties implied or expressed including but not limited to implied warranties of merchantability or fitness for purpose are excluded This document is intended only to assist the reader in the use of the product OLIMEX Ltd shall not be liable for any loss or damage arising from the use of any information in this document or any error or omission in such information or any incorrect use of the product
9. ost on PC If you use AVR JTAG L or AVR PG1 you will need RS232 cable If you use AVR PG2 you will need LPC cable Other cables might be required in case of other programming debugging tools Programmer Debugger AVR JTAG L AVR JTAG USB AVR PG1 AVR PG2 or other compatible programming debugging tool AVR Studio 4 13 or later WinAVR latest version or IAR AVR AVR Studio and WinAVR are free to download and use Take a note that AVR Studio 4 13 has a bug and doesn t read the fuses correctly On our request to Atmel support they had confirmed the bug and had suggested to fix the bug by AVR Studio 4 13 SP2 JTAGICE Fix available from http www atmel no beta ware For programming with 1 you could use PonyProg and for programming with AVR PG2 you could use PonyProg AVR Dude or other compatible tools PROCESSOR FEATURES AVR TLCD 128CAN board use MCU AT90CAN128 from Atmel with these features High performance Low power AVR 8 bit Microcontroller Advanced RISC Architecture 133 Powerful Instructions Most Single Clock Cycle Execution 32 x 8 General Purpose Working Registers Peripheral Control Registers Fully Static Operation Upto 16 MIPS Throughput at 16 MHz On chip 2 cycle Multiplier Non Program and Data Memories 128K Bytes of In System Reprogrammable Flash o Endurance 10 000 Write Erase Cycles Optional Boot Code Section with Independent Lock Bits o Selectable Boot Size 1K Bytes 2K
10. rential Channels With Programmable Gain at 1x 10x or 200x On chip Analog Comparator Byte oriented Two wire Serial Interface Dual Programmable Serial USART Master Slave SPI Serial Interface o Programming Flash Hardware ISP Special Microcontroller Features Power on Reset and Programmable Brown out Detection Internal Calibrated RC Oscillator 8 External Interrupt Sources 5 Sleep Modes Idle ADC Noise Reduction Power save Power down amp Standby Software Selectable Clock Frequency Global Pull up Disable I O and Packages 53 Programmable I O Lines 64 lead TQFP and 64 lead QFN Operating Voltages 2 7 5 5V Operating temperature Industrial 40 C to 85 C Maximum Frequency 8 MHz at 2 7V 16 MHz at 4 5V BLOCK DIAGRAM PF PFO PAT PAD ped dy PORTF DRIVERS PORTA DRIVERS DATA REGISTER DATA REGISTER DATA DIR PORTF REG PORTA amp BIT DATA BUS JTAG TAP ON CHIP DEBUG BOUNDARY SCAN PROGRAMMING LOGIC PORTC DRIVERS DATA REGISTER PORTC WATCHDOG TIMER MCU CONTROL REGISTER PROGRAM i COUNTER R PROGRAM INSTRUCTION REGISTER INSTRUCTION DECODER DATA REGISTER PORTD DATA REGISTER PORTE DATA DIR REG PORTB DATA REG PORTG MEMORY MAP Program Memory Application Flash Section Boot Flash Section Flash end SCHEMATIC Data Memor
11. y 32 Registers 0x0000 0x001F 64 I O Registers 0x0020 0 005 0x0060 0 00 ISRAM start ISRAM end XMem start Qquvo as AC 9 0 Tdo E 42 S3M cIva 5 Ooq o1va 255 WOSA LSSA IQ aWO So elva ao 086 15 ACE gSOqno ANI vasnas A3G WOO X3WI10 MWW Id LLH a17 X4WIN0 8002 9 H9IHAdOO V A38 821 G9 1L YAV OWW aS ysef 159 AGE xol es zen SNS anov E T819 pgp ORE amp T 103M6L609d 8119 T aM Ed duos JON zaNo 2119 2 4 azod 1 i 91 fanana 0 05 so eH 9Ad oaL eoqv SL 6L cody 055 SX Hey SJd SW L SDQV HHA i C Vd WO L vOQV a m 4000 5 SSA m zi ZJd zoav 1 SOW osiwead 10808 OSIN 0 o g camia 7 EE ViSo Sd 401 1 z sa Oz 1X3 2 8190 984 2 C za 1 d Zi OLOO ZOO LEd Nvoxw 9ad LL ZL NVOXL SQd LMOX ia tad LAI m Wa zs Qd CLNI LOXLL Y Qd ZANI
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