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1. 31 1 Reserved NA 0 ACK Acknowledge NMI and clear PI NMISTATUS NA 4 1 5 SW Board Reset Register Name PI SWRESET Address Ox1F00 0050 Access WO Reset Value N A Table 4 5 PI SWRESET register Bits Field name Function Initial Value El SWRST Writing 0x4D to this register field will generate a board reset MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 23 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Peripheral Bus Controller 4 1 6 PIC32 USB Status Register Name PI PIC32_USB_STATUS Address 0x1F00 0060 Access RO Reset Value N A Table 4 6 PI PIC32 USB STATUS Register Bits Field name Function Initial Value 31 USB Reserved USB device interrupt This field is set to 1 0x0 when usb device need to interrupt cpu INTID2 PIC32 GPIO Port B interrupt pin INTID1 INTIDO PIC32 GPIO Port A interrupt pin PIC32 SPI interrupt pin IORDY 4 1 7 SW Endian Register Name PI_SOFTENDIAN Address Ox1F00 0070 Access R W RO Reset Value N A This field indicates that the pending PIC32 oper ation has been completed and a status byte is available in the PIC32 interface read buffer at address 0 Table 4 7 PI SOFTENDIAN Register SOFTCONTROL Software control of Endianness and EIC Mode Ox1 is supported RO CFGPRESENT SEAD 3 CFG register is preset at 0x1b10 0110 RO 29 3 Reserved N A 2 EICPresent This field is set t2. 256 Mbytes DDR2 SDRAM SODIMM memory 0x1000 0000 176 Mbytes DDR2 SDRAM SODIMM memory accessible only when 512MB single rank SODIMM is used 0x1B00 0000 1 Mbyte DDR2 SDRAM controller registers 0x1B 10 0000 1 Mbyte SEAD 3 CFG and GIC registers 0x1B20 0000 1 Mbyte USB HS 2 0 OTG registers 0x1B30 0000 13 Mbytes Reserved 0x 1C00 0000 32 Mbyte Flash memory 0x 1E00 0000 4 Mbytes SRAM memory 0x1E40 0000 4 Mbytes SRAM memory if available 0x 1E80 0000 8 Mbytes Reserved 0x 1F00 0000 512 bytes Peripheral bus controller internal registers 0x 1F00 0200 56 bytes P SWITCH F SWITCH P LED F LED NEWSC LIVE NEWSC REG NEWSC CTRL Reserved Ox1F00 0240 448 bytes Reserved Ox1F00 0400 16 bytes LCD Data register Ox1F00 0410 8 bytes CPLD LCD Status register Ox1F00 0418 8 bytes CPLD LCD Data register Ox1F00 0480 8 bytes Device Reset register Ox1F00 0500 256 bytes Reserved Ox1F00 0600 256 bytes PIC32 device Ox1F00 0700 256 bytes Reserved Ox1F00 0800 256 bytes UART 0 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 15 Memory Map and Register Access Rules Table 3 1 SEAD 3 Physical Memory Map Continued Base address Size Function 0x1F00 0900 256 bytes UART 1 0x 1F00 0A00 62 Kbytes Reserved Ox1F01 0000 64 Kbytes ETHERNET device Ox1F02 0000 3 896 Mbytes Reserved Ox1F40 0000 4 Mbytes USER Board Ox1F80 0000 2 Mbytes Reserved FPGA ROM space Ox1FA0 0000 6 Mbytes SW EPROM Boot PROM memory REVISION registe
3. MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 29 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Peripheral Bus Controller 4 2 10 Device Reset Register Name PI DEVRST Address 0x1F00 0480 Access WO Reset Value 0x0 The CPU USB can reset pic32 by writing 0x01 to PI DEVRST register and pic32 can be brought out of reset by writing 0x0 to PI DEVRST register Table 4 17 PI DEVRST register Bits Field name Function Initial Value 31 1 Reserved NA 0 PIC32_RST 0 assert PIC32 reset 0 1 deassert PIC32 reset 4 2 11 UARTs UART O address base 0x1F00 0800 UART 1 address base Ox1F00 0900 The registers of the UARTS which have a native width of 8 bits are all memory mapped on 64 bit aligned boundaries as follows Table 4 18 UART Registers Name Offset Address Access Function RXTX 0x0000 0000 R W Receive Transmit char register INTEN 0x0000 0008 R W Interrupt enable register IIFIFO 0x0000 0010 R W Read Interrupt identification Write FIFO control LCTRL 0x0000 0018 R W Line control register 4 18 1 MCTRL 0x0000 0020 R W Modem control register 4 18 2 LSTAT 0x0000 0028 R W Line status register 4 18 3 MSTAT 0x0000 0030 R W Modem status register 4 18 4 SCRATCH 0x0000 0038 R W Scratch register 1 The Divisor Latch registers are accessible through RXTX and INTEN registers when bit 7 Divisor Latch Access Bit of the Line Control Register is set 30 MIPS
4. SEAD 3 Basic RTL User s Manual Revision 01 00 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Chapter 5 DDR2 SDRANM Controller The SEAD 3 Basic RTL uses the DDR2 SDRAM controller from Xilinx The DDR2 SDRAM is not full featured with respect to all the different configurations of DDR2 SDRAM SODIMMs on the market but is limited to support single rank sided SODIMMs only In order to use the complete DRAM address space on SEAD 3 board a 512 MByte single rank SODIMM is required Figure 5 1 DDR2 SDRAM Controller Block Diagram XILINX CPU Master DDR2 SDRAM X Bus X bus T t 0 Controller eee oc DDR2 SDRAM Q cr ui Interface App Bus cc Si DDR2 Bus LLI O E Controller E e lt O Master t 5 5 USB 2 0 HS ui 9 gt Controller 2 a Figure 5 1 illustrates SEAD 3 Basic RTL implementation of DDR2 SDRAM module There are two master data ports and one master register port in the interface controller The CPU accesses the memory controller from a master data port or a master register port USB access to the memory controller is only from a master data port CPU access DDR2 SDRAM Interface controller registers from a register port All data port accesses are forwarded to the Xilinx DDR2 SDRAM controller USB will have highest priority to access memory only exception is when cpu has started a burst read or write transaction The DDR2 SDRAM controller can be accesse
5. Internal Datapath 13 Figure 4 1 Default Access Timing for Peripheral Bus Devices u 20 Figure 5 1 DDR2 SDRAM Controller Block Diagram WI 31 Figure 6 1 USB HS 2 80 Controller Block Diagrama uu a ete t rete ees tta eee vo tatu vas EE 35 Figure Z T Intermiptinterface AA 38 MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 5 Copyright 2009 2010 MIPS Technologies Inc All rights reserved MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 Copyright 2009 2010 MIPS Technologies Inc All rights reserved List of Tables Table 2 1 SEAD 3 X bus Controller First level Address Map 11 able 312 SEAD S9 Physical Memory Mai AA 15 Table 3 2 SEADIS GFO ET 17 Table4 1 Pl TIMOMMPER E EE 21 Table 4 2 PI MEET LLL IR yeu Diaeta aeree sso aeta aed rase KAKA HOHER REM 22 Table 4 3 PILNMISTATUS Register u u uu ee nct te nk EN dd PARK d 23 Table 4 4 PI NMIAGI register 1 00000 23 Table 4 5 TER E 23 Table 4 6 PI PIG32 USB STATUS iii 24 Table 4 7 P SOFTENDIAN Regisie r AWE YR MUR RR RR 24 Bio er Me 25 Tablets FSWITGIH TE E 26 Tape a ll Re TEE 26 Table 4 4112 Ee 27 Table dE EE Ee EE 27 Table NEWSCREG RE EE 28 Table 4 14 Ee EE 28 Table 05 REVISION Register uuu E 29 Table4 16 ASGII Display E 29 Table 4 17 X d
6. SDRAM controller 0x0 1B00 0000 0x0 1BOF FFFF X bus 0 DDR2 SDRAM controller 0x0 1B10 0000 0x0 1B1F FFFF X bus 1 GIC 0x0 1B20 0000 0x0 1B2F FFFF Registers X bus 42 USB HS 2 0 OTG 0x0 1B30 0000 0x0 1 BFF FFFF Reserved 0x0 1C00 0000 0x0 1 EFF FFFF X bus 3 Peripheral bus controller 0x0 1F00 0000 0x0 1F00 01FF Registers X bus 3 Peripheral bus controller 0x0 1F00 0200 0x0 1 FFE FFFF Data X bus 3 Peripheral bus controller The X bus controller only decodes address bits 28 20 in the case of target 3 register decode bits 28 9 in order to map the accesses to the correct target ports Because the EC interface address bits 35 29 or AHB or OCP interface address bits 31 29 are not included in the address decoding the address segment 0x0 0000 0000 0x0 1FFF FFFF will be mirrored to 0x0 2000 0000 0x0 3FFFF FFFF and 0x0 4000 0000 0x0 5FFF FFFF etc In CPUs with a fixed mapping MMU the virtual base address of the user segment useg kuseg 0x0 0000 0000 maps to physical base address 0x0 4000 0000 which will be mirrored to address 0x0 0000 0000 in the SEAD 3 Basic RTL The kseg0 and kseg kernel segments both map to the physical address segment 0x0 0000 0000 0x0 1FFF FFFF so care should be taken in order to avoid mirroring user code and data onto the same physical addresses as the kernel code and data User code should therefore not be linked to virtual base address 0x0 0000 0000 but should be linked to some h
7. bus except the SRAM which has its own timing register PI TIMSRAM The slowest device on the peripheral bus thus dictates the timing of all the remaining devices except for the SRAM The default value assumes that the system is not run ning faster than 83 MHz All field values are interpreted as a number of clock cycles counting from the access start time as illustrated for the PI TIMOTHER default values in Figure 4 1 Table 4 1 PI TIMOTHER Register Bits Field name Function Initial Value Address and write data hold time Legal values CS2 1 to 63 inclusive Write enable deassertion time Legal values WE1 1 to ADH 1 inclusive Write enable assertion time Legal values CS1 1 to WE2 1 inclusive Read strobe deassertion time Legal values RD1 1 to ADH 1 inclusive Read strobe assertion time Legal values CS1 1 to RD2 1 inclusive Chip select deassertion time Legal values max RD2 WE2 1 to ADH 1 inclusive Chip select assertion time Legal values 0 to min RD1 WE1 1 inclusive MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 21 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Peripheral Bus Controller 4 1 2 SRAM Timing Parameters Name PI TIMSRAM Address 0x1F00 0010 Access R W Reset Value 0x30703824 The PI TIMSRAM register controls the timing of accesses to the SRAM All field values are interpreted as a number of clock cycles counting from the access star
8. however we need a mux because each X bus target has its own read data bus Timing is relaxed by adding a level of registers on the read data path but no changes are needed in the control protocol logic The control logic is quite complex see 2 MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 Copyright 2009 2010 MIPS Technologies Inc All rights reserved EC AHB OCP Interface 2 3 X Bus Controller Internal Architecture Figure 2 1 EC AHB OCP to X bus Controller Internal Datapath EC AHB OCP address bus EC AHB OCP read data bus EC AHB OCP to X bus controller optional output flops X bus MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 shared address bus shared write data bus Individual read data busses for each X bus target Copyright 2009 2010 MIPS Technologies Inc All rights reserved 13 X Bus Controller 14 MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Chapter 3 Memory Map and Register Access Rules The default physical memory map as seen from the CPU core is shown in Table 3 1 below This map can be modified by users no mapping restrictions are imposed by hardware MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 Base address Table 3 1 SEAD 3 Physical Memory Map Size Function 0x0000 0000 32
9. numbers give the RTL revmajor version as RTLMAJ RTLMIN RTLMIN For example if RTLMAJ 1 and RTLMIN revminor 24 then the SEAD 3 Basic RTL version is 1 24 4 bit binary number gives board ID 4 bit binary number gives board revision The REVISION register is used by the YAMON ROM monitor to identify the board and RTL The PROID and PRORV fields are read from the external peripheral bus while the RTLID RTLMAJ and RTLMIN fields are sup plied by the peripheral bus controller RTL 4 2 9 2 line 16 character Alphanumeric LCD Display ASCII Address Base Ox1F00 0400 The registers are 8 bits wide and are used to display characters LCD Status and Data register reside in the CPLD Table 4 16 ASCII Display Registers Name Offset Address Access Function LCD Read Write Control 0x0000 0000 R W LCD read write control register LCD Read Write Data 0x0000 0008 R W LCD read write data register CPLD LCD Status 0x0000 0010 RO 8b wide register bit 7 reflects lcd data port bit7 bit 1 is a 10ms pulse used in linux kernel to calculate cpu frequency bit 0 is the BUSY bit when set to 1 it indicates that LCD controller is busy processing a read write transaction CPLD LCD Data 0x0000 0018 RO ASCII character in position 3 See the documentation from HP for additional information on how to program the HDSP 2532 ASCII display The RTLMAJ and RTLMIN constants are defined in the synthesis Makefile
10. positive edge of the global clock There are no latches no tri states no asynchronous resets no gated clocks or other design practices that make implementing an ASIC difficult MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Chapter 2 X Bus Controller The X bus controller supports either an EC AHB or OCP front end interface and four X bus master ports as illus trated in Figure 1 1 Although four separate busses are shown in the Figure the address bus and write data bus origi nating from the X bus controller are actually shared between the X bus targets However in order to avoid tri state busses each of the four targets has its own read data bus As a build time option the user can select either an EC AHB or OCP based bus on the CPU bus interface 2 1 First level Address Mapping The X bus controller contains a fixed hardcoded first level address mapping which maps the physical address space from the CPU to the X bus ports An X bus may be used for data transfers typically memories and or register accesses For X busses with both types of functions the X bus controller decodes two segments The address map ping is shown in Table 2 1 Table 2 1 SEAD 3 X bus Controller First level Address Map Physical Address Range Type Function 0x0 0000 0000 0x0 0FFF FFFF X bus 0 DDR2 SDRAM controller 0x0 1000 0000 0x0 1 AFF FFFF Data X bus 40 DDR2
11. state of the host device controller Refer to the Synopsys document C113420 CI13520 C115620 CI13720 IPCS PM HighSpeedControllerCore 20A pdf for a detailed descriptions of all registers 36 MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Chapter 7 Interrupt Controller The SEAD 3 Basic RTL supports an interface to the MIPS Global Interrupt Controller GIC The GICPresent bit in the SEAD3 CFG register 0x1B10 0110 indicates the presence or absence of the GIC When the GIC option is not selected board and controller interrupts are directly mapped to processor interrupts as shown in Table 7 1 Table 7 1 Direct Mapped Interrupt Scheme System Interrupts Description CPU Interrupts PIC32 gpioa gpiob spi USB Interrupts from PIC32 and USB controller SI Int 0 I2C RTC Interrupt from Real Time Clock on I2C bus SI Int 1 uart 0 uart 1 UART interrupts on Peripheral bus SI Int 2 NEWSC Switch Activity detected on NEWSC switch SI Int 3 Ethernet Interrupt from Ethernet controller SI Int 4 SI TimerInt Timer Interrupt from processor SI Int 5 7 1 MIPS Global Interrupt Controller GIC Interface The Global Interrupt Controller GIC is mapped to X bus Target 1 address space see Chapter 3 Memory Map and Register Access Rules on page 15 The GIC base address on the SEAD 3 board is 0x1B1C 0000 The GIC is configured as follows 1 VPE 24 glob
12. the use duplication reproduction release modification disclosure or transfer of this information or any related documentation of any kind is restricted in accordance with Federal Acquisition Regulation 12 212 for civilian agencies and Defense Federal Acquisition Regulation Supplement 227 7202 for military agencies The use of this information by the Government is further restricted in accordance with the terms of the license agreement s and or applicable contract terms and conditions covering this information from MIPS Technologies or an authorized third party MIPS MIPS I MIPS II MIPS III MIPS IV MIPS V MIPS 3D MIPS16 MIPS16e MIPS32 MIPS64 MIPS Based MIPSsim MIPSpro MIPS Technologies logo MIPS VERIFIED MIPS VERIFIED logo 4K 4Kc 4Km 4Kp 4KE 4KEc 4KEm 4KEp 4KS 4KSc 4KSd M4K MIAK 5K 5Kc 5Kf 24K 24Kc 24Kf 24KE 24KEc 24KEf 34K 34Kc 34Kf 74K 74Kc 74Kf 1004K 1004Kc 1004Kf R3000 R4000 R5000 ASMACRO Atlas At the core of the user experience BusBridge Bus Navigator CLAM CorExtend CoreFPGA CoreLV EC FPGA View FS2 FS2 FIRST SILICON SOLUTIONS logo FS2 NAVIGATOR HyperDebug HyperJTAG JALGO Logic Navigator Malta MDMX MED MGB microMIPS OCI PDtrace the Pipeline Pro Series SEAD SEAD 2 SmartMIPS SOC it System Navigator and YAMON are trademarks or registered trademarks of MIPS Technologies Inc in the United States and other countries All other trademarks referred to herein are the pr
13. 1 1 1 1 esee itai aon races etae Price ER euer nih at Made dE xa Edd 25 Zo TA EUREN 25 42 2 UN e 26 Lp 3 AE A A A 26 4 2 4 P LED EE 27 eH ccm mE 27 425 NEWSGSREG is i dns ese telis ta duu iptui ee 28 42 1 NE WI GTR E 28 4 2 8 REVISION rM TU 29 4 2 9 2 line 16 character Alphanumeric LCD Display Au 29 4 2 10 Device Reset REGISICR EE 30 42 UA EE 30 Chapter 5 DDR2 SDRAM Controller ua 31 e BE EE EE 32 5 1 1 DDR2 SDRAM Presence Detected Configuration miwa 32 5 1 2 DDR2 SDRAM Presence Detected Read Address Register 32 5 1 3 DDR2 SDRAM Presence Detected Transfer Register a 33 Chapter 5 USB RS 2 0 2 2 12 12 2 2 2 2 12 1 1 1 1 1 7 35 MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 3 Copyright O 2009 2010 MIPS Technologies Inc All rights reserved pd GCPW accessible EEN EE 35 Chapter 7 Interrupt CON Aa 37 7 1 MIPS Global Interrupt Controller GIO Intel fag aa 37 Appendix A Fleferences 1 1 2 2 21 2 2 2 2 2 2 2 2 2 2 2 2 2 sssssassssasssspasasssasasasaawanasaspassssasassasa 39 Appendix B Revision HIStopy 2 12 2 2 12 212 2 2 2 2 2 2 2 2 2 2 2 2 2 202 Bas 41 4 MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 Copyright 2009 2010 MIPS Technologies Inc All rights reserved List of Figures Figure tai SEAD S Basic RTE Block DI iii EE 10 Figure 2 1 EC AHB OCP to X bus Controller
14. B Registers Slave accesses from the CPU enables access to the configuration control and status registers The USB register base address is 0x1b20 0000 Register offset definitions are listed in Table 6 1 below Configuration control and status registers are divided into three categories identification capability and opera tional MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 35 Copyright 2009 2010 MIPS Technologies Inc All rights reserved USB HS 2 0 Controller Identification registers are used to declare the slave interface presence along with complete set of the hardware con figuration parameters Static read only registers define the software limits restrictions and capabilities of the host device controller Operational registers consists of dynamic control and status registers that may be read only read write or read write to clear EHCI registers are listed along side device registers to show the complementary nature of host and device control Host mode EHCI compatibility registers begin at offset 0x100 Table 6 1 USB Slave Interface Register Sets Base at 0x1b20 0000 Address Otfset Register Set Function 0x000 to OxOFC Identification Registers Slave Interface Presence Hard ware configuration parameters 0x100 to Ox124 Capability Registers Capabilities limits and restrictions of a host device controller imple mentation 0x140 to OXIFC Operational Registers Control and monitor operational
15. D SPDCNF Address Ox1B00 0040 Access R W Reset Value 0x00000000 Table 5 2 SD SPDCNF Register 9 0 0x0 CPDIV Clock Down Scale Factor This register must be set by software to specify the clock down scale for the Serial Presence Detect controller The SPD controller must run at a lower clock frequency to provide safe timing margins at the serial interface To achieve a safe clock rate to the EEPROM CPDIV should be set to 10 gclk frequency in MHz for example gclk 83Mhz gt CPDIV 830 5 1 2 DDR2 SDRAM Presence Detected Read Address Register Name SD_SPDADR Address 0x1B00 0048 Access R W Reset Value 0x00000000 Table 5 3 SD_SPDADR register Bits Field name Function Initial value 31 8 Reserved NA 7 0 RDADR Read Address 0x0 The SD SPDCNF register must be set before accessing this register 32 MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 5 1 CPU Accessible Registers 5 1 3 DDR2 SDRAM Presence Detected Transfer Register Name SD_SPDDAT Address 0x1B00 0050 Access RO Reset Value 0x00000000 Table 5 4 SD_SPDDAT Register Bits Field name Function Initial value 31 10 Reserved NA 9 RDERR Missing acknowledge from EEPROM 0x0 8 BUSY Read Access in progress 0x0 7 0 RDATA Read Data 0x0 The SD SPDCNF register must be set before accessing this register Software can read DDR2 SDRAM SODI
16. E QUAS RK AER 30 Table 4 18 e RE 30 Table 5 1 DDR2 SDRAM Controller Module Registers BASE 0x1B00 0000 32 Table 5 2 SD _SPDGNF R8gi ler 0000 32 Table 53 SD SPDADH ET 32 Table 54 SD_SPDDAT e EE 33 Table 6 1 USB Slave Interface Register Sets Base at 0x1b20 0000 wazima 36 Table 7 1 Direct Mapped Interrupt Scheme n 37 Table 712616 Global Interrupt Source Pin Mapping ii 38 MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 7 Copyright O 2009 2010 MIPS Technologies Inc All rights reserved MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Chapter 1 Introduction This document describes the capabilities of the SEADTM 3 Basic RTL source code included in the MIPS SEAD 3 Basic Package as seen from the programmer s point of view This source code is a sample design which interfaces to the CPU core and implements all necessary control logic for the external resources including SDRAM The SEAD 3 Basic RTL is intended for demonstration purposes and as inspiration for the user It enables the user to bring up the board as a fully functional CPU system and to to exercise the board s functionality while developing their own RTL Note that future versions of the SEAD 3 Basic RTL may be totally different from the current version and MIPS does not support any user modifie
17. I NMI signal This ensures that the CPU takes an NMI exception whenever an illegal write access is detected by the Basic RTL Illegal read accesses are signalled on the EC AHB OCP interface using the read bus error signal See also Section 3 2 Accesses to Illegal Reserved Addresses The interrupt lines from the UARTS are also part of the peripheral bus these are connected to the interrupt controller source and are simply passed through the SEAD 3 Basic RTL directly to the interrupt lines on the CPU Interrupt mapping is described in Chapter 7 Interrupt Controller on page 37 MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 19 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Peripheral Bus Controller All the registers and programming details for the external devices attached to the peripheral bus are listed in section Section 4 2 External Peripheral Bus Registers below 4 1 Peripheral Bus Controller Internal Registers The peripheral bus is a simple asynchronous non burst bus which has the following data and control signals e PI A 24 0 address bus e PI D 31 0 bidirectional data bus PI SEL 4 0 device select mapped from address PI CS N common chip select e PI RD N read strobe PI BE N 3 0 byte enable strobes Figure 4 1shows the basic timing of read and write accesses back to back read followed by write for all devices on the peripheral bus except SRAM Figure 4 1 Default A
18. MM configuration data from the SODIMM Serial EEPROM in this register To do so the software must write the desired read byte address to the SD SPDADR register This will trigger the SPD controller to read data from this address in the SODIMM EEPROM while processing the BUSY bit is set to one When the BUSY bit has returned to zero read data will be presented in the RDATA field The RDERR bit is set if read data is corrupted MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 33 Copyright 2009 2010 MIPS Technologies Inc All rights reserved DDR2 SDRAM Controller 34 MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Chapter 6 USB HS 2 0 Controller The SEAD 3 Basic RTL supports the BVCI interface to the Synopsys USB HS 2 0 OTG controller The USB HS 2 0 Interface controller has one master port and one slave port CPU accesses USB HS 2 0 controller registers using slave port Master port is used for memory data transfer Figure 6 1 illustrates the interface of US HS 2 0 OTG controller Figure 6 1 USB HS 2 0 Controller Block Diagram Synopsys USB HS 2 0 USB BVCI Controller Interface Controller EC AHB OCP Bus USB X BUS Slave X BUS Interface Controller TARGET VUSBHS CORE X bus USB DDR2 Target 0 Master Interface X bus USB DDR2 SDRAM Controller INITIATOR DDR2 SDRAM Bus Dual Port SRAM 6 1 CPU accessible US
19. Mis TECHNOLOGI MIPS SEAD 3 Basic RTL User s Manual Document Number MD00693 Revision 01 00 March 10 2010 MIPS Technologies Inc 955 East Arques Avenue Sunnyvale CA 94085 4521 Copyright O 2009 2010 MIPS Technologies Inc All rights reserved Copyright 2009 2010 MIPS Technologies Inc All rights reserved Unpublished rights Gif any reserved under the copyright laws of the United States of America and other countries This document contains information that is proprietary to MIPS Technologies Inc MIPS Technologies Any copying reproducing modifying or use of this information in whole or in part that is not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly prohibited At a minimum this information is protected under unfair competition and copyright laws Violations thereof may result in criminal penalties and fines Any document provided in source format i e in a modifiable form such as in FrameMaker or Microsoft Word format is subject to use and distribution restrictions that are independent of and supplemental to any and all confidentiality restrictions UNDER NO CIRCUMSTANCES MAY A DOCUMENT PROVIDED IN SOURCE FORMAT BE DISTRIBUTED TO A THIRD PARTY IN SOURCE FORMAT WITHOUT THE EXPRESS WRITTEN PERMISSION OF MIPS TECHNOLOGIES INC MIPS Technologies reserves the right to change the information contained in this document to improve function design or otherwise MIPS Tech
20. P to X Bus Controller FEE Optional DDR2 Bus UPLI Bus All the blocks shown in the figure are described in detail in later chapters of this document The CPU has access to four slaves that are mapped to the X bus the Peripheral bus controller DDR2 SDRAM con troller Global Interrupt Controller and US HS 2 0 OTG controller The X bus is a 32 bit fully synchronous sin gle master multi target non tristate bus see 2 for details The DDR2 SDRAM controller can be accessed from the USB or CPU USB has the higher priority though if the CPU is in the middle of a burst access USB must wait until the burst trasaction is complete In the Basic RTL all blocks other than Peripheral bus controller and the EC AHB OCP to X bus controller are optional and must be selected as build time options To select an internal MIPS CPU users must have access to the RTL source for the MIPS32 M14K CPU The Basic RTL will select a external CPU module when present on the CoreBus connector The Basic RTL provides an interface to the Xilinx DDR2 SDRAM controller and Synopsys USB HS 2 0 OTG con troller The user must have access to the RTL for the respective option if they are selected in the build Interrupts on the board are directly mapped to processor interrupts when the Global Interrupt Controller option is not selected See Chapter 7 Interrupt Controller on page 37 The Basic RTL is a fully synchronous design all flops are clocked on the
21. PI NMISTATUS FLAG bit is set The CPU can also check the WERR bit to see whether the NMI exception was generated by an ille gal write access or by the user pressing the ON OFF push button 22 MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 4 1 Peripheral Bus Controller Internal Registers The CPU can clear both PI NMISTATUS bits by writing a 1 to register PI NMIACK see section Section 4 1 4 NMI Interrupt Acknowledge Register Pressing the ON OFF button will only generate an NMI interrupt if PI NMISTATUS is cleared If the ON OFF button is kept pressed for more than two seconds the SEAD 3 board will power off This is controlled by a on board timer and does not depend on the system frequency nor the Basic RTL Table 4 3 PI NMISTATUS Register Reserved WERR Write access error 0x0 no write access error 0x1 write access error 0 FLAG Latched NMI status 0x0 after cold reset Ox1 after NMI reset 1 In this case Initial value is the value the CPU sees after any reset including NMI exceptions 4 1 4 NMI Interrupt Acknowledge Register Name PI NMIACK Address Ox1F00 0048 Access WO Reset Value N A The CPU can clear the two PI NMISTATUS bits by writing a 1 to register PI NMIACK see also section Section 4 1 3 NMI Interrupt Latch Status Register Table 4 4 PI NMIACK register Bits Field name Function Initial Value
22. al interrupt sources Supports EIC or direct mapping Local Software Timer and Performance Counter interrupts Refer to the MIPS Global Interrupt Controller User s Manual 4 for a description of the GIC and programming details Figure 7 1 illustrates the SEAD 3 Basic RTL interface to the GIC The EIC Mode in the GIC is disabled on reset Software can enable EIC mode by setting the EICPresent bit in the Soft Endian Register Writes to this register reset the board and on resumption software can enable EIC Mode in the GIC MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 37 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Interrupt Controller Figure 7 1 Interrupt Interface to GIC X BUS Controller X Bus Target 1 MIPS Global Interrupt Controller GIC Processor Internal Interrupt System Y Controller Interrupts GIC INT Interrupts SI EICPresent Soft Endian Register System and processor interrupts are mapped to the GIC source pins as shown in Table below Table 7 1 GIC Global Interrupt Source Pin Mapping Global Interrupt System Interrupt Source PIC32 GPIO Port A Interrupt GIC_Int 8 PIC32 GPIO Port B Interrupt GIC_Int 7 PIC32 SPI Interrupt GIC_Int 6 USB HS 2 0 Controller Interrupt GIC_Int 5 I2C RTC Interrupt GIC_Int 4 UART device 1 Interrupt GIC_Int 3 UART device 0 Interrupt GIC_Int 2 NEWS Switch Inter
23. ccess Timing for Peripheral Bus Devices gclk gcik cyce g 0 1 23 4561 7 81 01112313415161 71 8 E PI A 24 0 EH read address valid write address valid ES PI SEL 4 0 E read select valid write select valid mi PI D 31 0 write data valid Pl CSN lt a PI RD N PI BE N 3 0 1111 asserted 1111 The Peripheral bus controller contains two bus timing registers with identical layout the first register controls the bus timing for SRAM accesses and the other register is a common bus timing register for all the other devices on the peripheral bus It is therefore possible to use a fast access timing for the SRAM while having a slow timing for the remaining devices The gclk cycle counter in Figure 4 1 illustrates how an internal access counter is used to control when to assert de assert the various peripheral bus control signals This counter equals the ADH field of the timing register in the 1 The interrupt lines from the UARTs PI UART n INT N are also part of the peripheral bus but they are not related to the peripheral bus accesses In the Basic RTL they are wired directly to the CPU interrupt lines 0 and 1 20 MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 Copyright 2009 2010 MIPS Technolog
24. d RTL The SEAD 3 Basic RTL is therefore delivered as is This document assumes that the reader has read the the SEADTM 3 Basic RTL Reference Manual 1 the SEAD 3 Board User s Manual 2 and SEAD 3 Board Getting Started 3 1 1 Features The SEAD 3 Basic RTL code implements the following features Interface to the CPU core bus EC AHB OCP interface for 32 bit CPUs Interface to Xilinx DDR2 SDRAM controller e Peripheral bus controller Interface to Synopsys USB HS 2 0 OTG controller Interface to MIPS Global Interrupt Controller All the RTL code is written in Verilog The Basic RTL and YAMON ROM monitor support dual endianness without any need to recompile The RTL can be compiled for a 32 bit CPU The SEAD 3 Basic RTL has two clock domains The DDR2 SDRAM controller is in domain 1 and all other modules are in domain 2 the DDR2 SDRAM controller domain is synthesized to run upto 266 MHz and the maximum fre quency of domain 2 is 83 MHz 1 2 Block Diagram A block diagram of the Basic RTL is shown in Figure 1 1 The SEAD 3 Basic RTL requires that the domain 1 supplied frequency is half the domain frequency MHz MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 9 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Introduction Figure 1 1 SEAD 3 Basic RTL Block Diagram Board Interrupts Peripheral Bus Peripheral Controller Bus EC AHB OCP EC AHB OC
25. d from the USB or CPU USB has the higher priority though if the CPU is in the middle of a burst access USB must wait until the burst trasaction is complete USB access will then have to wait for burst transaction to complete in the interface controller The transaction is sig nalled as complete when it is forwarded to the DDR2 SDRAM controller The RTL source User Guide and imple mentation details can be obtained from www xilinx com Memory Interface Generator MIG utility is invoked from Xilinx Coren to generate DDR2 Controller DDR2 controller is configured to work with Micron SODIMM mt4htf3264hy_667 However controller has been tested using SODIMM single rank upto 512MB CAS 5 from other vendors MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 31 Copyright 2009 2010 MIPS Technologies Inc All rights reserved DDR2 SDRAM Controller 5 1 CPU Accessible Registers The internal register maps and programming details for the DDR2 SDRAM device installed in the DDR2 SDRAM SODIMM socket are listed in Table 5 1 The DDR2 SDRAM controller module has 53 presence detection registers that are accessible by the CPU via the X bus Table 5 1 DDR2 SDRAM Controller Module Registers BASE 0x1B00 0000 SD_SPDCNF 0x0040 R W Presence Detect Configuration SD_SPDADR 0x0048 R W Presence Detect Read Address register SD_SPDDAT 0x0050 RO Presence Detect Read Data register 5 1 1 DDR2 SDRAM Presence Detected Configuration Name S
26. er implementation The X bus targets will generally signal read bus error to the master in case of illegal read accesses The master will forward any read bus error to the CPU via the EC AHB OCP interface which will take an exception In order to make sure that any illegal write access is noticed all the X bus targets are required to issue a write access error pulse to NMI logic in the peripheral bus con troller when they detect an illegal write access The NMI logic forces the CPU to take an NMI exception when a write access error pulse from any of the targets is detected see section Chapter 3 Memory Map and Register Access Rules on page 15 3 3 Register Macros Though explicit addresses are listed in the following sections it is recommended to use the macros in the sead h header file which is included with the YAMON source code Note that all register defines in this header file are pre fixed with SEAD to be able to easily distinguish these hardware specific defines from other defines 16 MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 3 4 Alignment 3 4 Alignment All registers are addressed as 32 bit words on 64 bit word boundaries This convention prevents any problems due to Endianness see the X bus specification in 2 for details 3 5 Reserved Bits Register bits marked as reserved are reserved for future use T
27. es 18 MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Chapter 4 Peripheral Bus Controller The Peripheral bus controller connects the CPU to all SEAD 3 peripherals on the external peripheral bus The peripheral bus is a simple asynchronous no handshake non burst bus The following peripherals are connected to the SEAD 3 peripheral bus 6MByte SW PROM Boot EPROM 32 MByte Flash 4 MByte SRAM e 16 software readable DIP switches P SWITCH F SWITCH 6 bar software controlled LEDs P LED F LEDs e 2 line 16 character alphanumeric LCD display PIC32 device that controls DC SPI ADC GPIO interface Ethernet controller CPLD board controller 2UARTs TL16C550 Board part of REVISION register Note that the peripheral bus on the SEAD 3 board can be disconnected from the FPGA by means of configurable CBT switches This is described in 2 The peripheral bus access timing can be programmed via two internal registers in the Peripheral bus controller The Peripheral bus controller also handles the NMI interrupt debouncing latching and the board reset These registers are all described in section Section 4 1 Peripheral Bus Controller Internal Registers below Each of the X bus targets in the Basic RTL outputs a write access error pulse signal to logic residing in the Periph eral controller module which ORs all these signals onto the S
28. he peripheral bus Table 4 9 FSWITCH Register Bits Field name Function Initial Value 31 8 Reserved N A 7 0 VAL 8 F SWITCH bits physical switches are num N A bered 8 to 1 0 OFF Open 1 ON Closed 4 2 3 P LED Name PLED Address Ox1F00 0210 Access R W Reset Value 0x00000000 The PLED register allows software to program the state of the 8 P LED bits on the peripheral bus Table 4 10 PLED Register Bits Field name Function Initial Value 31 8 Reserved NA 7 0 VAL 8 bits corresponding to the 8 P LED bits 0x0 0 Off all P LED bits off 1 On MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 4 2 External Peripheral Bus Registers 4 2 4 F LED Name FLED Address Ox1F00 0218 Access R W Reset Value 0x00000000 The FLED register allows software to program the state of the 8 F LED bits on the peripheral bus Table 4 11 FLED Register Bits Field name Function Initial Value 31 8 Reserved NA 7 0 VAL 8 bits corresponding to the 8 F LED bits 0x0 0 Off all P LED bits off 1 On 4 2 5 NEWSC LIVE Name NEWSC LIVE Address 0x1F00 0220 Access RO Reset Value N A The NEWSC LIVE register allows software to read the present state of NEWSC switch This is an 8 bit wide regis ter Table 4 12 NEWSC LIVE Register 7 5 Reserved N A sw cpld n Switch position North N A Switch position Ea
29. ies Inc All rights reserved 4 1 Peripheral Bus Controller Internal Registers last clock cycle of a peripheral bus access see Section 4 1 2 SRAM Timing Parameters and Section 4 1 1 Timing Parameters for Other External Peripherals The default timing for accessing all peripherals except the SRAM is as follows For both read and write accesses PI A and PI SEL are valid one clock cycle before PI CS N is asserted and stay valid until one clock cycle after PI CS N is deasserted For read accesses the read data is sampled when PI RD N is deasserted at the end of cycle 6 in Figure 4 1 above so the read data does not have to be valid until the last asserted cycle of PI RD N For write accesses the write data is valid when PI CS N is asserted and stays valid until one clock cycle after PI CS N is deasserted The write strobes PI WE N are deasserted one clock cycle after PI CS N and are deasserted one clock cycle before PI CSN This behavior can be changed by modifying the contents of the PI TIMOTHER register But note that it is pos sible to program access timing setups which will not work in practice so care should be taken when the periph eral bus timing is changed from the default 4 1 1 Timing Parameters for Other External Peripherals Name PI TIMOTHER Address Ox1F00 0020 Access R W Reset Value 0x61469354 The PI TIMOTHER register controls the timing of accesses to all external peripherals on the peripheral
30. igher address which is certain not to be mirrored onto kernel code and data MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 11 Copyright 2009 2010 MIPS Technologies Inc All rights reserved X Bus Controller 2 2 DDR2 SDRAM at Start of Memory Because all exception vectors are located at the bottom of memory following boot some sort of memory device must be mapped to the beginning of the physical address space In the SEAD 3 Basic RTL memory device mapping is selected by the sram map zero switch on the SEAD 3 board Switch position sram map zero ON will map SRAM to physical address 0x0 DDR2 SDRAM is mapped to the beginning of memory address 0x0 when this switch posi tion is OFF If the DDR2 SDRAM option is not selected during build then SRAM will be mapped to zero regardless of the switch position 2 3 X Bus Controller Internal Architecture The X bus controller separates read and write requests in such a way that it permits simultaneous outstanding reads on one port and active write requests on another port The data path of the X bus controller is illustrated in the Figure 2 1 Address and write data originating from the EC AHB OCP interface is either directly output to the addressed X bus target through an optional set of output flops to improve timing or it is saved in registers until it can be accepted by the X bus target Read data returned from an X bus target is simply passed directly to the EC AHB OCP interface
31. nologies does not assume any liability arising out of the application or use of this information or of any error or omission in such information Any warranties whether express statutory implied or otherwise including but not limited to the implied warranties of merchantability or fitness for a particular purpose are excluded Except as expressly provided in any written license agreement from MIPS Technologies or an authorized third party the furnishing of this document does not give recipient any license to any intellectual property rights including any patent rights that cover the information in this document The information contained in this document shall not be exported reexported transferred or released directly or indirectly in violation of the law of any country or international law regulation treaty Executive Order statute amendments or supplements thereto Should a conflict arise regarding the export reexport transfer or release of the information contained in this document the laws of the United States of America shall be the governing law The information contained in this document constitutes one or more of the following commercial computer software commercial computer software documentation or other commercial items If the user of this information or any related documentation of any kind including related technical data or manuals is an agency department or other entity of the United States government Government
32. o ensure software compatibility with future versions of the SEAD 3 Basic RTL software should always write 0 to reserved bits and ignore reserved bits on reads Reserved bits will return 0 on reads however this may change in future versions of the SEAD 3 Basic RTL 3 6 SEAD3 CFG Register Name SEAD3_CFG Address 0x1B10 0110 Access RO The SEAD3_CFG register describes BRTL and Board Configuration BRTL configuration is set in the rtl build pro cess SRAM_MAP_ZERO and FPGA_OPT are switches on the SEAD3 board Table 3 2 SEAD3 CFG register Fields Name Bits Description Access 0 31 5 USB_PRESENT Must be written as zero return zero on read 0 Not present no usb support 1 Present USB HS 2 0 Controller Interface RO DDR2_PRESENT SRAM_SIZE 0 Not present no dram support and sram will be mapped to address 0x0 1 Present DRAM interface is DDR2 0 sram size is 4MB FPGA_OPT switch in OFF position 1 sram size is 8MB FPGA_OPT switch in ON position GIC_PRESENT ADDRESS 0X0 DEVICE 0 Not present Interrupts are directly mapped 1 Present Interrupt Controller is GIC 0 dram mapped to address 0x0 SRAM MAP ZERO switch in OFF position sram mapped to address 0x0 SRAM MAP ZERO switch in ON position MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 17 Memory Map and Register Access Rul
33. o zero during power on reset A 0x0 value of 1 will set up CPU in EIC mode After power on this bit can be updated only writing to this register RW 24 MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 4 2 External Peripheral Bus Registers Table 4 7 PI SOFTENDIAN Register Continued DONE This field is set on write to bitO or bit2 cleared on write to PI SWRESET register RO 0 ENDIAN This field indicates board switch position sw bigend during power on reset After power on this bit can be updated only writing to this register RW 4 2 External Peripheral Bus Registers The following sections describe the programming of the devices attached to the peripheral bus 4 2 1 P SWITCH Name Address Access Reset Value PSWITCH Ox1F00 0200 RO N A This register allows software to monitor the state of the 8 bit P SWITCH 53 on the peripheral bus Table 4 8 PSWITCH Register 31 8 Reserved 7 0 VAL 8 P SWITCH bits physical switches are num bered 8 to 1 0 OFF Open 1 ON Closed MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 25 Peripheral Bus Controller 26 4 2 2 F SWITCH Name FSWITCH Address 0x1F00 0208 Access RO Reset Value N A This register allows software to monitor the state of the 8 bit F SWITCH S4 on t
34. operty of their respective owners Template nB1 03 Built with tags 2B MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Table of Contents Chapter VIMO USU u u e rr gt e 9 JUI MC 9 1 2 Block RI Le Le E 9 Chapter 2 X B Controller E 11 2 1 First level Address Mapping U 11 2 2 DDR2 SDRAM at Start of Me mO y c ya Dua geed 12 2 3 X Bus Controller intemal rei e EE 12 Chapter 3 Memory Map and Register Access Rules u 15 3 1 Uncached Access Or EE 16 3 2 Accesses to lllegal eserved Add eSSes aa bri eot dicor sumawa qaway dt ele de deren ay 16 2 9 Begistel MACIOS EE 16 314176119101116 EE 17 001010 17 Bg 6 SEADS CFO TEE 17 Chapter 4 Peripheral Bus Controller u u uu 19 4 1 Peripheral Bus Controller Internal Registers iia 20 4 1 1 Timing Parameters for Other External Peripherals A 21 4 1 2 SRAM Timing BEE 22 4 1 3 NMI Interrupt Latch Status Register a 22 4 1 4 NMI Interrupt Acknowledge Register A 23 4 1 5 SW Board Reset HeUISIOI cu aceite rubet dede qua iuc domu ruta arte cud deret tuia Magd ede rptu acad 23 4 1 6 PIC32 USB Status EE 24 2 17 SW Eeler 24 4 2 External Peripheral Bus oo
35. r at address OX1FCO0 0010 Note To ensure future compatibility address 1FC0 0010 is special in the sense that it does NOT decode to an address in the SW EPROM but rather to register address REVISION The YAMON ROM monitor uses the REVI SION register to identify the hardware platform and configure its drivers accordingly 3 1 Uncached Access of Registers To avoid cache coherency problems all registers internal to Basic RTL modules and in the peripheral bus devices must be accessed in uncached mode Such problems can arise for example when a dynamically changing status reg ister is polled If the program runs in kernel mode these registers can be accessed via ksegl mapping since ksegl is non cacheable In the rest of this document only 32 bit physical register addresses are provided a 32 bit physical address can be converted to a 32 bit kseg1 address by OR ing it with 0xA000 0000 For example if the peripheral bus controller reg ister PI TIMSRAM has physical address Ox1F00 0010 the virtual kseg1 address which kernel mode programs should use is 0x 1F00 0010 OxA000 0000 OxBF00 0010 3 2 Accesses to lllegal Reserved Addresses If the CPU attempts to access any of the above reserved areas the X bus controller will map those accesses to X bus target 2 as type Data This targets normal function is Register only so it is easy for this target to detect these illegal accesses and thus make a simpler X bus controll
36. rupt GIC Int 1 Ethernet Controller Interrupt GIC Int 0 38 MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Appendix References 1 MIPS SEADTM 3 Basic RTL Reference Manual MIPS Document MD00692 2 MIPSG SEAD 3 Board User s Manual MD00682 MIPS Technologies Inc 3 SEADTM 3 Board Getting Started MIPS Document MD00687 4 MIPS Global Interrupt Controller User s Manual MIPS Document MD00695 5 USB 2 0 High Speed Controller CI13720 Synopsys 6 Memory Interface Generator MIG User Guide UG086 Xilinx Corporation MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 Copyright 2009 2010 MIPS Technologies Inc All rights reserved References 40 MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Appendix B Revision History Change bars vertical lines in the margins of this document indicate significant changes in the document since its last release Change bars are removed for changes that are more than one revision old This document may refer to Architecture specifications for example instruction set descriptions and EJTAG register definitions and change bars in these sections indicate changes since the previous version of the relevant Architecture document Revision Date Comments 01 00 March 10 2010 Initial release MIPS SEAD 3 Basic RTL U
37. ser s Manual Revision 01 00 41 Copyright 2009 2010 MIPS Technologies Inc All rights reserved
38. st N A sw cpld w Switch position West N A sw cpld s Switch position South N A Switch position Center N A MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 27 Copyright 2009 2010 MIPS Technologies Inc All rights reserved Peripheral Bus Controller 4 2 6 NEWSC REG Name NEWSC REG Address 0x1F00 0228 Access RO Reset Value N A The NEWSC REG register allows software to read the state of NEWSC switch after debounce This is an 8 bit wide register Table 4 13 NEWSC REG Register Bits Field name Function Initial Value 7 5 Reserved N A sw cpld e Switch position East after debounce 0 sw cpld c Switch position Center after debounce N A 4 2 7 NEWSC CTRL Name NEWSC CTRL Address Ox1F00 0230 Access RW Reset Value N A The NEWSC CTRL register allows software to switch debounce time This is an 8 bit wide register Table 4 14 NEWSC CTRL Register Reserved DEBOUNCE This field indicates debounce count used in reading NEWSC switch values 28 MIPS SEAD 3 Basic RTL User s Manual Revision 01 00 Copyright 2009 2010 MIPS Technologies Inc All rights reserved 4 2 External Peripheral Bus Registers 4 2 8 Revision Info Name REVISION Address Ox1FCO0 0010 Access RO Reset Value N A Table 4 15 REVISION Register Bits Field name Function Initial Value 31 26 RTLID 6 bit binary number gives RTL ID Ox1 for Basic RTL RTLMAJ These two 7 bit binary
39. t time Check your oscillator frequency and the SRAM data sheet before changing values in the PI TIMSRAM register Table 4 2 PI TIMSRAM Register Bits Field name Function Initial Value Address and write data hold time Legal values CS2 1 to 63 inclusive Write enable deassertion time Legal values WE1 1 to ADH 1 inclusive Write enable assertion time Legal values CS1 to WE2 1 inclusive Read strobe deassertion time Legal values RD1 1 to ADH 1 inclusive Read strobe assertion time Legal values CS1 to RD2 1 inclusive Chip select deassertion time Legal values max RD2 WE2 to ADH 1 inclu sive Chip select assertion time Legal values 0 to min RD1 WE1 inclusive 4 1 3 NMI Interrupt Latch Status Register Name PI NMISTATUS Address Ox1F00 0040 Access RO Reset Value 0x00000000 The Peripheral bus controller contains logic to generate an NMI pulse if either of two cases occurs the user presses the ON OFF push button awrite access to an illegal address is detected In either case the FLAG field of the PI NMISTATUS register is set when an NMI exception is generated If the NMI exception is generated due to an illegal write access the WERR bit will also be set If an NMI pulse is signalled to the CPU the CPU will restart execution from the reset handler The CPU is then able to detect that it has restarted due to an NMI interrupt as opposed to a cold reset by noting that the
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