AD61 - inverter & Plc
Contents
1. oro mo Ke fosco kr D500 data is written to address 6 of buffer memory For others refer to DFRO 6 6 6 PROGRAMMING 1 External preset detection reset CH1 external preset request CH1 external preset request detection reset condition detection reset condition SET vie Y CH2 external preset request detection reset condition i T CH2 external preset request detection reset condition 1 CH1 external preset request detection reset 2 CH2 external preset request detection reset To perform preset from outside it is necessary to perform reset of external preset each time Since the preset operation occurs on the pulse leading edge further preset by external input or preset by sequence program cannot be performed until the external preset flip flop has been reset The external preset flip flop can be reset while the external preset input is on It is not necessary to execute this signal if the external preset terminal is not used 2 Setting of mode register 1 phase specification 1 phase specifying condition Mov k8 D0 Poet Set data to be written to data register ToP mo K3 00 Address of mode register Address a Head I O number of AD61 unit AD61 unit write instruction Data to be written Address of mode register in buffer memory ata to when 1 phase is specified ify 1 phase write 8 1 phase mode TO SPOCUY TP Word length Since mode register is 8 bits specify 1 word for the TO ins2. Cat No UMHS INTRODUCTION Thank you for your purchase of Mitsubishi General Purpose Programmable Controller MELSEC A Prior to use please read this User s Manual carefully to fully understand the functions and perfor mances of the A series programmable controller and also to use it correctly Please forward this User s Manual to the end user CONTENTS 1 GENERAL DESCRIPTION cupra rad de as E AAA 1 1 2 SYSTEM CONFIGURATION coooocococcocccncccccoc rr 2 1 2 2 2 1 General Description of System asi cta 2 See wo ones oe Oe Oe OP ee ee AS 2 1 22 Ap licable System 04a taisc 2 eee De be oe on OR ee 2 2 2 3 Cautions for System Configuration sasssa assas ee eee eens 2 2 3 SPECIFICATIONS ans Di DA OES OE ER RAR EOL 3 1 3 13 3 1 General Specifications lt 2 ised aie ad an he RNG Coe Ewe Rhee bade buses 3 1 3 2 Performance Specifications 000 cee cece eee cee eee tues monas 3 2 32 1 P riOrmance stud ES A A ES AA 3 2 S22 RUNCUONS acs cis ia A o A eS hws ea ee 3 3 3 3 1 0 Signals To and From Programmable Controller CPU o ooo ooo 3 9 3 4 Buffer MEMO atan daa a ee eae 3 11 3 5 Interface with External Equipment o o 3 13 d HANDLING cra oo ein AAA we cad 4 1 4 3 4 1 RanalindlnstructiiOns y cd a ica a aa RR eke Ree eee 4 1 4 2 Nomenclature and Explanation o ooooooooro noo anrca es 4 1 43 Setting f Ring COUNEIS ainia idad oh
3. e ips time t power on counter value is 0 A 104 105 106 107 108 109 os f LE LP Work Compa Counter value 97 98 99 100 101 102 103 Pulse input A Liu L El Content of counter is transferred to data 1 I By executing preset preset value is written to counter Content of latched data register is H written to preset value Preset command register through present value read a Present value read i 1 1 1 1 t Preset value write Latched Data register CPU We Memory AD61 Fig 3 4 Preset Operation e The preset value is written to the appropriate buffer memory address address 1 for CH1 address 33 for CH2 as a 24 bit binary number To load the preset value into the counter current value turn on the preset command Y 11 for CH1 Y18 for CH2 from the programmable controller CPU e The preset command may either be loaded from the program or input by applying a voltage to the PRST terminal on the external terminal block external preset When the external preset signal is given a flip flop F F is set If the external preset input turns on again while the F F is set the presetting function is stopped Reset the F F from the program Y16 for CH1 Y1D for CH2 Even if the external preset input remains on the F F can be reset The F F is set on the leading edge of the external preset pulse 3 7 3 SPECIFICATIONS 8 Disable function By turning
4. v Shield ME Phase B Y Twisted pair wire 4 4 sea SSA yA ony QQ gt lt A Shield Y OUT ea E External 24VDC Y Y power supply OV Y Y In order to minimize any interference from noise on the encoder power supply the encoder signal and supply lines should be wired as follows CORRECT External 5 2 5 WIRING AND INSTALLATION 2 Pulse generator is voltage output type 5V DC AD61 4 7KQ 1 4W 24V Pulse generator 2 2KQ 1 4W 12V 2 2KQ2 1 4W 12V Phase B a ME power ove e OV supply 4 7KQ 1 4W 12 24V oe E 2 12v ES Preset aa A Y Disable S 6802 1 4W 5V A 5 ES L DC Dhs Se ji qe CY Uy 5 3 5 WIRING AND INSTALLATION 4 Source load voltage output type Controller 4 7KQ aaa PANG AD61 gt gt 68007 1 4W 5V Pras Twisted shield wire ee 7 com de gt as oe dye 4 7K9 Boami ane 1 soy DC Taj 1 4W 5V E Twisted shield wire NESST a DL COM E A A 4 AA 5 Connection with EQU terminal To use the EQU terminal the internal photocoupler should be activated For this purpose 10 2 to 30V external power is necessary Connection methods are as follows AD61 Photocoupler 10 2 to 30V 5 4 6 PROGRAMMING 6 PROGRAMMING 6 1 General Description of Programming Program flow for the control of AD61 is as shown below Common to AQJ2 A1 A2
5. D61 Open collector A Output Fig 3 2 1 Phase and 2 Phase Inputs 3 4 3 SPECIFICATIONS 5 Count timing The timing for 1 phase input of the comparison result between a present value and a set value is as indicated below Indicated by the assignment numbers of CH1 and 2 For up count set value 100 96 97 98 99 100 101 102 103104 105 Count input Counter value lt set value X02 X06 Counter value set value X01 X05 Counter value gt set value X00 X04 Time Note During up count count 16777215 is followed by O For down count set value 100 104 103102101100 9998 97 96 95 Count input Counter value lt set value X02 X06 Counter value set value X01 X05 Lisa Counter value gt set value X00 X04 MA m m e y A a ew am aw Ee Note During up count count O is followed by 16777215 Fig 3 3 Count Timing 3 5 3 SPECIFICATIONS 6 Count mode On AD61 the count ratios of input pulses are as described below 1 Twice for 1 phase input 2 counts are made for 1 pulse input 2 Four times for 2 phase input 4 counts are made for 1 pulse input 1 Each input pulse registers two counts for 1 phase input and four counts for 2 phase input If the counting range is large select the pulse generator so that a value twice for 1 phase or four times for 2 phases greater than the number of generated pulses is within the counting range 0 to 16
6. preset counter plus ring counter Up down preset counter plus ring counter function 20usec Minimum count pulse width Set input rise and fall times to Busec or less Duty ratio 50 y 1Ousec MTRS 50usec SOpusec 71sec 71usec 1 2 phase inputs 1 phase input 2 phase input Magnitude 24 bits binary comparison ae between CPU Set value lt ount value and AD61 Comparison result Set value count value Set value gt count value Prosa 12 24V DC 3 6mA 5V DC 5mA Externa input l 12 24V DC 3 6mA Count disable 5V DC 5mA Coincidence Transistor Open collector output Performance specifications of 1 channel Table 3 2 Performance List Counting speed is influenced by pulse rise time and fall time Countable speeds are as follows If a pulse greater than 50Opusec is counted by the AD61 miscounting may occur In this case use the AD61S1 1 AD61 for both 1 and 2 phase inputs t 5us 50KPPS AK Sf t 50us 5KPPS 2 AD61S1 t t Time 1 Phase input 2 Phase Input 1OKPPS 7KPPS soorps 250PPS 3 2 3 SPECIFICATIONS A eR re A A A A A E eRe ea I Nee A 3 2 2 Functions 1 General description The AD61 unit counts high speed pulse input which cannot be used directly of programmable controller CPU Its size is the same as that of programmable controller O unit AD61 incorporates a BIN binary 24 bit preset counter function which is capable of up down count a ring count
7. Ares When using the A1E A2E or A3ECPU use the partial refresh instructions SEG kav115 ka81 SEG kav115 KaBt Timing chart Time ON Y115 The current value is continuously changing so to ensure that a correct value is read the oe XX X XA XX XX K XK above interlock must be used s Present value Immediately after Y115 turns on the count value is treated as present Indicates change value and latched Present value register BIN 24 bits Lower At read time OO is set into upper 8 bits Lower 6 14 6 PROGRAMMING 11 Set value read Set value read asno iio xe 58 KT Set value address Address CH K6 AD61 unit head I O number CH2 K38 Buffer memory address K38 for CH2 Word or AD61 unit read instruction Read operation Head number of data registers which will i store read data Word length K1 32 bits Buffer memory of AD61 set value 6 15 6 PROGRAMMING 6 3 Programming for AD61 in Remote I O Station 1 When using the AD61 in a remote I O station all data and O signals must be passed via the link memory This memory is only accessed after the END command in the main program has been executed so all handshake signals between the AD61 and the CPU will take several scans to be completed For example consider the resetting of the coincidence signals X01 using the coincidence signal reset comm
8. A3CPU 1 Flow chart and programming procedure when ring counter function is not used 1 Flow chart 1 External preset detection signal reset 2 Mode register setting Specification of 1 phase or 2 phases 8 Specification of up down direction when phase has been specified 4 Setting of preset value data 6 Setting of set value data Execution of preset Counter value coincidence signal reset Set value setting Count start Present value read YES Processing after comparison Program in this area is related to sequence control and will vary depending on the application l Count input enable ON 9 Coincidence signal output enable ON Present value read request ON 40 Present value read Present value read OFF External preset detection signal reset Completed YES Completed 6 1 Nee e a A Oe TS 5 6 PROGRAMMING le Hor a 2 Programming procedure The following example shows the programming procedure for the A1 A2 and A3CPUs according to the flow chart in 1 The AD61 I O numbers are assigned to 100 to 11F M9038 a MOV K8 DO 2er phase constant to data Ts oa Writes mode to buffer memory 1 X002 3 Up down count direction setting DMOV Writes preset value 0 to data 4 registers D5 D6 DTO H10 K1 D5 KB Writes preset value to buffer memory Reads set value from digital switch to DBIN K4x040 DI data registers D1
9. ede e rs o MT aa area e 6 PROGRAMMING ET TE A A A A A A A Ree a A SS 3 Differences of programming depending on system configurations Instruction or Programming Method Necessary for Use of AD6 1 Accessing method to buffer AD61 F F reset pulse generating memory method RERP instruction Since Y output to actual System Configuration Using AD61 A CPU data link sys tem Remote I O sta tion equivalent to FROM instruc tion RTOP instruction remote 1 O station is executed after END of sequence pro gram pulse is not output by the above method To output pulse to remote O station create the following program SET Y16 gt END link refresh gt RST Y16 gt END link refresh equivalent to TO instruction Only one instruction may be executed for 1 special unit within 1 scan instructions used Mu Use of PLS Y16 turns on Y16 for 1 scan This is undesirable because AD61 may not oper ate for that period A CPU in dependent FROM and TO SET and RST are system are used Example A CPU data link sys tem Master station and local station When using the I O refresh type CPU A1E A2E A3ECPU always use the partial refresh instructions and convert them into pulses using the SET and RST instructions 6 PROGRAMMING 6 2 Programming for A1 E A2 E and A3 E CPU This section describes the programming procedure for A1 E A2 E and A3 E CPU Explanation will be given in order o
10. is not latched lt Coincidence signal reset command The external preset detection reset command must be executed at high speed so that the scan time of the program has minunal effect on the AD61 operation For this reason do not use the PLS Y16 instruction Use a SET Y16 instruction followed by RST Y16 this is fully explained later in this manual 3 10 3 SPECIFICATIONS 3 4 Buffer Memory 1 General description By using FROM and TO instructions the AD61 is capable of making data communication with the programmable controller CPU through the buffer memory The address consists of 16 bits Phase A Phase B Count disable Preset Coincidence output Data such as set value preset value and present value O et ll Only FROM and TO instructions are accessible 2 Memory map The memory map inside the buffer memory is shown below When the power is turned on or the CPU is reset the contents of the buffer memory are initialized to O Preset value present value and set value and handled as 24 bit binary The address is expressed in decimal CH1 CH2 address address 1 l 33 Preset value write lower and middle Write only 2 34 Preset value write upper 3 l 35 Mode register Read write 4 36 Present value read lower and middle Read only 5 37 Present value write upper 6 38 Set value read write lower and middle Read write 7 39 Set value read wr
11. on the count enable signal i e a programmable controller O signal AD61 starts counting Y14 for CH1 Y1B for CH2 When a voltage is applied to the DIS disable terminal on the external input terminal block the AD61 stops counting By utilizing this counting may be started and stopped by the external input irrespective of scan time 9 ee Ring counter function By moving the ring counter setting pin on the AD61 circuit board to the ON position automatic preset is performed if the counter value becomes equal to the set value Use this function for cyclic control such as sizing feed The timing for the ring counter is shown below Setvalue Q Presetvalue 8 1 phase down count Counter value 4 7 6 5 43 2 108 7 6 5 43 2 1 08 Phase A pulse 0 8 y h input Coincidence signal EQU CH1 X01 CH2 X05 Coincidence signal reset CH1 Y10 CH2 Y17 Preset CH1 Y11 CH2 Y 18 When ring counter function is turned on preset is performed immediately within 2us after EQU signal turns on For continuous pulse inputs The ring counter performs preset operation internally when the coincidence signal turns on When preset is executed counter value is set to 8 If present value is read at the time of operation marked 1 8 or O is read Fig 3 5 Ring Counter Operation 10 External output AD61 is capable of giving a counter value coincidence signal open collector output which turns on if the counter
12. phase A LED flicker YES Check and correct ex ternal wiring Has count enable been turned on by sequence program Is enable LED on Is disable input provided to externa input terminal YES NO YES is 2 phase specified Does phase 8 LED flicker YES NO Correct 1 0 assignment number is the I O assignment number for AD61 correct YES Has stage setting NO switch of extension base been set correctly YES is AD61 loaded on an extension base YES Has AD61 been assigned to extension base without power supply unit ts main base power NO capacity proper YES Move AD61 to a station YES with its own CPU If this is impossible check program Has AD61 assigned to remote I O station NO Remove AD61 and check whether any matter has entered NO Remove foreign matter YES Hardware fault by directly applying voltage Are phase A and phase B LEDs lit to count input terminal Correct sequence pro gram so that count en able is turned on Check external connec tion Set stage number setting switch according to as signment Assign AD61 to exten sion base with power supply unit Hardware fault E 8 TROUBLESHOOTING Counter value is incorrect Counter value is incorrect NO Do coun
13. power input Current consumption 2 to 5mA Input Operating voltage 10 2 to 30V Rated voltage 0 5A Maximum rush current 4A 10msec 3 13 4 HANDLING 4 HANDLING 4 1 Handling Instructions This chapter describes the handling instructions nomenclature maintenance and inspection of the AD61 1 Protect the AD61 and its terminal block from impact 2 Do not touch or remove the printed circuit board from the case 3 When wiring ensure that no wire offcuts enter the unit and remove any that do enter 4 Tighten terminal screws as specified below Tightening Torque Range kg cm I O terminal block terminal screw M3 screw I O terminal block mounting screw M4 screw 5 To load the unit onto the base press the unit against the base so that the hook is securely locked To unload the unit push the catch on the top of the unit and after the hook is disengaged from the base pull the unit toward you 4 2 Nomenclature and Explanation aa catch LED indicators Printed circuit board I O terminal block Refer to Section 3 5 Ring counter setting pin E a 2 Y ES e A ee e SOM e zy Sv rn a com A6DU V O AS 2 i po 2 3 A Pu nm A lt 4 HANDLING 1 LED indicators LED on conditions are explained below LED operations of CH1 are the same as those of CH2 AD61 Phase A pulse input indicator Lit when voltage is appli
14. up noise The diagram below indicates the type of precautions required Metal piping Never run solenoid or inductive wiring through the same conduit If sufficient distance cannot be provided between the high current line and input wiring use shielded wire for the high current line J terminal block T block Separate more than l o 15cm from equip Distance between encoder and joint ment such as inver box should be as short as possible ters etc Also take If the distance from the AD61 to care of wiring inside ieidelbox the encoder is too long an excessive the panel voltage drop occurs Therefore measure the voltage during opera tion and check that the voltages are within the rated voltage of the encoder If the voltage drop is large increase the size of wiring or use an encoder of 24V DC with less current consumption Ground twisted shield wire on the encoder side joint box This is a connec tion example for 24V sink load Connect the encoder shield wire to the twisted pair shield wire inside the joint box If the shield wire of the encoder is not grounded in the encoder ground it inside the joint box as indicated by dotted line To phase A To phase B To AD61 5 WIRING AND INSTALLATION 5 2 2 Unit wiring examples 1 Pulse generator is open collector output 24V DC AD61 4 7KQ 1 4W 24V P eae e 2 eee Twisted pair wire 2 2 2KQ2 1 4W 12V Phase A
15. 1E A2E or A3ECPU use the partial refresh instructions Buffer memory of AD61 Preset value e 24 bits Transfer is made and upper 8 bits are ignored 3 When preset command signal turns on preset value is set as the initial value of counter at the edge of rise O If external preset request detection signal remains on preset operation is not performed even when the above instructions are executed Before turning on preset it is necessary to execute external preset detection signal reset O After preset value write has been executed preset can be made at any position 6 9 6 PROGRAMMING A block diagram related to the preset operation of the AD61 is shown below F F EQU Ring counter function xternal preset E P setting pin terminal Photocoupler 4 Preset operation at the edge of rise Preset command CH1 Y11 CH2 Y18 Coincidence signal reset command CH1 Y10 CH2 Y17 External preset detection reset command CH1 Y16 CH2 Y1D Three signals are available for preset operation 1 Preset by program 2 Input from external preset terminal 3 Counter coincidence when ring counter is on Preset operation uses logical add OR of these three signals Upon rise of this signal from off to on preset operation is performed If one of the signals remains on preset operation is not performed because if another preset signal is turned from off to on the output of logical add
16. 777 215 For 1 phase input specify any set value as twice the actual number of input pulses or halve the present value by using D instruction For 2 phase input specify any set value as four times the actual number of input pulses or divide the present value by four by using D instruc tion Counting methods for 1 phase input and 2 phase input are shown below When 1 phase is used down counting is made if down count specification is on When 2 phases are used down count is made if phase B input pulse leads phase A input pulse Count timing when 1 phase is used ED ESTELA IAAF MM Count timing when 2 phases are used Phase A pulse input Down count specification CH1 Y13 CH2 Y1A Counter value 16777215 16777214 Phase A pulse input oe los a ee Phase B pulse input m e ee r m ee oe oe oe oe A m cs CI ee ee ee il i ee m ee ee UNA a osm amm ee aia a m ar eee a er e m a m ee a ee un Counter value 4 8 us TEL 2 UIA indicates down counting 3 6 3 SPECIFICATIONS 7 Preset function When the power to the AD61 is turned off or the CPU reset the AD61 memory contents are lost i e present values set values etc If these values need to be retained for subsequent use they must be stored in a suitable data register in the Program mable controller CPU Example Next time
17. A Coincidence output mi External preset detection reset Coincidence output enable enable signal External preset request detection Fig 3 1 Block Deagram 3 3 3 SPECIFICATIONS 3 General description The AD61 counts the number of input pulses In the following figure for example each time a pulse is input the AD61 counts pulses in order of 1 to 2 to 3 to 4 to n The allowable counting range is O to 16 777 215 The AD61 unit always executes the comparison function gt lt with a set value a target value optionally set by user Input pulse 1 phase i Count operation of AD61 1 present value 4 Pulse input Pulse inputs may be 1 phase or 2 phase For 1 phase pulse input up count down count specification is also possible from the main program is made each time a pulse is input For 2 phase pulse input the up down direction of the counter is automatical ly judged depending on the relation between phase A and phase B In the following figure the voltages at the AD61 count input terminal are shown for 1 phase and 2 phase inputs In this manual explanation will be given in reference to source load Output Type of Pulse Generator 1 Phase Input 2 Phase Input Source load voltage output type Electrical angle Example NM 24 V 4 To 24V of Phase B AD61 Count 4 To phase A B EA E eee Sink load current output type Electrical angle Example 24v To 24V of
18. D2 The set 5 value should be twice the required pulse input Writes set value to buffer memory 1 External preset detection reset X000 MO x001 U E E Dd H10 1 6 Preset command SET Y110 MO 8 Count enable Y114 1 7 Coincidence signal reset MO 12 9 Coincidence signal output enable necessary for output to EQU ter Y112 minal Y114 Y112 LY TE 1 reser value read request DFRO 10 Reads present value from buffer memory to data registers D3 D4 Sequence control data to be programmed by user honor roo md POINT 1 When using the A1E A2E or A3ECPU use the partial refresh instructions AMET O MAI A 6 PROGRAMMING 2 Flow chart and function is used 1 Flow chart Initial setting and set value setting 11 Counter value coincidence signal reset Counter value coincidence signal reset Count start Present value read Processing after comparison programming procedure when ring counter 1 External preset detection signal reset 2 Mode register setting Specification of 1 phase or 2 phases 3 Specification of up down direction when 1 phase has been specified 4 Write of preset value data 5 Write of set value data 6 Counter value coincidence signal reset 7 Execution of preset 8 Count enable ON 9 Coincidence signal output enable ON Present value read Present value read request ON 10 Present value read re
19. RTOP and RFRP Refer to the Data Link Unit User s Manual Example AD61 head I O numbers assigned to X Y100 to X Y11F t Specify 3 digits Ali data is communicated via the link registers The link registers W should be set in the programmable controller CPU parameters In the following example the AD61 is assigned to X Y100 to X Y11F External preset detection reset Preset detection reset X103 O Mode register setting Mode register setting PLs ma aa M4 XI11F X11E Y 10F Y10E i 2 phase Write to aror HT00 ence I O station X11F i 6 17 A A A EA E PO A is RS Tor fy 7 TEST OPERATION 7 TEST OPERATION 7 1 Pre test Checks IMPORTANT Before switching on the encoder power supply check that the correct terminals have been used Application of 24V to 5V terminals will damage the unit Before turning on the power check the following Ring counter setting pin Check that the AD61 is properly loaded onto the base unit Check terminal wiring Check the voltage of the external power supply IS After the above checks turn on the power and operate the pulse generator Check the relevant phase indicator LED 7 1 8 TROUBLESHOOTING 8 TROUBLESHOOTING AD61 does not count AD61 does not count Is external NO power supply voltage correct Check or change exter nal power supply unit YES NO ls external wiring correct Does
20. Shear High speed command Low speed Shear x03 Stop completion Operation When the start pushbutton is pressed the amount set by the feedrate digital switch is advanced When positioning is completed a shear command is sent to the shear controller When shearing is complete the positioning operation is repeated Deceleration point is 100 counts ahead of the set value If the set value is 100 counts or less the program does not operate Data register assignment DO D1 Set value D2 Number value D3 D4 Preset value D5 D6 Present value APP 3 A a A II A Por e ara er e a APPENDICES Operation timing Number setting 2 Start pushbutton High speed Low speed E y 4 Y Stop gt TO Shear command Shear completion APP 4 APPENDICES 103 105 111 116 Application circuit using ring counter function for A1 A2 A3CPU X002 YO74 SS ss SLES MO MO 1 SET a RST K MOV 18 D9 H K TO 3 D9 DMOV D3 OSA K4 X020 BIN K4 D2 X030 D3 DBIN DTO DO K SET Y070 DTO OT OI DAA RST YO7O SET YO71 YO71 RST CO D7 YO45 4 K Y045 D lt 100 DO M1 100 MO Y045 CO a IEEE YO74 Y074 X061 Y041 Y045 4 Hh SET Y040 Y074 1 SET Y075 H K K RST Y075 APP 5 Start pulse External preset detec tion reset Constant of 2 phases is written to data register Mode is written to buff er memory Preset value O is written
21. YO75 H K K DFRO 6 4 D3 1 RST YO75 YO74 Y044 t C D lt D7 D3 Y _A SET Y041 Y074 Y041 Y044 H O vgn X061 RST Y041 Y042 APP 2 A eee Start pulse External preset detec tion reset Constant of 2 phases is written to data register Mode is written to buffer memory Preset value O is written to data registers D5 D6 Preset value is written to buffer memory Set value is read from digital switch to data registers D1 D2 For set value specify 4 times of required pulse input Set value range check Set value range check OK Set value is written to buffer memory Coincidence signal reset Preset command Deceleration point cal culation D7 D8 Count enable Coincidence signal out put enable Required for output to EQU terminal Present value read re quest Present value is read from buffer memory to data register D3 D4 When deceleration point is exceeded low speed command turns on High speed command turns on Low reset Completion signal speed command APPENDICES Work Coit Digital switch Feedrate setting La dl d dy X20 to X2F Number F om ddd A X30 to x3 X02 Start Y Variable Shear pushbutton oea controller 2 Example using ring counter function Shearing control application using the ring counter functio Feed rolls AY 6 Shear e Motor Encoder de 2 phases 0 1mm pulse
22. a sae pS 8 ONG RES eee es 4 3 Ab IVIAINEONENCE mid le dares wy ate ERA ree See eo ES are a Ene SAS 4 3 5 WIRING AND INSTALLATION 0 0 0 cc eee ee eee eee ees 5 1 5 4 5 1 Unit Arrangement Precautions 025554 bid ALAS A bees eS ee eS 5 1 WL ce chet a tesa A ee le eh bu ae ae Re AS Oa ee 5 1 B24 Wiring INSTTUCTIONS ica pd a a Wie awe eo EE EEG reve ee wae 5 1 5 2 2 Unit Wiring examples iii VAR AG AR ER WO eS 5 2 6 PROGRAMMING eee eee eee eee ee ee ee 6 1 6 17 6 1 General Description of Programming ccc ce ee ee eee eee teens 6 1 6 2 Programming for A1 E A2 E and AS E CPU 1 ee eee 6 6 6 3 Programming for AD61 in Remote I O Station 0 0c cee ee ete ee 6 16 7 TESI OPERATION ia a AS hase ARA 7 1 7 1 Pretest CHECKS 5 4 24a ee eS ee eee ae Se Ee Oe ES RR Re he alee ee 7 1 8 TROUBLESHOOTING coria Settee rie bebe ct a 8 1 8 2 APPENDICES i in ia Aad ee tae ease NA APP 1 APP 10 APPENDIX 1 Application Circuit ExamplesS o ooooooooooooooomoonoooos APP 1 APPENDIA 2 External VieW cir AAA a APP 10 1 GENERAL DESCRIPTION Ng a Se 1 GENERAL DESCRIPTION This manual describes the AD61 and AD61S1 high speed counter modules giving handling instructions and basic programming infor mation The AD61S1 allows counting pulses of long rise and fall times more than 50usec Unless otherwise specified the AD61 and AD61S1 are referred to as AD61 The AD61 high speed count
23. and Y10 Assume that the AD61 is loaded into the slot corresponding to head number X Y 100 and the coincidence occurs when the counter current value reaches 10000 SET Y110 RST Y110 Program scan time Y1100N Y110 OFF Link scan Counter value 10000 0 X101 A The above example operates correctly because the time taken for the counter to count from O to its set value 10000 is greater than the time taken for the handshake signals to operate If this count time was reduced i e the pulse frequency increased so that it became less than the time taken to complete the full handshake operation the AD61 would mis operate and continue counting above 10000 It is very important to be aware of this potential problem when using the high speed counter in a remote O station Careful consideration of the main program scan time the link scan time and the pulse frequency will avoid mis operation however it is recommended that the AD61 is used only in stations with their own CPU If the AD61 is used in a remote O station the handshake sequences described in this section should be used with caution 6 16 6 PROGRAMMING 2 For the communication program to and from the remote I O station use RTOP to write to the AD61 and RFRP to read from the AD61 The RTOP and RFRP instructions differ from TO and FROM in the following point To set the AD61 head 1 0 numbers specify upper 2 digits for TO and FROM Specify all digits for
24. ation of decelera tion point D11 D12 Set value stop point is written to buffer mem ory of CH1 Set value deceleration point is written to buffer memory of CH2 Coincidence signals of CH1 and CH2 are reset Preset commands of CH1 and CH2 APPENDICES 131 134 137 140 YO74 YO72 1 m 143 SET Y075 H K K DFRO 6 4 0 D3 o RST Y075 Y07B Y079 ii 1564 SET Y07C H K K DFRO 5 36 D13 RST YO7C Y074 X065 Y044 AA YAA lt lt Y 040 Y042 169 X061 1 3 Count enable of CH1 and CH2 Coincidence signal out put enable of CH1 and CH2 CH1 present value read request Present value is read from buffer memory of CH1 to data registers D3 04 CH2 present value read request Present value is read from buffer memory of CH2 to data registers D13 014 High speed command Completion signal For monitor When using the A1E A2E or A3ECPU use the partial refresh instructions at places marked in the program APP 9 APPENDICES APPENDIX 2 External View M3 0 12 x 0 5 0 02 x 6 0 24 4 2 0 17 Terminal screw Printed circuit board 6 0 24 e 10 0 39 8 106 4 17 25 0 9 4 2 0 17 131 5 16 37 5 1 48 Unit mm inch APP 10 IMPORTANT The components on the printed circuit boards will be damaged by static electricity so avoid handling them directly If it is necessary to handle them take the following precautions 1 Ground human body and wo
25. ed to phase A pulse input terminal Phase B pulse input indicator Lit when voltage is applied to phase B pulse input terminal CH1 7117 CH2 PA ru QA OB tnt OB DECO ni DEC ENABLE 7 7 ENABLE PRESET _11_ PRESET EQU nD EQU Down count indicator Count input acceptable Lit when disable input is off and internal output count enable is on External preset input detection Lit and latched when voltage is applied to preset input terminal External coincidence output operation Lit when counter value coincidence signal is on and external output enable is on lf external preset detectiori reset signal Y16 for CH1 Y1D for CH2 is turned on when this LED is on it will turn off 2 I O terminal block 1 O terminal block is explained below For the arrangement of terminal block refer to Section 3 5 Terminal block mounting screw By loosing this screw the terminal block can be removed from unit Terminal block cover gt ae rs ra es ae sor un y EKEk PL 4 2 4 HANDLING eed 4 3 Setting of Ring Counters To select the ring counter function change the setting of the pin on the circuit board As shown below ring counter setting pins are located AD61 at the bottom left of the circuit board Set the ring counters individually for CH1 and CH2 The pins are factory set at the OFF position If the pin is removed setting is placed into OFF state The figure shows CH1 ring cou
26. er function an internal preset function an external disable function a com parison function with BIN 24 bit set value and a coincidence signal external output function applicable to two channels 2 Block diagram General operation CH1 counter counts the pulse train entering its phase A input up or down as appropriate In order to read a count value from the CPU unit it is necessary to read the value via the buffer memory I O signals to and from the programmable controller CPU are used to control the operation of the counter The buffer memory is used to store set data etc which controls the counter 1 O signal to from I programmable controller CPU Pulse train MOAR Phase A input Coincidence signal reset Counter value preset Down count specification Phase B input Count start Present value read request Gri counter Disable BIN 24 bits Comparison result gt Preset Comparison result Comparison resuit lt Read write Coincidence output Coincidence output enable enable signa External preset request detection X3 Read write Interface with PC External interface photocoupler insulation Coincidence signal reset CH2 A Phase A input Down count specification Phase B input rian Ee resent ue rea request BIN 24 bits P Disable Comparison result gt PRESET E r Comparison result lt E de Preset
27. er module is used in conjunction with MELSEC A series programmable controllers The following manuals may also be required A CPU User s Manual A CPU Programming Manual A CPU Data Link User s Manual In this manual I O signals to and from the programmable controller CPU are explained on the assumption that AD61 is loaded in No 1 slot of the main base unless otherwise speci fied except circuit example in the Appendix 1 1 2 SYSTEM CONFIGURATION _ 2 SYSTEM CONFIGURATION 2 1 General Description of System A configuration example of an independent system is shown below For the use of the AD61 in a data link system refer to Section 2 2 Applicable Aaa peg O CPU unit AOJ2 AT E A2 E AS EJCPU Main base unit A32B A35B _ A38B Extension cable ACO6B AC12B AC30B Any number of AD61 be loaded Extension base unit A65B p A68B generator Select items which match a specifications Fig 2 1 Overall Configuration Diagram 2 1 2 SYSTEM CONFIGURATION 2 2 Applicable System 1 AD61 can be used with the following CPUs AOJ2CPU Applicable models A1 E CPU A2 E CPU A3 E CPU 2 The AD61 can be loaded into any slot of a base unit with the exceptions given below If the AD61 is loaded into an extension base unit without a power supply unit care must be taken to ensure that the power capacity is sufficient For the selection of power
28. f programming flow chart in Section 6 1 To use any special function unit utilize FROM and TO instructions These instructions will be described below For details refer to A1 A2 A3 Programming Manual Execution condition TFRom TO ot m2 D ra Word length K or H used 32 bits per word for DRFO DTO 16 bits per word for FROM TO Head device number which stores read data Optional number of T C D W or R usable Change of FROM TO instruction FROM for read TO for write r FROM Ea I 4 TO 47 P means that the instruction is For TO executed ae at the rise of Head device number which stores data to execution condition be written Optional number of T C D W or R usable D means that the word length is 2 words 32 bits Upper 2 digits of AD61 unit 1 0 assign For remote I O station use RFRP in ment number K or H used tead of FROM and RTOP instead of TO il En dl AD61 unit buffer memory address number K or H used Example This section uses the slot assignments shown on the left CPU unit E Q a rr ds gt a X000 X040 YO80 YOCO nee XO3F XO7F YOBF YOFF X10F Di Upper 2 digits of head O assignment X100 f VIF of AD61 K16 in decimal Address of set value in buffer memory Device number which stores read data Binary 24 bit value is entered into DO and Set value read D1 ALAS Setting K1 causes 32 bits to be read Set value write
29. g Conforms to JIS C 0912 10g x 3 times in 3 directions ae By noise simulator 1000Vpp noise voltage Noise durability Tus noise width and 25 to 60Hz noise frequency Dielectric 1500V AC for 1 minute acorss AC external terminais withstand voltage and ground Insulation 5M2Q or larger by 500V DC insulation resistance tester across batch resistance of AC externa terminals and ground Operating soy Free of corrosive gases Dust should be minimal Cooling method Self cooling Table 3 1 General Specifications Vibration resistance 10 times 1 octave minute REMARKS One octave marked indicates a change from the initial frequency to double or half frequency For example any of the changes from 10Hz to 20Hz from 20Hz to 40Hz from 40Hz to 20Hz and 20Hz to 10Hz are referred to as one octave 3 1 3 SPECIFICATIONS 3 2 Performance Specifications The AD61 is used to count pulses which are occuring at a frequency too high for the CPU counters to use The AD61 counts independ ently of the CPU 3 2 1 Performance list 1 0 points 32 points Number of channels Count input 5V DC signal Signal level Phase A Phase B SV a 2 to Dm A Counting speed t phase input 5OKPPS 1 phase input 10KPPS Maximum 2 phase input SOKPPS 2 phase input 7KPPS 2 bits binary O to 16 777 215 decimal Counter 1 phase input 2 phase input Up down preset counter plus ring counter function
30. gital switch X20 to X2F Start pushbutton 3 Operation A3 A6265 13 a T O a Variable speed controller High speed AY Low speed Output Stop Speed Time i i EQU2 EQU1 When the start pushbutton is pressed the set value is read from the digital switch output Y is provided and positions the job at high speed using the output signals EQU1 and EQU2 Deceleration point is 100 counts ahead of set value If the set value is 100 counts or less program does not operate Data register assignment DO D1 D2 D3 D4 D5 D6 D11 D12 D13 D14 Modes of CH1 and CH2 Set value of CH1 Present value of CH1 Preset values of CH1 and CH2 Set value of CH2 Present value of CH2 APP 7 X002 APPENDICES SET D5 K4 X020 RST D gt D1 M1 100 D D1 Y044 DTO 6 DTO A K SET ERST ESET TRST CSET TRST CSET TRST APP 8 MO Y076 Y076 YO7D YO7D D1 Y044 A 5 M D11 Y044 Start pulse External preset of CH1 and CH2 Constant of 2 phases is written to data register Mode is written to buff er memories of CH1 and CH2 Preset value is written to data registers D5 D6 Preset value is written to buffer memories of CH1 and CH2 D5 D6 Set value is read from digital switch to data registers DO D1 For set value specify 4 times of required pulse input Set value range check OK Calcut
31. ite upper Addresses in parentheses in the above table indicate those of the upper 8 bits of 24 bit data 3 11 3 SPECIFICATIONS 3 Setting of mode register Set the value of the mode register as indicated in the following table The value is indicated in decimal When the power is turned on the value is 0 tee CI Come o 3 12 3 SPECIFICATIONS 3 5 Interface with External Equipment The external equipment interface list of AD61 is indicated below oe Input Voltage Operation Current I O e EA Division Internal Circuit Guaranteed Guaranteed value value 24V At OFF 0 1mA or less a 2K9 1 4W Be Phase A pulse input 10 8 to 13 2V 2 pam 12V At OFF 0 1mA or less 4702 1 4W v At OFF 0 1mA or less 23 Phase B pulse input 21010 20 90 2 2KQ 1 4W Phase B pulse input 10 8 to 13 2V eer ad At OFF 0 1mA or less ee Phase B pulse input S910 Aay O 1mA or lese e 4 5 to 5 5V 3 5 to 5 5mA 5V At ALOFF 1 5V or less 1 5V or less less 0 1mA or less 1mA 0 1mA or less less Response OFF ON ON gt OFF time 0 5ms 3ms or less 12 24Y At EE 0 1mA or less 1 4W Input ha Es reso 4 5 to 5 5V 3 5 to 5 5mA E 9V At OFF 1 5V or less 0 1mA or less ICH EA ew ES EQU Open collector Maximum voltage drop at ON 1 5V at 0 5A Response time OFF gt ON 0 1msec or less Resistor load ON gt OFF 0 1msec or less 17 35 12 24V external Input voltage 10 2 to 30V With varistor 52 to 62V
32. nce signal is enabled again Channel nel Operation Timing oat Reset signal for counter value coin Y10 Y17 Coincidence signal cidence signal latch and coincidence reset command output EQU signal By turning on this signal counter Y12 Y19 value coincidence signal is output to P outside Y13 YIA Down count If this signal is on in 1 phase mode command down count is performed By turning on this signal count oper vis yic Present value read At the rise of this signal count value request is read as present value External preset Reset signal of externa preset re IO 0 aerea reser est detection signal latch command ques 9 Table 3 4 Output Signals Description IMPORTANT YOO to OF and Y1E to 1F may not be used as they are reserved If one of the above signals is used turned on off in a sequence program the functions of the AD61 cannot be guaranteed However when the AD61 is used for remote I O YOE and YOF may be reset from the program For details refer to Section 6 3 3 9 3 SPECIFICATIONS eo In Table 3 4 the symbol indicates that the function is executed on the rise of the signal The coincidence signal latches itself on and must be reset from the sequence program Set value 7 Count input Counter value coincidence sig nal is latched upon reaching set gt value If at this time coinci dence signal reset is provided the counter value coincidence signal
33. nter OFF and CH2 ring counter ON CH1 setting pin YALNNOD ONIY LHO Printed circuit board YALNNOD INIY CHO Expanded view CH2 setting pin 4 4 Maintenance For general maintenance and inspection items to the A CPU User s Manual Since the AD61 uses an external power supply check that the external power voltage is within 10 of the rated voltage every three to six months 4 3 e ee e 5 WIRING AND INSTALLATION 5 WIRING AND INSTALLATION 5 1 Unit Arrangement Precautions Only use the AD61 on an extension base which has a power supply unit installed Do not use the AD61 on an extension base which does not have a power supply unit because power capacity may become insufficient 5 2 Wiring 5 2 1 Wiring instructions a When using high speed pulse inputs take precautions against noise in all wiring 1 Be sure to use shielded twisted pair wires Also provide Class 3 grounding 2 Do not run a twisted pair wire in paralle with any power line I O line etc which may generate noise It is necessary to run the twisted pair wire separately from the above described lines and over the shortest possible distance 3 A stabilized power supply is necessary for the pulse generated For 1 phase input connect count input signal only to phase A For 2 phase input connect count input signal to phase A and phase B Special care must be taken to prevent the input wiring from picking
34. ponding to the digital switch setting O to 3599 The encoder is directly connected to the turn table rotating shaft The encoder gives 900 pulses per rotation 2 phase I O assignment X60 to X6F 1 1 with turn table Y70 to Y7F AP 2 phase 900 pulses per rotation X20 to X2F 4 digits of digi tal switch Phase A X02 Start switch To phase A of CH1 o phase Ao of AD61 Y 40 Motor high To phase B of CH1 of AD61 speed Y41 Motor low speed Y 42 Completion signal Y44 Set value range OK Data register assignment DO Mode D1 D2 Set value D3 D4 Present value D5 D6 Preset value D7 D8 Deceleration point value When the start pushbutton is pressed the motor rotates at high speed and present the value is read 10 degrees ahead of the indexing point the speed is reduced When the counter value coincidence signal turns on the turn table is brought to a stop f the set value is 10 degrees 100 counts or less the program does not operate APP 1 APPENDICES Example of turn table indexing X002 0 0 _ ao _ _ APLS MO MO 4 SET YO76 RST YO76 K rd mg TO 6 3 DO 1 DMOV A D5 H K K DTO amp D5 1 K4 DBIN 020 D1 RST Y044 D lt D K HH D gt D1 K I M1 M1 3599 100 e _ _ X gt gt _A_A A gt SET Y 044 E e o A 5 D1 hi SET Y070 RST Y070 SET Y071 RST YO71 D7 Y044 K D MO 100 Y074 Y074 MO Y072 072 Y074 Y072 HA D7 111 114 117 SET
35. quest OFF According to application When the ring counter function is used the next preset cannot be performed if the counter coincidence signal X01 for CH1 X05 for CH2 remains on Be sure to reset the counter coincidence signal 6 PROGRAMMING 2 Programming procedure The following example shows the programming procedure for the A1 A2 and A3CPUs according to the flow chart in 1 The AD61 I O numbers are assigned to 100 to 11F 0 1 External preset detection reset MOV K8 D9 regist 1 phase constant to data register To jmoj k3 o k1 Writes mode to buffer memory x001 4 x002 3 Up down count direction setting DMOV Writes preset value 0 to data 4 registers D3 D4 Writes preset value to buffer memory Reads set value from digital switch to DBIN kaxoso DO data registers D1 D2 The set 5 value should be twice the required Writes set value to buffer memory 6 Coincidence signal reset 170 7 Preset command 8 Count enable 9 Coincidence signal output enable necessary for output to EQU ter minal High speed command ON SET 115 15 1 Reade value read request DFRO H10 K4 DS KI 10 Reads present value from buffer RST Y115 memory to data registers D5 D6 Sequence control data to be programmed by user EA E es 11 Coincidence signal reset 1 When using the A1E A2E or A3ECPU use the partial refresh instructions BH ANE
36. remains on When ring counter function has been selected counter value coincidence signal preset signal and external preset signal are latched by flip flop Therefore it is necessary to provide a reset signal to each of them 6 10 6 PROGRAMMING 6 Setting of set value data Set value write pa B DMOV K12345678 ae Data to be written is stored into D20 and D21 RST Y112 Coincidence output enable is turned off DTOP H10 k6 D20 K1 SS SEN TES PE AD61 unit write instruction MM Upper 2 digits of AD61 unit head 1 0 E Address of set value in buffer memory Head register Data to be written Word length K1 32 bits e signal reset is converted into 4 RST IY110 pulse LI coincidence output enable is turned on 1 When using the A1E A2E or A3ECPU use the partial refresh instructions Set value address and signal Coincidence Coincidence CH2 OWhen external EQU terminal is not used RST Y112 and SET Y112 are not required oH em ka vne vm O When the set value data is written to the buffer memory the counter value coincidence signal may turn on For this reason turn off the coincidence output enable before the set value is written reset the coincidence signal and finally re enable the coincidence output 6 11 6 PROGRAMMING 7 To reset coincidence signal For A1 A2 A3CPU CH1 coincidence signal reset CH1 coincidence signal reset CH2 coincidence signal re
37. rk bench 2 Do not touch the conductive areas of the printed circuit board and its electrical parts with any non grounded tools etc Under no circumstances will Mitsubishi Electric be liable or responsible for any consequential damage that may arise as a result of the installation or use of this equipment All examples and diagrams shown in this manual are intended only as an aid to understanding the text not to guarantee operation Mitsubishi Electric will accept no responsibility for actual use of the product based on these illustrative examples Owing to the very great variety in possible applications of this equipment you must satisty yourself as to its suitability for your specific application NOTES
38. set CH1 coincidence signal reset CH2 coincidence signal reset CH2 coincidence signal reset K4B1 A AAA A AN 6 PROGRAMMING 8 To enable count input CH1 count start Count input of CH1 is enabled CH2 count start Count input of CH2 is enabled To count signals from the count input terminal block this signal should be on and the disable input of external terminal block should be off 9 To enable coincidence signal output CH1 coincidence output enable da o Counter value coincidence signal of CH1 is enabled CH2 coincidence output enable eee Counter value coincidence signal of CH2 is enabled If a counter value is equal to a set value after this signal is turned on the counter value coincidence signal is output to the EQU terminal At the same time EQU LED on the indicator at the top of AD61 is lit 6 13 A EI AN ee oe AO Hees 4 oe mr rage ee ra tee e ie A To 6 PROGRAMMING 10 Present value read Present value read instruction l Counter value is read to present value zi Y115 Y1C for CH2 C ee ee ae AD61 unit read instruction MN AD61 unit head O number Address of present value register in common ly used memory K36 for CH2 Register number which will store read data Head Word length K1 32 bits Y115 Reset of latch To output to BCD 7 segment indicator DBCD D20 oa 8 digits are output to Y40 to Y5F in BCD Present value read decimal
39. supply unit and extension cable refer to Section 3 4 to 3 5 of the CPU User s Manual For a data link system the CPU must be of one of the following types A1 E CPU P21 R21 A2 E CPU P21 R21 A3 E CPU P21 R21 2 3 Cautions for System Configuration Take special care of the following points When the PC power is turned on or off process output may not perform normal operation temporarily due to the difference between the delay time and rise time of the power of PC mainframe and the external power especially DC at the outputs Also in the event of external power supply failure or PC failure the output process may perform abnormally In order to prevent the aforementioned abnormal operations and also from a failsafe viewpoint program in precautions such as an emer gency stop circuit a protection circuit and an interlock circuit against any abnormal operation which may lead to machine damage The following page shows an example of such precautions 2 2 3 SPECIFICATIONS 3 SPECIFICATIONS 3 1 General Specifications This chapter describes the general specifications and performance specifications of the AD61 The general specifications of AD61 are shown in Table 3 1 Operating ambient o Storage ambient o Operating ambient humidity 10 to 90 RH no condensation Storage ambient humidity 10 to 90 RH no condensation Frequency Amplitude Sweep Count Conforms to 10to 55Hz 0 075mm JIS C0911 55 to 150H2 1
40. ter input specifications match YES NO Has all data been handled as 24 bits long YES Is phase setting of NO input pulse correct YES ls twisted shield NO wire used for counter input wiring YES Are spurious counter values related to operation of other equipment YES NO Have adequate measures been taken against noise in the panel NO YES is sufficient distance provided between heavy current equipment and counter input NO YES Are counter values the same by providing the same count inputs to CH1 and CH2 NO YES Observe and check input wave form correct Are rise and NO fall times Sus or less 500s or less for A D6151 Hardware fault 8 2 Match counter input to speci fication conditions Correct so that data is handied as 24 bit BIN For 1 p ase input set 8 to mode register For 2 phase input set 18 Use twisted shield wire for counter input wiring Separate wiring of relevant equipment Provide CR or noise suppres sion to magnetic switch etc independently wire counter input line Separate wiring in pane 15cm or more from power line Hardware fault Correct the waveform APPENDICES APPENDICES APPENDIX 1 Application Circuit Examples 1 Example of turn table indexing Operation The indexing table is posi tioned at a corres
41. to data registers D3 D4 Set value is read from digital switch to data registers D1 D2 For set value specify 4 times of required pulse input Number value is read from digital switch Preset value is written to buffer memory Set value is written to buffer memory Coincidence signal reset Preset command Number counter reset Deceleration point clear Set value range check OK Calculation of decelera tion point D7 D8 Count enable Coincidence signal out put enable Required for output to EQU terminal High speed command ON Present value read re quest Present value is read from buffer memory to data registers D5 D6 APPENDICES Y074 X061 Y045 T 128 444 D lt D7 D5 1 e Y040 Cae SET Y041 Y074 X061 1 144 m RST Y041 K5 TO X003 1 TO 148 4 paapa SET Y 042 X003 Y042 1 RST Y042 M1 1 1 RST Y070 CO 1 RST Y040 e Oe ee IS A E E Low speed command ON Dwell time Shear command Shear complete com mand Coincidence signal reset Completion signal When using the A1E A2E or A3ECPU use the partial refresh instructions at places marked in the program APP 6 APPENDICES 3 Example using CH1 and CH2 coincidence signal output This section shows a high speed response positioning circuit example which uses the coincidence signal outputs of CH1 and CH2 EQU1 and EQU2 and has no relation to the scan time of the sequence program Di
42. truction When the power is turned on or the CPU is reset the value of the mode register is 0 For the specification of up or down count refer to Section 4 6 PROGRAMMING 3 Setting of mode register 2 phase specification 2 phase specifying condition CH1 MOV K18 D100 Set data to be written to data register AD61 unit write instruction Address of mode register AD61 unit head I O number Address of mode register in buffer memory K35 for CH2 To specify 2 phases write 18 Data to be written when 2 phases have been specified in decimal 2 phase mode Word length 4 Setting of up down count when 1 phase has been specified CH1 down count specification Down count is specified for CH1 CH2 down count specification Down count is specified for CH2 o When Y113 or Y11A is off up count is made o When the power is turned on or the CPU is reset both Y113 and Y11A are off 6 8 6 PROGRAMMING 5 Setting of preset value data to set preset value to 100 Preset data write DMOV K100 DO RRA A AD61 unit write instruction Upper 2 digits of AD61 unit head I O number Address of preset register in buffer memory Head register number DO and D1 used Setting K1 causes 32 bits to be written 1 preset 1 preset command for A1 A2 A3CPU 1 Address of preset value ross CH1 Word length 2 Write operation 1 When using the A
43. value is equal to the set value In order to use the counter coincidence signal it is necessary to turn on the coincidence signal output enable Y12 for CH1 Y19 for CH2 which is assigned to the programmable controller O 3 8 3 SPECIFICATIONS 3 3 1 O Signals To and From Programmable Controller CPU This section describes I O signals to and from programmable control ler CPU when AD61 has been assigned to slot 0 MEC a nter if is or h x00 x04 Counter value Turned on if counter value is greater than set greater value xO X05 Counter value Latched on if counter value is equa to set value coincidence Turned off by coincidence signal reset command nput signal Counter value less Turned on if counter value is less than set value on if Turned on if counter value is less than set value value is less than set value Latched on when preset request is given from X03 X07 eee elie external input Turned off when external preset PANSER detection signal is reset Table 3 3 Input Signals e Do not use X08 to XOF signals e Counter value coincidence signal is turned on when the power is turned on or reset is executed because both the counter value and set value are O Therefore always reset the counter coincidence signal first by turning the coincidence signal reset command on and then off If both the counter and set values are O after executing the coincidence signal reset command the counter value coincide
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