nimrod - High Energy Physics
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1. More TDC data TDC data End Of Group ECNT Group WCNT End Of Event Event WCNT The E bit in the channel header is the Empty Event flag The SE bit in the TDC data is the Serial Error flag detected by the NIMROD 4 Test points and Jumpers settings The NIMROD has 4 test points TP1 to TP4 next to the memory chip IC17 and one test point TP5 next to the Trigger Connector TP1 to TP4 are connected to the memory control signals TP5 is connected to pin 10 of the trigger connector and is not used The flag words and header are inserted in the event data if bit 16 is set in the channel enable flag word 11 DRAFT VERSION 1 0 NIMROD 09 09 1999 Memory Chip Select Memory Clock Write Enable Output Enable not used The user definable jumpers are the address jumpers J50 to J55 and the 3V3 power select jumper J5 If J5 pos 1 is connected the 3V3 power is obtained from the backplane if pos 2 is connected the 3V3 is coming from the on board power regulator When the NIMROD is connected to a VME64x compatible backplane all the address jumpers should be removed and J5 can be either in pos 1 or 2 In all other cases the address jumpers should be installed and J5 pos 2 connected 5 Connector pinout Trigger NC GND Trigger Reset Trigger Reset GND GND Clock Clock GND Trigger Disable Channel input Clock2. Ga0 to J50 Ga4 should be installed to define the base address of the NIMROD If no jumpers are installed and no geographical addressing is supported the default value of Ga 4 0 0x4 A32 Base Address 31 24 23 22 21 20 19 16 12 8 4 0 0 0 Ga4 Ga3 Ga2 Gai Gad 0 0 0 0 0 A24 Base Address 23 22 21 20 19 16 12 8 4 0 Ga4 Ga3 Ga2 Gai Ga0 0 0 0 0 0 Figure 5 Base address Valid Address Modifier codes are 0x09 and OxOD for A24D32 transfers 0x39 and 0x3D for A24D32 transfers and Ox2F for accessing of the Configuration ROM CR and Control amp Status Register CSR The Configuration ROM is a 64 x 8 bit ROM that contains module identification data The ROM addresses are mapped in the VME address space from address offset 0x03 to OxFF on every fourth byte DRAFT VERSION 1 0 NIMROD 09 09 1999 The Control amp Status Register Control amp Status Bit Set Register address offset 0x7FFFB 1 put module in reset mode 1 module is in reset mode Bit 7 0 no effect 0 module is not in reset mode Bit4 1 enable module 1 module is enabled 0 no effect 0 module is disabled no effect module generated BERR no effect module did not generate BERR Control amp Status Bit Clear Register address offset 0x7FFFC On Writes On Reads 1 remove module from reset mode 1 module is in reset mode Bit 7 0 no effect 0 module is no
3. The NIMROD fanout module is connected to the NIMROD via row a and c of the VME P2 connector It connects the TDCs to the NIMROD inputs and multiplexes the trigger and reset signals to the TDCs The VME interface is used to control the NIMROD read the event data and generate test triggers and test resets DRAFT VERSION 1 0 NIMROD E L COHF iB WE ons f Lx ib BEM E Nm Oro e A x CERES xate AAA I Ri pe t See le E E LIT Figure 3 NIMROD front NIMROD 09 09 1999 On the frontpanel are two 10 pin connectors The upper connector labeled Test is a JTAG port used to perform in system programming of the FPGAs on the NIMROD The lower connector labeled Trigger must be connected to the CTP via the trigger bus to receive the 40 MHz TDC clock the coded trigger and reset signals and to return the inhibit trigger signal The signal levels are differential Positive ECL and must be terminated with 100 Ohm after the last NIMROD The combined inhibit trigger signals from the NIMRODs are terminated in the CTP The coding of the trigger reset signals on three sequential clock pulses is as follows 1 0 0 2 Trigger 1 0 1 gt Event Counter Reset ECR 1 1 0 gt Bunch Counter Reset BCR 1 1 1 gt Global Reset Due to coding of the Trigger and Reset internal in the NIMROD the maximum trigger frequency is the system clock divided by three This is 20MHz 3 6 7 MHz so the minimal deadtime i
4. Clock Trigger Reset Data Data Trigger Reset Strobe Strobe GND GND 1 2 3 4 5 6 7 8 9 1 12 DRAFT VERSION 1 0 VME Pl DO NIMROD NC D8 09 09 1999 D1 NC D9 D2 NC D10 D3 BGOIN_N Dil D4 BGOOUT_N D12 D5 BGIIN N D13 D6 BGIOUT N D14 oo 10 NBR WO D7 BG2IN_N D15 GND BG2OUT_N GND NC BG3IN_N NC GND BG3OUT N BERR N DS1 N NC SYS RES N DSO_N NC LWORD N WRITE N NC AM5 GND NC A23 DTACK_N AMO A22 GND AMI A21 AS N AM2 A20 GND AM3 A19 IACK N A18 IACKIN N NC A17 IACKOUT N NC A16 AMA A15 A7 Al4 A6 A13 AS A12 A4 All A3 A10 A2 A9 Al A8 NC NC 13 DRAFT VERSION 1 0 VME P2 GND NIMROD GND 09 09 1999 SER DATAO SER STRBO SER DATAI SER STRBI GND GND SER DATA2 SER STRB2 SER DATA3 SER STRB3 GND GND oo 10 NBR WO Re SER_DATA4 SER_STRB4 SER_DATAS SER_STRB5 GND GND SER_DATA6 SER STRB6 SER DATA7 SER STRB7 GND GND SER DATAS SER STRBS8 SER DATA9 SER STRB9 GND GND SER DATAA SER STRBA SER DA
5. register is 35 bits 40 MHz This results in an input rate of the FIFO of 1 14 MHz 875 ns per word With a system clock of 20 MHz the output rate is1 11 MHz 20 divided by 18 which is almost the same as the input rate DRAFT VERSION 1 0 NIMROD 09 09 1999 So the FIFO will only be filled when the write to memory is inhibited by a memory full or a LUT full condition The system clock of the first version NIMROD was 7 5 MHz So the output rate of the FIFO was 0 41 MHz 2 44 us which is much lower than the input rate Therefor a mechanism is built in that when the FIFO is almost full 56 words only the Begin Of Group and End Of Group words are stored in the FIFO This to prevent corruption of the bookkeeping of the event fragments 2 4 Event memory The event memory is a synchronous ZBT RAM that does not need the deselect cycle between a write and a read cycle The memory clock is 40MHz this enables a write and a read during one system clock cycle The memory has 17 circular buffers of 2K 32 bit words one for every Channel plus the Header For debugging purposes the memory is accessible from VME the address map is given in the next chapter 2 5 VME Interface The VME Interface is compliant to VME64x and all devices can be accessed in the A24D32 and A32D32 addressing modes The base address is defined by the Geographical Address pins on the backplane connector In case the backplane does not support geographical addressing jumpers J54
6. A K H NATIONAL INSTITUTE FOR NUCLEAR AND HIGH ENERGY PHYSICS ETR 99 06 NIMROD 16 channel read out driver for the Drift Chambers used in the L3 Cosmics project September 1999 Project no 32010 H L Groenstege P A M Rewiersma T A M Wijnen A N M Zwart email albert nikhef nl The NIKHEF MDT read out driver is a VME module that collects data from the TDCs connected to the Drift Chambers The data from several MDT chambers is merged and can be read by a VME master Check for most recent version http www nikhef nl pub departments et L3 cosmics NIKHEF DEPARTMENT OF P O box 41882 NL 1009 DB AMSTERDAM ELECTRONIC TECHNOLOGY DRAFT VERSION 1 0 NIMROD 09 09 1999 Table of contents 1 NIMROD 3 1 1 NIMROD connections 4 2 General description 7 2 1 Block diagram 7 2 2 Frontend FIFO 7 2 3 Event memory 8 2 4 VME Interface 8 3 Data format 10 3 1 Data format of a channel input 11 3 2 Event Data format of the NIMROD 11 4 Connector pinout 11 Abbreviations 15 Figures Figure 1 NIMROD modules Figure 2 NIMROD connections Figure 3 NIMROD front Figure 4 Block Diagram Figure 5 Base address 00 DU Hb UU DRAFT VERSION 1 0 NIMROD 09 09 1999 1 NIMROD The NIMROD NIKHEF MDT Read Out Driver concentrates the data from a number of TDCs into a single output register The unit receives trigger and clock from the CTP Central Trigger Processor and distributes this to the TDCs In the L3 Cosmics project t
7. TAB SER STRBB GND GND SER DATAC SER STRBC SER DATAD SER STRBD GND GND SER DATAE SER STRBE SER DATAF SER STRBF GND GND GND GND GND GND GND GND GND GND CPCTRST CPCTRCLK NC NC NC NC 14 DRAFT VERSION 1 0 NIMROD 09 09 1999 6 Abbreviations Abbreviations and other less well known definitions used in this and other documents BCID BCR CPC CTP CTT ECR FELink JTAG LVDS LUT Bunch Crossing IDentifier Reset by BCR Bunch Counter Reset used to synchronize Front End electronics Cosmics Personality Card Contains TDCs and interface logic Central Trigger Processor Generates first level trigger Cosmics Trigger and Timing module Event Counter Reset Front End Link Carries the Reset Trigger signals to the TDC and transports the TDC data to the NIMROD Joint Test Action Group IEEE 1149 1 Functional test and programming facility Low Voltage Differential Signaling 400 mV Compatible with 3V and 5V supply voltages Look Up Table contains start addresses of events in memory 15
8. d FIFO Simultaneously the TDCs will sent data via the FELinks to the NIMROD This data is converted from serial to parallel 32 bit and stored into a FIFO The data is read from the FIFO If it is a leader of an event Begin Of Group the start address of the event is stored in the LUT On the next address the Begin Of Group word is stored in the memory followed by the next word from the FIFO until the trailer of the event End Of Group is detected Then the Channel Header word is stored in the memory on the begin address of the event When there is no data between the Begin Of Group BOG and End Of Group EOG the Event Empty bit is set in the Channel Header After the writing of the Channel Header the event present counter is incremented If the event present counter is not equal to zero the event present flag of this channel is asserted When all channels have an event present the Read Out block starts a read out cycle At this point the Header block and the enabled channels get the read addresses from the LUTs the Header block reads the Begin Of Event from the memory and puts it in the Output Register in the VME interface Then Read Out waits for the VME Master to read the output register before it enables the Header block to get the next word If the Header block has read the data of the event it decrements its event present counter and enables the first enabled channel to read the data until the read address is equal to the next address in th
9. e LUT or equal to the write address Then the channel decrements its event counter and enables the next channel to send its data This continues until all channels have read the event data from the memory The Read Out now terminates the read out cycle and writes the End Of Event in the Output Register If the Read Out detects an Empty Event bit in a Channel Header it will skip this channel thus performing a zero suppressed read out This zero suppress is bypassed on event 1 modulo 0x1000 events The data rate of the Read Out via VME is 6 MB sec 670 ns word 2 2 Shift Register The serial data from the TDCs with LSB first is shifted in this register if the last bit MSB is shifted in the parity is checked When the parity is not correct the Serial Error Flag is asserted and the Serial Error bit bit 26 is set in the TDC data Then the data is loaded in the Frontend FIFO The serial error flag will be cleared when the flag word is written in the Event memory 2 3 Frontend FIFO The data in the event memory is written by 18 sources 16 Channels the Header and the VME interface These sources are scheduled with the system clock Therefore a 64 words deep Frontend FIFO is implemented for every channel to store the data which is not yet written in the Event Memory To prevent the FIFO to overrun an inhibit trigger is generated when the FIFO is half full 32 words The inhibit trigger is released when the FIFO is empty The input rate of the shift
10. he function of the CTP is fulfilled by the CTT V2 Cosmics Trigger and Timing m ule and the TDCs are interfaced to the NIMROD on a CPC Cosmics Personality Card A complete NIMROD consists of a set of modules a NIMROD a NIMROD fanout module and four patchpanel boards The NIMROD is a standard 6U 160 mm VME module Several NIMRODs may share a VME crate controlled by a single master This controller reads the event data and takes care of various settings in the NIMRODs patchpane boards MILD MIM ROD fan out Figure 1 NIMROD modules A 24 channel TDC for the ATLAS precision muon chambers Y Arai KEK J Christiansen CERN ETR 99 01 Cosmics Trigger and Timing Module H Verkooyen www nikhef nl pub departments et L3 cosmics gt ETR 99 02 Cosmics Personality Card H Groenstege et all www nikhef nl pub departments et L3 cosmics DRAFT VERSION 1 0 NIMROD 09 09 1999 VME TEST Channel 3 Channel 2 Channel 1 NIMROD Channel 0 CH 4 7 CH 0 3 from CTP gt TRIGGER NIMROD FANOUT PL CH 8 11 CH 12 15 Channel 15 Channel 14 Channel 13 Channel 12 Figure 2 NIMROD connections 1 1 NIMROD connections Each NIMROD accepts a maximum of 16 FELinks Front End Links via the NIMROD_ Fanout module and a patch panel The FELink connector is a standard shielded RJ45 and the cable is a shielded CAT 5 network cable
11. if bit 2 1s set the interrupt level is 2 and so on until bit 7 then the interrupt level is 7 bit O is not used Only one bit must be set in the interrupt request level register After reset the default interrupt request level is 2 The interrupt vector is set in the interrupt vector register at address offset Ox114 3 Data format The description below gives a summary of the data format that the NIMROD uses The data format is compliant to the L3 Cosmics data format It should be noted that the NIMROD only tests on BOG and EOG for administration purposes and that all incoming data appears in the event data KUN internal note HEN425 The L3 Cosmics Data format Thei Wijnen et all Iwww hef kun nl 13c 10 DRAFT VERSION 1 0 NIMROD 09 09 1999 3 1 Data format of a channel input Misi dn n Begin Of Group ECNT TDC data TDC data More TDC data TDC data End Of Group ECNT Group WCNT 3 2 Event Data format of the NIMROD Description Begin Of HE ECNT 24bits Flag Heade 0000 0000 0000 LUT full flags 000x XXXX XXXX Memory full flags 000x Xxxx XXXX FIFO half full flags 000x XXXX XXXX Serial error flags 000x XXXX XXXX Channel Header 000E 0000 Channel ID Begin Of Group ECNT Card ID TDC data TDC data More TDC data TDC data End Of Group Group WCNT Channel Header 0000 Channel ID Begin Of Group Card ID TDC data TDC data
12. pV s i ee op HUS Kenas peay uuqua py 7 MOL LEX9SZ uua M uonoejeg d Bed PON as RES im isse 909 t iud sselppy sselppy 40 4849U99 A P ssejppy PER PPV XNA 914M lt INO eu aides 0 auueyo urn 91qeu3 al ej 5 sbe uonesuy f Jo peeu Srqeu3 sBejy Ada siaBBiuL 3 10 eJ9uas Ul peey alqeua sseuppy pue E 996 uw E E L X OH pesed quo peoy ru quen py HALLIOSZ uen yy E oy 49junoQ peau 413 eje 9 SHO ce im eo PORN quen3 e sSalppy ssappy AOPBIBUSH k warn P ssouppy Wane E So a N oen ageug 560 abel JopeeH Block Diagram Figure 4 DRAFT VERSION 1 0 NIMROD 09 09 1999 2 General description 2 1 Block diagram The trigger and reset from the CTP is decoded in the Trigger and Reset Decoder The coded signals are distributed to the TDCs via the FELinks The Global Reset is used internally to reset all counters and FIFOs in the NIMROD the Event Counter Reset only clears the Event Counter in the Header block and the Bunch Counter Reset is not used in the NIMROD On a trigger the Event Counter in the Header block is incremented and the data is stored in a circular buffer in the Event Memory The address is stored in the Look Up Table LUT to be used for read out Then if the header enable bit is set a flag header word 0x18100000 is stored hereafter the flags are read and stored on the next addresses When the circular buffer or the LUT is full writing is inhibited and the triggers are stored in the Fronten
13. s 150ns All FELink signals to or from the TDCs are Low Voltage Differential Signals LVDS The serial data from the TDCs is received via two differential lines using DS coding without handshaking The data consist of a startbit followed by 32 bit TDC data a paritybit and a stopbit The rate on this connection is 40 Mbit s The two signals from the NIMROD to the TDCs are also distributed via differential lines e The 40 MHz TDC clock All signals are synchronous to this clock e The coded trigger reset signal Which is the trigger reset signal from the CTP after a delay of four clock pulses For test purposes the NIMROD mode register can also generate this signal 4Jepooeg san 19594 poo JeBBuL jeseueDDu yasau juenq Jase jeqoip e2ej191u AINA 49019 d 19 w044 UT 93HM e1qeu3 MO SUM alqeug lt ur peat ejgeug o L peey quasalg juon3 MO Pray egeuy SsoJppy AJ0uJ8 N quaag eed UL a un a1qeu3 GL suueyg eye te beg f uo asu sey f i du Sp4Jo NO pesy e qeu Ad pJOM ror ma 4o e4 u 9 eyed dos Aua v9 e 19 3siBo4 sgig os Jussara query SS9Jp
14. t in reset mode Bit4 1 disable module 1 module is enabled 0 no effect 0 module is disabled clear BERR bit module generated BERR no effect module did not generate BERR The module reset can be done in two ways 1 A short reset Global Reset or bit 7 in CSR is asserted not longer then 16 system clock cycles Resets all counters and FIFOs 2 Along reset bit 7 in CSR is asserted longer then 16 system clock cycles This reset does the same as a short reset but also clears the LUTs After this reset one has to wait for 786 system clock cycles for the clear LUT to complete The Mode Register Mode Bit Set Register address offset 0xX7FFF3 On Writes On Reads enable interrupt interrupt is enabled no effect interrupt is disabled Generate bunch reset bunch reset generated no effect no bunch reset generated Generate event reset event reset generated no effect no event reset generated Generate global reset global reset generated no effect no global reset generated Generate trigger trigger generated no effect no trigger generated O O O O O e oA O O O re O DRAFT VERSION 1 0 NIMROD 09 09 1999 Mode Bit Clear Register address offset 0x7FFEF On Writes On Reads Disable interrupt interrupt is enabled no effect interrupt is disabled clear bunch reset bit bunch reset generated no effect no bunch reset generated clear event reset bit event reset generated no effec
15. t no event reset generated clear global reset bit global reset generated no effect no global reset generated clear trigger bit trigger generated no effect no trigger generated O O O 1 0 O O e O O O O e The Event Memory has an address offset of 0x40000 On this address the 8KB cyclic buffer of channel O starts channel 1 starts at 0x42000 etc until the buffer of the header that starts at 0x60000 The Flags words are read only and the address offsets are 0x200 event present 0x210 FIFO empty 0x204 inhibit 0x214 FIFO half full 0x208 LUT full 0x218 channel enable 0x20C memory full Ox21C serial error Except for the channel enable the flags are read only Bit 16 of the flag words is the header flag bit 15 to O are the flags of channel 15 to 0 Reading of the flags should not be done when the trigger is enabled this corrupts the flag words in the event data The readout register is mapped to multiple addresses to enable block or DMA transfers the address offset is 0x300 to 0x1000 Reading the readout register when there is no event present will return 0x0 The interrupter is of a single level type An interrupt is generated when the interrupt enable is set in the mode register and the event present flags of all enabled channels are set The interrupt request level is set in the interrupt request register at address offset Ox110 If bit 1 is set the interrupt level is 1
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