TIP-VBY1HS Data Sheet
Contents
1. 4 Specification outline Table 4 1 TIP VBY1HS Specification Core Specifics Supported FPGA Family Virtex 6 LXT SXT Spartan 6 LXT 614Mbps 810Mbps 600Mbps 3 75Gbps 1 2288Gbps 1 62Gbps 2 45 Gbps 3 125Gbps 1 Performance Serial Line Rate Core Resources in case of Spartan 6 2 2 5 2 Transmitter Receiver 02 2 2 9 2 Core Highlights Designed Verification RIL Test Bench Hardware Verification Passed the connectivity test A A N AB N gt Provided with Core Data Sheet Transmitter Receiver Core User Manual Documentation Transceiver PLL Setting EstimateSheet xls Reference Design User Manual Design File Formats NGC Netlist Main Link module Instantiation Template Verilog HDL Wrapper UCF User Constraint File Timing Constraints Transceiver Physical Constraints Design Tool Requirements Xilinx Implement Tools ISE 11 4 Logic Edition and above Constraints File 1 Spartan 6 LXT Speed grade 2 has a line speed limit up to 2 7Gbps 2 Number of the Clock resources PLLs and BUFGs will change according to the user logic implementation and board circuit Rev1 00 TOKYO ELECTRON DEVICE LIMITED TIP VBY1HS DS inreviun 5 Functional Overview 5 1 Transmitter Core In the first the Transmitter core allocates the video stream and control signals to the Main links according to the number of the data lanes Each Main Link tra2. Schedule of Figures Figure 5 1 Transmitter Core Block Diagram 7 Figure 5 2 Receiver Core Block Diagram 8 Figure 7 1 TIP VBY1HS Clock Construction cece cccccecceeeeeece cece eeseeseeseeeseeeseeeaeeeaes 11 Figure 7 2 Transmitter FPGA Recommended Board 12 Figure 7 3 Receiver FPGA Recommended Board 12 Schedule of Tables Table 4 1 TIP VBY1HS Specification Hn 6 Table 6 1 Transmitter Core I O Signals 9 Table 6 2 Receiver Core I O Signals 10 Table 7 1 Virtex 6 GTX Reference Clock 11 Table 7 2 Spartan 6 GTP Reference Clock Characteristics 11 Tables Tarametemzduobr Table usos PIN 13 Rev1 00 TOKYO ELECTRON DEVICE LIMITED TIP VBY1HS DS inreviun 1 Introduction V by One HS standard has been developed by THine Electronics Inc to offer capabilities for Flat Panel Display FPD markets that are requiring ever higher frame rates and higher resolutions The TIP VBY1HS Core provided by Tokyo Electron Device Ltd TED is a high performance flexible solution for a high sp
3. Input DI 39 0 1 Input CTL 23 0 2 Input 3 0 PRE 3 0 Input Pre Emphasis Control FIELD BET Field BET Mode Enable BEEN Status Signal 1 Video data width is dependent on the Byte Mode setting with byte boundary 24 32 40 bits as following table Input 2 Control data width is dependent on the Byte Mode setting with byte boundary 8 16 24 bits as following table Byte Mode DI 39 0 CTL 23 0 Rev1 00 TOKYO ELECTRON DEVICE LIMITED TIP VBY1HS DS inreviun 6 2 Receiver Core Table 6 2 Receiver Core I O Signals Direction Polarity Description RN mu V Fwwbw MUI LM 71 17 CLKOUT output Recovery clock out for External PLL optional Main Link Interface ix ee exo Nino _ Huc oma v v TS Pk Owu V edMaembe 0 ooo Own coooa wu FeWBETModecnabe _ 00000000000 Status Signal FIELD BET CHK Output Filed BET mode Check Error Status 1 Video data width is dependent on the Byte Mode setting with byte boundary 24 32 40 bits as following table 2 Control data width is dependent on the Byte Mode setting with byte boundary 8 16 24 bits as following table 21 39 0 23 0 1 00 T
4. OKYO ELECTRON DEVICE LIMITED 10 TIP VBY1HS DS inreviumn 7T Reference Clock 7 1 Clock Construction Besides the pixel clock TIP VBY1HS Transmitter and Receiver Core require the high quality reference clock REFCLK P N port conforming to the GTP GTX transceiver s specification Especially the REFCLK of the Receiver Core side is important because it s frequency deviation is limited to the transmission rate of the Data Lane PXCLK PXCLK REFCLK P N should be generated from l PXCLK Frequency locking is required Transmitter Core Receiver Core REFCLK_P REFCLK_N REFCLKP gt REFCLK_N po Frequency deviation of REFCLK P N is limited to the transmission rate Figure 7 1 TIP VBY1HS Clock Construction In addition REFCLK is recommended to be supplied by the differential pair port and to be satisfied the specification shown in Table 6 1 and Table 6 2 For more information refer to the FPGA data sheets Table 7 1 Virtex 6 GTX Reference Clock Characteristics Symbol Description Max Units Reference clock frequency range 625 650 MHz TDCREF Reference clock duty cycle Rxppmtol Data REFCLK PPM offset tolerance Table 7 2 Spartan 6 GTP Reference Clock Characteristics Symbol Description _ Typ Units Reference dock Jiter tolerance 60 180 ps TDCREF Reference clock duty cycle Rxppmtol Date REFCLK PPM o
5. design labeled DO NOT MODIFY TED also offers a reference design with their evaluation board and a contract based development service for customized design or additional function design ex more than 16 data lanes for Virtex 6 12 Ordering Information Example TIP VBY1HS PROJ License Type PROJ Project License for product SITE Site License for division Rev1 00 TOKYO ELECTRON DEVICE LIMITED 0 Q VBY1HS TIP ee p o p p o o p o oo ee p d o o o o o oo o o 1 gt O am H Q 1 O gt x O H Rev1 00 TIP VBY1HS DS inreviun TOKYO ELECTRON DEVICE LIMITED Tokyo Electron Device Limited Inrevium Division Yokohama East Square 1 4 Kinko cho Kanagawa ku Yokohama City Kanagawa 221 0056 Japan 1 81 45 448 4031 81 45 448 4059 URL http www inrevium jp eng Email inrevium contact teldevice co jp Your Local Contact The Information described in this document will be changed from time to time without prior notice If you plan to buy and use this device product described herein please contact the sales person or address specified herein Tokyo Electron Device Limited shall not be liable for any claim by third party a
6. e locked to the recovery clock and generate the REFCLK of frequency that is completely the same as the Transmitter side Receiver FPGA Receiver Main Links VCXO PLL Clock Synthesizer amp Jitter Cleaner Figure 7 3 Receiver FPGA Recommended Board Design Rev1 00 TOKYO ELECTRON DEVICE LIMITED TIP VBY1HS DS inreviun 8 Parameterization Table 8 1 Parameterization Table P_PLL_DIVSEL_xxx PLL settings of the GTX GTP transceivers P PXCLK xxx settings of the PLL that generates the internal clock from the pixel clock oettings of the PLL that generates the internal clock from the GTPCLKOUT port the GTX GTP transceivers 1 2 3 Refer to the TIP VBY1 TX RX User Manual and GTX GTP transceivers User Guide for the details of these parameters 9 Verification The TIP VBY1HS Core has been verified with the RTL simulation and hardware validation of connectivity test by THine Electronics Inc 9 1 Simulation A highly parameterizable command based test bench was used to test the core All byte modes and data lane numbers are tested by following construcition Input command Onput message Video in TB SIM MODEL TX FPGA TOP _ _ TXn 1 P N RXn 1 P Video out 9 2 Hardware Validation The TIP VBY1HS Core has been validated using CVK kit of Tokyo Electron Device Ltd TED The hardware has been tested against the V by One HS evaluation board from THine e
7. ed into the main function blocks as follows eMain Link The Main Link is a main function block provided as the netlist file ngc Main Link consists of unpacker de scrambler decoder de serializer and receiver link monitor Each data lane has own Main Link block eDe formatter De formatter matches the skew of the packet data from the Main Links and regenerates the user driven stream of video data and control signals from the allocated data in the Main Links eClock Reset Generator This block makes all clocks and reset signals required in the Receiver core from the recovery clock from the transceiver in Main block Appropriate frequency clocks adjust the rate difference between the function blocks and regenerate the pixel clock of the Transmitter side Rev1 00 TOKYO ELECTRON DEVICE LIMITED 8 TIP VBY1HS DS inreviun 6 I O Signals 6 1 Transmitter Core Table 6 1 Transmitter Core I O Signals PDN npt C __ Main Link Interface ouput High speed serial data lanes positve V TXO N n 0 Output High speed serial data lanes negative HTPDN Input Hot plug detect LOCKN Lock detect User Data Interface Pixel Clock Vertical sync pulse lt Input PXCLK VSYNC HSYNC Input Input Input Horizontal sync pulse m I Video data enable Video data Control data Mode Setting Drive Strength Control
8. eed transmission of video signals designed to the V by One HS standard for the Xilinx FPGA State of the art Virtex 6 LXT SXT and Spartan 6 LXT are supported 2 Features Protocol compliant with V by One HS standard provided by THine Electronics Inc Independent Transmitter and Receiver module Supports 1 2 4 and 8 lanes operations Uses the transceivers of Spartan 6 LXT families and the GTX transceivers of Virtex 6 LXT SXT families Supports up to 3 5Gbps data rate per lane effective data rate 3Gbps using Virtex 6 GTX transceiver up to 3 125Gbps using Spartan 6 GTP transceivers Elastic buffers and Lane alignment Data scrambling and Clock Data Recovery CDR to reduce EMI Variable settings of the driver swing pre emphasis Flexible implementation and package compatibility 3 References V by One HS Standard Version 1 2 Jan 15 2009 by THine Electronics Inc TIP VBY1HS TX Transmitter UserManual TIP VBY1HS RX Receiver UserManual TIP VBY1HS CVKReferenceDesign UserManual TIP VBY1HS Transceiver PLL Setting EstimateSheet Virtex 6 FPGA GTX Transceivers User Guide UG366 v2 2 Feb 23 2010 Virtex 6 FPGA Data Sheet DC and Switching Characteristics DS152 v2 2 Feb 9 2010 Spartan 6 FPGA GTP Transceivers User Guide UG386 v2 1 Mar 30 2010 Spartan 6 FPGA Data Sheet DC and Switching Characteristics DS162 v1 4 Mar 10 2010 Rev1 00 TOKYO ELECTRON DEVICE LIMITED 5 TIP VBY1HS DS inreviun
9. ffset tolerance 200 200 ppm Generally frequency of the REFCLK is same to the pixel clock it is also possible to use the REFCLK of the frequency different from the pixel clock by setting the PLL of the GTP GTX Transceivers TIP VBY1HS Transceiver PLL Settings EstimateSheet Excel Sheet is useful to calculate the frequency that can be set to the REFCLK Rev1 00 TOKYO ELECTRON DEVICE LIMITED 11 TIP VBY1HS DS inreviun 7 2 Recommended Board Design Following Figures show the recommended REFCLK construction of the board e Transmitter side Figure 7 2 shows the construction of the Transmitter side It has the external PLL IC to clean up the jitter of the pixel clock or synthesize the frequency that Is required for the REFCLK input block in the FPGA generates the appropriate frequency to the external PLL IC s input so this block is optional Transmitter FPGA Pixel Clock gt TXn Transmitter PLL Main Links Clock Synthesizer prede amp Jitter Cleaner Figure 7 2 Transmitter FPGA Recommended Board Design e Receiver side Figure 7 3 shows the construction of the Receiver side In addition to the same purpose as the Transmitter side the Receiver side has the external VCXO PLL IC to generate the initial REFCLK of the frequency that is required for the Clock Data Recovery CDR of the GTP GTX Transceivers After CDR is locked this VCXO PLL should be phas
10. inreviunW Preliminary TIP VBY1HS Data Sheet V by One9 HS Standard IP for Xilinx FPGA Rev 1 00 High speed and Reduced digital connection concept Tokyo Electron Device Ltd Rev1 00 TOKYO ELECTRON DEVICE LIMITED 1 inreviun Revision History The following table shows the revision history for this document Revision Dae Comments Rev 1 0 0E 2010 04 12 Rev1 00 TOKYO ELECTRON DEVICE LIMITED inreviun Table of Contents WO dq 5 2 5 3 References ERR H 5 SSC lt 6 5 Functional Overview 7 SE ost ts oe dia f 2 2 B Lem 8 o O FESE T 9 9 6 2 Receiver Core 10 FAN Reference Clock aren ener een 11 Clock Constr HON EN ES 11 7 2 Recommended Board 12 8 AU Ocoee 13 SEIS Nie iio ner 13 DM 13 9 2 Hardware ValidatlO 13 SUDO ON Ure 14 Melee amp 1 Gall gt UTE 14 NZ ORGS pm 14 Rev1 00 TOKYO ELECTRON DEVICE LIMITED inreviun
11. lectronics Inc for warranty of the connectibity Rev1 00 TOKYO ELECTRON DEVICE LIMITED TIP VBY1HS DS inreviun 10 Family Support The TIP VBY1HS Core was designed to target the Virtex 6 and Spartan 6 FPGA families This Core can operate at full speed with the Virtex 6 all speed grades and at limited speed with Spartan 6 each speed grade part Below is a list of supported device families 600Mbps 3 75Gbps data rate per lane same as the standard e Virtex 6 LXT all speed grade Virtex 6 SXT all speed grade 614Mbps 810Mbps 1 2288Gbps 1 62Gbps 2 457 Gbps 3 125Gbps data rate per lane Spartan 6 LXT 3 speed grade 614Mbps 810Mbps 1 2288Gbps 1 62Gbps 2 457 Gbps 2 7Gbps data rate per lane Spartan 6 LXT 2 speed grade Fllowing equation shows how to determine the data rate of the lane Gbps fbatakate BITByteMode X X L 25 8B 10B Example Byte mode 4byte Pixel Clock frequency 148 5MHz Number of data lanes 2 Data rate per lane 32bit x 148 5MHz x 1 25 2 2 97Gbps 11 Technical Support Tokyo Electron Device Ltd TED provides technical support for this IP Core when used as described in the product documentation TED cannot guarantee timing functionality or support of product if implemented in devices that are not defined in the documentation if customized beyond that allowed in the product documentation of if changes are made to any section of the
12. lleging an infringement of patent right or any other intellectual property right where alleged liability of Users arises by reason of using the information and drawing described in this document Tokyo Electron Device Limited shall not be liable for any claim by third party alleging an infringement of the patent right utility model right circuit layout use right copyright or any other intellectual property right where alleged liability of Users arises by reason of using this device product in combination with other products or of any derivative products integrating this device product This device product is not designed manufactured or intended for use 1 in hazardous environment requiring extremely high safety including without limitation in operation of nuclear reaction control in nuclear facility aircraft flight control air traffic control mass transport control medical life support system missile launch control in weapon system in which the failure of this device product could have a serious effect to the public and lead directly to death personal injury severe physical damage or other loss or 2 in any other environment requiring extremely high reliability including without limitation in operation of submarine transmissions or space satellite 2010 Tokyo Electron Device Limited printed in Japan Apr 2010 Rev1 00 TOKYO ELECTRON DEVICE LIMITED
13. nsfers the allocated data through the High speed serial transceiver with framing packet data mapping scrambling and encoding The Transmitter core also has a training function for the link start up with the receiver side while checking the Hot plug and CDR Lock status signal In order to check the quality of the high speed serial data lines the Transmitter core has an operation mode in which they act as the bit error tester BET called Field BET mode Figure 5 1 shows the function block diagram of the Transmitter core FPGA TIP VBY1HS Transmitter Wrapper Tx Main Link N Netlist Tx Main Link 0 D D D D Netlist a Link status Clock Reset Generate NN Reference clock PLL Jitter cleaner Video data Control gt Data lanes J931euuo Test mode Parameter Figure 5 1 Transmitter Core Block Diagram The Transmitter core can be classified into the main function blocks as follows eMain Link The Main Link is a main function block provided as the netlist file ngc Main Link consists of packer scrambler encoder serializer and transmitter link monitor Each data lane has own Main Link block eFormatter The Formatter interfaces to a user driven stream of video data and control signals According to the number of the Main Links this block allocates the video data and matches the timing to the Main Link interface eClock Reset Generator Thi
14. s block makes all clocks and reset signals required in the Transmitter core Appropriate frequency clocks adjust the rate difference between the function blocks Rev1 00 TOKYO ELECTRON DEVICE LIMITED 7 TIP VBY1HS DS 5 2 Receiver Core The Receiver core has a symmetrical function with the Transmitter core Each Main Links receives the data from the transmitter side through the High speed serial transceiver and regenerates the allocated data with decoding de scrambling packet data un mapping and de framing In the end these framing data from the Main Links combined to regenerate the original stream of video data and control signals The Receiver core also has a training function for the link start up with the transmitter side while generating the Hot plug and CDR Lock status signal In order to check the quality of the high speed serial data lines the Receiver core has an operation mode in which they act as the bit error tester BET called Field BET mode Figure 5 2 shows the function block diagram of the Receiver core FPGA TIP_VBY1HS Receiver Wrapper M a Rx Main Link N Netlist lt Link 0 __ Netlist Link status Clock Reset Generate PLL Jitter cleaner Figure 5 2 Receiver Core Block Diagram Video data Data lanes lt Control 49318uu0J eq lt Test mode 4 Parameter The Receiver core can be classifi
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