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Pluto 5 Controller Manual

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1. 2 3 4 6 7 9 18 00 15 lt gt 2 Ap 23 gt _368MZ 36 53 TXDE 16 RXDA RXDE 16 13 TXDF 13 TXDF 16 58 RXDB or L RXDF 16 010 32 RISE 5 r 012 B 8 0 U53 D15 OPS 16 n af sue gt 368ME xia K H2 TXDC 16 ops 290 m RXDA RXDC 16 96 o END 13 2 8 CTSE 28 H TXDD 16 H CTSE 16 28 po RXDB RXDD 16 zd CTSF 16 010 g7 Di 32 RISC gt DT 19 02 14 RTSD 16 WS ce 121 RTSD 16 E vec 210 ips 42 Di3 20 DS RESET 389 RESET 014 251 21 1 57 Aoo m A1 4141 68692PLOC CTSC 16 A4 CTSD 16 CS DUARTO DSRC 16 gez CDC 16 2 RW FW 42 419 ps 42 vee 10 RESET RESET DSACKO 10 USS 2 39 DSACKO DTACK 29 PBS Fes 24 Ra 0 TXDA 33 16 68692PLOC 37 RDA degia GND xo 08 28 TXDB 744 RXDH TXDH 17 Do RXDB x L RXDH 17 Do 18 Di 010 27101 32 RTSG 011 19
2. HEBER LTD 1996 2002 7AHCT139 Fax 44 0 1453 885013 7 OP 0 63 9 022 26 vec vec vec vec 18 5 9014 56 D4 18 5 2014 5 5 GE 1 1 1 Sls S S SELO 33 ss 21 4 c2 SEO 815 GE 815 7 OP36 100 100 100 100 582 P 84 g 14 OP24 EEE cr EK 93 OP28 15 16 15 OP20 GND GND GND GND 13d CE OPB 134 95 16 12 88 Sa 95 17 17 vcco 2 voc H GND veco 2 vec GND PGND GND PGND GND A PGND d GND PGND HA GND GND PGND GND GND TPIC6259 TPIC6259 1 1 u23 u27 b gr 0 23 Za Di 18 5 mE 05 18 5 Ge dea SELO 3 ay e 45 A1 1 SELO 8159 GIE OP33 815 dde EEE ZOZ 0 14 25 SEE 12 34 29 94 17 94 EL 21 14 da Hez 95 16 069 134 95118 OPIS EO 46 GE p e OPS 3 veco 21 voc SND veco 2 voc PGND PGND PGND 4 GND 2 pen 4 enD 9 PGND GND GND PGND GND TPIC6259 TPIO6259 5 SEL2 1 1 24 28 74 14 D2 18 4
3. VMPX 3K3 8 SIL VMPX 0 LRO aig ed 126 KZ VMPX 0 LAI R85 22K 4 4 R84 ait R55 19 dk 1 2 EN d 5 GND 26 LAMP ROWS SOURCE 3 6 EE R82 KA VMPX o 1 CLK 12V 13 OE 12V OE Q4 zu de BC846 ok Q21 B as 14 R80 3K3 Q12 R56 TP128 LRO d s 06 13 R79 3K3 GND LRi 2 LA 16 12 R78 KZ LR3 LR2 ER e 12V VMPX ZE r 22K lt 3K3 R57 TRA 5 5 as 9 GND oe TRS SE ende 9816 KZ LR4 TRE Te BC846 22K 8219 4094 014 R58 TRS EEK TIP126 TRI 10 19 Fo 13 B 12V lt T Pe Em VMPX o LR5 MZ 024 L5 LRIZ 13 GND ae ES 26 LRI3 12V KZ VMPXIG 186 1814 15 BC846 22K Q25 1815 16 5 016 s 26 gt is GND HDR 16W AMP MTA 100 100n KZ VMPX 0 LR BC846 2 026 a5 917 TiP126 BC846 22K ax VMPX BC846 PP20 PP21 22 3K3 8 SIL lt VMPX 0 LRB Q27 m 26 22k Ma JUE Q28 1 4 a SS fer TIP126 13 MPX1 C 12V 310 02 rs 3K3 o LR10 CLK Q3 15 7 3K3 BC846 22K EE Lid EES Q4 R48 ae 95 R87 3K3 GND oo 06 12 3K3 R86 KZ VMPX 0 11 EE Sed 22K EE 95 GO TIP126 8 ig ii GNDI LR12 GND 05
4. HEBER LTD 1996 2002 12V0 Di R33 METER DETECTION UF4002 47R Imm I POWER FAIL DETECTION EE LC1 VEO d ds EMCFILTER o T Ro H i R37 R38 R39 R40 R40 revision 1 PP 12V 2 ATK 2 47K 2 AKT 2 lt 6 3k3 gt 4k7 Jul 2003 lt LM339 22K U16A 5 4 der d 2 METER SENSE er METER SENSE 2 i R36 E PPO GND 4 4 o LM339 PP10 47K 2 PP TPS 7 PAD GND 5 TP6 vec 0 9 021 TUM 7 PAD 2 59 10 PORTA O 7 SFX CK SFX 3 U16C 11 14148 5 TPB 12V_INo o 18 fe gt 1253 R127 11 LM339 22K Threshold 2 Lamp short cct MPX CURRENT 1 SENSE 05 em Threshold 1 Lamp present 47 47 R126 120R GND GND REF2 MPX_REF2 11 VMOT 12V LC2 u15 Fi EMCFILTER M7805 P3 12V_INO Sk A 1 3 vo VCC 12vo H GND o 3 15A F 20 5MM 3 5 Xi POWER MPX_GND 5 VMPX 0 6 D20 5 D2 D3 HDR6W AMP MTA 156 SA15 TI 150 1 50 SA5 SA15 GND GND GND MPX_GND GND REGULATED 5V MSS HEBERLTD Belvedere Mil Chalford Stroud GL6 Tel 44 0 1453 886000 Fax 44 0 1453 885013 itle 5 POWER SUPPLY Size Docume
5. veer M YE 1 DES GE RTSA Mi CTSB d RTSA RAM CS HEE Haga RAM Cs B ER rr STR 12V LC 0 15 LC 0 15 EE Mi EE RESET Bi xp i ZO 15741 11 o 1 HM e Mus SHT 12 LAMP ROW SOURCES ESO d 12V MPX1 B 12V L MPX1_B_12V 285 PORTA STR 12V MPX1 C 12V MPX1 C 12V PB6 PORTA 0 7 OE 12V MPX1 D 12V 4 MPX1 D 12V PORTA PORTAIO MPX1 A 12V LR 0 15 LR 0 15 15741 12 15741 9 5 0 2 15741 10 5 Ds FC3 TGATE1 TGATE2 HEBERL 157412 lelvedere Mil halford Stroud lb ucester shire GL6 8NT 0453 886000 Fax 0453 885013 ille PLUTO 5C ROOT SHEET Document Number 56 15741 712 HEBER LTD 1996 2002 Date Tuesday August 12 2003 Bheet Document 80 15744 Issue 5 HEBER LTD 45 Figure 2 Schematic Sheet 2 CPU BACKGROUND DEBUG PP TCK CONNECTOR N8 E MS is Ges Toa
6. 5 are provided for the Opto Inputs When driving stepper motor reels because the maximum static current load of each winding is 400mA assuming 300 12 windings it is important to connect the motors to distribute the load evenly amongst the TPIC6259 driver chips The recommended method of connection is to wire the reel motors as follows Table 18 Recommended Reel Stepper Motor Drive Connections REEL 1 3 REEL 2 OP4 7 REEL 3 OP8 11 REEL 4 OP12 15 REEL 5 OP16 19 REEL 6 OP20 23 This guarantees that a maximum of 3 motor windings are driven simultaneously by any one TPIC6259 device which is within the ratings of the device even under the worst case of a reel being stationary and unchopped Of course when the motor is running or is being chopped the average current drops significantly Extra reels could be connected via pins on the other connectors Providing the software chops the current to the reels when they are not spinning an extra 2 reels can be wired to OP24 27 and OP28 31 and should allow the TPIC6259s to remain within their ratings NB The 12V outputs on P7 Pins 45 50 are fed directly from the 12V Input to the Pluto 5 Board on P3 Pin 4 It does not go via Fuse F1 on the board 7 2 Reading the DIL Switches The state of the DIL Switches may be read at any time by reading the memory locations as described in Section 7 3 Reading the Switch Inputs The 32 switch inputs may be read at any time by
7. 1 Open Drain Output 24 OP24 1 1 25 Open Drain Output 25 Open Drain Output 26 26 OP27 Open Drain Output 27 Open Drain Output 28 OP28 OP29 Open Drain Output 29 Open Drain Output 30 OP30 OP31 Open Drain Output 31 Open Drain Output 32 OP32 OP33 Open Drain Output 33 Open Drain Output 34 OP34 OP35 Open Drain Output 35 Open Drain Output 36 OP36 OP37 Open Drain Output 37 Open Drain Output 38 OP38 OP39 Open Drain Output 39 Open Drain Output 40 OP40 OP41 Open Drain Output 41 Open Drain Output 42 OP42 OP43 Open Drain Output 43 Open Drain Output 44 OP44 OP45 Open Drain Output 45 Open Drain Output 46 OP46 OP47 Open Drain Output 47 GND GND Input 20 IP20 IP21 Input 21 Input 22 22 23 Input 23 Input 24 24 25 Input 25 Input 26 26 IP27 Input 27 Input 28 28 29 Input 29 Input 30 IP30 IP31 Input 31 12V 12V Document 80 15744 Issue 5 HEBER LTD 37 9 12 P8 Box Header General I O 1 Reference P8 Header 40W Tyco Box Header Type Description Document No 80 15744 Open Drain Output 24 Open Drain Output 26 Open Drain Output 28 Open Drain Output 30 Open Drain Output 32 Open Drain Output 34 Open Drain Output 36 Open Drain Output 38 Open Drain Output 40 Open Drain Output 42 Open Drain Output 44 Open Drain Output 46 Input 20 Input 22 Input 24 Input 26 Input 28 Input 30 Issue 5 General Purpose 1 24 1 2 25 26 4 OP27 28
8. 12 Note that this scrambling of address lines is applicable ONLY to sockets U1 U2 on the Pluto 5 Casino Controller Board Any EPROM sockets on Memory Expansion Cards are connected 1 1 to the address bus and do NOT require any special processing 6 7 EPROM Address Line Scrambling in 16 Bit Mode 6 7 1 2 27C040 EPROMs In 16 bit mode running with 2 27C040 EPROMs the scrambling of the address lines cause the following effect on the memory mapping the EPROMs Note that this table applies to the re mapping that occurs to the EPROM contents rather than the actual address lines Table 6 Re Mapping of Address Lines in 2 27C040 Mode 68340 Address Bus EPROM Address Not Used in 16 Bit Mode A2 A19 1 18 A2 A19 Thus for example addresses will be translated as follows so the contents of the EPROM must be re arranged to compensate Table 7 Re Mapping of EPROM Contents in 2 27C040 Mode 68340 Access Address Will Read From This Location in EPROM 0000 0000 0000 0000 ed 000 FFFS 0008 0000 0000 0002 0008 0002 0000 0006 Document 80 15744 Issue 5 HEBER LTD 13 6 7 2 2 27 801 EPROMs In 16 bit mode running with 2 27C801 EPROMs the scrambling of the address lines cause the following effect on the memory mapping in the EPROMs Note that this table applies to the re mapping that occurs to the EPROM contents rather than the actual address lines Table 8 Re Mapping of Addre
9. CTS Channel DATAPORT P2 RS232 level 6 4 5 Timer Module The Timer Module provides 2 General Purpose Timers The Pluto 5 Board uses these to provide a variable duty cycle signals on TOUT1 and 2 that is used to control the volume setting on each channel of the TDA7057AQ Stereo Audio Amplifier Timer 1 TOUT1 controls the volume of Sound Channel 1 Timer 2 TOUT2 controls the volume of Sound Channel 2 if it is fitted If Sound Channel 2 is not fitted then Timer 2 may be used for other purposes See Section Making Sounds for detailed information on the operation of the Volume Controls Pins TGATE1 and TGATE2 are allocated as general purpose inputs which are used to read the SCL and SDA lines on the External Connector P13 Pins controlled by the Timer Module are allocated as follows Table 4 Allocation of MC68340 Pins Controlled by Timer Module NO FUNCTION TGATE1 79 Read External line SCL on P13 Pin inverted TIN1 81 Not Used Strapped To Vcc 80 Variable Duty Cycle Volume Control SFX Channel 4 _ _ TGATE2 36 Read External Line SDA on P13 Pin 2 inverted TIN2 34 NotUsed StrappedToVec 2 35 O Variable Duty Cycle Volume Control SFX 2 1 Document 80 15744 Issue 5 HEBER LTD 11 6 5 The Pluto 5 Casino Controller is fitted with 84 lea
10. ipo Strapped to Table 15 Mapping of DUART U53 I O Pins Pin Channel Comments RS232 Level to P18 17 RTSE RS232 Level to P18 12 RTSF RS232 Level to P18 18 2 Noconnectin connection No connection No connection No connection No connection RS232 Level to P18 14 RS232 Level to P18 20 Strapped to VCC IP3 Strapped to VCC P4 StapedtoVCC O fips Document 80 15744 Issue 5 HEBER LTD 22 Table 16 Mapping of DUART U54 I O Pins Pin Channel Comments RS232 Level to P18 23 TTLLeveltoP19 3_ RXDB H _RXDH__ TTLLeveltoP19 5 6c RS232Leve oPi amp 24 H TTL Levelto P197 H 2 PIT H P3 TT Levelto P1913 gerrea _ _ l Noconnection l a connection H E TTL Level to 19 17 Strapped to pips Strapped to Table 17 Mapping of DUART U55 I O Pins 6 21 2 DUART Interrupts The interrupt outputs from the 3 DUARTs are connected in parallel wire ored and taken to IRQ5 5 the 68340 processor Note that IRQ5 must be run in Autovector mode and software must poll the
11. Slave Address of the RTC is as follows Table 13 Slave Addresses for RTC U40 READ OxA1 WRITE 6 20 2 U37 position is fitted with a socket that accepts an Industry Standard 24 04 512 bytes or 24 08 1024 bytes with pin 7 which serves a different function on devices from different manufacturers connected to GND The Pluto 5 Casino Controller Boards as standard do not have an E PROM fitted but they are available as an optional extra or may be fitted by the user Document 80 15744 Issue 5 HEBER LTD 20 We strongly recommend that if a user supplies or fits his own devices that only 24 04 or NM24C08 devices should be used manufactured by Fairchild or National Semiconductor Heber cannot offer Technical Support for the use of devices from alternate manufacturers To avoid a clash of addressing between the PCF8583 RTC and the 24Cnn E PROM A2 Pin 3 of the is strapped to Vcc and A0 A1 to GND and this socket is restricted to accepting devices no larger than the 24C08 Note however that there is no such size restriction on the devices that may be connected via P13 the External Bus Connector The Slave Address of each of the 256 byte Page Blocks in U37 is as follows Table 14 Slave Addresses for E7PROM 037 24 04 24 08 24 04 24 08 24 08 only 24 08 only 6 21 Serial Channels C H T
12. dup AS 2 2 Pe IFETCH 9 RESET RW 3 3 FREEZE 7 BRE BERR 4 4 IEEE 1149 1 ACCESS VCC BKPT ol 3 GND BKPT 5 5 BERR b Ds 6 6 1 7 7 LOW PROFLE HOR 10W 8 8 vec vec Us FITTED FOR DEV ONLY 9 9 3K3 8 SIL 3K3 8 SIL R102 R103 Se 888855599888888 6288 ENES 680R 680R 70 FCO gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt EEK Sire Do Da D1 602 D2 u 0 2 D3 00 15 3 46 79 15 18 5 103 na DS 104 AS 9 DS 107 08 3 9 15 18 RW RW D7 23 3 4 6 9 15 18 520 105 39 920 E 105 5 0 08 9 921 521 09 D10 3 915 DSACKO HH br D11 3 9 DSACKI DSACKI 012 013 BERR 99 9 BERR HALT BERR Bie RESET LED 9 HALT RESET 97 HALT_ D15 10 RESET RESET a BR 100 PAD BG 101 BR GO BGACK 102 108 BGACK A SOFTWARE E RMC 22 CONTROLLED 10 57 MODCK PBO A4 Ge 52 3 AS 74HC14 3 52 SHEE 3 7 CS21RQ2 PB2 A6 8 METER SENSE H IRCB PB3 AT 9 Gea SO 2 CSSIROAIPBA a E ON BOAR 8 NM E 10 eite 11 o o ea MI A12 tere Ga SW PUSHBUTTON 1 PN 2 14 9 9 10 33 RXDA 15 2 9 10 TXDA TTSA 28 16 AZ 4 9 10 CTSA ae 291 CISA 17 PETRI 5 8 9 10
13. 13 18 o 12v SEG1 NAT os veco vec H 337 ee SEG2 4504 NA 053 BC337 150R U35 R65 aH Send 12 MPX1 B 12V 310 NAT mA 1 75 7 BC337 Es OE a 74 SEG4 13 NA 12V 16 EHI ass 150R 8 Q7 H BOSE R67 m SEGS 8 os Ha M GND GND 05 86337 DR 4094 SEG6 NA 057 12 MPX1_C 12v 1 BC337 QR 12V SEG7 d 1508 E BC337 100 GND R70 12V0 SEGB NA oso pom 150R 312V R71 SEG9 NA 060 BC337 150R R72 SEG10 GND NA BC337 150R R73 1 4 SEG11 STR 01 12 MPX1 12V 2 D Q2 5 NA 1508 15 CLK Q3 7 BC337 R74 oE c 14 SEG12 13 NA Q6 Q63 95 12 BC337 H uid SEG13 9 Qs Q64 GND 8 GND 051 905 BC337 TOR 4094 SEG14 NA oes BC337 150R R77 SEG15 NA 066 BC337 1508 SECO 12 SEG 0 45 11 U31A MPX1_A_12V 1 2 NET U31B GND LC6 4069 N GND 3 4 1 num U31C 4069 STR A 12V 5 1 mum Pu 1 1310 GND Les 2135 4069 E EEEa CLK 12V 9 8 4123 b 5 2 U31E GND Lea 2 MULTIPLEX EXPANSION 4069 E Ti STR 12V 11 10 La 3 T HDR7W 0 1 KK GND 4069 E OE 12V 13 12 Lg sd FEBERLTD lelvedere Mil 4069 EZE halford Stroud GL6 8NT Tel 44 0 1453 886000 Fax 44 0 1453 885013 itle Mead PLUTO 5C LED DRIVES Size Document Number 56 15741 72 HEBER LTD 1996 2002 Date August 12 2003 Bheet 13 of 18 HEBER LTD
14. 58 06 18 4 OP62 Eri 5 RIE OP54 S l as 91 cS 42 SELO AA 46 815 7 815 7 GE SEL2 2 gu OP26 EZE 12 51 GORO OP18 94 15 22 13 Q6 16 OP10 13 G Q6 16 OP14 199 CLR 17 199 CLR Q7 veco 2 pen HL GND veco 21 vcc Hy SND PGND GND PGND GND PGND d GND E PGND H GND enD H PGND GND GND PGND GND 6259 06259 025 29 03 18 4 59 07 18 4 OP63 0 51 B 29 Es 0755 eda GE SELO 6 50 92 7 OP35 S0 92 7 SEL2 1277 84 27 5802 12 51 03 14 2 Q4 15 19 2 94 15 23 GP 1 134 95 16 134 95 16 5 19 17 192 17 10 RESET 4 CLR Q7 vcco 2 voc H GND veco 2 vec GND PGND GND PGND GND peno H Peno H GND GND PGND GND GND GND GND TPIC6259 TPIC6259 2 34 79 15 18 00 15 lt lt gt EEE brea 7 A4 GP HEBERLTDO CSM GND L cs m 9 lelvedere cs op halford Stroud GL6 8NT gt 44 0 1453 886000 ille PLUTO 5C OUTPUTS Document Number 56 15741 Date Tuesday August 12 2003 Sheet 3 of Document No 80 15744 Issue 5 HEBER LTD Figure 7 Schematic Sheet 7 Inputs Page 50 2 3
15. 80 15744 Issue 5 HEBER LTD 5 6 CIRCUIT OPERATION This section describes how some elements of the circuit operate and their capabilities and limitations A subsequent section deals with how the various capabilities of the board are used to implement specific amusement machine functions 6 1 Power Supplies The Power Input to the board is on P3 There are 3 input voltages required 12V 12V and 36V or 48V for the lamp multiplex The 12V supply is fused by F1 3 15A as it comes on the board From the unfused input side the 12V is distributed to the Reel Connector P7 where it may be used to provide the supply for the Stepper Motors From the fused side the 12V is used for the following e Regulated via U15 to provide the Vcc 5V supply for the board This will draw up to 250mA from the 12V e provide the Power Supply for the Stereo Audio Amplifier 032 The load current drawn by this will depend on the audio volume etc but is not likely to exceed an average of about 200mA Monitored by U16B to detect imminent failure of the 5V supply and cause a Level 7 Non Maskable Interrupt NMI The interrupt will occur if the 12V supply drops below approximately 7 8V e To provide the Power Supply for the multiplexed LED drive circuits With 32 LED digits fitted and all having all segments illuminated the current drain is likely to be between 400mA and 550mA Distributed to various connectors P1
16. 9 vec 1488 12Vo 12V mp 52 0 OHV ere GND DO CTSD o 9 exe EO GND prse gt CTSE 15 Roc C H im GND GND prop 15 eer lt d p E RXDD 8 10 RXD RXG RTSG 15 RxD lt RXC ETZE TXG CTSG CTSD 11 13 TXD i PORTD 15 RxD CTSD i HDR26W a 2 o 1489 GND 12V 12 m SO 5 gt RTSE 1 gt RISG H 15 pre gt 21 Ea 1208 Zua p3 rome H 2 RTSG 4 gt ABBE isi 5 15 gt de VCCo 9 B vcco 51 g2 6 15 TXDF TXDE 94 19 2 121 penin 15 RTSF RISE Gun GND Zip VCCo p2 VCCo Ean p2 0 a a 2 9 o vec 1488 vec 1488 RXF GND RISE GND 8 CISF 8 gt gt 15 pure lt HE A Ra H 15 Ros lt _ 2208 Ra H 15 lt __ SSE 15 lt SSG rxe rd 15 Ro lt E rxc H2 15 lt _ 9 H2 15 lt 13 15 pere lt __ PSR _____ p 13 DSRC Q 9 9 1489 1489 GND GND EBERLTD vec vec vec 12V lelvedere Mil 9 9 halford Stroud bucester shire GL6 8NT C54 C55 C56 58 Tel 01453 886000 Fax 01453 885013 oon 100n 100n 100n 100n itle G
17. Figure 14 Schematic Sheet 14 Root Sheet 2 Page 57 15 DUARTS 234619 00 15 lt gt 010 15 23 2 23 23 3 CS DUART CS DUART 2 RW 10 RESET 29 pe lt _ gt 85 3 3 68MHZ 3 68MHZ 2 39 DSACKO BEN 5 SHT 16 5232 BUFFERS TXDC TXDD TXDE TXDF TXDG RXDC RXDD RXDE RXDF RXDG RTSD RTSE RTSF RTSG CTSC CTSD CTSE CTSF RTSC CTSG DSRC 15741 15 HEBER LTD 1996 2002 CDC 15741 16 5 17 RS485 EXPANSION RXDH CTSH EXP OP2 EXP EXP 2 EXP E EXP EXP EXP 1 2 EXP 15741 17 3 co RAM_LITH BEE SHT 18 PICIRAM ty 00 15 O RW RAM LITH AME Be y RESET ESE Po PIC P1 PIC OPI Boy 15741 18 HEBERLTD halford Stroud loucestershire GL6 8 0453 886000 Fax 0453 885013 GEO Mil Title PLUTO 5C ROOT 2 Size Document Number 56 15741 7 2 Date Tuesday August 12 2003 Bheet Document 80 15744 Issue 5 HEBER LTD 58 Figure 15 Schematic Sheet 15 DUARTS Channels
18. 80 15744 Issue 5 HEBER LTD 3 5 8 Sheet 8 This sheet shows various Power Supply related functions Current sensing 12V Meter supply Power fail detection Current sensing from Lamp Multiplex Fuse and 5V regulator Voltage rail overvoltage and transient protection P3 PWR IN power input connector 5 9 Sheet 9 This sheet shows the following I O connectors e 7 REELS carries enough I O lines to run 6 reels including a sub set of the lamp multiplexer and power supplies for the motors 8 1 and P9 I O 2 are general purpose I O e P11 MULTIPLEX EXPANSION provides signals for the connection of Multiplex Expansion boards P12 AUX OUTPUTS provides 6 open drain TTL outputs typically for driving VFD displays e P13 provides a connector for external expansion e g E PROM modules Note that the lines used to implement this connector are different to the lines allocated for the internal bus to 040 and 037 14 EXPANSION is a position for a daughter board for I O expansion 5 10 Sheet 10 This sheet shows the following circuits and connectors Reset circuit and LED Battery Backup for RAM and optional Real Time Clock Optional Real Time Clock socket 040 PCF8583 Optional E PROM socket 037 24C04 512 bytes or 24 08 1024 bytes RS232 buffers P1 5232 is a general purpose RS232 serial communication port P2 DATAPORT
19. P4 18W MTA 100 1 640456 8 1 640621 8 1 640620 8 P6 LISA MTA 100 1640456 1 640621 6 1 6406206 P11 ZW 100 6404567 6406217 640607 Table 22 MTA 156 Connector Part Numbers AMP Part No iz i Colour Yeow Colour Natural Colour Yellow 6W MTA 156 640388 6 640429 6 640427 6 The above MTA 100 and MTA 156 IDC Connector Part Numbers are for illustration and are of the Feed Through Receptacle without Polarising Tabs type A number of alternatives exist that could also be used for example Closed End types Please consult the relevant AMP information for an exhaustive list If you have Internet Access the information is also available on the AMP Web Site at tto www amp com Strain relief covers are also available 9 2 P1 RS232 Channel Reference P1 Type Header 6W AMP MTA 100 Description RS232 Channel A Input to Pluto 5 Output from Pluto 5 Input to Pluto 5 Output from Pluto 5 Document 80 15744 Issue 5 HEBER LTD 30 9 3 P2 Dataport RS232 Channel B Reference P2 Type 25W D Socket Description BACTA Dataport RS232 Channel B 71 RXB Input to Pluto 5 2 nc TXB Output from Pluto 5 CTSB Input to 5 4 RTSB O f Pluto 5 kK utput from Pluto GA D nw GND qu 19 Inc GND 7 nc nc nc EE nc nc nc 12V 11 24 nc ep Document 80 15744 Issue 5 H
20. Reference P6 Type Header 16W AMP MTA 100 Description Lamp Rows Sources Document No 80 15744 Issue 5 LRO LR1 LR2 LR3 LR4 LR5 LR6 LR7 LR8 LR9 LR10 LR11 LR12 LR13 LR14 LR15 Lamp Row Source 0 Lamp Row Source 1 Lamp Row Source 2 Lamp Row Source 3 Lamp Row Source 4 Lamp Row Source 5 Lamp Row Source 6 Lamp Row Source 7 Lamp Row Source 8 Lamp Row Source 9 Lamp Row Source 10 Lamp Row Source 11 Lamp Row Source 12 Lamp Row Source 13 Lamp Row Source 14 Lamp Row Source 15 HEBER LTD 34 99 Reels Reference P7 Type Header 50W AMP Ultrex Description Reels Connector for 6 Stepper Motor Reel Mechanisms Lamp Column 0 LCO LC1 Lamp Column 1 Lamp Column 2 LC2 LC3 Lamp Column 3 Lamp Column 4 LC4 LC5 Lamp Column 5 Lamp Row 0 LRO LR1 Lamp Row 1 Lamp Row 2 LR2 LR3 Lamp Row 3 Lamp Row 4 LR4 LR5 Lamp Row 5 GND VCC Open Drain Output 0 OPO OP1 Open Drain Output 1 Open Drain Output 2 OP2 OP3 Open Drain Output 3 Open Drain Output 4 OP5 Open Drain Output 5 Open Drain Output 6 OP6 OP7 Open Drain Output 7 Open Drain Output 8 OP8 OP9 Open Drain Output 9 Open Drain Output 10 OP10 Open Drain Output 12 OP12 Open Drain Output 14 OP14 Open Drain Output 16 OP16 Open Drain Output 18 OP18 Open Drain Output 20 OP20 Open Drain Output 22 OP22 OP11 Open Drain Output 11 OP13 Open Drain Output 13 OP15 Open Drain Output 15 OP17 Open Drain Output 17 OP19 Open Drain Output 19 OP21 Open Drain Output
21. is the BACTA standard Dataport 5 11 Sheets 11 12 amp 13 These sheets show the Multiplex Lamp and LED drive circuits and connectors Sheet 11 shows the Lamp Columns Digits Sink drivers Sheet 12 shows the Lamp Row Source drivers Sheet 13 shows the LED Segment drivers P4 LAMP SINKS is the Lamp Array Column Sink outputs P5 LED is the connector for the 32 or 16 LED digits LAMP SRC is the Lamp Array Row Source outputs 5 12 Sheets 14 Sheets 1 13 are identical to the standard Pluto 5 Board This sheet is a secondary Root Sheet showing the extra 4 schematics Sheets 15 18 that have been added to make the Pluto 5 Casino Document 80 15744 Issue 5 HEBER LTD 4 5 13 Sheets 15 This sheet shows the three 68681 DUARTs U53 U55 that provide serial comms channels C H 5 14 Sheets 16 This sheet shows the following e Buffers for the 5 RS232 channels C G e Connector P17 for RS232 Channel C e Connector P18 for RS232 Channels D E F amp G 5 15 Sheets 17 This sheet shows the Channel H Interface This is at TTL levels and may connect directly via P19 to a variety of different format Interface Cards eg RS422 RS485 Opto Isolated RS485 5 16 Sheets 18 This sheet shows the following Optional security PIC Microcontroller U51 Security switch connector P20 Second non volatile battery backed 32Kbyte RAM U50 Second battery and back up circuit for U51 and U50 Document
22. August 12 2003 Sheet 17 of 18 Document No 80 15744 Issue 5 HEBER LTD 61 Figure 18 Schematic Sheet 18 Secondary NV RAM Security PIC Microcontroller GND GND C65 037 P20 15 1 N21 21 10K 8 SL 1N4148 372 1 D SE eie tarea u51 1 4148 TIE D 8 8 6 HDR 8 MTA 100 be 1 1N4148 9 PIC_PO E L 9 PETE H 1 deak 683 E 3 Bes 11 1N4148 9 RB5 17 d RBG 4 nar EZ 4 MEN as PIC16LV54P 4 1N4148 4 1N4148 066 R148 100n 120R 12V0 gt gt R142 22K 2 3 4 6 7 9 15 00 15 vec 2 PP27 4 PAD VBAT2 TP17 PAD R144 390R UB C62 100n TP18 47 16 PAD R146 Ei 62256 GND RAM LITH z RAM um gt BATTERY BACK UP 120R GND 10 C gt RESET GND lelvedere Mil halford Stroud lbucester shire GL6 8NT Tel 01453 886000 Fax 01453 885013 itle PLUTO 5C PE RAM Size Document Number 7 56 15741 712 HEBER LTD 1996 2002 Dat
23. Clock Data and Reset Connector P12 has 6 TTL level outputs which could drive up to 2 display modules The mapping of these outputs as the LSB of 6 bytes makes it convenient for the software to implement the bitwise drive required 7 7 Using the External IC Bus Connector P13 is intended for driving external boards containing Bus components A common use for this could be the provision of a removable E7PROM Module for use in Spain any other country with a similar requirement Heber have available a small PCB containing a NM24C04 or 24 08 E PROM that plugs directly on to P13 On this connector the SDA line is driven by the Open Drain Output AUX7 and may be read by the 68340 Timer Module as the inverted TGATE2 signal Similarly the SCL line is driven by AUX6 and read by TGATE1 Note On the Pluto 5 Casino Controller these 2 lines are also connected to the internal Security PIC Microcontroller which acts as slave device Care must be taken to avoid possible conflicts between the PIC and any external device connected on this bus 7 8 Driving Meters Electromechanical Meters or Counters should be 12V DC parts The common 12V supply to them should be the Vmeter supply from Connector P9 I O 2 pin B17 and each should be driven by Open Drain Output 63 As the meter is pulsed ON the software should check that the Vmeter Current Sense Input has operated i e that pin 4 h
24. DUARTS to establish the source of the interrupt Note also that if a Video Card is added on 14 amp P15 that IRQ5 may also be used as a Video Interrupt and the software must poll accordingly 6 22 Secondary RAM U50 is a 32Kx8 RAM completely independent of the main RAMs U3 and UA It is battery backed either by the Primary Backup Battery see Section if JP5 is fitted or by the Secondary Backup Battery BT2 if fitted The RAM is mapped as a Byte Wide Port at an address determined by the FPGA 6 23 Security PIC Microcontroller U51 is a socket for an optional PIC16C54 microcontroller It is powered by a battery backed supply and therefore continues to run when the controller is powered down The oscillator crystal is 32 768KHz to reduce power consumption Details of operation will be found in the Heber User Manual of the device fitted Document 80 15744 Issue 5 HEBER LTD 23 7 This section discusses how various standard amusement machine functions can be implemented 7 1 Driving Reels Up to six 12V Stepper Motor Reel Mechanisms may be connected to the REEL connector P7 12V outputs are available for the motor common connection and GND Vcc are available for the Opto supply A 6 6 subset of the Lamp Multiplex is configured so up to 6 lamps per reel may be accommodated in either sinking or sourcing mode depending on the wiring of the Reel Mechanism inputs
25. OP29 OP30 7 8 OP31 OP32 OP33 OP34 OP35 OP36 OP37 OP38 OP39 OP40 OP41 OP42 OP43 OP44 OP45 OP46 23 24 OP47 GND 21 IP23 IP25 IP27 IP29 IP31 12V Open Drain Output 25 Open Drain Output 27 Open Drain Output 29 Open Drain Output 31 Open Drain Output 33 Open Drain Output 35 Open Drain Output 37 Open Drain Output 39 Open Drain Output 41 Open Drain Output 43 Open Drain Output 45 Open Drain Output 47 Input 21 Input 23 Input 25 Input 27 Input 29 Input 31 HEBER LTD 38 9 13 P9 Ultrex General I O 2 Reference 9 Header 34W AMP Ultrex Description General Purpose 2 Open drain Output 48 OP48 Open drain Output 50 OP50 Open drain Output 52 OP52 Open drain Output 54 OP54 Open drain Output 56 OP56 Open drain Output 58 OP58 Open drain Output 60 OP60 Open drain Output 62 OP62 OP49 Open drain Output 49 OP51 Open drain Output 51 OP53 Open drain Output 53 OP55 Open drain Output 55 OP57 Open drain Output 57 OP59 Open drain Output 59 OP61 Open drain Output 61 OP63 Open drain Output 63 GND GND Input 6 IP6 IP7 Input 7 Input 8 IP8 IP9 Input 9 Input 10 IP10 IP11 Input 11 Input 12 IP12 IP13 Input 13 Input 14 IP 14 IP 15 Input 15 Input 16 IP16 A IP17 Input 17 Input 18 IP18 A IP19 Input 19 12V A17 17 Vmeter Current Sensing 12V 9 14 P9 Box Header General I O 2 Reference 9 Header 34W Box Header Description General Purpose I O 2 Open drain
26. 14 RTSH D3 RTSH 17 012 26 03 OF a EXP 2 deok 013 2010 22 EXP DES IM 014 25 05 30 b 015 21 06 16 07 A0 2 U52A 4 M A4 2 4 CS DUARTO A2 6 5 3 5 CS DUART A3 ebe erc de 6 CS DUART2 At 2 EE CS_DUART ee 19 fio EXP IPS RW 74HCT139 pe 142 o vec EEEa RESET DSACKO 10 SA 1o brack PES 242 68692 1 C68 FEBERLTD 100n 100n 100n 100n 100n lelvedere GND GND GND GND GND halford Stroud lbucestershire GL6 8NT Tel 01453 886000 Fax 01453 885013 itle PLUTO 5C DUARTS Size Document Number s A3 56 15741 7r2 HEBER LTD 1996 2002 Date Tuesday August 12 2003 Sheet 15 18 Document 80 15744 Issue 5 HEBER LTD Figure 16 Schematic Sheet 16 5232 Buffers Channels C H Page 59 42V 2 U41 i gt 15 TXDC TE Zua TXA 15 per gt AISE 2 9 15 p 1081 erk OW D PLUG 15 RTSD RISO dun 02 4
27. 16 1Mbyte 27 801 1024k 8 1Mbyte 27C801 27C801 16 bit 1024k 16 2Mbyte It is not necessary to change any links on the board in order to switch between different memory configurations All relevant switching is carried out within the FPGA which contains an Autoselect feature After Power up during the reset period the FPGA reads the top byte address of U1 Data contained in this byte defines the memory configuration required and the FPGA sets up the control lines to the EPROM sockets accordingly so that at the end of reset the processor is able to read the EPROM s correctly Thus after the final linked EPROM software module has been created prior to being blown into EPROM the top location of the memory must be overwritten with suitable data to signify the EPROM configuration that will be used This is the feature referred to as EPROM Autoselect A full operational description of this feature is given in the User manual for the FPGA in use on the Pluto 5 Casino Controller Board As with the Pluto 1 System in order to facilitate the option to use either 1 or 2 EPROMS i e run in 8 bit or 16 bit mode it is necessary to have some scrambling of the address lines to the EPROMs when operating in 16 bit mode Therefore prior to blowing 16 bit 5 the data must be re arranged to compensate A software utility is provided with the Pluto 5 Development Kit to carry this out Document 80 15744 Issue 5 HEBER LTD
28. 21 OP23 Open Drain Output 23 Input 0 IPO IP1 Input 1 Input 2 IP2 IP3 Input 3 Input 4 4 IP5 Input 5 12V 12V 12V 12V 12V 12V Document 80 15744 Issue 5 HEBER LTD 35 9 10 P7 Box Header Reels Reference P7 Type Header 50W Tyco Box Header Description Reels Connector for 6 Stepper Motor Reel Mechanisms Lamp Column 0 LCO LC1 Lamp Column 1 Lamp Column 2 LC2 LC3 Lamp Column 3 Lamp Column 4 LC4 LC5 Lamp Column 5 Lamp Row 0 LRO LR1 Lamp Row 1 Lamp Row 2 LR2 LR3 Lamp Row 3 Lamp Row 4 LR4 LR5 Lamp Row 5 GND VCC Open Drain Output 0 OPO OP1 Open Drain Output 1 Open Drain Output 2 OP2 OP3 Open Drain Output 3 Open Drain Output 4 OP5 Open Drain Output 5 Open Drain Output 6 OP6 OP7 Open Drain Output 7 Open Drain Output 8 OP8 OP9 Open Drain Output 9 Open Drain Output 10 OP10 Open Drain Output 12 OP12 Open Drain Output 14 OP14 Open Drain Output 16 OP16 Open Drain Output 18 OP18 Open Drain Output 20 OP20 Open Drain Output 22 OP22 OP 11 Open Drain Output 11 OP13 Open Drain Output 13 OP15 Open Drain Output 15 OP17 Open Drain Output 17 OP19 Open Drain Output 19 OP21 Open Drain Output 21 OP23 Open Drain Output 23 Input 0 IPO 1 Input 1 Input 2 2 Input 3 Input 4 4 IP5 Input 5 12V 12V 12V 12V 12V 12V Document 80 15744 Issue 5 HEBER LTD 36 9 11 8 Ultrex General I O 1 Reference P8 Type Header 40W AMP Ultrex Description General Purpose
29. 4 6 9 15 18 00 15 lt gt BEURKO ele 7 6 R2 24 R3 6 191 2 R4 E 103 3 2 os R6 47K 2 01 9 10 R6 ATK 2 25 X RZ gien 47K 2 RB E u14 swt 202 13 47K 2 ay D 1 A7K 2 jer 5 2 14 SELO 47K 2 162 4 4 3 1 4 12 rs d 41 23 1G E z 18 NM D9 aye epi EN I ea 3K3 8 SIL 2 1 11 4 d 10 74 253 PG 1 SO cL U10 R9 L vcc 2 ed dire me 6 Eis EZ aw DIL SW 1 1 5 R11 1 2 ATK 2 R12 ATK 2 am RIS ATK 2 GND D3 9 10 R14 47K 2 w e 1 Ris EZ 74 253 201 12 47K 2 EO 263 13 2 vec T 47K 2 lt GEO SELO
30. 47K 2 T E SE pal ii si 100n 1 10 Pig 2 GND 22 3K3 8 SIL eje ee 253 swe U11 R17 TL VCC D10 1Y 6 mt 1 16 D4 6 R18 ESO 5 2 15 1 100 1 1 5 RIS EO 4 h 3 14 ma T 2 1 2 MES 102 r Ee E 1C3 2 R21 47K 2 D11 10 4 6 11 05 9 10 R22 ATK 2 1P29 w 1 T 10 R23 121 261 12 1 8 9 pes ATK 2 R32 3 202 AAEE 47K 2 1 5 8WDILSW 27 2 sao GEO SELO 47K 2 2 Sent 16 pt ah 1 15 1G 26 p N3 2G 3K3 8 SIL 74 253 253 012 R24 D6 7 6 R25 9 VOS E R26 1 22 47K 2 RZ E 12 63 47K 2 1 6 R28 47K 2 m D7 9 10 R29 47K 2 1 EE EE R30 1223 pele 47K 29 R3t m P15 vec 47K 2 47 2 14 SELO 47K 2 de 16 Pig 1 15 N4 ab 26 3K3 8 SIL 253 L o CSIP 2 6 980 2 NOTE SELO 2 ARE INVERTED 1 3 FEBERLTD lelvedere Mil halford Stroud GL6 8NT 44 0 1453 886000 Fax 44 0 1453 885013 itle PLUTO 5C INPUTS Document Number 7 56 15741 HEBER LTD 1996 2002 Date Tuesday August 12 2003 Bheet 7 of 18 Document 80 15744 Issue 5 HEBER LTD 51 Figure 8 Schematic Sheet 8 Power Supply
31. FPGA routes either Vcc A19 or A20 to this pin depending on the memory mode set in the FPGA See Section EPROM Sockets EPROM Autoselect Feature for further information 9 21 P16 Background Debug Mode Connector Reference P16 Type 10W Low Profile Header Description Background Debug Mode Connector Only fitted to Software Development Boards DS BERR GND 3 4 BKPT GND 5 6 FREEZE RESET 7 8 IFETCH VCC 9 10 Document 80 15744 Issue 5 HEBER LTD 42 9 22 P17 RS232 Channel Reference P17 Type 9W D Plug Description RS232 Channel C GND DTRC Output from Pluto 4 TXC Output from Pluto 3 RXC Input to Pluto 2 CDC Input to Pluto 1 nc 8 CTSC Input to Pluto 7 RTSC Output from Pluto 6 DSRC Input to Pluto m B Note 1 This signal DTRC is commoned with RTSD 9 23 P18 RS232 Channels D E F amp G Reference P5 Type Header 26W 2 54mm Low Profile Description Connections for RS232 Channels D G 12V 12V 12V 3 4 12V Input to Pluto RXD RTSD Output from Pluto Output from Pluto TXD CTSD Input to Pluto GND GND Input to Pluto RXE RTSE Output from Pluto Output from Pluto TXE CTSE Input to Pluto GND GND Input to Pluto RXF RTSF Output from Pluto Output from Pluto TXF CTSF Input to Pluto GND GND Input to Pluto RXG RTSG Output from Pluto Output from Pluto TXG CTSG Input to Pluto Document 80 15744 Issue
32. P2 P8 P9 P12 and P14 for optional use by external circuits When connecting external loads to the Fused 12V outputs on P1 P2 P8 P12 and P14 make sure that the total current drawn is within the rating of fuse F1 3 15A making due allowances for the other loads as described above The 12V supply input provides the negative supply for the 1488 RS232 Transmitter Buffers 033 041 043 amp 046 and the 12V supply required the DATAPORT Connector P2 The Lamp Multiplex supply should be 36V or 48V depending upon the duty cycle employed by the software See Section Multiplexer for more information Transient suppressers Tranzorbs are fitted on the 12V supply fused side 12V supply and Vcc to protect these lines against any overvoltage 6 2 Reset and Power Fail Detection TL7705 device U17 on Schematic Sheet 10 provides the system reset At power up the system is held in a reset state RESET low RESET high for about 5 seconds This time is determined by C14 The processor may initiate a full hardware reset at any time by asserting Port B 0 PBO low which will trigger the TL7705 via the RESIN pin The RESET lines will also be immediately asserted by the TL7705 if the Vcc line drops below 4 75V While the system is a reset state i e RESET is low a red LED 101 is illuminated The power fail detection is a simple threshold detection on the 12V rail using one section of the quad compara
33. VMPX 0 ze E GND 13 MPX1_D_12v lt e VMPX O LR13 Ge 97 26 Ks LR14 BC846 a Q33 Es EE 26 100 KZ VMPX 0 1815 Gune 9 E BC846 22K Q34 GND an 99 Fee 26 KZ BC846 22K BC846 FEBERL TD lelvedere Mil halford Stroud GL6 8NT 44 0 1453 886000 Fax 44 0 1453 885013 itle PLUTO 5C LAMPROW DRVES Document Number 7 56 15741 72 HEBER LTD 1996 2002 Date August 12 2003 Sheet 12 of 18 Document No 80 15744 Issue 5 HEBER LTD Figure 13 Schematic Sheet 13 LED Segment Drives Page 56 u34 3 ao H OE 12V 11 12 3 MPX 5 SRAN 12V 11 12 ee 3 5 c CO 16 MEX 12 STR 12V 11 12 3 MPX1 DI DO MPXi A 12V 12 12Vo H2n NA 14 15 STR 12V 150R 3 MPX STR FO STR A 12V 11 BC337 Se
34. generated on Channel 1 to be heard through LS2 along with the sounds from Channel 2 Note that the Channel 2 Volume Control will adjust the overall volume of the sound heard from LS2 while the Channel 1 Volume Control will adjust the volume of Channel 1 relative to Channel 2 If the Channel 1 Volume Control is fixed at 7 or 8 where 15 is maximum then sounds reproduced through either Channel 1 or Channel 2 will come out at approximately the same level and the overall volume may be controlled by the Channel 2 Volume Control Document 80 15744 Issue 5 HEBER LTD 26 7 10 Using Multiplexed Lamps all Multiplex lamp outputs the Column Drives LC0 15 SINK current to ground and the Row Drives LRO 15 SOURCE current from the Lamp Supply 36V or 48V Thus any lamps should be connected between a Row and a Column drive with their series diodes orientated with the cathode towards the Column Drive The choice of operation at 36V or 48V is determined by the Power Supply and the software When running at 48V the software will sequentially drive all 16 Columns LCO 15 on a 1 16 duty cycle each column being ON for 1mS and OFF for 15 When running at 36V the software will sequentially drive only the first 8 Columns LCO 7 on a 1 8 duty cycle each column being ON for 1mS and OFF for 7 Please note that the multiplex circuitry is designed to drive 12V 100mA bulbs only 7 11 Using Multiplexed LEDs The multiplexed LED driv
35. it is permissible for a small number up to 16 of positions to drive either a higher power bulb 12V 180ma or a pair of 100mA bulbs These high load positions should be arranged such that no more than one is on one Row or Column drive The Lamp Multiplexer will normally be driven from a 48V dc supply Vmpx and run with a 1 in 16 duty cycle which allows the maximum complement of 256 lamps to be driven However if necessary a 36V Document 80 15744 Issue 5 HEBER LTD 17 supply be used provided the duty cycle is reduced to 1 8 which has the side effect of reducing the drive capability to 128 lamps and 128 LEDs 16 seven segment digits The Multiplex Array has hardware assistance from the FPGA to enable dimming control Dimming level may be set independently for each of the 16 Column strobes e g the 8 lamps on one Column Strobe could be set to one brightness level while the 8 lamps on a different Column Strobe could be set to another brightness The overall basic timing of the multiplexing remains under software control allowing overdrive of lamps for special effects Dimming is achieved changing the data presented to the Lamp Row LED Segment drives at an adjustable time within the 1mS strobe time Thus each lamp LED has two bits of data associated with it in software the first bit is the data applied during the first part of the 1mS Strobe period the second bit is applied during the second pe
36. of Q2 through R43 into the battery On charge the voltage BT1 will be about 2 6V so the current through R43 will be 5 2 6 3300 about 0 5mA Thus Q2 will be turned ON and Vbatt will be Vcesa below Current will therefore also flow through R132 into Vbatt 5 Vcg 4 2 6 3300 about 0 7mA Total trickle charge current is therefore 0 5 0 7 1 2mA The specification of the cells calls for a trickle charge of between 01C and 03C is 70mA so the acceptable range is between 7mA and 2 1mA When power is removed Vcc collapses to ground The base emitter junction of Q2 is now reverse biased and therefore no current flows through R43 and Q2 is OFF Vbatt is now connected to the positive end of BT1 via R132 The discharge current into the RAMs and RTC should not exceed 40uA which will result in a voltage drop in R132 of less than 0 15V This gives a worst case battery life in excess of two months and in practice much higher When on battery backup it is vital that the RAMs are placed in the standby state by ensuring that the CS line is high Q1 and R42 achieve this When the RESET line goes low which may occur either as a result of a Reset occurring or Vcc collapsing Q1 turns OFF causing the CS lines to the RAMs to be pulled to Vbatt by R42 6 4 The MC68340 Processor Full details of the operation of the processor is given in the Motorola MC68340 User Manual see Adobe Acrobat File 68340um pdf plus Addenda files 68340
37. 01615 SEG1 SEG3 5 5 SEG7 SEG9 SEG11 SEG13 SEG15 9 7 P5 Box Header Multiplexed LEDs Reference P5 Header 34W Tyco Box Header Type Description Document No 80 15744 Not Used Cathodes Digit O Cathodes Digit 2 Cathodes Digit 4 Cathodes Digit 6 Cathodes Digit 8 Cathodes Digit 10 Cathodes Digit 12 Cathodes Digit 14 Anodes Segment 0 Anodes Segment 2 Anodes Segment 4 Anodes Segment 6 Anodes Segment 8 Anodes Segment 10 Anodes Segment 12 Anodes Segment 14 DIGO DIG2 DIG4 DIG6 DIG8 DIG10 DIG12 DIG14 SEGO SEG2 SEG4 SEG6 SEG8 SEG10 SEG12 SEG14 Issue 5 LED Drive for 16 or 32 seven segment LED Digits Not Used DIG1 DIG3 DIGS DIG7 DIG9 DIG11 DIG13 DIG15 SEG1 SEG3 SEG5 SEG7 5 9 SEG11 SEG13 SEG15 Cathodes Digit 1 Cathodes Digit 3 Cathodes Digit 5 Cathodes Digit 7 Cathodes Digit 9 Cathodes Digit 11 Cathodes Digit 13 Cathodes Digit 15 Anodes Segment 1 Anodes Segment 3 Anodes Segment 5 Anodes Segment 7 Anodes Segment 9 Anodes Segment 11 Anodes Segment 13 Anodes Segment 15 Cathodes Digit 1 Cathodes Digit 3 Cathodes Digit 5 Cathodes Digit 7 Cathodes Digit 9 Cathodes Digit 11 Cathodes Digit 13 Cathodes Digit 15 Anodes Segment 1 Anodes Segment 3 Anodes Segment 5 Anodes Segment 7 Anodes Segment 9 Anodes Segment 11 Anodes Segment 13 Anodes Segment 15 HEBER LTD 33 9 8 P6 Multiplexed Lamps Sources
38. 2 Channels A amp B igure 11 Schematic Sheet 11 Lamp Column LED Digit Drives igure 12 Schematic Sheet 12 Lamp Row Drives igure 13 Schematic Sheet 13 LED Segment Drives igure 14 Schematic Sheet 14 Root Sheet 2 igure 15 Schematic Sheet 15 DUARTS Channels C H igure 16 Schematic Sheet 16 RS232 Buffers Channels C H igure 17 Schematic Sheet 17 Port H TTL Buffers igure 18 Schematic Sheet 18 Secondary NV RAM Security PIC Microcontroller igure 19 Pluto 5 Casino with Ultrex connectors Pluto 5CU Photograph igure 20 Pluto 5 Casino Component Ident Document 80 15744 Issue 5 HEBER LTD 1 1 INTRODUCTION Pluto 5 Casino Controller board is a natural progression in the Pluto family of products It builds on the proven reliability and technical excellence of previous Pluto boards and provides improved performance and flexibility at lower cost This manual covers the detail of the hardware operation of Pluto 5 Casino Controller board other boards in the system have their own manuals 2 NEW IN THIS RELEASE e Section 7 13 includes information about the Calypso 16 Video Card e Section B 1 includes information about Box Header type connectors and their corresponding part numbers e Schematic drawings have been updated to reflect hardware changes 3 OVERVIEW The Pluto 5 Casino Controller board is a low cost high performance single board controller for amusement machines An 8 reel ma
39. 5 A25 B25 825 2 TGATE PPIS 22K HDR 50W 74HC14 T 18 Lun 7 10 31 be R106 6 0 631 2 1 lt d 9 lt PPI7 22K 74HC14 lt 18 L 2 58 10 PORTA O 7 2 3 4 6 7 15 18 00 15 Eda 1 A2 A3 5 6 210 RXDA AQ 2 TXDA A10 2 CTA AT 2 RTSA A12 A13 A14 A15 A16 DIN41612 48W DIN41612 48W DIN41612 48W R2 VERT MALE R2 VERT MALE TY PE R 2 VERT MALE halford Stroud GL6 8NT 44 0 1453 886000 2 0 23 44 0 1453 885013 itle PLUTO 5 CONNECTORS Size Document Number 56 15741 712 HEBER LTD 1996 2002 Date Tuesday August 12 2003 Bheet 9 of 18 Document 80 15744 Issue 5 HEBER LTD 53 Figure 10 Schematic Sheet 10 Reset Battery RS232 Channels amp BATTERY BACK UP 5 Q2 VBATT 6 a TEA a 1 R42 PAD PAD 3K3 R43 PP18 Riad d ORM
40. 5 HEBER LTD 43 9 24 P19 Channel H TTL Serial Port Reference P19 Type Header 20W 2 54mm Low Profile Description TTL Level Serial Port Channel H Power Out 100mA Max Output from Pluto Input to Pluto Output from Pluto Input to Pluto Output from Pluto Output from Pluto Input to Pluto Input to Pluto 12V 1 2 TXDH RXDH 5 6 RTSH 7 8 CTSH 9 10 OP2 11 12 OP3 13 14 17 18 GND 9 25 P20 Power Off Security Monitor Reference P20 Type Header 8W AMP 100 Description 7 Switch Inputs monitored while Pluto powered off Document 80 15744 Issue 5 PSW1 PSW2 PSW3 PSW4 PSW5 PSW6 PSW7 PSW COMMON GND GND GND GND GND GND GND GND GND GND HEBER LTD Figure 1 Schematic Sheet 1 Root Sheet Page 44 000 15 SHT 9 CONNECTORS 23 5 6 OPEN DRAIN OUTPUTS CS DUART RESET cs rn 3 68MHZ SHT8 5V CURRENT SENSE CS 63 RW 015 63 OP 0 63 RESET DUEk po Ga 5 0 2 1 00 31 DSACKO _m aam 23 LITH METER SENSE SZC VREF SHT 77 INPUTS DIL SW CS_TTL SFX2_D 0 3 NM
41. 52 9 n 680R LC3 05 GND BGE552 9 1 3K3 8 SIL 12V 12V C17 C18 100n 100n GND GND 18W MIA 100 LAMP COLUMNS SINKS March 2003 THESE COMPONENTS OMITTED ON PLUTO 5 128 16 DRIVE FOR 108 15 0108 15 Rsense MPX REF2 BUK552 24 milliohms copper track C MPX 8 gt REF2 D4 D19 Changed from 1N4005 to UF4002 HEBERLTD lelvedere Mil halford Stroud GL6 8NT 44 0 1453 886000 Fax 44 0 1453 885013 ille PLUTO 5C LAMPILED SNKS Document Number 56 15741 712 HEBER LTD 1996 2002 Date Tuesday August 12 2003 Bheet 11 of 18 Document 80 15744 Issue 5 HEBER LTD Figure 12 Schematic Sheet 12 Lamp Row Drives Page 55
42. 56 3 96mm single in line headers with friction lock and polarisation AMP Ultrex 2 54mm dual row headers 25 way D Type Pluto 5CB uses the following 4 different families of connectors for connection to the cableform in the machine AMPMTA 100 2 54mm single in line headers with friction lock and polarisation AMP MTA 156 3 96mm single in line headers with friction lock and polarisation Tyco Box Header 2 54mm dual row headers 25 way D Type The actual part numbers of the board headers fitted to the Pluto 5 Casino PCB along with the part numbers of suitable mating cableform parts are given in the following tables Table 19 AMP Ultrex Connector Part Numbers Description PCB Header AMP IDC Connector Part Number AMP 28 24 AWG Wire EPOR M 32W Ultrex ee 172870 2 3 172866 2 50W Ultrex 5 172870 0 5 172866 0 P8 40W Ultrex 4 172870 0 4 172866 0 P9 34W Ultrex 3 172870 4 3 172866 4 Table 20 Tyco Box Header Connector Part Numbers Description PCB Header Tyco IDC Connector Part Number 2824AWGWire AWG Wire e P8 40W BoxHeader 8 1437061 5 10238979 P9 34W Header 7 1437061 5 10578 Document 80 15744 Issue 5 HEBER LTD 29 Table 21 100 Connector Part Numbers Description PCB Header AMP IDC Connector Part Number AMP Part No adiz Colour eg Colour Natural Colour Red
43. 886000 Fax 44 0 1453 885013 itle PLUTO 5C RESET BA TTERY RS232 Document Number 7 56 15741 712 HEBER LTD 1996 2002 Tuesday August 12 2003 Bheet 10 of 18 Document 80 15744 Issue 5 HEBER LTD Figure 11 Schematic Sheet 11 Column LED Digit Drives Page 54 N18 3K3 8 SIL Lqo 15 9 B10 SEGG A12 11 12 SEG7 SEGB A13 12 B12 SEG9 SEG10 A14 13 B13 Bia SEG11 SEG12 A15 14 B14 B15 SEG13 SEG14 A16 15 815 816 SEG15 13 15 16 B16 HDR 32W ULTREX OR 34W BOX HEADER Pins 33 34 no connection 7 SEG LED DRIVE 32 DIGIT OR 14 SEG LED DRIVE 16 DIGIT Loo Lco DIGO EZ u20 p STR_12V 14 str 4 R95 GO bie Heda 2215 g 5 1 R96 1 4 DIGI 13 CLK 12V HS 4 oR R E E 05 13 OE 12V OE 04 Hia 4 E SUR BGE552 Q5 Q6 H3 R100 680R 1 LC2 LC2 4 052 12v0 181 E 1 680R EO R104 EOI D6 Q8 4 PT BOK5
44. A 1K pull up to 5V Open drain output 150mA 1K pull up to 5V Open drain output 150mA 1K pull up to 5V Open drain output 150mA 1K pull up to 5V Open drain output 150mA 1K pull up to 5V Open drain output 150mA 1K pull up to 5V HEBER LTD 40 9 18 P13 External Bus Reference P13 Type Header 4W AMP MTA 100 Description External Bus 1 GND AUX7 SDA 12C SDA line TTL Open Collector I O 1K Pull up 3 AUX6 SCL 2 SCL line TTL Open Collector I O 1K Pull up 5V 9 19 P14 IO Expansion Card Connector Reference P14 Type DIN41612 C 2 Vertical Plug Description Connector for IO Expansion Boards 0I SES E SEE 2 09 PORTA CLKOUT 3 PORTA2 4 5 6 7 A22 8 AS 9 RXDA TTL DS 5 MW K TXDA TTL CTSA TTL DSACKO RTSA TTL DSACK1 5120 VCC 5121 15 2 5 GND 16 PB6 Document 80 15744 Issue 5 HEBER LTD 41 9 20 15 Memory Expansion Card Connector Reference P15 Type DIN41612 C 2 Socket Vertical Description Connector for Memory Expansion Boards 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 NB Pin c8 20 is in fact the connection to Pin 1 ROM P1 of the 2 on board EPROMs U1 amp U2 and is driven by the FPGA For all memory accesses excluding those to the ROM EPROM area mapped by 50 the FPGA routes A20 to this pin For all memory accesses to the ROM EPROM area mapped by CSO the
45. ATT VBATT ROM pe gt u2 2 12 13 12 13 B 10 DO 10 A1 11 AD 00 14 01 1 ORIAN 14 A2 SAS 29142 Di Bao 00 1 Di 1 Di S A2 10 15 02 A2 10 18 10 A3 8 13 02 A3 8 A2 D2 A2 D2 A2 02 2 02 9 17 D3 A3 9 17 Dii A4 7 15 D3 4 7 03 03 4 8 18 D4 4 8 18 D12 5 6 16 04 6 4 04 4 04 4 04 4 04 5 7 19 05 A5 7 19 013 AG 5 17 D5 6 5 5 05 5 05 5 05 5 05 6 6 20 D6 6 20 D14 AT 4 18 D6 AT 4 A6 D6 A6 D6 06 AG 06 AT 5 21 AT 5 21 015 AB 3 19 D7 3 AT D7 07 07 AT 07 27 A8 A 9 25 A9 25 A9 26 48 vec A9 287186 10 24 A8 A10 24 48 A10 23 A10 23 A10 9 11 21 410 AT 21 A10 A11 25 A11 25 A A12 23 A12 23 12 E bd A12 ga A13 2155 VBATT A13 215 A13 28 100n A13 28 100n 14 26 9 14 26 A13 A13 A13 A13 14 20 als A14 29 15 15 15 caer GND 15 GND AM EO u 100 518 Zar 418 2 A16 3 RAM WL 27 WR RAM WU 271 WR 30 A17 30 A17 10 RAM CS Ole ME 10 RAM CS Bice 9 18 31 A48 vec 32 voc A18 31 A18 vec 2 o veg RAM O 2 DE GND 2 power power HV62266BLFP 3 ROM O 22 3 ROM 25 m 22 H GND GND GND GND GND EPROM EPROM EPROMS 2 27 040 OR 2 27 801 13 04 32
46. Aig 18 B19 IP31 os Mig 8 ia A20 19 B19 B20 m 6 CS TT Q6 17 12V0 12 eri em ar HDR8W AMP MTA 100 1 PGND GND HDR4OW PGND B GND 42 PIC FO RC 18 I O 2 PGND GO P1 GND PGND GND gt 1 18 TPIC6B259 A pi Bi 50 2 82 EMC FILTER 52 B3 053 B7 054 83 B4 GE AB 87 OP T ENCE 56 As B5 OP2 A9 OP5B 85 B6 59 OPS 101 49 pig B10 Ops aL LC5 6 E OPS 0 E B11 EMC FILTER 62 AB ZA Bg 6 OPS A12 11 HEE 1 3 A9 88 GND GEO 13 B13 bea A10 A gi BIO IT 1 12 13 813 14__ AMP 100 1 8 E Bii E 14 A18 414 Big 15 __ EO Bi B12 16 A16 15 Bie 16 L 2 2121442 Big 813 18 815 B17 GND EZ AMA 813 B14 5 OP20 17 EU OP21 ES A15 At Bis B15 22 A19 818 819 ZE A16 415 815 Bis IPIS A20 MS Boo B20 A17 B17 2 21 B21 12VO 17 B17 21 B21 E A22 21 821 B22 E A23 23 VMOT o A23 B23 VMOT HDR 34W 24 B24 R107 vMotT o 424 A24 824 VMETER 0 1 VMOT o A2
47. CPU Size Document Number ev A3 56 15741 72 HEBER LTD 1996 2002 Tuesday August 12 2003 2 of 18 Document No 80 15744 Issue 5 HEBER LTD Figure 3 Schematic Sheet 3 FPGA Page 46 2 RMW 2 915 2 5120 5 6 CS_IP 7 10 RESET WL 4 2 CS0 RAM WU 4 2 CS1 2 CS2 2 2 9 2 4 6 7 9 15 18 00 15 4 ROM OE 4 ROM P 4 PLUTO 5C FPGA GND FPGA 6 4 VCO ede see zelo ue lolo 58 gt o 2 5 21 vo H4 137 5 14119 FPGAO 15 vo vo 71 FPGA1 16 00 1719 E FPGAS GND voc 88 o vec 3K3 8 SIL m GND Z vo mote GND 4 21110 65 FPGA4 A5 22 64 AG 23119 0000 FPGAS 2 1o io E FPGAS SEX2 DIO 3 25 GND 8 GND 19 Hie 59 S
48. EBER LTD 15 6 10 AUX Outputs AUX0 7 8 auxiliary TTL level open drain outputs are provided by U30 see Figure 9 Schematic Sheet 9 10 Connectors U30 is a TPIC6B259 which functions exactly the same as the TPIC6259 devices used to drive 63 but with a lower drive capability see data sheet tpic6b259 pdf On the Standard Pluto 5 they are memory mapped as the least significant bit of a block of 8 bytes of address space at an address determined by the FPGA fitted to the board However on the Pluto 5 Casino Controller they are selected by the same line as the 64 Open drain outputs 0 63 via 1 2 74 139 052 They are open drain outputs fitted with 1K pull up resistors to Vcc AUXO 5 are routed to connector P12 AUX OUTPUTS AUX6 7 are routed to Connector P13 6 11 Inputs 0 31 External inputs are catered for by 32 input lines IPO 31 shown on Schematic Sheet 7 Like the Open Drain outputs these are memory mapped as the least significant byte of a block of 4 words of address space Each input is provided with a 3K3 pull up resistor to Vcc 5V and feeds into a 74HC family device rather than 74HCT This give the inputs a low level threshold of 1 5V and a high threshold of 23 5V The 47K resistor in series with the input protects the 74HC253 devices from noise spikes or high voltages on the inputs The 1 5V low threshold allows the inputs to be safely driven as a multiplexed array wi
49. EBER LTD 9 4 Power Input Page 31 Reference P3 Type Header 6W AMP MTA 156 Description Power 12V GND GND 12V GND Vmpx Neg supply for RS232 buffers Ground Ground Main supply Ground Lamp MPX supply 36V or 48V 9 5 P4 Multiplexed Lamp Sinks Reference P4 Type Header 18W AMP MTA 100 Description Lamp Columns Sinks Document No 80 15744 LCO LC1 LC2 LC3 LC4 LC5 LC6 LC7 LC8 LC9 LC10 LC11 LC12 LC13 LC14 LC15 Issue 5 Lamp Column Sink 0 Lamp Column Sink 1 Lamp Column Sink 2 Lamp Column Sink 3 Lamp Column Sink 4 Lamp Column Sink 5 Lamp Column Sink 6 Lamp Column Sink 7 Lamp Column Sink 8 Lamp Column Sink 9 Lamp Column Sink 10 Lamp Column Sink 11 Lamp Column Sink 12 Lamp Column Sink 13 Lamp Column Sink 14 Lamp Column Sink 15 No Connection No Connection HEBER LTD 32 9 6 P5 Ultrex Multiplexed LEDs Reference P5 Header 32W AMP Ultrex Type Description Cathodes Digit 0 Cathodes Digit 2 Cathodes Digit 4 Cathodes Digit 6 Cathodes Digit 8 Cathodes Digit 10 Cathodes Digit 12 Cathodes Digit 14 Anodes Segment 0 Anodes Segment 2 Anodes Segment 4 Anodes Segment 6 Anodes Segment 8 Anodes Segment 10 Anodes Segment 12 Anodes Segment 14 DIGO DIG2 DIG4 DIG6 DIG8 DIG10 DIG12 DIG14 SEGO SEG2 SEG4 SEG6 SEG8 SEG10 SEG12 SEG14 LED Drive for 16 or 32 seven segment LED Digits DIG1 DIG3 0165 0167 0169 01611 01613
50. EX2 DO 20 28 58 SEX2 DT A21 29110 E 67 5 2 02 22 19 to 56 SEX2 03 A23 31 55 SFX2 vo vo SFX2_VCK 5 32 vo 54 LTH RAM LTH 18 a o OOOOOOOZOOOOOOOOOOOOO a a dazae d ek tae oP de ae oe exo oo F 2 FPGA 859 SS SFX1 0 3 GND FOM PIR gt ROM P12 4 1 5 spi gt gt 58 SFX 2 DREQI MPX OE 13 2 DREQ2 MPX_CLK 13 MPX_STR_13 13 2 15 3 68MHZ CS DUART 15 2 MPX STR DATA A 13 2 CLKOUT R104 1 1 10M 1 R105 1 14 7456 2 680R gt FEBERLTD 33p 33p vec vec vec vec 9 9 9 9 GND GND halford Stroud GL6 c34 C35 C36 el 44 0 1453 886000 100 100 100 100 44 0 1453 885013 GND GND GND GND ile Document Number 56 15741 712 HEBER LTD 1996 2002 Date August 12 2003 Sheet 3 of 18 Document No 80 15744 Issue 5 HEBER LTD Figure 4 Schematic Sheet 4 Memory Page 47 2 3 6 7 9 15 18 00 15 3 TYPE 2 VERT SKT TY PE 2 VERT SKT 23619518 00 15 lt gt gt 2 Alo 23 gt eg VB
51. F AS PIC PO REF2 E DS PIC P1 sp p CS SEL 0 2 RW 7 0 15 DSACKO SFX_CLK 000 15 DSACK1 15741 8 Pp 31 520 15741 14 SERIAL PORTS 15741 7 m CLKOUT SHT 2 MC68340 CPU SHT4 RE CS TXDA CS CTSA RAM GS RAM_CS RTSA WL RAM WL 23 RXDB RAM WU WU DID 15 TXDB RAM RAM 00 15 da CTSB ROM P12 ROM P12 RTSB ROM OE ROM 0 6 RESET ROM RESET 3 68MHZ RAM LITH 15741 4 6 SFX2_VCK MPX_CLK BEE MPX_CLK MEX STR 0 15 MPX_STR MEX OE PIC_OPO DP 15 ON 00 15 MPX_OE DATA MPX1_DATA_A 6 521 lt DATA A MPX STR DATA SHT 13 LED SEG DRIVES SFX2 D 0 3 MPX_CLK CE DUNEN CS_DUART SFX1 D 0 3 MPX STR D 0 15 SFX1_VCK MPX_OE 0 23 23 0 23 SFX_CLK DATA P RTA 0 7 MPX STR DATA METER SENSE SENSE Tif MPX2 DATA A SFX NMF MPX1_D_12V SFX_MX 7 SFX_CLK CLK 12V TOUT2 PORTA 0 7 SFX1 VCK STR 12V MPX1 C 12V 151 SFX1_D 0 3 OE 12V 152 SFX2_D 0 3 MPX1_A_12V MPX1 B 12V POPS POPS SFX2 VCK TGATE2 TOUT TOUT SFX2 VCK R RESET STR_A_12V SEG 0 15 TOUT2 TOUT2 RESET 15741 13 HALT bd SHT 11 COL DIG SINKS d 12V SEGQ0 15 10 RESET BATT RS232 2C 11 RAR iay 0 15 ZO
52. GA Start 1mS timer Loop watching lines PORTA6 and PORTAT If PORTA7 line goes high there is a short circuit in this position so immediately disable the multiplex drives by turning off Multiplex OE line in the FPGA f PORTAG line goes high but not PORTAT then there is a light bulb connected and apparently working e f 1mS timer times out without either line going high then either no bulb present or it is open circuit e Record result and go on to next bulb e When complete act as required on results Re enable SFX CLK to allow Sound Channels to work 6 17 Sound Generation The sound generation circuits are shown on Schematic Sheet 5 08 and optionally 039 are the source of Sound Channel 1 amp 2 respectively with the audio output being pin 10 Aout These OKI MSM6585 devices are 4 bit ADPCM D A converters capable of running at sample rates of 4KHz 8KHz 16KHz or 32KHz This rate is selected by software by setting levels on the 51 52 pins On Channel 1 08 these pins are controlled by the 4 and OP6 lines from the MC68340 Serial Module On Channel 2 039 these pins are controlled by the PORTA6 and PORTA lines from the MC68340 SIM40 Module The VCK output from the MSM6585 is a square wave at the sampling frequency selected by 51 and 52 The MSM6585 reads the 4 bit sample immediately after the rising edge of VCK The VCK from the MSM6585 is connected to the FPGA where it is divided by 2 to produce a DMA Reque
53. K 8 STATIC RAMS SOP PINS 1 12 SET BY FPGA MODE ROM 12 READ 1 27 040 vec A0 0 READ 2 27 040 19 READ 1 27 801 19 A0 0 READ 2 27C801 A20 A19 NON ROM CYCLE A20 A0 A19 RESET 1 1 2 23 LINES FPGA0 6 HAVE THE FOLLOWING DEFAULT FUNCTIONS FUNCTION MEM CARD PRESENT ROM MAP 1 ROM MAP 2 WU WRITE HIGH BYTE WL WRITE LOW BYTE B13 613 bora CS FOR EXPANSION RAM B14 C14 B15 C15 A16 B16 C16 DINA41612 48W DIN41612 48W DIN41612 48W TY PE C 2 VERT SKT 11 08 12 09 13 D0 15 D11 16 D12 AT D13 18 D14 19 015 VBATT 100n GND HM62256BLFP HEBERLTD lelvedere Mil halford Stroud GL6 8NT 44 0 1453 886000 Fax 44 0 1453 885013 ille PLUTO 5C MAIN EPROM RAM Document Number 56 15741 712 HEBER LTD 1996 2002 Date Tuesday August 12 2003 Bheet Document 80 15744 Issue 5 HEBER LTD Figure 5 Schematic Sheet 5 Sound Page 48 SAMPLED SOUND CHANNEL 1 SAMPLED SOUND CHANNEL 2 vec c
54. ND GND GND GND GND PLUTO 5C RS232 BUFFERS Eie Document Number 7 56 15741 72 HEBER LTD 1996 2002 Date Tuesday August 12 2003 Bheet 16 of 18 Document No 80 15744 Issue 5 HEBER LTD Figure 17 Schematic Sheet 17 Port H TTL Buffers Page 60 15 BEE 15 15 RXDH 15 TXDH 15 ETZ 15 EXP OP2 15 EXP R153 vcco 3k3 R154 R155 3K3 R156 19 1 gt R139 2 T 2 6140 TXO 3loo RTSH 4 16 4 19 EXP 2 12 47R R145 1 taper EXP EEE 8 12 aR EZ 478 XRTS XCTS R151 13 T 47R P 89 73 2 R152 47824 15 2 2 EZE SES 47K 2 1 3 19 9 2 e iilan 2 12 7294 GND T 16 T EE 1 SEE 18 129 EEE 18120 CTSH 20 RXDH 20W GND vec o PORT H TTL LEVEL 100n GND FEBERLTD lelvedere Mil halford Stroud bucester shire GL6 8NT 01453 886000 Fax 01453 885013 ille PLUTO 5C PORT H TTL LEVELS Document Number 56 15741 712 HEBER LTD 1996 2002 Date Tuesday
55. O 4 1 2 15 PAD Bh b 2N7002 24V NiMH z I PL A 1 GND 1 3 GND RS232 RESET 2 TAL gt A9 wont a 2 PTA Herrri dro 82 b 12 5 2 Ho HDRGW AMP 100 19 xc 2 H 131 p DO 2 o 1488 062 x2 RTC GND 22p 32Khz 40 ab 1 voo 8 VBATT PORTA 7 2 5 8 9 1 R OSCO NT PORTA4 14 Ea SCL SDA HAT GND GND SDA 4519 PCF8583 R161 5 16 oo 4 120R RS u37 ee gari GND AO vec 8 VCC VCC 19 DATAPORT GND 2 GND GND o 20818 A2 SCL GND 4 spa EZ Pride 24 04 24 08 5 9 22 9 Dots 10 INTERNAL 126 BUS Alte 3 1 23 29 RXDA RXA goatee pn e 7095 ER 2 CTSA bon lt a 8 10 2 RXDB C J RXC 12 0 281 0 11 13 2 lt RXD C 25W D SOCKET Q 2 o 1489 PP19 T POWER ON RESET GND vREF lt id u17 2 69 15 18 RESET lt S RESET 9 sense 7 gt pegi ek EEEn 8 RESET RESN 2 Ceo 2 2 3 gt j R41 REF o 100 117705 c 14 220 16 100 1 1 1 GND EBERT TD lelvedere Mil halford Stroud GL6 8NT GND 44 0 1453
56. Output 48 OP48 Open drain Output 50 OP50 Open drain Output 52 OP52 Open drain Output 54 OP54 Open drain Output 56 OP56 Open drain Output 58 OP58 Open drain Output 60 OP60 Open drain Output 62 OP62 Open drain Output 49 Open drain Output 51 Open drain Output 53 Open drain Output 55 Open drain Output 57 Open drain Output 59 Open drain Output 61 Open drain Output 63 GND Input 6 IP6 Input 7 Input 8 IP8 Input 9 Input 10 IP10 Input 11 Input 12 IP12 Input 13 Input 14 IP 14 Input 15 Input 16 IP16 Input 17 Input 18 IP18 Input 19 12V Current Sensing 12V Document 80 15744 Issue 5 HEBER LTD 9 15 P10 Loudspeakers Page 39 Reference P10 Type Header 5W AMP MTA 100 Description Loudspeakers 1 151 Loudspeaker Channel 1 LS1 Loudspeaker Channel 1 3 MIX Channel 2 mixer input LS2 Loudspeaker Channel 2 LS2 Loudspeaker Channel 2 WARNING Loudspeaker outputs are bridge driven and must NOT be connected ground 9 16 P11 Multiplex Expansion Reference P11 Type Header 7W AMP MTA 100 Description Multiplex Expansion MPX1_DATA_A 12V CMOS Output 2 Logic 1 Level 12V CMOS Output MPX_STR_A 12V CMOS Output GND MPX_CLK 12V CMOS Output 6 STR 12V CMOS Output MPX_OE 12V CMOS Output 9 17 P12 Aux Outputs Reference P12 Type Header 8W 100 Description Aux Outputs GND AUXO AUX1 AUX2 AUX3 AUX4 AUX5 12V Document 80 15744 Issue 5 Open drain output 150m
57. Pluto User Manual Pluto 5 Casino Controller Document No 80 15744 Issue 5 HEBER LTD Current Issue Issue 5 12th August 2003 Previous Issues Issue 1 8th June 1999 Issue 2 4th January 2000 Issue 3 5th February 2002 Issue 4 8th October 2002 Ltd 2003 This document and the information contained therein is the intellectual property of HEBER Ltd and must not be disclosed to a third party without consent Copies may be made only if they are in full and unmodified File Name H pluto5 manuals pluto_5_casino doc HEBER LTD Document No 80 15744 Issue 5 HEBER LTD Belvedere Mill Chalford Stroud Gloucestershire GL6 8NT England Tel 44 0 1453 886000 Fax 44 0 1453 885013 Email Bupport heber co uk ttp www heber co uk File Name H pluto5 manuals pluto_5_casino doc HEBER LTD Document No 80 15744 Issue 5 Page i CONTENTS Document 80 15744 Issue 5 HEBER LTD Page ii Document 80 15744 Issue 5 HEBER LTD Page iii LIST OF TABLES LIST OF FIGURES Figure 1 Schematic Sheet 1 Root Sheet igure 2 Schematic Sheet 2 CPU igure 3 Schematic Sheet 3 FPGA igure 4 Schematic Sheet 4 Memor igure 5 Schematic Sheet 5 Sound igure 6 Schematic Sheet 6 Open Drain Outputs igure 7 Schematic Sheet 7 Inputs igure 8 Schematic Sheet 8 Power Suppl igure 9 Schematic Sheet 9 IO Connectors igure 10 Schematic Sheet 10 Reset Battery RS23
58. R126 by comparators U16C and U16D see Schematic Sheet 8 These thresholds correspond to nominal currents of about 375mA and 4 8A The outputs of the 2 comparators U16C and U16D are connected to processor lines PORTA6 and PORTA The current sensing comparators may be disabled by SFX CLK being enabled When SFX CLK a 640kHz clock is enabled by setting a bit in the FPGA see FPGA USER MANUAL the inputs of the 2 comparators are pulled up to about 5V by D21 C9 C10 which forces the comparator outputs which are open collector OFF In this state the lines PORTA6 and PORTA are free to be used as outputs driving the S1 amp S2 pins of SFX Channel Z2 or as required by any card fitted to the Expansion Connector P14 When the SFX CLK is turned OFF and forced low voltage on C9 10 is discharged by R127 and the current sensing circuit is enabled With no current through the Column Digit Sinks both outputs PORTAG 7 will be LOW because V lt V on the comparators When the current through the 24mQ resistor exceeds a nominal 375mA PORTA6 will go high When the current exceeds a nominal 4 8A 7 will also go high Document 80 15744 Issue 5 HEBER LTD Page 18 sequence of operation to test a lamp is as follows Turn off SFX_CLK in FPGA to enable circuit Turn off all Row Digit drives on MPX1 Ensure PORTA6 and PORTA7 both read 0 Turn on lamp to be tested on multiplex by writing appropriate data to FP
59. ao GND GND SFX1 0 31 gy w 3 SFX2_D 0 3 lt gp S 8 12 8 12 8 J PORTANO 7 Di 5 2 89 10 PORTA O 7 D2 1318 9 n D3 gei m POP4 SEX1_S1 dise PORTAG SFX2 51 die oe EE SFX1_S2 zi pac elg PORTA SFX2 52 ESKO da PORTAO 15 1 seser PORTA 1 45 eeen SFX_CLK 8 gt 168 xr aour 2 SFX_cLK gt 16 xr H2 os vec H o 585 MSNB 585 o R111 2130 JL 2 d 47K 2 GND GND SFX1_VCK lt SFX1 VGK SFX2 VCK L SFX2 C44 gt C51 10n 10n R129 cag 4 R112 R131 22K 1 50 22K 22K BE C50 220 16 100 M u32 LS CONNECTOR 13 PPS EO 3 1 131 a2 US1 11 1 50 PP 3 CH2 MX R108 4 152 1 4 TOUT 2 8 d HDR SW AMP 100 ah 045 R109 5 1 50 3K3 10 1 50 R110 id 1 4 TOUT2 2 TDA7057AQ R113 al o 1 50 3K3 GND 4 4 1 lelvedere Mil halford Stroud GL6 8NT 44 0 1453 886000 Fax 44 0 1453 885013 Tie PLUTO 5C SOUND Size Document Number 7 56 15741 7 2 HEBER LTD 1996 2002 Date Tuesday August 12 2003 Sheet 5 of 18 Document No 80 15744 Issue 5 HEBER LTD Figure 6 Schematic Sheet 6 Open Drain Outputs Page 49 ZEU 63
60. as gone high Because of possible delays in responding to a meter being turned on it is recommended that the software checks the current sense pin immediately before the meter is turned OFF at the end of a pulse To detect tampering or a failure of the current sense circuitry the software should also check that the current sense pin goes LOW when no meter is operated Document 80 15744 Issue 5 HEBER LTD 25 7 9 Making Sounds Loudspeaker outputs on connector P10 are bridge driven so do NOT connect either connection of a loudspeaker to ground or to any other loudspeaker drive Ideally 8Q loudspeaker s should be used but higher impedance components could be used without any risk of damage to the amplifier The use of 3 or 4ohm loudspeakers should be avoided It is possible to run the sound in a number of different modes 7 9 1 Single Channel Single Speaker Mono Mode This is the lowest cost option using the standard Pluto 5 Board with a single loudspeaker The optional SFX Channel 2 039 is not fitted and only SFX Channel 1 U8 is operational A single loudspeaker is connected to LS1 pins 1 amp 2 only Pins 3 4 5 should be left open 7 9 2 Single Channel Dual Speaker Mode This mode still uses the standard Pluto 5 Board with only SFX Channel 1 U8 operational but allows the use of 2 loudspeakers to improve the quality or quantity of the sound One loudspeaker LS1 is connected between Pins 1 amp 2 of P10 Th
61. chine with 256 lamps 32 LED digits Linewriter display Coin Acceptors Note Acceptors and Payout Hoppers can be controlled without any additional boards Single channel sound can be played through one or two speakers Two Channel mono or stereo sound is available by plugging in an additional IC Pluto 5 Casino boards are supplied with either Ultrex or Box Header connectors Pluto 5 Casino with Ultrex connectors is referred to as Pluto 5CU Pluto 5 Casino with Box Header connectors is referred to as Pluto 5CB These connectors and all the other connectors on the Pluto 5 Casino board are documented in section p onnector Types and Pin Outs in this user manual Integrated Processor with DMA 4 DIFFERENCES FROM PLUTO 5 The Pluto 5 Casino Controller is basically an upgrade to the standard Pluto 5 Controller with the following additional functionality added 1 Provision for up to 6 extra serial communication ports Channels3 C H by fitting DUARTs U53 U54 amp U55 2 Additional 32Kbyte RAM with independent battery backed supply 3 Provision for a battery powered PIC Microcontroller which allows power down monitoring of up to 7 external switches To allow the above additions the following changes have been made to the operation of the controller 1 Astandard Pluto 5 FPGA will not work in the Pluto 5 Casino Controller the functions of pins 48 amp 54 are changed 2 The Multiplex Expansion MPX2 facility offered on Plut
62. d PLCC socket position U6 into which is plugged an FPGA The standard FPGA type used is Actel A40MX04 PL84 The purpose of fitting an FPGA to the system is twofold First to allow the Pluto 5 Casino Controller to be uniquely configured for each user of the system to give commercial and software security see FPGA SECURITY MANUAL Secondly it allows particular advanced features for example the EPROM Autoselect and Multiplex dimming to be economically implemented The following main functions are carried out by the FPGA Control automatic EPROM mode selection Generate control signals for on board EPROM and RAM Generate control signals for Memory Expansion Connector P15 Generate DMA requests and multiplex data for Sound Channels 1 amp 2 Control and drive of data to Multiplex Arrays both on board MPX1 and expansion MPX2 Provide various levels of Software Security Form an oscillator with 14 75MHz resonator Generate Main Clock EXTAL for MC68340 Processor 32 768kHz Generate clock for MC68340 Serial Module 3 6864MHz Generate clock for OKI MSM6585 devices U8 39 640KHz 6 6 EPROM Sockets EPROM Autoselect Feature The 2 EPROM positions U1 and U2 are configured such that 4 possible configurations of programme memory are possible assuming no external memory expansion via P15 Table 5 Possible EPROM Configurations Configuration Total Size Addresses scrambled 27 040 512k 8 512Kbyte 27 040 27 040 16 bit 512K
63. e Tuesday August 12 2003 Bheet Document 80 15744 Issue 5 HEBER LTD 62 Figure 19 Pluto 5 Casino with Ultrex connectors Pluto 5CU Photograph Document No 80 15744 Issue 5 HEBER LTD Figure 20 Pluto 5 Casino Component Ident 385232 CH D TO C58 655 R8232 use The 044 var A Page 63 COMPONENT LEGEND LAYER 56 15741 3 POFF INPUTS 41 P17 u53 55 1 0 EXPANSION A P14 PLUG w CLKOUT 5 us C51 be HEBER Ltd PLUTO 5 R111 R108 R189 5 MEMORY EXPANSION T 9 P15 SKT gt BDM _ C28 qe CL j HEEEEHHEEEH HO 18 7 R144 E C61 R142 E EZ R148 66 Ce2 LAMP SRC P6 Document No 80 15744 Issue 5 HEBER LTD
64. e circuit is intended to be used with Common Cathode digits either 7 segment plus decimal point or 14 segment The common cathode connection of each digit should be connected to a digit drive output DIGO 15 on connector P5 Each digit drive output can drive two 7 Segment Digits the segment anodes for one connecting to drive SEGO 7 and the other to SEG8 15 By convention segment would connect to SEGO or SEG8 Alternatively 14 segment starburst digits can be used in which case each digit output would drive one digit and the 14 segment anodes should each be connected to one of the segment drive lines SEGO 13 The LED Digit drive circuitry shares the same Current Sink transistors as the Lamp Column drives Thus if the system is being driven in a 1 8 duty cycle to allow a 36V Lamp Supply only Digit drive lines DIGO 7 are active In this case only 16 Seven Segment LED digits may be driven from the controller 7 12 Using the Multiplex Expansion Connector The outputs on P11 are all CMOS signals swinging between GND and 12V These signals may be connected to Pluto 5 Multiplex Expansion Boards to increase the Lamp and or LED drive capability of the system See the PLUTO 5 MULTIPLEX EXPANSION BOARD USER MANUAL for details of connection and operation 7 13 Adding Video Capabilities A Calypso 16 Video Card is available from Heber Ltd which plugs directly onto the Pluto 5 Casino board via the 2 DIN41612 connectors P14 and P15 Se
65. e of this module are 6 4 2 1 Module Base Address Register Set the Module Base Address Register MBAR to a suitable address during initialisation This sets the base address of all the internal module registers In the example code it is set in Module except asm to value Oxffff 1000 There is nothing magic about this value but obviously it must be set to an address that is clear of any other devices in the processor memory map This register must be set before any other module initialisation is attempted 6 4 2 2 Chip Selects Set up the 4 Chip Select outputs 50 to CS3 The Pluto 5 System allocates these as follows CS0 is used to map the system programme memory This consists of any EPROM fitted to the on board EPROM sockets U1 and U2 plus any extra EPROM or FLASH devices fitted to the Memory Expansion Connector P14 Exact mapping within the area defined by 50 is carried out be the system FPGA CS1 is used to map the on board battery backed RAM if fitted any external RAM on memory card on connector P15 CS2 is used to map both the internal registers of the FPGA and the on board CS3 is normally spare and is available on the I O expansion connector P14 Its main use is for the selection of the optional add on CGA VGA Video Card After hardware reset CSO will be asserted for memory accesses anywhere in the memory map which allows the processor to boot However the chip selects must be progra
66. e second loudspeaker LS2 is connected between Pins 4 amp 5 of P10 A wire should also be fitted joining together Pins 1 amp 3 of P10 which allows the sound from SFX Channel 1 to be reproduced via Amplifier Channel 2 The Channel 1 Volume Control will control the overall volume heard from both speakers while Channel 2 Volume Control may be used to control Balance allowing an adjustment of the level of sound heard from LS2 relative to LS1 If Channel 2 Volume is fixed at 7 or 8 where 15 is maximum this will result in approximately equal sounds being heard from each speaker and the overall volume may be controlled by the Channel 1 Volume Control 7 9 3 Dual Channel Dual Speaker Stereo Mode In Stereo Mode the optional second channel IC U39 is fitted and 2 loudspeakers are used connected to LS1 and LS2 pins Pin 3 is left open Channel 1 Volume Control will adjust the level of LS1 Channel 2 Volume Control will adjust the level of LS2 In this mode true stereo sound effects may be reproduced although the subjective effect heard by the player will depend upon the placement of the loudspeakers in the cabinet 7 9 4 Dual Channel Single Speaker Mode This mode may be used when the Pluto 5 Casino Controller is used in a cabinet containing only 1 loudspeaker but has the optional Channel 2 IC 039 fitted The single loudspeaker is connected to the LS2 pins 4 amp 5 of P10 A link is fitted between pins 1 and 3 This will allow sounds
67. e the CALYPSO 16 USER MANUAL for details The Calypso 16 Video Card supersedes the Pluto 5 CGA VGA Video Card For further information the Pluto 5 CGA VGA Video Card refer to the PLUTO 5 CGA VGA BOARD USER MANUAL Document 80 15744 Issue 5 HEBER LTD 27 8 SOFTWARE DEVELOPMENT A number of options exist for the development and debug of software for use on Pluto 5 Software will normally be generated using a Cross Assembler Cross Compiler and Linker package A suitable package is included with the Pluto 5 Development Kit When software has been successfully compiled assembled and linked it may be tested and debugged using the Background Debug Mode facility built in to the 68340 Processor For full details of debugging refer to the PLUTO 5 DEVELOPMENT KIT QUICK START GUIDE and other documentation supplied with the Development Kit Document 80 15744 Issue 5 HEBER LTD 28 9 CONNECTOR TYPES AND PIN OUTS 9 1 Schedule of Connector Types There are two types of Pluto 5 Casino Board with either Ultrex or Box Header connectors and 3 other families of connectors e Pluto 5 Casino with Ultrex connectors is referred to as Pluto 5CU e Pluto 5 Casino with Box Header connectors is referred to as Pluto 5CB Pluto 5CU uses the following 4 different families of connectors for connection to the cableform in the machine AMPMTA 100 2 54mm single in line headers with friction lock and polarisation AMP MTA 1
68. ered to RS232 levels and connected to DATAPORT connector P2 Signals RX TX RTS and CTS are provided The 4 Channel A signals are also made available on the TTL Expansion Connector P14 at TTL levels Thus alternative interfaces be provided on an Add on Board to allow say RS485 or Mars HII interfaces to be implemented The exact set up of the Serial Module will obviously depend upon the functionality required Document 80 15744 Issue 5 HEBER LTD Page 10 Pins controlled by the Serial module are allocated as follows Table 3 Allocation of MC68340 Pins Controlled by Serial Module PIN NO FUNCTION 33 RXDA RX DATA Channel A 1 Pin 2 RS232 level amp To Expansion Connector P14 Pin 9 TTL level pem EZ TX DATA Channel A P1 Pin 3 RS232 level amp To IO Expansion Connector P14 Pin c10 TTL level 25 RX DATAChannel DATAPORT P2 RS232 level 2 TXDB 24 Channel DATAPORT P2 RS232 level 2 OPO RTSA 29 RTS Channel A P1 Pin 5 RS232 level amp To 10 Expansion Connector P14 Pin c12 TTL level OP1 RTSB 23 RTS Channel DATAPORT P2 RS232 level OP4 RXRDYA 27 SFX Channel 1 U8 Pin S1 Select Sample Rate OP6 TXRDYA 26 SFX Channel 1 U8 Pin S2 Select Sample Rate CTSA 28 CTS DUART Channel A P1 Pin 4 RS232 level amp To IO Expansion Connector P14 Pin c11 TTL level CTSB 22
69. hree 44 lead PLCC sockets are provided 053 054 and 055 into which may be fitted 68681 or 68692 DUARTs These are mapped as 8 bit devices by the FPGA Please consult the User Manual for the FPGA being used for details of mapping e Channel C is buffered to RS232 levels and taken to 9 way D Type Plug P17 to provide a PC AT compatible Serial Port with lines RX TX RTS CTS DST DTR amp CD Control line RI is not implemented e Channels D G are buffered to RS232 levels and taken to connector P18 Only RX TX RTS amp CTS lines are provided on these channels e Channel H is buffered to TTL levels by non inverting buffer U49 and taken to P19 3 Input and 3 Output control lines are provided in addition to the RX and TX data lines Document 80 15744 Issue 5 HEBER LTD 21 6 21 1 Mapping of DUART Lines The I O lines of the DUARTs are mapped as shown in the following tables Pin Channel Name Comments C RS232 Level to P17 3 TXDD RS232Llevelto P18 7 RXDD RS232levelto 85 ___ D RTSD RS232LeveltoP18 6 OP2 __ _ ________ Noconnection ___________ Noconnection __ _ 5 Noconnection OP6 Noconnection EE jNocomecin IPO CTSC RS232 Level to P17 8 D CTSD RS232Levelto P18 8 2 DSRC RS232 Level to P17 6 RS232 Level to P17 1 PA 1 Strapped to
70. i 9 10 RTSA RTSA OPO 18 E A19 5 221 EXSDYAJOPA A20 1 5 POP TXRDY A OP6 A21 AS RXDB 25 an d Ze 08 23 3K3 8 SIL 10 CTSB CISB 22 CTSB RISB 23 5 10 RTSB RTSBIOPI ee A24 PAQ roe 9 TGATEH gt 79 2 Do 2 2 VCC 81 Di 3 AQ 3 0 50 TInt A26 PA2 IACK2 02 4 AG 1 5 lt 1 27 Sensi D3 5 Ad 5 36 A28 PA4 ACK4 D4 6 A12 6 9 TGATE gt gt 29 5 55 7 Aq 7 dris 34 d d 5 lt TOUT2 A31 PA7 IACK7 D ae B gt d 12 3K38 SIL 3K3 8 SIL 2 DAGO DACK2 a DONEI 14 DONE2 DONE DONE2 m ee 6 77MH Eu cLKoUT 2 He vec Era 32 768KHz 91 LE 3 68MHZ 8 m 3 ATT 3 a 5 5 PAD PAD 012 6 20 6 D13 7 21 L 89 20 014 8 A22 8 B D15 9 A23 9 90 21 o 21 Los oar 3K3 8 SIL 3K3 8 SIL EMCFILTER us La sn MC68340PV C24 GND 100 vec vec vec vec vec vec vec vec 9 9 9 9 9 9 9 C25 C26 C28 c29 c30 c32 100 100 100 100 100 100 100 100 GND GND GND GND GND GND GND GND GND FERT lelvedere halford Stroud GL6 8NT 44 0 1453 886000 Fax 44 0 1453885013 Te PLUTO 5C MC68340
71. led by SIM40 Module NAME PIN VO FUNCTION 24 123 To I O Expansion Connector P14 Pin b1 3K3 pull up amp PAS O GZ PA1 A25 IACK1 122 To I O Expansion Connector P14 Pin b2 3K3 pull up amp PRINS LE PA2 A26 IACK2 121 To I O Expansion Connector P14 Pin b3 3K3 pull up amp l Dae 27 120 To I O Expansion Connector P14 Pin b4 3K3 pull up amp EE E 777767 PA4 A28 IACK4 117 To I O Expansion Connector P14 Pin 05 AKO pull up PISS 17 O Celine RTO Usd and EPROM UST PA5 A29 IACK5 116 To I O Expansion Connector P14 Pin 66 3K3 pull up amp eor KZ SDA line to RTC U40 E PROM 037 6 115 Drives S1 on SFX Channel 2 039 pull up 8 MPX Lamp Current Sense Input PA7 A31 IACK7 114 Drives 52 pin on SFX Channel 2 039 3K3 pull up amp MPX Lamp Short Circuit Sense Input PBO MODCK 87 O Drive LOW to initiate hardware reset PB1 IRQ1 CS1 PB2 IRQ2 CS2 2 O 51 __ _ S O 3 O CS2 MapsFPGAregistersandVO PB3 IRQ3 4 Vmetercurrentsenseinput PB5 IRQ5 8 VO Tol O Expansion Connector P14 Pin b15 3K3 pull up PB6 IRQ6 9 VO Tol O Expansion Connector P14 Pin 516 3K3 pull up PB7ZIRQ7 10 1 IRQ7 NMI input from Power Fail Detection Circuit BARE CS0 AVEC CS0 Ma
72. mmed immediately after Reset and prior to any function or subroutine calls because until they are CS1 will not be active and therefore it will not be possible for the processor to access RAM Example code for setting up the 4 pairs of Chip Select Base and Mask registers is given in Module except asm 6 4 2 3 Periodic Interrupt Timer The sim40_m c Module in the Sample Software sets this timer to provide a high priority 1mS interrupt which is normally used by the software to provide basic system timing This function is controlled by the PICR and the PITR Document 80 15744 Issue 5 HEBER LTD 8 6 4 2 4 Clock Synthesiser Control The SYNCR controls the operation of the main processor clock The MC68340 is provided with a 32 768KHz reference to which the main clock is phase locked After reset the main clock defaults to 8 39MHz The maximum clock frequency of the standard MC68340 is 16 77MHz 6 4 2 5 System Protection The SYPCR controls the bus monitors and software watchdog Other safeguards in the design give adequate protection against programme malfunction as a result of noise etc The Software Watchdog feature is disabled however it could be used if required The Bus Monitor should be enabled and may be left set at its default of 64 clock cycles time out 6 4 2 6 SIM40 Module Pin Allocations Pins under the control of the SIM40 module are allocated as follows Table 1 Allocation of MC68340 Pins Control
73. nt Number Rev 56 15741 72 te Tuesday August 12 2003 Sheet 8 of Document No 80 15744 Issue 5 HEBER LTD 52 Figure 9 Schematic Sheet 9 Connectors I O 1 24 1 0825 26 AZ Ad 81 B2 28 42 82 83 GE OP30 A Ba 2 AB 4 BS 0283 vec 4 A6 B8 05 AT Ae 86 8_ OP39 N20 TTL I O DS ben BB B9 OPT 12 LR O 15 1 0 8 SIL OP42 8 B9 OP44 A11 11 11 0 45 P12 2 U30 GND ifa A13 B13 DB 18 4 2 GND A13 B13 GND D Qo P20 B14 E l 5 4 3 zA Al ais pasi 11 100 15 so a2 4 24 16 215 815 B16 E 8 50 GE 1 5 IP26 17 17 27 2 12 14 6 17 B17 7892 Q4 ESO 18 18 1P29 15 7 E
74. o 5 has been lost 3 The General Purpose TTL outputs and external Bus on connectors P12 8 P13 have been remapped Document 80 15744 Issue 5 HEBER LTD 2 5 CIRCUIT SCHEMATIC DESCRIPTION This section is a walk through of the Pluto 5 Casino Controller board 56 15741 circuit schematics Figures 1 13 of this document A detailed description is given in Section 4 CIRCUIT OPERATION 5 1 Sheet 1 This sheet shows the interconnection between the remaining sheets of this drawing 5 2 Sheet 2 This sheet shows the following items e Motorola MC68340 Processor Pull up resistors on Address Bus Data Bus and other Control Signals e Push Button Switch SW3 P16 BACKGROUND DEBUG connector 5 3 Sheet 3 This sheet shows the FPGA 5 4 Sheet 4 This sheet shows the following memory related circuits Sockets for 1 or 2 EPROMs U1 and U2 64Kbytes Battery backed RAM U4 P15 MEMORY EXPANSION connector for plug in Memory Cards 5 5 Sheet 5 This sheet shows the following sound related circuits e Standard Sound Channel 1 U8 OKI MSM6585 Optional Sound Channel 2 039 OKI MSM6585 TDA7057AQ Stereo Audio Amplifier e P10 LS connector for loudspeakers 5 6 Sheet 6 This sheet shows the 64 Open Drain Outputs 63 5 7 Sheet 7 This sheet shows the following circuits External inputs IPO 31 e Two 8 way DIL switches SW1 and SW2 Document
75. ps ROM both on board U1 U2 and on Memory Expansion Connector via FPGA Document 80 15744 Issue 5 HEBER LTD 9 6 4 3 DMA Controller Module The DMA Module provides 2 DMA Channels On the Pluto 5 these are used for sending sound data from the Programme Memory to the OKI MSM6585 Sound Chip s DMA Channel 1 is used to send data to Sound Channel 1 which is fitted as standard to the Pluto 5 Board DMA Channel 2 is used for the optional add on Sound Channel 2 if fitted 1C39 The DMA channel should be set to work in following modes External request Dual address Source address incrementing Memory Destination address not incrementing FPGA sound register Transfer size byte Interrupt on completion Pins controlled by the DMA module are allocated as follows Table 2 Allocation of MC68340 Pins Controlled by DMA Module PIN NO WO FUNCTION DREQ1 16 SFX Channel 1 DMA request DACK1 15 Noconnection DONET 14 IO pull up DREQ2 13 j SFXChannel2DMArequest DACK2 12 O i DONE2 11 10 Not used 3K3 pull up 6 4 4 Serial Module The Serial Module provides Asynchronous Comms on 2 Channels Channel A and Channel B It is functionally very similar to the 1681 68681 range of DUARTS Channel A is buffered to RS232 levels and connected to connector P1 Signals RX TX RTS and CTS are provided Channel B is buff
76. reading the memory locations as described in Section In most applications these inputs should be debounced in software A typical debounce algorithm might be to read the switches every 1mS but only register a change of state on the input after it has been stable for 3 consecutive readings It is possible to implement say a 64 multiplexed switch input array by using 8 of the Open Drain Outputs 63 as strobes and 8 of the Inputs IPO 31 In this case a diode would need to be connected in series with each switch Document 80 15744 Issue 5 HEBER LTD 24 7 4 Interfacing to Coin Note Acceptors Most Coin or Note Acceptors have open collector sink to ground outputs These may be connected directly to any of the Pluto 5 Inputs 1 0 31 Mechanism Enable or Control inputs may usually be driven directly from any of the Pluto 5 Open Drain Output lines 63 7 5 Interfacing to Coin Payout Mechanisms Payout Hoppers that require relatively low drive currents e g Coin Controls Universal Hopper may be driven directly from an Open Drain Output Higher current devices such as 50Vac or 24Vdc Payout Solenoids should be driven using Open Drain Outputs via a suitable Triac or Relay Interface Card Heber produces a number of suitable interfaces 7 6 Driving Vacuum Fluorescent Displays VFD The standard VFD Linewriter display used in most Gaming Amusement Machines is driven by 3 TTL level signals
77. riod The duration of the period that the first bit is applied for may be set in units of 1 16 mS The multiplex is software driven Every 1mS data for the next strobe is written to the FPGA which in turn formats and serialises the data before clocking out the MPX1 data to the on board 4094 shift registers U18 U19 U20 U21 U35 U36 The exact format of the data to be written each millisecond is determined by the design of the FPGA being used but in general it is as follows 32 bits of MPX1 Row Segment data First period data 32 bits of MPX1 Row Segment data Second period data 4 bits defining Column Digit strobe number to activate 4 bits defining First Period duration units of 62 5uS Consult the User Manual of the actual FPGA in use for exact details of operation 6 16 Multiplexed Lamp Current Sense A facility is provided to allow the processor to check the 256 128 possible lamp positions of MPX1 to determine alight bulb present b Is there a short circuit in this position This facility is intended to be run at power up and perhaps as a production test The facility cannot be used during normal operation of the machine A resistance of approximately 24mQ is implemented as a copper track on the PCB between common source connection of all the Lamp Column LED Digit sinks Q35 50 and Gnd see Schematic Sheet 11 The voltage across this resistor is compared against 2 thresholds formed by resistor chain R124 R125 and
78. ss Lines in 2 27C801 Mode 68340 Address Bus EPROM Address Not Used in 16 Bit Mode Thus for example addresses will be translated as follows so the contents of the EPROM must be re arranged to compensate Table 9 Re Mapping of EPROM Contents in 2 27C801 Mode 68340 Access Address Will Read From This Location in EPROM 0000 0000 0000 0000 0000 0002 0000 0004 0000 0004 0000 0008 ae p d 000 FFFE 000F FFFA 0010 0000 Ed E I Document 80 15744 Issue 5 HEBER LTD 14 6 8 Memory Expansion Various optional memory cards may be fitted to the Memory Expansion Connector P15 Seven lines from the FPGA are included along with 16 data lines and 21 address lines The default functionality of the FPGA lines allows memory cards fitted with up to 4 EPROM or FLASH devices to be accommodated along with a pair of RAM devices with no additional mapping components If a memory card is fitted with 5V FLASH devices then Write facilities are available EPROM Autoselect is also available with devices fitted on a Memory Card 6 9 Open Drain Outputs OP0 63 A block of 64 Open Drain Outputs OPO 63 are provided by 8 off TPIC6259 devices U22 U29 see Figure 6 Schematic Sheet Open Drain Outputs These are memory mapped as the least significant byte of a block of 8 words of address space The chip select for these devices CS OP is provided by the FPGA Consult the User Manual of
79. st signal to the processor Sound data is transferred a byte at a time 1 byte 2 4 bit sound samples to the appropriate register within the FPGA by the DMA Module if a sound is being played The FPGA in turn presents alternately the high and low nibble to the MSM6585 OKI chip The sound channel requests a byte of data via the FPGA at half the sound sample rate E g if the MSM6585 has been set to run at 16KHz sample rate the FPGA will issue DMA requests at 8KHz These requests are issued continuously to the DMA Module but in times of silence the DMA channels are inactive and therefore no new data is transferred into the FPGA sound register In this case the user must ensure that the last data written to the FPGA sound register before a period of silence is 0x80 This will ensure that during a silent period the MSM6585 is being continuously fed a repeated sequence of alternate 0x8 and 0 0 nibbles This keeps the ADPCM converter in its quiescent state If the sound data is generated using the Heber Sound Solutions software the last byte of the data is always 0x80 so this condition will automatically be satisfied Sound Channel 1 U8 is fitted as standard and uses DMA Channel 1 Sound Channel 2 U39 is optional and uses DMA Channel 2 The RESET pin of each channel is under individual software control Pin PORTAO drives SFX Channel 1 RESET Pin PORTA1 drives SFX Channel 2 RESET After Power Up these pins will default to being inp
80. th a diode in series with each switch with the strobes generated using a number of the Open Drain Outputs OPO 63 described above The 32 inputs are mapped as shown in the following table The top 4 bits of each word are read as 175 and bits 8 to 11 contain the DIL Switch Settings as described in the next section The base address is defined by the FPGA Table 11 Mapping of Inputs 0 31 qc Dosen Ie De AZE Df5 12 0114 EA OxF IP31 iP30 1 29 1028 27 1 26 IP25 24 DIL SW _ P22 P21 120 Pe P7 P Bases2 Pis Pm Po 68 Base ox x Ps 2 ier Document 80 15744 Issue 5 HEBER LTD 16 6 12 DIL Switches The Pluto 5 board is equipped with two 8 way DIL Switches SW1 SW2 These are read at the same addresses as the 32 Inputs see preceding Section Table 12 Mapping of DIL Switch Inputs 07 00 om om 68 6 13 Software Controlled Indicator LED LD2 is a green LED that may be turned on or off under software control see Schematic Sheet 9 The LED may be used to provide an indication that software is running or perhaps for fault diagnosis The PORTA2 line from the MC68340 SIM40 Module drives the LED After reset the PORTA pins are high impedance and pulled high by resistor ne
81. the FPGA being used for exact mapping Please note that the chips are bit wide not byte wide Thus Bit 0 of each word drives one device U22 Bit 1 drives U23 etc Table 10 Mapping of Open Drain Outputs 63 to TPIC6259 Devices Bit D7 D6 D5 D4 D3 D2 D1 DO Pin U29 U28 U27 U26 U25 U24 U23 U22 Adar 8 Q1 0 15 13 0 12 oP11 9 Base 2 ore 065 4 2 OPO Basically the drive capability of these devices is 250mA per output continuous with all outputs ON If less than 8 outputs are ON in any one package or any outputs are operating with a small load the capacity of the other outputs increases For example at 25 C the TPIC6259 can sink 400mA continuously from 3 outputs Please refer to the data sheet for the TPIC6259 tpic6259 pdf for details When allocating any output to a load greater than 250mA consideration should be given to the loading on each device See Section 5 1 Driving Reels for details on driving standard reel mechanism stepper motors Note also that because they are MOSFETs the outputs are resistive lt 2Q and do not suffer from the minimum saturation voltage of about 1V which would be the case if they were darlingtons Therefore at low currents they pull down close to Gnd and may be safely used to drive TTL Inputs Switch Strobes Coin Mechanism Enables etc Document 80 15744 Issue 5 H
82. tor LM339 U16B on Schematic Sheet 9 When the 12V input falls below a threshold of approximately 7 8V the output of the comparator goes low which causes a Level 7 interrupt NMI to the processor This will occur BEFORE the 7805 regulator drops out of regulation and the Vcc line starts to drop thus giving the processor a period of time to react before the RESET is asserted by the TL7705 U17 The main purpose of giving the Document 80 15744 Issue 5 HEBER LTD 6 processor the NMI advance of the RESET is to avoid the risk of an incomplete RAM write operation occurring if the RESET were to be asynchronously asserted while such an operation was being carried out The time available between the assertion of NMI and the assertion of RESET will depend on the rate of fall of the 12V line which will obviously be dependent upon the power supply and the loading on the 12V but will typically be several milliseconds 6 3 Primary Battery Backup A backup battery BT1 is provided Schematic Sheet 10 to allow the two RAMs U3 and U4 to retain data while the board is powered down and to keep the optional Real Time Clock chip U40 running BT1 two cell rechargeable NiMH Nickel Metal Hydride battery capacity 70mA hr The circuit comprising BT1 Q2 43 R132 provides the battery trickle charge and switchover of the secured power supply rail Vbatt While Vcc is at 5V current flows through the base emitter junction
83. twork N11 This signal passes through the inverter U7F which thus turns ON the LED Therefore initially and with no action on the part of the software the LED will be ON indicating that Vcc is present If the software sets PORTA2 pin as an output and drives it low the LED will go OFF The PORTA pins are taken to the I O Expansion Connector P14 Future Expansion Cards may use the PORTA2 pin for some other function in which case this will have to be taken into consideration when operating the indicator LED 6 14 On board Push Button A Push Button Switch SW3 is provided on the board see Schematic Sheet 2 The function of this switch is at the discretion of the user of the board It is connected so as to pull the line from the MC68340 5 40 Module to GND when operated The PORTA pins are taken to the Expansion Connector P14 Future Expansion Cards may use the PORTAS pin for some other function in which case the possible interaction with SW3 will have to be taken into account 6 15 Multiplexer The Pluto 5 Casino Controller provides hardware assistance within the FPGA to the Processor allowing a single 32 16 Multiplex Array MPX1 to be controlled The Pluto 5 Casino Controller has 1 2 of MPX1 configured as a 16 16 256 Lamp Drive Array and the other 72 configured as a 16 16 32 seven segment digits LED Drive Array The Lamp Multiplex Drive Circuitry is designed to drive 12V 100mA bulbs However
84. um and 68340um ad2 pdf The MC68340 contains the following functional blocks CPUS2 68020Based Processor Two Channel DMA Controller Document 80 15744 Issue 5 HEBER LTD 7 6 4 7 CPU32 Processor Module CPU32 is a processing core which is basically 68000 code compatible but with a number of enhancements For full details of operation please refer to both the Motorola MC68340 User Manual and the Motorola M68000 Family Programmers Reference Manual see Adobe Acrobat File 68kprm pdf All modern 68000 Compilers and Assemblers have various options for the target CPU When generating code for the Pluto System the CPU32 option should be used If the Compiler Assembler is old it is possible that it may not have a CPU32 option In this case the Compiler if used should be run with the 68000 option set The assembler may be run in 68020 mode which will allow the use of the MOVES command which is required during initialisation to set up the Module Base Address Register MBAR in the MC68340 Care must be taken not to write code that calls any other 68020 instructions that may not be implemented on the CPU32 The Pluto 5 Development Kit includes a suitable C Compiler and Assembler 6 4 2 SIM40 System Integration Module This module controls various aspects of the operation of the processor such as configuration clock external bus etc When used in the Pluto System the main considerations in the us
85. uts and therefore the Resistor network N11 will pull them High holding both Sound Channels in a RESET state Before the Sound Channels can be used these two pins must be set as outputs by the SIM40 6 18 Stereo Amplifier and Volume Controls The Stereo Amplifier is shown on Schematic Sheet 5 Document 80 15744 Issue 5 HEBER LTD 19 032 is a Philips TDA7057AQ Stereo Audio Amplifier with independent DC volume controls Note that the loudspeaker outputs on Connector P10 are bridge driven so neither of the loudspeaker wires may be connected to Gnd The DC volume controls of the TDA7057 work over the range 0 4V min to 1 2V Max The variable duty cycle outputs on pins TOUT1 2 from the two timers in the MC68340 Timer Module are integrated by the combination of two 3K3 resistors and a 1uF capacitor R108 R109 C45 on Channel 1 R110 R113 C46 on Channel 2 to provide the control voltage needed The control voltage is given by the formula 2 5 duty cycle where duty cycle is the proportion of the time that the TOUT Pin is HIGH Normally Sound Channel 1 U8 DMA Channel 1 feeds Amplifier Section 1 volume control Timer Channel 1 driving LS1 Sound Channel 2 U39 DMA Channel 2 feeds Amplifier Section 2 volume control Timer Channel 2 driving LS2 A pin on the Loudspeaker Connector P10 pin 3 which allows the output signal from Amplifier Channel 1 to be fed back into the input of Amplifier Channel 2 This allo
86. ws various alternative modes of operation for example if only Sound Channel 1 is fitted then by linking the LS1 output to the feedback pin the same signal can drive BOTH loudspeakers See Section Making Sounds below for a more detailed explanation of the different operational modes that are possible 6 19 Serial P1 provides connections to RS232 Channel A Data Receive amp Transmit plus RTS CTS P2 provides connections to RS232 Channel B Data Receive amp Transmit plus RTS CTS and is in the format specified by the BACTA standard Operation of the above two ports is determined by the operation of the Serial Module in the MC68340 Processor Refer to the Serial Module Section of Motorola MC68340 User Manual for a full explanation 6 20 Internal Bus An internal Bus is implemented using SIM40 Lines 4 SCL and PORTAS SDA This bus allows the processor to read and write the optional Real Time Clock chip U40 and the optional E PROM 037 If neither of these devices is fitted then these 2 lines are also available on the I O Expansion Connector P14 and are free for other uses 6 20 1 Real Time Clock 040 is a position that accepts a Philips PCF8583 Real Time Clock The standard Pluto 5 Casino Controller has a socket fitted in this position along with the 32 768KHz Crystal X2 However the PCF8583 IC is NOT fitted as standard but is available as an optional extra or may be fitted by the user The

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