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AW-NH580 - AzureWave

1. Bluetooth L Full compliance with Bluetooth specification version 4 0 including Bluetooth Low Energy Fully supports Bluetooth Core Specification version 2 1 2 0 EDR and 3 0 features ired by wireless InsP 2 e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f q S nti 0 is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document AzureWave A AzureVWave Technologies Inc www dZUrewave com FM True worldwide FM band support 70 108 MHz for US Europe and Japan for wire antenna with single application Embedded loop antenna support for FM TX RX FM TX on dual FM channel with RDS AF list for robust FM transmission R B DS modulator demodulator and encoder decoder compliant with EN 621 FMline level analog stereo output available NA GPS S Advanced proprietary multipath algorithms for robust low t tracking in indoor and outdoor urban canyons Xx 2 GSM WCDMA and CDMA control plane aGPS assis qe Standards Exceeds 3GPP and TIA performance requireme S L SUPL user plane aGPS assistance data 14 search and three track channels used ack up to 47 individual satellite signals Measurement engine with a search capa deed correlators
2. Inc Table 2 4 14 Low power clock WWW OZUrewave com Symbol Parameter Condition Min Typ Max Unit Square wave V 0 7 Vi V Vipo_clk LPO clock voltage Square wave Vj 0 0 2 V Vi Input Hysteresis voltage ETE V Ipo_Hys VpDio Fipo_clk LPO clock frequency 32 768 kHz LPO clock frequency Fipo_acc a 250 250 ppm 2 butycycle LPO clock duty cycle 30 70 96 Standard deviation of litter Short term jitter 1000 consecutive 25 25 ns periods y Table 2 4 15 System clock input SYS_CLK Fat Symbol Parameter Condition Min Typ Max Unit i Input capacitance on Cosc in SYS CLK 4 7 pF Stabilization time for Tsys_stability input clock in number of 65535 cycles system clock cycles Tsys_start Turn on time SH T9 Ppnvertinel 100 us freq Tsys_stop Turn off time peso power down 50 ns System clock voltage Vsys_clk swing Square or sine 0 4 VDD_TXCO Vpp wave Fsys clk System clock frequency 19 2 19 8 24 26 38 4 52 MHz System clock frequency Fsys acc accuracy 3m 99 PES 1Hz 55 dBc Hz 10 Hz 83 dBc Hz 100 Hz 108 dBc Hz PhiN Phase Noise 1 kHz 130 dBc Hz 10 kHz 146 dBc Hz 100 kHz 148 dBc Hz Fora TCXO with frequency of 26 MHz Noten clock output SYS CLK OUT N Symbol Parameter Condition Min Typ Max Unit Fsys clk System clock frequency 19 2
3. The principal function of the host software is to perform satellite navigation A calculations N y wireless 2 e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f q S nti 0 is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document www dZUrewave com A AzureWave AzureWave Technologies Inc Block Diagram A simplified block diagram of the AW NH580 module is depicted in the figure below AW NH580 VBAT 3 6 4 8V VDDIO 1 65V 1 95V ST Ericsson E 4 GH ILAN a paite CW1100 2 4GHz WLAN BT Antenna SDIO SPI for WLAN FM TX Antenna FM RX Antenna n GPS Antenna UART for BT FM GPS PCM I2S for BT FM Analog Line out for FM RX I2S for BT FM ST Ericsson CG2900 y wireless pired b Ins e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f j q e nti e is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document www dZUrewave com p Azure
4. A3 4 275 2 375 SDIO DATAS SPI_CSN A4 4 275 1 425 SDIO_CMD SPI_DI A5 4 275 0 475 GND A6 4 275 0 475 VDDIO W A7 4 275 1 425 GND A8 4 275 2 375 FM_ANT A9 4 275 3 325 FM_WANT A10 4 275 4 275 GND B1 3 325 4 275 ANT_2G4 B2 3 325 3 325 GND B3 3 325 2 375 SDIO_DATA1 WIRQ B4 3 325 1 425 SDIO_CLK SPI_SCLK B5 3 325 0 475 GND B6 3 325 0 475 AUDOR B7 3 325 1 425 AUDOL B8 3 325 2 375 GND B9 3 325 3 325 GND B10 3 325 4 275 VDD_CORE C1 2375 4 275 GND C2 2 315 3 325 GND C3 2 373 2 375 SDIO DATAO SPI DO C4 2 375 1 425 GND c5 2 375 0 475 PDB COUTE SE 375 0 475 GND C7 2 315 1 425 GND c8 2 375 2 375 UART CTS 2 C9 2 315 3 325 UART RTS 3 C10 2 375 21275 VDD FM PA D1 1 425 4 275 1 8V_WLAN D2 1 425 3 325 GND D3 1 425 2 375 GND D4 1 425 1 425 EXT DUTY CYCLE 19 y wireless inspired b E e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and 9 a f q e n i q is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document 46 E AzureWave AzureWave Technologies Inc WWW OZUrewave com 1 425 0 475 D6 1 425 0 475 EXT FRM SYNCH 20 D7 1 425 1 425 GPS ANT SEL TP2 D8 1 425 2 375 UART_TXD_ 4 D9 1 425 3 325 UART_RXD_ 5 D10 1 425 4
5. Rxyport 2 sega 16 bits or 32 bits Rx port 3 Audio lo channel 16 its Rx port 4 4 b cad channel 0 Tx port T f Speech channel 1 Tx port 6 NO Audio transmit channel 16 bits or 32 bits Tx port Audio transmit channel 16 bits Tx port qv Bi directional port for asynchronous channel 0 HCI Tx in full half duplex VS 9 Bi directional port for asynchronous channel 1 HCI Rx in full duplex Bi directional port for asynchronous channel 2 10 GPS Rx in half duplex GPS Tx in half duplex pired by wireless Ins 2 e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f q e nti 0 is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document 16 A AzureWave AzureWave Technologies Inc www azurewave com The FM TX or BT A2DP burst mode is supported mapping the audio stereo channel to a SLIMbus channel at a maximum segment rate of 500 kHz The data flow can be controlled in two ways to average the data throughput to the real sample rate 1 Use the segment presence bit to indicate which segments in the 500 kHz stream carry data 2 Pausing the bus Please note that in case 1 the bus may also be paused when there is no da
6. 275 VDDIO_G E1 0 475 4 275 1 8V_GBF E2 0 475 3 325 GND E3 0 475 2 375 GPS LNA EN TP1 E4 0 475 1 425 GND E5 0 475 0 475 HOST WAKE 11 E6 0 475 0 475 GND E7 0 475 1 425 12S WS 13 E8 0 475 2 375 I2S DIN 15 E9 0 475 3 325 GND E10 0 475 4 275 VOUT F1 0 475 4 275 VBAT_DUT_W F2 0 475 3 325 WRESET F3 0 475 2 395 CLKREQOUT2_TP4 F4 0 475 1 425 FE_LDO_EN F5 0 475 0 475 GND F6 0 475 0 475 GND F7 0 475 1 425 12S CLK 14 F8 0 475 2 375 I2S_DO_ 12 F9 0 475 3 325 PCM B 6 F10 0 475 4 275 VBAT DUT G G1 1 425 4 275 GND G2 1 425 3 325 SYS CLK REQ IN G3 1 425 2 375 GND G4 1 425 1 425 GND G5 1 425 0 475 GND G6 1 425 0 475 GND G7 1 425 1 425 GND G8 1 425 2 375 PCM_A 9 G9 1 425 3 325 PCM_CLK 8 G10 1 425 4 275 GND H1 2 375 4 275 GND y wireless inspired P e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document Confidential 47 E AzureWave AzureWave Technologies Inc WWW OZUrewave com 2 375 3025 SYS_PWR_REQ 10 H3 233 2097 GND H4 2 375 1 425 PTA STATUS 1 H5 2 375 0 475 PTA_FREQ 16 H6 2 509 0 475 LPO CLK MB H7 2 375 1 425 EXT_REF_CLK_CG2900 H8 2 375 PBA PCM SYNC 7 H9 2 905 3 325 GND H10 239
7. Azurewave and the information you are viewing now is strictly confidential and C 9 n f q e nti a is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document 40 A AzureWave AzureWave Technologies Inc www azurewave com 2 8 2 GPS BT FM Reset cold start and start up 2 8 2 1 Reset conditions The device is reset cold start from the following conditions e Power on start up After applying the power supply voltage nothing happens as long as the PDB pin is kept at low level 0 When the PDB pin goes to high level 1 the reset condition is met This powers e device and causes a power on reset gt e PDBpin The PDB pin can be used to asynchronously reset the device e Watchdog timer 2 8 2 2 Start up conditions ion 1 7 2 When the system starts up it goes through a power on reset where the syste ackis requested by both the Figure 2 4 16 presents the device start up phases as describ stable system clock by counting a number of cloc ilst the system is still kept in reset Once the system clock is stable a synchronous reset for a fixed number of system clock cycles keeps the System in reset until the system is ready 1d goin the System Enable state In System Enable state the device ayto tically detects the
8. Programmable pin CLKREQOUTN 1 0 F4 FE_LDO_EN Enable the GBF internal LDO to generate 1 8V from VBAT_DUT_G l F5 GND Ground F6 GND Ground FY 12S CLK 14 GBF IIS CLK 1 0 F8 12S DO 12 GBF IIS DOUT 1 0 F9 PCM_B 6 GBF_IOM_DIN VO F10 VBAT_DUT_G Battery supply Regulator input 3 6 V l G1 GND Ground G2 SYS_CLK_REQ_IN System clock request input Only used for test purpose NC l G3 GND Ground G4 GND Ground G5 GND Ground G6 GND Ground G7 GND Ground G8 PCM A 9 GBF IOM DOUT 1 0 G9 PCM CLK 8 GBF_IOM_CLK 1 0 InsP Confidential ired bY wireless e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document www dZUrewave com A AzureWave AzureWave Technologies Inc a NN EN Ground H1 GND Ground Power mode request to wake up external PMU Only used for test H2 SYS PWR REQ 10 purpose NC 1 0 H3 GND Ground H4 PTA_STATUS 1 e cee pin WB_PTA_STATUS Only used for test purpose oO H5 PTA_FREQ 16 PES pin WB_PTA_FREQ not connected Only used for test oO H6 LPO_CLK_MB Low power clock input l H7 EXT_REF_CLK_CG2900 GPS cellular clock H8 PCM_SYNC_ 7 GBF_IOM_TFS 1 0 H9 GND Ground H10 GND Ground Ji GND Ground J2 GND Gr
9. for legal actions against any loss suffered or expenditure due to the misuse of any information form this document www dZUrewave com A AzureWave AzureWave Technologies Inc 3 Pin Definition 3 1 Pin Description PIN No Name Description Type Al GND Ground Programmable pin SDIO DATA HIF The state of this pin is monitored on the rising edge of WRESETN A2 SDIO_DATA2 HIF L LOW selects SPI V0 HIGH selects SDIO A3 SDIO DATAS SPI CSN Programmable pin SDIO_DATA3 SPI CSN V0 A4 SDIO CMD SPI DI Programmable pin SDIO CMD SPI DI V0 A5 GND Ground A6 VDDIO W General Purpose IO supply 1 8V l A7 GND Ground l A8 FMANT FM TX antenna output port 50 Ohms 0 A9 FM WANT FM Rx antenna input port 50 Ohms need to series L 150nH Q gt 30 VO A10 GND Ground B1 ANT 2G4 Antenna IO port for Bluetooth and WLAN 50 ohms 2 4GHz band I O B2 GND Ground B3 SDIO_DATA1 WIRQ Programmable pin SDIO DATA1 WIRQ VO B4 SDIO CLK SPI SCLK Programmable pin SDIO_CLK SPI_SCLK I O B5 GND Ground B6 AUDOR FM Rx analog audio output channel Right DC Block Capacitor Required O B7 AUDOL FM Rx analog audio output channel Left DC Block Capacitor Required O B8 GND Ground B9 GND Ground l B10 VDD_CORE ds AE analog supply BT Power Amplifier supply FM C1 GND Ground C2 GND Ground C3 SDIO DATAO SP DO Programmable pin SDIO DATAO SPI DO I O C4 GND Ground C5 PDB GBF LDO power down input l C6 GND Ground C7 GND Gr
10. suffered or expenditure due to the misuse of any information form this document A AzureWave AzureWave Technologies Inc www azurewave com Table 2 4 6 PCM master timings Symbol Parameter Min Typ Max unit Tps FSC_IP high time one z NOOK ns T24MHz T24MHz Tch DCLK IP high time 4XT24MUz 96xT 4MmHz ns Tcl DCLK IP low time 3xT24MHz 96XTo4uuz ns Tjit DCLK IP jitter Ton ns T24MHz Tdps Delay from DCLK IP rising edge to FSC IP edge 50 ns Tddo Delay from DCLK IP rising edge to Dataout transition 50 ns Tdzdo Delay from DCLK IP rising edge and Dataout High Z i 50 h to Dataout valid Tddoz Delay from DCLK IP rising edge to Dataout High Z 50 ns Thdi Hold time from DCLK_IP falling edge to Datain 50 i s transition Tsdi set up time of Datain to DCLK_IP falling edge 50 ns 1 T24MHz is one 24 MHz period 41 66 ns y 2 max DCLK_IP high low time and FSC IP high time correSport DCLK IP at 128 kHz 3 min DCLK IP high low time and FSC IP high time coges ponds to DCLK IP at 3072 kHz 2 4 3 Second I2S interface This second 12S interface is a synchroneus sefial interface used for the transfer of voice audio samples with full duplex capabilities BT or h ex The 12S interface can also be use audio interface when the AW NH580 is running the BT A2DP nnig BT Wideband speech or FM stereo transmission or reception in the AW NH580 the left channel while a high le
11. system clock frequency and enables the UART SPI and SLIMbus HCI interfaces A automatic detection on these interfaces is then performed to select the one used by the Host O HCI interface has been detected the device goes into the System Active state In System Active stat and ARM SS an active or in po has to configure the device further This is to download patch file BT ettings file Following reset by default GPS and FM are in power down BT is ending on the static settings file The different device subsystems GPS BT and FM c e enabl d or disabled separately As long as ene e device subsystems GPS BT and FM is enabled and active the device stays in the m ve state When all the device subsystems GPS BT and FM are disabled or in low power mode the device goes into the System Deep Sleep state In System Deep Sleep state only the low power clock is used and the power supplies are managed to reduce the power consumption Waking up from the System Deep Sleep state can be triggered from an internal device event e g BT Sniff beacon or by the Host via one of the different HCI or GPS wakeup mechanisms ed by wireless inspi e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f j q e nti a is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss
12. 0 65 VDDIO V VoL Low level output voltage 100 pA 0 0 2 V Vou High level output voltage 100 pA VDDIO 0 2 VDDIO V y wireless pired b Ins gt e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f q e nti 0 is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document A AzureWave AzureWave Technologies Inc 2 4 GPS BT FM Host Interface The AW NH580 is the optimal solution for any voice or data application that requires the Bluetooth SIG standard Host Controller Interface HCI using a high speed UART The GPS subsystem the FM subsystem and the Bluetooth subsystem share the same high speed UART WWW OZUrewave com 2 4 1 UART Interface ND The implemented UART interface is an asynchronous serial interface used for the GPS BT FM control and data transfer SN Features The following features are supported e 1 bit start generation NS e 8 bits character size NS e 1 bit stop generation e No parity generation and detection e Programmable standard baud rates from 38 4 PN for fast data transfer from 2 5 MBaud up td 4 92 MBaud e Automatic line error checking stop bitfailure framing RX overrun and break e RTS CTS hardware handshak
13. 52 MHz 1Hz 55 dBc Hz 10 Hz 83 dBc Hz 100 Hz 108 dBc Hz PhiN Phase Noise 1 kHz 129 dBc Hz 10 kHz 142 dBc Hz 100 kHz 146 dBc Hz 1 Fora TCXO with frequency of 26 MHz meeting the conditions of Table 2 4 15 red by wireless Insp e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document Confidential A AzureWave AzureWave Technologies Inc www azurewave com 2 8 Reset and Regulator Control Signaling 2 8 1 WLAN Power up power down Reset and power up The device is able to start up without the reference clock being present The chip shall request it through the use of one of the CLKREQOUTx signals The platform is than expected to provide a stable clock within Tstable ms unless the built in XTAL oscillator is used A valid reset shall be obtained by maintaining WRESETN active low for at least two cycle K after VDDIO is stable within it operating range There is no constraint on the activati as er supplies during this process The reset is propagated to the core during the sta sequence described below A typical startup for the WLAN system is as follo
14. 8 rising edge to SDI I2S 50 hs transition Tsdi set up time of SDI_I2S to SCK 128 rising edge 50 ns 1 MaxSCR 12S and WS _12S high low time corresponds to SCK 12S at 128 kHz 2 Min SCK 12S and WS_12S high low time corresponds to SCK_I2S at 3072 kHz 3 T24MHz is one 24 MHz period 41 66 ns ed by wireless inspi 2 e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f q e nti a is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document 26 A AzureWave AzureWave Technologies Inc www azurewave com Figure 2 4 8 I2S slave timing Tus me T gt WS _I2S Tras Ts T Tras SCK_I2S x vx AP SS L Xe 7X LJ X z msb SDO 2 SDI_I2S Table 2 4 10 I2S slave timing ARN Symbol Parameter Min Typ Max unit Twsh Short WS 12S high time 2 Tae 0 0c S Twsl Long WS 2S high time MeTaeua 0c om SCK_I2S high time Taeus2 Trzente 2 ns TH SckK2Stowtime Tents Trame ne Tous set up time from WS 12S transition to SCK_I2S rising pom foe fe edge Th hold time from SCK_I2S rising edge to WS_I2S WS 7A transition ali E a Po ojn 1 Tclkburst is actually expe
15. 95 4 275 GND Ji 3 325 4 275 GND J2 2 225 3 2925 GND J3 3 325 2375 CLKREQIN1_TP3 J4 3 325 1 425 PMU_EN J5 3 329 0 475 PTA RF ACT 17 J6 3 325 0 475 GPS CAL FREQ 18 J7 3 225 1 425 GND J8 2 325 2 375 GND J9 9 325 3 325 TCXO IN MB J10 3 325 4 2775 VDD TCXO K1 4 275 4 275 GND K2 4 275 3325 1 8V_SMPS K3 4 275 23S GND K4 4 275 1 425 VBAT_PWR K5 4 275 0 475 W IRQ K6 4 275 0 475 PTA TX CONF 0 K7 4 275 1 425 GND K8 4 275 2 375 GPS RFIN K9 4 2775 3 325 GND K10 4 275 4 275 GND V y wireless inspired P E e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and 9 a f q e n i q is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document 48 AzureWave Technologies Inc a 4 Mechanical Information 9 6mm AzureWave AW NH580 9 6mm YYWW 9 CHINA XXXXXXXXXXXX Side View J S Dimension Tolerance 0 imm PIN 1 ID e TOP VIEW SIDE VIEW inspired py wireless e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f j q S nti 0 is a knowledge property to Azurewave e Unauthorized use of this document is prohi
16. A AzureWave AzureWave Technologies Inc www azurewave com S AW NH580 SS IEEE 802 11 b g n Wirele Bluetooth GPS and FM C Module Q Ss AV Datasheet o v y wireless inspired b 2 e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f q e nti 0 is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document www dZUrewave com A AzureWave AzureWave Technologies Inc Document m n release Date Modification Initials Approved x A Kai CE Version 0 1 2010 09 06 Initial Version Wu Wena 1 Corrected Model Name in 1 3 Specifications Table NP 2 Corrected General description in 1 2 Kai C Version 0 2 2010 11 11 Huang Key Features 3 Add shipping information red by wireless InsP 2 e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f q S nti 0 is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document A Azure
17. O the TCXO is directly supplied from the VDD TCXO pin and can be controlled by switching on off the VDD TCXO supply Since the range of frequencies supported is wide from 19 2 to 52 MHz the AW NH580 ce input at capability to automatically detect the system clock frequency using the external LPO 32 768 kHz as reference Since the system clock input is AC coupled there is no need for an external ing capacitor as long as the requirements on the voltage swing are met see Table 2 4 15 System clock output VDDIO need to be supplied 2 7 2 Low power clock The low power clock is used to keep the GP nd FM subsystems timing when in low power mode The low power clock is to be provided o low power clock input LPO CLK as a 32 768 kHz square wave clock input This clock is used for the er modes of the WLAN systems After power up the low power clock must be available bef he e et is released It must remain active all the time until the chip is powered off A S inspired py wireless 2 e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f q e nti 0 is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document 38 E AzureWave AzureWave Technologies
18. Portable Navigation Devices vig al ne Digital Assistants PDAs Tracking Devices Gaming Devices and mobile phones whi small footprint package low power consumption multiple OS support By using AW NH54 amp D t omers can easily enable the Wi Fi BT GPS and FM embedded applications with the befefits t high design flexibility short development cycle and quick time to market Compliance with the IEEE 802 11b g n standard the AW NH580 uses D DBPSK DQPSK of the power management functions specified in the IEEE 802 1 a d minimize the system power requirements by using AW NH580 In addition to the supp PA2 personal and WEP Quality of Service QoS For Bluetooth operation the AW NH580 je Blue V1 2 V2 0 V2 1 Enhanced Data Rate EDR V3 0 and V4 0 including Bluetooth lt L rgy compliant The AW NH580 supports extended Synchronous Connections eS far emhanced voice quality by allowing for retransmission of dropped packets and Adaptive uency Hopping AFH for reducing radio frequency interference It provides easier to connegt devices lower power consumption and improved security For FM receiver trans W NH580 is 70 MHz to 108 MHz FM bands supported and supports the European Rad ystems RDS and the North American Radio Broadcast Data System information In a Mobile Phone application the BT link is the medium for PCs telephones PDAs and other peripherals to communicate together on an ad hoc basis The FM subsystem is us
19. Vo data Output data low level 4 om j 20 VDDIO lt 80 o om po Time to Drive Output Data SRpata_ Data Output Slew Rate Tpp Active Driver Disable Time Data terminal input Vindata Input data high level Vitdata Input data low level H Active Input Hold Time erup Active Input Setup Time Data transmission line characteristics d ETTLE Time to settle the DATA line DV Time for Data Output Valid Ho Inspired by wireless e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n j j q S nti a is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document 18 A AzureWave AzureWave Technologies Inc www azurewave com 2 4 2 PCM I2S interface The implemented PCM I2S interface is a synchronous serial interface used for the transfer of voice audio samples with full duplex capabilities The PCM I2S interface can also be used as audio interface when the AW NH580 is running the BT A2DP A standard application may be running BT Wideband speech and or FM stereo transmission reception between the CG2900 and CW1100 in the AW NH580 Interface description ND The POM interface consists of four wires XS e FSC IP is used to synchronize the slave dev
20. Wave AzureWave Technologies Inc 1 3 Specifications Table Specifications are subject to change without notice Model Name AW NH580 Product Description Wireless LAN amp Bluetooth amp FM WLAN Standard IEEE 802 11b g n Wi Fi compliant Bluetooth Standard Bluetooth 2 1 Enhanced Data Rate EDR BT3 0 HS BT4 0 SDIO SPI for WLAN Host Interface UART for GPS Bluetooth and FM Digital PCM I2S for FM Bluetooth Audio Interface Analog line level i o for FM 12S for FM Bluetooth Dimension 9 6 mm X 9 6 mm x 1 3 mm Package LGA package Operating Conditions Input supply for internal PMU 3 8 4 8V Voltage Temperature Relative Humidity Input supply for host I O 1 8 to 3 6V Operating 20 70 C Storage 40 85 C lt 60 storage lt 85 operation Electrical Specifications 2 4 GHz Band WLAN Bluetooth Frequency Range 1575 42 MHz GPS L1 radio band 70 MHz to 108 MHz FM bands 802 11b USA Canada and Taiwan 11 Most European Countries 13 Japan 14 802 119 USA and Canada 11 Most European Countries 13 Number of Channels DSSS OFDM DBPSK DQPSK CCK 16 QAM 64 QAM for WLAN Modulation GFSK 1Mbps 1 4 DQPSK 2Mbps and 8DPSK 3Mbps for Bluetooth inspired py wireless E e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and 0 a f q e n ti q is a knowledge property to Azurewave e Unauthorized use of this doc
21. Wave AzureWave Technologies Inc www azurewave com Table of Contents 1 General Description 1 1 Product Overview and Functional Description 1 2 Key Features 1 3 Specifications Table ND 2 Electrical Characteristic EN 2 1 Absolute Maximum Ratings 2 2 Recommended Operating contre A A 2 2 3 DC Characteristics for Host I O 2 4 GPS BT FM Host Interface lt gt 2 5 Multimedia features 2 6 WLAN interface 2 7 Reset and Regulat r control signaling 2 8 LPO Clock PCLK 2 9 Reset an ulator Control Signaling 3 Pin pennin A 4 Caos scription GA Location TOP View X Y Coordinate 4 Ne ical Information pired py wireless Ins 2 e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f q e nti 0 is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document A AzureWave AzureWave Technologies Inc www azurewave com 1 General Description 1 1 Product Overview and Functional Description AzureWave Technologies Inc introduces the first IEEE 802 11b g n WLAN BT BLE GPS and FM TX RX combo module AW NH580 The module is targeted to mobile devices including Digital Still Cameras DSCs Portable Media Players PMPs
22. ansaction and it remains active for the duration of the transaction The signal RF ACTIVE synchronizes the PTA to the BT slots by occurring a fixed pre defined period before the next BT slot RF ACTIVE will be de asserted by BT as soon as possible at the end of the transaction inspired py wireless e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f j q e nti 0 is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document 35 A AzureWave AzureWave Technologies Inc www azurewave com The STATUS line output from BT and input to PTA is used to signal both the priority of the pending BT transaction and also the RX TX status during the transaction The priority of the transaction is signaled by the STATUS signal for a defined duration after the RF_ACTIVE is asserted The PTA should sample the priority status during this defined window After signaling of the priority the STATUS line may signal the RX TX mode of the BT The FREQ signal output from BT is optional and is asserted when the BT transceiver hops irto the restricted channels defined by the host The signal TX CONFX output from PTA and input to BT is de asserted when the P prevent BT transmission The BT module shall not i
23. ata input FM stereo reception uni directional data output FM stereo reception Stereo uni directional data output BT SCO iris Left ri directional data BT SCO Slave dn Left bi directional data 1 on Stereo 2 BT SCO Master Left 10on bi directional data Stereo Right 1 on Stereo 2 BT SCO Slave Left 10n bi directional data Stereo Right Enabling or disabling the I2S interface usage is done via a host command When disabled the IO state is configurable to high Z state Pull Up Pull Down driven 1 driven O bh rect speech path mode is provided for BT SCO data at 16 kHz 8 kHz For BT A2DP audio data an FM stereo audio data it is provided at 48 kHz or 44 1 kHz BT SCO handling is programmable SCO Channel 0 can be mapped on either left or right 12S channel WS high low In BT SCO handling it supports up to 2 speech channels In FM stereo handling or BT A2DP the Left channel is indicated with WS 12S signal at low level and right channel with WS I2S signal at high level y wireless 2 e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f q e nti a is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document p AzureWave AzureWa
24. been transmitted 6 Master de selects the Slave S d Figure 2 4 13 SPI setup and hold timing i T10 T11 SPI CSN SPI CLK T4 T2 SPI DI 4 MOSI MISO X ired by wireless InsP 2 e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f q e nti 0 is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document 33 www dZUrewave com A AzureWave AzureWave Technologies Inc Table 2 4 11 SPI timing parameters Symbol Description Min Typ Max Unit T1 Clock period 19 230 ns T2 amp T3 Clock high and low duration 0 45 T1 T4 0 55 T1 T4 ns T4 amp T5 Clock rise and fall time 1096 to 9096 1 2 5 ns Input setup time Te SPI_DI valid to SPI_CLK active edge ue 2d Input hold time P T7 5 0 SPI CLK active edge to SPI DI invalid i Output setup time T8 14 23 SPI_CLK active edge SPI_DO valid dd Output hold time T9 5 0 SPI CLK active edge to SPI DO invalid i T10 CSN to clock CSN fall to 4st rising edge 5 0 ns Clock to CSN T11 1 0 Last falling edge of SPI_CLK to CSN rising edge ns 1 19 23 ns 1 52 MHz 2 14 23 ns 19 23 ns 5 ns SS F 2 6 3 FEM control s
25. bited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document 49 A AzureWave AzureWave Technologies Inc www dZUrewave com b Ci00Bal s 009 o 2 0 o Q Qo amp Table 4 1 aCKage dimensions M Reference Min Typ Max Unit 1 2 1 3 14 mm Vy 0 35 0 4 0 45 mm E 9 5 9 6 9 7 mm E1 8 55 mm e 0 95 mm g 0 525 mm Inspired by wireless e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f q S nti 0 k is a knowledge property to Azurewave Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document A AzureWave AzureWave Technologies Inc www azurewave com AW NH580 Top View PCB Layout Footprint Unit mm 0 45 MASK SIZE FN AN CY 7 90 55 PAD SIZE SA fe oN AN l4 ND e X 8 55 VEN lias O f Y FN AN NA 2 L4 Note SRO 350 Sea defined Recommended SRO for customer s PCB is TS Ider mask defined ma inspired py wireles
26. components This filter consists of an inductor and capacitor D FM wire antenna A The AW NH580 supports also an FM wire antenna connected through an induct to RM WANT the inductor value and Q factor is important to reach good sensitivity The FM wi a can be used for FM RX AN 2 5 Multimedia features NJ Thanks to its ultra low power audio DSP the AW NH580 off cient i loading to reduce the Host computation needs and to optimize overall platform pow 2 5 1 Wideband speech support The AW NH580 embeds support of SBC eneedin ecoding for Wideband speech The whole processing is performed internally and d e ire dedicated processing from Host side Raw audio samples 16bit at 16 kHz tkansf rred over PCM I2S or SLIMbus interface and all necessary processing like SBC VS encapsulation in e SCO packets is handled internally is the AW NH580 2 5 2 Direct loop f Rx to BT A2DP link The AW NH58 me he streaming of FM radio over a BT A2DP link without any involvement of the host during the stheaming This leads to a drastic reduction of the power consumptions as the host can sta tin amp ously in sleep mode All the nece sapy processing that is normally done in the host is handled inside the AW NH580 This i SBC encoding and A2DP L2CAP framing d by wireless Inspire 2 e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f q e nt
27. cted to be 16 MHz nominal 20 ppm 2 Other SCK_I2S input frequencies in between f 128 kHz featured by the period T128kHz to 4 8 MHz are actually expected to be f nominal 20 ppm V 2 4 4 Analog audio interface ms Delay from SCK_I2S falling edge to SDO_I2S Tddo transition Tdzd Delay from SCK 25S falling edge and SDO_I2S High 700 IZ to SDO I2S valid Delay from SCK_I2S falling edge to SDO I2S High Z Thdi Hold time from SCK_I2S rising edge to SDI I2S transition set up time of SDI_I2S to SCK_I2S rising edge The audio analog interface consists of two wires AUDOL and AUDOR to receive the analog signal These signals are used to receive the stereo analog audio from the FM RX y wireless pired b Ins gt e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f q e nti a is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document 27 A AzureWave AzureWave Technologies Inc www azurewave com 2 4 5 FM RF interface FM embedded antenna The CG2900 supports an FM embedded antenna implemented as an inductive loop connected to FM ANT This antenna can be used for both FM TX and FM RX A filter between antenna and pins is needed to filter out FM TX out of band
28. ddress EA which incorporates manufacturer ID product code device index and Instance value for a device as described in Table 2 4 3 pired by wireless Ins 2 e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f q e nti 0 is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document 15 A AzureWave AzureWave Technologies Inc www azurewave com Table 2 4 3 SLIMbus enumeration addresses Device MI Pcl DI IV Generic device 0x0104 0x0100 0x00 0x00 Interface device 0x0104 0x0100 OxFD 0x00 1 The 4 Isb s of the PC value contain the SLIMbus IP version Identification Operations NP A port provides the connection path to data flow between Devices The AW NH580 s Sung nd see Table 2 4 4 using asynchronous and extended asynchronous segments for data streaming as well as isochronous segments Pushed or pulled protocol for speech 8 bite or 16 bits data and audio 16 bits data only channels usage Please note the audi el may use either two 16 bits ports for the left and right channels or a single 32 bits port bo am ee W Table 2 4 4 SLIMbus configuration Sf Port number Description 0 Speech channe ort 1 Speech ongni
29. e RXD edge detect AN Interface description The UART interface co e TXD UARTt n The data igari en rding to the local clock and features programmed e RXD A Oreceive the data a is r ad according to the local clock and features programmed 8432 MBaud additional baud rates e CTS UART to indicate receiver is ready ijnal is active at low level and indicates the external modem it is ready to accept transmitted via RXD UART e HRTS UART to indicate transmitter is ready This signal is active at low level and asks to the external modem if it is ready to receive data via TXD UART d by wireless Inspire 2 e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f q e nti 0 is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document www dZUrewave com A AzureWave AzureWave Technologies Inc Operations The UART uses the modem signals Clear To Send CTS and Request To Send RTS for a hardware handshake between the devices at both sides of the serial line The notation for the signals is from the Data Terminal Endpoint DTE point of view i e the device at the other side of the serial line has to be configured as Data Communication Equipment DCE An example of a f
30. eful to listen to radio stations or may be used to send music through e g a car radio system Inspired by wireless 2 e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f q e nti a is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document A AzureWave AzureWave Technologies Inc www azurewave com The audio and voice path is using either the SLIMbus the PCM or 12S interfaces to carry BT SCO and eSCO as well as FM stereo Rx and TX data and BT stereo data for A2DP Next to this the FM stereo RX can use the analog audio output interface A system clock request signal is provided to manage the system clock coming from TCXO The system clock request signal may be shared with multiple sources The low power clock is used to manage the AW NH580 low power modes The AW NH580 supports standard interface SDIO v1 10 4 bit and 1 bit for WLAN High spee T interface for BT FM GPS host controller interface and PCM I2S for BT FM audio dat FM audio signal is available as line level analog stereo output AW NH580 is sui or iple mobile processors for different applications With the combo functions and the orrffance the AW NH580 is the best solution for the consumer electronics and the lapt
31. ent on the line it is used as interrupt line from the slave used to reque e The gaximum operating frequency is 26 MHz The SDIO interface in AW NH580 supports the timings defined below e The SDIO interface is master at the host side and slave at the AW NH580 side e Operation in SD mode from 1 to 4 data bits inspired py wireless 2 e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f q e nti 0 is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document 29 www dZUrewave com A AzureWave AzureWave Technologies Inc Figure 2 4 9 SDIO interface timing fop v i r 1 i Letti mr L4 9 Lun 9 4 twh 91 SDIO CLK INPUT OUTPUT Table 2 4 11 SDIO interface timing J inspi Confidential Symbol Parameter Min Typ Max Unit f Clock frequency data transfer 0 26 MHz Pp mode tni Clock fall time 9 ns ttih Clock rise time 9 ns twi Clock low time 10 ns twh Clock high time 10 ns tisu Input setup time ns tih Input hold time ns t Output delay time during data 44 ns odly transfer mode v ed by wireless e Warning This is a message from Azurewave and the informat
32. ff loading with transcoding in the AW NH580 FM TX RX audio data and GPS data A standard application may be running BT Wideband speech and or FM Stereo Transmission Reception and GPS BT FM control or data between the CG2900 and CW11 Ne 9 NH580 SS Features The AW NH580 implements the following SLIMbus features x e Extended asynchronous protocol channels with double ended flow to dle half full duplex BT HCI transport on one two SLIMbus simplex e Extended asynchronous protocol channel with double end i to handle half duplex GPS transport on one SLIMbus simplex sochronous protocol channel pushed protocol ofp Up to 2 BT e SCO 8 kHz and or 16 kHz spee an A 44 1 kHz or 48 kHz FM stereo output audio channe A 44 1 kHz or 48 kHz FM stereo input io c e Several data format to support 8 bit and 16 bit speech channef 16 bit audio channel e LPOM offset sign and nitude audio data coding on 16 bit data and coding support for PCM 2s complement col to handle simultaneously e Alarge range of ro ency IMbus bit errors e Mbus low power modes bus pause and wake up d by wireless Inspire 2 e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f q e nti 0 is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss s
33. fter T STATUS line MAY indicate TX RX mode of the subsequent slot s i If the STATUS signal will convey TX RX mode the STATUS T3 0 475 signal shall be set to reflect the RX TX mode for the slot N no y later than 475 us from the start of N 1 slot T4 For reference only If ePTA wishes to prevent a BT transmission then it must de assert logic high the TX CONFX signal at least 75 us before the start of the BT transmit slot The BT device will sample the Ts 75 TX CONFX signal Ts or shortly after before the start of the transmit slot in order to determine whether transmit is allowed Whenever RF_ATIVE is asserted ePTA shall not change the TX CONFX inside the T5 window prior to start of a TX slot RF ACTIVE shall be de asserted within 25 us after last RX or TX activity of the transaction has ended Te 25 The STATUS signal will indicate priority of the signal no later than 1 us after RF_ACTIVE is asserted If the BT device de asserts RF ACTIVE whilst TX CONFX is de asserted e g in response to ePTA blocking BT TX the ePTA Tg 20 must re assert TX CONFX line within Tg This is incase the BT device immediately schedules a new transaction and asserts RF_ACTIVE T7 1 The PTA mechanism relies on bo ice and software parts The PTA packet wise arbitrator hardware can be programmedkto implement multiple protections and ways to grant access to the medium to one system er or to both simultaneou
34. i 0 is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document 28 A AzureWave AzureWave Technologies Inc www azurewave com 2 5 3 SBC host off loading for BT A2DP BT A2DP off loading can also be performed with audio data transferred from Host over PCM I2S or SLIMbus This slightly reduces the processing needs at Host side for A2DP streaming becomes similar to playback with wired headset In that mode Host sends stereo audio data samples 44 1 or 48 kHz to the AW NH580 This data is encoded locally using SBC and encapsulated in A2DP and L2CAP frames for sending over ND 2 6 WLAN interface AO 2 6 1 SDIO interface The SDIO interface is a 4 to 6 wire data interface SDIO CLK SDIO_CMD IA TAO SDIO DATA INT optional SDIO DATA2 and SDIO DATA3 The S with the SDIO specification version 1 10 with the exception that a the SI is not SD compatible bl but is compatible with the standard I O levels defined in this do pau errupt may be generated to the host in 4 bit SDIO mode even with no SDIO clock max olackfrequelicy is 26MHz The 6 signals of the SDIO interface are the following e SDIO CLK clock signal e SDIO CMD bidirectional SDIO comman e SDIO DATAO bidirectional data line e SDIO DATA1 INT bidirectional line n no data is pres
35. ice regarding data exchange S FSC_IP signal is driven from the master and is an active pulse at high le osition is configurable FSC_IP is used as word select in 12S mode e DCLK IP is used to clock the data The activity duration depends on the way the PCM interf AN he clock is driven from the master e DA IP and DB IP are used to transmit receive r sp grively data A and B The PCM clock can be inverted this allows the P to be used with I2S clocking Operations The AW NH580 supports both master and sl odes In both modes several configurations for the PCM clock and frame frequencies are supperted as given in Table 2 4 6 The PCM interface is able to carry two streams with different sa quencies multiplexed on a single PCM frame e g a 32 bits Left amp Right at 48 kHz audio m and an 8 kHz BT voice stream This allows the simultaneous transmission of both C d FM or both BT SCO and BT A2DP over the same PCM frame This is achieved r tojthe following principle e The FSC IF fre whatever master or slave mode used is the higher of the two streams sampl A encies e A ratio value f atures the frequency ratio of the two sampling frequencies By convention for the S haying the smaller sampling frequency Thetoutput data is repeated over ratio value PCM frames The input data is expected once every ratio value PCM frames ed by wireless inspi 2 e Warning This is a message from Azurewave and the information you a
36. ignals The AW NH580 has 5 dedicated lOs to control the state of the Front End Module and or antenna switch Four of the IOs are reserved to control t antenna switch for the 2 4 GHz frequency band The matching of the four lOs to the four f controlled by PTA see Section 2 4 duri low by a pull down resistor w switch The behavior of this IO is controlled by the PTA block see Section 2 6 4 even when WLAN is reset This guarantees that B n access the media on request when WLAN is reset Tae ontrol signals ogrammable software The behavior of those IOs is normal operation All IOs are configured as input and kept N is reset The fifth IO is reserved for the control of the BT Signal Direction Function control of antenna switch FEM CTRL 1 FEM CTRL 2 FEM CTRL 3 Output 2 4 GHz TX or 2 4 GHz RX software programmable FEM CTRL 4 FEM CTRL 5 Output BT ired by wireless InsP 2 e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f q e nti a is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document 34 A AzureWave AzureWave Technologies Inc www azurewave com 2 6 4 PTA interface Bluetooth and WLAN occupy the same 2 4 GHz ISM band which ma
37. ion you are viewing now is strictly confidential and is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document A AzureWave AzureWave Technologies Inc www azurewave com 2 6 2 SPI interface The physical SPI interface is a 5 wire data interface SPI_CSN SPI CLK SPI DO SPI DI and SPI INT Figure 2 4 10 SPI interface HOST AW NH580 SPI CLK Ves SPI_CSN SPI_MISO SPI MOSI SPI IRQ The five signals of the SPI interface are the following e SPI CSN device select allows the use of ib s evice selects per slave This signal is active low This signal is mandatory even with only ene slave because the host must drive this signal to indicate SPI frames e SPI CLK clock signal active for a f data length cycles during an SPI transfer SPI CSN active The clock is allowed to n SPI CSN is not active in order to serve other slaves e SPI DO data transfer from sl ve to master Data is generated on the negative edge of SPI CLK by the slave and sampled ay edge of SPI CLK When SPI CSN is inactive this AW NH580 output is in tristate m e SPI DI data transfer fjom master to slave Data is generated on the negative edge of PI CLK by the master and ed e positive edge of SPI CLK EC uL from the slave used to request a
38. n SPI transfer by the slave to the master The igh host input must be level sensitive e The SPI interface is operating in half duplex mode e The SPI interface is master at the host side and slave at the AW NH580 side e The SPI data length endianness and flow control are configurable The host can change the configuration by writing in the SPI configuration register ed by wireless inspi 2 e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f q e nti a is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document 31 A AzureWave AzureWave Technologies Inc www azurewave com e 16 and 32 bit word lengths are supported including the following configurable modes where bn is the bit transmission order from left to right 32 bit ModeO b15 b8 b7 b0 b31 b24 b23 b17 32 bit Mode b31 b24 b23 b17 b15 b8 b7 b0 32 bit Mode2 b7 b0 b15 b8 b23 b1 7 b31 b24 16 bit ModeO b15 b8 b7 b0 16 bit Mode1 b7 b0 b15 b8 ND e Rising clock edge is used for sampling Active clock edge for shifting is configura e Supports automatic indirect addressing of device internal memory via fixed a facilitate bulk DMA transfer e S
39. nitiate a transmission when t asserted The BT device samples the TX CONFX prior to a TX slot If TX C an on going BT transmission the BT transmission may be continued to t When WLAN is reset the signal TX CONFX will be kept low by a puldowq BT access to the media The input RF ACTIVE will be kept Pau ode wants to is de ig de asserted during scheduled ing it s effect on the control of the antenna switch when WLAN is reset Figure 2 4 15 Timing diagram for the EA BT slots Slot N 2 Slot N 1 Slot N BT activity RF_ACTIVE STATUS TX_CONF inspired py wireless 2 e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f q e nti a is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document 36 www dZUrewave com A AzureWave AzureWave Technologies Inc Table 2 4 13 Details on the timing constraints for PTA signals Parameter ie is Description T 450 200 RF ACTIVE will be asserted no earlier than 200 us and no later than 150 us before the medium is required The STATUS signal indicates the priority of a transaction for the To 15 20 duration of T2 T7 after RF ACTIVE is asserted A
40. ops d by wireless Inspire 2 e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f q e nti 0 is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document p AzureWave AzureWave Technologies Inc www azurewave com 1 2 Key Features General Integrates ST Ericsson solutions of ST Ericsson CG2900 GPS BT FM SoC and CW1100 Wi Fi SoC Depopulated 100 pin WLCSP 9 60 mm x 9 60 mm x 1 3 mm with 0 95 mm pitch SDIO interfaces support for WLAN High speed UART and PCM I2S for Bluetooth GPS and FM Vy Audio DSP embedded BT wide band speech SBC codec A2DP ws ncoding and L2CAP encapsulation to reduce host processing Direct loop through mode from FM Rx audio to BT A2DP Flexible Power Supply 3 6V 4 8V Multiple power saving modes for low power consu e ON 4 Lead free Halogen Free Design Power supply X Integrated SMPS for direct battery Tq Software adjustable output o mize power consumption L Clocks Low power clock input PAN required WLAN vy Single band 2 4 gebe b g n iVersity 1 d e h i j r k w Securit A WPA2 personal AES HW TKIP HW CKIP SW WMM WMM PS WMM SA Th AW NH580 supports also the CCX version 5
41. oss suffered or expenditure due to the misuse of any information form this document A AzureWave AzureWave Technologies Inc www azurewave com Timing In PCM framing mode the PCM synchronization pulse is a one PCM clock cycle pulse The received PCM data are sampled on the falling edge of the DCLK_IP whilst the PCM data to send are output on the rising edge of the DCLK_IP The PCM interface is defined according to the timing indicated in Figure 2 4 5 In slave mode data is sampled using the clock edges as shown in Figure 2 4 6 In 12S mode synchronization is performed using the FSC_IP as word select signal The re yy data are sampled on the rising edge of the DCLK_IP whilst the PCM data to ANS n the falling edge of the DCLK IP Figure 2 4 5 PCM interface timing master mode PS Tps FSC PCM i Tad Tu T Tit DCLK_PCM 2 T NER V 7 Taso doz tdo data out lb gt X lt msb X X X gt 4 X deb Lll FSC mark first data bit Tsai Thai data in Isb X msb X und OX sb msb data out 2X Ib X msb X l X X sb FSC mark last data bit i i datain X isb X mb X X b X X ib gt Z inspired py wireless e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f j q S nti a is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss
42. ound C8 UART CTS 2 GBF UART RTSN V0 C9 UART RTS 3 GBF UART CTS I O C10 VDD_FM_PA FM Power Amplifier supply Decoupled by Capacitor 470nF l D1 1 8V_WLAN oeoo o DCXO supply supply for RF Transmit Supply for D2 GND Ground ired DY wireless InsP E e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and 9 a f q e n i q is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document 43 www dZUrewave com A AzureWave AzureWave Technologies Inc LINNECCRNN NN RN Ground D4 EXT DUTY CYCLE 19 GPS blanking input 1 0 D5 GND Ground D6 EXT_FRM_SYNCH_ 20 GPS cellular frame timing reference V0 D7 GPS_ANT_SEL_TP2 GPS antenna selection O D8 UART TXD 4 GBF UART RXD 1 0 D9 UART_RXD_ 5 GBF_UART_TXD 1 0 D10 VDDIO_G General Purpose IO supply 1 8V l E1 1 8V GBF Digital supply GBF_1 8V WLAN1 8V Decoupled by Capacitor 1uF l E2 GND Ground E3 GPS_LNA_EN_TP1 GPS LNA enable O E4 GND Ground E5 HOST WAKE 11 GBF HOST WAKEUP 1 0 E6 GND Ground EY I28 WS 13 GBF IIS WS 1 0 E8 I28 DIN 15 GBF IIS DIN 1 0 E9 GND Ground E10 VOUT GBF Regulator output 1 8 V O F1 VBAT_DUT_W Battery supply Regulator input 3 6 V l F2 WRESET RESET of the WLAN subsystem active low l F3 CLKREQOUT2_TP4 WLAN
43. ound J3 CLKREQIN1_TP3 WLAN Programmable pin CLK_REQ_IN VO J4 PMU_EN EC DC DC 1 8V power supply Only used for test J5 PTA_RF_ACT 17 See pin WLAN PTA RF ACTIVE Only used for test UO J6 GPS CAL FREQ 18 GPS cellular ref clock request for calibration VO J7 GND Ground i l J8 GND Ground J9 TCXO_IN_MB Only used for test purpose NC l J10 VDD_TCXO E LDO External TCXO power supply Only used for test purpose 9 K1 GND Ground K2 1 8V_SMPS WLAN Internal regulators 1 8V switch output O K3 GND Ground K4 VBAT_PWR WLAN Power stage supply pin O K5 W_IRQ e aie pin PTA WIMAX WIRQ Only used for test purpose jo K6 PTA TX CONF 0 d pin GBF PTA CONFX Only used for test purpose UO K7 GND Ground K8 GPS_RFIN GPS antenna input port 50 Ohms VO K9 GND Ground K10 GND Ground GBF GPS Bt FM NC No Connect ired bY wireless InsP e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and 9 a f j q S n i 0 is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document 45 p AzureWave AzureWave Technologies Inc www azurewave com 3 2 Pin Location Top View X Y Coordinate Unit um PIN NUMBER ad PIN_Y NAME Al 4 275 4 275 GND A2 4 275 3 325 SDIO_DATA2 HIF
44. program as either the first Figure 2 4 3 or the last Figure 2 4 4 bit of the frame The number of R lock cycles between two PCM synchronization pulses defines the PCM frame duration There ctive slots supported within a PCM frame Each active PCM slo eseither 8 or 16 bits wide For each slot the slot start time relative to FCS IP can be progra clock cycles The timing of the PCM slots must be such that slot 0 is always is however possible to only uses for example slot 1 and not slot 0 The DCLK IP ammed to be active until the last data bit or can be continuously active over the located bef activity whole PCM frame The PCM data in and data out can per active slot be programmed to be mapped on DA I IP Figure 24 4 shows example of a PCM frame The PCM frame starts with FSC IP followed by the PCM slots In this example the PCM frame consists of 4 PCM slots the first one slot 0 is 16 bits wide and starts at PCM bit 1 the second one is 16 bits wide and start at PCM bit 17 and etc pired py wireless Ins 2 e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f q e nti 0 is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document 20 A AzureWave AzureWave Technologie
45. rame for a protocol with one start bit 0 8 data bits LSB first no parity and one stop bit 1 is shown in Figure 2 4 1 ND Figure 2 4 1 Example of a serial interface frame X Baud rates SN The AW NH580 supports a wide range from standard rates as listed in the following chapters The default baud rate is provided from the static T 5 2 kBaud The AW NH580 can start at 115 2 and 120 kBaud f Ps Supported baud rates Table 2 4 1 lists the baud rates SOragorted by the AW NH580 Baud rates bps 4 950 000 2 000 000 4 920 000 1 800 000 4 860 000 1 500 000 4 800 000 1 444 400 i E 4 050 000 1 000 000 4 000 000 750 000 i i 3 692 300 162 500 3 690 000 120 000 3 600 000 115 200 3 250 000 81 250 3 000 000 pired py wireless Ins 2 e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f q e nti a is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document 13 A AzureWave AzureWave Technologies Inc www azurewave com 2 4 2 SLIMbus interface The SLIMbus interface is a synchronous serial interface used to transfer asynchronous HCI data BT ACL data Isochronous BT e SCO voice data BT A2DP stereo data in the case of host o
46. re viewing now is strictly confidential and C 9 n f q e nti a is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document 19 A AzureWave AzureWave Technologies Inc www azurewave com Table 2 4 6 PCM frame duration in number of PCM clock cycles master and slave modes DCLK_IP s khz R o o ceo amp e amp gt co o N co i o e e IRIS fe 9 z 9 R8 RIS EB 5 3 amp FSC_IP A 3 e kHz a 8 16 32 64 96 128 192 250 256 300 384 16 89 169 32 48 64 96 125 128 150 x 32 E 8 16 24 32 48 a 64 75 44 1 82 of i 48 169 i 32 V Jt SCO two channels or both BT A2DP and BT SCO Up to 50 E 1 Slave mode only 2 Clock frequency to support both FM audio left amp right channel amp 3 POM burst mode 4 Transmitting 16 bits left and 16 bits right as PCM data with FSC 0 kHz requires minimum DCLK IP216 MHz 5 Only one 8 bits slot A law u law voice channel is 6 Only one 16 bits slot one PCM linear 16 bit voi lowe el is allowed In PCM framing mode a PCM frame s iththe PCM synchronization pulse The position of this PCM synchronization pulse is
47. rewave com p AzureWave AzureWave Technologies Inc 2 Electrical Characteristics 2 1 Absolute Maximum Ratings Parameter VDD_CORE Core Voltage for GPS BT FM conditions at 1 8V 0 5 VDD_FM_PA Core Voltage for FM Tx Power Amplifier 0 5 VDDIO_G I O power supply for BT FM GPS 0 5 VDDIO_W I O power supply for WLAN 0 3 VBAT_DUT_G Battery supply voltage 0 5 VBAT_DUT_W Battery supply voltage 0 2 2 Recommended Operating Conditions OO Symbol Parameter Type Min Typ Max Units VBAT DUT G W Regulator input supply voltage npb 3 6 E 4 8 V 1 8V GBF Digital supply voltage NO Input 1 7 18 195 V 1 8V WLAN WLAN supply voltages 1 8 V W input 1 65 1 8 1 95 V GPS BT FM analog supply volt and Input 1 7 1 8 1 95 V VDD CORE Power Amplifier supply voltage VDDIO_G W I O power supply for aver PS Input 1 65 1 8 1 95 VOUT Regulator output su ly Itage for GPS BT FM Output 1 7 1 8 1 95 PF VDD TCXO TCXO supply volta Output TBD 1 88 TBD Power st ge at connected to VBAT PWR Input 3 6 4 8 V VBAT GA for SMPS 1 8V_SMPS MRS output conditions at 5 accuracy Output 1 71 1 8 1 89 V 1 Supply ripple bellow 1 all be 50 mVpp 2 Supply ripple from 1 hall be 25 mVpp 3 Supply ripple aboy Parameter Vit Low level input voltage 0 0 35 VDDIO V Vin High level input voltage
48. s e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f q S nti 0 k is a knowledge property to Azurewave Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document www dZUrewave com A AzureWave AzureWave Technologies Inc 5 Shipping Information 5 1 BHODOODOOU BBOOOoOOoOoO0O Bu li uuucdd BUD IIUUU Bag gaHE CU DU UL HHEB lj 1317 Figure 1 Describes when the J tray is placed on the working table the tray notch shall face the bottom left hand side partial devices places form bottom to up direction Figure 2 Describes when the E tray is placed on the working table the tray notch shall face the up left hand side partial devices places form bottom to up direction Ly meg Figure 2 Figure 1 1 UNIT DESICCANT HUMIDITY INDICATO R f PLN DRYPACK BAG AS BAG HOLE DIRECTION SS a Se ON a mg BB PINK BUBBLE WRAP AFFIX WARNING LABEL d by wireless i r gt e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n j q e nti e is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or e
49. s Inc www azurewave com Figure 2 4 3 PCM transfer example synchronization pulse is first bit of the frame DCLK IP FSC IP T JI paan LTA Bep I PEN ee BENI eiei TEE EEN I bag T ELT PE D aout FATT BER N EEN I BST EEN HE Bee N EEN EE T T ETT PE slot stat 0 0 sict_start_1 16 1 Slot start 0 0 first data bit of slot 0 occurs within the same DCLK_IP cycle as FSC_IP rising edge 2 Slot start 1 16 Figure 2 4 4 PCM transfer example synchronization pulse is last bit d DCLK IP FSC IP an LTT Bate EENI SPEEN see P TEL EELL dea ELLE E ond FALI SPU TEU ESET PEE EA SP sot start 0 1 sd stat 1 17 1 Slot start 0 1 first data bit of slot O occurs 1 DCLK IP cycle after FSC IP rising edge 2 Slot start 1 7 17 As it is important to synchronize the NG are several configurations as outlined below e Bluetooth master and PCM m ster In this case the voice path i sy ized e Bluetooth master and ve In this case the voice pa synchronized th is synchronized The PCM timing is synchronized to the Bluetooth timing slave and the Bluetooth slave timings a PCM sample is lost or duplicated inspired py wireless e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f j q e nti a is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any l
50. sly in RX sometimes The high level controller PTA firm denied aborts o d trols the HW parameters and monitors the number of grant access N traffic to ensure that the medium is shared efficiently and fairly over time TC CLK There are 2 clock sources the system clock used in normal operations and the low power clock used for low power operations In Active mode the system clock is mandatory when using the WLAN GPS BT and or FM subsystems The low power clock is used to keep the enabled system subsystems WLAN GPS BT and or FM running during their low power mode It is also used for the automatic system clock frequency detection Inspired by wireless e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f j q e nti a is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document 37 A AzureWave AzureWave Technologies Inc www azurewave com 2 7 1 System clock The AW NH580 provides a single ended system clock input for all integrated subsystems GPS BT and FM This system clock input can come from a TCXO which is included in the reference design Or the system clock input can come from the Host see Table 2 4 14 When the system clock comes from an external TCX
51. spired py wireless e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n j j q e nti a is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document 25 A AzureWave AzureWave Technologies Inc www azurewave com Timing In master mode the 12S interface is defined according to the timing indicated in Figure 2 4 7 In slave mode data is sampled using the clock edges as shown in Figure 2 4 8 Figure 2 4 7 12S master timing 4 Twsl WS _12S T Taws seks A_ el eme T T SDO I2S msb Tsai Thai SDI I28 msb Table 2 4 9 I2S master timings ROS Symbol Parameter Min Typ Max unit 3 Twsh Short WS 12S high time O Us ii s ns 24MHz 2 125 Twsl Long WS 12S high time ns To4MHz Tch SCK I2S high time 4xToamuz 96XT24MHz ns Tel SCK_I2S low time 3xXT24MHz 96XT24MHz ns Tjit SCK 12S jitter x 3 ns 24MHz Tdws Delay from SCK 128 falling edge to WS I2S edge 50 ns Tddo Delay from SCK 12S falling edge to SDO I2S E 50 ns transition Delay from SCK_I2S falling edge and SDO 12S High Tdzdo 7 to SDO I2S valid 20 ns Tddoz Delay from SCK_I2S falling edge to SDO 12S High Z 50 ns Thdi Hold time from SCK 12
52. suffered or expenditure due to the misuse of any information form this document www dZUrewave com p AzureWave AzureWave Technologies Inc Once the device is in System Deep Sleep state and all device subsystems GPS BT and FM are disabled the device can be put in the System Off state to reduce the consumption even further e g this mode is used when all device subsystems are disabled from the Host In System Off state the lOs can be configured by the Host to keep a pull up pull down or high Z state retention configuration to not interfere with the rest of the application and all the clocks are switched off The System Off state is entered via a Host software request and via PDB pin assertion to a lo level Then going back to the System Active mode requires the PDB pin to be asserted to a hig el Following the high level on PDB the CG2900 goes through the system reset AE Figure 2 4 16 Start up and reset state diagram Power Off b y resetcomplete System enable HCI detected System active functions disabled or in low power mode System Deep sleep device event or host wakeup request pired py wireless Ins 2 e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f q e nti 0 is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right
53. ta to transfer Timing The SLIMbus interface complies with the timing characteristics indicated in Figur Figure 2 4 2 SLIMbus interface timing data transmit T TCLKIH Earliest Clock receiver Latest Clock transmitter Data atreceiver Table 2 4 5 meam timing characteristics data transmit Parameter Conditions Min Max Unit Clock terminal input 0 65 ViLimin Input clock high level VDDIO V 0 35 ViL max Input clock low level VDDIO V Teiku CLK Input High Time 12 ns TeLkiL CLK Input Low Time 12 ns Inspired by wireless e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f j q e nti a is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document 17 A AzureWave AzureWave Technologies Inc www azurewave com Table 2 4 5 SLIMbus interface timing characteristics data transmit continued Clock Input Slew Rate 20 lt VI lt 80 cae is Clock Input Slew Rate 20 lt VI lt 80 0 019 as ome Ww Clock transmission line characteristics Total jitter from voltage and time ce J Im a Qa o 3 m Tskew _ Clock line delay TCLKUNC RT Data terminal output V Vondata Output data high level
54. uffered or expenditure due to the misuse of any information form this document www dZUrewave com A AzureWave AzureWave Technologies Inc Interface description The SLIMbus interface consists of 2 wires e SLIM_CLK to clock the data It is active during all the SLIMbus transfer The SLIMbus clock is driven by the external SLIMbus Framer device e SLIM DATA to transmit receive data The data is written on the positive edge and read on the negative edge of the clock The data uses a NRZI encoding and the data size handled depend on the protocol u In AW NH580 the SLIMbus interface supports only the Interface Device class a given in Table 2 4 2 which allows for 8 16 44 1 and 48 kHz sample rates u ing on the root frequency the isochronous pushed or pulled protocol has to be used E ofth jsochronous ports use four SLIMbus slots for the 16 bit data The pushed or pulled protocol wiif Be seg when the root frequency does not allow to create a segment rate equal to MBS a Table 2 4 2 SLIMbus root frequencies 2 xd oca Description 16 384 SLIMbus mm Y for 8 16 kHz 16 9344 SLIMbus n tural frbquency for 44 1 kHz 18 432 sy s natural frequency for 48 kHz 19 2 Dh reference 19 8 ee reference ame SLIMbus natural frequency for 44 1 kHz d SLIMbus cardinal frequency for 8 16 48 kHz a 26 Cellular reference EE oa to the SLIMbus is addressable by a unique 48 bit Enumeration A
55. ument is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document www dZUrewave com p AzureWave AzureWave Technologies Inc WLAN TBD GPS TBD Output Power Bluetooth TBD FM TBD WLAN TBD GPS TBD Receive Sensitivity Bluetooth TBD FM TBD WLAN 802 11b 1 2 5 5 11Mbps 802 119 6 9 12 18 24 36 48 54Mbps Rate Rates 802 11n MCS 0 7 Bluetooth Bluetooth 2 1 EDR data rates of 1 2 and 3Mbps Power Consumption Not specified WPA and WPA2 Personal support for powerful encryption and authentication AES and TKIP acceleration hardware for faster data encryption and 802 11i compatibility Cisco Compatible Extension CCX CCX 2 0 CCX 3 0 CCX Security 4 0 CCX5 0 certified SecureEasySetup for simple Wi Fi setup and WPA2 WPA security configuration X Wi Fi Protected Setup WPS WEP CKIP Software Operating System Compatibility TBD y wireless pired b Ins E e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and 0 a f q e n ti q is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document 10 www dZU
56. upports host wake up of the WLAN block by SPI register access NS The default WLAN SPI configuration is O e 32 bit data length e Most significant byte first default is little endian e Most significant bit first Q e Flow control on SPI DO and in a register Figure 2 4 11 Default SPI data tragffoc fro e host master to the AW NH580 slave SPI CSN 1 4 SPI CLK i i SPI DO i SPI DI 21 3 Write Length Data SPI INT i 1 Master selects the Slave 2 Master sends Write command and data to Slave 3 All data have been transmitted 4 Master de selects Slave y wireless e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f j q e nti a is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document 32 www dZUrewave com A AzureWave AzureWave Technologies Inc Figure 2 4 12 Default SPI data transfer from the AW NH580 slave to the host master SPI_CSN 2 6 SPI CLK 4 eps ue oo To 15 gt 3 Reed commend ke Do 1 SPI INT 1 Slave requests the bus 2 Master selects the Slave 3 Master sends Read command to Slave 4 Slave sends back Length and Data 5 All data has
57. ve Technologies Inc www azurewave com Table 2 4 8 I2S frame modes and rates 16 kHz 32 FS 32 bit frame 8 8kHz 64 FS 64 bitframe 16 kHz 48 FS 48 bit frame om 8 kHz 96 FS 96 bit frame 16 16 kHz 64 FS G4 bitfframe L S4 jJ 8 kHz 128 FS 128 bit frame 048 48 kHz 32 FS 32 bit frame 1536 16 16 kHz 96 FS 96 bit frame 1024 8 B kHz 192 FS 192 bit frame kHz 150 FS 150 bit frame 2400 SN 8 kHz 300 FS 300 bit frame 48 kHz 64 FS 64 bit frame 3072 16 16 kHz 192 FS 192 bit frame 8 8 kHz 384 FS 384 bit frame 44 i 44 1 kHz 32 FS 32 bit frame 1411 20 22 22089 22 05 kHz 64 FS 64 bit frame EUR 44 1 kHz 64 FS 64 bit frame 2822 40 22 052 22 05 kHz 128 FS 128 bit frame 160002 up to 500 up to 16000 kHz 32 bit frame 1 Actual 12S master mode WS rate and CLK rate have a 0 04 error 16 kHz 128 FS 128 bit frame 8 fs kHz 256 FS 256 bit frame 2 Only 16 bit word width is supported i F Figure 24 8 shews an example of an l2S bus frame Figute 2 4 bus transfer example Left channel data Right channel data sooes 8 BE ENNAN so_es _ AII T at WS I2S Isb data length is determined by word wide sck_l28 JUHU UUW UUW UU UU ULE UU UU EHE UTLTUE ET LTLI in
58. vel select the right channel This signal is continuously running when th ce is enabled e SCK 12S to clock the data The clock is driven from the master and it is continuously running when the interface is enabled e SDI l2S and SDO 128 to respectively receive transmit the data The data is driven on the negative edge and read on the positive edge of the clock The data size handled is 16 bits The supported bit ordering is MSB first left justified Inspired by wireless e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n f j q e nti a is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document 23 A AzureWave AzureWave Technologies Inc www azurewave com Operations The AW NH580 supports both master and slave modes together with mono and stereo types as listed in Table 2 4 6 In both modes several configurations for the 12S word selection and clock rates are supported as given in Table 2 4 7 In stereo mode the left and right data are transferred In mono mode the same data is output twice ND A W Table 2 4 7 I2S audio interface mode FM stereo transmission or BT A2DP Master Stereo uni directional data input FM stereo transmission or BT A2DP Slave Stereo uni directional d
59. ws e VDDIO is applied NS e LP CLK low power clock is running and stable ND e WRESETN pin is released after at least two LP CLK cycles e PMU EN is asserted in case the internal SMPS is no uilt in SMPS is activated in case it shall get a valid supply within 20 ms is used In both cases VDD W HV x and VDD W COR e The host should wait 30 ms after the WRESE elease for the on chip LDO to stabilize e The chip is now in the sleep state e The host should now wake the devic iting over the host interface SPI or SDIO to WUP bit e The device asserts CLKREQOUTX to requ he reference clock e Within Tstable ms the referenge clock Should be stable and the system can start using it e The device will set the R rea and assert IRQ to the host e The host can download th amp fitmwdre and release the CPU reset by further SPI SDIO write e The host now waitg fonthe 1100 sub system to initialize and can clear the WUP bit e Onceinitializ ich ngl des a series of message passing between the host and the WLAN the WLAN mayat Nav ything further to do and will enter the sleep state More detailed ipforrgation on this startup sequence and the required host commands can be found in the hardware user manual The n of the device does not imply any constraint It is also recommended that the platform activates the RESETN at least 2 LP CLK cycles before powering off of the supplies ed by wireless inspi 2 e Warning This is a message from
60. xpenditure due to the misuse of any information form this document www dZUrewave com A AzureWave AzureWave Technologies Inc 5 4 INNER BOX DRYPACK BAG HOLE Cardboard Notice Please use Cardboard to fill space AFFIX PACKING LABE TRANSPARENT ING r ed by wireless inspi 2 e Warning This is a message from Azurewave and the information you are viewing now is strictly confidential and C 9 n j q S nti a is a knowledge property to Azurewave e Unauthorized use of this document is prohibited and Azurewave retains the right for legal actions against any loss suffered or expenditure due to the misuse of any information form this document
61. y lead to interference when operating concurrently The IEEE standard 802 15 2 recommends a collaborative coexistence mechanism of Packet Traffic Arbitration PTA based on time sharing BT and or WLAN requesting the medium before any communication In case of conflict PTA decides whom to award the medium to based on priority of the BT and WLAN traffic and their current status By using the coexisten mechanism it is possible to dynamically allocate bandwidth to the two devices when simult gt operations is required while the full bandwidth can be allocated to one of them in cas other does not require activity The combination of time division multiplexing and the priority mechanism amp voigs the interference due to packet collision It also allows the maximization of the 2 4 GHz ISM b usage for both devices while preserving the quality of some critical types of link A typica jlleatio would be to guarantee optimal quality to the Bluetooth voice communication while a ensiv AN communication is ongoing AW NH580 implements the IEEE 802 15 2 AN Description of standard PTA ctices referred to as standard PTA The standard PTA implementation in AW I4H580 uses a four wire interface The polarity of the signals is programmable f PLN Elda ehe traffic arbitration PTA between BT and WLAN Signal RF ACTIVE output from BT and input to PTA is asserted prior to any BT tr

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