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SH6622A

1. SH6622AH yyxxx 000HR Chip Form SH6622AK yyxxx 028DU 28L DIP SH6622AM yyxxx 028MU 28L SOP Note 1 yy means 2 bits option and means bits code seriary number If the product is OTP type and in blank order those bits should be none 2 The data after mark in Part No block is the package and packing information for ordering 3 The size of those package types are showed in Package Information Page26 27 4 Any other package or packing request please refer to following table Normal package size and in tray packing QFP Normal package size and in tube packing CHIP Normal package size tape amp reel packing J CER DIP Larger package size in tray packing SKINNY Larger package size and in tube packing PLCC Larger package size and tape amp reel packing SOP Smaller package size and in tray packing omes Srater packege size andin we pacing S660 DE ON WAFER N Sater package sze andin tape amp reel so 0L wemse 1 LL 1 25 IM SH6622A Package Information DIP 28L Outline Dimensions unit inches mm E Mounting Plane a E 0 175 Max 4 45 Max 0 010 Min 0 25 Min 0 130 0 005 3 30 0 13 0 018 0 004 0 46 0 10 0 002 0 05 0 060 0 004 0
2. 00010 Obbb xxx AC lt AC CY SBCM 00010 1bbb lt Mx AC CY SUB X B 00011 Obbb xxx xxxx AC lt Mx AC 1 SUBM 00011 1bbb Mx lt AC 1 EOR X B 00100 Obbb xxx xxxx AC lt Mx 6 AC EORM 8 00100 1bbb xxx xxxx AC lt Mx AC OR X B 00101 Obbb xxx xxxx AC lt Mx AC X B 00101 1bbb xxx xxxx AC lt Mx AC X B 00110 Obbb xxx xxxx AC lt Mx amp AC 00110 1bbb xxx lt Mx amp AC 0 gt 3 AC 0 AC shift right one bit 11110 0000 000 0000 Immediate Type Lemon 0000 comm xi om xi oromo n the assembler ASM66 V1 0 EORIM mnemonic is EORI However EORI has the operation identical with EORIM Same for the ORIM with respect to ORI and ANDIM with respect to ANDI Decimal Adjustment 11001 0110 xxx xxxx AC Mx Decimal adjustment for add DAS X 11001 1010 xxx xxxx AC Mx Decimal adjustment for sub CY 12 5 6622 Transfer Instruction PC ifCYz1 PC 3 1 ST lt CY PC 1 PC Not including p PC ST TBR lt hhhh lt III oF Where Control Inst
3. Current into 50 Current out of Vss 150mA Output current sunk by any I O port 25 Output current sourced by any I O port 20mA Output current sunk by all ports A B C D E F Include supply voltage and chip to chip variation 50mA Output current sourced by all ports A B C D E F 40mA 16 5 6622 DC Electrical Characteristics 3 0V GND 25 Fosc 4MHz unless otherwise specified Parameter in Operating Voltage All output pins unloaded Execute NOP instruction Stand by Current HALT All output pins unloaded All output pins unloaded Stand by Current STOP LPD off If LPD 1 2 WDT off If WDT ISB2x IsB2 54A Input Low Voltage GND 0 2 X VDD ports pins tri state Input Low Voltage GND 0 15 X VDD RESET TO Input Low Voltage GND 0 15 X OSCI Driven by external clock Input High Voltage 0 8 X VDD ports pins tri state Operating Current Input High Voltage 0 85 X TO Input High Voltage 0 85 X OSCI Driven by external Clock Leakage Curent mi 1 1 FinputLeakage Curent ma amp 5 GND lt Vmm lt voo 1 F input Leakage Curent ma s Leakage Curent ms ports 7 Vpp
4. PCXOUT PDXOUT PEXOUT X 0 1 2 3 PFXOUT X 0 1 1 Use as an output buffer 0 Use as an input buffer Power on initial TO amp WDT System Register 1C 1C Tos TOE TO signal edge Bit1 TO signal source TOE TO signal edge 0 Increment on low to high transition TO pin Power on initial 1 Increment on high to low transition TO pin TOS TO signal source 0 OSC 1 4 Power on initial 1 Transition on TO pin 5 6622 TOS OSC A gt 8 BITS 11 x x 0 TOE EOR 3 BUILT IN RC OSCILLATOR 0 2 0 WDT ENABLE gt WDT amp WARM iy M USER OPTION UP COUNTER 3 WDT TIMEOUT System Register 1E 1 NNNM se ra wre ut orton in The input clock of watchdog timer is generated by a built in RC oscillator So that the WDT will always run even in the STOP mode SH6622A generates a RESET condition when watchdog is time out Watchdog can be enabled or disabled permanently by user option To prevent it from time out and generating a device RESET condition you should write this bit as 1 before timing out The WDT has a time out period of more than 7ms 5V If longer time out periods are desired prescaler with a divide ratio of up to 1 2048 can be assigned to the WDT under software controlled by writing to the TMO register Prescaler divide ratio v
5. SINO WEALTH Features m SH6610C based single chip 4 bit microcontroller B ROM 4K X 16 bits RAM 160 X 4 bits Data memory Operation voltage 2 2 6 0V Typical 3 0V 5 0 22 CMOS bi directional pins E 4 level subroutine nesting including interrupts One 8 bit auto re load timer counter Warm up timer for power on reset W Powerful interrupt sources Internal interrupt TimerO External interrupts PortB amp PortC Falling edge General Description SH6622A Mask 4 bit Microcontroller B Oscillator code option X tal oscillator 32 768KHz 4MHz Ceramic resonator 400K 4MHz RC oscillator 400K 4MHz External clock 30K 4MHz E Instruction cycle time 4 32 768KHz 122us for 32 768KHz OSC clock 4 4MHz 1us for 4MHz OSC clock W Two low power operation modes HALT and STOP E Built in watchdog timer code option 5 6622 is a 4 bit microcontroller This chip integrates the SH6610C 4 bit CPU core with SRAM 4K program ROM Timer and Port Pin Configuration 2 1 PORTE3 2 PORTA2 4 PORTA3 5 9 10 2 11 PORTB 3 12 PORTD O 13 PORTD 1 0 14 VcCC99HS PORTE 1 0 0 1 0 OSCI OSCO PORTC 3 PORTC 2 PORTC 1 0 PORTD 3 PORTD 2 V2 4 5 6622 PRESCALER 4
6. 5 3 0 1 GND VoD Pin Description Pin No Designation 3 0 PORTC 3 0 PORTD 3 0 PORTE 3 0 PORTF 1 0 Descriptions 27 28 1 2 PE 0 PE 3 Bit programmable 26 3 0 PF 1 Bit programmable 24 25 4 5 PA 0 PA 3 Bit programmable TO Timer Clock Counter input pin Schmitt Trigger input RESET Reset input active low Schmitt Trigger input GND Ground pin PB 0 PB 3 Bit programmable 1 Vector Interrupt Active falling edge PD 0 PD 3 Bit programmable PC 0 PC 3 Bit programmable Vector Interrupt Active falling edge VDD Power supply pin OSCO OSC output pin There is a signal with a frequency of Fosc 4 for RC mode OSCI OSC input pin connected to crystal ceramic or external resistor Function Description 1 CPU The CPU contains the following function blocks Program Counter Arithmetic Logic Unit ALU Carry Flag Accumulator Table Branch Register Data Pointer INX DPH DPM and DPL and Stack 1 1 PC Program Counter The Program Counter is used to address the 4K program ROM It consists of 12 bits Page Register PC11 and Ripple Carry Counter PC10 PC9 PC8 PC6 PC5 PC4 PC3 PC2 PC1 PCO The program counter normally increases by one 1 with every execution of
7. 3V 5 0 7mA 3V ports lol 8mA VDD OSCOrc lor 1 0 Vpp 3V Output High Voltage Output Low Voltage AC Electrical Characteristics VoD 3 0V GND Ta 25 Fosc 4MHz unless otherwise specified Parameter in Condition Oscillator start time Crystal Osc 32 768KHz Vpp 3 0V Oscillator start time Ceramic Osc 400KHz 3 0V Oscillator start time RC Osc 400KHz Vpop 3 0V WDT period Vpp 3 0 Frequency stability crystal Crystal oscillator F 3 0 F 2 7 F 3 0 Frequency variation crystal Crystal oscillator C1 C2 5 30P Frequency stability ceramic Ceramic resonator OSC F 3 0 2 7 3 0 Frequency Variation RC Include supply voltage and chip to chip variation Operation frequency vs IsB1 IsB1x Frequency 4MHz X IsB1 Operation frequency vs Frequency 4MHz X lop 32K Max Halt current 32KHz Halt current lt 5uA 3V WDT is disabled 17 5 6622 Characteristics Wax Unt Condition ter rono mw N Precalerdide rato mw High pulse wit m 8 m iowsmewan Timing Waveform TO Input Waveform M gt lt TiwL TO RC OSCO Timing Waveform T1 T2 TA T5 16 T7 T8 T1
8. T2 T3 T4 T5 T6 RC OSC OSCO RC Built in RC Oscillator OSC WDT Built in RC 4 gt M 2 Tosc3 5 6622 Typical RC oscillator Resistor vs reference only F 400KHz 4MHz 480 45 _ 460 a x 440 X 35 420 400 25 2 0 4 0 6 0 2 0 3 0 4 0 5 0 Volts VpD Volts Typical RC oscillator Frequency vs for reference only 410 4200 400 4000 390 3800 380 3600 370 3400 360 3200 350 3000 2 0 3 0 4 0 5 0 2 0 3 0 4 0 5 0 Volts Volts Typical RC oscillator Resistor vs Frequency for reference only R F 3 0V 500 450 400 350 300 Y 250 200 150 100 50 0 100 1000 10000 KHz 19 5 6622 1 Operating voltage 3 0V 2 Oscillator Crystal 32 768KHz 3 For high reliability C1 is better to be added 4 PORTA F I O 2 o N gt 2 1 Operating voltage 5 0V 2 Oscillator Ceramic resonator 400KHz 3 For high reliability C1 is better to be added 4 TO
9. an instruction except in the following cases 1 When executing a jump instruction such as JMP BAO BC 2 When executing a subroutine call instruction CALL 3 When an interrupt occurs 4 When the chip is at the INITIAL RESET mode The program counter is loaded with data corresponding to each instruction The unconditional jump instruction JMP can be set at 1 bit page register for higher than 2K 1 2 ALU and CY ALU performs arithmetic and logic operations The ALU provides the following functions Binary addition subtraction ADC SBC ADD SUB ADI SBI 2 ROM SH6622A Decimal adjustment for addition subtraction DAA DAS Logic operations AND EOR OR ANDIM EORIM ORIM Decision BAO BA1 BA2 BA3 BAZ BC Logic Shift SHR The Carry Flag CY holds the ALU overflow which the arithmetic operation generates During an interrupt servicing or call instruction the carry flag is pushed into the stack and restored back from the stack by the RTNI instruction It is unaffected by the RTNW instruction 1 3 Accumulator Accumulator is a 4 bit register holding the results of the arithmetic logic unit In conjunction with ALU data transfer between the accumulator and system register or data memory can be performed 1 4 Stack A group of registers are used to save the contents of CY amp PC 11 0 sequentially with each subroutine call or interrupt It is organized in 13 bits X 4 levels The MSB is s
10. 002 0 010 0 004 0 25 0 10 0 288 0 005 7 32 0 13 5 Notes 1 The maximum value of dimension D includes end flash 2 Dimension E1 does not include resin fins 3 Dimension S includes end flash 26 x SH6622A SOP 28L Outline Dimensions unit inches mm 28 15 E 1 14 Detail F See Detail L uem 02885 0 016 0 004 0 41 0 10 ET 0 002 0 05 0 010 0 004 0 25 0 10 oe 8 0050005 1 015 e ew vw Notes 1 The maximum value of dimension D includes end flash 2 Dimension E does not include resin fins 3 Dimension e is for PC Board surface mount pad pitch design reference only 4 Dimension S includes end flash Seating Plane 27 5 6622 Data Sheet Revision History 4 3 2 1 0 28
11. 68KHz Crystal C1 C2 lt 56 VDD 5V C1 C2 lt 56 Crystal 4MHz C1 C2 lt 33p VDD 5V C1 C2 lt 10 VDD C2 2 Ceramic resonator 400KHz 4MHz C1 C1 C2 Setting Ceramic 400KHz Ceramic 20 lt C1 C2 lt 470p VDD 5V 400K 4MHz 20 lt C1 C2 lt 150p VDD Ceramic 4MHz 20 lt C1 C2 lt 100p VDD 5V C1 C2 lt 10 VDD C2 3 RC oscillator 400KHz 4MHz VDD 4 External input clock 30KHz 4MHz 5 External clock source OSCO 10 5 6622 Initial State Hardware After power on reset Program counter 000 CY Undefined Data memory Undefined System register Undefined AC Undefined Timer counter 0 Timer load register 0 WDT counter 0 WDT prescaler 0 ports Input LPD3 0 1010 Enable LPD TOS TOE 00 WDT 0 11 5 6622 Instruction Set All instructions are one cycle and one word instructions The characteristic is memory oriented operation Arithmetic and Logical Instruction Accumulator Type Mnemonic Instruction Code Function Flag Change ADC X B 00000 Obbb xxx xxxx AC lt 00000 1bbb Mx CY 00001 Obbb lt Mx AC ADDM X B 00001 1bbb xxxx lt Mx AC 58
12. A WDT off If WDT on IsB2x IsB2 15 Input Low Voltage GND ports pins tri state Operating Current Input Low Voltage GND RESET 10 Input Low Voltage GND OSCI Driven by external clock Input High Voltage 0 8 X VDD ports pins tri state Input High Voltage 0 85 X RESET TO Input High Voltage 0 85 X OSCI Driven by external Clock Input Leakage Current ports GND lt lt VDD Input Leakage Current GND lt V Reser lt VDD Input Leakage Current GND VDD ports 10 6 0V 0 7mA 6 0V ports loL 20mA 6 0V OSCORc lor 1 6mA 6 0V GND 0 6 15 5 6622 AC Electrical Characteristics Voo 5 0V GND 25 Fosc 4MHz unless otherwise specified Parameter Condition Oscillator start time X tal Osc 32 768KHz VDD 5 0V Oscillator start time Ceramic Osc 400KHz Vpb 5 0V Oscillator start time RC Osc 400KHz 5 0V WDT period 5 0V Frequency stability c rystal Crystal oscillator F 5 0 F 4 5 F 5 0 Frequency variation crystal Crystal oscillator C1 C2 5 30P Frequency stability ceramic Ceramic resonator Osc F 5 0 4 5 5 0 Frequency Variation RC User Notice Max Max Max Max Max Max
13. H Please refer to SH6610C User s manual 5 6622 Low Power Detection The LPD function is to monitor the supply voltage and applies an internal reset in the microcontroller at the time of battery replacement If the applied circuit satisfies the following conditions the LPD can be incorporated by software control W High reliability is not required W Power supply voltage 2 2 to 6 0 V W Operating ambient temperature TA 20 C to 70 C Functions of LPD Circuit The LPD circuit has the following functions Generates an internal reset signal when x VLPD Cancels the internal reset signal when gt VLPD Here power supply voltage VLPD LPD detect voltage it is about 1 6 1 7V and lower than 2 2 LPD Control Register The LPD circuit is controlled by software enable flag LPD Enable Control LPD3 0 LPD3 LPD2 LPD1 LPDO 1010 LPD Enable Default 0101 LPD Disable LPD3 LPD2 LPD1 LPDO LPD Enable Disable flag 1 0 1 0 Enable LPD circuit Power on initial 0 1 0 1 Disable LPD circuit 5 6622 System Register 16 1B Address RW 7 priour PFOOUT SetPORTFtobeouputpot Equivalent Circuit for a Single 1 Pin DATA WRITE RESET VO PIN DATA IN CONTROL PXXOUT WRITE CK RESET QB gt L V GND RESET PAXOUT
14. alid for 5V Prescaler divide ratio Timer out period 1 1 1 7ms 1 1 2 14ms 1 14 28 5 1 1 8 56ms 0 1 32 224ms 0 1 128 896ms 0 1 512 3 584ms 0 1 2048 Power on initial 14 336ms WDT TIME WDT 0 875 INTERNAL OUT PERIOD 7ms PRESCALER TMO RC OSC SCALER 1 18 f FINAL WDT TIME OUT PERIOD 4 0 5 6622 SH6622A has 8 bit timer The time counter has the following features 8 bit timer counter Readable and writeable Automatic reloadable counter 8 prescaller scale is available Internal and external clock select Interrupt on overflow from FF to 00 Edge select for external event Following is a simplified timer block diagram TO TOE TOS 4 1 Configuration and Operation consists of an 8 bit write only timer load register TLOL TLOH and an 8 bit read only timer counter TCOL TCOH The counter and load register both have low order digits and high order digits The timer counter can be initialized by writing data into the timer load register TLOL TLOH Load register programming Write the low order digit first and then the high order digit The timer counter is loaded with the content of load register automatically when the high order digit is written or counter counts overflow from FF to 00 Timer Load Register Since the register H woul
15. aved for CY 4 levels are the maximum allowed for subroutine calls and interrupts The contents of Stack are returned sequentially to the PC with the return instructions RTNI RTNW Stack is operated on a first in last out basis This 4 level nesting includes both subroutine calls and interrupts requests Note that program execution may enter an abnormal state if the number of calls and interrupt requests exceed 4 and the bottom of stack will be shifted out The SH6622A can address up to 4096 X 16 bit of program area from 000 to FFF Service routine as starting vector address Vector Address Area 000 to 004 The program is sequentially executed There is an area address 000 through 004 that is reserved for a special interrupt service routine such as starting vector address Address Instruction Function 000H JMP instruction Jump to RESET service routine 001H NOP Reserved 002H JMP instruction Jump to TIMERO service routine 003H NOP Reserved 004H JMP instruction Jump to PBC service routine 5 6622 3 Built in RAM consists of general purpose data memory system register Direct addressing one instruction can access ata memory and system register The following is the memory allocation map 000 01F System register and 1 020 0BF Data memory 160 X 4 bits The configuration of system Register Address Remarks 00 Inter
16. d control the physical READ and WRITE operation Please follow these rules Write Operation Low nibble first High nibble to update the counter 4 2 TimerO Interrupt SYSTEM CLOCK 8 BIT COUNTER PRE SCALER TOM Read Operation High nibble first Low nibble followed Load Reg L Load Reg H 8 bit timer counter Latch Reg L The timer overflow will generate an internal interrupt request when the counter counts overflow from FF to 00 If the interrupt enable flag is enabled then a timer interrupt service routine will proceed This can also be used to wake CPU from HALT mode 5 6622 4 3 0 mode register The timer be programmed in several different prescaler ratios by setting Timer Mode register TMO The 8 bit counter counts prescaler overflow output pulses The timer mode registers TMO are 3 bit registers used for timer control as shown in table1 These mode registers select the input pulse sources into the timer Table 1 Timer 0 Mode Register 02 Prescaler Divide Ratio Ratio N 12 2048 initial 512 128 32 8 4 2 4 4 External Clock Event T0 as Timer0 Source When external clock event input is used for TMO it is synchronized with CPU system clock Therefor the external source must follow certain constrains The output from TOM multiplex is TOC It is sampled by system clock in instruction frame cycle Ther
17. ection Circuit 2 VDD R1 5 10 R2 5 40K RESET VCC99HS RESET will be pulled to GND when VDD X R1 R1 R2 is lower than 0 7V 23 Bonding Diagram Pad No ON Oo WwW 11 12 13 14 5 6622 Designation PE2 PE3 GND1 PF 1 PA2 PA3 TO RESET GND PBO PB 1 PB2 PB3 GND2 PDO PD 1 1 GND1 GND2 amp GND3 BONDING TO GROUND 2 SUBSTRATE CONNECTED TO GROUND 94 00 38 40 164 40 290 40 422 80 543 80 700 60 700 60 700 60 754 40 605 50 485 50 353 10 213 75 74 40 58 00 586 55 586 55 586 55 586 55 586 55 586 55 584 30 441 40 188 65 537 75 586 55 586 55 586 55 586 55 586 55 586 55 Pad No 15 16 17 18 19 20 21 22 23 24 25 26 27 28 24 RESET Designation PD2 PD3 PCO PC 1 PC2 PC3 VDD GND3 OSCO OSCI 1 1 178 00 310 40 430 40 562 80 701 95 717 50 713 70 717 05 717 05 717 05 721 30 598 80 466 40 346 40 214 00 5 6622 unit um 586 55 586 55 586 55 586 55 586 55 276 80 95 10 34 40 188 10 311 10 586 55 586 55 586 55 586 55 586 55 5 6622 Ordering Information
18. efore it is necessary for TOC to be high at least 2 tosc and low at least 2 tosc When prescaler ratio selects 20 TOC is the same as the system clock input Therefore the requirements are as follows TOH TOCH TO high time gt 2 tosc AT TOL TOCL TO low time gt 2 tosc AT When other prescaler ratio is selected the TMO is scaled by the asynchronous ripple counter and so the prescaler output is symmetrical Then 2221 N TO TOC high time TOC low time 2 Where TO TimerO input period value The requirement is therefore gt 2tosc or TO gt Toso tht The limitation is applied for TO period time only The pulse width is not limited by this equation It is summarized as follows 4 tosc 2AT TimerO period gt N 5 6622 5 Port Interrupt PBC interrupt amp PORTO 8bits is falling edge active It means that if an interrupt request IEx is set to 1 and one port bit is high go low is been touched and that the condition is the other port bits are high level Only input port can generate interrupt 6 System Clock and Oscillator System clock generator produces the basic clock pulses that provide the system clock with CPU and peripherals Instruction cycle time 1 4 32 768KHz 122us for 32 768KHz system clock 2 4 4MHz 1us for AMHz system clock Oscillator 1 Crystal oscillator 32 768KHz 4MHz C1 C1 C2 Setting Crystal 32 7
19. input timer clock counter 5 PORTA F VCC99HS AP3 1 Operating voltage 5 0V 2 Oscillator RC 400KHz 3 For high reliability C1 is better to be added 4 PORTA E 2 470KQ 1000pF 1 0 OSCI VCc99HS 20 1 PORTA as scan KEYBOARD 32 keys 2 PORTD F I O Pull high resistor 47 PORTD PCO PC1 PORTF PC2 1 2 VCC99HS 2 21 5 6622 5 Weight Scale 1 Operating voltage 5 0V 2 Oscillator Ceramic resonator 4MHz 3 Port A0 External interrupt input for ON OFF switch 4 Port E2 E3 F1 A2 S4 81 analog switch control signals that control Vil to be charged and discharged by both the reference voltage Vref and the amplified voltage Vo The charged and discharged times are determined by the values of C1 R4 and the threshold voltage of To input pin and the ADC resolution could be up to 8 bit 5 Other Ports Sink seven segment LED current directly O 199 can be displayed in this configuration Instrumentation Amplifier R6 Vo 1 2R2 R1 R4 R3 Vi 47K 120 470P 22 5 6622 AP6 Reset Protection Circuit 1 VCC99HS RESET will be pulled to GND when goes lower than Zener voltage 0 7V Reset Prot
20. ruction 11000 RTNWH L 11010 000h hhh 2 00 Immediate data ROM page 0 s Table Branch Register 13 1 OSC 0562 0561 0560 OSC type 0 0 0 External Default 1 0 0 RC 1 1 0 X tal 400K 4MHz 1 0 1 Ceramic 1 1 1 X tal 32 768KHz 2 WDT EN 0 Enable Default 1 Disable 14 SH6622A 5 6622 Absolute Maximum Rating Comments DC Supply 0 3V to 7 0 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to this device These Input 0 3 0 3 stress ratings only Functional operation of this device under these or any other conditions above those indicated in Operating Ambient Temperature 10 C to 60 C the operational sections of this specification is not implied or intended Exposure to the absolute maximum rating conditions Storage 55 125 C for extended periods may affect device reliability DC Electrical Characteristics 5 0V GND 25 Fosc 4MHz unless otherwise specified Parameter in Condition Operating Voltage All output pins unloaded Execute NOP instruction Stand by Current HALT All output pins unloaded All output pins unloaded Stand by Current STOP off If LPD on Isg2 34
21. rupt enable flags 01 Interrupt request flags 02 TimerO Mode register Prescaler 03 Reserved 04 TimerO load counter register low digit 05 TimerO load counter register high digit 06 Reserved LPD Enable Control LPD3 0 07 LPD2 LPD1 LPDO 1010 LPD Enable Default 0101 LPD Disable 08 2 0 09 2 1 0 0 2 1 0 0B PD 2 PD 1 PD O PORTD 0C PE 2 0 00 1 PF 0 PORTF 0E TBR 2 TBR 1 TBR O Table Branch Register 0F INX 2 INX 1 INX O Pseudo index register 10 DPL 2 DPL 1 DPL O Data pointer for INX low nibble 11 DPM 2 DPM 1 0 Data pointer for INX middle nibble 12 DPH 2 DPH 1 DPH O Data pointer for INX HIGH nibble 13 15 Reserved 16 PA3OUT 2 PA1OUT Set PORTA to be output port 17 PB2OUT PB1OUT PBOOUT Set PORTB to be output port 18 PC3OUT PC2OUT PC1OUT Set PORTC to be output port 19 PD2OUT PD1OUT PDOOUT Set PORTD to be output port 1A PE2OUT PE1OUT PEOOUT Set PORTE to be output port 1B PF1OUT PFOOUT Set PORTF to be output port signal edge Bit1 TO signal source 1D Reserved 1E Bit3 WDT time out write 1 only 1F Reserved 1C TOS TOE System Register 500 12 except 07

SH6622A

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