LC87F7932B - ON Semiconductor
Contents
1. Specification Parameter Symbol Pin Remarks Conditions T_T VppIV min typ max unit Onboard IDDFW 1 Vpp 1 e Excluding power dissipation in programming the microcontroller block 3 0 to 5 5 5 10 mA current Programming tFW 1 e Erasing operation 20 30 ms _ A 3 0to 5 5 time tFW 2 Programming operation 45 60 us UART Full Duplex Operating Conditions at Ta 40 C to 85 C Vss1 Vss2 OV Specification Parameter Symbol Pin Remarks Conditions VpplV min typ max unit Transfer rate UBR UTX P00 2 4 to 3 6 16 3 8192 3 tCYC URX P01 Data length 7 8 9 bits LSB first Stop bits 1 bit 2 bits in continuous data transmission Parity bits None Example of 8 bit Data Transmission Mode Processing Transmit Data 55H Start bit Stop bit Start of End of transmission Transmit data LSB first transmission Sm coal MEE 2 mend UBR Example of 8 bit Data Reception Mode Processing Receive Data 55H Start bit Stop bit Start of End of reception Receive data LSB first reception En y WS ee nd UBR No A1841 25 30 LC87F7932B Characteristics of a Sample Main System Clock Oscillator Circuit Given below are the characteristics of a sample main system clock oscillator circuit which are measured using a Our designated oscillation characteristics evaluation board and external components with circuit constant values with normal and stable oscillation confirmed by the resonator vendor2. Base Timer LCD Controller INTO to 3 Noise Filter Timer 4 Timer 5 Bus Interface Port 0 Timer 7 k gt PC 3 ACC iF B Register H y C Register RES ALU ee PSW RAR La RAM mn Stack Pointer gt Watchdog Timer On chip Debugger i No A1841 10 30 Pin Description LC87F7932B Pin Name 1 0 Description Option Vss1 Vss2 Power supply No Vpp1 Vpp2 V2 e Power supply No VDC Internal power supply No CUP1 CUP2 Capacitor connecting pins for step up step down circuits No Port 0 VO 8 bit I O port Yes POO to P07 e I O can be specified in 1 bit units e Pull up resistors can be turned on and off in 1 bit units HOLD release input e Port 0 interrupt input e Multiplexed functions P00 UART1 transmit data output P01 UART1 receive data input P04 System clock output P05 DBGPO LC87F7932B P06 Timer 6 toggle output DBGP1 LC87F7932B P07 Timer 7 toggle output DBGP2 LC87F7932B AD converter input ports ANO P00 to AN4 P04 Port 1 VO 8 bit I O port Yes P10 S24 to e 1 O can be specified in 1 bit units P17 S31 e Pull up resistors can be turned on and off in 1 bit units e Multiplexed functions P10 SIOO data output P11 SIOO data input or bus I
3. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Resonator oh ba Operating Oscillation Circuit Constant FN 8 Nominal Vendor Voltage Stabilization Time Resonator Name Remarks Frequency Name Ci C2 Rf Rdi Range typ max pF pF Q Q VI ms ms CSTCR4M0O0G53 RO 15 15 Open 1k 2 4 to 3 6 0 03 0 15 Internal 4 00MHz Murata CSTLS4M00G53 BO 15 15 Open 1k 2 4 to 3 6 0 02 0 15 Ci C2 The oscillation stabilization time is the period required for the resonator to stabilize in the following situations See Figure 4 e After VDD goes above the operating voltage lower limit until the oscillation is stabilized e After the instruction for starting the main clock oscillation circuit is executed until the oscillation is stabilized e After HOLD mode is released until the oscillation is stabilized e After HOLD mode is released and oscillation is started with CFSTOP OCR register bit0 set to O until the oscillation is stabilized Characteristics of a Sample Sub system Clock Oscillator Circuit Given below are the characteristics of a sample sub system clock oscillator circuit which are measured using a Our designated oscillation characteristics evaluation board and external components with circuit constant values with normal and stable oscillation confirmed by the resonator vendor Different evaluation boards are used for Tables 2 and 3 Table
4. tal 32 768kHz crystal oscillation e System clock set to high speed 2 4 to 3 6 68 280 internal RC oscillation VMRC oscillation stopped 1 1 frequency division ratio IDDHALT 3 HALT mode FmCF 0Hz Oscillation stopped e FsX tal 32 768kHz crystal oscillation e System clock set to low speed 2 4 to 3 6 7 85 internal RC oscillation e VMRC oscillation stopped e 1 1 frequency division ratio IDDHALT 4 HALT mode e FmCF 0Hz Oscillation stopped FsX tal 32 768kHz crystal oscillation e Internal RC oscillation stopped 2 4 to 3 6 650 1460 e System clock set to 4MHz VMRC oscillation 1 1 frequency division ratio IDDHALT 5 HALT mode FmCF 0Hz Oscillation stopped e FsX tal 32 768kHz crystal oscillation e Internal RC oscillation stopped 2 4 to 3 6 68 280 e System clock set to VMRC oscillation 500kHz e 1 1 frequency division ratio IDDHALT 6 HALT mode e FmCF 0Hz Oscillation stopped e FsX tal 32 768kHz crystal oscillation e System clock set to 32 768kHz side e Internal RC oscillation stopped VMRC oscillation stopped 1 1 frequency division ratio Normal XT amp mode IDDHALT 7 HALT mode e FmCF 0Hz Oscillation stopped e FsX tal 32 768kHz crystal oscillation e System clock set to 32 768kHz side e Internal RC oscillation stopped e VMRC oscillation stopped 1 1 frequency division ratio e Low consumption XT amp mode Note 7 1 The consumption current value does not include current that flo
5. 2 Characteristics of a Sample Sub system Clock Oscillator Circuit with a Crystal Resonator 1 A Operating Oscillation Circuit Constant ne Nominal Vendor Voltage Stabilization Time Resonator Name Remarks Frequency Name C3 C4 Rf2 Rd2 Range typ max pF pF 9 9 V s s CL 7 0pF 9 9 Open 330k 2 4 to 3 6 1 3 Normal amp Epson CL 7 0pF 32 768KHz R MC 306 R Toyocom Low 3 3 Open 0 2 4 to 3 6 2 6 consumption amp Table 3 Characteristics of a Sample Sub system Clock Oscillator Circuit with a Crystal Resonator 2 5 i Oscillation i Circuit Constant Operating a Nominal Resonator Voltage Stabilization Time Vendor Name Remarks Frequency Name C3 C4 Rf2 Rd2 Range typ max pF pF Q 9 VI s s SSP T7 F CL 12 5pF 3 22 22 Open 820k 2 4to 3 6 1 8 3 Normal am 32 768kHz Seiko Instruments V1 200 F P 1 2 SSP T7 FL CL 6 0pF 4 7 6 Open 0 2 4 to 3 6 0 9 3 Low consumption VT 200 FL amp 1 Normal XT amplifier mode 3 or low consumption amplifier mode 4 should be selected for the sub system clock oscillator circuit 2 Contact Seiko Instruments Inc http www sii crystal com for further information about the use of the resonator 3 When considering the use of normal XT amplifier mode use an resonator that has a large load capacitance 4 When considering the use of low consumption
6. 3 Specified level input to at least one of INTO INT1 and INT2 pins 4 Port 0 interrupt 5 Base timer interrupt 6 RTC interrupt 7 SPI interrupt by receiving 1 byte 8 bit clock BOn chip Debugger e Supports software debugging with the IC mounted on the target board EPackage Form e QIP64E 14x14 Lead and halogen free product e TQFP64J 7x7 Lead and halogen free product e SQFP64 10x10 Lead and halogen free product EDevelopment Tools e On chip debugger TCB87 TypeB LC87F7932B Flash ROM Programming Boards Package Programming Boards QIP64E 14x14 W87F70256Q TQFP64J 7x7 W87F70256TQ7 SQFP64 10x10 W87F79256SQ No A1841 5 30 LC87F7932B BFlash ROM Programmer Maker Model Supported Version Device Single AF9708 AF9709 AF9709B Rev 03 04 or later Flash Support Group Inc 7 E ve sj AF9723 Main unit Rev Ox xx or later LC87F2832A Formerly Ando Electric Co Ltd Ganged AF9833 Unit Rev 0x xx or later p SKK SKK Type B Application Version Single ganged SANYO FWS 1 05A or later Our company LC87F7932B Onboard SKK SKK Type B Chip Data Version Single ganged SANYO FWS 2 25 or later For information about AF Series Flash Support Group Inc TEL 81 53 459 1050 E mail sales j fsg co jp No A1841 6 30 LC87F7932B Package Dimensions Package Dimensions unit mm typ unit mm typ 3159A 3
7. Ceramic resonator Cac Capacitor for ceramic oscillator Cpc Capacitor for ceramic oscillator Refer to Page 26 Characteristics of a sample clock oscillator circuit C1 to C4 Capacitors 0 1uF recommended CDEN Electrolytic capacitor For back up CRES Capacitor for RES RRES Resistor for RES Refer to User s manual Reset Function No A1841 15 30 LC87F7932B Absolute Maximum Ratings at Ta 25 C and Vss1 Vss2 0V Specification Parameter Symbol Pin Remarks Conditions VpplV min typ max unit Maximum supply VDD max Vpp1 Vpp2 V2 Vop1 Vpp2 V2 03 5A voltage Supply voltage VLCD vi 0 3 1 2Vpp for LCD v2 0 3 VDD V3 0 3 2 3Vpp V Input voltage Vi XT1 CF1 RES 0 3 Vpp 0 3 Input output Vio 1 Ports 0 1 3 7 voltage LPA LPB LPC 0 3 Vpp 0 3 LPL XT2 Peak IOPH 1 Ports 0 1 CMOS output selected 40 output e Current at each pin current IOPH 2 Port 3 CMOS output selected 20 5 IOPH 3 LPA LPB LPC CMOS output selected A 3 LPL e Current at each pin 3 IOPH 4 P71 to P73 e Current at each pin 5 E Total XIOAH 1 Port 0 Total of all pins 20 output XIOAH 2 Ports 3 7 Total of all pins 30 5 current T XIOAH 3 Port 1 Total of all pins 20 XIOAH 4 Ports 1 3 7 Total of all pins 45 XIOAH 5 LPA LPB LPC Total of all pins 30 LPL mA Peak IOPL 1 Ports 0 1 Curren
8. GND in the input buffer If VDD and Vpp2 are not backed up configure the program or set up the external circuit so that the output is held at a low level in HOLD mode to prevent an unnecessary through current from flowing Power supply For back up IC MEE Vpp1 gt VDD2 V1 HHHH HH V2 V3 VDG Vss1 Vss2 CUP1 CUP2 E No A1841 13 30 Circuit Example 1 1 3 bias 1 4 duty LC87F7932B LCD panel 24SEGx4COM 1 0 1 0 1 Crystal oscillator 2 Ceramic oscillator X tal Crystal resonator Refer to Page 26 Cex Trimmer capacitor Characteristics of a sample clock oscillator Cpx Capacitor for crystal oscillator circuit CF Ceramic resonator Refer to Page 26 Cac Capacitor for ceramic oscillator Characteristics of a sample clock oscillator Cpc Capacitor for ceramic oscillator EN C1 to C5 Capacitors 0 1uF recommended CDEN Electrolytic capacitor For back up CRES Capacitor for RES Refer to User s manual Reset Function RRES Resistor for RES No A1841 14 30 2 1 2 bias 1 3 duty 1 0 1 0 LC87F7932B LCD panel 24SEGx3COM 1 Crystal oscillator 2 Ceramic oscillator X tal Crystal resonator CGx Trimmer capacitor Cpx Capacitor for crystal oscillator Refer to Page 26 Characteristics of a sample clock oscillator circuit CF
9. O P12 SIOO clock I O P13 SIO1 data output P14 SIO1 data input or bus I O P15 SIO1 clock I O P16 Timer 1 PWML output P17 Timer 1 PWMH output buzzer output Segment output for LCD S24 P10 to S31 S17 Port 3 VO lt 1 bit I O port Yes P30 e I O can be specified in 1 bit units e Pull up resistors can be turned on and off in 1 bit units Port 7 VO 4 bit I O port No P70 to P73 e I O can be specified in 1 bit units e Pull up resistors can be turned on and off in 1 bit units e Multiplexed functions P70 INTO input HOLD release input timer OL capture input output for watchdog timer P71 INT1 input HOLD release input timer OH capture input P72 INT2 input HOLD release input timer O event input timer OL capture input high speed clock counter input P73 INT3 input with noise filter timer O event input timer OH capture input AD converter input ports AN5 P70 AN6 P71 Interrupt acknowledge type Rising Falling Rising and falling H level L level INTO Enable Enable Disable Enable Enable INTA Enable Enable Disable Enable Enable INT2 Enable Enable Enable Disable Disable INT3 Enable Enable Enable Disable Disable Continued on next page No A1841 11 30 LC87F7932B Continued from preceding page Pin name VO Description Option S00 LPAO to VO Segment output for LCD No SO7 LPA7 e Can be used as general purpose I O ports LPA S08 LPBO to VO
10. Vss IL 4 CF1 Vin Vss 2 4 to 3 6 High level output Von 1 CMOS output ports Igy 0 4mA 3 0 to 3 6 voltage VoH 2 0 1 loH 0 2mA 2 4 to 3 6 VOH 3 CMOS output port 3 Igy 1 6mA 3 0 to 3 6 VoH 4 loH 1mA 2 4 to 3 6 VohH 5 P71 to 73 loH 0 4mA 3 0 to 3 6 VoH 6 loH 0 2mA 2 4 to 3 6 V 7 LPA LPB LPC lOH 0 1mA OH OH 2 4 to 3 6 LPL Low level output VoL 1 Ports 0 1 loL 1 6mA 3 0 to 3 6 0 4 voltage VoL 2 loL 1mA 2 4 to 3 6 0 4 VoL 3 Port 3 IOL 5MA 3 0 to 3 6 0 4 VoL loL 2 5mA 2 4 to 3 6 0 4 ES VoL 5 Port 7 loL 1 6mA 3 0 to 3 6 0 4 VoL 6 xT2 loL 1MA 2 4 to 3 6 0 4 Vor 7 LPA LPB LP lo 0 1mA out a OLA 2 4 to 3 6 0 4 LPL LCD output voltage VODLS S00 to S31 e lO 0mA deviation e V1 V2 V3 Hu 2 4 to 3 6 0 2 LCD level output e See Fig 8 VODLC COMO to COM3 g 0mA e V1 V2 V3 2 4 to 3 6 0 2 LCD level output e See Fig 8 Pull i Rpu 1 Ports 0 1 3 7 VoH 0 9V Hi pu 1 s OH SDD 2 4 to 3 6 50 150 ka Hysterisis voltage VHYS 1 Ports 1 7 te Oy tc 2 4 to 3 6 0 1Vpp v RES Pin capacitance CP All pins e For pins other than that nder test V y V E IN Y88 2 4 to 3 6 10 pF e f 1MHz e Ta 25 C No A1841 18 30 LC87F7932B Serial I O Characteristics at Ta 40 C to 85 C Vss1 Vss2 0V 1 SIOO Serial I O Characteristics Note 4 1 1 Specification Parameter Symbol Pin
11. channel open drain COMO LPLO to No CMOS No COM3 LPL3 P channel open drain N channel open drain XT1 a No Input only No XT2 No 32 768kHz crystal resonator output No N channel open drain when selected as a general purpose output port No A1841 12 30 User Option Table LC8 7F7932B Option to be Mask Version Flash ROM Option Selected Option Name 4 Option Selection Applied on Version in Units of Port output type POO to P07 CMOS O 1 bit N channel open drain P10to P17 CMOS O 1 bit N channel open drain P30 CMOS O 1 bit N channel open drain Base timer Watchdog timer 1 second watchdog timer detection period 2 seconds O 4 seconds 8 seconds Program start 00000h address 2 o 07E00h 1 Mask option selection No change possible after mask is completed 2 Program start address of the mask version is 00000h Note 1 Connect the IC as shown below to minimize noise on the VDD1 Be sure to electrically short the VsS1 and Vss2 Note 2 The power to retain the internal memory is supplied via the V2 pin VDD1 Vpp2 and V2 are used as power supply for ports If VDD1 and Vpp2 are not backed up the output does not go high even if a high level is applied to the port latch Therefore if Vppl and Vpp2 are not backed up the high level output becomes unstable in HOLD mode and the backup time becomes shorter because a through current flows from Vpp to
12. falling edge of SIOCLK Must be specified as the time up to the beginning of output state change in open drain output mode See Fig 6 No A1841 19 30 LC87F7932B 2 SIO1 Serial I O Characteristics Note 4 2 1 Specification Parameter Symbol Pin Remarks Conditions VoplV min typ max unit Frequency tSCK 3 SCK1 P15 See Fig 6 2 Low level tSCKL 3 p pulse width 2 4 to 3 6 a tCYC High level tSCKH 3 i pulse width E y Frequency tSCK 4 SCK1 P15 CMOS output selected 2 2 8 Low level tSCKL 4 See Fig 6 1 2 3 pulse width 2 4 to 3 6 HER 8 High level tSCKH 4 a pulse width Data setup time tsDI 2 SB1 P14 e Must be specified with oa SI1 P14 respect to the rising edge 0 03 of SIOCLK ee Data hold time thDI 2 See Fig 6 9 0 03 Output delay time tdDO 4 SO1 P13 e Must be specified with ig SB1 P14 respect to the falling edge 2 of SIOCLK 3 Must be specified the SAVE 1 3 tC YC 3 time up to the beginning 0 05 B of output state change in open drain output mode e See Fig 6 Note 4 2 1 These specifications are theoretical values Be sure to add margin depending on its use Pulse Input Conditions at Ta 40 C to 85 C Vss1 Vss2 0V Specification Parameter Symbol Pin Remarks Conditions VppIV min typ max unit High low level tPIH 1 INTO P70 Interrupt source flag can be se
13. for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PS No A1841 30 30
14. oscillation OpVMRC 1 When VMSL4M 0 3 0 to 3 6 8 10 12 MHz osaberange OpVMRC 2 When VMSL4M 1 2 4 to 3 6 3 5 4 45 VMRC oscillation VmADJ 1 Each step of VMRAJn adjustment Wide range 2 4 to 3 6 8 24 64 range VmADJ 2 Each step of VMFAJn 2 4to 3 6 1 4 8 Small range Note 2 1 VDD must be held greater than or equal to 3 0V in the flash ROM onboard programming mode Note 2 2 Relationship between tCYC and oscillation frequency is 3 FmCF at a division ratio of 1 1 and 6 FmCF at a division ratio of 1 2 Note 2 3 See Tables 1 and 2 for the oscillation constants No A1841 17 30 Electrical Characteristics at Ta 40 C to 85 C Vgs1 Vss2 0V LC87F7932B Specification Parameter Symbol Pin Remarks Conditions 7 VpplV typ max unit High level input WH Ports 0 1 3 7 e Output disabled current LPA LPB LPC e Pull up resistor off LPL e Vin VDD 2 4 to 3 6 1 Including output Tr s off leakage current IjH 2 RES Vin VDD 2 4 to 3 6 1 HH 3 XT1 XT2 Input port specification HG PRE p 2 4 to 3 6 1 Vin VDD 11H 4 CF1 VIN VDD 2 4 to 3 6 15 F Low level input IL Ports 0 1 3 7 Output disabled A current LPA LPB LPC e Pull up resistor off LPL Vin Vss 2 4 to 3 6 Including output Tr s off leakage current Ir 2 RES Vin Vss 2 4 to 3 6 Le XT1 XT2 e Input port specification IL S ei 2 4 to 3 6 ViN
15. 289 17 2 14 0 48 33 x AARARARARBRAAE sE 32 M Li Ji VEE es 0 8 0 35 0 15 1 0 1 2max 3 0max TQFP64J 7X7 QIP64E 14X14 Package Dimensions unit mm typ 3190A 0 5 0 15 1 7max SQFP64 10X10 No A1841 7 30 LC87F7932B Pin Assignment S23 LPC7 S22 LPC6 S21 LPC5 S20 LPC4 S19 LPC3 S18 LPC2 S17 LPC1 S16 LPCO S15 LPB7 S14 LPB6 S13 LPB5 S12 LPB4 S11 LPB3 S10 LPB2 SO9 LPB1 S08 LPBO or LO St Nr D OD Y st Y Y e 4 NANO RES 49 32 gt SO7 LPA7 XT1 50 31 S06 LPA6 XT2 51 30 E S05 LPA5 Vss1 52 29 SO4 LPA4 CF1 EY 53 28 1 S03LPA3 CF2 od 54 27 S02 LPA2 Vpp1 Td 55 26 1 SO1 LPA1 POO UTX1 ANO Ed 56 25 SOO LPAO PO1 RTX1 AN1 57 LC87F7932B 24 COM3 LPL3 PO2 AN2 58 23 gt COM2 LPL2 PO3 AN3 59 22 COM1 LPL1 PO4 CKO AN4 Td 60 21 COMO LPLO P05 DBGPO 61 20 V3 P06 T6O DBGP1 T 62 19 v2 P07 T70 DBGP2 Td 63 18 E gt vi P30 64 eens 17 VDE NO Tw OR QD venen nn E a SSZZAPAR SATS HES SESS 8888588 R8855 EESSPPSSSrereEINDO 598227 9mSo0m2 5 23Ioz DRHRODROSa eses SSL Sar SEAR Za aSr EEZO ro Yage ZEN a a gf Top view e N a E p Ere X a QIP64E 14
16. Ordering number ENA1841A LC87F7932B CMOS IC 32K byte FROM and 2048 byte RAM integrated 8 bit 1 chip Microcontroller ON Semiconductor http onsemi com Overview The LC87F7932B is an 8 bit microcontroller that centered around a CPU running at a minimum bus cycle time of 250ns integrates on a single chip a number of hardware features such as 32K byte flash ROM onboard programmable 2048 byte RAM an on chip debugger an LCD controller driver two sophisticated 16 bit timers counters may be divided into 8 bit timers two 16 bit timers counters may be divided into 8 bit timers counters or 8 bit PWMs four 8 bit timers with a prescaler a real time clock function RTC a base timer serving as a time of day clock a synchronous SIO interface with automatic transfer function an asynchronous synchronous SIO interface a UART interface full duplex a 7 channel AD converter with a 12 8 bit resolution selector a high speed clock counter a system clock frequency divider an internal reset circuit and a 21 source 10 vector interrupt function Features EFlash ROM e Capable of on board programming with a wide supply voltage range of 3 0V to 5 5V e 128 byte block erase e 32768 x 8 bits BRAM e 2048 x 9 bits Minimum Bus Cycle Time e 250ns 4MHz Vpp 24V to 3 6V Note The bus cycle time here refers to the ROM read speed E Minimum Instruction Cycle Time tC YC e 750ns 4MHz Vpp 2 4V to 3 6V This product is licensed fro
17. Remarks Conditions VppIV min typ max unit Frequency tSCK 1 SCKO P12 See Fig 6 2 Low level tSCKL 1 A pulse width A 4 8 High level tSCKH 1 1 O 5 pulse width tSCKHA 1 Continuous data 2 4 to 3 6 a tCYC transmission reception mode 4 C e See Fig 6 8 Note 4 1 2 oO T Frequency tSCK 2 SCKO P12 CMOS output selected 4 3 a Low level tSCKL 2 See Fig 6 es pulse width x A tSCK S High level tSCKH 2 1 2 Pulse wiern 2 4 to 3 6 g tSCKHA 2 Continuous data O transmission reception tSCKH 2 p tSCKH 2 2 mode 10 3 tCYC 2tCYC CMOS output selected tCYC e See Fig 6 Data setup time tsDI 1 SBO P11 e Must be specified with SIO P11 respect to the rising edge 0 03 of SIOCLK 2 4 to 3 6 Data hold time thDI 1 See Fig 6 D 0 03 Output delay tdDO 1 SO0 P10 e Continuous data x time SBO P11 transmission reception 1 3 tC YC 3 mode 0 05 us El Note 4 1 3 2 tdDO 2 Synchronous 8 bit mode 1tCYC Note 4 1 3 2 4 to 3 6 0 05 8 x tdDO 3 Note 4 1 3 2 1 30 YC a 0 05 6 Note 4 1 1 These specifications are theoretical values Be sure to add margin depending on its use Note 4 1 2 In an application where the serial clock input is to be used in continuous data transmission reception mode the time from SIORUN being set when serial clock is high to the falling edge of the first serial clock must be longer than tSCKHA Note 4 1 3 Must be specified with respect to the
18. Segment output for LCD No S15 LPB7 e Can be used as general purpose I O ports LPB S16 LPCO to VO Segment output for LCD No S23 LPC7 e Can be used as general purpose I O ports LPC COMO LPLO to O Common output for LCD No COM3 LPL3 e Can be used as general purpose I O ports LPL V1 to V3 O LCD drive bias power supply No RES I e Reset pin No XT1 O e 32 768kHz crystal resonator input pin No e General purpose input port e Must be connected to Vpp1 if not to be used XT2 O 32 768kHz crystal resonator output pin No e General purpose I O port e Must be set for oscillation and kept open if not to be used CF1 l e Ceramic resonator input pin No e Must be connected to Vpp1 if not to be used CF2 O Ceramic resonator output pin No e Must be kept open if not to be used Port Output Types The table below lists the types of port outputs and the presence absence of a pull up resistor Data can be read into any input port even if it is in output mode Port options Selected m Option Output Type Pull up Resistor Units of Type POO to P07 1 bit 1 CMOS Programmable 2 N channel open drain Programmable P10 to P17 1 bit 1 CMOS Programmable 2 N channel open drain Programmable P30 1 bit 1 CMOS Programmable 2 N channel open drain Programmable P70 No N channel open drain Programmable P71 to P73 No CMOS Programmable SOO LPAO to No CMOS No S23 LPC7 P channel open drain N
19. XT amplifier mode use a resonator that has a small load capacitance The applicable CL value of 6 0pF makes it possible to achieve a high time accuracy for the subclock oscillator as well as high speed oscillation startup and low power dissipation In addition to this value 7 0pF and 9 0pF also fall within the applicable CL value range No A1841 26 30 LC87F7932B 5 A sample PCB trace pattern for a Seiko Instrument resonator is shown below MCU XT1 xT2 Vdd MCU xT1 XT2 Rd Cg T 32 768kHz Jo Vss Note 1 The oscillation stabilization time is the period required for the oscillator to stabilize in the following situations see Figure 4 e After the instruction for starting the subclock oscillator circuit is executed until the oscillation is stabilized e After HOLD mode is released and oscillation is started with EXTOSC OCR register bit 6 set to 1 until the oscillation is stabilized Note 2 The circuit constants shown are the reference values that are provided by the resonator vendor for evaluation To make final verification of the oscillation characteristics on production boards call the resonator vendor for evaluation on printed circuit boards Note 3 When using an oscillator circuit observe the following wiring precautions to avoid the possible adverse influence of wiring capacitance especially in low consumption XT amplifier mode e Place the components that are involved in oscillation as close to the resona
20. m Silicon Storage Technology Inc USA Semiconductor Components Industries LLC 2013 May 2013 Ver 1 04 41812HKIM 20120328 S00004 No A1841 1 30 LC87F7932B BOperating Temperature Range e 40 C to 85 C MPorts e Normal withstand voltage I O ports Ports whose input output can be programmed in 1 bit units 21 POn P1n P30 P70 to P73 Multiplexed functions Input ports for debugger 3 DBGPO P05 to DBGP2 P07 LCD ports segment output 8 Pln e LCD ports general purpose I O ports Segment output 32 S00 to S31 Common output 4 COMO to COM3 Bias power supply for LCD driving 5 VI to V3 CUP1 CUP2 Multiplexed functions Input output ports 36 LPAn LPBn LPCn LPLO to LPL3 P1n e Oscillator pins 4 CF1 CF2 XT1 XT2 e Reset pin 1 RES e Power supply 5 Vss1 Vss2 Vppl Vpp2 V2 ELCD Controller 1 Seven display modes are available 2 Duty 1 3 duty 1 4 duty 3 Bias 1 2 bias 1 3 bias 4 Segment common output can be switched to general purpose I O ports 5 LCD power range 1 1 3 2 1 2 ATimers e Timer 0 e Timer 1 e Timer 4 e Timer 5 e Timer 6 e Timer 7 bias V1 1 2V to 1 8V V2 2 4V to 3 6V V3 3 6V to 5 4V An LCD panel that supports the V2 Vpp X 1 5 V must be used when 1 3 bias is selected If the supply voltage Vpp is 3 0V for example use an LCD panel that supports 4 5V bias V1 1 2V to 1 8V V2 2 4V to 3 6V V3 2 4V to 3 6V Connect V2 and V3 externally A
21. marks Conditions VbplV min typ max Unit Resolution N ANO P00 to 3 0 to 3 6 8 bit Absolute ET AN4 P04 Note 6 1 Fes AN5 P70 to 3 0 to 3 6 1 5 LSB Conversion time TCAD AN6 P71 e See conversion time calculation formulas 3 0 to 3 6 40 90 us Note 6 2 Analog input VAIN 3 0 to 3 6 Vss Vin v voltage range Analog port input IAINH VAIN Vpp 3 0 to 3 6 1 current IAINL VAIN Vss 3 0 to 3 6 1 el Conversion Time Calculation Formulas 12 bit AD conversion mode TCAD conversion time 52 AD division ratio 2 x 1 3 x tCYC 8 bit AD conversion mode TCAD conversion time 32 AD division ratio 2 x 1 3 x tCYC lt Recommended Operating Conditions gt External Supply Volga Hande System Clock cjoe Tire AD Frequency Conversion Time Oscillator Division Ratio Division Ratio TCAD FMCF VoD SYSDIV eve ADDIV 12 bit AD 8 bit AD CF 4MHz 3 0V to 3 6V 1 1 750ns 1 8 104 5us 64 5us Note 6 1 The quantization error 1 2LSB is excluded from the absolute accuracy The absolute accuracy is measured in the microcontroller s state in which no I O operations occur at the pins adjacent to the analog input channel Note 6 2 The conversion time refers to the period from the time an instruction for starting a conversion process is executed until the time the conversion result register s are loaded with a complete digital conversion value corresponding to the analog input value The conversion time is doubled in the foll
22. n LCD panel that supports the V2 Vpp V must be used when 1 2 bias is selected If the supply voltage Vpp is 3 0V for example use an LCD panel that supports 3 0V 16 bit timer counter with a capture register Mode 0 8 bit timer with an 8 bit programmable prescaler with two 8 bit capture registers x 2 channels Mode 1 8 bit timer with an 8 bit programmable prescaler with an 8 bit capture register 8 bit counter with an 8 bit capture register Mode 2 16 bit timer with an 8 bit programmable prescaler with a 16 bit capture register Mode 3 16 bit counter with a 16 bit capture register 16 bit timer counter that supports PWM toggle output Mode 0 8 bit timer with an 8 bit prescaler with toggle output 8 bit timer counter with toggle output Mode 1 8 bit PWM with an 8 bit prescaler x 2 channels Mode 2 16 bit timer counter with an 8 bit prescaler with toggle output Toggle outputs also from the low order 8 bits Mode 3 16 bit timer with an 8 bit prescaler with toggle output The low order 8 bits can be used as a PWM 8 bit timer with a 6 bit prescaler 8 bit timer with a 6 bit prescaler 8 bit timer with a 6 bit prescaler with toggle output 8 bit timer with a 6 bit prescaler with toggle output e Base Timer 1 The clock can be selected from any of the following Subclock 32 768kHz crystal oscillator low speed RC oscillator system clock and timer 0 prescaler output 2 Interrupts can be generated at five specified time inter
23. nd Oscillation Stabilization Time Note Oscillation is enabled before HOLD mode is entered Figure 4 Oscillation Stabilization Time No A1841 28 30 Na n SIOCLK DATAIN DATAOUT SIOCLK DATAIN DATAOUT SIOCLK DATAIN DATAOUT LC87F7932B VDD RRES Note External circuits for reset may vary depending on the usage of POR Please refer to the user s manual on reset function CRES ZIT Figure 5 Reset Circuit a a e DIO DH DI2 DI3 DI4 DI5 D 6 DI7 X Dooi Y DO1 y Do2 X DO3 y DO4 y DOS y Dos DO7 l Data RAM SES e transfer period AAA en SIO0 only a is EK A oc gt l ISCKL e _tSCKH gt l is ISP i thDI i HDO _ gt e Data RAM Da Tiens D S SR SET transfer period EE SES SIO0 only desen tSCKkL pie tSCKHA yy Figure 7 Pulse Input Timing Waveform No A1841 29 30 LC87F7932B POR release voltage D b Pi VDD Reset undefined region Figure 8 Sample Operating Waveforms when POR is Used Reset pin Pull up resistor RRES only e The POR function generates a reset only when power is turned on starting at the VSS level e No stable reset will be generated if power is turned on again when the power level does not go down to the Vss level as shown in a e A reset is generated only when the power level goes down
24. om among 750ns 1 5us 3 0us 6 0us 12us 24us 48us 96us and 192us at a main clock rate of 4MHz System Clock Output e The system clock can be output from the P04 pin No A1841 4 30 LC87F7932B EStandby Function e HALT mode HALT mode is used to reduce power consumption Halts instruction execution while allowing the peripheral circuits to continue operation Some serial transfer functions are suspended 1 Oscillators do not stop automatically 2 Released by a system reset or occurrence of an interrupt e HOLD mode HOLD mode is used to reduce power consumption Suspends instruction execution and operation of the peripheral circuits 1 CF oscillator RC oscillators crystal oscillator and VMRC oscillator stop automatically 2 There are five ways of releasing HOLD mode 1 Low level input to the reset pin 2 Watchdog timer interrupt 3 Specified level input to at least one of INTO INT1 and INT2 pins 4 Port 0 interrupt 5 SPI interrupt by receiving 1 byte 8 bit clock e X tal HOLD mode X tal HOLD mode is used to reduce power consumption Suspends instruction execution and the operation of the peripheral circuits except the base timer 1 CF oscillator RC oscillators and VMRC oscillator stop automatically 2 The state of the crystal oscillator when X tal HOLD mode is entered is retained 3 There are seven ways of releasing X tal HOLD mode 1 Low level input to the reset pin 2 Watchdog timer interrupt
25. owing cases e The first AD conversion is performed in the 12 bits AD conversion mode after a system reset e The first AD conversion is performed after the AD conversion mode is switched from 8 bits to 12 bits conversion mode No A1841 21 30 LC87F7932B Consumption Current Characteristics at Ta 40 C to 85 C Vssl Vss2 OV Specification Parameter Symbol Pin Remarks Conditions 7 7 VppiV min typ max unit Current IDDOP 1 Vpp1 Vpp2 e FmCF 4MHz ceramic oscillation consumption in V2 e FsX tal 32 768kHz crystal oscillation normal operating e System clock set to 4MHz side mode e Internal RC oscillation stopped Note 7 1 VMRC oscillation stopped 1 1 frequency division ratio IDDOP 2 FmCF 0Hz Oscillation stopped FsX tal 32 768kHz crystal oscillation e System clock set to high speed internal RC oscillation VMRC oscillation stopped e 1 1 frequency division ratio IDDOP 3 FmCF 0Hz Oscillation stopped FsX tal 32 768kHz crystal oscillation e System clock set to low speed internal RC oscillation e VMRC oscillation stopped 1 1 frequency division ratio IDDOP 4 FmCF 0Hz Oscillation stopped FsX tal 32 768kHz crystal oscillation e Internal RC oscillation stopped e System clock set to 4MHz VMRC oscillation e 1 1 frequency division ratio IDDOP 5 FmCF 0Hz Oscillation stopped FsX tal 32 768kHz crystal oscillation e Internal RC oscillation stopped e System clock set
26. precedence No Vector Address Level Interrupt Source 1 00003H X or L INTO 2 0000BH X or L INT1 3 00013H Hor L INT2 TOL 4 0001BH Hor L INT3 base timer RTC 5 00023H HorL TOH 6 0002BH HorL T1L T1H 7 00033H Hor L SIOO UART1 receive 8 0003BH HorL SIO1 UART send 9 00043H Hor L ADC T6 T7 SPI 10 0004BH Hor L Port 0 T4 T5 e Priority level X gt H gt L e For equal priority levels the interrupt with the lowest vector address is given priority ESubroutine Stack Levels e Up to 1024 levels max Stack is allocated in RAM E High speed Multiplication Division Instructions e 16 bits x 8 bits 5 tCYC execution time e 24 bits x 16 bits 12 tC YC execution time e 16 bits 8 bits 8 tCYC execution time e 24 bits 16 bits 12 tC YC execution time Oscillator Circuits e On chip high speed RC oscillator For system clock 500kHz typ e On chip low speed RC oscillator For system clock 50kHz typ e CF oscillator For system clock Rf built in Rd external e Crystal oscillator For low speed system clock Rf built in e On chip variable modulation frequency RC oscillator VMRC For system clock 1 Adjustable in 4 typ step from a selected center frequency 2 Can measure the frequency of the source oscillator clock using an input signal from the XT1 pin as a reference System Clock Divider e Low consumption current operation possible e The minimum instruction cycle can be selected fr
27. r Circuit multiplexed with the P73 INT3 TOIN pin e Noise rejection function Noise filter time constant selectable from 1 32 128 tCYC B Watchdog Timer e Generation of interrupt or system reset selectable e Two types of watchdog timer 1 Watchdog timer using an external RC circuit 2 Watchdog timer using the microcontroller s base timer e Detection intervals 1 2 4 8 seconds can be selected for the watchdog timer that uses the base timer by configuring options BBuzzer Output e Generates buzzer output from P17 using the base timer Real Time Clock RTC 1 Uses the base timer to count the calendar years months days hours minutes and seconds 2 Calendar counts up to December 31 2799 and calculates leap years automatically 3 The RTC uses the Gregorian calendar which maintains GMT Greenwich Mean Time EiInternal Reset Function e Power on reset POR function 1 The POR causes a system reset only when power is turned on No A1841 3 30 LC87F7932B Elnterrupts e 21 sources 10 vectors 1 Provides three levels low L high H and highest X of multiplex interrupt control Any interrupt request of the level equal to or lower than the current interrupt is not accepted 2 When interrupt requests to two or more vector addresses occur at the same time the interrupt of the highest level takes precedence over the other interrupts For interrupts of the same level the interrupt into the lowest vector address takes
28. t pulse width tPIL 1 INT1 P71 e Event inputs for timer 0 2 4 to 3 6 1 INT2 P72 are enabled tPIH 2 INT3 P73 when Interrupt source flag can be set tPIL 2 noise filter time Event inputs for timer 0 are 2 4 to 3 6 2 constant is 1 1 enabled YG tPIH 3 INT3 P73 when Interrupt source flag can be set tPIL 3 noise filter time Event inputs for timer 0 are 2 4 to 3 6 64 constant is 1 32 enabled tPIH 4 INT3 P73 when Interrupt source flag can be set tPIL 4 noise filter time Event inputs for timer 0 are 2 4 to 3 6 256 constant is 1 128 enabled tPIL 5 RES Resetting is enabled 2 4 to 3 6 200 us No A1841 20 30 LC87F7932B AD Converter Characteristics at Vss1 Vss2 0V lt 12 bit AD Conversion Mode at Ta 40 C to 85 C gt Specification Parameter Symbol Pin Remarks Conditions VopIV min typ max unit Resolution N ANO P00 to 3 0 to 3 6 12 bit Absolute ET AN4 P04 Note 6 1 eenen AN5 P70 to 3 0 to 3 6 16 LSB Conversion time TCAD AN6 P71 e See conversion time calculation formulas 3 0 to 3 6 64 115 us Note 6 2 Analog input VAIN 30136 Vss dn v voltage range Analog port input IAINH VAIN Vpp 3 0 to 3 6 1 current IAINL VAIN Vsg 3 0 to 3 6 1 c lt 8 bit AD Conversion Mode at Ta 40 C to 85 C gt Specification Parameter Symbol Pin Re
29. t at each pin 20 output IOPL 2 Port 3 Current at each pin 30 current IOPL 3 Port 7 Current at each pin 10 IOPL 4 LPA LPB LPC Current at each pin 6 5 LPL El Total XIOAL 1 Port 0 Total of all pins 40 E output YIOAL 2 Ports 3 7 Total of all pins 50 3 current YIOAL 3 Port 1 Total of all pins 40 a XIOAL 4 Ports 1 3 7 Total of all pins 65 XIOAL 5 LPA LPB LPC Total of all pins dd LPL Allowable power Pd max QIP64E 14x14 Ta 40 C to 85 C 267 dissipation TQFP64J 7x7 152 mW SQFP64 10x10 192 Operating Topr temperature 40 85 range C Storage Tstg temperature 55 125 range Stresses exceeding Maximum Ratings may damage the device Maximum Ratings are stress ratings only Functional operation above the Recommended Operating Conditions is not implied Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability No A1841 16 30 LC87F7932B Allowable Operating Conditions at Ta 40 C to 85 C Vgs l Vss2 0V Specification Parameter Symbol Pin Remarks Conditions VbplV min typ max unit Operating supply Vpp 1 Vpp1 Vpp2 V2 0 75usstCYC lt 200us voltage Normal mode 24 3 6 Note 2 1 Memory VHD Vpp1 Vpp2 V2 RAM and register contents sustaining sustained in HOLD mode 2 2 3 6 supply voltage High level input Vin Ports 0 3 Output disabled 0 3V g p 1401 p 24t036 DD VDD vol
30. tage LPA LPB LPC LPL 0 7 ViH 2 Port 1 Output disabled P71 to 73 e When INT1VTSL 0 0 3VDD 2 4 to 3 6 VDD P70 port input P71 only 0 7 interrupt side VIHG P71 interrupt side Output disabled 2 4 to 3 6 0 85VDD VDD e When INT1VTSL 1 ViH 4 P70 watchdog timer Output disabled y 2 4 to 3 6 0 9Vpp VDD side ViH 5 XT1 XT2 CF1 RES 2 4t03 6 0 75Vpp Vpp Low level input ViL 1 Ports 0 3 Output disabled 2 4 to 3 6 Vss 0 2VDD voltage LPA LPB LPC LPL VIL 2 Port 1 Output disabled P71 to 73 e When INT1VTSL 0 2 4 to 3 6 Vss 0 2Vpp P70 port input P71 only interrupt side ViL 3 P71 interrupt side Output disabled 2 4 to 3 6 Vss 0 45VDD e When INT1VTSL 1 VIL 4 P70 watchdog timer Output disabled 0 8V IL 3 j 2 4 to 3 6 Vss Be side 1 0 VIL 5 XT1 XT2 CF1 RES 2 4 to 3 6 Vss 0 25VDD Instruction cycle tCYC time 2 4 to 3 6 200 us Note 2 2 External system FEXCF 1 CF1 e CF2 pin open clock frequency e System clock frequency division ratio 1 1 2 4 to 3 6 0 1 4 e External system clock MHz duty 50 5 e CF2 pin open e System clock frequency 2 4 to 3 6 0 2 8 division ratio 1 2 Oscillation FmCF 1 CF1 CF2 4MHz ceramic oscillation 2 4 to 3 6 4 MHz frequency range e See Fig 1 Note 2 3 FmRC 1 Internal high speed RC ne 2 4 to 3 6 250 500 750 oscillation FsRC 1 Internal low speed RC ae 2 4 to 3 6 25 50 75 oscillation kHz FsX tal XT1 XT2 32 768kHz crystal oscillation 2 4 to 3 6 32 768 e See Fig 2 VMRC
31. to 500kHz VMRG oscillation 1 1 frequency division ratio IDDOP 6 FmCF 0Hz Oscillation stopped FsX tal 32 768kHz crystal oscillation e System clock set to 32 768kHz side e Internal RC oscillation stopped 2 4to 3 6 20 86 VMRC oscillation stopped 1 1 frequency division ratio Normal XT amp mode IDDOP 7 FmCF 0Hz Oscillation stopped e FsX tal 32 768kHz crystal oscillation e System clock set to 32 768kHz side e Internal RC oscillation stopped 2 4to 3 6 15 72 e VMRC oscillation stopped 1 1 frequency division ratio e Low consumption XT amp mode Note 7 1 The consumption current value does not include current that flows into the output transistors and internal pull up resistors 2 4 to 3 6 2 0 4 2 mA 2 4 to 3 6 250 900 HA 2 4 to 3 6 30 120 2 4 to 3 6 2 0 5 4 mA 2 4 to 3 6 250 900 uA Continued on next page No A1841 22 30 LC87F7932B Continued from preceding page Specification Parameter Symbol Pin Remarks Conditions E VppIV min typ max unit Current IDDHALT 1 Vpp1 Vpp2 HALT mode consumption V2 FMCF 4MHZ ceramic oscillation in HALT mode e FsX tal 32 768kHz crystal oscillation Note 7 1 e System clock set to 4MHz side 2 4 to 3 6 0 55 1 55 mA e Internal RC oscillation stopped VMRC oscillation stopped 1 1 frequency division ratio IDDHALT 2 HALT mode FmCF 0Hz Oscillation stopped e FsX
32. to the Vss level as shown in b and power is turned on again after this condition continues for 1000us or longer ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries LLC SCILLC SCILLC owns the rights to a number of patents trademarks copyrights trade secrets and other intellectual property A listing of SCILLC s product patent coverage may be accessed at www onsemi com site pdf Patent Marking pdf SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or
33. tor as possible with the shortest possible traces as the oscillation characteristics are subject to the variation of trace patterns e Do not take a signal directly from the oscillator circuit e Do not place the oscillator circuit in the vicinity of any lines that carry large current e Exercise extreme care in the wiring method when using low consumption XT amplifier mode CF1 CF2 XT1 XT2 Rf1 Rd1 cde HE de a Figure 1 CF Oscillator Circuit Rf2 Rd2 Ld Figure 2 XT Oscillator Circuit Figure 3 AC Timing Measurement Point No A1841 27 30 LC87F7932B Vpp Power supply Enne 1 VDD lower limit A ON ON ov 4 Resettime D m n Im Internal RC oscillation 7 le imsCF tmsX tal _ XTN ATE a ul i lii Execute oscillation enable command Operating mode Unfixed Pe Reset be Instruction execution mode Reset Time and Oscillation Stabilization Time HOLD release signal OORD p lt HOLD release signal VALID release Internal RC oscillation A tmsCF gt CF1 CF2 Note AN ig tm Xl y XT1 XT2 Note ee Operation mode HOLD X HALT HOLD Release Signal a
34. vals No A1841 2 30 LC87F7932B High speed Clock Counter 1 Capable of counting a clock with a maximum clock rate of 8MHz at a main clock of 4MHz 2 Real time output Serial Interface e SIOO 8 bit synchronous serial interface 1 Synchronous 8 bit serial I O 2 or 3 wire configuration 4 3 to 512 3 tCYC transfer clock rate 2 Continuous data transfer variable length data transfer in bit units from 1 to 256 bits 4 3 to 512 3 tCYC transfer clock rate 3 Bi phase modulation Manchester Bi phase Space data transfer 4 LSB first MSB first selectable 5 SPI function HOLD X tal HOLD mode release function upon receipt of a 1 byte 8 bit clock e SIO1 8 bit asynchronous synchronous serial interface Mode 0 Synchronous 8 bit serial I O 2 or 3 wire configuration 2 to 512 tCYC transfer clock rate Mode 1 Asynchronous serial I O half duplex 8 data bits 1 stop bit 8 to 2048 tC YC baudrate Mode 2 Bus mode 1 start bit 8 data bits 2 to 512 tC YC transfer clock rate Mode 3 Bus mode 2 start detection 8 data bits stop detection BUART e Full duplex e Data length 7 8 9 bits selectable e stop bit 2 bits in continuous data transmission e Built in baudrate generator e Operating mode Programmable transfer mode fixed rate transfer mode e Transfer data conversion Normal NRZ Manchester encoding MAD Converter 12 bits 8 bits x 7 channels e 12 8 bit AD converter resolution selectable E Remote Control Receive
35. ws into the output transistors and internal pull up resistors HA 2 4 to 3 6 8 70 2 4 to 3 6 4 50 Continued on next page No A1841 23 30 LC87F7932B Continued from preceding page Parameter Symbol Pin Remarks Conditions VoplV min Specification typ max unit Current consumption in HOLD mode IDDHOLD 1 Vpp1 Vpp2 V2 HOLD mode CF1 Vpp or open When using external clock 2 4 to 3 6 0 05 30 Current consumption in time of day clock HOLD mode IDDHOLD 2 IDDHOLD 3 IDDHOLD 4 Vpp1 Vpp2 V2 Time of day clock HOLD mode CF1 Vpp or open When using external clock FsX tal 32 768kHz crystal oscillation 1 1 frequency division ratio LCD display off Normal XT amp mode 2 4 to 3 6 6 5 67 Time of day clock HOLD mode CF1 Vpp or open When using external clock FsX tal 32 768kHz crystal oscillation e 1 1 frequency division ratio LCD display off e Low consumption XT amp mode 2 4 to 3 6 0 45 HA 46 Time of day clock HOLD mode e CF1 Vpp or open When using external clock e FsX tal low speed RC oscillation e 1 1 frequency division ratio LCD display off 2 4 to 3 6 70 No A1841 24 30 LC87F7932B F ROM Programming Characteristics at Ta 10 C to 55 C Vssl Vss2 0V
36. x14 Lead and halogen free product TQFP64J 7x7 Lead and halogen free product SQFP64 10x10 Lead and halogen free product No A1841 8 30 LC87F7932B PIN No NAME PIN NO NAME 1 P7O INTO TOLCP AN5 33 S08 LPBO 2 P71 INT1 TOHCP AN6 34 S09 LPB1 3 P72 INT2 TOIN NKIN 35 S10 LPB2 4 P73 INT3 TOIN 36 S11 LPB3 5 Vpp2 37 S12 LPB4 6 Vss2 38 S13 LPB5 7 P10 S00 S24 39 S14 LPB6 8 P11 SI0 SB0 S25 40 S15 LPB7 9 P12 SCK0 S26 41 S16 LPCO 10 P13 SO1 S27 42 S17 LPC1 11 P14 SI1 SB1 S28 43 S18 LPC2 12 P15 SCK1 S29 44 S19 LPC3 13 P16 T1PWML S30 45 S20 LPC4 14 P17 T1PWMH BUZ S31 46 S21 LPC5 15 CUP1 47 S22 LPC6 16 CUP2 48 S23 LPC7 17 VDC 49 RES 18 Vi 50 XT1 19 v2 51 XT2 20 V3 52 Vss1 21 COMO LPLO 53 CF1 22 COM1 LPL1 54 CF2 23 COM2 LPL2 55 Vpp 24 COM3 LPL3 56 POO UTX1 ANO 25 SOO LPAO 57 PO1 RTX1 AN1 26 SO1 LPA1 58 P02 AN2 27 SO2 LPA2 59 P03 AN3 28 S03 LPA3 60 P04 CKO AN4 29 SO4 LPA4 61 PO5 DBGPO 30 SO5 LPA5 62 P06 T60 DBGP1 31 S06 LPA6 63 P07 T70 DBGP2 32 SO7 LPA7 64 P30 No A1841 9 30 System Block Diagram LC87F7932B Interrupt Control l Standby Control Generator Reset Circuit POR gt D IR PLA Flash ROM Reset Control SIO0 SIO1 Timer 0 Timer 1
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