Home

System Design Guidelines for the TM4C129x

1. BO a F F re ue a be T 6 E Acceptable F Acceptable G Acceptable H Not recommended Via locations are as close to pins as possible Traces to capacitor are short Low inductance ground plane used to connect pin and capacitor GND Via locations are as close to pins as possible Traces to capacitor are short Although GND trace from the pin to capacitor is not optimal the inductance from pins to power planes is low Via is located too far from the GND pin adding inductance to the path Figure 18 QFP PCB Routing Options SPMA056 October 2013 Submit Documentation Feedback System Design Guidelines for the TM4C129x Tiva C Series Microcontrollers Copyright 2013 Texas Instruments Incorporated l TEXAS INSTRUMENTS www ti com General Design Information 3 4 4 Table 7 shows recommended example placement and routing of the Vpp and Vppa decoupling capacitors Table 7 Vb Routing and Capacitor Placement Examples for TM4C129x Devices 212 BGA Package 128 TQFP Package i 4 ea The highlighted traces show the VDD net and decoupling The highlighted traces show the VDD net and decoupling cap cap locations locations Blue Traces and pads are on the top side Red Traces Blue Traces and pads are on the top side Red Traces and and pads are on the bottom side
2. Figure 3 128 Pin TQFP Footprint Table 2 128 Pin TQFP Footprint Dimensions Designator Description Size A Pad Pitch 0 4 mm 15 75 mil B Pad Width 0 25 mm 9 84 mil Cc Pad Length 1 4mm 55 12 mil D Horizontal Row Pitch Pad Center to Pad Center 15 4 mm 606 30 mil E Vertical Row Pitch Pad Center to Pad Center 15 4 mm 606 30 mil F Solder Mask Oversize is dependent on fab capabilities and 0 mm 0 mil to 0 05 mm 2 0 tolerances mil G Solder Paste Oversize 0 mm 0 mil SPMA056 October 2013 System Design Guidelines for the TM4C129x Tiva C Series Microcontrollers 5 Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated I TEXAS INSTRUMENTS General Design Information www ti com 3 2 3 2 1 3 2 2 PCB Stack up and Trace Impedance An important component of any layout is determining what PCB stack up to use The PCB stack up configuration determines several elements of the design Number of layers available for routing e Number of layers available for power and ground planes e Single ended trace impedance capacitance per inch and propagation delay per inch of a trace of a particular width These factors are important for longer trace lengths typically longer than 6 inches on critically timed interfaces or on interfaces that are near the maximum capacitive load e Trace width and spacing required to achieve the differential impedance targets fo
3. ccceeceeee eee ee eee eee eee eee eeeeee seas teen eeeneeeaeee 27 25 Recommended Layout for Crystal with GNDX Connection cceeee cece ence eee eee eee sees eeeeeeeeeeeeeneeeeees 27 26 Cortex ETM CONNECTOR EE E EE E EAE EE 29 27 General Protection Using Bi direction TVS Diode sssssssssssnnnnrnnnnnnnnrrrrnnnnnnnrnnrnrnnnnnnnnnnnnnnnnnnn 31 28 General ESD Protection Using Uni direction TVS Diode cceceeeeeee eee ee eee eens eee eeeeeeeeeeeeeeeeeeeenee 31 29 10 100 Mb s Twisted Pair Interface 00 cecceeee cece eee ene ee eeeeeeeeneeeeeeeeneee sense eneeeneeeneeeeneseneeeteeee 33 30 GPIO Sourcing LED Curr ntisciscsccctenisccwesenexscewaanancnexeadacswemeaexeaewcawagensxediacemepeeensaenceeanenanenn 35 31 GPIO Sinking LED Cun Mbicewctsathockiisiephidiiicntonnsetendceeumnedbnivnaiwdhhapbindiecaubniedeechniehinniecdeed 35 32 Ethernet PHY POB Layout scsictstecaicccciredcns dam lectins N E O E E tide teat 36 33 USB Routing Example scsi ccicrecsesccrssaiad careractare cape enetearmeroatecin salen E O ETENE 38 34 Tiva Microcontroller ADC Input Equivalency Diagram eceeceeeeeee eee eee eee eee eeeeeeeeeeeeeeeeeeeeeeeee 41 System Design Guidelines for the TM4C129x Tiva C Series SPMA056 0October 2013 Microcontrollers Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated l TEXAS INSTRUMENTS www ti com Introduction 1 Introduction The General Design Information section of this
4. Power Mgmt Microcontrollers RFID OMAP Applications Processors Wireless Connectivity dataconverter ti com www dip com www ti com clocks interface ti com logic ti com microcontroller ti com www ti rfid com www ti com omap Computers and Peripherals Consumer Electronics Energy and Lighting Industrial Medical Security Space Avionics and Defense Video and Imaging TI E2E Community www ti com wirelessconnectivity www ti com computers www ti com consumer apps www ti com energy www ti com industrial www ti com medical www ti com security www ti com space avionics defense www ti com video Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2013 Texas Instruments Incorporated
5. 3 There are some additional routing considerations for the internal layers 3 and 4 when using a six layer stack up e These internal layers 3 and 4 are considered asymmetric stripline relative to the Ground and Power plane layers 2 and 5 Refer to Figure 7 The calculations for impedance of traces on these layers are different than layers 1 and 6 e Generally traces on layers 3 and 4 are higher in capacitance per inch and have a higher propagation delay e Traces on layers 3 and 4 can impact each other via crosstalk if they are run parallel and over each SPMA056 October 2013 System Design Guidelines for the TM4C129x Tiva C Series 7 Submit Documentation Feedback Microcontrollers Copyright 2013 Texas Instruments Incorporated I TEXAS INSTRUMENTS General Design Information www ti com 3 2 3 other e Traces on layers 3 and 4 are better shielded from external EMC radiation or interference because they are shielded by the power and ground planes Trace Properties Impedance Inductance Capacitance Propagation Delay Impedance Zo Capacitance per inch Co Inductance per inch Lo and Propagation Delay Tpp are all important considerations when routing high speed signals and low impedance power nets Differential trace impedance is important for Ethernet and USB differential signals All of these properties are dependent on the trace width used W distance away from the reference plane H thickness of the trace
6. INSTRUMENTS Feature Specific Design Information www ti com 4 14 GPIO Most pins on a TM4C129x device can be used as a GPIO pin GPIO pins are designated by the letter P followed by their port letter A Q followed by their pin number 0 7 GPIO pins can be used for inputs sampled by software inputs that generate interrupts outputs that drive logic inputs high or low or outputs that drive LEDs A PinMux Utility for Tiva C Series MCUs is available which allows a user to graphically configure the device GPIOs and peripherals Refer to the Electrical Characteristics chapter of the TM4C129x device data sheet where important operational conditions are detailed The following considerations should be taken into account when selecting and designing with pins configured as GPIO inputs Pins are 3 3V tolerant NOT 5V tolerant e Maximum injection current limits are defined for pins that have their VIN greater than Vpp i e GPIOs that have power applied prior to theTM4C129x having power e GPIO port pins PPO PP7 and PQO PQ7 can be configured to use a unique interrupt vector table entry per port pin Other GPIO ports only have the option of an interrupt vector table entry per port letter requiring the input port value to be read to determine which specific pin on the port generated the interrupt e GPIO pins can be configured with an internal pull up or pull down Refer to the Electrical Characteristics chapter of the TM4C129x device data
7. corresponding to those found in the Tiva C device s data sheet VDD GND GND KEY GNDDetect GND GND GND GND GND TMS SWDIO TCK SWDCLK TDO SWO TDI RST TRCLK TRDO TRD1 TRD2 TRD3 Figure 26 Cortex ETM Connector On TM4C129x family devices TRCLK runs at 1 2 of the system clock speed which can be a high frequency TRDO 3 and TRCLK should be short traces less than 6 in 152 mm in length The TRCLK and TRDO 3 I O pads should be configured for 8mA drive strength initially and reduced on an individual basis if needed On some Tiva C microcontroller development kits the 2x10 0 05 in pitch connector is used however PA1 UOTX is connected to pin 14 TRDO and PAO UORX is connected to pin 16 TRD1 in order to provide a debug UART interface to TI s on board ICDI SPMA056 October 2013 System Design Guidelines for the TM4C129x Tiva C Series 29 Submit Documentation Feedback Microcontrollers Copyright 2013 Texas Instruments Incorporated I TEXAS INSTRUMENTS General Design Information www ti com 3 9 3 9 1 3 9 2 30 System This section describes system level design considerations related to the TM4C129x family of microcontrollers 1 0 Drive Strengths The Tiva C series microcontrollers have GPIO pads with programmable drive strength For outputs driving high speed buses higher capacitance loads greater than 15pF or LEDs the 8mA drive strength should be selected Higher drive
8. or 0 0355 mm thick The height of traces above the ground plane is defined by the thickness of the PCB prepreg material in this case 0 008 in 0 2032 mm thick Therefore total thickness is Total thickness 0 062 in 4 x 0 0014 in 0 040 in 2 x 0 008 in 1 Two Layer Stack up A two layer stack up may be acceptable given the following considerations e No timing sensitive high speed interfaces are being used e USB and Ethernet are either not being used on the design or the distance to connectors is short e The design allows for adequate power and ground routing with good decoupling placement and ESD protection System Design Guidelines for the TM4C129x Tiva C Series SPMA056 October 2013 Microcontrollers Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com General Design Information A typical configuration for an FR 4 0 062 in 1 5748 mm circuit board with two layers of 1 oz copper no plating is shown in Figure 5 1 0z Copper Mixed Signal Plane Layer 0 06 10 Core 0 58 1 0z Copper JX Mixed Signal Plane Layer Figure 5 Typical Two Layer PCB Stack with Routing Assignments For this example the top and bottom layers are used for both signal routing and copper power floods The 1 0z copper mixed plane is 1 4 mils 0014 in or 0 0355 mm thick The height of traces above any ground pour is defined by the thickness of the PCB core
9. 2013 Texas Instruments Incorporated l TEXAS INSTRUMENTS www ti com Feature Specific Design Information 4 3 2 4 3 3 4 4 4 5 If PB1 must be used for a function other than USBOVBUS any other available GPIO could be used in its place Because no other GPIO pins are 5V tolerant a 5 6KQ 5 in series with a 10KQ 5 resistor should be wired as a voltage divider between VBUS on the connector and ground This circuit drops the 5V VBUS value to 3 2V at the GPIO pin USB Embedded Host For TM4C129x devices that are used in a host only configuration the USBOEPEN and USBOPFLT signals may be used in the design in addition to USBODM and USBODP These two signals typically connect to a power switch such as a TPS2051B which controls power to the host s USB connector Refer to the TM4C129x device s data sheet to determine which ports these functions are available on USB OTG TM4C129x devices that support USB OTG mode include the signals for USB Device mode signals for USB Host mode and an additional signal USBOID located on pin PBO This USB ID signal is the 5th pin found on a USB micro AB connector If a micro A cable end is plugged into this connector the ID pin on the cable is tied to ground causing the TM4C129x device to operate as a USB host If a micro B cable end is plugged into the USB connector the ID pin is left floating In this case the TM4C129x device s internal pull up on the USBOID signal causes the controller to
10. RMII Timer PWM e USB e External Peripheral Interface EPI e USB ULPI e LCD Controller e SSI Buses e Quadrature Encoder Interface QEl e UART e GPIO e 12C SMBUS e Hibernation Signals e ADC 4 1 Ethernet Internal PHY This section describes design considerations related to the TM4C129x internal Ethernet PHY and details related to the network or Medium Dependent Interface MDI connection The MDI connection is accomplished via the transmit ENOTXOP amp ENOTXON and receive ENORXIP amp ENORXIN differential pair pins These signals connect to a termination network then to 1 1 magnetics transformer then through TVS diodes for ESD protection and to an RJ 45 as shown in Figure 29 These names reflect the default functions in fact the receive and transmit pairs are identical and can perform either function because the Internal Ethernet PHY supports MDI MDX NOTE Pull up resistors and decoupling cap should be located near U1 C s Otui 2 3 asg 499 3 3v R37 23v c2 F R asi freo ouf gt t je 49 9 Figure 29 10 100 Mb s Twisted Pair Interface SPMA056 October 2013 System Design Guidelines for the TM4C129x Tiva C Series 33 Submit Documentation Feedback Microcontrollers Copyright 2013 Texas Instruments Incorporated I TEXAS INSTRUMENTS Feature Specific Design Information www ti com 4 1 1 34 Termination Resistors Four pull up resistors are required for terminating
11. S E ZbpiFF R Z and Layer mil mil mil mil Ohms Ohms Notes The Saturn PCB Toolkit was used to calculate the layer 1 trace width and spacing for a 1000 10 differential Mere cal 12 1 4 8 24 14 3 104 1 53 5 impedance trace with a 500 10 single ended y impedance target using the stack ups defined in Figure 4 and Figure 6 The Saturn PCB Toolkit was used to calculate the layer 1 trace width and spacing for a 1000 10 differential Two Layer 1 30 1 4 58 7 43 107 84 94 19 impedance trace using the stack up defined in Figure 5 A single ended impedance target of 50Q 10 is not realistic with this stack up The Saturn PCB Toolkit was used to calculate the layer 1 trace width and spacing for a 900 10 differential area 15 1 4 8 24 4 3 90 1 46 3 impedance trace with a 450 10 single ended y impedance target using the stack ups defined in Figure 4 and Figure 6 The Saturn PCB Toolkit was used to calculate the layer 1 trace width and spacing for a 90Q 10 differential Two Layer 48 1 4 58 7 43 90 2 78 82 impedance trace using the stack up defined in Figure 5 A single ended impedance target of 45Q 10 is not realistic with this stack up NOTE The PCB fab house knows their process and materials the best They should be contacted to confirm stack up heights dielectric constant E and recommended trace widths and spacing for t
12. and F is 0 12 mm 4 76 mil All other balls require vias to the backside or power planes The placement of the vias is important to enable all traces on the back side to escape See Figure 11 It may be necessary to use a very small grid spacing to align the vias with 4 mil spacing Each set of three balls that connect to GND on the three of the corners of the BGA can share a via to GND The balls near the center of the BGA are either power Vpp or ground GND These balls are connected together in a web like structure with 6 mil wide traces to provide a low impedance connection to power or ground This web structure is preferred over a copper pour which may cause assembly issues due to uneven ball melting The location of the vias in the center of the BGA allow for placement of two 0402 decoupling capacitors on the back side of the board directly under the BGA as shown in Figure 11 Impedance controlled differential signals are routed with 0 1 mm 4 mil trace spacing until they escape the perimeter of the BGA and can be routed with the desired trace width and spacing to meet the impedance target All Vbo Vooa GND GNDA VREFA and VREFA signals are routed as 0 1524 mm 6 mil traces within the BGA escape area All Vbpc Signals are routed as 0 2032 mm 8 mil traces within the BGA escape area All other signals are routes as 1 mm 4 mil traces within the BGA escape area Figure 11 Bottom Layer 212 Ball BGA Escape Routing Figure 1
13. and biasing the Ethernet transceivers Refer to R40 R41 R42 and R37 in Figure 29 These resistors should be connected from the ENOTXOP ENOTXON ENORXIP and ENORXIN signals to 3 3 V The specified value for these resistors is 50 Q The recommended commonly available value is 49 9 Q 1 Do not use resistors with a tolerance greater than 1 Resistor power dissipation is low because the peak voltage on the resistor is only approximately 1 V in 100 Mbps mode and 2 5V in 10 Mbps mode Small 0402 1005 metric surface mount resistors have an acceptable power rating Isolation Transformer The transformer used in the MDI connection provides DC isolation between local circuitry and the network cable The Tiva C Series data sheets list both the part number and manufacturer s name for approved Ethernet transformer magnetics options Other parts can be approved by similarity but it is highly recommended to check with the manufacturer for their assessment of suitability Magnetics with integrated common mode choking devices are recommended to help with EMI performance The center tap of the transformer microcontroller side of the transformer should be connected to 3 3V Each connection point to the 3 3V rail must be adequately filtered with a capacitor 0 1 F or greater if a solid power plane is present C40 C60 in Figure 29 If the center tap connects to a PCB trace instead of a plane the capacitor value should be 1 UF or greater The cente
14. details Decoupling capacitors should be 6 3 V to 25 V X5R X7R ceramic chip types Z5U dielectric capacitors are not recommended due to wide tolerance over temperature The capacitance of most ceramic capacitors decreases with increasing voltage Avoid using capacitors at close to their rated voltage unless reduced capacitance is acceptable X7R capacitors may lose 15 20 of their capacitance at rated voltage while Y5V capacitors may drop 75 80 Cain Jeffrey Comparison of Multilayer Ceramic and Tantalum Capacitors AVX Technical Bulletin Figure 18 shows different options for routing PCB traces between the Tiva C Series microcontroller power pins and a decoupling capacitor Cap O o VDD A Best practice Minimal inductance from between capacitor pins and power planes B Acceptable Short low inductance traces from power pins to vias and from capacitor pins to vias Power planes are lower inductance than routed traces C Acceptable Inductance to VDD and GND planes is low D Not Recommended Distance from pins to vias increasees inductance in power rails
15. material in this case 0 058 in 1 4732 mm thick Therefore total thickness is Total thickness 0 061 in 2 x 0 0014 in 0 058 in 2 3 2 2 1 Six Layer Stack up Stack ups greater than four layers can be used if desired for high density designs A typical configuration for an FR 4 0 062 in 1 5748 mm circuit board with six layers of 1 0z copper no plating is shown in Figure 6 1 0z Copper Signal Layer 2 Sheets 2116 0 008 1 0z Copper Ground Plane Core 0 014 1 0z Copper Signal Layer lt q 2 Sheets 2113 0 007 1 0z Copper Signal Layer Core 0 014 1 0z Copper Power Plane 2 Sheets 2116 0 008 1 0z Copper Signal Layer A o 0 06 10 Y Figure 6 Typical Six Layer PCB Stack with Routing Assignments For this example we place a solid ground plane on layer 2 and a power plane on layer 5 The 1 oz copper planes are 1 4 mils 0014 in or 0 0355 mm thick The height of traces on the outer layers 1 2 above the planes is defined by the thickness of the PCB prepreg material in this case 0 008 in 0 2032 mm thick The height of the traces on the inner layers 3 4 above the planes is defined by the thickness of the PCB core material in this case 0 040 in 1 016 mm thick In between layers 3 and 4 is additional prepreg material in this case 0 007 in 0 1778 mm thick Therefore total thickness is Total thickness 0 0594 in 6 x 0 0014 in 2x 0 008 2x 0 014 in 0 007 in
16. microcontroller data sheet for specific information Increased source impedance can provide a degree of protection to the ADC Semiconductor clamping circuits can also be used typically zener diodes or clamping diodes to 3 3 V and GND When specifying diodes consider leakage current over temperature lp because this parameter affects overall conversion accuracy Comparators There are three independent integrated analog comparators available on TM4C129x devices Refer to the Analog Comparators chapter of the part data sheet for specific details When selecting comparator pins the following should be considered e C0 PC6 can be used as a common reference input to all three comparators e CO0 PC7 C1 PC4 and C2 PP1 are the unique negative inputs for each comparator e Pins used for comparator inputs must not exceed the maximum injection current if voltage is applied to them prior to the device s Vpp supply being powered up Timer PWM There are several general purpose timer pins available on a TM4C129x family devices Refer to chapter General Purpose Timers in the data sheet for specific details Each timer module has a CPPO and a CPP1 pin associated with it Each timer module can be configured as two independent 16 bit timers or a combined 32 bit timer When selecting timer pins the following should be considered e Timer modules configured for 32 bit mode use the CCPO pin input The CCP1 pin input is not used e 32 bit mo
17. of two or more 10 tolerance ceramic chip capacitors totaling 3 3yuF to 3 4uF examples are one each of 3 3uF and 0 1uF capacitors or one each 2 2uF 1 0uF and 0 1yF Z5U dielectric capacitors are not recommended due to wide tolerance over temperature The following recommendations should be followed when placing and routing the capacitors connected to Vope e The larger values of capacitance should be placed closest to the pin specified in the data sheet and the 0 1uF capacitor can be placed near the other Vp pins e The ESR Max Specification in the data sheet for Cipo must be adhered to and should include any via and trace resistance from the pin or ball to the capacitors All Vppc pins should be routed together using wide traces for lower resistance See Table 6 for examples of recommended Vppc routing and Cipo capacitor placement Table 6 Vboc Routing and Capacitor Placement for TM4C129x Devices 212 Ball BGA Package 128 Pin TQFP Package e Highlighted Trace is VDDC routed with 0 254 mm 10 mil trace 2 2uF 1 0uF and 0 1uF capacitors placed closest to pin 115 0 1uF capacitor placed near pin 87 e Highlighted Trace is VDDC routed with 0 2032 mm 8 mil trace 2 2uF 1 0uF and 0 1uF capacitors placed closest to ball E10 0 1uF capacitor placed near ball H16 NOTE Vonc is an internally generated voltage rail Vooo should only be connected to the Cpo filter capacitors Vboc should not be c
18. or Vona to ensure the correct power up sequence Table 8 Example Vpera Vacra Routing and Capacitor Placement Examples for TM4C129x Devices 212 BGA Package 128 TQFP Package o ci ST REE ROAR SS Sees were mere tees EO ts 00 menr irag ets reed it Bil b N N 9 4 prin Pv ON Mt MAY AG Bt Fi o o e The highlighted trace is the VREFA net The highlighted trace is the VREFA net e The 1uF capacitor is located on the top side The 0 01uF C26 and C27 are the 1uF and 0 01uF capacitors placed capacitor is located on the bottom side close to the device In this example VREFA is a dedicated pin connected directly e This device has VREFA internally connected the GNDA to GND pin which is connected to digital GND on this design System Design Guidelines for the TM4C129x Tiva C Series SPMA056 October 2013 Microcontrollers Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com General Design Information 3 4 6 Vear The TM4C129x family of devices supports a Var supply for battery backed RAM retention and RTC operations when the main VDD supply is not powered Vsar has a maximum ramp time as specified in the data sheet as Veatampe If Vear is to be driven from a coin cell battery or switched an RC filter as shown in Figure 19 can be used adhere to the Vearamp rise time requirem
19. pads are on the bottom side e Most of the decoupling caps shown in this example are Two decoupling caps are located on the back side directly on the back side under the BGA There is at least one decoupling capacitor on each side of the chip Splitting Power Rails and Grounds Tiva C Series microcontrollers are designed to operate with Vpp and Vppa pins connected directly to the same 3 3V power source Some applications may justify separation of Vppa from Vpp to allow insertion of a filter to improve analog performance Before deciding to split these power rails the power architecture of the device should be reviewed to determine which on chip modules are powered by each supply The device data sheet contains a drawing that shows power architecture Filter options include filter capacitors in conjunction with either a low value resistor or inductor ferrite bead to form a low pass filter If the Vbo and Vppa pins are split the designer must ensure that Vpp power is applied before or simultaneously with Vpp and that Vppa is removed after or simultaneously with Vpp If Vbpa iS to be selected as a reference source for the ADC the ADC will achieve better performance when powered with a separate Vpp power rail and filtered with a 0 01uF and 1uF capacitor Cker between Vopa and GNDA The GND and GNDA pins should always be connected together preferably to a solid ground plane or copper pour SPMA056 October 2013 System Design Gu
20. property of TI Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices TI is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements Buyer acknowledges and agrees that it is solely responsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures monitor failures and their consequences lessen the likelihood of failures that might cause harm and take appropriate remedial actions Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety critical applications In some cases TI co
21. series with the 75Q termination resistors RBIAS Resistor An additional resistor is required on the RBIAS pin R38 in Figure 29 to set the bias voltage for the Ethernet module The bias resistor is a 4 87 KQ 1 resistor and must be located close to the microcontroller pin ideally less than 0 25 in or 6 mm The other resistor terminal should have a very short trace directly to GND The trace via for the GND connection should not be shared with any other pin An incorrect value of RBIAS resistor results in incorrect amplitude on the transmit differential pair Crystal Requirements In order to use the Internal Ethernet PHY the main oscillator circuit of the microcontroller must be driven with a 25MHz 50ppm clock source Refer to Section 3 6 for additional details about the Main Oscillator Circuit System Design Guidelines for the TM4C129x Tiva C Series SPMA056 October 2013 Microcontrollers Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated l TEXAS INSTRUMENTS www ti com Feature Specific Design Information 4 1 6 4 1 8 Ethernet ESD ESD protection for the MDI differential pairs is strongly recommended One recommended solution is the SLVU2 8 4 TVS Diode Array shown in Figure 29 as D14 This device is placed on the differential lines between the transformer and the RJ45 connector The JEDEC SO 8 package is well suited for routing the transmit and receive differential pairs A second
22. sheet for specifics of the internal pull up and pull down values It may be desirable to use external pull ups or pull downs in situations where a more consistent rise fall time is required e GPIO port pins PK4 PK7 can be configured to cause a wake from hibernate mode e GPIO port pins PM4 PM7 can be configured as tamper input detects The following considerations should be taken into account when selecting and designing with pins configured as GPIO outputs e Pins PM4 PM7 and PJ1 have 2mA max output capability when configured as outputs e Pins PL6 and PL7 have a fixed 4mA output drive strength and cannot operate in open drain mode On devices that support USB these pins function as USBODP and USBODM e At system power on reset pins power up as GPIO inputs with no pull up or pull down configured Pins used as outputs that are required to be at a high or low value at system power up should be externally pulled up or down The exception to this statement is JTAG pins which power on with internal pull ups enabled and configures for JTAG e A total of four GPIO pins may be used simultaneously to each sink 18mA but the Vo is specified as 1 2V when operating in this manner There should be a maximum of two high current pins per physical die side defined in the Recommended Operating Conditions chapter of the TM4C129x device data sheet 44 System Design Guidelines for the TM4C129x Tiva C Series SPMA056 October 2013 Microcontrollers Submit
23. strengths can be selected based on the Vo Vo and total GPIO current per side limits given in the parts data sheet Some Tiva C series microcontrollers have GPIO pads that are limited to 2mA drive strength If these pads are to be used as outputs they should be limited to low capacitance loads less than 15pF or signals that can support the longer rise fall time associated with a 2mA drive strength Refer to the device s data sheet for a list of GPIO pins supporting only 2mA drive The GPIOs that are shared with the USB functions USBODP and USBODM on TM4C129x microcontrollers are fixed at 4mA drive strength and cannot be configured as open drain These limitations must be considered if these pins are used as outputs Series Termination Resistors Series termination resistors provide two different functions The first type of use is for outputs with fast rise fall times driving light loads to help match the output impedance of the driver to the impedance of the net being driven This configuration helps with several items e Lower over or under shoot at the input destination e Reduce ringing near the transition region of the input that could cause false clocking or timing violations e Limit crosstalk induced on neighboring signals e Reduce EMC emissions Output series termination is best placed within 0 5 in 12 7 mm of the output pin The values used are system dependent but often are one of 0O 100 220 or 330 The second type o
24. that can be used when VDD30N hibernation mode is used e Four GPIOs can be configured as external wake sources e Four GPIOs can be configured as tamper detect inputs e The hibernation clock source can be output on a GPIO configured for the RTCCLK function Refer to the devices data sheet for specific details of these functions SPMA056 October 2013 System Design Guidelines for the TM4C129x Tiva C Series 45 Submit Documentation Feedback Microcontrollers Copyright 2013 Texas Instruments Incorporated I TEXAS INSTRUMENTS System Design Examples www ti com 5 46 System Design Examples For example designs using the TM4C129x family of microcontrollers see Table 11 for the detailed list of TM4C129x Reference Design Kits RDKs Evaluation Kits EKs and Development Kits DKs Table 11 TM4C129x Example Designs PCB Key Features Layer Count Tiva C Series Device Part Number Description Device Package USB Ethernet LCD SPI DK TM4C129x Development Kit TM4C129XNCZAD 212 pin BGA Launchpad Headers Conclusion Applying good system design practices from the earliest design stages ensures a successful board bring up The design process should include thorough design reviews using the information in this application report other embedded system design resources and reports created by the design team These efforts will be rewarded with a reliable and properly performing Tiva C Series
25. the microcontroller data sheets System Design Guidelines for the TM4C129x Tiva C Series SPMA056 October 2013 Microcontrollers Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com General Design Information 3 6 Crystal Oscillators This section describes design considerations related to the microcontroller oscillators 3 6 1 Crystal Oscillator Circuit Components 3 6 1 1 Main Oscillator Circuit Tiva TM4C129x family of microcontrollers has a main oscillator circuit that can be used as a clock source for the device This clock source is required for parts that contain and use the USB Ethernet or CAN interfaces Tiva TM4C129x family parts that support the integrated Ethernet PHY require a 25MHz crystal on the main oscillator circuit If the integrated Ethernet PHY is not used any of the supported crystals as specified in the data sheet can be used Some of the Tiva C family parts bring the GNDX2 signal of the main oscillator circuit out to a ball or pin on the part When the GNDX2 signal is available it should be connected to the digital ground plane as shown in Figure 20 for proper operation Early designs may show the crystal load capacitors and GNDX2 pin connected only to each other without a connection to digital ground Either is a valid configuration however the low impedance connection to the digital ground helps isolate the circuit from external system no
26. ti com Ethernet circuits Do not extend the ground plane under the transformer unless the transformer is shielded on all sides Do not extend the ground plane under the signals from the transformer to the connector Refer to the lack of a ground plane under T1 D14 and J8 in Figure 32 Do not extend the power plane that is the Vpp plane under the Ethernet signals unless there is a solid ground plane between the differential Ethernet signals and the power plane Make sure there are no ground plane discontinuities under or near the differential signals between the microcontroller and the transformer Create a chassis ground to which the metal shield of the RJ 45 is connected and the Bob Smith termination is connected as described in Section 3 3 6 l a he ee tos ix 2 i Figure 32 Ethernet PHY PCB Layout 4 2 External Ethernet PHY Interface An external Ethernet PHY Interface is available on some devices within the TM4C129x family of microcontrollers This interface connects the Ethernet Media Access Controller MAC within the microcontroller to an external Ethernet PHY Data transfer occurs over the Media Independent Interface MII or the Reduced MII RMII The external Ethernet PHY register space is accessed using the Management Data Input Output MDIO interface The MDIO interface is made up of the ENOMDC and the ENOMDIO pins Each PHY connected to the MDIO interface must have a unique address The in
27. 1 shows the bottom layer escape routing under the BGA from the vias In the center of the bottom layer are two 0402 sized 0 1uF decoupling capacitors connected between VDD and GND SPMA056 October 2013 System Design Guidelines for the TM4C129x Tiva C Series 13 Submit Documentation Feedback Microcontrollers Copyright 2013 Texas Instruments Incorporated I TEXAS INSTRUMENTS General Design Information www ti com 3 3 4 3 3 5 14 PCB Design Rules 90 PCB Traces For many years it has been common PCB design practice to avoid 90 corners in PCB traces In fact most PCB layout tools have a built in miter capability to automatically replace 90 angles with two 45 angles The reality is that the signal integrity benefits of avoiding 90 angles are insignificant at the frequencies and edge rates seen in microcontroller circuits even up to and past 1 GHz 100 ps Johnson H and Graham M High Speed Digital Design a Handbook of Black Magic Prentice Hall New Jersey 1993 Additionally one report could find no measurable difference in radiated electromagnetic interference EMI Montrose Mark Right Angle Corners on Printed Circuit Board Traces Time and Frequency Domain Analysis undated 90 Acceptable PCB Also acceptable trace routing PCB trace routing Figure 12 Acceptable PCB Trace Routing NOTE Loops in PCB traces are not acceptable despite the references that indicate that the signal int
28. 2 2KQ resistors but the value used depends on bus speed and total bus capacitance Refer to the Pull up resistor sizing section of the UM10204 l2C bus specification and user manual v 5 from NXP for details on how to calculate the minimum and maximum pull up resistor values Only 3 3V I2C buses are directly supported 5V or 1 8V buses can be supported with the use of external level shifting diodes An 2C bus pulled up and connected to a 3 3V power rail different from the one attached to the Vpn of the TM4C129x device can be pulled low by the devices ESD structures when VDD to the device is not powered Routing Considerations An 2C bus should be routed such that the I2CxSCL and I2CxSDA signals follow similar layer transitions and stay within approximately 1000 mils of each other It is not recommended that these signals be routed as a differential pair and there is no length matching requirement for them I2C signals should not be routed next to signals that can cause significant cross talk to the l2CxSCL signal Cross talk noise could interfere with the 12C transaction and cause a bus error requiring an I2C bus is reset System Design Guidelines for the TM4C129x Tiva C Series SPMA056 October 2013 Microcontrollers Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated l TEXAS INSTRUMENTS www ti com Feature Specific Design Information 4 8 4 8 1 ADC This section describes design considera
29. 2 Class 2 requirement allow for one void per hole in not more than 5 of the holes Boards fabricated and inspected with the IPC 6012 Class 3 requirements allow for no voids per hole A PCB fab house usually requires a larger adder for Class 3 boards A PCB fab house maintains a minimum annular ring typically 1 mil around each via hole but the customer could choose to allow tangency where the hole is up to the edge of the pad but breakout has not occurred This method can allow for a smaller diameter via pad if needed Table 5 lists some common via sizes along with some of characteristics calculated using the Saturn PCB Toolkit Table 5 Via Sizes and Properties Via poy Drill Via Ref Plane Via Via viapes Via Type Size Size Height Opening E Cap Ind mOhms Impd Notes yp min mil mil Diam mil pF nH Ohms Small lower capacitance but higher resistance via Some PCB fab 16D6 16 6 62 24 4 3 0 75 1 49 2 08 44 48 houses may not be able to accommodate this size Useful for tight spaces and dense routes The largest via pad size 18mils that can be used to break out route 18D8 18 8 62 26 4 3 0 85 1 40 1 62 40 63 of the BGA package with 4 mil spacing Pad size is 10 mils over drill size of 8 The largest via pad size 18mils that can be used to break out route 18D9 18 9 62 26 4 3 0 85 1 36 1 46 40 01 of the BGA package with 4 mil spacing Pad siz
30. 29 3 9 SYSTEMI cGiiictneniilsniiineidawtitelenntesdehabenigaatinnin EEE E EE a E E AEE EE EE 30 BAO SAll ExltermalSignal S senene E a E E E neta E E ES 32 4 Feature Specific Design Information sssssssssssnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nnmnnn 33 4 1 Ethernet Internal PHY sidecases se eanteuaeicedae adv badateautaddactbatcntelnidtedsbawaiehadihedevevadvletwadegds 33 4 2 External Ethernet PHY Interface tac scsmcnexcneanais anomie wieintnanacnemeraemehaddicatamane deena texetensadsmeemeces 36 4 3 USB caprea a a nts bid E slain dais eine eigiei OE EEEa 37 4 4 USB ULPIExt rmal PHY Interfac siaisiccececmamsnaninccscniaaleews ioni a 39 4 5 SS BUSES siwasccimeeswetivtdiaiiccuiame ena seecemecamaciar wee gawey eee iencemamonmumemaneneweredeenan ocamaweveucenaan 39 4 6 VARI iese cars casas cane E O alc iateel clevlstare ove E E EAE E E E 40 4 7 M2 encanta E R N E nl twin las a lS alaibhntallainc 40 4 8 ADO eisissiatanivecctwarewasvads de vabaneccaleadswaledvace adsl thcbaedadey addvesieenatadevacd EEEE 41 4 9 Comparators arer irane E T E E E 42 A0 MMe FVM sasidan O a E E a a A E 42 4 11 External Peripheral Interface EPI c ccceecee cece ee eee eens tees ee eeeeeeeeeeeeeneeeneeeeeeeeeneeeeeeteeeees 42 AA LGD COmtrollen visdsieinicscaitssseiatsicatecrera aie ninioisranie apaaaramceinaareateerda saibiayeniainamolem nomamadnantena menu weumanenamamamecanaan 43 4 13 Quadrature Encoder Interface QEI cececeec
31. 5 mm 9 84 mil Solder Mask Opening 0 30 mm 11 81 mil Not Applicable N A Trace Width Trace Spacing 0 1016 mm 4 00 mil Trace to Landing Pad Spacing 0 1210 mm 4 76 mil nm ojojo System Design Guidelines for the TM4C129x Tiva C Series SPMA056 0October 2013 Microcontrollers Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com General Design Information 3 1 2 128 Pin TQFP Package PDT The 128 Pin TQFP package is 14 mm x 14 mm x 1 mm in size The package has 32 pins per side with a pin pitch of 0 4 mm Figure 3 shows the results of a PCB footprint calculator that follows the IPC 7351 specification based on the package tolerances Solder Mask oversize is dependent on the tolerances and capabilities of the PCB fabrication shop being used Three common options for a 0 4 mm pitch TQFP are 1 Make the solder mask the same size as the pad 0 oversize and allow the fab shop to make any required adjustments to the gerber files as required for their process 2 Make the solder mask 0 05 mm 2 0 mil larger than the pad 0 05 mm 2 0 mil oversize and confirm that the fab shop can handle the 0 1 mm 3 94 mil solder mask width between pads 3 Create a gang solder mask that voids the solder mask along all pins of each side such that there are no slivers of solder mask between each individual pin This approach may require special care during assembly
32. AG SWD Signal 0 1 in pitch 0 05 in pitch TCK SWCLK 9 TMS SWDIO 7 TDI 5 TDO SWO 13 RESET 15 10 GND 4 6 8 10 12 14 16 18 20 3 5 9 TVCC 1 1 O OINI zs Tiva C Series microcontrollers have default internal pull up resistors on TCK TMS TDI and TDO signals External pull up resistors are not required if these connections are kept short If the JTAG signals are greater than 2 in 51 mm or routed near an area where they could pick up noise TCK should be externally pulled up with a 10K or stronger resistor or pulled down with a 1K or stronger resistor to prevent any transitions that could unexpectedly execute a JTAG instruction System Design Guidelines for the TM4C129x Tiva C Series SPMA056 October 2013 Microcontrollers Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com General Design Information 3 8 CoreSight ETM Trace Port Connections The TM4C129x family of microcontrollers includes ARM s Embedded Trace Macrocell ETM for instruction trace capture Trace data is output on pins TRDO 3 and clocked with TRCLK Refer to the Signal Tables in the device s data sheet to determine which GPIOs the trace signals are available on ARM defines a 2x10 0 05 in pitch connector with a key on pin 7 as a standard to interface to debuggers supporting JTAG with trace data capture Figure 26 shows this connector definition with signal names
33. Another key benefit of specifying controlled impedance is that the PCB manufacturer assumes on going responsibility for maintaining the impedance of those traces This stipulation can be a factor when lot to lot differences introduce variation While specifying controlled impedance is preferred it may be acceptable not to if the trace length is less than approximately 2 in 50 8 mm If good design rules are followed during layout it should be possible to achieve routing that provides good signal integrity SPMA056 October 2013 System Design Guidelines for the TM4C129x Tiva C Series 9 Submit Documentation Feedback Microcontrollers Copyright 2013 Texas Instruments Incorporated I TEXAS INSTRUMENTS General Design Information www ti com 3 3 10 A slight variation of this method which also avoids the additional cost of controlled impedance PCBs is sometimes called controlled dielectric This approach involves the PCB designer using a dielectric specification that is either supplied or agreed to by the board fab house The material and dielectric constant should be added to the PCB fab notes The differential impedance calculations use the Microstrip differential transmission line type as with a ground reference plane as shown in Figure 8 4 ke 4 A T Microstrip Stripline Figure 8 Differential Transmission Line Types Table 4 Differential properties by width and stack up Configuration W T H
34. Application Report l TEXAS SPMA056 October 2013 INSTRUMENTS System Design Guidelines for the TM4C129x Family of Tiva C Series Microcontrollers Ken Krakow Sheldon Johnson Jonathan Guy ABSTRACT The Tiva C series TM4C129x microcontrollers are highly integrated system on chip SOC devices with extensive interface and processing capabilities Consequently there are many factors to consider when creating a schematic and designing a circuit board By following the recommendations in this design guide you will increase your confidence that the board will work successfully the first time it is powered it up Contents 1 IMMFOGUGCTION risorsa a a a a dda hin endl ial eb Mii Mas dled tadev 3 2 USNA THIS GUE mesas sero EEE O E 3 3 General Design ItOnimMeathon sereante nne EE E E E E G 3 3 1 Package Footprint srrisidsnososisiiemaen e a 4 3 2 PCB Stack up and Trace ImpedaNte siusssrrssrsssieisisisieniednennnre nennir 6 3 3 General Layout DESigh CHOICES isis ccicicidice si ciciartiere a ane conceded sein ase aun EEE EER 10 3 4 POW cscicntsis wserctiaiasclig wie a e anim inact eatin pig in a wine etna a a r a 18 3 5 RESE uinen canoe dalndd EA E a aaa Eaa a EEE te 24 3 6 Cystal OsCillatonss isens E NEE ms eeleading 25 3 7 JTAG INtrfaA C aicisseccsisincicivaicitiediemadaiceiinss aaaaaidacaiananaisesiainacts EA a EE aS 28 3 8 CoreSight ETM Trace Port Connections cecceeeeee eee eee eee ee eee eee e eee eee eee e eee eeeeaeeaeeeeeeeeeaes
35. Copyright 2013 Texas Instruments Incorporated l TEXAS INSTRUMENTS www ti com General Design Information 3 6 2 Crystal Oscillator Circuit Layout The key layout objectives should be to minimize both the loop area of the oscillator signals and the overall trace length A poor oscillator layout can result in unreliable or inaccurate oscillator operation and can also be a noise source Ideal trace length is less than 0 25 in or 6 mm Do not exceed 0 75 in or 18 mm Figure 24 shows a preferred layout for a small surface mount crystal The GND side of each capacitor routes directly to a via that provides a low impedance connection to the GND plane Figure 24 Recommended Layout for Small Surface Mount Crystal Some crystal circuits require a series resistor Rg in order to limit drive power delivered to the crystal This component should be a small chip resistor located between capacitor C and the OSC1 pin of the device Figure 25 shows a recommended layout for a small surface mount crystal for a device that contains a GNDxX pin between the XOSC0O XOSC1 signals The GND side of each capacitor can share the via with the GNDX pin using a 10 mil wide trace to provide a low impedance connection to the GND plane If the distance between capacitors and the GNDX pin is greater than 200 mils each should have their own via to GND Crystal Figu
36. DAC LCDCP LCDFP LCDLP and LCDMCLK For a detailed explanation check the device s data sheet 4 12 2 Raster Mode TM4C129x devices with the LCD peripheral can function in Raster mode with up to a 24 bit bus Pins used for this mode are LCDDATA00 LCDDATA23 LCDAC LCDCP LCDFP LCDLP and LCDMCLK For adetailed explanation check the device s data sheet 4 13 Quadrature Encoder Interface QEI Some TM4C129x devices support connection to a quadrature encoder that tracks position direction of rotation and estimates velocity The frequency of the QEI inputs can be as high as 1 4 of the processor frequency Pins used for the QEI are IDXn PhAn and PhBn A series resistor followed by a capacitor to digital ground should be placed on each QEI input to filter the inputs from noise that would violate the input electrical specifications of the device A common value for the series resistor is 1000 and for the capacitor is 1nF The electrical specifications of the quadrature encoder being attached and the system environment determine the optimum resistor and capacitor values for the system Some quadrature encoders may output at 5V levels requiring a resistor divider or 5V tolerant input buffer be placed in series to bring the signal levels down to 3 3V SPMA056 October 2013 System Design Guidelines for the TM4C129x Tiva C Series 43 Submit Documentation Feedback Microcontrollers Copyright 2013 Texas Instruments Incorporated I TEXAS
37. DX Figure 23 Hibernate Oscillator Circuite without GNDX 32 768KHz Crystal C Capacitors C and C must be sized correctly for reliable and accurate oscillator operation Crystal manufacturers specify a load capacitance C which should be used in the following formula to calculate the optimal values of C and C C C C C C Cs 4 C is the stray capacitance in the oscillator circuit Stray capacitance is a function of trace lengths PCB construction and microcontroller pin design For a typical design C should be approximately 2pF to 4pF Because C and C are normally of equal value the calculation for a typical circuit simplifies slightly to C and C C 3pF 2 5 C and C should stay within the maximum and minimum specifications listed in the Hibernation Clock Source Specifications section of the data sheet for the part Capacitors with an NPO COG dielectric are recommended and are almost ubiquitous for small value ceramic capacitors It is possible to use a single ended clock source such as an external oscillator to drive the XOSCO input of the Hibernate Oscillator Circuit Refer to the device s data sheet for input specifications When a single ended clock source is used the XOSC1 pin should be left unconnected and GND if present should be connected to GND System Design Guidelines for the TM4C129x Tiva C Series SPMA056 October 2013 Microcontrollers Submit Documentation Feedback
38. Documentation Feedback Copyright 2013 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com Feature Specific Design Information 4 15 Hibernate Signals Some of the TM4C129x family devices contain a Hibernation module that can be used to put the device in its lowest power state Refer to the device data sheet for a detailed description of the Hibernation module The Vegar pin can be used to power the Hibernation module Refer to Section 3 4 6 for system considerations related to Var The Hibernation module can be clocked by a 32 768KHz external clock source or if the real time clock is not used by the internal Hibernation Low Frequency Oscillator HIBLFIOSC Refer to Section 3 6 1 2 for system level considerations of this clock source The WAKE pin on the TM4C129x device is used to wake the device from hibernation mode This pin can also be used to generate an interrupt when in run mode sleep mode or deep sleep mode This pin is can be connected to a switch to ground and pulled up externally with a 1MQ resistor connected to the same supply voltage that the Vaar pin is connected to If the WAKE pin is not used it should be connected to system ground The HIB pin on the TM4C129x device can be used to control the regulator supplying Vpp Refer to the TM4C129x data sheet for more details on the Hibernate functionality If the HIB pin is not used it can be left unconnected There are some additional hibernate features
39. ROUtING cceeeeee eee eee eee eee eens eee n eee n ene ee eee eee nae ease eeneeeneeeaeeee 12 10 BGA Escape Routing Through Depopulated Ball Location cceeceee eee e eee neces eee seen eeeeeeeaeeeeeeeenaes 12 11 Bottom Layer 212 Ball BGA Escape ROuting cceeceeeeeeeeeeeeeeeeeee eee eeeeeeenaeeeeeeeeeeenaeeeeeeeeeeenanes 13 12 Acceptable PCB Trae Routing a iiiiwicciendenenncwins cencmenitctacicpemewieapinwncnencninsintete a a E E 14 13 Ghassis Ground Guideline iscsi anita iea idee a aE E a E 15 14 Examiples of PCB Trace Layou ovseni niie EE baad SE E EEEE ENN a 16 15 DitferentialSignal PAi seroniiniree rninn E E EEE E CE E Tz 16 Examples of Differential Pair LayOUt ccccee cece cece eee ee eee ence eee ee nee ences tees eeneeeneeeneeeeneeeneeeeeeeeneee 17 17 Differential Signal Pair Plane CroSSing cseeeeeeeeeee eaii E EEE EE Eaa Es 18 18 QFP PCB Routing Options osoei i a a a detneicinaeneen 20 19 Var RG PIMC sees aa E EE E E E aa E a E EE ASES 29 20 Main Oscillator Circuit With GNDX2 gt icciscacdeisd ct bits edsane e Savane cceloae enciciaie 25 21 Main Oscillator Circuit without GNDX2 sivecsccicaicenatecnnged a E AE E 25 22 Hibernate Oscillator Circuit with GNDX cee cece cece ee eee eee eee e ence ee anaE aas EEEE Saa 26 23 Hibernate Oscillator Circuite without GNDX ceeeeeeee eee eee eee eee eee eee e een eens teen neste eee e eee eeeneeeeeeee 26 24 Recommended Layout for Small Surface Mount Crystal
40. T and relative permittivity of the dielectric Eg see Table 3 Differential impedance is also significantly affected by the distance between the differential traces S Some PCB design tools have an integrated trace impedance calculator that factors in trace geometry trace length board stack up and the board material dielectric constant Several free programs are also available that can perform similar calculations The Saturn PCB Toolkit from Saturn PCB Design Inc is an example of one of these free programs that has been used for most of the impedance calculations in this document 3 2 3 1 Single ended Trace Impedance The first step in calculating these single ended trace properties is to identify the transmission line type of the trace The Microstrip transmission line type as shown in Figure 7 is most common on two layer and four layer boards as well as layers 1 and 6 of six layer boards The Asymmetric Stripline transmission line type is most common on layers 3 and 4 of six layer boards Copper Ground Plane Copper Power Plane Microstrip Asymmetric Stripline Figure 7 Transmission Line Type The typical dielectric constant Ep for FR 4 material is about 4 3 The following examples use this parameter as well as the stack ups defined in Section 3 2 to generate some typical PCB geometries They are intended as starting points for PCB designs You should repeat the calculations for your own design because even small changes i
41. TS General Design Information www ti com 3 1 3 1 1 Package Footprint Packages for Tiva C devices are PBGA TQFP or LQFP Package details and dimensions can be found in the data sheet for the part PCB footprints for the part should be created using the IPC 7351 standard For BGA parts the nominal ball diameter is used as a reference for the landing pad size and solder mask opening for each ball pad For TQFP and LQFP parts the package and lead dimensions maximum and minimum specifications along with standard tolerances are used to calculate the pad size and locations Many PCB layout tools offer package wizards to perform these calculations 212 Ball BGA Package ZAD The 212 Ball BGA package is 10 mm x 10 mm x 1 mm in size The ball array consists of a 19x19 ball array with a ball pitch of 0 5 mm Selected balls are not populated in order to allow 0 8 mm routing rules to be used when routing See Figure 1 Ball H8 is not populated in order to provide an obvious orientation of the part for both layout and assembly The IPC 7351 standard should be followed for NSMD Non Solder Mask Defined pads for a 0 3 mm nominal ball diameter which translates to a 0 25 mm land pad with a 0 30 mm solder mask opening as shown in Figure 2 Tm mMm mmm Figure 1 ZAD BGA Footprint Top View Figure 2 ZAD BGA Pad Dimensions Table 1 Dimensions for Figure 2 Designator Description Size A Ball Pitch 0 50 mm 19 68 mil Landing Pad Size 0 2
42. a Circuit PA Pin 1 Input PAD Rape X i Equivalent Ls A V 4 Circuit 1 1 Figure 34 Tiva Microcontroller ADC Input Equivalency Diagram SPMA056 October 2013 System Design Guidelines for the TM4C129x Tiva C Series 41 Submit Documentation Feedback Microcontrollers Copyright 2013 Texas Instruments Incorporated I TEXAS INSTRUMENTS Feature Specific Design Information www ti com 4 9 4 10 4 11 4 11 1 4 11 2 42 If resistor dividers are used to scale an input voltage then best results can be achieved with low value resistors The resistor from the ADC input to ground should ideally be less than 1 kQ Avoid values higher than 10 kQ unless a large filter capacitor is present If the voltage rail or other input being monitored is powered up when the Vp and Vpp Supplies to the part are not care must be taken not to exceed the input injection current specified in the data sheet Ceramic filter capacitors of 1 uF or more can substantially improve noise performance The trade off is a reduction in signal bandwidth as a function of the source impedance and phase shifting Input protection should also be considered especially when converting signals from external devices or where transient voltages might be present The ADC pins on some Tiva C Series devices in ADC mode are not 5V tolerant but do allow some margin over the 3 0V span See the respective
43. ant factors is the I O switching rate and current If only low speed low current switching on the Tiva C Series peripheral pins then acceptable practice rules are likely sufficient If high speed switching is present particularly with simultaneous transitions then best practice rules are recommended NOTE Some of the information in this guide comes directly from the individual Tiva C series microcontroller data sheets The microcontroller data sheets are the defining documents for device usage and may contain specific requirements that are not covered in this design guide You should always use the most current version of the data sheet and also check the most recent errata documents for the part number you have selected Visit www ti com tiva c to sign up for email alerts specific to a Tiva C Series part number This document defines system design guidelines for Tiva C Series microcontrollers with part numbers starting with TM4C129 General Design Information This section contains design information that applies to most Tiva C series microcontrollers including e Package Footprint e PCB Stack Up e General Routing Rules e Power e Reset e Oscillators e JTAG Interface e ETM Interface e System e All External Signals SPMA056 October 2013 System Design Guidelines for the TM4C129x Tiva C Series 3 Submit Documentation Feedback Microcontrollers Copyright 2013 Texas Instruments Incorporated I TEXAS INSTRUMEN
44. ayer 1 6 packages and the decoupling capacitors 10 mil trace impedance for the internal layers Six layer 3 4 10 1 4 14 22 4 4 3 59 69 2 94 10 49 175 74 using asymmetric stripline 10 mil wide traces are recommended for Two layer 1 10 1 4 58 N A 4 3 131 37 1 06 18 34 139 58 routing to power and ground pins of the QFP packages and the decoupling capacitors 3 2 3 2 Differential Trace Impedance The Ethernet and USB interfaces have critical differential impedance requirements Both Ethernet signal pairs should be routed as a 100Q 10 differential pair on the top layer of the PCB with a ground plane as a reference The USB signal pair should be routed as a 900 10 differential pair on the top layer of the PCB with a ground plane as a reference When possible a single ended impedance that is half of the differential impedance should be targeted to determine the initial trace width The optimal way to achieve a specific differential impedance is a two step process During PCB layout the designer should use PCB tools to set the spacing and width of the traces to get close to the target characteristic impedance The second step is performed by the PCB fab house as they adjust the trace space and width to match their specific materials and process NOTE The PCB fab notes should include annotations that specify which traces are to be impedance controlled
45. concerns RMII The RMII signals include ENOREF_CLK ENOTXD 1 0 ENOTXEN ENORXD 1 0 and ENORXDV The RMIl interface runs at a constant 50MHz ENOREF_CLK is a 50MHz 50ppm input to both the TM4C129x microcontroller and the external Ethernet PHY It is important that both the microcontroller and the external PHY receive a clean clock edge from the external clock source such as an oscillator If the microcontroller and the external PHY are close together this can be accomplished by a well balanced tee route If they are more than 2 in 5 08 cm apart a low skew low jitter clock buffer such as the CDCLVC1102 can be used to provide a clean clock to the two destinations The ENORXDV has a slightly different function in RMII mode vs MII mode In RMII mode the ENORXDV combines Carrier Sense and Receive Data Valid functions Review the external Ethernet PHY s data sheet to determine the correct location to connect this signal to when in MII mode On some TM4C129x devices the RMII signals are available on two sets of pins However there is only one MAC within the microcontroller If the user wishes to connect two external Ethernet PHYs using RMI only one interface can be enabled at a time The RMII signal trace lengths should be kept as short as possible ideally under 6 in 15 24 cm Trace length matching across the RMII bus signals to within 2 0 in 5 08 cm is recommended Significant differences in the trace lengths can cause data timing is
46. d are designed for multiple drops These guidelines are not meant to restrict such clocks 5 V Tolerant Inputs The TM4C129x family of microcontrollers do not have 5V tolerant GPIO inputs with the exception of PB1 which is used as USBOVBUS Refer to the device s data sheet for details on this input Unused Pins The preferred connection for an unused microcontroller pin depends on the pin function Each Tiva C Series microcontroller data sheet has a table in the Signals Tables chapter that lists the fixed function pins as well as both the acceptable practice and the preferred practice for reduced power consumption and improved electromagnetic compatibility EMC characteristics If a module is not used in a system and its inputs are grounded it is important that the clock to the module is never enabled by setting the corresponding bit in the RCGCx register Errata Documentation Part of any good system design includes reviewing and understanding any errata associated with the revision of device being used Each family of Tiva C series microcontrollers has a separate published errata document that describes any deviations from the data sheet These advisories must be followed to ensure correct device operation All External Signals This section describes design considerations related to signals that connect directly from the microcontroller to a connector that takes the signal to another board or external device The system design
47. d requires the 4 mil 0 1016 mm trace and space rules to be able to route the I Os from that package refer to Section 3 3 3 The routing of power and ground nets should be done with the wider lower impedance traces wherever possible Accordingly trace width routes should be 10 mil 0 2540 mm or wider from decoupling caps and for main power nets and 7 mil 0 1778 mm or 10 mil 0 2450 mm from the QFP power pins For the BGA it may be necessary to route using a 4 mil trace for a short distance until a wider 7 mil or 10 mil trace can be used When routing a signal that is going to be used as a fast edge rate clock be sure to provide two times the spacing requirement from adjacent signals where possible to reduce crosstalk to and from the clock net For example if routing with a 7 mil wide trace space rule make sure there is a 14 mil spacing between the clock and adjacent signals 3 3 2 Via Sizes PCB fab houses can vary in their capabilities for through hole vias Via size is often limited by the smallest mechanical drill diameter a PCB fab house uses The minimum via pad size is usually required to be the drill size plus an additional adder Drill size 10 mil is quite common for a via pad size Drill size 8 mil and drill size 12 mil are also common The amount of the adder is related to the IPC 6012 class of inspection requested by the customer and annular ring requirement of the customer Boards fabricated and inspected with the IPC 601
48. des are one shot input periodic input and RTC input e PWM outputs operate in 16 bit mode only and therefore both the CCPO and CCP1 can be independently used as PWM outputs External Peripheral Interface EPI The TM4C129x device supports the EPI with a dedicated 8 16 or 32 bit parallel bus The EPI has a variety of memories and peripherals that can work with the EPI module Single SDRAM In SDRAM mode the maximum frequency is 60 MHz Pins used for this mode are EPIOSO EPIOS19 and EPI0S28 EP10S31 refer to TM4C129x device data sheet to see SDRAM signal functions Host Bus Mode Host bus supports 8 and 16 bit interfaces used in SRAM PSRAM and NOR flash memory EPIOSO is the LSB of the address and should be connected to AO of 16 bit memories The three main strobes are Address Latch Enable ALE Write WRn and Read RDn and the polarity of these pins can be configured in software Depending on the mode all of the EPI pins may be used EPIOSO EPI0S35 Refer to the device data sheet for more information on how these signals are used in the various modes System Design Guidelines for the TM4C129x Tiva C Series SPMA056 October 2013 Microcontrollers Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com Feature Specific Design Information 4 11 3 Routing Considerations In EPI mode the TM4C129x device pins are characterized with a 35pF output capacitance To main
49. e Depending on the system design a common mode choke may be helpful to pass EMI testing An ACM2012 common mode choke by TDK is one recommended device If EMI is a concern for the design it is recommended that a footprint for the choke be included in the design placed close to the USB connector Figure 33 shows how two 0805 sized resistors R29 R30 can be placed and later replaced with an ACM2012 choke if needed during system EMI testing e Additional High Speed USB Platform Design Guidelines including more details on using a common mode choke can be found at http Awww usb org Refer to http Awww usb org developers docs hs_usb_pdg_r1_0 pdf 4 3 1 38 Figure 33 USB Routing Example USB Device Only For TM4C129x devices that are used in a device only configuration the only signal used in addition to USBODM and USBODP is USBOVBUS which is located on port PB1 PB1 is 5 V tolerant In USB device only mode USBOVBUS is used to detect when voltage has been applied to or removed from the USB connector which triggers software to manage the internal USB PHY accordingly For a USB device only configuration a 100Q resistor should be placed in series between VBUS on the USB connector and PB1 or alternate GPIO on the microcontroller in order to limit damage caused by any ESD events System Design Guidelines for the TM4C129x Tiva C Series SPMA056 October 2013 Microcontrollers Submit Documentation Feedback Copyright
50. e devices in the TM4C129x family have a hibernation module that runs from a 32 768 kHz clock source used to clock the Real Time Clock RTC circuit within the module accurate even when only Veat is Supplied to the system Refer to the device s data sheet for specifics on the Hibernation Module and the Hibernation Clock Source Specifications There are many readily available crystals that meet the Hibernation Clock Source Specification in the data sheet so there is no need to provide a specific recommended list Some of the Tiva C family parts bring the GNDX signal of the hibernate oscillator circuit out to a ball or pin on the part When the GNDxX signal is available it should be connected to the digital ground plane as shown in Figure 22 for proper operation Early designs may show the crystal load capacitors and GNDX pin connected only to each other without a connection to digital ground Either is a valid configuration however the low impedance connection to the digital ground helps isolate the circuit from external system noise sources When the GNDxX signal has not been brought out to a ball or pin then it has been connected to a GND pin internally For this configuration implement the circuit shown in Figure 23 TIVA Microcontroller Hibernate Oscillator Circuit TIVA Microcontroller Hibernate Oscillator Circuit XOSC1 GNDX 32 768KHz Crystal ik T Figure 22 Hibernate Oscillator Circuit with GN
51. e is 9 mils over drill size of 9 SPMA056 October 2013 System Design Guidelines for the TM4C129x Tiva C Series Microcontrollers 11 Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated I TEXAS INSTRUMENTS General Design Information www ti com Table 5 Via Sizes and Properties continued Min Bea SS ua Soars en cap tor Mamos ma ie mil mil Diam mil pF nH Ohms 3 3 3 12 mil A standard via pad size 20 mils that is 10 mils over the drill size of 10 Good for vias for power traces 20D10 20 10 62 28 4 3 0 94 1 33 1 32 37 57 and general I O traces Achievable by a large number of PCB fab houses A standard via pad size 22 mils that is 12 mils over the drill size of 10 Good for vias for power traces 22D10 22 10 62 30 4 3 1 03 1 33 1 32 35 81 and general I O traces Achievable by an even wider number of PCB fab houses 212 Ball BGA Escape routing The populated balls on the 212 Ball BGA package See Section 3 1 1 and the choice of their functions were arranged to allow all I O signals to be routed from the BGA on a four layer board See Section 3 2 1 using 4 mil traces with 4 mil spacing and 18 mil diameter vias This section talks about how to route all I O signals away from the BGA also known as Escaping the BGA with the following considerations in mind e Standard process 4 mil trace 4 mil space and 18 mil dia
52. e the best clocking scheme and maximum distance the microcontroller can be from the external USB PHY Typically the distance will be 6 inches or less ULPI pins should be configured for 12mA drive strength to meet timings SSI Buses All the SSI buses can communicate in Advanced Bi or Quad SSI mode SSIO bus is located on GPIO port A SSI1 bus is located on GPIO port B and port E SSI2 bus is multiplexed between GPIO port D and or port G and SSI3 is multiplexed between using GPIO port F and or port Q and port P if using Quad SSI All SSI buses have equivalent functionality Due to errata number SSI 03 SSI1 bus can only be used in legacy mode If the SSI bus is used a 10K pull up should be placed on SSIXFSS to prevent any unexpected accesses prior to code booting and the pins being configured For all SSI buses when in legacy mode SSIxXDAT0O is SSIxTX Output SSIXXDAT1 is SSIxRX Input If using quad SSI mode SSIxXDAT2 and SSIxXDAT3 are used and a 10KQ pull up to Vpp should be placed on these pins for proper operation until the flash is configured for quad access SPMA056 October 2013 System Design Guidelines for the TM4C129x Tiva C Series 39 Submit Documentation Feedback Microcontrollers Copyright 2013 Texas Instruments Incorporated I TEXAS INSTRUMENTS Feature Specific Design Information www ti com 4 6 4 7 4 7 1 40 If operating at the maximum 60 MHz clock rate into the maximum load of 25pF the 12mA dri
53. eeeee eens eee eee eeeeee sees esada sasas aisanana 43 ANA GPIO sairone a E awd salms E E E EE EEE 44 AAD Hibernate Signals sses AE EE AE CS EEEN 45 5 System Design EXAM ple S inasre EE EEEE E 46 6 GCONCIUSION srorsnenni oee a e E 46 7 ReferenCES sdidsdwecictteieddoneh tastier a O A a a a a a 46 Tiva TivaWare are trademarks of Texas Instruments ARM is a registered trademark of ARM Limited All other trademarks are the property of their respective owners SPMA056 October 2013 System Design Guidelines for the TM4C129x Tiva C Series 1 Submit Documentation Feedback Microcontrollers Copyright 2013 Texas Instruments Incorporated IJ TEXAS INSTRUMENTS www ti com List of Figures 1 ZAD BGA Footprint TOP VIEW iieseteot cite Saeed te Dia teva ce hada E N EEEE 4 2 ZAD BGA Pad Dimensio S csv use a AEE EE 4 3 123 Pin TOE RP ROOLIIN arsa T EEA EEE 5 4 Typical Four Layer PCB Stack with Routing Assignments ssssssssssssssnnnnnnnnnnnnnnnnnnnnnnnnnnrnnnnnnnnnn 6 5 Typical Two Layer PCB Stack with Routing Assignments assssssssssssnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 7 6 Typical Six Layer PCB Stack with Routing ASSIQNMenNtS saasssssnsnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 7 7 Transmission LING TYPC ccccceeeeee cece ee se en ee cence eeeeeenee A A 8 8 Differential Transmission Line Types cccee cece cece e ee ee eee ence eeee cence eeeeeneeeeeeeeeneeeneeeeneeeneeeneeeeneee 10 9 Top Layer 212 Ball BGA Escape
54. egrity benefits of avoiding 90 angles is negligible Loops in traces form antennas and add inductance The data shows that if your layout does have antenna loops then mitering the angles to 135 is not going to help Avoid loops in PCB traces Despite these conclusions there are a few simple reasons to continue to avoid 90 angles e There is a higher possibility of an acid trap forming during etching on the inside of the angle especially in acute angles An acid trap causes over etching which can be a yield issue in PCBs with small trace widths e Routing at 45 typically reduces overall trace length This practice frees board area reduces current loops and improves both EMC emissions and immunity e It looks better This consideration is an important factor for anyone who appreciates the art of PCB layout Copper Pours While solid ground and power planes are highly desirable small areas of copper pour should be used cautiously It is often not a good idea to pour every available area on the routing layers of multi layer boards On one and two layer board designs multiple pours might be necessary because dedicated plane layers are not available If used never leave small copper pours floating or unconnected Isolated conductor areas can cause unwanted coupling and EMC problems if they act as antennae Small copper pours should have solid connections to a ground net trace Ideally use several vias to provide a low impedance con
55. ems Do NOT cross Power or Ground Plane Gap Ground or Power Ground or Power Plane Plane Figure 17 Differential Signal Pair Plane Crossing Power This section describes design considerations related to the microcontroller power supply Microcontroller Power Supply Tiva C Series microcontrollers require only a single 3 3V power supply connected to Vpp and Vpp Other supply rails are generated internally by on chip low drop out LDO regulators The most visible internal supply rail is the core voltage Vbpc because it has dedicated power pins for filter and decoupling capacitors During normal microcontroller operation the power supply rail must remain within the electrical limits listed in the microcontroller data sheet Vpp min and Vpp max For optimal performance of the on chip analog modules the supply rail should be well regulated and have minimal ripple Electrical noise sources such as motor drivers relays and other power switching circuits should each have a separate supply rail especially if analog to digital converter ADC performance is a factor The microcontroller has analog power on reset POR and power OK POK circuits that release and assert once the Vpp power supply rails reach specific thresholds The microcontroller also has digital power OK POK and brown out reset BOR circuits that release and assert once the Vbo power supply rails reach specific thresholds Details on the
56. ent TIVA Microcontroller VBAT 51 Ohm Coin 0 1uF Cell Figure 19 Var RC Filter If a dedicated battery is not going to be used Vga can be connected to the same net driving the Vpp pins without adding the RC filter No dedicated decoupling is needed for the Vga pin NOTE If a single ended clock source is used to drive XOSCO to the RTC hibernation module the voltage level of Vsar impacts the acceptable XOSCO input levels Refer to the HIB Oscillator Input Characteristics in the data sheet SPMA056 October 2013 System Design Guidelines for the TM4C129x Tiva C Series 23 Submit Documentation Feedback Microcontrollers Copyright 2013 Texas Instruments Incorporated I TEXAS INSTRUMENTS General Design Information www ti com 3 5 3 5 1 24 Reset This section describes design considerations related to reset External Reset Pin Circuits A special external reset circuit is not normally required Tiva C Series microcontrollers have an on chip Power On Reset POR circuit with a delay to handle power up conditions The RST input pin can be used to hold off initialization of the device if asserted prior to power on reset or to create the equivalent of a power on reset if asserted after power has been applied The input pin can be configured to perform either a system reset power on reset or a simulated full initialization Refer to the External RST Pin section of the System Control chapter in the dev
57. f series termination resistor use is to protect input and output pins from ESD strikes by limiting the currents and voltages seen at these pins This protection is particularly important for signals that go to connectors that are exposed externally to the system and for signals that go through connectors to other boards or cables that remain in the system Higher speed signals that go from board to board typically have resistor values in the 10Q to 330 range Lower speed signals that connect to cables or external connectors typically have resistor values in the 500 to 1500 range System Design Guidelines for the TM4C129x Tiva C Series SPMA056 October 2013 Microcontrollers Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com General Design Information 3 9 3 ESD EMC Protection Any signal from the Tiva C series microcontroller that is exposed outside the system enclosure via a connector should have ESD protection Common examples are Ethernet and USB signals ESD protection for Ethernet is covered in Section 4 1 ESD protection for USB is covered in Section 4 3 In some system environments signals that stay internal but come through a connector from another board or cable can be subject to radiated noise from electrical noise sources such as motor drivers relays and other power switching circuits Radiated noise is particularly a concern for two layer boards that do not have a so
58. gnal This distance limits any crosstalk from neighboring nets Add a footprint for a series resistor close to the clock output pin in order to adjust for any ringing or EMI concerns beyond what changing the I O drive strength can do Typical series resistor values are 00 100 220 or 330 e If probe points are added for clocks place them as close to the clock destination as possible Consider adding a ground point nearby for ease of measurement Clocks look their noisiest near the middle of the net due to reflections Clocks measured at a location other than the destination are usually not representative of of how the signal appears at the destination e When routing a clock to multiple destinations try to group the destination points in the same area In most cases it is best to daisy chain route the clock instead of tee routing the clock to the destinations Tee routing generally causes greater reflections unless carefully balanced When routing a clock to multiple destinations place the most timing sensitive and critical of the destination devices at the end of the net where the clock is the cleanest e The clock should follow the same general path as the data and control signals associated with the interface it clocks to help maintain any relative bus timings e Clocks should avoid crossing splits in the ground or power plane NOTE Clocks that are open collector such as I2C clocks running at 400KHz have a very slow rise time an
59. guide contains design information that applies to most designs Section 3 Topics include important factors in the schematic design and layout of power supplies oscillators and debug accessibility The Feature Specific Design Information section describes specific peripherals and their unique considerations that are relevant to your design Section 4 To further assist you with the design process Texas Instruments provides a wide range of additional design resources including application reports and reference designs See the System Design Examples Section 5 for links to these resources Using This Guide The information in this design guide is intended to be general enough to cover a wide range of designs by describing solutions for typical situations However because every system is different it is inevitable that there will be conflicting requirements and potential trade offs particularly in designs that include high performance analog circuits radio frequencies high voltages or high currents If your design includes these features then special considerations beyond the scope of this application report may be necessary Where possible the distinction is made between preferred practice and acceptable practice This distinction addresses the reality that constraints such as size cost and layout restrictions might not always allow for best practice design When considering which practices to apply to a design one of the most import
60. he targeted differential impedances The only way to guarantee the impedance target is met by the PCB manufacturer is to specify traces as impedance controlled General Layout Design Choices There are a number of layout design choices that can affect PCB fabrication cost assembly costs and operational reliability This section describes some of these choices and the thoughts behind them System Design Guidelines for the TM4C129x Tiva C Series SPMA056 October 2013 Microcontrollers Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com General Design Information 3 3 1 Trace Width and Spacing Trace width and spacing impact the design in many ways The minimum trace width and space on the PCB are two factors defining the cost of the PCB and they are highly dependent on the capabilities of the PCB fab house As a general guideline for low volume production there is a cost increase for a minimum width spacing less than 7 mils 0 1778 mm A large number of PCB fab houses can produce boards with a minimum width spacing of 4 mils 0 1016 mm and a maximum 1 oz finished copper weight on the outer layers Another common minimum width spacing capability point is 5 mil 0 1270 mm These factors are some of the reasons behind the trace width choices in Table 3 and why 7 mil trace width space is recommended for routing I O signals from the QFP packages The BGA Package is denser an
61. ice data sheet for specific details The RST pin should never be left floating It can be driven from a voltage supervisor or other control chip It can be connected to an external RC combination or it can be pulled up using a 0 to 100K resistor connected to Vpp The RST pin input contains a glitch filter to prevent noise from causing a system reset The RST input pin is one of several device reset controls Refer to the System Control chapter in the part data sheet for specific details Because the RST signal routes to the core as well as most on chip peripherals it is important to protect the RST signal from noise This protection is particularly important in applications that involve power switching where fast transitions can couple into the reset line The reset PCB trace should be routed away from noisy signals Do not run the reset trace close to the edge of the board or parallel to other traces with fast transients If you choose to use a capacitor it should be located as close to the pin as possible If the RST signal source is another board it is recommended to add a buffer IC on the Tiva C Series board to filter the signal A simple push switch can be used to provide a manual reset To protect against possible device damage due to electrostatic discharge and to avoid ringing on the RST signal caused by switch bounce and stray inductance add a low value resistor 100 Q in series with the switch Reset circuit options are shown in
62. idelines for the TM4C129x Tiva C Series 21 Submit Documentation Feedback Microcontrollers Copyright 2013 Texas Instruments Incorporated J TEXAS INSTRUMENTS General Design Information www ti com 3 4 5 22 Vreras Vrera Vaera and Vpera can be selected to be the reference voltage for the ADC maximum and minimum conversion values Some Tiva C Series parts have Vacca aNd Vgera brought out to dedicated pins some parts have a dedicated pin for Vaee ANd Vera iS internally connected to GNDA and some parts do not have dedicated pins for Vacca OF Vrera and instead Varra is internally connected to Vppa and Vera is internally connected to GNDA For designs that require high precision ADC conversions and use MCUs that have dedicated Vrera Or Vaera Pins should ensure that the references pins are connected to a high precision voltage reference IF the ADC conversions are not required to be high precision then Vpe should be externally connected to Vbpa and Vpgera Should be externally connected to GNDA NOTE Do not leave Vper OF Vrea UNConnected Vgera Must power up after or simultaneous to Vppa For optimized ADC precision Vae Should be supplied from a high precision reference such as the TI REF3230 Vkera Should be connected to GNDA and a 0 01uF and 1uF filter capacitor pair Caer should be placed as close as possible to the Vkera Vrera pins The Enable and V_IN of the REF3230 should be driven from Vpp
63. ise sources When the GNDX2 signal has not been brought out to a ball or pin then it has been connected to a GND pin internally These devices must be connected as shown in Figure 21 TIVA Microcontroller Main Oscillator Circuit TIVA Microcontroller Main Oscillator Circuit Crystal il ily Figure 20 Main Oscillator Circuit with GNDX2 Figure 21 Main Oscillator Circuit without GNDX2 The device data sheet provides a list of recommended crystals that have been simulated to work with the main oscillator and includes recommended values for C C and Rg It may be possible to substitute other manufacturer s crystals with like crystal parameters and frequencies Crystals with C values of 18pF or greater or that support a maximum drive of less than 200uW are not robust enough to be used Crystal Cy It is possible to use a single ended clock source such as an external oscillator to drive the OSCO input of the Main Oscillator Circuit Refer to the device s data sheet for input specifications When a single ended clock source is used the OSC1 pin should be left unconnected and GNDX2 if present should be connected to GND SPMA056 October 2013 System Design Guidelines for the TM4C129x Tiva C Series 25 Submit Documentation Feedback Microcontrollers Copyright 2013 Texas Instruments Incorporated I TEXAS INSTRUMENTS General Design Information www ti com 3 6 1 2 Hibernate Oscillator Circuit 26 Some of th
64. lid ground plane to shield the signals from this type of noise For signals that fall into this category it is recommended that PCB footprints be included in the design to allow for the components shown in Figure 27 or Figure 28 Package options for the TVS diodes that support multiple I O are also available The exact resistor values and TVS diode configuration is highly system and environment dependent Timing requirements of the interface input or output signal direction exposure to electrical noise sources and IEC test level must be taken into account when determining what values to use TIVA Microcontroller GPIO TIVA Microcontroller GPIO Connector Connector 10 150 Q 10 150 Q TPD1ExxB TPD1ExxU Figure 27 General Protection Using Bi direction TVS Figure 28 General ESD Protection Using Uni direction Diode TVS Diode Table 10 lists some recommended TI ESD protection options for use with the Tiva C series microcontrollers Table 10 ESD Protection Options Part Description TPD1E10B06 Bi Directional ESD protection for low speed I O with 6V breakdown voltage and 12pF IO capacitance TPD1E05U06 Uni Directional ESD protection for high speed I O with 6 5V breakdown voltage and 0 45pF IO capacitance TPD2E001 2 Channel Low Capacitance ESD protection array for high speed data interfaces TPD4E1B06 Quad Channel High Speed ESD Protection Device side Ethernet TPD4S012DRYR 4 Channel ESD P
65. meter vias also known as 0 8 mm routing rules are the smallest needed to escape the BGA e The BGA can be routed using a minimum of a four layer board with two routing layers on top and bottom a ground plane and a power plane e Required power routing and capacitor decoupling placement for all power rails can be achieved using 0402 sized capacitors e Routing of impedance controlled traces is a priority nmnmmmmmmnon Figure 9 Top Layer 212 Ball BGA Escape Routing Figure 10 BGA Escape Routing Through Depopulated Ball Location Figure 9 shows the recommended top layer routing pattern used to escape the BGA The black dots are the 0 25 mm 9 84 mil BGA landing pads Also shown as B in Figure 10 The black circles with white centers are 0 457 mm 18 mil vias System Design Guidelines for the TM4C129x Tiva C Series SPMA056 October 2013 Microcontrollers Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com General Design Information Some things to note about Figure 9 For the outer two rows of balls all but four signals route on the top layer to escape the BGA Routing from the second row of balls between balls with a 0 5 mm 19 69 mil spacing and 0 1 mm 4 0 mil trace space is not possible Traces from the second row of balls must be routed through the opening left by the depopulated ball in the first row as shown in Figure 10 where E is 0 1 mm 4 mil
66. microcontroller based design The use of the TivaWare for C Series Peripheral Driver Library also minimizes software changes to the start up routines that configure the I O enabling application code to be moved to the new devices with minimal functional changes References The following related documents and software are available on the Tiva C Series web site at www ti com tiva c e Tiva C Series TM4C Microcontroller Data Sheet individual device documents available through product selection tool e TivaWare for C Series Driver Library Available for download at www ti com tool sw tm4c drl e TivaWare for C Series Driver Library User s Manual literature number SPMU298 e Tiva cC Series PinMux Utility Available for download at www ti com tool tm4c_pinmux System Design Guidelines for the TM4C129x Tiva C Series SPMA056 October 2013 Microcontrollers Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections enhancements improvements and other changes to its semiconductor products and services per JESD46 latest issue and to discontinue any product or service per JESD48 latest issue Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All semiconductor products also referred to herein as comp
67. mil trace and space rules can be used to Four layer route I O signals from the QFP packages 1 4 5 1 4 8 N A 4 3 79 42 1 76 11 09 139 58 These rules result in a slightly lower Six layer 1 6 impedance but higher capacitance than 4 mil traces 5 mil trace impedance of asymmetric stripline on internal layers 3 and 4 of a six layer board Six layer 3 4 5 1 4 14 224 43 76 82 2 29 13 50 175 74 Note H1 H2 results in similar impedance to outer layers but higher capacitance and propagation delay 5 mil traces are generally not applicable to 2 Two layer 1 5 1 4 58 N A 4 3 N A N A N A N A layer designs and are outside the constraints of the PCB calculator used 7 mil trace and space rules can be used to Four layer route I O signals from the QFP packages 7 1 4 7 1 4 8 N A 4 3 69 98 1 99 9 77 139 58 mil trace width is recommended for routing Six layer 1 6 I O signals from the QFP packages when space is available 7 mil trace impedance for the internal layers Six layer 3 4 7 1 4 14 224 43 68 67 2 56 12 07 175 74 using asymmetric stripline 7 mil trace and space rules are recommended Two layer 1 7 1 4 58 N A 4 3 142 10 0 98 18 83 139 58 for routing I O signals from the QFP packages on two layer boards Four layer 10 mil wide traces are recommended for 1 4 10 1 4 8 N A 4 3 59 24 2 36 8 27 139 58 routing to power and ground pins of the QFP Six l
68. mponents may be promoted specifically to facilitate safety related applications With such components TI s goal is to help enable customers to design and create their own end product solutions that meet applicable functional safety standards and requirements Nonetheless such components are subject to these terms No Tl components are authorized for use in FDA Class III or similar life critical medical equipment unless authorized officers of the parties have executed a special agreement specifically governing such use Only those TI components which TI has specifically designated as military grade or enhanced plastic are designed and intended for use in military aerospace applications or environments Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer s risk and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use TI has specifically designated certain components as meeting ISO TS16949 requirements mainly for automotive use In any case of use of non designated products TI will not be responsible for any failure to meet ISO TS16949 Products Applications Audio www ti com audio Automotive and Transportation www ti com automotive Amplifiers amplifier ti com Communications and Telecom www ti com communications Data Converters DLP Products DSP Clocks and Timers Interface Logic
69. must ensure that the ground reference of any incoming signal is the same as the microcontroller ground If the grounds do not match the signal level seen at the input pin of the microcontroller might be significantly higher than what the data sheet specifies Ground connections between boards should be low impedance and as short as possible System Design Guidelines for the TM4C129x Tiva C Series SPMA056 October 2013 Microcontrollers Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com Feature Specific Design Information The system design should avoid routing the Vpp 3 3V supply that connects to the microcontroller directly to a connector pin that can be subject to ESD or EMC radiated emissions If Vpp does need to be routed to a connector it should be routed through a ferrite bead and optionally a TVS diode I O signals that are sourced from cables or other boards should not be driven prior to the power being applied to the microcontroller unless the strict guidelines for injection current and voltage limits from the data sheet are followed External I O signals that come directly from the microcontroller should have layout options to implement ESD protection as described in Section 3 9 3 4 Feature Specific Design Information This section contains feature specific design information and is grouped by function or peripheral Ethernet PHY e Comparators Ethernet MII
70. n the PCB stack up can significantly change the impedance Table 3 Single ended Trace Properties by Width and Stack up H Configuration W T Zo Co Lo Tpp and Layer mil mil frail H2 Er Ohms pF in nH in ps in Notes 4 mil trace and space rules 0 8 mm routing Four layer rules can be used to route I O signals from 1 4 4 1 4 8 N A 4 3 85 26 1 64 11 90 139 58 the BGA package This trace width can also Six layer 1 6 be used to route I O signals from the QFP packages 4 mil trace impedance of asymmetric stripline on internal layers 3 and 4 of a six layer board Six layer 3 4 4 1 4 14 224 43 82 03 2 14 14 42 175 74 Note H1 H2 results in similar impedance to outer layers but higher capacitance and propagation delay 4 mil traces are generally not applicable to Two layer 1 4 1 4 58 N A 4 3 N A N A N A N A two layer designs and are outside the constraints of the PCB calculator used 8 System Design Guidelines for the TM4C129x Tiva C Series Microcontrollers SPMA056 October 2013 Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com General Design Information Table 3 Single ended Trace Properties by Width and Stack up continued H Configuration W T 4 Zo Co Lo Tpp and Layer mil mil aii H2 En Ohms pF in nH in ps in Moles 5
71. nclosures or apertures in the enclosure see Figure 13 J Tiva Gap to avoid q C Series No plane under loop antenna MCU E Ethernet transformer Capacitor for ESD discharge path sometimes included in Ethernet magnetics Figure 13 Chassis Ground Guidelines SPMA056 October 2013 System Design Guidelines for the TM4C129x Tiva C Series 15 Submit Documentation Feedback Microcontrollers Copyright 2013 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS General Design Information www ti com 3 3 7 16 Routing Across Plane Splits Avoid discontinuities in ground planes and power planes under high speed signals as shown in Figure 14 For all signals a break in the ground plane removes a direct path for any return current to flow through This consideration is important even for balanced differential pairs because perfect matching is seldom achievable and ground current is inevitable Plane A Plane A Plane B Plane B Do not route signals over non continuous plane Poor PCB trace routing Good PCB trace routing Figure 14 Examples of PCB Trace Layout Tiva C Series microcontrollers provide programmable drive strength for all digital output pins When initially bringing up the design the drive strength for the output pins of a high speed interface should be set to 8mA to avoid any marginal timing requirements associated with too low of a drive strength However if a signal is showing signal integrity iss
72. nection System Design Guidelines for the TM4C129x Tiva C Series SPMA056 October 2013 Microcontrollers Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com General Design Information 3 3 6 Chassis Ground When properly designed a chassis ground routed on the PCB can be a very effective feature for addressing a range of EMC challenges One specific benefit is improved electro static discharge ESD immunity due to the provision of a safe discharge path that avoids sensitive circuitry in the center of the board In general a chassis ground on the PCB works in conjunction with the overall enclosure to improve electro magnetic emissions and especially immunity The chassis ground should be routed or poured copper around the perimeter of the PCB ideally on all layers If the ground is not present on all PCB layers then other layers should be pulled back from the chassis ground to avoid coupling The chassis ground should not route over the top of any power or ground layer Typically the chassis ground should have a break or void in it to prevent loops that could cause loop antenna effects However depending on the size of the board enclosure design and ground connection point locations it might still be acceptable or preferable to have a continuous chassis ground around the board A chassis ground is particularly important in systems with external connectors metal e
73. ntial routing of the signals they are protecting without the need for stubs or vias Many packages have no connect pins that allow routing of the differential signal through the protection circuit and a no connect pin in order to maintain signal spacing Does Not Maintain Parallelism Ground or Power Plane Figure 15 Differential Signal Pair e Avoid stubs in differential signal pairs where possible as shown in Figure 15 and Figure 16 Where termination or bias resistors are needed one terminal should be located directly on the trace Both resistors should be located at the same distance from the source and load Resistors should be located at the same distance on the trace pair 502 pO Very poor stub length Poor differential pair routing Improved differential pair routing Figure 16 Examples of Differential Pair Layout PCB trace lengths should be kept as short as possible SPMA056 October 2013 System Design Guidelines for the TM4C129x Tiva C Series 17 Submit Documentation Feedback Microcontrollers Copyright 2013 Texas Instruments Incorporated I TEXAS INSTRUMENTS General Design Information www ti com 3 4 3 4 1 18 e Differential signal traces should not be run such that they cross a plane split as shown in Figure 17 A signal crossing a plane split may cause unpredictable return current paths resulting in an impedance mismatch which can impact signal quality and potentially create EMI probl
74. ocontroller and directly at the ESD suppressor and USB connector may not be possible to achieve Minimize these deviations as much as possible being sure to maintain symmetry SPMA056 October 2013 System Design Guidelines for the TM4C129x Tiva C Series 37 Submit Documentation Feedback Microcontrollers Copyright 2013 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS Feature Specific Design Information www ti com Follow the recommendations for routing differential pairs as detailed in Section 3 3 8 The individual traces within the differential pair should be length matched to within 0 150 in 3 81 mm e Avoid stubs when adding components to D and D signals Devices such as ESD suppressors should be located directly on the signal traces as shown in Figure 16 e Maintain symmetry when routing differential pairs Some PCB layout tools can assist with this kind of routing Avoid vias if possible If it is necessary to switch layers then both signals in the pair should pass through a via at the same distance on the trace e Total trace length for the USB differential pair should be limited to 12 in 30 48 cm e Place ESD suppressors as close as possible to the USB connector to minimize any areas of impedance discontinuities Refer to Table 10 for recommended ESD suppressors e For best ESD and EMI performance create a chassis ground to which the metal shield of the USB connector is connected as shown in Section 3 3 6
75. onents are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment Tl warrants performance of its components to the specifications applicable at the time of sale in accordance with the warranty in Tl s terms and conditions of sale of semiconductor products Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by applicable law testing of all parameters of each component is not necessarily performed Tl assumes no liability for applications assistance or the design of Buyers products Buyers are responsible for their products and applications using TI components To minimize the risks associated with Buyers products and applications Buyers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right relating to any combination machine or process in which TI components or services are used Information published by TI regarding third party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual
76. onnected to any kind of external source or load SPMA056 October 2013 System Design Guidelines for the TM4C129x Tiva C Series 19 Submit Documentation Feedback Microcontrollers Copyright 2013 Texas Instruments Incorporated General Design Information 3 4 3 20 I TEXAS INSTRUMENTS www ti com Decoupling Capacitors Ideally Tiva C Series microcontrollers should have one decoupling capacitor in close proximity to each power supply pin Decoupling capacitors are typically 0 1 uF in value and should be accompanied by a bulk capacitor near the microcontroller The combined Vpp and Vpp bulk capacitance of the microcontroller is typically between 2 uF and 22 uF with values on the upper end of that range providing measurable ripple reduction in some applications especially if the circuit board does not have solid power and ground planes Bulk capacitance is particularly important if the microcontroller is connected to high speed interfaces or must source significant GPIO current that is greater than 4mA on more than a few pins For optimal performance locate one decoupling capacitor adjacent to each Vpp power and ground pin pair At a minimum there should be one decoupling capacitor on each side of the microcontroller package connected between Vpp and Ground Vopa GNDA and packages that support Vacra Vacra have specific decoupling requirements as defined by Crer in the data sheet Refer to Section 3 4 5 for additional
77. operate in device mode In order to limit damage from ESD events a 1000 resistor should be placed in series between the ID pin on the USB connector and USBOID PBO on the microcontroller To support full USB OTG negotiation using the SRP and HNP protocols VBUS from the USB connector must be directly connected to USBOVBUS PB1 of the microcontroller without a series resistor in between In this case USBOVBUS should be connected to an ESD suppressor such as a TVS diode or ESD resistant VBUS switch USB ULPI External PHY Interface TM4C129x devices that support USB and ULPI can attach to an external USB PHY ULPI uses 12 pins to interface between the USB controller within the microcontroller and an external PHY The ULPI specification and additional information on ULPI can be found at the ULPI working group page www ulpi org ULPI uses a 60 MHz clock Standard operation is for the USB PHY to generate the clock Optionally the PHY can receive the clock as an input The TM4C129x microcontroller can be configured to use the input clock from the USB PHY or to output the 60 MHz clock to the USB PHY A population option for a series resistor should be placed at the source device for the ULPI clock in order to address any system EMI issues found during systems test ULPI timings of both the TM4C129x microcontroller and the external USB PHY must be reviewed and a timing budget for both control timings and data transfers should be developed to determin
78. operation and threshold levels of these circuits can be found in the data sheet for the part The supply connected to Vpp must accommodate a short period 40uSec to 60uSec of additional inrush current that occurs as the decoupling capacitors connected to the LDO on the Vpp rail charge up to the Vopc voltage level Internal circuitry limits the inrush to the lijausy max specified in the data sheet for the part The supply connected to Vpp can self limit the current it supplies to something less than the maximum linausy however that extends the period it takes to bring Vppc up to operating voltage External supervisors may also be used to assert the external reset signal RST under power on brown out or watchdog expiration conditions System Design Guidelines for the TM4C129x Tiva C Series SPMA056 October 2013 Microcontrollers Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated l TEXAS INSTRUMENTS www ti com General Design Information 3 4 2 LDO Filter Capacitor Vppc All Tiva C Series microcontrollers have an on chip voltage regulator to provide power to the core The voltage regulator requires a filter capacitor to operate properly see the Cipo parameter in the corresponding microcontroller data sheet for acceptable capacitor value range The Cpo capacitance is the sum of the capacitor values on the Vp pins The recommended Vpp capacitor solution taking tolerance into account consists
79. r USB and Ethernet connections Four Layer Stack up A four layer stack up two signal layers two power planes is recommended for most designs A four layer stack up has the following benefits A solid ground plane reference for USB and Ethernet signals that have a specific impedance target e Low impedance power and ground connections to components and decoupling capacitors through the planes e High speed signals have lower impedance smaller propagation delay and more immunity to crosstalk due to the closer distance to the reference plane on a four layer design as compared to a two layer design e Analog signals have more immunity to crosstalk and the analog modules in the device can provide higher precision results when used with the solid ground plane reference that a four layer stack up provides A typical configuration for an FR 4 0 062 in 1 5748 mm circuit board with four layers of 1 0z copper is shown in Figure 4 1 0z Copper Signal Layer 2 Sheets 2116 0 008 1 0z Copper Ground Plane A 0 06 10 Core 0 040 1 0z Copper Power Plane j q _ 2 Sheets 2116 0 008 1 0z Copper Signal Layer Y Figure 4 Typical Four Layer PCB Stack with Routing Assignments For this example we place a solid ground plane on layer 2 and a power plane on layer 3 The outer signal layers each consist of 1 2 0z base copper with 1 2 0z plating to total 1 0z copper Each 1 oz copper layer is 1 4 mils 0014 in
80. r tap of the isolated windings RJ 45 side of the transformer has Bob Smith termination through 75Q resistors R64 R65 in Figure 29 and a 1000pF capacitor C90 in Figure 29 to chassis ground The termination capacitor should be rated to a voltage of at least 2kV In certain applications an alternate method of connecting the internal PHY to another device may be desirable Specifically designs for applications where a backplane is the choice of media between devices In these applications DC isolation must be maintained while providing an AC signal coupling path by using capacitors for the connection instead of magnetics This type of configuration is not IEEE compliant and data sheet specifications are not guaranteed For details on the transformerless configuration refer to TI Application Report SLLA327 RJ 45 Connections Use of a metal shielded RJ 45 connector with the shield connected to chassis ground is recommended to improve EMI performance Bob Smith termination to the RJ 45 connector involves 75Q termination resistors connected to the unused differential pair connections on the RJ 45 connector R66 R67 in Figure 29 Bob Smith termination is used to reduce noise resulting from common mode current flows as well as reduce susceptibility to any noise from unused wire pairs on the RJ 45 NOTE A modified Bob Smith termination is required for Power Over Ethernet PoE applications which consists of DC blocking capacitors in
81. re 25 Recommended Layout for Crystal with GNDX Connection SPMA056 October 2013 System Design Guidelines for the TM4C129x Tiva C Series 27 Submit Documentation Feedback Microcontrollers Copyright 2013 Texas Instruments Incorporated I TEXAS INSTRUMENTS General Design Information www ti com 3 7 3 7 1 28 JTAG Interface This section describes design considerations related to the microcontroller JTAG interface Debug and Programming Connector When designing a board that uses a Tiva C Series microcontroller it is preferable to provide connections to all JTAG SWD signals In pin constrained applications SWD can be used instead of JTAG SWD only requires two signals SWCLK and SWDIO instead of the four signals that JTAG requires freeing up two additional signals for use as GPIOs Check that your preferred tool chain supports SWD before choosing this option The LM Flash Programmer utility can program devices using SWD The most common ARM debug connector is a 2x10 way 0 1 in pitch header Although it is robust the 0 1 in header is too large for many boards and is considered legacy implementation An alternate connector definition which is now quite popular uses a 0 05 in half pitch 2x5 connector known as the Cortex Debug Connector The applicable assignments for both connectors are shown in Table 9 Table 9 Applicable Debug Connector Pin Assignments P Legacy ARM 20 pin Cortex Debug Connector 10 pin JT
82. rotection for USB HS USB OTG 3 9 4 Interrupt Pin Selection Any GPIO pin in the microcontroller can be used as an interrupt input pin In most cases there is one interrupt vector per GPIO port so the interrupt service routine must check status registers to determine which port pin generated the interrupt The system designer must determine if it is more desirable to group more than one interrupt within a GPIO bank or separate interrupts to unique GPIO banks Some Tiva C Series microcontrollers have one or two GPIO banks where each individual pin in that bank has a unique interrupt vector Consult the device s data sheet to determine which GPIO pins have this capability SPMA056 October 2013 System Design Guidelines for the TM4C129x Tiva C Series 31 Submit Documentation Feedback Microcontrollers Copyright 2013 Texas Instruments Incorporated I TEXAS INSTRUMENTS General Design Information www ti com 3 9 5 3 9 6 3 9 7 3 9 8 3 10 32 Clock Routing Special attention should be paid to any pins or nets that are used as clock signals The cleanest clock is one that routes directly from an output pin to an input pin without stubs tees or multiple destinations The following guidelines should be considered when routing clock signals e Give clocks 2x spacing from other signals Fore example if a 7 mil trace with 7 mil space routing rules are being used give 14 mil spacing between the clock and any other si
83. s on the top layer with a trace width and differential spacing tuned to the PCB stack up for 1000 differential impedance as detailed in Section 3 2 3 2 It may be difficult to implement a trace geometry that achieves both 100Q differential impedance and 50Q single ended impedance The most critical parameter to optimize in this design is the 1000 differential impedance e Follow the recommendations for routing differential pairs as detailed in Section 3 3 8 The individual traces within the differential pair should be length matched to within 0 05 in 1 27 mm e Separate the Ethernet transmit pair from the receive pair by at least 0 050 in 1 27 mm This requirement is necessary to avoid cross coupling between the RX and TX pairs e Place Ethernet termination resistors as close as possible to the Tiva C Series microcontroller e Place the Ethernet transformer within 1 in 2 54 mm of the RJ 45 connector e Place 0 1uF capacitors close to the Ethernet transformer Refer to C40 and C66 in Figure 32 e Acontinuous ground plane is a good PCB design practice however there are special considerations when using planes and copper pours near Ethernet signals The following restrictions apply only to SPMA056 October 2013 System Design Guidelines for the TM4C129x Tiva C Series 35 Submit Documentation Feedback Microcontrollers Copyright 2013 Texas Instruments Incorporated I TEXAS INSTRUMENTS Feature Specific Design Information www
84. ses noise on the conversion result increases Noise sources include coupling from other signals power supplies external devices and from the microcontroller itself Refer to the TM4C 129x data sheet for specifics on the analog input impedance with respect to the sample and hold circuit A 500Q effective input impedance Zs is required to support the maximum input sampling period of 250ns This input impedance allows the voltage on the ADC input pin to charge Canc to the input pin voltage going through Rap Refer to Figure 34 for the ADC Input Equivalency Diagram and to the part data sheet for the values of Capo and Rape If voltage rails are to be monitored adequate capacitance is required to hold the voltage during the sampling period The exact amount of capacitance Cs depends on the accuracy required the amount of time between samples and the resistor values used for any voltage divider circuit The TM4C129x devices allow the ADC sample period to increase which provides additional time for the Capc Capacitor in Figure 34 to charge and higher effective input impedance Zs Tiva Microcontroller Input PAD 4 Equivalent 1 Circuit Z ESD clamps iiis i pe to GND only i f i 1 i 1 i R n Rs Pin i Poy ADC 12 bit MWe 1 o o SAR ADC 1 12 bit i i Converter i Clamp Word my Vs a Vapcin j i Pes ae i o ke E Pa e 1 i Pin 1 Input PAD H Rane KH i Equivalent a Aaea AVA Aaa
85. solution that can be placed on the device side of the transformer between the termination resistors on the differential pairs and the transformer is TI s TPD4E1B06 This device is not shown in Figure 29 Ethernet LEDs The LEDs associated with the internal Ethernet PHY ENOLEDO ENOLED1 ENOLED2 are multiplexed in several locations with some of the microcontrollers GPIOs Refer to the Signal Tables section of the device s data sheet Any of the ENOLEDs can perform any of the internal Ethernet PHY LED functions The ENOLEDs can be connected such that current is sourced from the GPIO through a resistor and into the anode of an LED Refer to Figure 30 or the GPIO can be connected to the cathode of the LED and sink current Refer to Figure 31 All ENOLEDs must be wired up in the same manner It is common to have LEDs as part of the RJ 45 which are connected up no different than discrete LEDs VDD TIVA Microcontroller ENOLEDO TIVA Microcontroller ENOLEDO ENOLED1 ENOLED2 ENOLED1 ENOLED2 Figure 30 GPIO Sourcing LED Current Figure 31 GPIO Sinking LED Current Ethernet PHY PCB Layout Good PCB layout and routing practices are important to ensure reliable Ethernet signaling as shown in the example depicted in Figure 32 Follow these design rules and recommendations when routing the MDI interface of the Integrated Ethernet PHY for best results e Route the transmit and receive differential pair
86. sues GPIO drive strength for the RMII signals should be set to 8mA to achieve timings specified in the microcontroller data sheet Series resistors are recommended on the RMII signals to prevent ringing and EMI concerns USB The TM4C129x family of microcontrollers includes devices that support an internal USB 2 0 PHY capable of full soeed operation Refer to the data sheet of the device being used to determine which of the following configurations the device supports This internal PHY supports USB Device Only USB Embedded Host and USB OTG operation The TM4C129x family of microcontrollers also has the ULPI that interfaces to a external high speed PHY as discussed in Section 4 4 The critical component of the internal USB PHY is the bidirectional differential data pins USBODM D and USBODP D The following design rules and recommendations should be followed when routing the USB differential pair for best results e Route the USB differential pair on the top layer with a trace width and differential spacing tuned to the PCB stack up for 90Q differential impedance as detailed in Section 3 2 3 2 It may be difficult to implement a trace geometry that achieves both 90Q differential impedance and 450 single ended impedance The most critical parameter to optimize in this design is the 900 differential impedance The trace width and spacing to maintain the required 90Q differential trace impedance directly at the pins of the micr
87. tain timing margins over the full operating speed of the EPI module EPI signal capacitance including boh load and trace capacitance must be 35pF or less and the GPIO drive strength must be configured for 8mA Additionally when EPI0S31 is used as a high speed clock pin it must be configured to 12mA in order to maintain timing margins It is not necessary to include the TM4C129x device pin and pad characteristics when evaluating total capacitance Total trace length should be limited to 6 in 15 24 cm for full operating speed Make an effort to keep trace lengths for clock and data similar lengths and give the clock signal 2X width spacing from other signals to avoid crosstalk 4 12 LCD Controller Some TM4C129x devices include an LCD controller This controller works with character based panels passive matrix LCD panels active matrix LCD panels and OLED panels using either LIDD or Raster mode The signal interface to the LCD panel is a likely ESD exposed interface Use of series resistors on all the LCD interface signals is recommended The value of the resistor can be in the range of 100 to 1500 depending on the system environment and the required speed of the LCD interface The LCD outputs should be configured for 8mA drive strength to achieve the timings specified in the devices data sheet 4 12 1 LIDD Mode The LIDD controller supports the synchronous and asynchronous LCD interface The pins used in LIDD mode are LCDDATA00 LCDDATA15 LC
88. ternal Ethernet PHY is configured for address 0 leaving addresses 1 7 for any external Ethernet PHY Refer to the data sheet of the external Ethernet PHY being used to determine how to configure the PHY s MDIO address The interrupt from the external Ethernet PHY should be connected to the ENOINTRN pin function of the microcontroller Refer to the TM4C129x devices data sheet for full details on the MAC interface signals 36 System Design Guidelines for the TM4C129x Tiva C Series SPMAO056 October 2013 Microcontrollers Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated l TEXAS INSTRUMENTS www ti com Feature Specific Design Information 4 2 1 4 2 2 4 3 The MII signals include ENOTXCK ENOTXDJ8 0 ENOTXEN ENORXCK ENORXDJ 3 0 ENORXDV ENORXER ENOCOL and ENOCRS ENOTXCK and ENORXCK are generated from the external Ethernet PHY and run at 2 5MHz for the 10Base T communication speed and 25MHz for the 100Base T communication speed The MII signal trace lengths should be kept as short as possible ideally less than 6 in 15 24 cm Trace length matching across the MII bus signals to within 2 0 in 5 08 cm is recommended Significant differences in the trace lengths can cause data timing issues GPIO drive strength for the MII signals should be set to 8mA to achieve timings specified in the microcontroller data sheet Series resistors are recommended on the MII signals to prevent ringing and EMI
89. tions related to the microcontroller ADC module ADC Inputs In order to achieve the best possible conversion results from an ADC it is important to start with a good schematic design All ADCs require a voltage reference or occasionally a current reference whether the voltage reference is provided from an on chip source or via an external pin Any deviation in the reference voltage from its ideal level results in additional gain error or slope error in the conversion result For optimal ADC performance a precision voltage source should be used to supply the Var pin when available as a separate pin on the part or Vbpa pin on parts that have Vger internally connected to Vppa Refer to Section 3 4 5 for additional details on the filter capacitance required for ADC performance Refer to the part data sheet for ly specification maximum that the precision voltage source must supply There are up to 24 pins on the TM4C129x family of devices that support analog inputs AINOO AIN23 All inputs can be used in single ended mode while differential mode is supported for consecutive even odd pairs All analog inputs are equivalent in function and capability Selection of which analog inputs to use should be based on ease of PCB routing and pin muxing selection Optimal ADC accuracy is achieved with a low impedance source Rs and a large input filter capacitor Cs as shown in Figure 34 As the signal source impedance increases and capacitance decrea
90. to ensure there is no solder bridging between pins Paste Mask is typically the same size as the pad 0 oversize Decal Preview Pin ilkocation Default Side Bottom X Place Left Origin Heght H 12 Center Pini Pins Placement outline Horizontal pins 32 Numbering direction iii z Oxkwse CCW Width 17 05 Verticalpins 32 Height 17 05 a a gt ADI gt 4 fidth L e 4 z width 0 25 ength 1 2 overander elze Papih 0 4 Solder 9 Row pitch Paste 0 a Measurement type Center to Center SA gt i Thermal TAF EMITA Horizontal 15 4 2 Vertical 15 4 z eee Create Pin ishope Pin shape Rectange oval Rectange oval Honzontal size 4 064 L Views from bottom side Rectangular pins a o Verteal sze 4 064 layer Comer type 90 z a Radue a c Display Colors Actve layer lt All Layers gt X Decal Caladator Show dims Package type Quad Fist Package X g x Protusion variaton rinna z Al Used in cakulations Dimensions Min Max A2 Lead Span 1 15 9 16 1 82 Used Span 18918 L Lead length 045 0 75 W Lead with OCS a Monn Al Body width 13 95 14 05 TSQFP40P 1600X 1600X 120 126N B1 Body length 13 95 14 05 H2 Standoff height 0 05 Woes T On Calculate decal pins wil get measurements and locations according to the standard The following parameters may get updated Origin Width Length Row Pitch Placement outine and Mask over under size A standard decal name wil be generated
91. ues such as ringing and reflections the GPIO drive strength can be lowered to improve the performance as long as timing requirements are still met It is acceptable to route lower speed and slow edge rate signals such as the open collector 12C UART signals and mostly static GPIOs across a plane split however it is preferable to avoid this practice as it can be a source of EMI radiation due to the return current flow path System Design Guidelines for the TM4C129x Tiva C Series SPMA056 October 2013 Microcontrollers Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com General Design Information 3 3 8 Routing Differential Traces e For each differential pair the traces withing the pair should be run parallel to each other and be matched in length Matched lengths minimize delay differences avoiding an increase in common mode noise and increased EMI as shown in Figure 15 It may be impossible to maintain parallelism immediately near the connector ESD component or Tiva C series microcontroller For these cases minimize the distance the traces are not parallel and keep them localized near the start or endpoints of the traces e Ideally there should be no crossover or via on the signal paths Vias present impedance discontinuities and should be minimized Route an entire trace pair on a single layer if possible e Choose ESD components in packages that support good differe
92. ve strength should be selected for all outputs in order to meet data sheet timings Series termination should be used for any outputs UART There are 8 UART modules U0 U7 available on TM4C129x family devices Basic RX TX functionality is the same between them The following are important considerations when selecting UART pins to use e Example software commonly uses UORX on PAO and UOTX on PA1 for debug messages and input If a debug port is to be implemented this location is recommend e UARTO and UART1 offer modem flow control and modem status UART2 UART4 offer modem flow control while UART5 UART7 offer only RX and TX 12C A TM4C129x device can have up to ten I2C buses The buses appear on the l2COSCL I2C9SCL I2CO0SDA I2C9SDA signals Each bus is functionally equivalent to the others and can be either a master or a slave Refer to the nter Integrated Circuit I2C Interface chapter of the TM4C129x data sheet for detailed information The 12C bus requires signals to be configured in open collector mode The I2CSDA pin requires the associated GPIO to be configured as an open collector signal in the GPIOODR register The I2CSCL pin should not be configured in this manner as the pad is designed differently The TivaWare GPIOPinTypel2C API should be used for the I2CSDA pin and the GPIOPinTypel2CSCL API should be used for the I2CSCL pin The 12C pins must be externally pulled up to 3 3V for proper operation Typical pull up values are

System Design Guidelines for the TM4C129x

Contents

Download Pdf Manuals

Related Search

Related Contents