PCIE-1744 User Manual
Contents
1. C 12 1 Interrupt Control Register PCIE 1744 provide 9 sources to generate the interrupt Write 1 to enable the interrupt write 0 to disable The INTE is control the total interrupt FIFO0 HFFIFO 0 Half Full FIFO0 AFFIFO 0 Almost Full FIFO1_HFFIFO 1 Half Full FIFO1_AFFIFO I Almost Full FIFO2 HFFIFO 2 Half Full FIFO2 AFFIFO 2 Almost Full FIFO3 HFFIFO 3 Half Full FIFO3 AFFIFO 3 Almost Full DMA TCDMA counter Terminal Count INTE Total Interrupt Enable C 12 2 Interrupt Flag PCIE 1744 User Manual 66 These bits correspond to the same bit number of the interrupt control reg ister to indicate which interrupt occurred Read I means interrupt occurred INTFO FIFO 0 Half Full interrupt flag INTFI FIFO 0 Almost Full interrupt flag INTF2 FIFO 1 Half Full interrupt flag INTF3 FIFO 1 Almost Full interrupt flag INTF4 FIFO 2 Half Full interrupt flag INTF5 FIFO 2 Almost Full interrupt flag INTF6 FIFO 3 Half Full interrupt flag INTF7 FIFO 3 Almost Full interrupt flag INTF8 DMA counter Terminal Count interrupt flag INTF Total Interrupt flag C 13 Clear Interrupt Write BASE 22 Table C 15 Register for Clear Interrupt Base P Register Forma HEX 15 14 113 12 Mm 110 9 8 7 6 5 48321 0 W Clear Interrupt Clear Interrupt Write any value to this address will clear interrupt It will clear all flags to 0 if ther2. CM2 CM1 CMO Meaning 0 0 0 Analog input CHO offset adjustment 0 0 1 Analog input CHO gain adjustment 0 1 0 Analog input CH1 offset adjustment 0 1 1 Analog input CH1 gain adjustment 1 0 0 Analog input CH2 offset adjustment 1 0 1 Analog input CH2 gain adjustment 1 1 0 Analog input CH3 offset adjustment 1 1 1 Analog input CH4 gain adjustment G1 G0 Calibration range code G1 G0 Input range 0 0 5 to 5 V 0 1 2 5 to 2 5 V 1 0 1 to 1 V 1 1 0 5 to 0 5 V CBUSY Calibration command busy flag This bit indicates the calibration command is complete and ready for next command input 69 Appendix C C 16 BoardiD Read BASE 2C Table C1 Register for BoardID Switch BID3 BIDO BoardID BoardID selector value is from 0 to 15 Please refer to board ID switch setting C 17 Reset DMA Start Channel to CHO Write BASE 30 Table al 1 9 Register for Reset DMA Start Channel to CHO HEX 145114 113 12 11 10 9 8 7 6 5 4 B 2 VU Oh W Reset DMA start channel to CHO Reset DMA start channel to CHO Write any value to BASE 30h to reset DMA transfer data from CHO Before start DMA transfer user has to reset the start channel to CHO This only for four channels DMA data transfer PCIE 1744 User Manual 70 C 18 AD Channel n DATA Read BASE 30 32
3. PCIE 1744 30 MS s Simultaneous 4 ch Analog Input PCI Express Card User Manual Copyright The documentation and the software included with this product are copy righted 2009 by Advantech Co Ltd All rights are reserved Advantech Co Ltd reserves the right to make improvements in the products described in this manual at any time without notice No part of this man ual may be reproduced copied translated or transmitted in any form or by any means without the prior written permission of Advantech Co Ltd Information provided in this manual is intended to be accurate and reli able However Advantech Co Ltd assumes no responsibility for its use nor for any infringements of the rights of third parties which may result from its use Acknowledgements Intel and Pentium are trademarks of Intel Corporation Microsoft Windows and MS DOS are registered trademarks of Microsoft Corp All other product names or trademarks are properties of their respective owners Part No 2003174400 Ist Edition Printed in Taiwan December 2009 PCIE 1744 User Manual ii Product Warranty 2 years Advantech warrants to you the original purchaser that each of its prod ucts will be free from defects in materials and workmanship for two years from the date of purchase This warranty does not apply to any products which have been repaired or altered by persons other than repair personnel authorized by Advantech or which have been s
4. 1 sa Storage volumes Figure 2 3 The Device Name Listed in the Device Manager Note If your card is properly installed you should see the device name of your card listed on the Device Manager tab If you see your device name listed but marked with an exclamation sign it means your card has not been correctly installed In this case remove the card device from the Device Manager by selecting its device name and press the Remove button Then go through the driver installation process again After your card is properly installed on your system you can now start configuration using Device Manager which was installed on your system during driver setup A complete device installation procedure should include board selection and device setup The following sections will guide you through the board selection device setup and operation of your device PCIE 1744 User Manual 16 2 4 Device Setup amp Configuration Device Manager is a utility that allows you to setup configure and test your device and later store your settings on the system registry These settings will be used when you call the APIs of Advantech Device Driv ers Setting Up and Configuring the Device 1 Note To connect I O devices with your card you must first run the Advantech Device Manager program by accessing Start Programs Advantech Automation Device Manager Advan tech Device Manager You can then view the device s already
5. J1 to J4 BNC are analog input connectors Jl is for AIO J2 is for AI1 J3 is for AI2 and J4 is for AI3 25 Chapter 3 PCIE 1744 User Manual 26 CHAPTER Operation This chapter describes the following features ofthe PCIE 1744 card Analog input ranges and gains Analog input acquisition modes e A D sample clock sources Trigger sources Analog Input Data Format Chapter 4 Operation 4 1 Analog Input Ranges and Gains Each channel on the PCIE 1744 can measure bipolar analog input signals ranging within 5 V FSR and can be set up with different input ranges respectively The sampling rate can be up to 30 MS s The PCIE 1744 also provides various gain levels that are programmable on each channel Table 4 1 lists the effective ranges supported by the PCIE 1744 using these gains Table 4 1 Gains and Analog Input Range Gain Code 1 2 5 10 Input Range 5 2 5 1 0 5 For each channel choose the gain level that provides the most optimal range that can accommodate the signal range you have to measure For detailed information please refer to Appendix C 4 AI Range Control 4 2 Analog Input Acquisition Modes The PCIE 1744 can acquire data in single value pacer post trigger delay trigger about trigger and pre trigger acquisition modes These ana log input acquisition modes are described in more details below 4 2 1 Single Value Acquisition Mode The single value acquisition m
6. 3 1 I2Eh W R PCIE 1744 User Manual 56 Table C PCIE 1744 register format Part 4 Base 1 44 Register Format Address HEX 5 114 713 12 1 110 8 7 6 5 4 B 2 0 30h W Reset start read channel to CHO IR JAD Channel n DATA GF 1 10 IR AD Channel n 1 DATA TR OV IGT GUO AD1 GF 1 34h W DMA Request selector AD9 AD8 AD7 AD6 ADS AD4 AD3 AD2 ADT JADO E C 3 A D Single Value Acquisition Write BASE 0 2 4 6 In single value acquisition mode SW trigger the A D converter will convert one sample when you write to the register Write BASE 0 2 4 6 with any value User can check the A D FIFO status FIFOn_FE to make sure if the data is ready to be received Table C 3 Register for Single Value Acquisition Base 1 44 Register Forma Address HEX 15 11411312 11 10 9 8 7 6 5 4 3 72 T D Oh W JAI Channel 0 Single Value Acquisition IR AT Channel 0 Data 57 Appendix C Table C 5 Register for Single Katuk Acquisition 4h W JAI Channel 2 Single Value Acquisition IR Al Channel 2 Data TR JOV G1 GO JAD JAD AD9 AD8 AD7 AD6 AD5S AD4 AD3 AD2 AD1 JADO GF 11 10 6h W JAI Channel 3 Single Value Acquisition IR Al Chann
7. Acquisition Mode esnene 42 2 Pacer Acquisition Mode enrrnnrrnvrnrrnrrnrrrrerrerserrrernensenn 4 2 3 Post Trigger Acquisition Mode 1 0 eee Figure 4 1 Post Trigger Acquisition Mode dn 4 2 4 Delay Trigger Acquisition Mode 30 Figure 4 2 Delay Trigger Acquisition Mode 30 4 2 5 About Trigger Acquisition Mode ieevenvrnrvvrverrnvernenne 31 Figure 4 3 About Trigger Acquisition Mode 31 4 2 6 Pre Trigger Acquisition Mode neeenne 32 Figure 4 4 Pre Trigger Acquisition Mode 0 32 A D Sample Clock Sources 4 3 1 Internal A D Sample Clock 4 3 2 External A D Sample Clock 0 eenenenne 33 4 3 3 External A D Sample Clock I eeenenene 33 Figure 4 5 PCIE 1744 Sample Clock Sources 33 Trigger Sources aan 4 4 1 Software Trigger 4 4 2 External Digital TTL Trigger occ eres 4 4 3 Analog Threshold Trigger 0 0 cee eceeeeeecteeeeeeeeeees Analog Input Data Format Table 4 2 Analog Input Data Format Table 4 3 Corresponding Full Scale Values for Various Input Voltage Ranges 36 Calibration 0s0ssesoeoo00sossssoesossossssssssessess 38 Calibration Procedure 38 Figure 5 1 Click the Setup button to Launch the Device Setting 38 Figure 5 2 Click the Calibration Button to Launch the Calibration 39 Figure 5 3 The Start up Window of Offset Calibration 39 Figure 5 4 The Adjustment Process of Offset Calibratio
8. PF1 PFO 14 2 11110 6 IR FIFO 3 Programmable Flag Register PF PF13 FP1 PF PFT PFY PF8 PF PF PF5 PF4 PF3IPPF2 PF1 PFO 14 2 11110 7 16 TCh W DMA Counter Register ICNICN ICNT ICNTICNICNTICNSICNEICN CN CNE ICNA CN3JCN2 CNT CNO 15 114 3 2 11110 7 16 R ICNICN ICNT ICNTICNICNTICNICNEICN CN CNE CN4 CN3JCN2 CNT JONO 15 114 3 2 11110 7 16 TER W Rest DMA Counter R Table C PCIE 1744 register format Part 3 Base 1 44 Register Format Address HEX 75 114 113 12 717 10 9 8 7 6 5 4 B 2 T W 20h W IInterrupt Control Register INT DM FIF FIF JFIF FIF FIF FIF FIF E A T 03 03 02 02 01 101 100 100 C LALHLATHJA HF JAF HF F FF R INT INT IINTINTINTINTINTINT INT IN F F8 F7 F6 F5 F4 F3 F2 F1 FO 22h W Clear Interrupt R N A 55 Appendix C Table C 3 PCIE 1744 register format Part 3 W Analog Trigger voltage Register AT JAT JAT JAT JAT AT1 7 16 5 14 13 IR Analog Trigger Threshold voltage Register AT JAT JAT JAT AT AT1 7 16 5 14 13 26h W N A R N A 28h W Calibration Command Register CGTICGOX CM CM CM CD CD CD CD CD CD1 2 1 0 17 6 5 4 3 R CG CGO CBU CM CM CM CD CD CD CD CD CD1 1 SY 2 1 10 7 6 5 4 13 2Ah W R I2Ch W Board ID R BID BID
9. Write the RMA number visibly on the outside of the package and ship it prepaid to your dealer iii CE This product has passed the CE test for environmental specifications when shielded cables are used for external wiring We recommend the use of shielded cables This kind of cable is available from Advantech Please contact your local supplier for ordering information Technical Support and Assistance Step 1 Visit the Advantech web site at www advantech com support where you can find the latest information about the product Step 2 Contact your distributor sales representative or Advantech s cus tomer service center for technical support if you need additional assistance Please have the following information ready before you call Product name and serial number Description of your peripheral attachments Description of your software operating system version appli cation software etc A complete description of the problem The exact wording of any error messages Packing List Before setting up the system check that the items listed below are included and in good condition If any item does not accord with the table please contact your dealer immediately M PCIE 1744 card M Companion CD ROM DLL driver included M User Manual Safety Precaution Static Electricity Follow these simple precautions to protect yourself from harm and the products from damage 1 To avoid electrical shock always discon
10. also refer to the Appendix C 14 Analog Trigger Threshold Voltage for more details 35 Chapter4 4 5 Analog Input Data Format Table 4 2 Analog Input Data Format AID Code Mapping Voltage Hex Dec 000h Od FS 7FFh 2047d 1 LSB 800h 2048d 0 FFFh 2095d FS 1 LSB 1LSB FS 2048 Table 4 3 Corresponding Full Scale Values for Various Input Volt age Ranges Gain Range FS 5 5 2 2 5 2 5 1 1 10 0 5 0 5 PCIE 1744 User Manual 36 CHAPTER Calibration This chapter offers you a brief guide to the calibration procedure Sections include e Calibration Procedure Chapter 5 Calibration The PCIE 1744 has been calibrated at the factory for initial use You are not required to calibrate the PCIE 1744 in normal conditions However if calibration is required the procedure shown in the next pages will show how it is done To perform an effective calibration prepare a standard 4 1 2 digits reso lution stable and low noise DC voltage source It is important as the accuracy of the device will depend on the accuracy of the DC source 5 1 Calibration Procedure Step 1 Click the Setup button on the Advantech Device Manager win dow Fig 5 1 to launch the PCIE 1744 Device Setting window Advantech Device Manager Your ePlatform Partner ANNE bine Mm Device Manager Installed Devices SR My Computer Setup 001 lt PCIE 1744 BoardID 0 I10 400H gt
11. em Test Clos Add lt amp Advantech DEMO Board 3 Advantech PCI 1680 Advantech PCI 1710 L HG HGLATULAGU Riou 3 Advantech PCI 1711 3 Advantech PCI 1711L PCI 1731 Import 3 Advantech PCI 1712 il Advantech PCI 1 713 U Export lt Advantech PCI 1714 0L Ber 3 Advantech PCI 1715U es Supported Devices an About Figure 5 1 Click the Setup button to Launch the Device Setting PCIE 1744 User Manual 38 Step 2 Select the input range of the channel which you want to calibrate Step 3 Click the Calibration button to start the calibration process The Calibration Wizard window will pop up Note Each calibration process can calibrate only one channel and one input range at a time x Base Address Hex E000 Intemupt 11 r Auto Calibration Advanced Setting Maximal allowable PCI bus bandwidth SEE net ht 80 MBytes Sec CHI so Calibration Maximal allowable interrupt frequency Ly fm CH 50v 2 Calbvation Masimal buffer for DMA transfer f 16 MBytes CH3 50V 2 Caibraon Defauks or Core _ Abou Figure 5 2 Click the Calibration Button to Launch the Calibration Step 4 Follow the instruction of Calibration Wizard to input a correct DC voltage as a reference and click the Next button to proceed to the next step F i Calibration Wizard xj This wizard will help you calibrate your P CI 1714 device Condition Channel 0 i
12. for FIFO Programmable Flag HEX 15114 13 12 MT 10 9 B 76 5 4 3 2 1 0 14h W FIFO 0 Programmable Flag Register PF14PF13FP12 PF11 PF10 PFIIPPFEIPFTIPFEIPFSIPFAPFZ3IPF2IPFTIPFO IR FIFO 0 Programmable Flag Register PF14PF13FP12 PF11 PF10 PFIIPPFEIPFTIPFEIPFSIPFAPFZIPF2IPFTIPFO 16h W FIFO 1 Programmable Flag Register PF14PF13FP12 PF11 PF10 PFIIPPFEIPFTIPFEIPFSIPFAPFZ3IPF2IPFTIPFO IR FIFO 1 Programmable Flag Register PF14PF13FP12 PF11 PF10 PFIIPPFEIPFTIPFEIPFSIPFAPFZIPF2IPFTIPFO 18h W FIFO 2 Programmable Flag Register PFT IPFT3 FPT2 PF11 PF10 PFIPPFEIPFTIPFEIPFSIPFAPFZ3IPF2IPFTIPFO IR FO 2 Flag Register PF14 PFT FP12 PET PF10 PFOPFSPF7IPFOPFSPFAPF3IPF2IPFTJPFO TAR JW FIFO 3 eme Flag Register PF14PF13 FP12 PF11 PF10 PFOPFSIPF7IPFOPFSPFAPF3IPF2 PF1 PFO IR FIFO 3 Programmable Flag Register PF14PF13 FP12 PF11 PF10 PFOPFS8IPF7IPFOPFSPFAPF3IPF2 PF1 PFO PF14 PFO FIFO n Programmable Flag Register n 0 3 The FIFO on PCIE 1744 is very powerful It allows user to define the indicate flag in any depth There are two flags could be defined FIFO Almost Empty flag and FIFO Almost Full flag To define these flags must follow the procedure First write is the Almost Empty flag offset count from the empty Second write is the Almost Full flag offset count from the
13. of at least 600 kHz This consideration can avoid an error condi tion often know as aliasing in which high frequency input components appear erroneously as lower frequencies when sampling 4 3 2 External A D Sample Clock 0 The external sample clock 0 is a sine wave signal source which is con verted to a TTL signal inside the PCIE 1744 This signal is AC coupled The input impedance of the external clock 0 is 50 ohms and the input level is 5 volts peak to peak Please note that the frequency of the external clock is the system clock The maximum A D clock frequency is half of the system clock 4 3 3 External A D Sample Clock 1 The external sample clock 1 is a digital clock The input impedance is 50 ohms and the input level should be 2V 5V into the 50 ohm load This signal is DC coupled AD Converter Internal EXTCIKO Trigger Source ETC Figure 4 5 PCIE 1744 Sample Clock Sources 33 Chapter 4 4 4 Trigger Sources The PCIE 1744 supports the following trigger sources for post delay about and pre trigger acquisition modes e Software trigger External digital TTL trigger Analog threshold trigger You can define the type of trigger source as rising edge or falling edge These following sections describe these trigger sources in more detail 4 4 1 Software Trigger A software trigger event occurs when you start the analog input operation the computer issues a write to the board to begin acquisitions Wh
14. provides information about how to connect input signals to the PCIE 1744 via the I O connectors Sections include e Overview e Switch and Jumper Settings e Signal Connections Chapter 3 Signal Connections 3 1 Overview Maintaining signal connections is one of the most important factors in ensuring that your application system is sending and receiving data cor rectly A good signal connection can avoid unnecessary and costly dam age to your PC and other hardware devices This chapter provides useful information about how to connect input signals to PCIE 1744 via the I O connectors 3 2 Switch and Jumper Settings The PCIE 1744 has one function switch and five jumper settings Figure 3 1 Card Connector Jumper and Switch Locations PCIE 1744 User Manual 22 3 2 1 BoardID Switch Setting SW1 BoardID settings are used to set a board s unique identifier when multiple identical cards are installed in the same system The PCIE 1744 has a built in DIP switch SW1 which is used to define each card s unique identifier You can determine the unique identifier in the register as shown in following table If there are multiple identical cards in the same chassis the BoardID switch helps differentiate the boards by identifying each card s device number with the switch setting The BoardID switch s unique identifier has been set to 0 at the factory If you need to adjust it to other numbers set SW1 by referring to DIP swit
15. 4113 112 1110 9 B 76 BS 4 PB 2 71 0 10h JW FIFO Control Register FRSIFCL FRSTO FCL T1 R1 RO IR FIFO Status Register FIFO FIF FIF FIF FIF FIF FIF FIFO FIFOO_ FIFO 1_AF O1_ O1_ 01_ O1_ O0_ O0_ 0 FFIHF 0 EF AE FF HF EF AF JAE 12h W FIFO Control Register FRSIFCL FRST2 FCL T3 R3 R2 IR FIFO Status Register FIFO FIF FIF JFIF FIF FIF JFIF FIFO FIFO2_ FIFO 3 AF 03 03 03 03 02 O2_ 2 FFIHF 2 EF AE FF HF EF AF JAE 14h W FIFO 0 Programmable Flag Register PF PF13 FP1 PF PF1 PF9 PF8 PF IPF PF5 PF4 PF3 PF2 PF1 PFO 14 2 11110 6 IR FIFO 0 Programmable Flag Register PF IPFT3IFP1 PF PF1 PF9 PF8 PF IPF PF5 PF4 PF3 PF2 PF1 PFO 14 2 11110 7 16 16h W FIFO 1 Programmable Flag Register PF PF13 FP1 PF PF1 PF9 PF8 PF IPF PF5 PF4 PF3 PF2 PF1 PFO 14 2 11110 7 16 IR FIFO 1 Programmable Flag Register IPF4 PF3 PF2 PF1 PFO PF IPF13IFPTIPF PF1 PF9 PF8 14 2 11110 DE oF PCIE 1744 User Manual 54 Zope 097 ee 744 register format Part 2 W Programmable Flag Register PF IPFT FP1 PF IPF1IPF9IPF8 PF IPF PF5 PF4 PF3IPPF2 PF1 PFO 14 13 2 11 10 6 IR FIFO 2 Programmable Flag Register PF PF1 FP1 IPF IPF1IPF9IPF8 PF IPF PF5 PF4 PF3 PF2 PF1 PFO 14 3 2 11 10 7 16 TAR W FIFO 3 Programmable Flag Register PF PF13 FP1 PF IPF1 PF9 PF8 PF IPF PF5 PF4 PF3IPPF2
16. 44 please refer to Appendix A Specifications 3 Chapter I 1 2 Applications The following are some of the possible applications of the PCIE 1744 Testing Instruments e Ultrasound Imaging Gamma Camera Imaging e CCD Camera Imaging e Video Digitizing 1 3 Installation Guide Before you install your PCIE 1744 please make sure you have the fol lowing necessary components e PCIE 1744 DA amp C card PCIE 1744 Startup Manual Driver software Advantech DLL drivers included in the companion CD ROM Wiring cables PCL 10901 1 PCL 1010B 1 optional Wiring board ADAM 3909 optional Computer Personal computer or workstation with a PCI Express bus slot running Windows 2000 XP or Vista Some optional components are also available for enhanced operation Application software ActiveDAQ Pro or other third party software packages After you get the necessary components and maybe some of the accesso ries for enhanced operation of your DA amp C card you can then begin the installation procedures Figure 1 1 on the next page provides a concise flow chart for a broad picture of the software and hardware installation procedure PCIE 1744 User Manual 4 Install Driver from CD ROM and turn off computer Install hardware and turn on computer Use driver utility to configure hardware Use test utility to test hardware Read examples amp driver manual Start to write your own application Figure 1 1 Installa
17. 76 51413 2 11 0 10h JW FIFO Control Register FRSTT FCLR1 FRSTO FCLRO 12h W FIFO Control Register FRST3 FCLR3 FRST2 FCLR2 FCLRn n 0 3 FIFO Clear register Write I to this bit to clear FIFO data FRSTn n 0 3 FIFO Reset register Write 1 to this bit to clear FIFO data and reset the AE and AF flag posi tion to 7FH PCIE 1744 User Manual 62 C 9 FIFO Status Read BASE 10 12 Table C 11 Register for FIFO Status Base P 1 44 Register Forma Address HEX 5114113 12 117110 9 8 7165 4 3 2 1 10h IR FIFO Status Register FIFO FIFO FIFO FIFOTIFIFO FIFO FIFO FIFOO FIFO 1_AF 1_AE M_FF HF 11 EF O_AF O_AE FF 10 HF 0 EF 12h R FIFO Status Register FIFO FIFO FIFO FIFO3 FIFO FIFO FIFO FIFO2 FIFO FIFO 3 AF3 AE 3 FFI HF 3 EF 2 AF 2 AE FF 2 HFI2 EF T FIFOn_EF n 0 3 FIFO Empty Flag 1 FIFO is empty 0 FIFO is not empty FIFOn_HF n 0 3 FIFO Half full Flag 1 FIFO is half full 0 FIFO is not half full FIFOn FF n 0 3 FIFO Full Flag 1 FIFO is full 0 FIFO is not full FIFOn_AE n 0 3 FIFO Almost Empty flag 1 FIFO is almost empty 0 FIFO is not almost empty FIFOn AF n 0 3 FIFO Almost Full flag 1 FIFO is almost full 0 FIFO is not almost full 63 Appendix C C 10 FIFO for Programmable Flag Write Read BASE 14 16 18 1A Table C 12 Register
18. Analog I nput Channels 4 single ended analog input channels Resolution 12 bit FIFO Size 32k Max Sampling Rate 30 MHz Input range and Gain 1 2 5 10 Gain List Range 5V 2 5V 1V 0 5V Drift Gain 1 2 5 10 Zero 200 100 40 20 HV C Gain 30 30 30 30 ppm C Small Signal Band Gain 1 2 5 10 width for PGA Pana 7MHz 7MHz 7MHz 7MHz Max Input voltage 15 V Input Surge Protection 30 Vp p Input Impedance 50 1M Hi Z jumper selectable T00pF Trigger Mode Software pacer post trigger pre trigger delay trigger about trigger Accuracy D T1LSB No Missing Codes 12 Bits Guaranteed C INLE 2LSB Offset error Adjustable to 1LSB Gain error Adjustable to 1LSB A SINAD S 166 dB Hi Z C N D ENOB 10 67 bits Hi Z THD 73 dB Hi Z External Clock 1 Logic level TTL Low 0 8 V max High 2 0V min Input imped 50 ohms ance Input coupled DC Frequency Up to TOMHz External Clock 0 Logic level 5 0V peak to peak sin wave Input imped i ance Input coupled JAC Frequency Up to TOMHz External Trigger 0 Logic level TTL Low 0 8 V max High 2 0V min Input imped Hi Z ance Input coupled IDC External Analog Range By analog input range Trigger Input Resolution 8 bit Frequency Up to TMHz 47 Appendix A PCIE 1744 User Manual 48 APPENDIX Bloc
19. Figure 2 2 Different Options for Driver Setup For further information on driver related issues an online version of the Device Drivers Manual is available by accessing Start Programs Advantech Automation Device Manager Device Driver s Manual PCIE 1744 User Manual 14 2 3 Hardware Installation After the DLL driver installation is completed you can now go on to install the PCIE 1744 in any PCI Express slot on your computer It is rec ommended that you refer to the computer s user manual or related docu mentation if you have any doubts Please follow the steps below to install the card in your system Note Note Make sure you have installed the driver before you installthe card Please refer to 2 2 Driver Installation Turn off your computer and unplug the power cord and cables TURN OFF your computer before installing or removing any com ponents on the computer Remove the cover of your computer Remove the slot cover on the back panel of your computer Touch the metal part on the surface of your computer to neutralize the static electricity that might be in your body Insert the card into a PCI Express Hold the card by its edges and carefully align it with the slot Insert the card firmly into place Use of excessive force must be avoided or the card might be damaged Fasten the bracket of the PCIE 1744 on the back panel rail of the computer with screws Connect appropriate accessories such as source sync s
20. Message function to return the error message Or you can refer to the Device Drivers Error Codes Appendix in the Device Drivers Manual for a detailed listing of the Error Code Error ID and the Error Message PCIE 1744 User Manual 8 1 6 Accessories Advantech offers a complete set of accessory products to support the PCIE 1744 These accessories include 1 6 1 Wiring Cables PCL 10901 1 is specially designed for PCIE 1744 to connect to the wir ing board ADAM 3909 for external synchronization signal sources such as external triggers and or clock signals PCL 1010B 1 is designed for connecting to a signal source The cable links the PCIE 1744 with the signal source via the BNC connectors There are four BNC ports available for simultaneous signal input 1 6 2 Wiring Boards ADAM 3909 is a DB9 Wiring Terminal for DIN rail Mounting This ter minal module can be readily connected to the Advantech PC LabCard products and allows easy yet reliable access to individual pin connections for the PCIE 1744 9 Chapter I PCIE 1744 User Manual 10 CHAPTER Installation This chapter gives a package item checklist proper instructions about unpacking and step by step procedures for both driver and card installation Sections include e Unpacking Driver Installation Hardware Installation Device Setup amp Configuration Device Testing Chapter 2 Installation 2 1 Unpacking After receiving your PCIE 1744 pack
21. TA 71 C 19 DMA Request Selector Write BASE 34 72 Table C 21 Register for DMA Request Selector 72 PCIE 1744 User Manual viii CHAPTER Introduction This chapter will provide information on the features ofthe PCIE 1744 card a quick installation guide and informa tion on software and accessories Sections include Features Applications Installation Guide Software Overview Device Drivers Programming Roadmap Accessories Chapter 1 Introduction Thank you for buying the Advantech PCIE 1744 The PCIE 1744 is a simultaneous 4 channel analog input card with high sampling rates It is an advanced performance data acquisition card based on 32 bit PCI express bus architecture The maximum sampling rate of PCIE 1744 is up to 30 MS s 1 1 Features The PCIE 1744 offers the following main features 32 bit PCI Express bus Mastering DMA data transfer Four A D converters for simultaneous sampling 12 bit A D converter with up to 30 MS s 4 single ended analog input channels Programmable gain for each input channel On board FIFO memory Multiple A D triggering modes Programmable pacer counter Auto calibration BoardID switch PCI Express interface Some of the features are described in details from the next page PCIE 1744 User Manual 2 1 1 1 32 bit PCI bus Mastering DMA Data Transfer The PCIE 1744 supports PCI bus mastering DMA for high speed data transfers By setting as
22. Table C 20 Register for AD Channel n DATA Base P 1 44 Register Forma Address HEX 5 14 13 M2 1 10 9 B 7 6 5 4 B 2 M 0 30h R JAD Channel n DATA RGFJOV GT GO JAD11 JAD10JAD9 AD8JAD7 AD6 AD5 AD4 AD3 AD2 ADT ADO 32h R JAD Channel n 1 DATA RGFIOV GT GO AD 11 AD 10 AD9 AD8 AD 7 AD6ADS AD4 AD3 ADZ AD 1 ADO AD Channel n DATA n 0 or 2 BASE 30 32 are for four channels DMA data transfer Data transfer will alternate from CHO CHI to CH2 CH3 automatically The format is the same as BASE 0 2 or BASE 4 6 CHO CH1 is first 32 bit CH2 CH3 is the second and CHO CHI and so on User only want to transfer CHO CH1 please use BASE 0 2 transfer CH2 CH3 please use BASE 4 6 About DMA data transfer please refer to PCI9056 datasheet DMA data transfer support 1 2 or 4 channels data acquisition For 1 channel data acquisition only channel 0 or 2 is acceptable For 2 channels data acquisition only channel 0 1 or 2 3 is acceptable The DMA data transfer to memory format are list as below 1 One channel CHO Memory Address D31 D16 D15 DO N CHO data 1 CHO data 0 N 1 CHO data 3 CHO data 2 N 2 CHO data 5 CHO data 4 N 3 CHO data 7 CHO data 6 71 Appendix C 2 Two channels CHO CH1 Memory Address D31 D16 D15 DO N CH1 data 0 CHO data 0 N 1 CH1 data 1 CHO dat
23. a 1 N 2 CH1 data 2 CHO data 2 N 3 CH1 data 3 CHO data 3 3 Four channels CHO CH1 CH2 CH3 Memory Address D31 D16 D15 DO N CH1 data 0 CHO data 0 N 1 CH3 data 0 CH2 data 0 N 2 CH1 data 1 CHO data 1 N 3 CH3 data 1 CH2 data 1 C 19 DMA Request Selector Write BASE 34 HEX 145 114 13 112 11 110 9 8 7 6 5 4 3 72 TT 0 4h W DMA Request selector DSO DMA Request selector This bit select the DMA request hardware signal DREQ user could use FIFO 0 flag or FIFO 2 flag to generate DREQ 0 FIFOOflag 1 FIFO2flag PCIE 1744 User Manual 72
24. age please inspect its contents first The package should contain the following items M PCIE 1744 M Companion CD ROM DLL driver included M User Manual The PCIE 1744 harbors certain electronic components vulnerable to elec trostatic discharge ESD ESD could easily damage the integrated cir cuits and certain components if preventive measures are not carefully paid attention to Before removing the card from the antistatic plastic bag you should take following precautions to ward off possible ESD damage Touch the metal part of your computer chassis with your hand to dis charge static electricity accumulated on your body Or use a grounding strap Touch the anti static bag to a metal part of your computer chassis before opening the bag e Hold the card only by the metal bracket when removing it from the bag After taking out the card you should first inspect the card for any possi ble signs of external damage loose or damaged components etc If the card is visibly damaged please notify our service department or the local sales representative immediately Avoid installing a damaged card into your system Also pay extra caution to the following aspects to ensure proper installation M Avoid physical contact with materials that could hold static electricity such as plastic vinyl and Styrofoam X Whenever you handle the card grasp it only by its edges DO NOT TOUCH the exposed metal pins of the connector or the elec
25. ault installation path Program Files Advantech ADSAPI Examples For information about using other function groups or other development tools please refer to the Device Driver Programming Guide and the Function Reference on the Device Drivers Manual 7 Chapter I 1 5 2 Programming with Device Drivers Function Library Advantech Device Drivers offers a rich function library to be utilized in various application programs This function library consists of numerous APIs that support many development tools such as Visual C Visual Basic Delphi and C Builder According to their specific functions or services the APIs can be catego rized into several function groups Device Function Analog Input Output Function Digital Input Output Function Port I O Function e Counter Function Temperature Measurement Function Temperature measurement Function Alarm Function e Communication port Function e High speed Function e Hardware Function For the usage and parameters of each function please refer to the Func tion Description chapter in the Device Drivers Manual 1 5 3 Troubleshooting Device Drivers Error Driver functions will return a status code when they are called to perform a certain task for the application When a function returns a code that is not zero it means the function has failed to perform its designated func tion To troubleshoot the Device Drivers error you can pass the error code to DRV_GetError
26. ch settings below ID3 1D2 ID1 IDO Board ID 1 1 1 1 0 1 1 1 0 1 1 1 0 1 2 1 1 0 0 3 1 0 1 1 4 1 0 1 0 5 1 0 0 1 6 1 0 0 0 7 0 1 1 1 8 0 1 1 0 9 0 1 0 1 10 0 1 0 0 11 0 0 1 1 12 0 0 1 0 13 0 0 0 1 14 0 0 0 0 15 Note On 1 Off 0 23 Chapter 3 3 2 2 Power on Configuration after Hot Reset JP1 Use JP1 to set the hot reset type of PCIE 1744 JP1 Power on configuration after hot reset Keep the hardware register setting after hot reset Load the hardware register default setting after hot reset Default setting 3 2 3 Input Terminator Select JP2 to JP5 Use JP2 to JPS to set input terminator values for each AI channel CHO to CH3 JP2 JP3 JP4 JP5 Input terminator select 50 ohm 1M ohm Default setting High impedance PCIE 1744 User Manual 24 3 3 Signal Connections 3 3 1 Pin Assignments The pin assignments for the PS 2 connector and the DB9 connector are shown below Table 3 1 PS 2 Pin Assignments Pin Description EXT TRIG 0 NC EXT CLK 0 GND EXT CLK 0 EXT CLK 1 oO oa oO NA N gt Table 3 2 DB9 Pin Assignments Pin Description EXT TRIG 0 NC EXT CLK 0 GND EXT CLK 0 EXT CLK 1 GND GND GND 12345 O0000 OOOO 6 7 8 9 CO CO Nj amp O1 A N gt
27. codes included on the companion CD ROM PCIE 1744 User Manual 6 1 5 Device Drivers Programming Roadmap This section will provide you a roadmap to demonstrate how to build an application from scratch using Advantech Device Drivers with your favorite development tools such as Visual C Visual Basic Delphi and C Builder The step by step instructions on how to build your own applications using each development tool will be given in the Device Drivers Manual Moreover a rich set of example source code is also given for your reference 1 5 1 Programming Tools Programmers can develop application programs with their favorite devel opment tools e Visual C Visual Basic e Delphi e C Builder For instructions on how to begin programming in each development tool Advantech offers a Tutorial Chapter in the Device Drivers Manual for your reference Please refer to the corresponding sections in this chapter of the Device Drivers Manual to begin your programming efforts You can also look at the example source code provided for each programming tool The Device Drivers Manual can be found on the companion CD ROM Or if you have already installed the Device Drivers on your system the Device Drivers Manual can be readily accessed through the Start but ton Start Programs Advantech Automation Device Manager Device Drivers Manual The example source codes can be found under the corresponding installa tion folder such as the def
28. e and Source Write Read BASE E 61 Table C 9 Register for Trigger Mode and Source 61 C 8 FIFO Control Write BASE 10 12 Table C 10 Register for FIFO Control C 9 FIFO Status Read BASE 10 12 Table C 11 Register for FIFO Status C 10 FIFO for Programmable Flag Write Read BASE 14 16 18 1A64 Table C 12 Register for FIFO Programmable Flag 64 C 11 DMA Counter Write Read BASE 1C Write BASE 1E 65 Table C 13 Register for DMA Counter eee 65 C 12 Interrupt Control Flag Write Read BASE 20 66 Table C 14 Register for Interrupt Control Flag 66 C 12 1 Interrupt Control Register C 12 2 Interrupt Flag sasra narsis irera C 13 Clear Interrupt Write BASE 22 nennen 67 Table C 15 Register for Clear Interrupt 67 C 14 Analog Trigger Threshold Voltage Write Read BASE 24 68 Table C 16 Register for Analog Trigger Threshold Volt age 68 vii Table of Contents C 15 Calibration Command Write Read BASE 28 69 Table C 17 Register for Calibration Command 69 C 16 BoardID Read BASE 2C eesennseesensensennenensenn 70 Table C 18 Register for BoardID Switch 70 C 17 Reset DMA Start Channel to CHO Write BASE 30 70 Table C 19 Register for Reset DMA Start Channel to CHO 70 C 18 AD Channel n DATA Read BASE 30 32 71 Table C 20 Register for AD Channel n DA
29. e is no any interrupt in coming 67 AppendixC C 14 Analog Trigger Threshold Voltage Write Read BASE 24 Table C 16 Register for Analog Trigger Threshold Voltage Base P 1 44 Register Forma HEX 15 14113 12111 10 8 7 6 5 14 3 2 1 0 24h JW Analog Trigger Threshold voltage Register AT7 ATG ATS AT4 JATS AT2 JATT JATO IR Analog Trigger Threshold voltage Register AT7 ATG ATS AT4 JATS AT2 JATT JATO AT7 ATO Analog Trigger Threshold voltage Register These registers set the analog trigger threshold voltage level AT7 ATO 0 5V 1V 2 5V 5V FFh 0 496 0 992 2 48 4 96 FEh 0 492 0 984 2 46 4 92 81h 0 004 0 008 0 02 0 04 80h 0 0 0 0 79h 0 004 0 008 0 02 0 04 01h 0 496 0 992 2 48 4 96 00h 0 5 1 2 5 5 PCIE 1744 User Manual 68 C 15 Calibration Command Write Read BASE 28 Table C 17 Register for Calibration Command Base 1 44 Register Forma Address HEX 51413 12 111 110 9 B 7 6 5 4 B T D 28h W Calibration Command Register CGT CGOX CM2 CM1 CMO CD CD CD CD CD3ICD2ICDTICDO 7 16 15 14 R CG1 CGOICBUICM2ICMTICMOICD CD CD CD CD3 CD2 CD1 CDO SY 7 16 15 14 CD7 CDOCalibration data The value is from 00h to FFh CM2 CMOCalibration Command Register
30. e trigger event occurred Please specify the following parameters after Pre trigger Acquisition Mode has been set The sample clock source and sample rate The trigger source e Assume the total acquired sample number is N then set the total sample number to be N 2 Figure 4 4 Pre Trigger Acquisition Mode 4 3 AID Sample Clock Sources The PCIE 1744 can adopt both internal and external clock sources for pacer post trigger delay trigger about trigger acquisition modes Internal A D sample clock with 8 bit divider External A D sample clock that is connected to either the EXT CLKO the differential clock source or the EXT CLK1 the single ended clock source on the ADAM 3909 screw terminal board The internal and both external A D sample clocks are described in more details in the next pages PCIE 1744 User Manual 32 4 3 1 Internal A D Sample Clock The internal A D sample clock uses a 60 MHz time base Conversions start on the rising edge of the counter output You can use software to specify the clock source as internal and the sampling frequency to pace the operation The minimum frequency is 234375 S s the maximum fre quency is 30 MS s According to the sampling theory Nyquist Theorem you must specify a frequency that is at least twice as high as the input s highest frequency component to achieve valid sampling For example to accurately sample a 300 kHz signal you have to specify sampling fre quency
31. el 3 Data TR OVIG1 GO JAD JAD AD9 AD8 AD7 AD6 ADSJ AD4 AD3 AD2 AD1 JADO GF 11 110 AD11 ADO12 bits Data of A D Conversion ADO the least significant bit LSB of A D data AD11 the most significant bit MSB of A D data G1 GO Range code These 2 bits indicate the input range of the data G1 GO Input range 0 0 5 to 5V 0 1 2 5 to 2 5V 1 0 1 to 1V 1 1 0 5 to 0 5V OV Over range flag This bit indicates whether the input voltage is over range or not Read 1 means over range TRGF Trigger Flag For about trigger use only The trigger flag indicates whether a trigger event has happened during A D conversion process PCIE 1744 User Manual 58 C 4 Al Range Control Write Read BASE 8 Table C 6 Register Jor Analog Input Range Control Base 44 Register Forma Address HEX f5 114 113 12 11 10 987 6 5 4 B 2 1 0 8h JW Al Range Control Register G1 GO G1 GO G1 GO G1 G60 G1 GO G1 GO G1 GO G11G0 Analog Input Range Selector These registers are used to select the analog input range for each channel CHn G1 CHn GO Input range 0 0 5 to 5 V 0 1 2 5 to 2 5 V 1 0 1 to 1 V 1 1 0 5 to 0 5 V n 0 3 C 5 A D Converter Enable Write Read BASE A Table C 7 Rosier for A D Co
32. en you write the value to analog input trigger flag TRGF on Write BASE Eh to produce either a rising edge or falling edge trigger depend ing upon the trigger source type you choose This edge will then act as an A D trigger event For detailed information please refer to Appendix C 7 Trigger Mode and Source 4 4 2 External Digital TTL Trigger For analog input operations an external digital trigger event occurs when the PCIE 1744 detects either a rising or falling edge on the External A D TTL trigger input signal from screw terminal EXT_TRIG on the ADAM 3909 screw terminal board The trigger signal is TTL compatible PCIE 1744 User Manual 34 4 4 3 Analog Threshold Trigger For analog input operations an analog trigger event occurs when the PCIE 1744 detects a transition from above a threshold level to below a threshold level falling edge or a transition from below a threshold level to above a threshold level rising edge You should connect the analog signals from the external device to one of the four BNC source connec tors Which one of the four sources is selected as the trigger source can be defined or identified by writing to or reading from the flags from TSO to TS2 of Write Read BASE Eh On the PCIE 1744 the analog trigger threshold voltage level is set using a dedicated 8 bit DAC you can write or read the flags from ATO to AT7 on Write Read BASE 24h to define or identify the analog trigger threshold voltage level Please
33. full Read procedure is the same as write Once set the offset the value will keep until FIFO reset PCIE 1744 User Manual 64 C 11 DMA Counter Write Read BASE 1C Write BASE 1E Table C 13 Register for DMA Counter Base P 1 44 Register Forma Address HEX 15 114 113 12 11 10 9 8 7 6 5 4 B 2 W TCh W Counter Register ICN CN ICN CN CN CN ICNIICNBSICNTICNSICNSICNAICNSICNZICNTICNO 15 114 113 112 111 10 ICN ICN ICN ICN ICN CN ICNIICNEICNTCNEICNSICNAICNSICN2 CNTICNO 15 114 113 12 11 110 TEA W Rest DMA Counter CN15 CNO DMA counter register DMA counter is al6 bit counter designed for ABOUT and DELAY trig ger mode only Set the counter value for about trigger data counts after the trigger event Also the value for delay trigger data counts after the trigger event Rest DMA Counter Before start the DMA counter write the BASE 1Eh to reset the DMA counter 65 Appendix C C 12 Interrupt Control Flag Write Read BASE 20 Table C 14 Register for Interrupt Control Flag Base P 1 44 Register Forma Address HEX 115 114 13 112111 109 8 7 6 5 4 PB 2 1 0 20h W Interrupt Control Register INT DM FIF FIF JFIF FIF FIFOTFIFO FIFO JFIFO E A 103 103 102 02 AF 1 HF 0 AF 0 HF TG AF HF AF HF IR Interrupt Flag INT INTJINT INT INT INT INTF3INTFZIINTFTIINTFO F F8 F7 F6 F5 F4
34. gister for Trigger Mode and Source Base PCIE 1 44 Register Forma Address HEX 715 114 13 112 11 109 8 7 6 5 4 8 2 1 0 Eh W Trigger Mode and Source Register TR DM TSEITS2 ITS1 TSO TM2 TM TMO GF A T CF R TR DM TSEITS2 ITS1 TSO TM2 TM TMO GF AT CF TM2 TMO Trigger Mode selector There are 5 trigger modes for PCIE 1744 Please refer to the operation theorem for more information ITM2 TMI TMO Meaning 0 0 0 Single value acquisition mode SW trigger 0 0 1 Pacer acquisition mode 0 1 0 Post trigger acquisition mode 0 1 1 Delay trigger acquisition mode 1 0 0 About trigger acquisition mode 1 0 1 N A 11 1 0 N A 11 1 1 N A TS2 TSO Trigger Source selector TS2 TST TTSO Meaning 0 0 0 Analog input CHO 0 0 1 Analog input CH1 0 1 0 Analog input CH2 0 1 1 Analog input CH3 1 0 0 Digital trigger input 11 0 1 N A 11 1 0 N A 1 1 1 N A TSE Trigger Edge selector Rising edge trigger Falling edge trigger 61 AppendixC DMA TCF DMA counter terminal count flag DMA counter is not terminal count DMA counter is terminal count TRGF Trigger flag Trigger not occurred Trigger occurred C 8 FIFO Control Write BASE 10 12 Table C 7 0 Rester for FIFO Control Base 44 Register Format Address HEX 75 14 113 142 11 10 9 8
35. ide a block of memory in the PC the card performs bus mastering data transfers without CPU intervention freeing the CPU to perform other more urgent tasks such as data analysis and graphic manipulation The function allows users to run all I O functions simulta neously at full speed without losing data 1 1 2 Four A D Converters for Simultaneous Sampling The PCIE 1744 is capable of simultaneous sampling with their 4 identical circuits and a dedicated A D converter for each analog input channel When the time relationship between inputs is important this feature lets you sample simultaneously 1 1 3 Supports S W Internal amp External Pacer Triggering The PCIE 1744 supports three kinds of trigger modes for A D conver sion software triggering internal pacer triggering and external pacer trig gering The software trigger can acquire a sample whenever needed while the internal pacer saves CPU resources by triggering the sampling at a pre programmed frequency An external pacer can also be used for triggering by externally connected equipment 1 1 4 Onboard FIFO Memory There is 32k of FIFO sample memory on PCIE 1744 This is an impor tant feature for faster data transfers and more predictable performance under Windows systems 1 1 5 Auto Calibration The PCIE 1744 features software auto calibration There is no variable resister trimming required This is convenient for user calibration Note For detailed specifications ofthe PCIE 17
36. ignal cables wiring terminals etc if necessary to the card Replace the cover of your computer chassis Re connect the cables you removed in Step I Plug in the power cord and turn on the computer In case you installed the card without installing the DLL driver first Windows 2000 XP and Vista will recognize your card as an unknown device after rebooting and will prompt you to provide the necessary driver You should ignore the prompting messages just click the Cancel button and set up the driver according to the steps described in 2 2 Driver Installation 15 Chapter 2 After the PCIE 1744 is installed you can verify whether it is properly installed on your system in Device Manager 1 Access Device Manager through Start Control Panel System Device Manager 2 The device name of card should be listed on the Device Manager tab on the System Property Page Device Manager ME E3 Fie Action View Help uo P J COSP E1LEBE94B94 8 ADVANTECH B Advantech PCIE17445 Device M Advantech Motion Control cards Computer Disk drives 2 Display adapters 2 DVD CD ROM drives Floppy disk controllers Floppy disk drives IDE ATAJATAPI controllers ae Keyboards Mice and other pointing devices Monitors M Network adapters NPM USB Devices PUSB3601 Ports COM amp LPT E Processors amp SCSI and RAID controllers Sound video and game controllers
37. installed on your system if any in the Installed Devices list box Advantech Device Manager Your ePlatform Partner INO bine tm Device Manager Installed Devices My Computer EZ 001 lt PCIE 1744 BoardID 0 110 400H gt Supported Devices lt amp Advantech DEMO Board 3 Advantech PCI 1680 lt amp Advantech PCI 1710 L HG HGL U UL HGU 3 Advantech PCI 1711 3 Advantech PCI 1711L PCI 1731 3 Advantech PCI 1712 Advantech PCI 1713 0 Advantech PCI 1714 0L 2 Advantech PCI 17150 Figure 2 4 Device Manager with Installed Devices As we have noted the device name 001 lt PCIE 1744 BoardID 0 I O e400H gt begins with a device number 001 which is specifically assigned to each card The device number is passed to the driver to specify which device you wish to control If you want to test the card device further go to the next section on the Device Testing You can find rich examples on the CD ROM to speed up your programming 17 Chapter 2 2 5 Device Testing Following the setup and configuration procedure to the last step described in the previous section you can now proceed to test the device by click ing the Test button in Device Manager s dialog box A Device Test dialog box will appear See Figure 2 5 IE Advantech Device Test PCIE 1744 BoardID 0 1 0 400H Analoginput Analog output Digital input Digital output Channel No Input range Analog input reading sw en Channe
38. k Diagram Appendix B Block Diagram Input Attenuator Attenuator Input Attenuator Input Attenuator Ranger Selector Gain and Offset Auto Calibration Local Bus Timing and Triggerin External Trigger ariel a and Clock PCI BUS 5V 32bit 33MHz PCIE 1744 User Manual 50 APPENDIX Register Structure amp Format Appendix C Register Structure amp Format C 1 Overview The PCIE 1744 is delivered with an easy to use 32 bit DLL driver for user programming under the Windows 2000 XP and Vista operating sys tems We advise users to program the PCIE 1744 using the 32 bit DLL driver provided by Advantech to avoid the complexity of low level pro gramming by register The most important consideration in programming the PCIE 1744 at reg ister level is to understand the function of the cards registers The infor mation in the following sections is provided only for users who would like to do their own low level programming C 2 Register Format The register format is the basis to control the PCIE 1744 There are some rules for programmer s reference All registers are 32 bit format Please use the DWORD command in your own software Some registers are used only for write or read Some registers can support write and read back they usually use the same name Some registers could write any value to complete a command In general read only register is called status register write only register is cal
39. l mode psw xl HE 4 single ended channels sw vi 0 0109887 Sampling period 1000 a so z EEE Change device Figure 2 5 The Device Test Dialog Box of PCIE 1744 In the Device Test dialog box you are free to test various functions of PCIE 1744 on the analog input tab functions on the other tabs are not supported for this model 2 5 1 Testing the Analog Input Function Make sure the Analog Input tab is selected otherwise click on the Ana log Input tab to bring it up to the front of the screen Select the input range for each channel in the Input range drop down boxes Configure the Sampling period on the scroll bar to adjust the sampling rate the Ana log input reading windows will show the readings of all four channels accordingly Scroll the Sampling period scroll bar freely to test any sam pling rate you want When the device is fully tested click the Exit button to end the testing procedure PCIE 1744 User Manual 18 AA Advantech Device Test PCIE 1744 BoardID 0 1 0 400H Analoginput Analog output Digital input Digital output Channel No Input range Analog input reading 5 0v gt jooma r Channel mode 5 0v 00329667 4 single ended channels 5 0 v 0 0103887 Sampling period 1000 me Fev mE Change device Exit Figure 2 6 Analog Input tab on the Device Test dialog box 19 Chapter 2 PCIE 1744 User Manual 20 CHAPTER Signal Connections This chapter
40. led control register Some registers are very similar usually denote as a group For exam ple A4 A3 A2 Al AO usually denote as A4 AO In this document 1Fh means hexadecimal number 1F PCIE 1744 User Manual 52 Table C 1 shows the function of each register of the PCIE 1744 or driver and their address relative to the card s base address 115 14 13 12 9 18 AT Channel 0 Sin gle Value Acquisition a GO AD 11 AD 10 AD9 AD8 AD3 gle Value Acquisition a GO AD 11 AD 10 AD9 AD8 AD3 gle Value Acquisition a GO AD 11 AD 10 AD9 AD8 AD3 6h W gle Value Acquisition a GO AD 11 AD3 AT Range Control Registe Gi GO Ke GO CH1 Gt CH1 CHO CHO GO G1 GO _G1 GO _G1 GO CH1 _G1 CH1 CHO CHO 6061 60 Ah W AID Converter Enable Registe CH2 CH1 CHO 53 Appendix C Table C 1 PCIE 1744 register format Part 1 Eh W Trigger Mode and Source Register ITRGFIDMA TSE TSZ TST TSO TM2ITMTITMO _TCF IR ITRGFIDMA TSE TSZ TST TSO TM2ITMTITMO _TCF Base P 1 44 Register Format Address HEX 1511
41. n 40 Figure 5 5 Offset Calibration Succeeded 40 PCIE 1744 User Manual vi Appendix A A l A2 Appendix B Appendix C Figure 5 6 Offset Calibration Failed 20 0 ceeseseeee 41 Figure 5 7 The Start up Window of Offset Calibration 41 Figure 5 8 The Adjustment Process of Gain Calibration 42 Figure 5 9 Gain Calibration Succeeded 42 Figure 5 10 Gain Calibration Failed ssseseseeeeeeseeeeee 43 Figure 5 11 Calibration Procedure Completed 43 Specifications scccscccscssccccsscsscssescsseseees 40 Generale na E a eee ee tiated 46 Analog Mputa ms isin ae 47 Block Diagram ccicccccssssessenssceesassvensecnsseessssee DO Register Structure amp Format 52 CL Overviewasnassssass ae C 2 Register Format Table C 1 PCIE 1744 register format Part 1 Table C 2 PCIE 1744 register format Part 2 Table C 3 PCIE 1744 register format Part 3 Table C 4 PCIE 1744 register format Part 4 C 3 A D Single Value Acquisition 5 Table C 5 Register for Single Value Acquisition 57 C 4 AI Range Control Write Read BASE 8 enn 59 Table C 6 Register for Analog Input Range Control 59 C 5 A D Converter Enable Write Read BASEH A 59 Table C 7 Register for A D Converter Enable 59 C 6 Clock Source and Divider Write Read BASE C 60 Table C 8 Register for Clock Source and Divider 60 C 7 Trigger Mod
42. n range Fr 50V Offset Calibration Please connect a reference voltage of 0 0 V in channel 0 Note The calibration will fail if the voltage is invalid Figure 5 3 The Start up Window of Offset Calibration 39 Chapter 5 Step 5 Click the Start button to start the Offset Calibration Note that the Status will indicate Unknown as default at the beginning Adjust Offset Value This action will take a few time to adjust Adjust 07255 Hex Ave Voltage Status Unknow 2050 1101 0 0061 Unknow Start Note If Fail please check input voltage Figure 5 4 The Adjustment Process of Offset Calibration Step 6 If the reference DC voltage source and the wiring are both correct the calibration will proceed automatically after the Start button is clicked When the offset calibration is completed the Status will indicate Succeeded then click the Next button to proceed to the next step Calibration Wizard xl m Adjust Offset Value This action will take a few time to adjust Adjust 0 255 Hex Ave Voltage Status 96 2047 9399 0 001 2 Success Note If Fail please check input voltage Next gt Cancel Figure 5 5 Offset Calibration Succeeded PCIE 1744 User Manual 40 Step 6a Once the Status indicates Failed please check if both the wiring and the input voltage are correct When finished checking click the Start button again to restart the p
43. nect the power from your PC chassis before you work on it Don t touch any components on the CPU card or other cards while the PC is on 2 Disconnect power before making any configuration changes The sudden rush of power as you connect a jumper or install a card may damage sensitive electronic components PCIE 1744 User Manual iv Chapter Chapter Chapter 1 mo Wh 1 5 1 6 DE br N 2 3 2 4 2 5 New Contents Introduction 2 Features 1 1 1 32 bit PCI bus Mastering DMA Data Transfer 3 1 1 2 Four A D Converters for Simultaneous Sampling 3 1 1 3 Supports S W Internal amp External Pacer Triggering 3 1 1 4 Onboard FIFO Memory rrernrnenrenrenververnerrernernernersernenne 3 1 1 5 Auto Calibration enesenusensanesetesensn 3 Applications essen 4 Installation Guide eus enssersensann 4 Figure 1 1 Installation Flow Chart neee 5 Software Oveiview neue 6 1 4 1 Programming Choices for DA amp C Cards 00 eee 6 1 4 2 Device Drivers u est nennen 6 1 4 3 Register Level Programming n een 6 Device Drivers Programming Roadmap 7 1 5 1 Programming Tools 2u ee riter ete 7 1 5 2 Programming with Device Drivers Function Library 8 1 5 3 Troubleshooting Device Drivers Error 8 Accessories 89 161 Winne Cables unseres ange 9 1 6 2 Wiring Boards csnsnsnesnennnnsensensen
44. nennennennennn 9 Installation uses 12 Unpackine tu nsuenstessit net nie 12 Driver Installation 02 0045 8 as ra net 13 Figure 2 1 The Setup Screen of Advantech Automation Software 13 Figure 2 2 Different Options for Driver Setup 14 Hardware Installation uuesnsnssnssnensnnnesnnnesnenn 15 Figure 2 3 The Device Name Listed in the Device Man ager 16 Device Setup amp Configuration neeeeneenneennn 17 Figure 2 4 Device Manager with Installed Devices 17 Device Testing uuhsandosinesngseniaing dessert 18 Figure 2 5 The Device Test Dialog Box of PCIE 1744 18 2 5 1 Testing the Analog Input Function enee 18 Figure 2 6 Analog Input tab on the Device Test dialog box 19 Signal Connections ss 22 OVEIVIEW ren aueh 22 Switch and Jumper Settings 20 0 ccescsseeseeseeeeeeteeeeees 22 Figure 3 1 Card Connector Jumper and Switch Locations v Table of Contents 3 3 Chapter 4 4 1 4 2 4 3 4 4 4 5 Chapter 22 3 2 1 BoardID Switch Setting SW1 neene 3 2 2 Power on Configuration after Hot Reset JP1 3 2 3 Input Terminator Select JP2 to JP5 osses Signal Connections ueeesnenenesnnnsnnsennenneennnnennee nennen 3 3 1 Pin Assignment paora o aiaa nea Table 3 1 PS 2 Pin Assignments Table 3 2 DB9 Pin Assignments Op rations 28 Analog Input Ranges and Gains Table 4 1 Gains and Analog Input Range AE Input Acquisition Modes 4 2 1 Single Value
45. nverter Enable Base 44 Register Forma Address HEX 5 114113 12 911 110 9 8 7 6 5 4 3 2 1 0 CH3 CH2 CH1 CHO A D converter Enable bit These bits control the A D converter s operation Write 0 will disable the A D while 1 will enable They could be read back for checking purposes 59 Appendix C C 6 Clock Source and Divider Write Read BASE C Address Table C 8 Register for Clock Source and Divider Base P 1 44 Register Forma HEX 15 114 113 12 11 10 9 ICh W Clock Source and Divider Regis CKSICKS DIV DIV DIV DIV DIV DIV DIV DIV 1 0 7 6 5 4 3 2 1 0 IR CKSICKSIDIV DIV DIV DIV DIV DIV DIV DIV 1 0 7 6 5 4 3 2 1 0 DIV7 DIVO Clock Divider When select the internal clock source 60MHz the clock will pre divide by the clock divider The divider is 8 bit wide so it could divide from 2 to 256 DIV7 DIVO Divide value 00h N A Oth divide by 2 02h divide by 3 FEh divide by 255 FFh divide by 256 CKS1 CKSO Clock Source selector These 2 bits select the clock source feed to the A D converters CKS1 CKSO Clock source 0 0 Internal clock 60MHz 0 1 External clock 0 1 0 External clock 1 1 1 Off PCIE 1744 User Manual 60 C 7 Trigger Mode and Source Write Read BASE E Table C 9 Re
46. ode is the simplest way to acquire data Once the software issues a trigger command the A D converter will con vert one data and return it immediately You can check the A D FIFO status Read BASE 10 12 to make sure if the data is ready to be received For detailed information please refer to Appendix C 8 FIFO Control Appendix C 9 FIFO Status and Appendix C 10 FIFO for Pro grammable Flag PCIE 1744 User Manual 28 4 2 2 Pacer Acquisition Mode Use pacer acquisition mode to acquire data if you want to accurately con trol the time interval between conversions of individual channels in a scan A D conversion clock comes from A D counter or external clock source on connector A D conversion starts when the first clock signal comes in and will not stop if the clock is still continuously sending into it Conversion data is put into the A D FIFO For high speed data acquisi tion you have to use the DMA data transfer for analog input to prevent data loss 4 2 3 Post Trigger Acquisition Mode Post trigger allows you to acquire data based on a trigger event Posttrig ger acquisition starts when the PCIE 1744 detects the trigger event and stop when the preset number of post trigger samples has been acquired or when you stop the operation This trigger mode must work with the DMA data transfer mode enabled Use post trigger acquisition mode when you want to acquire data when a post trigger event occurs Please specify the following parameters af
47. r and a post trigger acquisition When using software please specify the following parameters after About Trigger Acquisition Mode has been set The sample clock source and sample rate The trigger source The total acquired sample number N The specific sample number M after the trigger event The range of pre set sample number is from 2 to 65536 samples In about trigger mode users must first designate the size of the allocated memory and the amount of samples to be snatched after the trigger event happens The about trigger acquisition starts when the first clock signal comes in Once a trigger event happens the on going data acquisition will continue until the designated amount of samples have been reached When the PCIE 1744 detects the selected about trigger event the card keeps acquiring the preset number of samples and keeps the total number of samples on the FIFO Trigger Event Acquired number of samples M after trigger event happened Total Acquired sample number N Figure 4 3 About Trigger Acquisition Mode 31 Chapter4 4 2 6 Pre Trigger Acquisition Mode Pre Trigger mode is a particular application of about trigger mode Use pre trigger acquisition mode when you want to acquire data before a spe cific trigger event occurs Pre trigger acquisition starts when you start the operation and stops when the trigger event happens Then the specific number of samples will be reversed in the FIFO before the pr
48. rocedure or click the Cancel button to stop the calibration caibraton wzera x m Adjust Gain Value This action will take a few time to adjust en Hex Ave Voltage nen Note If Fail please check input voltage Next Cancel Figure 5 6 Offset Calibration Failed Step 7 If the offset calibration is completed it will proceed to the Gain Calibration The steps of gain calibration are quite similar to those ofthe offset calibration Follow the instructions of the Calibration Wizard to input a correct DC voltage and click the Next button to proceed Calibration Wizard gt Condition Channel 0 in range Fr 5 0 Gain Calibration A Please connect a reference voltage of 4 9987 V in channel 0 Note The calibration will fail if the voltage is invalid Next gt Cancel Figure 5 7 The Start up Window of Offset Calibration 41 Chapter 5 Step 8 Click the Start button to start gain calibration Note that the Sta tus will indicate Unknown as default at the beginning Calibration Wizard Figure 5 8 The Adjustment Process of Gain Calibration Step 9 When the gain calibration is completed click the Next button to proceed Calibration Wizard Figure 5 9 Gain Calibration Succeeded PCIE 1744 User Manual 42 Step 9a Once the Status indicates Failed please check if both the wiring and the input voltage are correct When finished checking click the Start button again to re
49. start the procedure or click the Cancel button to stop the calibration f Calibration Wizard Fr x m Adjust Gain Value This action will take a few time to adjust Adjust 07255 Hex Ave Voltage Status 255 2048 1201 0 0072 Fail Start Note If Fail please check input voltage Next gt Cancel Figure 5 10 Gain Calibration Failed Step 10 When the current channel is calibrated click the Finish button to end the procedure You can proceed to Step 3 to select another channel for calibration and repeat from Step 4 to Step 9 until the rest of the chan nels are all calibrated one after one m Adjust Gain Value Channel 0 has been successfully calibrated Adjust 07255 Hex Ave Voltage Status Unknow 4094 4299 4 9976 Success Bancel Figure 5 11 Calibration Procedure Completed 43 Chapter 5 PCIE 1744 User Manual 44 APPENDIX Specifications Appendix A Specifications A 1 General I O Connector Type 4 BNC connector for Al 1 PS2 connector for ext clock and trigger Dimensions 175 mm x 100 mm 6 9 x 3 9 Power Typical 5 V 850 mA 12 V 600 mA mn Max 5 V 1 A 12 V 700mA Temperature Operating 9 70 C 32 158 F Storage 20 85 C 4 185 F Relative Humidity 5 95 RH non condensing refer to IEC 68 2 3 Certification CE certified PCIE 1744 User Manual 46 A 2
50. ter Post Trigger Acquisition Mode has been set The A D sample clock source and sampling rate The trigger source The acquired sample number N Trigger Event Acquired number of samples N Ist 2nd 3rd N Ah N Ih Nih f14 141 Figure 4 1 Post Trigger Acquisition Mode 29 Chapter 4 4 2 4 Delay Trigger Acquisition Mode In delay trigger mode data acquisition will be activated after a preset delay number of sample has been taken after the trigger event The delay number of sample ranges from 2 to 65535 as defined in DMA counter Delay trigger acquisition starts when the PCIE 1744 detects the trigger event and stop when the specified number of A D samples has been acquired or when you stop the operation This triggering mode must work with the DMA data transfer mode enabled Please specify the following parameters after the Delay Trigger Acquisition Mode has been set The sample clock source and sampling rate The trigger source The acquired sample number N The sample number M delays after the delay trigger event happened Trigger Event Delay time M Acquired number of samples N from 2 to 65535 samples M 2 Figure 4 2 Delay Trigger Acquisition Mode PCIE 1744 User Manual 30 4 2 5 About Trigger Acquisition Mode Use about trigger acquisition mode when you want to acquire data both before and after a specific trigger event occurs This operation is equiva lent to doing both a pre trigge
51. tion Flow Chart 2 Chapter I 1 4 Software Overview Advantech offers a rich set of DLL drivers third party driver supports and application software to help fully utilize the functions of your PCIE 1744 card Device Drivers on the companion CD ROM e LabVIEW driver e WaveScan 1 4 1 Programming Choices for DA amp C Cards You may use Advantech application software such as Advantech Device Drivers On the other hand advanced users may choose register level programming although it is not recommended due to its laborious and time consuming nature 1 4 2 Device Drivers The Advantech Device Drivers software is included on the companion CD ROM It also comes with all Advantech DA amp C cards Advantech s device drivers feature a complete I O function library to help boost your application performance The Advantech Device Drivers for Windows 98 2000 and XP works seamlessly with development tools such as Visual C Visual Basic Borland C Builder and Borland Delphi 1 4 3 Register Level Programming Register level programming is reserved for experienced programmers who find it necessary to write code directly at the level of device regis ters Since register level programming requires much effort and time we recommend that you use the Advantech Device Drivers instead How ever if register level programming is necessary you should refer to the relevant information in Appendix C Register Structure and Format or to the example
52. tronic compo nents Note Keep the anti static bag for future use You may need the original bag to store the card if you have to remove the card from the PC or transport it elsewhere PCIE 1744 User Manual 12 2 2 Driver Installation We recommend you to install the driver before you install any of the the PCIE 1744 into your system since this will guarantee a smooth installa tion process The Advantech Device Drivers setup program for the PCIE 1744 is included on the companion CD ROM that is shipped with your DA amp C card package Please follow the steps below to install the driver software Step 1 Insert the companion CD ROM into your CD ROM drive Step 2 The Setup program will be launched automatically if you have the AUTORUN function enabled on your system When the Setup program is launched you ll see the following setup screen AD ANTECH DA amp C Device Driver CDV y Device Manager Individual Driver Example amp Utility x Advance Options J Figure 2 1 The Setup Screen of Advantech Automation Software Note If the AUTORUN function is not enabled on your computer use Windows Explorer or the Windows Run command to execute Autorun exe on the com panion CD ROM 13 Chapter 2 Step 3 Select the Individual Drivers option Step 4 Select the specific device then just follow the installation instruc tions step by step to complete your device driver setup CompactPCI IC 2000
53. ubject to misuse abuse accident or improper instal lation Advantech assumes no liability under the terms of this warranty as a consequence of such events Because of Advantech s high quality control standards and rigorous test ing most of our customers never need to use our repair service Ifan Advantech product is defective it will be repaired or replaced at no charge during the warranty period For out of warranty repairs you will be billed according to the cost of replacement materials service time and freight Please consult your dealer for more details If you think you have a defective product follow these steps 1 Collect all the information about the problem encountered For example CPU speed Advantech products used other hardware and software used etc Note anything abnormal and list any onscreen messages you get when the problem occurs 2 Call your dealer and describe the problem Please have your man ual product and any helpful information readily available 3 If your product is diagnosed as defective obtain an RMA return merchandize authorization number from your dealer This allows us to process your return more quickly 4 Carefully pack the defective product a fully completed Repair and Replacement Order Card and a photocopy proof of purchase date such as your sales receipt in a shippable container A product returned without proof of the purchase date is not eligible for war ranty service 5
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