PowerDNA DNA-AI-208 Strain Gauge Analog Input Layer — User
Contents
1. 26 B 4 Configuring Framework for Shunt Calibration 27 B 5 Shunt Calibration in C lsssslesesse n 28 B 6 Shunt Calibration in LabVIEW sslssssese III 29 Ode HEU 31 Hi List of Figures Chapter 1 Introduction 0 0 eee eee 1 1 1 DNA AE208 Board nae eu ettet aita EORR 4 1 2 Block Diagram of DNA AI 208 Device Architecture ssseen 4 1 3 DB 37 I O Connector Pinout enne nne nnne nennen nennen 5 Chapter 2 Programming with the High Level API 7 None Chapter 3 Programming with the Low Level API 9 None Appendix A A 1 Photo of DNA STP AI 208 Screw Terminal Panel sse 16 A 2 Pinout Diagram for the DNA STP AI 208 sse nnns 18 A 3 Single Channel Wiring Diagram Full Bridge 18 A 4 Single Channel Wiring Diagram Half Bridge 19 A 5 Single Channel Wiring Diagram Quarter Bridge 20 A 6 Physical Layout of STP AI 208 Board 21 Appendix B B 1 Strain Gauge Bridge icr Rente ra cec lei bu ii Piece oda 23 B 2 Strain Gauge with Shunt Resistance Rs Added a 24 B 3 Usi2. Open communication with IOM hd0 DqOpenlOM IOM IPADDRO DQ UDP DAQ PORT TIMEOUT DELAY amp RdCfg Receive IOM crucial identification data DqCmdEcho hd0 DQRdCfg Set up channel list for n 0 n lt CHANNELS n CL n n STEP 2 Create and initialize host and IOM sides Now we are going to test device DqAcbCreate pDqe hd0 DEVN DQ SSOIN amp bcb Let s assume that we are dealing with AI 208 device dquser initialize acb structure Now call the function DgAcbInitOps bcb amp Config 0 TrigSize NULL pDOSETTRIG TrigMode amp fCLC1k 0 loat fCVClk amp CLSize Copyright 2007 Tel 508 921 4600 www ueidaq com Vers 1 4 United c iecironte industries hes Date 07 26 2007 File AI208 Chap3 fm DNA AI 208 Layer Chapter 3 13 Programming with the Low Level API Ch 0 uint32 ScanBlock amp acb printf Actual clock rate f n fCLCIlk Now set up events DqeSetEvent bcb DQ eFrameDone DQ ePacketLost DQ eBufferError DQ ePacketOOB STEP 3 Start operation Start operations DqeEnable TRUE amp bcb 1 FALSE STEP 4 Process data We will not use event notification at first just retrieve scans while keep looping DqeWaitForEvent amp bcb 1 FALSE EVENT TIMEOUT amp events if events amp DQ eFrameDone minrq acb frames
3. 26 S4 27 DIOO EXT_TRIG S7 PS7 S6 P6 S5 p54 AGND S4 S3 29 10 PS4 P3 30 11 S3 AGND 31 12 PS3 S2 32 52 PS2 33 14 P2 S1 34 15 S1 PS1 35 16 Pi SO 36 17 AGND PO 37 18 50 19 PSO ooo Ou p N 20 37 Figure A 2 Pinout Diagram for the DNA STP Al 208 Figure A 3 shows a typical Single Channel Wiring diagram for a Full bridge Strain Gauge connected to the STP AI 208 panel As the figure indicates you should remove the board mounted jumper when you use a 6 wire Circuit Insert jumper when using a 4 wire connection Remove when using a 6 wire connection to DB 37 Connector Figure A 3 Single Channel Wiring Diagram Full Bridge Copyright 2007 Tel 508 921 4600 Vers 1 4 sue MD ns Date 07 26 2007 File Al 208 App A fm DNA STP AI 208 Strain Gauge Analog Input Layer Appendix A 19 Accessories Figure A 4 shows a typical single channel wiring diagram for a Half bridge Strain Gauge connected to the STP AI 208 panel As the figure indicates you should remove the board mounted jumper when you use a 4 wire circuit Note that a half bridge circuit requires that you solder precision resistors to the board where indicated in Figure A 6 to complete the measuring bridge As an alternative you can install precision Resistor Divider Networks in SOT23 packages directly on
4. Factor Disengage shunt calibration resistors and apply adjustment factor to every measurement from now on Tel 508 921 4600 Date 07 26 2007 The Shunt Calibration method of calibration and reading uses a 4 wire sensor configuration When you use this method you should permanently connect the PS pin to the S pin and remove the jumper and other 6 wire connections to the PS pin The only connection to PS should be the connection to S shown in bold in Figure B 3 A low level API function allows activation and precise measurement of Ra and Rb Once Ra or Rb value is known the value can be inserted into Equation 4 or 5 to calculate the Gain Adjustment Factor Vers 1 4 File Al 208 App B fm DNA STP AI 208 Strain Gauge Analog Input Layer Appendix B 28 Shunt Calibration Support in Framework 2 5 Shunt The following is an example of C code used for performing shunt calibration Calibration in of strain gauges C Create session for measurement with excitation set to 10V CUeiSession session CUeiAIVExChannel pChannel session CreateAIVexChannel pdna 192 168 100 2 Dev0 Ai0 0 015 0 015 UeiSensorQuarterBridge 10 0 false UeiAIChannelInputModeDifferential Session ConfigureTimingForSimpleIO CueiAnalogScaledReader reader session GetDataStream double voltageWithoutShunt voltageWithShunt Take one measurement without shunt resistor session Start read
5. LI ED status enable operations 10 For streaming operations with hardware clocking the user has to select the fol DQ_LN_STR EAMI NG DQ LN ENABLE enables all layer operations DQ LN CLCKSRCO selects the internal channel list clock CL source as a time base The AI 208 layer supports the CL clock only where the time between con secutive channel readings is calculated by the rule of maximizing setup time per channel If you d like to select the CL clock from an external clock source such as the SYNCx line set DQ LN CLCKSRC 1 as well Settings bInitOps functions The following bits are used define DQ LN IRQEN 1L 10 define DQ LN PTRIGEDGE1 1L 9 define DQ LN PTRIGEDGEO 1L 8 software define DQ LN STRIGEDGE1 1L lt lt 7 define DQ LN STRIGEDGEO 1L 6 software 01 rising define DQ LN CLCKSRCI 1L lt lt 3 define DQ_LN_CLCKSRCO 1L lt lt 2 HW 11 EXT define DQ LN ACTIVE 1L 1 define DQ LN ENABLED 1L 0 lowing flags DO LN ENABLE DQ LN CLCKSRCO DO LN ACTIVE Aggregate rat DO EN LN IRO Per channel rate Number of channels Copyright 2007 United Electronic Industries Inc Tel 508 921 4600 Date 07 26 2007 www ueidaq com File AI208 Chap3 fm Vers 1 4 8 DNA AI 208 Layer Chapter 3 Programming with the Low Level API 3 2 Channel List The Al 208 layer has a very simple channel list st
6. United Electronic Industries The High Performance Alternative PowerDNA DNA AI 208 Strain Gauge Analog I nput Layer User Manual 18 bit 8 channel 4 and 6 wire Strain Gauge Differential Input Layer for the PowerDNA Cube July 2007 Version 1 4 PN Man DNA AI 208 0707 Copyright 1998 2007 United Electronic I ndustries I nc All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form by any means electronic mechanical by photocopying recording or otherwise without prior written permission Information furnished in this manual is believed to be accurate and reliable However no responsibility is assumed for its use or for any infringements of patents or other rights of third parties that may result from its use All product names listed are trademarks or trade names of their respective companies See UEI s website for complete terms and conditions of sale http www ueidaq com company terms aspx Contacting United Electronic Industries Mailing Address 27 Renmar Avenue Walpole MA 02081 U S A For a list of our distributors and partners in the US and around the world please see http www ueidaq com partners Support Telephone 508 921 4600 Fax 508 668 2350 Also see the FAQs and online Live Help feature on our web site Internet Support Support support ueidag com Web Site www ueidaq com FTP Site ftp ftp ueidaq com
7. rT DNA STP AI 208 Strain Gauge Analog Input Layer Appendix A 16 Accessories Appendix A Accessories A 1 DNA STP AI The DNA STP AI 208 Screw Terminal Panel is an easy to use versatile 208 Screw accessory for direct connection of strain gauge and other bridge type sensors to Terminal the DNA AI 208 Strain Gauge Analog Input Layer board It can accept signals Panel from 8 strain gauge type sensor channels in several types of bridge configurations full bridge 4 and 6 wire circuits half bridge 3 and 4 wire circuits and quarter bridge 2 and 3 wire circuits configurations Note that quarter and half bridge configurations require user populated bridge completion resistors Since the panel is supplied with a DB 37 board mounted connector that mates directly with the I O connector on a DNA AI 208 Layer board it can be plugged directly into the Layer in the Cube As an alternative you can use a DNA CBL 37 37 way Flat Ribbon Cable or a DNA CBL 37S 37 way Round Cable to mount the unit as a desktop panel A photo of the panel is shown in Figure A 1 below Figure A 1 Photo of DNA STP AI 208 Screw Terminal Panel RM M M M Copyright 2007 Tel 508 921 4600 Vers 1 4 sr MD ns Date 07 26 2007 File AI 208 App A fm DNA STP AI 208 Strain Gauge Analog Input Layer Appendix
8. A 17 Accessories The Technical Specifications for the DNA STP AI 208 are listed in the table below Technical Specifications Number of channels Bridge Configurations Full Bridge Half Bridge Quarter Bridge Wiring Schemes Full Bridge Half Bridge Quarter Bridge Operating temperature 6 and 4 wire 4 and 3 wire 3 and 2 wire 20 C to 85 C 9096 non condensing 4 x 2 5 x 0 7 Operating humidity Dimensions The Wiring Settings for the DNA STP AI 208 panel are listed in the table below Bridge Configuration Wiring Jumper Scheme Settings J Off 2 Bridge Completion Resistors Full Bridge None required J On J Off J On J Off J On The Bridge Completion Resistors in the table are shown in the bridge circuit wiring diagrams illustrated in Figure A 4 and Figure A 5 Half Bridge RA RB or RN RA RB or RN Quarter Bridge Rc RsTRAIN RM M M M Copyright 2007 Tel 508 921 4600 Vers 1 4 sue MD ns Date 07 26 2007 File Al 208 App A fm DNA STP AI 208 Strain Gauge Analog Input Layer Appendix A 18 Accessories The Pinout for the DNA STP AI 208 DB 37connector is as follows DB 37 male 37 pin connector S7 20 P7 21 AGND 22 S6 23 PS6 24 S5 25 PS5
9. Product Disclaimer WARNING DO NOT USE PRODUCTS SOLD BY UNITED ELECTRONIC INDUSTRIES INC AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS Products sold by United Electronic Industries Inc are not authorized for use as critical components in life support devices or systems A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness Any attempt to purchase any United Electronic Industries Inc product for that purpose is null and void and United Electronic Industries Inc accepts no liability whatsoever in contract tort or otherwise whether or not resulting from our or our employees negligence or failure to detect an improper purchase Table of Contents Chapter 1 Introduction A hee ecu ve rre rr E RUE TES 1 1 1 Orgarizatlor ze ies egets entrate ege bi Ee RO ore Ed RET apu ee as 1 1 1 1 INTOCUCTION EPI 1 1 1 2 DNA AI 208 Layer vy us Re E RERO REEL 1 1 1 3 Programming with High Level API 1 1 1 4 Programming with the Low Level API 1 1 2 The DNA AI 208 Analog Output Layer 3 1 3 Device Architecture 2 2 0 tees 4 1 4 Layer Connectors and Wiring 1 4 1 4 1 GOMMECIONS T nd wad as Sea aq dette te nd ir a a i eda d
10. Tel 508 921 4600 Vers 1 4 United Electronic Industries Inc Date 07 26 2007 File AI 208 App B fm nsi Numerics 3 wire Circuit 20 6 wire Circuit 18 A Architecture 4 B Block Diagram 4 Board mounted Jumper 19 20 Bridge Completion Resistors 16 17 Bridge Configurations 16 C Cable s 22 Calibration 22 Channel List Structure 9 Connector DB 37 5 Connectors 5 D DNA CBL 37 22 DNA CBL 37S 22 DNA STP 37 22 F Flat Ribbon Cable 16 Full bridge Strain Gauge 18 G Gain s 9 H Half bridge Strain Gauge 19 l Input Mode ACB 12 Differential 4 Index Manual Conventions 2 Manual Organization 1 Mode DMap 14 P Photo of DNA AI 208 Board 4 Photo of STP AI 208 Panel 16 Physical Layout of the STP AI 208 21 Pinout 18 Q Quarter bridge Strain Gauge 20 R Resistor divider Networks 19 20 Round Cable 16 s Screw Terminal Panel 16 Screw terminal panels 22 Settings Channel List 9 Configuration 8 Gain 9 Shunt Calibration 23 Shunt Calibration in C 28 Shunt Calibration in LabVIEW 29 Shunt Calibration Resistors 26 Single Channel Wiring 18 SOT23 19 20 Specifications 17 Strain Gauge 10 W Wiring Diagram Half Bridge 19 Wiring Settings 17 t AI n s W rH HN dc nC Copyright 2007 Tel 508 921
11. and the second one to odd numbered chan and Wiring nels Excitation voltage can be switched on and off on a per channel basis When an AI 208 performs continuous acquisition it applies voltage to the next channel in the channel list while acquiring the current channel This technique gives a channel enough time to settle and limits current consumption and heat dissipation by the layer Copyright 2007 Tel 508 921 4600 www ueidaq com Vers 1 4 United Eleetrohie Industries Ine Date 07 26 2007 File AI208 Chap1 fm DNA AI 208 Layer Chapter1 5 Introduction The Al 208 layer can measure voltage on every channel between the S and S terminals differential mode channels 0 7 between the Px lines channels 0x10 0x17 and signal ground and between the PSx and signal ground chan nels 0x20 0x27 The Al 208 layer can also be used to measure signals from differential signal sources other than bridges using the S and S terminals In such application situations sensor excitation is usually not required Precise measurement is achieved through the use of more than 8 channels internally in the Al 208 board NOTE For descriptions of connections used with quarter half and full bridge circuits refer to Figure A 3 Figure A 4 and Figure A 5 in the Appendix 1 4 4 Connectors The pinout of the 37 pin connector for the DNA AI 208 Layer board is shown in Figure 1 3 A physical layout of the board is shown in Figure 1 3 PO
12. 100 in differential mode program the excitation to 10V and turn on scaling with excitation session CreateAI ExChannel pdna 192 168 100 2 Dev0 Ai0 1 0 1 0 1 UeiSensorFullBridge 10 0 true UeiAIChannellnputModeDifferential 2 3 Configuring the Timing 2 4 Reading Data You can configure the Al 208 to run in simple mode point by point or buffered mode ACB mode In simple mode the delay between samples is determined by software on the host computer In buffered mode the delay between samples is determined by the Al 208 on board clock The following sample shows how to configure the simple mode Please refer to the UeiDaq Framework User s Manual to learn how to use the other timing modes session ConfigureTimingForSimpleIO Reading data from the Al 208 is done using a reader object There is a reader object to read raw data coming straight from the A D converter There is also a reader object to read data already scaled to volts or mV V The following sample code shows how to create a scaled reader object and read samples Create a reader and link it to the session s stream CUeiAnalogScaledReader reader session GetDataStream read one scan the buffer must be big enough to contain one value per channel double data 2 reader ReadSingleScan data 2 5 Cleaning up the Session Copyright 2007 United Electronic Industries In
13. 2007 File AI 208 App A fm s Ami A 2 Other Accessories A 3 Layer Calibration DNA STP AI 208 Strain Gauge Analog Input Layer Appendix A 22 Accessories In addition to the DNA_STP AI 208 screw terminal panel the following cables and accessories are available for the Al 208 layer DNA CBL 37 3ft 37 way flat ribbon cable connects DNA AI 208 to panels DNA CBL 37S 3ft 37 way round extender cable with thumbscrew connectors on both ends connects DNA AI 208 to screw termination panels and other devices DNA STP 37 37 way screw terminal panel Please note that once you perform layer calibration yourself the factory calibration warranty is void For Al 208 layers we recommend annual factory recalibration at UEI Copyright 2007 United Electronic Industries Inc Tel 508 921 4600 Vers 1 4 Date 07 26 2007 File AI 208 App A fm DNA STP AI 208 Strain Gauge Analog Input Layer Appendix B 23 Shunt Calibration Support in Framework Appendix B Shunt Calibration Support in Framework B 1 Introduction Strain gauges and load cell measurements are typically based on the Wheatstone bridge which allows the measurement of the very small resistance changes that characterize strain gauges The values measured from a Wheatstone bridge are very sensitive to
14. 27 DOL IOCTL208 analog groun DQOL IOCTL208 DOL IOCTL208 DOL IOCTL208 DQL IOCTL208 DOL IOCTL208 DOL IOCTL208 DOL IOCTL208 DOL IOCTL208 EAD_ EAD_ neas neas eas eas eas eas neas EAD EA EA EAD _ J D D IIIo SA d LN ede amp 5 lt 4 ma d Es 3 3 3 3 REF read 2 ure ure ure ure ure UES ure FAD_AGND connect both differential inputs of the PGA to 5V voltage reference switch resistance Rs multiplexer resistance shunt resistor Ra shunt resistor Rb S4 t to S P4 t Lo AGND PS to AGND Because the resistance can differ from channel to channel current is flowing through different channels of the same multiplexer which can have different resistances you should set up the channel number to be used This function returns the number of samples requested for averaging Data is returned in raw format DgAdv208MeasureParams This function is used to measure a variety of Al 208 front end parameters see channel equivalent diagram Vref Vexc Reference voltage Volts Excitation voltage Volts Vmeas for Rs Volts Switch resistance Ohms Vmeas for Rx Volts Mux resistance Ohms Vmeas for Ra Volts Resistance of shunt resistor Ra plus 5k constant Ohms Vmeas for Rb Volts Resistance of shunt resistor Rb plus 5k constant Ohms Before the function can measure these parameters spe
15. 37 19 PS0 AGND 22 4 S6 External Trigger P7 21 3 PS7 Input only S7 20 2 S7 4 EXT_TRIG Figure 1 3 DB 37 I O Connector Pinout When using a long cable to a sensor be sure to use the same gauge wire for the excitation source GND and GND Sense lines m s Copyright 2007 I Tel 508 921 4600 www ueidaq com Vers 1 4 United Eleetrohie Industries Ine Date 07 26 2007 File AI208 Chap1 fm DNA AI 208 Layer Chapter 2 Programming with the High Level API Chapter2 Programming with the High Level API This chapter describes how to program the PowerDNA Al 208 using UeiDaq s Framework High Level API Since Framework is object oriented its objects can be manipulated in the same manner using different development environments such as Visual C Visual Basic or LabVIEW Although the following section focuses only on the C API the concept is the same no matter what programming language you use Please refer to the UeiDaq Framework User Manual for more information on using other programming languages 2 1 Creating a The Session object controls all operations on your PowerDNA device There session fore the first task is to create a session object as follows CUeiSession session 2 2 Configuring Framework uses resource strings to select each device subsystem and chan Channels nels to use within a session and The resource string syntax is similar to a web URL Excitation lt d
16. 4600 www ueidaq com Vers 1 4 M EU dc Ng Date 07 26 2007 File AI 208IX fm
17. NA AI 208 Analog Output Layer Copyright 2007 United Electronic Industries Inc DNA AI 208 Layer Chapter 1 Introduction This manual describes the DNA AI 208 18 bit 8 channel Strain Gauge Analog Input Board Layer It also describes the DNA STP 208 Screw Terminal Panel accessory board The technical specifications for the DNA AI 208 Analog Input Layer are listed in Table 1 1 Number of channels 8 differential ADC resolution 18 bits Sampling rate 1S s 1 kS s per channel Input range 10V FIFO size 512 samples Wiring scheme 4 and 6 wire with Kelvin connection all channels share the same ground Bridge configurations Full Bridge Half Bridge with ext terminal panel Quarter Bridge with ext terminal panel Bridge resistance 120Q 3500 100082 and custom Input impedance 10MQ in parallel with SOpF Gains 1 2 4 8 10 20 40 80 100 200 400 800 Gain accuracy Offset accuracy See Table 1 2 Temperature drift Offset drift Gain drift 5uV C typ 30ppm C G 1 45ppm C G 800 Shunt calibration Onboard software selectable 256 steps fom 5K to 205K External Excitation voltage Isolation 350 Vrms Overvoltage protection 40V 55V 1 5V 10 05V software selectable Excitation current 85 mA per channel Excitation type Pulsing for overheating protection Power consumption bridge resistance excitation depende
18. T 2 3 package for precision dividers RSTRAIN Rp Rp 0 196 to DB 37 Connector User supplied raphi bridge completion s aed q resistors resistor onto board or connected divider in SOT23 to screw terminals Package soldered to board Figure A 5 Single Channel Wiring Diagram Quarter Bridge GS a a Copyright 2007 f Tel 508 921 4600 Vers 1 4 United Electronic Industries Inc Date 07 26 2007 File Al 208 App A fm DNA STP AI 208 Strain Gauge Analog Input Layer Appendix A 21 Accessories Figure A 6 shows the physical layout of the STP AI 208 board indicating where you should install bridge completion resistors or resistor divider packages if required for your application It also shows which terminals to use for making the strain gauge connections for a typical channel Solder terminals for external trigger connection Copyright c 2005 Boston USA Plug into dd Mating Connector E on Al 208 Layer wA Jumper id E for Ch 3 PSn Solder terminals for SOT23 divider Pn Sn Ch 1 Sn Solder terminals for z gt AGND bridge completion REO RCi resistors Ground for 758 0044 connector shield Figure A 6 Physical Layout of STP AI 208 Board RM M M M s Copyright 2007 Tel 508 921 4600 Vers 1 4 sr MD ns Date 07 26
19. are teach a aya d dope asa 5 Chapter 2 Programming with the High Level API 6 2 1 Greating a session v oxi di ua uqa seek Pata a nhe aaa del 2 anaq al 6 2 2 Configuring Channels and Excitation 6 2 3 Configuring the timing Ru T 2 4 Reading data u usu yy a ides a a ee a ged ew eae ey 7 2 5 Cleaning up the Session 7 Chapter 3 Programming with the Low Level API 8 3 1 Configuration settings 8 3 2 Channel list settings _ a 1 9 3 3 Layer specific Commands and Parameters 9 3 4 Using Layer in ACB Mode lssssssssssese ren 12 3 5 Using layer in DMap mode sesleeee III 14 Appendix A AccessorieS 2200 c cece eee eee eee eee eee nh nh nn 16 A 1 DNA STP AI 208 Screw Terminal Panel 16 A 2 Other Accessories 22 A 3 Layer Calibration uu s ayna ba teh aoe ERE REP Ry aed wee are epus 22 Appendix B Shunt Calibration Support in Framework 23 B 1 IntroductlOn 3 aote s be tb ebR teres hiebeertpbrbuscrideq4u e eure 23 B 2 Theory un A obs dt sus cit LA ILLA mdr LE Pe a 23 B 3 Using Shunt Resistors on the Al 208
20. bal shunt resistance e Semiconductors involved in the shunt calibration circuitry have signifi cant changes in resistance with temperature change To overcome those problems UEI included 25 ppm C 5kOhm 0 1 resistors into shunt calibration circuitry When PS is connected to S on the screw terminal panel internal circuitry makes it possible to measure voltage drop on one of those precision 25 ppm C resistors thus precisely measuring current through them By knowing current and voltage drop in the shunt calibration circuitry you can calculate total resistance of the switches resistors and multiplexers which is equal to the shunt resistance Due to the additional resistance in the shunt calibration circuitry and the 30 accuracy of 200kOhm digital potentiometer the shunt calibration resistance can be between 10k and 170k Ohms Tel 508 921 4600 Date 07 26 2007 Vers 1 4 File Al 208 App B fm B 4 Configuring Framework for Shunt Calibration Copyright 2007 United Electronic Industries Inc DNA STP AI 208 Strain Gauge Analog Input Layer Appendix B 27 Shunt Calibration Support in Framework Flow of operations The shunt calibration will be performed using the following steps Measure bridge output voltage without shunt Engage shunt and measure bridge output voltage again Calculate what the bridge output offset should be theoretically using Eq 4 or 5 Calculate Gain Adjustment
21. ble for use with a DNA AI 208 layer B Shunt This appendix describes procedures for using Framework to perform shunt cal Calibration Support ibration of strain gauges It includes examples of C code and LabVIEW pro in Framework cedures for shunt calibration Index This is an alphabetical index of topics covered in this manual NOTE A glossary of terms used with the PowerDNA Cube and layers can be viewed and or downloaded from www ueidaq com Copyright 2007 Tel 508 921 4600 www ueidaq com Vers 1 4 United c iecironte industries hes Date 07 26 2007 File AI208 Chap1 fm NOTE DNA AI 208 Layer Chapter 1 Introduction Manual Conventions To help you get the most out of this manual and our products please note that we use the following conventions Tips are designed to highlight quick ways to get the job done or reveal good ideas you might not discover on your own Notes alert you to important information CAUTION Caution advises you of precautions to take to avoid injury data loss and damage to your boards or a system crash Text formatted in bold typeface generally represents text that should be entered verbatim For instance it can represent a command as in the following exam ple You can instruct users how to run setup using a command such as setup exe Copyright 2007 United Electronic Industries Inc Tel 508 921 4600 www ueidaq com Vers 1 4 Date 07 26 2007 File AI208 Chap1 fm 1 2 The D
22. c The session object will clean itself up when it goes out of scope or when it is destroyed However you can also clean up the session manually to reuse the object with a different set of channels or parameters session CleanUp Tel 508 921 4600 www ueidaq com Vers 1 4 Date 07 26 2007 File AI208 Chap2 fm 7 3 1 Chapter 3 DNA AI 208 Layer Chapter 3 Programming with the Low Level API Programming with the Low Level API This section describes how to program the PowerDNA cube using the Low level API The low level API offers direct access to PowerDNA DAQBios protocol and also allows you to access device registers directly We recommend that when possible you use the UeiDaq Framework High Level API see Chapter 2 because it is easier to use You should need to use the low level API only if you are using an operating sys tem other than Windows Not all configuration bits apply to the Al 208 layer B Configuration Configuration settings are passed through the DaCmdSetCfg and DqAc 00 00 enable layer irqs stop trigger edge MSB stop trigger edge 01 rising 02 falling start trigger edge MS start trigger edge 02 falling CL clock source MSB CL clock source 01 SW es
23. cify the measurement conditions Channel Channel being used for measurements ExcA ExcB Ra Rb Excitation level A even channels 16 bit Excitation level B odd channels 16 bit Shunt A level 8 bit 256 positions from 0 to 200k Shunt B level 8 bit 256 positions from 0 to 200k The AI 208 layer has a 14 bit excitation DAC and an 8 bit shunt calibration digital potentiometer The digital potentiometer has a 30 initial resistance accuracy 60 150 Ohm runner resistance and a Copyright 2007 Tel 508 921 4600 United Electronic Industries Inc Date 07 26 2007 www ueidaq com Vers 1 4 File Al208 Chap3 fm DNA AI 208 Layer Chapter 3 12 Programming with the Low Level API 35ppm temperature coefficient Thus measuring this resistor is crucial for shunt calibration An additional series resistor 4 99k 0 0196 is inserted in the shunt calibration circuit to ensure precise measurement 3 4 Using Layer This is a pseudo code example that highlights the sequence of functions needed in ACB Mode to use ACB on the AI 208 layer A complete example with error checking can be found in the directory SampleACB208 include PDNA h unit configuration word define CFG208 DQ_LN_ENABLED DO LN ACTIVE N DQ LN CLCKSRCO N DO LN RAW32 uint32 Config CFG208 STEP 1 Start DQE engine fifndef WIN32 DqInitDAQLib endif Start engine DqStartDQEngine 1000 1 amp pDqe NULL
24. els on or off e DqAdv208SetExcVoltage Set excitation voltage for excitation sources A and B and measure it back using specified channels The Al 208 layer is capable of providing two sources of excitation voltage Excitation A is connected to even channels and B is connected to odd channels Excitation voltage can be selected and set at any level from 1 5V to 10V This function sets up excitation voltage as close as possible to the requested level and reads it back from the selected channels The user can select either channels 0x10 through 0x17 to read the excitation voltage from the Px terminal four wire connection or channels 0x20 through 0x27 to read the excitation voltage from PSx terminals six wire connection All readings are performed relative to AGND The user has to use the read back excitation voltage from the terminal because of DACs there is a voltage drop in the strain gauge leads and DAQ output quantization error amounts to 1 1024 of the range Note that this function must be called before starting data acquisition or reading channels in order to set up the proper excitation voltage source before gathering data Copyright 2007 Tel 508 921 4600 www ueidaq com Vers 1 4 United c iecironte industries hes Date 07 26 2007 File AI208 Chap3 fm DNA AI 208 Layer Chapter 3 11 Programming with the Low Level API e DqAdv208ReadChannel This function performs raw measurements of the following values 0x0 0x
25. er ReadSingleScan amp voltageWithoutShunt session Stop Turn on shunt calibration for the first channel shunt branch R4 and program the shunt resistance to 100kOhms pChannel gt EnableShuntCalibration true pChannel SetShuntLocation UeiShuntLocationR4 pChannel gt SetShuntResistance 100000 0 Take one measurement with shunt resistance enabled session Start reader ReadSingleScan amp voltageWithShunt Session Stop Retrieve the global shunt resistance for the first channel and the actual excitation voltage double Rs pChannel GetActualShuntResistance double Vex pChannel GetExcitationVoltage Assume all gauge resistances are 330 Ohms double Rgage 330 calculate actual and theoretical offset caused by shunt double measuredDeltaV voltageWithShunt voltageWithoutShunt double calculatedDeltaV Vex Rgage 4 0 Rs 2 0 Rgage Calculate gain adjustment factor double gaf calculatedDeltaV measuredDeltaV Turn off shunt resistor pChannel EnableShuntCalibration false Starts the session again session Start Copyright 2007 Tel 508 921 4600 Vers 1 4 tiis o Du Date 07 26 2007 File AI 208 App B fm DNA STP AI 208 Strain Gauge Analog Input Layer Appendix B 29 Shunt Calibration Support in Framework Read calibrated measurements double calibratedVoltage reader ReadSing
26. evice class gt lt IP address gt lt Device Id gt lt Subsystem gt lt Channel list gt For PowerDNA the device class is pdna For example the following resource string selects analog input channels 0 2 3 4 on device 1 at IP address 192 168 100 2 pdna 192 168 100 2 Dev1 A10 2 3 4 The gain to be applied on each channel is specified with low and high input limits For example the Al 208 available gains are 1 2 4 8 10 20 40 80 100 200 400 800 and the maximum input range is 10V 10V To select a gain of 100 you must specify input limits of 0 1V 0 1V Configure channels 0 1 to use a gain of 100 in differential mode session CreateAIChannel pdna 192 168 100 2 Dev0 Ai0 1 0 1 0 1 UeiAIChannellInputModeDifferential To program the excitation circuitry you need to configure the channel list using the session object method CreateAIVExChannel instead of Cre ateAIChannel This method also gives you the ability to select the bridge configuration you want and to select whether or not you wish to obtain the acquired data already scaled in mV V acquired voltage divided by actual excitation voltage as follows Copyright 2007 Tel 508 921 4600 www ueidaq com Vers 1 4 United Elgetronie Industries ine Date 07 26 2007 File Al208 Chap2 fm DNA AI 208 Layer Chapter 2 Programming with the High Level API Configure channels 0 1 to use a gain of
27. ialize host and IOM sides DqDmapCreate pDqe hd0 amp pBcb UPDATE PERIOD amp dmapin amp dmapout STEP 3 Add channels into DMap for i 0 i lt CHANNELS i DqDmapSetEntry pBcb DEVN DQ SSOIN i DQ ACB DATA RAW 1 amp ioffset il DqDmapInitOps pBcb DqeSetEvent pBcb DO eDataAvailable DQ ePacketLost DQ eBufferError DQ ePacketOOB STEP 4 Start operation DqeEnable TRUE amp pBcb 1 FALSE STEP 5 Process data Copyright 2007 Tel 508 921 4600 www ueidaq com Vers 1 4 United c iecironte industries hes Date 07 26 2007 File AI208 Chap3 fm 14 DNA AI 208 Layer Chapter 3 Programming with the Low Level API while keep_looping DqeWaitForEvent amp pBcb 1 FALSE timeout amp eventsin if eventsin amp DQ eDataAvailable datarcvt printf ndata for i 0 i lt CHANNELS i printf s04x uint32 ioffset i STEP 6 Stop operation DqeEnable FALSE amp pBcb 1 FALSE STEP 7 Clean up DqDmapDestroy pBcb DqStopDOQEngine pDqe DqcCloseIOM hd0 ifndef WIN32 DqCleanUpDAQLib endif nr V Copyright 2007 Tel 508 921 4600 www ueidaq com Vers 1 4 United Eieelronie industries ne Date 07 26 2007 File AI208 Chap3 fm mu X NCC d M O
28. ize avail minrg while TRUE DqAcbGetScansCopy bcb data acb framesize acb framesize amp size amp avail samples size CHANNELS for i 0 i lt size CHANNELS i fprintf fo SfNt float data i if i CHANNELS CHANNELS 1 fprintf fo n printf eFD d scans received d samples min d avail d n size samples minrq avail if avail lt minrq break STEP 5 Stop operation DqeEnable FALSE amp bcb 1 FALSE STEP 6 Clean up Copyright 2007 Tel 508 921 4600 www ueidaq com Vers 1 4 United Electronic Industries Inc Date 07 26 2007 File AI208 Chap3 fm DNA AI 208 Layer Chapier 3 Programming with the Low Level API DqAcbDestroy bcb DqStopDOQEngine pDqe DqcCloseIOM hd0 ifndef WIN32 DqCleanUpDAQLib endif 3 5 Using Layer include PDNA h in DMap mode STEP 1 Start DQE engine ifndef _WIN32 DqInitDAQLib endif Start engine DqStartDQEngine 1000 10 amp pDqe NULL open communication with IOM hd0 DqOpenlOM IOM IPADDRO DQ UDP DAQ PORT TIMEOUT DELAY amp DORdCfg Receive IOM crucial identification data DqCmdEcho hd0 DORdCfg for i 0 i lt DQ MAXDEVN i if DORdCfg devmod i printf Model x Option x n DORdCfg devmod i DQRdCfg option i else break STEP 2 Create and init
29. leScan calibratedVoltage calibratedVoltage calibratedVoltage gaf session CleanUp B 6 Shunt The following is an example of a typical LabVIEW procedure for performing Calibration in shunt calibration for strain gauges LabVIEW The procedure is as follows Copyright 2007 STEP 1 Create a session to measure voltage with excitation Differential Y Resource _ abch STEP 3 Measure bridge output with shunt enabled Enable shunt resistor on all channels and program shunt resistance gt ChannelList AIVEx EnableShuntCal L ChannelList AIVEx ShuntLocation bChannelList AIVEx ShuntResistance Analog Single Scaled _ Scan 1D DBL Tel 508 921 4600 Vers 1 4 United Electronic Industries Inc Date 07 26 2007 File Al 208 App B fm DNA STP AI 208 Strain Gauge Analog Input Layer Appendix B 30 Shunt Calibration Support in Framework STEP 4 Calculate Gain Adjustment Factor Bridge Gage resistance Ohms Measurements with shunt v Measurements without shunt v gaf Vexc Rgage 4 0 Rshunt4 2 0 Rgage deltav ain adjustment lt UeiDaq 5 actor ChannelList AIVEx Excitation h ChannelList AIVEx ShuntResistance UeiDaq ni ChannelList AIYEx EnableShuntCal Analog Single Scaled _ Scan 1D DBL i R M A Copyright 2007
30. ng Shunt Resistors on the DNA AI 208 Layer sss 26 DNA AI 208 Layer Chapter 1 Introduction Chapter 1 Introduction This document outlines the feature set and use of the DNA Al 208 strain gauge analog input layer when used with the PowerDNA Core Module This manual describes the following products e DNA AI 208 18 bit 8 channel differential input analog input strain gauge layer board e DNA STP AI 208 Screw Terminal Panel Accessory Board designed as a convenient interface for connecting full half and quarter bridge strain gauge type sensors to the DNA AI 208 board Accessory modules such as cables 1 14 Organization This DNA AI 208 User Manual is organized as follows 1 1 1 Introduction This chapter provides an overview of DNA AI 208 board layer features acces Sories and what you need to get started 1 1 2 DNA AI 208 This chapter provides an overview of the device architecture connectivity logic Layer and accessories for the DNA AI 208 layer board 1 1 3 Programming This chapter provides a general overview of procedures that show how to create with High a session configure the session and generate output on a DNA AI 208 layer Level API working with the UeiDaq Framework High Level API 1 1 4 Programming This chapter describes the Low Level API commands for configuring and using with the Low a DNA AI 208 layer Level API Appendices A Accessories This appendix provides a list of accessories availa
31. nt 2 5W 4 5W Operating temp tested 40 C to 85 C Operating humidity 9096 non condensing Table 1 1 DNA AI 208 Technical Specifications Offset and Gain Calibration Limits Gain LSB mV 1 2 0 000763 0 015259 2 2 0 000763 0 007629 4 4 0 001526 0 007629 8 4 0 001526 0 003815 10 4 0 001526 0 003052 20 4 0 001526 0 001526 40 6 0 002289 0 001144 80 6 0 002289 0 000572 100 6 0 002289 0 000458 200 6 0 002289 0 000229 400 10 0 003815 0 000191 800 18 0 006866 0 000172 Table 1 2 Offset and Gain Calibration Limits Tel 508 921 4600 Date 07 26 2007 www ueidaq com Vers 1 4 File Al208 Chap1 fm 3 DNA AI 208 Layer Chapter 1 4 Introduction Figure 1 1 is a photo of the DNA AI 208 Layer board 120 pin DNA bus connector Power Connector DB 37 female 37 pin I O connector Figure 1 1DNA AI 208 Board 1 3 Device The DNA AI 208 Analog Output Layer board has eight individual analog output Architecture channels A Block Diagram of the board layer is shown in Figure 1 2 PO P2 P4 P6 P1 P3 P5 P7 PO P7 Isolation PSO PS7 32 bit 66 MHz bus t ov E c s P a o 2 g c lt Figure 1 2 Block Diagram of DNA AI 208 Device Architecture 1 4 Layer Two D A converters produce excitation voltages The first converter drives exci Connectors _ tation on even numbered channels
32. on on the device specified and reprograms it in accordance with the channel list supplied This function uses the preprogrammed CL update frequency 10Hz You can reprogram the update frequency by calling the DqCmdSetC1k command after the first call to DgAdv208Read 508 921 4600 www ueidaq com Vers 1 4 Date 07 26 2007 File AI208 Chap3 fm 9 DNA AI 208 Layer Chapter3 10 Programming with the Low Level API Therefore you cannot call this function when the layer is involved in any streaming or data mapping operations If you specify a short timeout delay this function can time out when called for the first time because it is executed as a pending command and layer programming takes up to 10ms Once this function is called the layer continuously acquires data and every next call function returns the latest acquired data If you would like to cancel ongoing sampling call the same function with OxFFFFFFFF as a channel number e DqAdv208SetControl This function allows you to set up different internal parameters The following sub functions are available DOL IOCTL208 SET Ra setvalue for shunt calibration resistor A in 256 steps P to S DOL IOCTL208 SET Rb set value for shunt calibration resistor B in 256 steps S to P DOL IOCTL208 SET EXC A setexcitation DAC A DOL IOCTL208 SET EXC B setexcitation DAC B DOL IOCTL208 SET EXC CH Switch excitation chann
33. ructure as shown below Settings 3 3 Layer specific Commands and Parameters Copyright 2007 United Electronic Industries Inc Bit Name Purpose Macro 31 DQ LNCL NEXT Tells firmware that there is a Next Entry in the channel list 20 DQ LNCL TSRQ Request timestamp as the next data point 11 8 Gain DQ LNCL GAIN 7 0 Channel number Gains are different for different options of the Al 208 layer as listed in the follow ing table Min Allowed Gain Settling Time Layer type Range Gain Number ms Al 201 208 10V 1 0 35 5V 2 1 40 2 5V 4 2 45 1 25V 8 3 50 1V 10 4 55 500mV 20 5 70 250mV 40 6 85 125mV 80 7 100 100mV 100 8 110 50mV 200 9 125 25mV 400 10 140 12 5mV 800 11 160 NOTE The Minimum Allowed Settling Time is the shortest time for which the firmware allows a channel to settle When the scan rate and channel are programmed the firmware allocates the minimum time for each channel depending on the gain selected and then stretches the settling time as much as possible to utilize at least 2 3 of the time between scan clocks The Al 208 layer has a number of layer specific functions as follows Tel DqAdv208Read This function uses DqReadAIChannel but converts data using internal knowledge of the input range and gain of every channel When this function is called for the first time the firmware stops any ongoing operati
34. th one of the branches To simulate a compression load we need to add a shunt resistance to Rg and to simulate a tension load we need to add a resistance to R3 The following figure assumes that all branch resistances are equal to Rg strain gauge resistance and that the R4 branch was shunted with a resistance Rs shunt resistance Figure B 2 Strain Gauge with Shunt Resistance R Added After replacing R4 with R4 Rs R4 Rs in Equation 1 the voltage output of the bridge when the shunt calibration resistor is enabled is R4 Eq 2 Vout Vex R4tRs _ RI R34 R4 R1 R2 R4 Rs The voltage output change after enabling the shunt resistor is AVout Vouts Vout R4 Eq 3 AVout Vex at a R R4 R3 R4 R4 Rs In most applications all branches of the Wheatstone bridge use the same resistance Standard values for Rg are 120 350 and 1000 Ohms After setting R1 R2 R3 Rg Equation 3 becomes _ Rg Eq 4 AVout Ves E TIRE Copyright 2007 Tel 508 921 4600 Vers 1 4 i MD ns Date 07 26 2007 File Al 208 App B fm DNA STP AI 208 Strain Gauge Analog Input Layer Appendix B 25 Shunt Calibration Support in Framework Shunting branch R3 instead of R4 to simulate a tensile load gives Rg Eq 5 AVout l eR Now that we know how to calculate the theoretical offset on the Wheatstone bridge output when one of the branch resistances is changed with a known value we can compare it
35. the resistance of its branches and there can be signal attenuation caused by lead resistances Shunt calibration is used to compensate for the loss of sensitivity The strain gauge is desensitized Shunt calibration is the action of simulating a load on one of the branches of a Wheatstone bridge with a resistor of a known value and comparing the measured value to the calculated ideal value The ratio between the ideal value and the measured value is called Gain Adjustment Factor It should be very close to 1 Multiplying the measurement value by the gain adjustment factor compensates for the loss of sensitivity introduced by the lead resistances in a four wire gauge B 2 Theory Load cell and strain gauge measurement are normally done through a Wheatstone bridge For load cells the Wheatstone bridge is built into the cell For Strain Gauges the bridge is part of the wiring Figure B 1 Strain Gauge Bridge Vex is the excitation voltage applied to the bridge by the instrument Vout is the output voltage measured by the instrument The formula to calculate Vout knowing Vex is Eq 1 Vout vex E RI R3 R4 RI R2 Copyright 2007 f Tel 508 921 4600 Vers 1 4 United Electronic Industries Inc Date 07 26 2007 File Al 208 App B fm DNA STP AI 208 Strain Gauge Analog Input Layer Appendix B 24 Shunt Calibration Support in Framework Simulating a load is usually done by adding a larger resistance in parallel wi
36. the board to complete the bridge circuits Insert jumper when using a 3 wire connection Remove when using a 4 wire connection Rn Chan SOT 2 3 package for precision dividers to DB 37 Connector User supplied User supplied bridge completion bridge completion resistors Soldered resistors resistor onto board or connected divider in SOT23 to screw terminals package soldered to board Figure A 4 Single Channel Wiring Diagram Half Bridge GS a Copyright 2007 f Tel 508 921 4600 Vers 1 4 United Electronic Industries Inc Date 07 26 2007 File Al 208 App A fm sss rrt II rs v T Ts lt saassa aats sC lt s ssrsrsssrss lt rwAtrrvas DNA STP AI 208 Strain Gauge Analog Input Layer Appendix A 20 Accessories Figure A 5 shows a typical single channel wiring diagram for a Quarter bridge Strain Gauge connected to the STP AI 208 panel As the figure indicates you should remove the board mounted jumper when you use a 3 wire Circuit Note that a quarter bridge circuit requires that you solder precision resistors to the board where indicated in Figure A 6 to complete the measuring bridge As an alternative you can install precision resistor divider networks in SOT23 packages directly on the board as shown in Figure A 6 to complete the bridge circuits Insert jumper when using a 2 wire connection Remove when using a 3 wire connection nan E k Rn Chan J SO
37. with the measured value and get the Gain Adjustment Factor Eq 6 Gaf AVoutCalculated AVoutMeasured Multiplying each measured values by the Gain Adjustment Factor gives us calibrated measurements Copyright 2007 United Electronic Industries Inc Tel 508 921 4600 Vers 1 4 Date 07 26 2007 File AI 208 App B fm 23 Using Shunt Resistors on the Al 208 External Wiring DNA STP AI 208 Strain Gauge Analog Input Layer Appendix B 26 Shunt Calibration Support in Framework There are two programmable digital shunt calibration resistors on the Al 208 Ra and Rb The Shunt calibration resistor Ra shunts the branch R4 and Rb shunts R3 Al 208 Copyright 2007 United Electronic Industries Inc RL P H J Disconnect normal Q sense wiring from PS l PS when shunt calibration is used i Ra O To use the shunt calibration feature remove jumper 5k 0 1 S Q Mux 91 5k 0 1 lt Rb R p_ Figure B 3 Using Shunt Resistors on the DNA AI 208 Layer The internal circuitry of the Al 208 makes it difficult to know the exact value of the resistance used to shunt the Wheatstone bridge due to the following factors The digital shunt resistor accuracy is only 30 and needs to be mea sured prior to doing any calculation The resistance of internal components on the Al 208 such as multiplex ers and switches is not negligible and needs to be measured and added to the glo
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