Technical Information Manual
Contents
1. T 11 iue WAS UL PME BO 11 lycos B GLO uie M CONNECTOR ene meee ene ne ne nee ee 12 1 15 FIG 3 2 CLOCK DISTRIBUTION DIAGRAM 15 IE EUN 17 FIG 3 4 EVENT ORGANIZATION STANDARD MODE NORMAL 2 4 0 00 0 00 0 0 00 nnne 19 FIG 3 5 EVENT ORGANIZATION PACK2 5 MODE NORMAL FORMAT RN 20 FIG 3 6 EVENT ORGANIZATION STANDARD MODE ZERO LENGTH ENCODING ppp 20 FIG 3 7 EVENT ORGANIZATION 2 5 MODE ZERO LENGTH ENCODING RN 21 E UDIN ee 23 FIG 3 9 EXAMPLE WITH POSITIVE LOGIC AND NON OVERLAPPING Ni 24 Filename Number of pages Page 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 5 CAEN Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 3 10 EXAMPLE WITH NEGATIVE LOGIC AND NON OVERLAPPING Ni px Ny pyp RN 24 Fic 3 11 EXAMPLE WITH POSITIVE LOGIC AND NON OVERLAPPING pxk ennemis 25 3 12 EXAMPLE WITH POSITIVE LOGIC AND OVERLAPPING px eene 26 FIG 3 13 BLOCK DIAGRAM OF TRIGGER 0000 27 FIG 3 14 LOCAL TRIGGER GENERATION et 28 FIG 3 15 LOCAL TRIGGER RELATIONSHIP WITH COINCIDENCE LEVEL Ne 29 FIG 3 16 EXAMPLE OF BL2. Technical Information Manual Revision n 0 15 March 2010 MOD DT5720 4 CHANNEL 12 BIT 250 MS S DIGITIZER MANUAL REV 0 NPO 00100 09 5720x MUTx 00 CAEN will repair or replace any product within the guarantee period if the Guarantor declares that the product is defective due to workmanship or materials and has not been caused by mishandling negligence on behalf of the User accident or any abnormal conditions or operations CAEN declines all responsibility for damages or injuries caused by an improper use of the Modules due to negligence on behalf of the User It is strongly recommended to read thoroughly the CAEN User s Manual before any kind of operation 4 CAEN reserves the right to change partially or entirely the contents of this Manual at any time and without giving any notice Disposal of the Product The product must never be dumped in the Municipal Waste Please check your local regulations for disposal of electronics products CAEN Is foi PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 TABLE OF CONTENTS 1 GENERAL DESCRIPTION ec icoiusOssivi verno es DU 7 7 22 aE ee eee 9 2 TECHNICAL SPECIFICA 10 2 PACKAGING AND COMPLIANCY AN AEE EAA 10 2 2 POWER REQUIREMEN
3. X chamein 25 aa jaw X X Chamein THRESHOLD ovina kw X Game TMEOVERUNDERTHRESHOLD X chameinstarus pem k Channel n EPGA FIRMWARE REVISION X X jaw X ADC CONFIGURATION ovina jaw X CHANNEL CONFIGURATION 0400 aw X CHANNEL CoNFiouRATIONBITseT pem X CHANNEL CONFIGURATION BIT CLEAR losos X BUFFERORGANZATION jaw X customsze X x ACQUISITION STATUS 0x8104 SW TRIGGER 0x8108 ain ae POSTTRIGGERSETTING _ FRONTPANELVOCONTROL Rw _ CHANNELENABLEMAsK oso ROCFPGAFIRMWAREREVISION R _ EventsToreD 0 X X X poaRDINFO wem R _ EVENT SIZE 0x814C CONTROL OxEFOO INTERRUPTEVENTNUMBER oers BLTEVENTNUMBER Rw X OX scrarcn 1 ew OX swreseT FLASHENABLE X NPO Filename Number of pages Page 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 32 CAEN Q is for Discove PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 REGISTER NAME ADDRESS MODE RES S
4. 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 37 CAEN Q is for Discove PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 0 Channel 2 trigger disabled 1 Channel 2 trigger enabled 2 0 Channel 1 trigger disabled 1 Channel 1 trigger enabled EN 0 Channel 0 trigger disabled 1 Channel 0 trigger enabled This register bits 0 3 enable the channels to generate a local trigger as the digitised signal exceeds the Vth threshold see S 3 5 3 Bito enables to generate the trigger bit enables Ch1 to generate the trigger and so on Bits 26 24 allows to set minimum number of channels that must be over threshold beyond the triggering channel in order to actually generate the local trigger signal for example if bit 3 0 F all channels enabled and Local trigger coincidence level 1 whenever one channel exceeds the threshold the trigger will be generated only if at least another channel is over threshold at that moment Local trigger coincidence level must be smaller than the number of channels enabled via bit 3 0 mask EXTERNAL TRIGGER ENABLE bit30 enables the board to sense TRG IN signals SW TRIGGER ENABLE bit 31 enables the board to sense software trigger see S 4 19 4 21 Front Panel Trigger Out Enable Mask 0x8110 r w 31 0 Software Trigger Disabled 1 Software Trigger Enabled 0 External Trigger Disabled 30
5. 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 16 OSC CLK handles Local Bus communication between motherboard and mezzanine boards see red traces in the figure above REF CLK handles ADC sampling trigger logic acquisition logic samples storage into RAM buffer freezing on trigger through a clock chain Such domain can use either an external via front panel signal or an internal via local oscillator source in the latter case OSC CLK and REF CLK will be synchronous the operation mode remains the same anyway DT5720 uses an integrated phase locked loop PLL and clock distribution device AD9520 It is used to generate the sampling clock for ADCs SAMP CLKO SAMP CLK1 and trigger logic synchronization clock TRG CLK Both clocks can be generated from the internal oscillator or from external clock input CLK IN By default board uses the internal clock as PLL reference REF CLK External clock can be selected by register access AD9520 configuration can be changed and stored into non volatile memory AD9520 configuration change is primarly intended to be used for external PLL reference clock frequency change DT5720 locks to an external 50 MHz clock with default AD9520 configuration Please contact CAEN support frontend caen it for more information and configuration tools Refer also to AD9520 data sheet for more details http www analog com UploadedFiles Data Sheets AD9520 pdf 3 2 1 Trigger Clock TRG CLK signal has a freq
6. 250MS s Digitizer 15 03 2010 0 NPO the required number of samples for building the pre trigger of the event is not reached yet this happens typically as the trigger occurs too early either with respect to the RUN ACQUISITION command see 8 3 3 1 or with respect to a buffer emptying after a MEMORY FULL status the trigger overlaps the previous one and the board is not enabled for accepting overlapped triggers As a trigger is refused the current buffer is not frozen and the acquisition continues writing on it The Event Counter can be programmed in order to be either incremented or not If this function is enabled the Event Counter value identifies the number of the triggers sent but the event number sequence is lost if the function is not enabled the Event Counter value coincides with the sequence of buffers saved and readout 3 3 2 1 Custom size events It is possible to make events with a number of Memory locations which depends on Buffer Organization register setting see S 4 15 smaller than the default value One memory location contains two ADC samples and the maximum number of memory locations is therefore half the maximum number of samples per block NS 512K Nblocks 640K Nblocks when Pack2 5 mode is used Smaller values can be achieved by writing the number of locations into the Custom Size register see S 4 16 0 means default size events i e the number of memory locations i
7. CHANNEL N DAC 0XIN98 R W 35 4 11 CHANNEL N ADC CONFIGURATION OXINOC RAW 35 4 12 CHANNEL CONFIGURATION 0X8000 0000500 0 0 35 4 13 CHANNEL CONFIGURATION BIT SET 0 8004 W 30 4 14 CHANNEL CONFIGURATION BIT CLEAR 0X8008 36 4 15 BUFFER ORGANIZATION 0 800 R W 40 2 4 0 0000 0 0 36 4 16 bae dua 36 4 17 ACODISITION CONTROLAO X3 100 R W RE 36 4 18 JXCODISITION STATUS ONS TOA R len EE 37 4 19 SOFTWARE TRIGGER 0 8108 W nee nn e nemen he en 37 4 20 TRIGGER SOURCE ENABLE MASK 0X810C R W 37 4 2 FRONT PANEL TRIGGER OUT ENABLE MASK 0X81 10 R W eene 38 4 22 POST TRIGGER SETTING 0 8114 R W 38 4 23 FRONT PANEL I O CONTROL 0X81 IC 30 4 24 CHANNEL ENABLE MASK 0X8120 02 0 0 0 ne enhn 39 4 25 ROC FPGA FIRMWARE REVISION 0 8124 R 39 4 26 39 4 27 BOARD INFO 39 Filename
8. Number of pages Page 00100 09 5720 00 DT5720_REV0 DOC 42 4 CAEN Is fos PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 4 28 EVENT SIZE IAC EAEE 39 4 29 CONROE B W 40 4 30 STATU UXETOR 40 4 31 INTERRUPT STATUS ID XBET4 R W 40 4 32 INTERRUPT EVENT NUMBER OXEF18 R W resins enses nnus 40 4 33 BLOCK TRANSFER EVENT NUMBER O XEFIC 0 0 2 40 4 34 We idu RE 40 4 35 RESET 41 4 36 SOFWARE WV 41 4 37 PLASILENABEB UXEE2C B W PUR 41 4 38 HLEASHDATA OXEB30 41 4 39 CONFIGURATION RELOAD 4 41 5 NS TION 42 POWER ON SEQUENCE 42 2 2 UN SPATUS 42 22 FIRMWARE UPORA DE N 42 LIST OF FIGURES FIG 1 1 D5720 DESKTOP WAVEFORM DIGITIZER ee 7 FIG LT NIOD D5720 BLOCR DIAGRAM ee 9 FIG 2 1 EB PANEL 10 ODN 10 FG 2 2 MCX CONNECTOR
9. Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 3 4 Zero suppression The board implements two algorithms of Zero Suppression and Data Reduction Full Suppression based on the signal amplitude 75 Zero Length Encoding ZLE The algorithm to be used is selected via Control register and its configuration takes place via two more registers CHANNEL n 25 THRES and CHANNEL ZS NSAMP When using these algorithms it must be noticed that that one datum 64bit long word contains 4 samples 5 samples with Pack2 5 mode therefore depending also on trigger pom settings of bit31 of Channel n Z8 THRES register threshold is crossed if Positive Logic one datum is considered OVER threshold if at least one sample is higher or equal to threshold Negative Logic one datum is considered UNDER threshold if at least one sample is lower than threshold 3 4 1 Zero Suppression Algorithm 3 4 1 1 Full Suppression based on the amplitude of the signal Full Suppression based on the signal amplitude allows to discard a full event if the signal does not exceed the programmed threshold for Ns subsequent data at least Ns is programmable see 5 4 4 It is also possible to configure the algorithm with negative logic in this case the event is discarded if the signal does not remain under the programmed threshold for Ns subsequent data at least 3 4 1 2 Zero Length Encoding ZLE Zero
10. 15 14 131211109 8 7 6 5 4 3 2 10 SIZE CONTROL WORD 0000 SAMPLE 1 0000 SAMPLE 0 CH 1 fo CONTROL WORD 0000 SAMPLE N 1 CH 1 0 000 SAMPLE N 2 SIZE CONTROL WORD x 0000 SAMPLE 1 CH 3 0000 SAMPLE 0 CH 3 x D CONTROL WORD F 0000 SAMPLE N 1 CH 3 0000 SAMPLE N 2 CH 3 Fig 3 6 Event Organization standard mode Zero Length Encoding NPO Filename Number of pages Page 00100 09 5720x MUTXx 00 DT5720 REVO DOC 42 CAEN Tools Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 1019187654321 0 SIZE CONTROL WORD 0 0 S 2 CH 3 L S 1 CH 3 H 1 CH 3 L 0 CH 3 H S 0 CH 3 L 0 0 S 4 CH 3 H 4 CH 3 L S 3 CH 7 H 3 CH 7 L 2 CH 3 H 5 CONTROL WORD lt 0 ES S N 2 CH 3 L S N 3 CH 3 H S N 3 CH 3 L S N 4 CH 3 H S N 4 CH 3 L 0 S N CH 3 H S N CH 3 L S N 1 CH 3 H S N 1 L S N 2 CH 3 H Fig 3 7 Event Organization Pack2 5 mode Zero Length Encoding NPO Filename Number of pages Page 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 21 CAEN PRELIMINARY Document type Title Revision date
11. 22 freezing then the buffer for readout purposes while acquisition continues on another buffer Table 3 1 Buffer Organization REGISTER see 4 15 BUFFER NUMBER SRAM 1 25 MB ch Pack2 5 1 25 An event is therefore composed by the trigger time tag and post trigger samples and the event counter Overlap between acquisition windows may occur a new trigger occurs while the board is still storing the samples related to the previous trigger this overlap can be either rejected or accepted programmable via software If the board is programmed to accept the overlapped triggers as the overlapping trigger arrives the current active buffer is filled up then the samples storage continues on the subsequent one In this case events will not have all the same size see figure below EVENT n TRIGGER EVENT n 1 EVENT n 2 Recorded Not Recorded O PRE POST ACQUISITION WINDOW Overlapping Triggers A trigger can be refused for the following causes acquisition is not active memory is FULL and therefore there are no available buffers NPO Filename 00100 09 5720x MUTx 00 DT5720 REVO DOC Fig 3 3 Trigger Overlap Number of pages 42 Page 17 ver PRELIMINARY Ix for Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit
12. Data transfer activity SSS O PLL LOCK The PLL is locked to the reference clock PLL BYPS green The reference clock drives directly ADC clocks the PLL circuit is switched off and the PLL_LOCK LED is turned off green RUN bit set see 8 4 18 Triggers are accepted Triggers are DRDY Event data depending on acquisition mode are present in the Output Buffer BUSY All the buffers are full NPO Filename Number of pages Page 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 13 Tools Discovery Document Users Manual PRELIMINARY Title Revision date Revision Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 Technical specifications table Table 2 3 Mod DT5720 technical specifications Desktop module 154x50x164 mm WxHxD Weight 680 gr 4 channels MCX 50 Ohm Single ended Input range 2 Vpp Bandwidth 125 MHz Programmable DAC for Offset Adjust x ch adjustment range 1V Resolution 12 bit Sampling rate 10 to 250 MS s simultaneously on each channel Three operating modes PLL mode internal reference 50 MHz loc oscillator PLL mode external reference on IN Jitter lt 100ppm PLL Bypass mode Ext clock on CLK IN drives directly ADC clocks Freq 10 250 MHz IN AMP Modu 11 AC coupled differential input clock LVDS ECL PECL LVPECL CML single ended NIM TTL available Jitter lt 100ppm TRG IN LEMO 50 Ohm NIM TT
13. Length Encoding allows to transfer the event in compressed mode discarding either the data under the threshold set by the User positive logic or the data over the threshold set by the User negative logic With Zero Length Encoding it is also possible to set LOOK BACK the number of data to be stored before the signal crosses the threshold and or Nirwo LOOK FORWARD the number of data to be stored after the signal crosses the threshold see 4 3 In this case the event of each channel has a particular format which allows the construction of the acquired time interval Total size of the event total number of transferred 32bit data words Control word stored valid data if control word is good Control word stored valid data if control word is good The total size is the number of 32 bit data that compose the event including the size itself The control word has the following format Available with Piggy Back Rev 0 5 and Firmware Rev 0 5 NPO Filename Number of pages Page 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 22 CAEN Is for Discon PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 Bit 0 skip 9 1 good Function 1 AMC FPGA FW rev 0 6 and later 29 21 0 If the control word type is good then it will be followed by as many 32bit data words as those indicated in the stor
14. RES CLR FLASHDAA w CONFIGURATIONRELOAD oera CONFIGURATIONROM 4 2 Configuration ROM OxF000 0xF088 The following registers contain some module s information they are D32 accessible read only manufacturer identifier IEEE OUI Version purchased version Board ID Board identifier Revision hardware revision identifier Serial MSB serial number MSB Serial LSB serial number LSB Table 4 2 ROM Address Map for the Model DT5720 checksum sernum1 JOxF080 sernumO OxF084 VCXO type OxFO88 0 00 AD9520 3 These data are written into one Flash page at Power ON the Flash content is loaded into the Configuration RAM where it is available for readout NPO Filename Number of pages Page 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 33 is for Dtscavi PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 4 3 Channel n ZS THRES 0x1n24 Bit 31 0 Positive Logic 1 Negative Logic 30 11 The 12 LSB represent the value to be compared with each sample 11 0 of the event and see if it is good or skip type see 3 4 and 4 12 4 4 Channel n ZS NSAMP 0 1 28 r w With Full Suppression based on the amplitude ZS AMP bits 20 0 allow to set the number
15. via the external AC DC stabilized 230Vac 12Vdc 1 4A power supply Alpha Elettronica Nr SW18 12 60 CDZ Nr 97894 2 3 Front and Back Panel ES cy CAEN Desktop Digitizer 29 eU Fig 2 1 Mod DT5720 front panel SPARE LINK Fig 2 2 Mod DT5720 back panel NPO Filename Number of pages 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 is for Discover PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 2 4 External connectors 2 4 1 ANALOG INPUT connectors CHO Fig 2 3 MCX connector Function Analog input single ended input dynamics 2Vpp Zin 50Q Mechanical specifications MCX connector CS 85MCX 50 0 16 SUHNER 2 4 2 CONTROL connectors Function IN External trigger input NIM TTL Zin 500 Mechanical specifications 00 type LEMO connectors 2 4 3 ADC REFERENCE CLOCK connectors GND CLK CLK Fig 2 4 CLK IN Connector Function CLK IN External clock Reference input AC coupled diff LVDS ECL PECL LVPECL CML Zdiff 1100 Mechanical specifications AMP 3 102203 4 AMP MODUII 2 4 4 Digital connectors Function e GPI programmable front panel input NIM TTL Zin 50Q NPO Filename Number of pages Page 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 11 CAEN Q is for Discove PRELIMINARY Document type Title Rev
16. 0 S Nirwo lt then readout event 15 N 4 N 5 control words 1 size Skip 2N Good 2 N words with samples over threshold Skip 2 N3 Good N 4 N 5 N 5 235 words with samples over threshold 3 If the algorithm works in positive logic and 0 N S lt then the readout event is NPO Filename Number of pages Page 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 25 Is for Discover PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 gt 3 control words 1 size Skip 2N Good 2 Na N 2 words with samples over threshold Skip 5 2 Ns Niewp 4 If the algorithm works in positive logic and S lt Nirwo 0 Fig 3 12 Example with positive logic and overlapping then the readout event is N 4 4 control words 1 size Skip 2 1 Niek Good gt 2 N words with samples over threshold Good 2 N5 4 N 4 words with samples over threshold Skip N 5 2N5 In this case there are two subsequent intervals 5 If the algorithm works in positive logic and 0 lt Ni lt lt
17. 1 External Trigger Enabled 29 4 reserved 0 Channel 3 trigger disabled 3 1 Channel 3 trigger enabled 0 Channel 2 trigger disabled 1 Channel 2 trigger enabled 0 Channel 1 trigger disabled 1 Channel 1 trigger enabled 0 Channel 0 trigger disabled 1 Channel 0 trigger enabled This register bits 0 3 enable the channels to generate a TRG_OUT front panel signal on GPO output as the digitised signal exceeds the Vth threshold see 3 5 3 enables ChO to generate the TRG OUT bit1 enables Ch1 to generate the TRG OUT and so on EXTERNAL TRIGGER ENABLE bit30 enables the board to generate the TRG OUT SW TRIGGER ENABLE bit 31 enables the board to generate TRG OUT see S 4 19 4 22 Post Trigger Setting 0x8114 r w Post trigger value The register value sets the number of post trigger samples The number of post trigger samples is Npost PostTriggerValue 4 ConstantLatency where Npost number of post trigger samples PostTriggerValue Content of this register ConstantLatency constant number of samples added due to the latency associated to the trigger processing logic in the ROC FPGA this value is constant but the exact value may change between different firmware revisions NPO Filename Number of pages Page 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 38 AEN Q is for PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250M
18. 2 then the readout event is 4 control words 1 size Skip 2 1 Niek Good 2 N words with samples over threshold Good 2 2N 2Nirwp N 4 words with samples over threshold Skip 2 In this case there are two subsequent GOOD intervals These examples are reported with positive logic the compression algorithm is the same also working in negative logic NPO Filename Number of pages Page 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 26 Tools for Discovery PRELIMI NA RY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 3 5 Trigger management All the channels in a board share the same trigger this means that all the channels store an event at the same time and in the same way same number of samples and same position with respect to the trigger several trigger sources are available Mother Board Mezzanines Memory Buffers GPO TRG OUT f TRG IN RIGGE a Acquisition Logic Digital Local Bus Interface Fig 3 13 Block diagram of Trigger management 3 5 1 External trigger External trigger can be NIM TTL signal on LEMO front panel connector 50 Ohm impedance The external trigger is synchronised with the internal clock see S 3 2 1 if External tr
19. 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 digitized DT5720 is well suited for data acquisition and processing of signals from scintillators photomultipliers or SiPM detectors implementing function functionalities of a digital QDC Table 1 1 Available items NPO Filename Number of pages Page 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 8 CAEN is for PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 1 2 Block Diagram FRONT PANEL x4 channels AMC FPGA ADC amp MEMORY CONTROLLER BUFFERS o zl C ROC FPGA Readout control Optical link control USB interface control Trigger control External interface control Fig 1 1 Mod D5720 Block Diagram The function of each block will be explained in detail in the subsequent sections NPO Filename Number of pages Page 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 9 is for Discove PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 2 Technical specifications 2 1 Packaging and Compliancy The unit is a Desktop module housed in a 154x50x164 mm alloy box 2 2 Power requirements The module is powered
20. 720 REVO DOC 42 3 Is for Discos PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 3 5 2 Ns EUM MM D 27 3 5 3 27 mr 28 3 5 4 1 29 30 DATATRANSFER CAPABILITIES 29 945 30 3 0 OPTICAL LINK AND USB ACCESS 30 3 8 1 E aa A E 31 4 BOARD INTERNAL REGISTERS 32 4l REGISTERS ADDRESS MAP 22 4 2 CONFIGURATION ROM OXFOOO OXFO8S 33 4 3 CHANNEL NZS THRES O0X1N24 0200 2 nnne nennen nnne ne se ese 34 4 4 CHANNEL Z8 NSAMP OX1N28 R W eene enne 000600 34 4 5 CHANNEL THRESHOLD OXINS8035 02 2 1 26660 0000000000 ense ense sense ense eise sensere 34 4 6 CHANNEL OVER UNDER THRESHOLD 1384 R W 34 AI OCHANNELNSTATUSTOXINGSS 34 4 8 CHANNEL FPGA FIRMWARE 0 1 8 35 4 9 CHANNEL BUFFER OCCUPANCY 0 1394 2 200000 2 0 35 4 10
21. Channel Configuration register 6 1 Fig 3 14 Local trigger generation 3 5 3 1 Trigger coincidence level is possible to set the minimum number of channels that must be over threshold beyond the triggering channel in order to actually generate the local trigger signal If for example Trigger Source Enable Mask see 4 20 bits 3 0 F all channels enabled and Local trigger coincidence level 1 bits 26 24 whenever an enabled channel exceeds the threshold the trigger will be generated only if at least another channel is over threshold at that moment Local trigger coincidence level must be smaller than the number of channels enabled via bit 3 0 mask The following figure shows examples with Local trigger coincidence level 1 and 0 NPO Filename Number of pages Page 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 28 CAEN is for PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 3 6 NPO CHO THRESHOLD CHO IN CH1 THRESHOLD CH1 IN LOCAL TRG 0 LOCAL TRG 1 TRIGGER Coinc_lev 1 TRIGGER Coinc_lev 0 Fig 3 15 Local trigger relationship with Coincidence level 3 5 4 Trigger distribution The OR of all the enabled trigger sources after being synchronised with the internal clock becomes the global trigger of the board and is fed in parallel to all the channels which store an event A T
22. L GPI GPO LEMO 50 Ohm NIM TTL 1 25 M sample ch Multi Event Buffer Programmable event size and pre post trigger Divisible into 1 1024 buffers Readout of Frozen buffer independent from write operations in the active buffer ADC data storage Common Trigger TRG IN External signal Software from USB or Optical Link Self trigger Internal threshold auto trigger Daisy chain trigger propagation among boards using GPO 32bit 8ns 34s range Allows data alignment and consistency across multiple 075720 modules CLK IN allows the synchronization to a common clock source ensures Trigger time stamps and start acquisition times alignment USB2 0 and USB1 1 compliant Up to 30 MB s transfer rate 2222 CAEN proprietary protocol up to 80 MB s transfer rate with Optical Link Controller Mod A2818 A3818 Firmware can be upgraded via Optical Link or USB interface 2 General purpose C and LabView Libraries Demo and Software Tools for Windows and Linux Voltage range 12 10 Vdc NPO 00100 09 5720x MUTx 00 Filename Number of pages Page DT5720_REV0 DOC 42 14 CAEN Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 3 Functional description 3 1 Analog Input Input dynamics is 2V Zin 50 16bit DAC allows to add a DC offset to the signal in the 1 V range Th
23. Niewo If the algorithm works in negative logic and Nigk lt Nigk lt DS 2 PEN NLFWD N LBK Nek Fig 3 10 Example with negative logic and non overlapping Nurwp then the readout event is N 4 N s 5 control words 1 size Good 2 N1 words with samples under threshold Skip 2 Niewp Niek Good 2 N words with samples under threshold NPO Filename Number of pages Page 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 24 CAEN Tools for Discover PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 Skip 2 Niewp Niek Good N s 2 Ni T 5 N 5 words with samples under threshold In some cases the number of data to be discarded can be smaller than gk and 1 If the algorithm works in positive logic and S lt Nirwp 0 Fig 3 11 Example with positive logic and non overlapping then the readout event is gt 5 control words 1 size Good 10 2 N4 words with samples over threshold Skip 2 N3 Good 2 words with samples over threshold Skip N 5 2N5 2 If the algorithm works in positive logic and Niek
24. Ns of subsequent data which must be found over under threshold depending on the used logic necessary to validate the event if this field is set to 0 it is considered 1 With Zero length encoding ZLE bit 31 16 allows to set read the number of data to be stored before the signal crosses the threshold bit 15 0 allows to set read Ni the number of data to be stored after the signal crosses the threshold see 8 3 4 and 8 4 12 4 5 Channel n Threshold 0x1n80 r w Bit 11 0 Threshold Value for Trigger Generation Each channel can generate a local trigger as the digitised signal exceeds the Vth threshold and remains under or over threshold for Nth 4 samples 5 samples in Pack2 5 mode at least local trigger is delayed of Nth 4 5 samples with respect to input signal This register allows to set Vth LSB input range 12bit see also 3 5 3 4 6 Channel n Over Under Threshold 0x1n84 r w Bit 11 0 Number of Data under over Threshold Each channel can generate a local trigger as the digitised signal exceeds the Vth threshold and remains under or over threshold for Nth 4 5 samples at least local trigger is delayed of Nth 4 samples 5 samples in Pack2 5 mode with respect to input signal This register allows to set Nth see also S 3 5 3 4 7 Channel n Status 0x1n88 Bit O 5 3 Channel n DAC see 4 10 Busy 2 1 Busy 0 DC offset updated Memo
25. OCK TRANSFER 30 FAIT OPTICAL CINK DAISY 31 LIST OF TABLES TABLE LI AVAILABLEE ITEMS E EEEE TE ET E E E 9 qe gp 13 TABLE 2 3 MOD DT5720 TECHNICAL SPECIFICATIONS pe 14 TABLE 3 1 BUFFER ORGANIZATION ee 17 TABLE 4 1 ADDRESS MAP FOR THE MODEL DT5720 et 32 TABLE 4 2 ROM ADDRESS MAP FOR THE MODEL DT5720 et 33 NPO Filename Number of pages Page 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 6 NO is for Otscove PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 1 General description NPO 1 1 Overview 9 caen Desktop Digitizer Fig 1 1 Mod 05720 Desktop Waveform Digitizer The Mod DT5720 is a 4 Channel 12 bit 250 MS s Desktop Waveform Digitizer with 2 Vpp dynamic range on single ended MCX coax input connectors The 2 Channel version Mod DT5720A is also available The DC offset adjustment 1V range on each channel by 16bit DACs allows a right sampling of a bipolar Vin 1V up to a full positive Vin 0 2V or negative Vin 0 2V analog input swing without losing dynamic resolution The module features a front panel clock and a PLL for clock synthesis from internal external references The data stream is continuously written in a circular memory buffer When triggered the FPGA writes further N sa
26. PO Filename Number of pages Page 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 19 CAEN Tools far Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1211 10 9 876543210 RESERVED 00 SrD2 cHoLl Sr t cH oH 5 1 CH 0 L S 0 CH O L 00 4 CH 0 H 5 41 CH O L 3 H 5 3 L 5 CH O H 010 SIN CH 0 H SIN CH 0 L S N CH O H S N 1 CH 0 L 5 2 CH 0 H OHO VLVG aoo 2 00 lt Sm cH3IH 0 6101 so cHe 00 4 CH 3 H 5 4 CH 3 L 3 CH 3 H 5 3 CH 3 L S 2 CH 3 H z gt 5 00 SN 1 1 51 2 CH 3 H Fig 3 5 Event Organization Pack2 5 mode normal format 31 3029 28 27 26 25 24 23 22 21 20 19 18 17 16
27. S s Digitizer 15 03 2010 0 4 23 Front Panel I O Control 0x811C r w Bt Function 15 2 O panel output signals GPO enabled 1 1 panel output signals GPO enabled in high impedance ENS 16 1 GPI GPO TRG IN are TTL I O Levels 4 24 Channel Enable Mask 0x8120 r w Bit Function reserved 0 Channel 3 disabled 1 Channel 3 enabled 0 Channel 2 disabled 1 Channel 2 enabled 0 Channel 1 disabled 1 Channel 1 enabled EN 0 Channel O disabled 1 Channel 0 enabled Enabled channels provide the samples which are stored into the events and not erased The mask cannot be changed while acquisition is running 4 25 ROC FPGA Firmware Revision 0x8124 r Bit 1 Function 31 16 Revision date in Y M DD format Bits 31 16 contain the Revision date in Y M DD format Bits 15 0 contain the firmware revision number coded on 16 bit X Y format 4 26 Event Stored 0x812C r Bit This register contains the number of events currently stored in 31 0 Output Buffer This register value cannot exceed the maximum number of available buffers according to setting of buffer size register 4 27 Board Info 0x8140 r Bt Function 0 23 16 Number of channels DT5720 0x04 DT5720A 0x02 1 15 8 Memory size code DT5720 0x02 7 0 Board Type DT5720 0x03 4 28 Event Size 0x814C r 31 0 Nr of 32 bit words in the n
28. TS wo 10 25 PEPOT NE 10 2 EXTERNAL CONNECTOR 11 2 4 1 PON FTO GTN LO Il 2 4 2 CONT OF CONC COWS ainena EE EE AE EE E 11 2 4 3 ADC REFERENCE CLOCK connectors 11 2 4 4 dero RT 11 2 4 5 AR 12 2 4 6 72 2 4 7 2 12 2 4 6 12 2 3 OTHER COMPONENTS we 13 222 4 XN 2 13 TECHNICAL SPECIFICATIONS TABLE terc cita ta 14 3 FUNCTIONAL DESCRIPTION RPRUR PATER RS 15 2 S IRONIA 15 ON 15 JR DIU S M E H 16 SUL MODES cse pid 16 70 3 2 2 Acquisition Triggering Samples and 16 18 5 3 3 18 18 SA MER 100 TE 18 222 CS NE E 19 34 ZERO SUPPRESSION we 22 3 4 1 Zero Suppression Algorithm deduce ela auae ea 22 3 4 1 1 Full Suppression based on the amplitude of the sigmal pp 42 241222 eto 22 3 4 2 Zero Suppression 23 IRON 27 3 5 1 Be nabh P DOE I D 27 Filename Number of pages Page 00100 09 5720x MUTx 00 DT5
29. ber OxEF1C r w This register contains the number of complete events which has to 15 0 be transferred via Block Transfer see 3 7 4 34 Scratch OxEF20 r w B 31 0 Scratch to be used to write read words for test purposes NPO Filename Number of pages Page 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 40 is for Otscove PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 4 35 Software Reset OxEF24 w 31 0 4 36 Software Clear OxEF28 A write access to this location clears all the memories 4 37 sh Enable OxEF2C r w Reserved for Firmware upgrade tool 4 38 sh Data OxEF30 7 0 Data to be serialized towards the SPI On board Flash This register is handled by the Firmware upgrade tool 4 39 Configuration Reload OxEF34 Bit 2 31 0 A write access to this register causes a software reset a reload of Configuration ROM parameters and PLL reconfiguration NPO Filename Number of pages Page 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 4 is for Discove PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 5 Installation 5 1 Power ON sequence To power ON the board follow this procedure 1 connect the 12V dc pow
30. d USB access The board houses a USB2 0 compliant port providing a transfer rate up to 30 MB s and a daisy chainable Optical Link able to transfer data at 80 MB s the latter allows to connect up to eight DT5720 to a single Optical Link Controller a standard PC equipped with the PCI card CAEN Mod A2818 The A2818 is a 32 bit 33 MHz PCI card the communication path uses optical fiber cables as physical transmission line see S 1 1 A new type of PCle communication card A3818 with up to four optical links will be soon available contact info caen it Filename Number of pages Page 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 30 CAEN is for PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 AY2705 and AY2720 have a duplex connector on the A2818 side and two simplex connectors on the board side the simplex connector with the black wrap is for the RX line lower and the one with the red wrap is for the TX higher see also S 2 4 5 The Optical Link allows to perform read Single data transfer and Block transfers and write Single data transfer operations See also the web page http www caen it nuclear product php mod A2818 Control Register bit 3 see S 4 29 allows to enable the module to broadcast an interrupt request on the Optical Link a bit mask see Libraries Demos and Software tools documentation allows to enable the correspo
31. e input bandwidth ranges from DC to 125 MHz with 1s order anti aliasing low pass filter Input Dynamic Range 2 Vpp MCX Positive Unipolar Input 2 00 DAC FSR 50ohm 1 00 0 1 00 2 00 Unipolar Bipolar DAC FSR 2 Fig 3 1 Input diagram 3 2 Clock Distribution AD9520 CLK IN Phase MEZZANINES Detector VCXO CHO INTCLK SAMP CLKO Ee Acquisition amp Memory Control SyncB TRG CLK rrr rrr Te TRG IN Trigger amp Sync Logic Local Bus Local Bus Interface Interface OSC CLK 1 9 4 FPGA ROC Fig 3 2 Clock distribution diagram The module clock distribution takes place on two domains OSC CLK and REF CLK the former is a fixed 50MHz clock provided by an on board oscillator the latter provides the ADC sampling clock NPO Filename Number of pages Page 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 15 CAEN PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0
32. ed skipped words field if the control word type is skip then it will be followed by a good control world unless the end of event is reached IMPORTANT NOTE the maximum allowed number of control words is 62 14 for AMC FPGA release 0 5 and earlier therefore the ZLE is active within the event until the 14 transition between a good and a skip zone or between a skip and a good zone All the subsequent samples are considered good and stored 3 4 2 Zero Suppression Examples If the input signal is the following No are 64bit longwords 4 samples each Fig 3 8 Zero Suppression example If the algorithm works in positive logic and lt Nirwp lt lt 5 samples each with Pack2 5 mode NPO Filename Number of pages Page 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 23 CAEN Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 Fig 3 9 Example with positive logic and non overlapping Nurwp then the readout event is 5 control words 1 size Skip N 2 N4 Good 2 Nigk Niewp N words with samples over threshold Skip N s 2 Ns Good 2 N 4 words with samples over threshold Skip 5 Z2 Ns
33. er supply to the DT5720 2 power up the DT5720 5 2 Power ON status At power ON the module is in the following status e the Output Buffer is cleared registers are set to their default configuration 5 3 Firmware upgrade The DT5720 firmware is stored onto on board non volatile memory CAEN provides a firmware upgrade tool that can be used with either USB or optical link paths Please download the software package application notes and user manual available at http www caen it nuclear product php mod DT5720 then follow the instructions for installation and usage WARNING in case of programming failures the board hosts a backup image of factory firmware Please contact CAEN at support frontend caen it for instuctions in order to restore the backup image Once the board is successfully powered with backup firmware the standard firmware image can be reprogrammed NPO Filename Number of pages Page 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 42
34. ext event NPO Filename Number of pages Page 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 39 is for Otscove PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 4 29 Control OxEFOO r w Reserved must be set to 0 Release On Register Access RORA Interrupt mode 7 6 Reserved must be set to 0 Reserved must be set to O Reserved must be set to 1 3 0 interrupt disabled 1 7 interrupt enabled 2 1 Reserved 0 Reserved must be set to 0 Interrupt request can be removed by accessing this register and disabling the active interrupt level 4 30 Status 0 4 0 Slave Terminated Transfer Flag no terminated transfer 1 Slave Terminated Transfer Flag one transfer has been terminated by DT5720 unsupported register access or block transfer prematurely terminated in event aligned reaout 0 The Output Buffer is not FULL 1 The Output Buffer is FULL 0 No Data Ready 1 Event Ready 4 31 Interrupt Status ID OxEF14 r w 31 0 This register contains the STATUS ID that the module places on the data stream during the Interrupt Acknowledge cycle 4 32 Interrupt Event Number OxEF18 r w INTERRUPT EVENT NUMBER If interrupts are enabled the module generates a request whenever it has stored in memory a Number of events INTERRUPT EVENT NUMBER 4 33 Block Transfer Event Num
35. igger either on channel over or under threshold see S 4 3 and 8 4 6 0 Test Pattern Generation Disabled 1 Test Pattern Generation Enabled 0 Trigger Overlapping Not Enabled 1 1 Trigger Overlapping Enabled on 19 16 Allows to handle trigger overlap see S 3 3 2 reserved This register allows to perform settings which apply to all channels NPO Filename Number of pages Page 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 35 CAEN is for PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 4 13 4 14 4 15 4 16 4 17 NPO It is possible to perform selective set clear of the Channel Configuration register bits writing to 1 the corresponding set and clear bit at address 0x8004 set or 0x8008 clear see the following S 4 13 and 4 14 Default value is 0x10 Channel Configuration Bit Set 0x8004 w Bits set to 1 means that the corresponding bits in the Channel 7 0 Configuration register are set to 1 Channel Configuration Bit Clear 0x8008 w Configuration register are set to 0 Buffer Organization 0x800C r w Bit BUFFER CODE The BUFFER CODE allows to divide the available Output Buffer Memory into a certain number of blocks according to the table in 3 3 2 A write access to this register causes a Software Clear see 8 4 36 This register must not be written while acquisition is runni
36. igger is not synchronised with the internal clock a one clock period jitter Occurs 3 5 2 Software trigger Software trigger are generated INTERNALLY write access in the relevant register see 4 19 3 5 3 Local channel auto trigger Each channel can generate a local trigger as the digitised signal exceeds the Vth threshold ramping up or down depending on register settings and remains under or over threshold for Nth 4 5 samples groups depending on selected storage mode see 3 3 3 at least Nth is programmable via register setting The Vth digital threshold the edge type and the minimum number Nth of 4 5 samples are programmable via register accesses see 4 3 and 4 6 actually local trigger is delayed of Nth 4 5 samples with respect to the input signal NPO Filename Number of pages Page 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 2T CAEN is for PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 N B the local trigger signal does not start directly the event acquisition on the relevant channel such signal is propagated to the central logic which produces the global trigger which is distributed to all channels see S 3 5 4 Nth 4 5 samples Nth 4 5 samples Nth 4 5 samples THRESHOLD CHO IN Local Trigger CHO Channel Configuration register 6 0 Local Trigger CHO
37. ision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 e GPO programmable front panel output NIM TTL Zin 50Q used as output for trigger propagation Mechanical specifications 00 type LEMO connectors 2 4 5 Optical LINK connector LINK TX red wrap black wrap Fig 2 5 LC Optical Connector Mechanical specifications LC type connector to be used with Multimode 62 5 125 cable with LC connectors both sides Electrical specifications Optical link for data readout and slow control with transfer rate up to 80MB s daisy chainable 2 4 6 USB Port Mechanical specifications B type USB connector Electrical specifications USB 2 0 and USB 1 1 compliant 2 4 7 12V External Mechanical specifications RAPC722X SWITCHCRAFT PCB DC Power Jack Electrical specifications 12 DC Input 2 4 8 Spare Link Mechanical specifications 3M 7610 5002 connector NPO Filename Number of pages Page 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 12 is for Discove PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 2 5 Other components 2 5 1 Displays The front panel hosts the following LEDs Table 2 2 Front panel LEDs _ Function 0 Standard selection for CLK GPO TRG IN GPL USB
38. mples for the post trigger and freezes the buffer that can be read via USB or optical link The acquisition can continue dead timeless in a new buffer Each channel has a SRAM memory buffer 1 25 M Samples ch divided in buffers of programmable size 1 1024 The readout from USB or Optical link of a frozen buffer is independent from the write operations in the active circular buffer ADC data storage Zero suppression and data reduction algorithms allow substantial savings in data amount readout and processing rejecting samples smaller than programmable thresholds DT5720 supports multi board synchronization an external reference clock can be distributed to all modules CLK IN and a common input can be used to align all event trigger time tags DT5720 houses USB 2 0 and optical link interfaces USB 2 0 allows data transfers up to 30 MB s The Optical Link supports transfer rate of 80 MB s and offer daisy chain capability Therefore it is possible to connect up to 8 ADC modules to an A2818 Optical Link Controller or 32 modules to an A3818 4 channel version CAEN provides also for this model a Digital Pulse Processing firmware for Physics Applications This feature allows to perform on line processing on detector signal directly Filename Number of pages Page 7 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 is for Otscove PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720
39. nding A2818 s to propagate the interrupt on the PCI bus as a request from the Optical Link is sensed The module can be accessed either via Optical Link or USB USB and Optical Link simultaneous access is anyway not recommended The following diagram shows how to connect DT5720 modules to the Optical Link Link PC side digitizer side BdNum 0 A2818 H EU DT57XX 0 0 side 1 1 Fig 3 17 Optical Link daisy chain 3 8 1 Software tools CAEN provides Libraries Demos and Software tools for Windows and Linux The packages developed so far include Libraries for National Instruments LabVIEW and Demo programs in source code Windows and Linux and as a starting point for the development of user specific applications Software Tools firmware upgrade Module configuration Windows 2000 XP Vista and Linux supported NPO Filename Number of pages Page 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 31 ls for Discover PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 4 Board internal registers The following sections will describe in detail the registers accessible via software in D32 mode content 4 1 Registers address map Table 4 1 Address Map for the Model DT5720 REGISTER NAME ADDRESS MoDEILRESSLRESICIR EVENTREADOUTBUFFER X
40. ng Custom Size 0x8020 r w 0 Custom Size disabled 0 Number of memory locations per event 1 location 2 samples or 2 locations 5 samples when Pack2 5 mode is used see 3 3 3 This register must not be written while acquisition is running Acquisition Control 0x8100 r w Bit 0 Internal clock source 1 External clock source Reserved 0 COUNT ACCEPTED TRIGGERS 3 1 COUNT ALL TRIGGERS allows to reject overlapping triggers see S 3 3 2 0 Acquisition STOP 2 1 Acquisition RUN allows to RUN STOP Acquisition Reserved set to 0 0 REGISTER CONTROLLED RUN MODE 1 GPI CONTROLLED RUN MODE Bit 2 allows to Run and Stop data acquisition when such bit is set to 1 the board enters Run mode and a Memory Reset is automatically performed When bit 2 is reset to 0 the stored data are kept available for readout In Stop Mode all triggers are neglected Bit 0 descritpion Filename Number of pages Page 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 36 is for Otscove PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 0 REGISTER CONTROLLED RUN MODE multiboard synchronisation front panel signal control start stop set clear of bit 2 always active Continuous Gate Mode 1 GPI CONTROLLED RUN MODE Multiboard synchronisation GPI fr
41. of events let X the size of the event expected or read from dedicated register f the event size is known a read cycle equal to N X will return all data without interruptions number of data read from the Event Readout Buffer is higher than N X transfer will be terminated anyway by DT5720 at the end of N X data event size X is unknown for example in case of overlapping triggers there are two cases data transfer x all data will be returned data transfer gt only N X data will be returned Once an event is read the corrisponding acquisition buffers are available to store new data During readout the board can continue to store events in memory up to the maximum number of programmed buffers available the acquisition process is therefore dead timeless event storage is only interrupted if the combination of trigger and readout rate causes a memory full situation all acquisition buffers are used and they have not been read yet In order to exploit the maximum readout rate allowed by the communication path USB or optical link it is suggested to perform block transfer read cycles of at least N X data with N set to its maximum value whether possible READOUT EVENTS BUFFERS Save Tornatore Flag Block size 1024 bytes Slave Terminated Transfer Flag enabled Block Transfer BLT size 16384 bytes N 4 Fig 3 16 Example of block transfer readout Optical Link an
42. ont panel signal works both as SYNC and RUN START command GATE always active Continuous Gate Mode 4 18 Acquisition Status 0x8104 r Bit Board ready for acquisition PLL and ADCs are synchronised correctly 0 not ready 1 ready This bit should be checked after software reset to ensure that the board will enter immediatly run mode after RUN mode setting otherwise a latency between RUN mode setting and Acquisition start might occur PLL Status Flag see S 2 5 1 PLL loss of lock 1 no PLL loss of lock NOTE flag can be restored to 1 via read access to Status Register see S 0 PLL Bypass mode see 8 2 5 1 0 No bypass mode 1 Bypass mode Clock source 5 0 7 Internal 1 External 4 EVENT FULL itis set to 1 as the maximum nr of events to be read is reached EVENT READY it is set to 1 as at least one event is available to readout 0 RUN off 21 11 RUN on 1 0 reserved 3 4 19 Software Trigger 0x8108 31 0 A write access to this location generates a trigger via software 4 20 Trigger Source Enable Mask 0x810C r w Bit Function 31 0 Software Trigger Disabled 1 Software Trigger Enabled 0 External Trigger Disabled 1 External Trigger Enabled 26 24 Local trigger coincidence level default 0 21 reserved 41 3 0 Channel 3 trigger disabled 1 Channel 3 trigger enabled NPO Filename Number of pages Page
43. rigger Out is also generated on the relevant front panel GPO connector NIM or TTL and allows to extend the trigger signal to other boards For example in order to start the acquisition on all the channels in the crate as one of the channels ramps over threshold the Local Trigger must be enabled as Trigger Out the Trigger Out must then be fed to a Fan Out unit the obtained signal has to be fed to the External Trigger Input of all the boards in the crate including the board which generated the Trigger Out signal Data transfer capabilities The board can be accessed by using software drivers and libraries developed by CAEN Single 16 32 register read write cycles multi read cycles and block transfers are supported by the provided library please consult the relevant documentation for details Sustained readout rate is up to 60 MB s for optical link using block transfers and up to 30 MB s for a USB 2 0 link using block transfers as well Filename Number of pages Page 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 20 CAEN is for PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 3 7 3 8 NPO Events readout Event readout is done by accessing the Event Readout Buffer see S 4 1 a FIFO First In First Out memory that can be accessed into the 0x0000 OxOFFC address space Data transfer is always aligned to the programmed number N
44. ry empty 0 Memory full NPO Filename Number of pages Page 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 34 Ix for Driscovi PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer 15 03 2010 0 4 8 Channel n AMC FPGA Firmware 0x1n8C Funcin 0 1 16 Revision date in Y M DD format Bits 31 16 contain the Revision date in Y M DD format Bits 15 0 contain the firmware revision number coded on 16 bit X Y format Example revision 1 3 of 12 June 2007 is 0x7612103 4 9 Channel n Buffer Occupancy 0x1n94 Bit 10 0 Occupied buffers 0 1024 mm 4 10 Channel n DAC 0x1n98 r w Bit DAC Data Bits 15 0 allow to define a DC offset to be added the input signal in the 1V range When Channel n Status bit 2 is set to 0 DC offset is updated see S 4 7 4 11 Channel ADC Configuration 0x1n9C Bit T B D This register allows to pilot the relevant ADC signals See the LTC2242 12 12 Bit 250Msps ADC data sheet for details 4 12 Channel Configuration 0x8000 r w Allows to select Zero Suppression algorithm 0000 no zero suppression default 0010 zero length encoding ZLE 0011 full suppression based on the amplitude ZS 1 Pack2 5 enabled 0 Trigger Output on Input Over Threshold 1 Trigger Output on Input Under Threshold allows to generate local tr
45. s Digitizer 15 03 2010 0 3 9 3 9 Event format examples The event format is shown in the following figure case of 4 channels enabled with Zero Length Encoding disabled and enabled respectively see S 3 3 3 1 and S 3 4 1 2 An event is structured as follows identifier Trigger Time Tag Event Counter samples caught in the acquisition windows The event can be stored in the board memories and can be readout via Optical Link in two ways data format is 32 bit long word and each long word may contain 2 samples Standard mode or two and a half Pack2 5 mode depending on Channel Configuration register setting see S 4 12 The event format is therefore one of the following 31 3029 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1211 10 9876543210 0 000 SAMPLE 1 0 000 0 SAMPLE 0 CH 0 0000 SAMPLE 3 CH 0 0000 SAMPLE 2 r gt ele 0 0 0101 SAMPLE N 1 0 0 0 0 0 SAMPLE N 2 CH 0 0000 SAMPLE 1 CH 3 0000 SAMPLE 0 CH 3 0000 SAMPLE 3 CH 3 0000 SAMPLE 2 CH 3 gt 0000 SAMPLE N 1 CH 3 0000 SAMPLE N 2 CH 3 Fig 3 4 Event Organization standard mode normal format N
46. s the maximum allowed N1 with the constraint O N1 72NS 0 N1 2 5NS with Pack2 5 means that one event will be made of 2 N1 samples 2 5 N1 samples with Pack2 5 3 3 3 Event structure An event is structured as follows Header 4 32 bit words Data variable size and format The event can be readout via Optical Link data format is 32 bit long word therefore each long word contains 4 samples 3 3 3 1 Header It is composed by four words namely Size of the event number of 32 bit long words Bit24 data format 0 normal format 1 Zero Length Encoding data compression method enabled Channel Mask 71 channels participating to event ex CH2 and CH3 participating Ch Mask OxC this information must be used by the software to acknowledge which channel the samples are coming from Event Counter It is the trigger counter it can count either accepted triggers only or all triggers see S 4 16 Trigger Time Tag It is a 32 bit counter 31 bit count 1 overflow bit which is reset as acquisition starts and is incremented at each sampling clock hit It is the trigger time reference 3 3 3 2 Samples Stored samples data from masked channels are not read Filename Number of pages Page 00100 09 5720x MUTx 00 DT5720 REVO DOC 42 18 Tools Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5720 4 Channel 12bit 250MS
47. uency equal to 72 of SAMP CLK therefore a 2 samples uncertainty occurs over the acquisition window Acquisition Modes 3 3 1 Acquisition run stop The acquisition can be started in two ways according to Acquisition Control register bit O setting see S 4 17 setting the RUN STOP bit bit 2 in the Acquisition Control register bit O of Acquisition Control must be set to REGISTER CONTROLLED RUN MODE driving signal high bit O of Acquisition Control must be set to 1 CONTROLLED RUN MODE acquisition is stopped either resetting the RUN STOP bit bit 2 in the Acquisition Control register bit O of Acquisition Control must be set to REGISTER CONTROLLED RUN MODE driving signal low bit of Acquisition Control set to 1 CONTROLLED RUN MODE 3 3 2 Acquisition Triggering Samples and Events When the acquisition is running a trigger signal allows to storea Trigger Time Tag TTT the value of a 32 bit counter which steps on with 125MHz frequency and represents a time reference increment the EVENT COUNTER see 8 4 26 Filename Number of pages Page foals ror ETET Document Title User s Manual MUT Mod DT5720 4 Channel 12bit 250MS s Digitizer fill the active buffer with the pre post trigger samples Revision date 15 03 2010 PRELIMINARY 0 Revision whose number is programmable Acquisition window width S 4
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