Home

FlexModel User`s Manual

1. process tms320c6201 int signal PROCESS 2 tms320c6201 get intr priority inst priority status if priority 2 tms320c6201 begin intr inst priority status interrupt service routine for priority 2 tms320c6201 end intr inst priority status end end Attention 34 With Scirocco 2000 02 you can only define interrupt signals at the top level in your HDL testbench without specifying any hierarchy For example to make the above code sample work with Scirocco 2000 02 change TOP tms320c6201 int signal to tms320c6201 int signal With Scirocco 2000 06 and above use a full path delimited by colons TOP tms320c6201 int signal Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 2 Using FlexModels Scenario 1 INT1 occurs before INT2 To understand how this interrupt service routine works consider the case where the FlexModel receives the INTI interrupt before the INT2 interrupt The execution sequence proceeds as follows 1 Model samples the INT1 signal asserted and toggles the model_int_signal in the HDL testbench This starts both process 1 and process 2 The model get intr priority command executes and returns the priority as 1 so process 2 exits and process 1 starts executing its commands Simulation time continues to advance as model commands in the interrupt routine are executed Now the model samples the INT2 signal
2. 100 An instance of one model was passed to a command for another model type 101 A command associated with an uninitialized model type was received 102 The model instance name was not mapped to an instance handle with flex_get_inst_handle 103 The system ran out of memory 104 An attempt was made to define an instance for a second time 105 An attempt was made to access an undefined model instance 106 A C program exited with fatal errors Internal Errors Status value range 200 through 299 Contact Customer Support See Getting Help on page 11 56 Synopsys Inc August 28 2001 FlexModel User s Manual Table 3 Status Parameter Error Codes Continued Error Code Description User Errors Status value range 300 through 399 300 Contact Customer Support See Getting Help on page 11 301 Contact Customer Support See Getting Help on page 11 302 Cannot open file to read 303 The flex_clear_queue command was called with an invalid queue initialize number 304 An interrupt command with a priority less than zero was received Interrupt priorities start at zero 305 An attempt was made to access an uninitialized data queue 306 An attempt was made to access an uninitialized command queue 307 An attempt was made to access an uninitialized active command queue 308 An attempt was made to access an un
3. August 28 2001 Synopsys Inc 29 Chapter 2 Using FlexModels FlexModel User s Manual VHDL Example Example using SWIFT template generated by host simulator Ul model generic map FlexModelID gt my inst 1 FlexTimingMode gt FLEX TIMING MODE CYCLE port map model ports Controlling Timing Checks and Delays If you instantiate your FlexModel with timing mode on you can configure timing checks at runtime using the model specific model set timing control commands The general syntax for the model set timing control commands is model set timing control id timing parameter state status The complete syntax for these commands and the supported timing parameter values are listed in the individual FlexModel datasheets The state parameter takes one of two predefined constants e FLEX ENABLE Enables timing for the specified parameter e FLEX DISABLE Disables timing for the specified parameter The following examples show how to use model set timing control commands to configure timing checks for the tms320c6201 fx FlexModel The first command initializes timing with all timing and access delays turned on Then specific commands turn off all setup checks and one specific hold check Verilog Example Timing previously enabled with FlexTimingMode parameter for inst Turn off all setup timing checks tms320c6201 set timing control inst TMS320C6201 SETUP FLEX DISABLE status Tur
4. Defined interrupt function void my_intr_handler Handler routine commands go HERE August 28 2001 Synopsys Inc 63 Chapter 4 FlexModel Command Reference FlexModel User s Manual flex define intr signal Defines an interrupt signal in an HDL or VERA testbench Not used in C Command Mode instead see flex switch intr control on page 82 Syntax flex define intr signal inst handle sig name status Parameters inst handle An integer instance handle returned by the flex get inst handle command sig name A name for the interrupt signal you want to define This is a signal that you define in your testbench status A status of 1 means the command completed successfully A status less than or equal to 0 means the command did not complete successfully Negative integers provide error code information see Table 3 on page 56 Description The flex define intr signal command defines a signal in an HDL or VERA testbench In VHDL the sig name is a signal In Verilog it is a register In both cases the sig name must specify the full path to the signal FlexModels toggle this signal when they detect interrupts thus starting the interrupt service routines tied to that signal Prototypes VHDL procedure flex define intr signal inst handle in integer Sig name in string status out integer Verilog task flex define intr signal input 31 0 inst handle input 8 FLEX
5. Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 5 FlexModel C Testbench Interface flex_incr ADDRESS SMALL ADDRESS DONE Exit the C Testbench exit 0 BRK KKK KK KK KK A KK KK KK KK k KK k Kk kK KK Kk kK k kkk kk kkk kk k INTERRUPT HANDLER Fe KK KK A I KK kCkCK A kCkCK A A A I I I I I KK void my intr function int nValid nPriority nStatus Id used here is the global variable which was assigned when we obtained the instance handle model get intr priority nId amp nValid amp nPriority amp nStatus Use flex fprintf to print the priority flex fprintf stderr Priority DWMn nPriority switch nPriority case 1 model begin intr nId nPriority amp nStatus Place commands HERE for priority 1 Commands must be placed between begin and end intr commands model end intr nId nPriority amp nStatus case 2 model begin intr nId nPriority amp nStatus Place commands HERE for priority 2 Commands must be placed between begin and end intr commands model end intr nId nPriority amp nStatus default printf Unknown priority n August 28 2001 Synopsys Inc 107 Chapter 5 FlexModel C Testbench Interface FlexModel User s Manual 108 Synopsys Inc August 28 2001 FlexModel User s Manual Appendix A Reporting Problems A Reporting Problems Introduction This chapter explains how to run diagnostics create F
6. dir input itype PSAMPLE Define the Intr Signal model define intr signal model test top INTR SIGNAL status fork Interrupt Routine For Interrupt Priority 1 integer priority valid_f status while 1 intrPort S intrSignal model get_intr_priority valid_f priority status if priority printf DETECTED EXCEPTION PRIORITY 1 n model begin intr 1 status Send Commands For Priority 1 here model end intr 1 status Interrupt Routine For Interrupt Priority 2 integer priority valid f status while 1 intrPort SintrSignal model get_intr_priority valid_f priority status if priority printf DETECTED EXCEPTION PRIORITY 2 Mn model begin_intr 2 status Send Commands For Priority 1 here model end intr 2 status join End fork End program my test 38 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 3 FlexModel Command Modes 3 FlexModel Command Modes Introduction If you are using a simulator with a custom FlexModel integration you can issue FlexModel commands from HDL VERA or C Otherwise with the standard SWIFT integration you use Direct C Control For information about configuring FlexModels in your simulator with both standard and custom integrations refer to the Simulator Configuration Guide for Synopsys Models This chapter explains how to use FlexMode
7. Chapter 5 FlexModel C Testbench Interface FlexModel User s Manual flex slice be The flex slice be command copies a bit slice from the fromVec vector to the result vector The be stands for big endian this operator copies from the Oth bit in the fromVec vector starting with the left most bit Truncation if any occurs on the left side If you specify hIdx greater than rhIdx the bits are reversed in the result vector Here s the syntax void flex slice be FLEX VEC result const FLEX VEC fromVec unsigned int lhlIdx unsigned int rhIdx For example FLEX DEFINE data8 8 h0 Big endian void flex slice be data8 b0110100100010111 4 11 no bit reversal data8 b10010001 void flex slice be data8 b0110100100010111 11 4 bit reversal data8 b10001001 flex slice le offset The flex slice le offset command does a little endian copy of a bit slice from fromVec to result starting with the specified offset of resultOffsetIdx bits in the result vector Truncation if any occurs on the left side If you specify a hIdx less than the rhIdx the bits are reversed in the result vector Here s the syntax void flex slice le offset FLEX VEC result unsigned int resultOffsetIdx const FLEX VEC fromVec unsigned int lhIdx unsigned int rhIdx For example FLEX DEFINE rsltl6 16 b1110111111110111 Little endian flex slice le offset rslti6 4 b0110100100010111 11 4 no bit re
8. C Commands Figure 1 FlexModel Structure and Interface Installing FlexModels For FlexModel installation information refer to the SmartModel Library Installation Guide This guide contains instructions for installing the models and associated software For information about supported platforms and simulators refer to the SmartModel Library Supported Simulators and Platforms 14 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 1 FlexModel Overview FlexModel Installation Tree Figure 2 illustrates the organization of FlexModel files installed in an LMC_HOME tree pe doc models smartmodel model fx model fxversion intro pdf platform flexum pdf relnotes pdf slum pdf install pdf model fxversion mdl examples SIC model fxversion so pe j Pd TN model fxversion pdf wd lt vd lt a c yera model_fxversion mmt mode _fxversion td model pkg inc platform model fxversiont modelv model user pkg inc model fxversion tt model tst v model pkg vr model fxversion xrt model fx sim model pkg vhd model pkg h model pkg vrh model user pkg vhd model whd model pkg o model tst vhd model c tst v model fx comp vhd model c tst vhd model fx sim vhd model c commands c Figure 2 FlexModel Structure in LMC HOME Tree FlexModel Licensing FlexModels use FLEXIm floating licenses to authorize their use just like other SmartModels If licensing is not set up refer to the SmartModel Library Installation Guide for
9. Definition The flex synchronize command suspends command execution for the model instance named in the inst handle parameter until sync total number of synchronize commands with matching sync tag parameters have been executed by other models in the testbench Prototypes C void flex synchronize const int inst handle const int sync total const char synoc tag const int sync timeout int status August 28 2001 Synopsys Inc 83 4 f 5 f Chapter 4 FlexModel Command Reference VHDL procedure flex_synchronize inst_handle in integer sync_total in integer sync_tag in string sync_timeout in integer status out integer Verilog task flex_synchronize input 31 0 inst_handle input 31 0 sync_total input 8 FLEX CHARMAXCNT 1 sync tag input 31 1 sync timeout output 31 0 status VERA task synchronize integer sync total string sync tag integer sync timeout var integer status Examples In the following example the flex synchronize in command 4 causes command execution to halt for instance 1 Command execution resumes when a matching sync label sync1 has been identified In this case command 5 carries the identical sync label sync1 Command 6 starts after commands 1 2 and 3 have been completed FLEX WAIT F is a predefined constant For more information refer to The wait mode Parameter on page 56 VHDL Example arm tdmi read req
10. Ig char ModelId idl flex get inst handle ModellId amp Id amp status model write Id Addr Data amp status Error issuing model command before end of initialization Compiling an External C File The compile line you use differs based on your platform Note that these examples include creation of a working directory workdir and running flexm setup a On HP UX you need to link in the LBSD library as shown in the following example mkdir workdir flexm setup dir workdir model fx bin c89 o executable name your C file c workdir src C hp700 model pkg o IMC HOME lib hp700 1ib flexmodel pkg o ISLMC HOME sim C src Iworkdir src C lBSD oe oe August 28 2001 Synopsys Inc 45 Chapter 3 FlexModel Command Modes FlexModel User s Manual 46 On Solaris you need to link in the Isocket library as shown in the following example oo mkdir workdir flexm setup dir workdir model fx cc o executable name your C file c workdir src C solaris model pkg o LMC HOME lib sun4Solaris lib flexmodel pkg o ISLMC HOME sim C src Iworkdir src C lsocket oo oo AIX oo mkdir workdir flexm setup dir workdir model fx bin cc o executable name your C file c workdir src C ibmrs model pkg o LMC HOME lib ibmrs lib flexmodel pkg o Iworkdir src C IS LMC HOME sim C src 1dl oo oo Linux oo mkdir workdir flexm setup dir workdir model fx e
11. SLMC HOME models model fx model fxversion src C 2 Initialize the C program using the flex get inst handle and flex start program commands as shown in the following example main int status Id char ModelID idl Must be same as in VHDL testbench flex get inst handle ModelId amp Id amp status Id is the returned integer handle flex start program amp status End of initialization sequence This next example adds a definition for an interrupt function This is in the C testbench void my intr function main int status Id char ModelId idl flex get inst handle ModelID amp Id amp status Exiting initialization phase 44 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 3 FlexModel Command Modes flex start program amp status Registering my intr function next flex define intr function Id my intr function amp status Common Errors to Avoid Here s an example of what not to do You cannot issue a flex start program command until you obtain a model instance handle using the flex get inst handle command main int status Id char ModelId idl flex start program amp status Error flex start program before getting instance handles Another common error is to issue model commands before the initialization sequence is complete as shown in the following example main int status
12. flex define intr signal 64 flex get cmd status 66 flex get coupling mode 68 flex get inst handle 69 flex print msg 73 flex run program 75 flex set coupling mode 77 flex start program 81 flex switch intr control 82 flex synchronize 83 flex wait 85 result identifiers 55 Comments reporting doc suggestions 12 Compiling external C program 45 Compiling C files AIX 46 HP UX 45 Intel NT 47 Linux 46 NT 46 Solaris 46 Synopsys Inc 115 Index Constants FLEX_ALL_QUEUES 61 FLEX_CMD_QUEUE 61 FLEX_COUPLED_MODE 23 FLEX_DEFINE 91 FLEX_DISABLE 30 FLEX_ENABLE 30 FLEX_INT 91 FLEX_RSLT_QUEUE 61 FLEX_TIMING_MODE_CYCLE 29 FLEX_TIMING_MODE_ON 28 FLEX_UNCOUPLED_MODE 23 FLEX_VEC 44 91 FLEX_VEC_CONST 44 FLEX_WAIT_F 56 FLEX_WAIT_T 56 MAX 29 MIN 29 TYP 29 Controlling command flow 20 Conventions command syntax 11 system generated text 10 UNIX prompt 10 user input 10 variables 11 D DelayRange 29 Direct C Control compiling C files 45 restrictions 13 Documentation online 15 E Errors synchronize command 28 timeout 28 Examples branching on result 25 C Command Mode errors 45 C Command Mode example 103 C Command Mode interrupt 35 116 Synopsys Inc FlexModel User s Manual C initialization 44 logging files 111 message logging 113 non pipelined transfers 24 stimulus logging 112 switching to C program 47 Verilog cycle based mode 29 Verilog timing 29 Verilog timing setup 30 VHDL command mode 39
13. top a bl b1 amp status flex wait on node top b 3 bl bl amp status flex wait on node top b 3 0 D1010 b1111 amp status Flex wait on node top b 31 0 h0000a0a0 hO0OO00ffff amp status VHDL Scirocco Flex wait on node top a bl bi amp status lex wait on node top b 3 b1 b1 amp status ex wait on node top b 3 downto 0 b1010 b1111 amp status lex wait on node top b 31 downto 0 h0000a0a0 hOO000ffff amp status h Fh 1 h 88 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 5 FlexModel C Testbench Interface o FlexModel C Testbench Interface Introduction This chapter explains how to define and manipulate FLEX VEC vectors using the FlexModel C functions and operators provided in ANSI compliant include files This information is organized in the following sections e Creating FLEX VEC Vectors on page 90 e FLEX VEC Lexical Rules on page 91 e FLEX VEC Error Handling on page 92 e FLEX VEC Command Descriptions on page 93 e C Testbench Example on page 103 What Are FLEX VEC Vectors Before you can use the C versions of the model specific commands documented in the individual FlexModel datasheets you must define the required variables or vectors using the FLEX DEFINE command described in this chapter For example model read commands typically require you to sp
14. 2001 FlexModel User s Manual Chapter 5 FlexModel C Testbench Interface int flex lt const FLEX VEC vecl const FLEX VEC vec2 vecl lt vec2 flex Ite The flex lte command returns true if vec is less than or equal to vec2 For example int flex lte const FLEX VEC vecl const FLEX VEC vec2 vecl lt vec2 flex gt The flex gt command returns true if vec is greater than vec2 For example int flex gt const FLEX VEC veci const FLEX VEC vec2 vecl gt vec2 flex gte The flex gte command returns true if vec is greater than or equal to vec2 For example int flex gte const FLEX VEC veci const FLEX VEC vec2 vecl gt vec2 flex slice le The flex slice le command copies a bit slice from the fromVec vector to the result vector The le stands for little endian this operator copies from the Oth bit in the fromVec vector starting with the right most bit Note that truncation if any still occurs on the left side If you specify a hIdx less than the rhIdx the bits are reversed in the result vector Syntax void flex slice le FLEX VEC result const FLEX VEC fromVec unsigned int lhlIdx unsigned int rhIdx For example FLEX DEFINE data8 8 h0 Little endian void flex slice le data8 b0110100100010111 11 4 no bit reversal data8 b10010001 void flex slice le data8 b0110100100010111 4 11 bit reversal data8 b10001001 August 28 2001 Synopsys Inc 95
15. 34 56 111 August 28 2001 Index FLEX WAIT T 33 56 111 flex warnings 92 flex xnor 99 flex xor 99 FLEXIm license 15 flexm setup 18 FlexModel block diagram 14 Command Core 14 39 command interface 17 39 53 controlling command flow 20 features 13 initialization 19 licensing 15 limitations 15 structure 15 flexmodel pkg h 44 FlexModels Command Core 41 Functions 63 Functions C mode flex add 94 flex and 99 flex assign 93 flex assign int 93 flex assign int array 93 flex assign int list 03 flex decr 94 flex define 90 flex eq 94 flex errors 92 flex fprintf 102 flex gt 95 flex gte 95 flex incr 94 flex iprintf 102 flex lrot 98 flex Ishift 97 flex 1t 95 flex lte 95 flex nand 99 flex ne 94 flex nor 99 flex not 98 flex notes 92 Synopsys Inc 117 Index flex_or 98 flex_rrot 98 flex_rshift 97 flex_slice_be 96 flex_slice_be_offset 97 flex_slice_le 95 flex_slice_le_offset 96 flex_sprintf 103 flex_sub 94 flex_to_int 100 flex_to_int_array 100 flex_to_int_list 101 FLEX_VEC 90 flex_warnings 92 flex_xnor 99 flex_xor 99 H HDL Command Mode 20 39 HDL Control Command Core timing 41 HDL C mechanism 41 multiple state commands 42 timing diagram 42 Header files 44 Help how to get 11 HP UX compiling C files 45 I Initialization 19 inst_handle 27 55 69 Install Process 14 Integers in C and HDL 44 Interrupt Commands and FLEX_WAIT_F 34 and FLEX_WAIT_T 33 model_begin_intr 34 model_end_intr 34 mo
16. C void flex print msg const int inst handle const char text int status VHDL procedure flex print msg inst handle in integer text in string status out integer Verilog task flex print msg input 31 0 inst handle input 8 FLEX CHARMAXCNT 1 text output 31 0 status August 28 2001 Synopsys Inc 73 Chapter 4 FlexModel Command Reference FlexModel User s Manual VERA task print msg string text var integer status Examples The following examples produce output formatted as shown below where time is the current simulation time time ns INSTANCE znst name NOTE This is a test VHDL Example flex_print_msg inst This is a test status Verilog Example flex print msg inst 4 This is a test status C Example flex print msg inst 4 This is a test amp status VERA Example model_object print_msg This is a test status 74 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 4 FlexModel Command Reference flex_run_program Transfers control to a C program Used in HDL and VERA command modes Syntax flex run program filename status Parameters filename The filename of a compiled C program must be enclosed in quotation marks status A status of 1 means the command completed successfully A status less than or equal to 0 means the command did not complete successfully Negative integers
17. CHARMAXCNT 1 sig name output 31 0 status 64 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 4 FlexModel Command Reference VERA task define_intr_signal string sig_name var integer status Examples VHDL Example architecture Signal int_signal std_logic begin process flex define intr signal inst top int signal status Verilog Example module example reg int signal initial begin flex define intr signal inst top int signal NERA Example model object define intr signal top int signal status August 28 2001 Synopsys Inc status 65 Chapter 4 FlexModel Command Reference FlexModel User s Manual flex_get_cmd_status Checks the status of a command in the model s queue Used in all command modes Syntax flex_get_cmd_status inst_handle cmd_tag valid_f status Parameters inst_handle An integer instance handle returned by the flex_get_inst_handle command cmd_tag An integer that identifies the command in the command queue This is usually the returned status of the command valid_f A boolean returned value 1 valid 0 invalid that indicates whether the specified cmd_tag represents a valid command in the queue status A status of 1 means the command completed successfully A status less than or equal to 0 means the command did not complete successfully Negative integers provide error code information see Table 3 on page 56 Des
18. DEFINE at the top of the current scope before any functions are called Syntax FLEX DEFINE vecName vecSize initVal Example The following example creates a FLEX VEC called addr with space for 64 bits FLEX DEFINE addr 64 haaaabbbbccccdddd FLEX VEC SIZEOF To dynamically create FLEX VEC vectors use the FLEX VEC SIZEOF macro You can calculate the bitcnt on the fly based on other operations in your C testbench The example that follows contains the function declaration and assignment in one line of code which creates a FLEX VEC with a local scope If you want the FLEX VEC to have a global scope put your function declaration outside of the subroutine where you make the variable assignment Syntax FLEX VEC SIZEOF int bitcnt Example FLEX VEC dynVec64 FLEX VEC malloc FLEX VEC SIZEOF 64 90 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 5 FlexModel C Testbench Interface FLEX VEC Lexical Rules The following lexical and semantic rules apply to FLEX_VEC vectors e Vector values must be either string literals or objects of type FLEX_VEC created with FLEX DEFINE e Values are truncated on the left side to fit the size of the receiving variable For example if you assign haf to a 4 bit wide vector the result is hf e VHDL 9 state values are mapped to 4 state values as shown in Table 9 Therefore FLEX VEC vectors do not represent signal strength levels Table 9 VHDL 9 St
19. INTs i0 0x08889999 i2 Ox0aaabbbb i3 0Ox00cccddd i4 OxOeeeffff count 4 Reset FLEX INTs i0 il i2 i3 0 count 2 flex to int list datal128 amp count amp il amp i2 amp i3 amp i4 Issues a warning about only reading the 2 rightmost FLEX INTs while the actual vector is 4 FLEX INTs wide i0 Ox00cccddd il OxOeeeffff i2 0 i3 0 count 2 flex_iprintf The flex_iprintf command works just like the ANSI C printf utility You can use flex_iprintf to print a string to the simulator transcript For example void flex iprintf int instHandle const char formatStr The instHandle must be a valid model instance handle obtained with the flex get inst handle command The maximum string length is 255 characters flex fprintf The flex fprintf command works just like the ANSI C fprintf utility You can use flex fprintf to print a string to a file For example void flex fprintf FILE fp const char formatStr In this example fp must point to a FILE open for output The maximum string length is 255 characters 102 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 5 FlexModel C Testbench Interface flex sprintf The flex sprintf command works just like the ANSI C sprintf utility You can use flex sprintf to print a string to a buffer For example void flex sprintf char bu
20. RRS ERE EES P Aa Ede 49 Examples with Top level Testbenches ood nae bb treek iad eee dn 50 Accessing de Current Error StAtUs cca oe eek oo ones ERR TEFEEE oH es 31 Flex Model Logging from the VERA Class lt ccsveuet caused svewevawnwe 52 Chapter 4 FlexModel Command Reference 610 essen sccecus eee RR ER 53 WOON 4idiacd sodo i 1p dm ae aoa n e sede dedo ERR Aro Lac do 53 Model Specific and Global Commands 22 05 464s0s4sbsaasdeacdeesesarvns 53 About the NS be end owt chess Hk boo neds Shes bidd ede ERR 54 Bus and Zora C vele Commands couessexsekaxrc 9 emnes REA n ha 54 The msi handie Paranict r oasc euetasa den Chess Ea t P CE ESER 54 The req and rslt Command Suffixes 444 5 404 ese ee eewribaeecavivnenss 25 Command Result Identifiers deesse ds ska end d SAMEERA ERE EHE 55 The wait mode Parameter 6 cn ck ce cede sdun eee steer eich eee arden ewes 56 Th status PT Luesexdesbtebexebet dqeteobexeviei ts ddbeccbeses 56 4 Synopsys Inc August 28 2001 FlexModel User s Manual Contents Command Syntax Differences in VERA Command Mode 58 Global FlexModel Commands 4a id ipae e CEP ER ER hs 59 Global FlexModel Command Descriptions 2 c2 cs00s lt aess RR RR ERR 61 Ix SEM UES eeeraieer HEDHEOHHIRRERE E ERE AO Hop EE LEER XAR 61 flex define Witt TUNCHION Loueoucesoesas Er ERE CR RARO R eR 63 ilex define imir signal Loue esu DURAS GORVR EORR CHLACRORECR KV ROSES RC A 64 Hx pet cmd SAUS ailixeqxA MIp ered aera a MICE EC EH
21. The command stream for il initial begin command flow for il goes here il mpc740 idle and so forth for il end The command stream for i2 initial begin command flow for i2 goes here i2 mpc740 idle and so forth for i2 end 3 On the simulator invocation line add the multi instance specification to your invocation Tdefine tflex multi inst Controlling the FlexModel Command Flow You can control the flow of FlexModel commands in several ways as explained in the following sections e Resetting the Simulation on page 21 e Transferring Control to a C Testbench on page 21 e Using Multiple Command Streams in a C Testbench on page 21 e Using Uncoupled Mode in a C Testbench on page 22 e Burst Transfers on page 24 e Non pipelined Bus Operations on page 24 e Pipelined Bus Operations on page 25 e Synchronizing the Command Flow on page 27 20 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 2 Using FlexModels Resetting the Simulation The ability to reset a simulation to an initial state without re invoking the simulator can save considerable time Reset is also important for what if simulation runs FlexModels support reset returning to the state when the simulator was initially invoked Attention Reset is not currently supported on NT Also when using FlexModels on Verilog XL with model logging enabled some FlexModels may not reset after th
22. The entire string must be in uppercase MODEL_INSTANCE LOG_MODE where MODEL is the model name without the _ fx INSTANCE is the instance name specified in the FlexModelld SWIFT parameter Typical FlexModel instantiations looks like the following examples Note the value of the FlexModelld generic or defparam that is what you use in the INSTNAME portion of the model logging file name 110 Synopsys Inc August 28 2001 FlexModel User s Manual Appendix A Reporting Problems VHDL U1 MPC860 generic map FlexModelld gt Model_id_1 FlexTimingMode gt FLEX TIMING MODE OFF Timing Version gt MPC860 25 DelayRange gt MAX VERILOG defparam ul FlexModelld Model id 1 For this example the logging file name would be MPC860 MODEL ID 1 LOG MODE 1 Rerun your simulation so that the models can record their activity in the following log files O pin events pin model_instance log o trace messages msg model_instance log o model commands cmd model_instance log For example assuming model logging is enabled for an mpc860 fx model instance with a FlexModelld of Model Id 1 the model generates the following files o emd mpc860 Model Id 1 log o pin mpc860 Model Id 1 log o msg mpc860 Model Id 1 log Command Logging Model commands are logged as shown in the following example CE150 mpc860 idle inst 1 FLEX WAIT F status This indicates that at simulation time 150
23. VHDL Example C Example VERA Example FLEX CMD QUEUE flex clear queue inst FLEX CMD QUEUE flex clear queue inst FLEX CMD QUEUE status status amp status model object clear queue FLEX CMD QUEUE status Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 4 FlexModel Command Reference flex_define_intr_function Defines a C interrupt function Used only in C Command Mode Syntax flex_define_intr_function inst_handle my_function status Parameters inst_handle The model instance for which interrupts are to be controlled from the C testbench my_function A pointer to the C interrupt function This function must return void and does not take any arguments status A status of 1 means the command completed successfully A status less than or equal to 0 means the command did not complete successfully Description The flex define intr function command specifies to the Command Core which function to call if an interrupt occurs This command only works in C Command Mode For HDL Command Mode use the equivalent flex define intr signal command documented on page 64 Prototype C void flex define intr function const int inst handle FLEX FUNC my function int status Example C Example Function prototype void my intr handler main int status flex define intr function id my intr handler amp status
24. VHDL cycle based mode 30 VHDL interrupt 33 VHDL timing 29 VHDL timing setup 30 wait_mode 26 F FLEX Commands command descriptions 61 command summary 59 flex_add 94 FLEX_ALL_QUEUES 61 flex_and 99 flex_assign 93 flex_assign_int 93 flex_assign_int_array 93 flex_assign_int_list 93 flex_change_setup 23 flex_clear_queue 61 FLEX_CMD_QUEUE 61 FLEX_COUPLED_MODE 23 flex_decr 94 FLEX_DEFINE 91 flex_define 90 flex_define_intr_function 35 82 flex_define_intr_signal 33 63 64 FLEX_DISABLE 30 FLEX_ENABLE 30 flex_eq 94 flex_errors 92 flex_fprintf 102 flex_get_cmd_status 66 flex_get_coupling_mode 68 August 28 2001 FlexModel User s Manual flex_get_inst_handle 69 flex_gt 95 flex_gte 95 flex_incr 94 FLEX_INT 91 flex_iprintf 102 flex_lrot 98 flex_Ishift 97 flex_It 95 flex lte 95 flex nand 99 flex ne 94 flex nor 99 flex not 98 flex notes 92 flex or 98 flex print msg 73 flex rrot 98 flex rshift 97 FLEX RSLT QUEUE 61 flex run program 21 25 40 75 flex set coupling mode 77 flex slice be 96 flex slice be offset 97 flex slice le 95 flex slice le offset 96 flex sprintf 103 flex start program 43 44 81 flex sub 94 flex switch intr control 82 flex synchronize 27 40 83 FLEX TIMING MODE CYCLE 29 FLEX TIMING MODE ON 28 flex to int 100 flex to int array 100 flex to int list 101 FLEX UNCOUPLED MODE 23 FLEX VEC 44 90 91 FLEX VEC CONST 44 flex vec sizeof 90 flex wait 33 85 FLEX WAIT F
25. WAIT F tag3 result 3 model read rslt modl1 x DEADBEF1 tag3 datal stat result 2 model read rslt modl1 x DEADBEFO tag2 data0 stat result 1 model read rslt modl1 x DEADBEEF tagl data stat In this example the three read requests complete in order but the read results commands are in reverse order The model waits until the result 3 command completes which depends on completion of read 3 before proceeding to the result 2 and result 1 commands thus producing the pipeline effect Synchronizing the Command Flow To coordinate the behavior of multiple FlexModels in your testbench use the flex synchronize command Do not use multiple HDL command streams to control a single FlexModel instance This produces unpredictable model behavior The flex synchronize command suspends operations in the model instance identified by the inst handle parameter until the number of instances specified in the num instance parameter execute flex synchronize commands with matching sync label strings For example if a FlexModel issues the following command it suspends all operations until two other model instances execute flex synchronize commands with a matching sync label of sync1 flex synchronize inst 3 syncl timeout status All three models simultaneously execute their next commands one clock cycle after the third model executes this command A FlexModel holding for a synchronizatio
26. after the specified number of clock cycles have elapsed Prototype C void flex wait const int clock cycles int status Example C Example main int nstatus flex wait 2 amp nstatus Wait for 2 clock cycles model write id addr data amp status Seen 3 clock cycles later The following diagram shows the timing cycles for this example 1 clk 2 clk flex_wait begins write posted write begins August 28 2001 Synopsys Inc 85 Chapter 4 FlexModel Command Reference flex_wait_on_node Suspends command execution in C program until the specified design net is assigned the expected value Used only in C Command Mode Syntax flex_wait_on_node path expected_value mask status Parameters path FlexModel User s Manual The hierarchical path of the specified net if the net is a bus or part of a bus it needs to be explicitly specified with a range for example b 31 0 If the range is not specified b defaults to b 0 The path parameter depends upon the simulator you are using Examples of the syntax are given in Table 8 where nets a and b are declared in the testbench which has a top level block called top The command can access any net in the design provided that the full hierarchical path is specified Table 8 Syntax Examples for the path Parameter Simulator Single Bit Form Bus or Part of Bus Form Verilog Simulators VCS top a
27. command rotates the vec vector shiftCnt bits to the left and puts the result in result The rotation point is determined by the size of the result vector Here is the syntax result left rotate vec by shiftCnt void flex lrot FLEX VEC result const FLEX VEC vec unsigned int shiftCnt For example FLEX DEFINE rslt8 8 h0 flex lrot rslt8 b101100 4 left rotate a 6 bit vector into rslt8 rslt8 b11000010 flex not The flex not command does a bitwise not operation on vec and puts the result in result Here is the syntax result vec void flex not FLEX VEC result const FLEX VEC vec flex or The flex or command does a bitwise or operation on vec and vec2 and puts the result in result Here is the syntax result vecl vec2 void flex or FLEX VEC result const FLEX VEC vecl const FLEX VEC vec2 98 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 5 FlexModel C Testbench Interface flex and The flex and command does a bitwise and operation on vec and vec2 and puts the result in result Here is the syntax result vecl amp vec2 void flex and FLEX VEC result const FLEX VEC vecli const FLEX VEC vec2 flex nor The flex nor command does a bitwise nor operation on vec and vec2 and puts the result in result Here is the syntax result vecl vec2 void flex nor FLEX VEC result const FLEX VEC vecli const FLEX VEC vec2 flex nand The flex
28. in the design flex print msg All Prints a message flex_run_program HDL VERA Switches control to a compiled C program flex set coupling mode C Sets the coupling mode for the model flex set value C Sets the single bit value of a specified net in the design flex start program C Signals the Command Core that the testbench is done getting model instance handles and is beginning to send model commands flex_switch_intr_control C Switches model interrupt control to HDL flex_synchronize All Synchronizes the model with other models in the testbench flex_wait C Causes the model to wait for a specified number of clock cycles August 28 2001 Synopsys Inc 59 Chapter 4 FlexModel Command Reference FlexModel User s Manual Table 4 Global FlexModel Command Summary Continued Command Command Name Mode Description flex wait on node C Suspends command execution in C program until the specified design net is assigned the expected value 60 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 4 FlexModel Command Reference Global FlexModel Command Descriptions The following pages describe the global FlexModel commands Model specific commands are described in the individual FlexModel datasheets flex_clear_queue Clear the command queue Used in all command modes Syntax flex clear queue inst handle queue select status Parameters inst handle An integer instance
29. integer begin Start Read model read req instance address readType FLEX WAIT T status AE OK if status gt 0 then Get Read result tag not needed model read rslt instance address 0 result status end if end 24 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 2 Using FlexModels The following example shows another command sequence that branches according to the result of the returned data model read req inst x 00000060 x O FLEX WAIT T status model read rslt inst x 00000060 0 data status if status 1 and data 31 downto 0 x 33334444 then model write inst mem write x AOOO000FF x 1DE4543C FLEX WAIT F status else assert FALSE report WRONG DATA READ severity NOTE end if There is a minimum delay of one clock cycle between the completion of a request command and the completion of a corresponding result command You must precede a result command with a request command Pipelined Bus Operations Bus cycle pipelining occurs when multiple bus operations overlap Because FlexModels typically divide bus operations between request and result phases or commands you can pipeline multiple request commands before the result command from the first request is complete By preloading the model command queue with pipelined bus operations you can avoid dead cycles and more closely model the behavior of devices that support pipelining You can then retri
30. interrupt signal in a top level Verilog testbench include vera defines vrh include flexmodel pkg vrh include model pkg vrh program my test Create an instance of the model class ModelFx model new modeliInstName ul CLK Define the Intr Signal NOTE here INTR_SIGNAL is the name of a reg in the top level verilog testbench and we pass the full path to the interrupt signal model define intr signal model test top INTR SIGNAL status Monitoring the Interrupt Signal The following example illustrates one way to monitor the interrupt signal in a top level VHDL testbench For other methods of determining when the interrupt signal has been toggled in the Verilog or VHDL testbench and for more information on VERA syntax refer to the Vera Verification System User s Manual include vera defines vrh include flexmodel pkg vrh include model pkg vrh Create A VERA Port data type port my port intrSignal program my test Create an instance of the model class August 28 2001 Synopsys Inc 37 Chapter 2 Using FlexModels FlexModel User s Manual ModelFx model new modellInstName ul CLK Create a Variable of type my_port Give it a null bind my_port intrPort new Make a connection to the interrupt signal in the top level VHDL testbench signal_connect intrPort SintrSignal model test top INTR SIGNAL
31. nStatus i int tagl tag2 August 28 2001 Synopsys Inc 103 Chapter 5 FlexModel C Testbench Interface FlexModel User s Manual 104 char sInstName 1 Define four FLEX_VEC type arrays and initialize them with a NULL vector these vectors have actual storage and will be used to get the returned results from result commands LEX_DEFINE LEX_DEFINE LEX_DEFINE ret_data MODEL_DATABUS_WIDTH FLEX_NULL_VEC act data MODEL DATABUS WIDTH FLEX_NULL_ 7 gs Hj F E F F LEX_DEFINE I VEC ADDRESS MODEL ADDRBUS WIDTH FLEX NULL VEC DATA MODEL DATABUS WIDTH FLEX NULL VEC Defining some FLEX VECs One very important point to note here is that since a FLEX DEFINE has not been used there is no actual storage for these vectors and they can ONLY be used as input values and not for result values const FLEX VEC BADADDR h000ff00 const FLEX VEC ADDR INCR h4 Increment address 4 bytes const FLEX VEC DATA INCR b1 Increment data 1 Get the instance handle flex get ins t handle sInstName amp nId amp nStatus Issue a start program indicating end of initialization flex start program amp nStatus BRK KK IK I I I KKK KKK KKK KK K KK KK K Ck KC kK k k Kk KC KC Kk KK CK k kk kk k k End of Initialization Now commands can be s
32. read req inst X 00000002 X 0 FLEX WAIT F status COMMAND 3 model read req inst X 00000000 X 0 FLEX WAIT T status model read rslt inst X 00000004 0 datal status model read rslt inst X 00000004 0 data2 status model read rslt inst X 00000000 0 data3 status Commands 1 2 and 3 are loaded into the model queue immediately because the first two commands have wait mode parameters set to false FLEX WAIT F Commands following 3 are not loaded right away because Command 3 has a wait mode parameter set to true FLEX WAIT T No further commands are loaded until Command 3 completes When Command 3 completes the results commands retrieve the results from the three pipelined read requests Pipelining With Delayed Results Checking Supposed you want to pipeline multiple read commands and check results in a different order You can simply invert the order of the result commands as shown in the following example 26 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 2 Using FlexModels Model Commands are model read req inst address wait status model read rslt inst address result status Assume no pipeline reordering read 1 model_read_req modl x DEADBEEF FLEX WAIT F tagl read 2 model read req modl x DEADBEFO FLEX WAIT F tag2 read 3 model read req modl x DEADBEF1 FLEX
33. session After the initialization sequence is complete the model checks the value of the flex change setup variable before executing each command August 28 2001 Synopsys Inc 23 Chapter 2 Using FlexModels FlexModel User s Manual and changes the mode of operation accordingly Here is an example that uses the flex_change_setup global variable to change to uncoupled mode in between bus cycles for the mpc860_fx model mpc860 read idl address tr attr FLEX WAIT F amp status flex change setup FLEX UNCOUPLED MODE set from the debugger mpc860 write idl address tr attr data FLEX WAIT F amp status gt Note The flex change setup command may be used to interactively change other simulation settings in the future if the need arises Burst Transfers Burst transfers are multiple data transfers caused by a single bus command Like the devices they model some FlexModels support burst transfers check the FlexModel datasheets for supported burst transfer commands and how to use them Non pipelined Bus Operations Use non pipelined bus operations when you want to branch the control program based on the result returned by the model This means issuing a model result command right after a paired model request command as shown in the following example procedure my read instance in integer address in BIT VECTOR 0 to 31 readType in natural result out BIT VECTOR 0 to 31 is variable stat
34. timeformat ns 1 0 pO il pl i0 p6 OZ EZ p10 bz rz t 60 p6 OZ rZ 112 Synopsys Inc August 28 2001 FlexModel User s Manual Appendix A Reporting Problems po7 b ritiri rt Pet ot Ts tt es ei et FD Notice that for input pins only the value of the pin is recorded 1 For output pins both the value that the model is driving onto the pin 0 and the resolved value r are recorded For bidirectional pins both the value the model is driving b and the resolved value r are recorded Thus contentions for output and bidirectional pins can be caught Message Logging Here is an example of a message log file 420 450 450 4 4 uuu 180 180 480 510 N 540 54 570 N 600 N 600 N Z Z Z z Ce Z ANNANANANNNNNNN INSTANCE 1 Idle State INSTANCE 1 arm7tdmi write 00000F0C INSTANCE 1 T1 State INSTANCE 1 T2 State INSTANCE 1 Writing Data Address 00000F0C Size 4 Data 98765432 INSTANCE 1 Idle State INSTANCE 1 arm7tdmi read req 00000F00 INSTANCE 1 T1 State INSTANCE 1 T2 State INSTANCE 1 Latching Data Address 00000F00 Size 4 Data 3C3C3C3C Sending the Log Files to Customer Support After you rerun your simulation to generate the model log files tar those files up along with the swiftcheck
35. top b 31 0 top b 15 8 top b 0 top b 5 top b uses single bit b 0 only MTIVLOG top a top b 31 0 top b 15 8 top b 0 top b 5 top b uses single bit b 0 only VXL top a Not supported VHDL Simulators MTI top a Not supported 86 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 4 FlexModel Command Reference Table 8 Syntax Examples for the path Parameter Simulator Single Bit Form Bus or Part of Bus Form SCIROCCO top a top b 31 downto 0 top b 0 to 31 top b 18 downto 8 top b 8 to 15 top b 0 top b 5 top b uses single bit b 0 only VSS CYCLONE Not supported Not supported expected_value The expected_value on a net specified by path The expected_value should match the width of the signal specified by path mask Any register value specifying the mask for expected_value A zero in the mask indicates a don t care The vector size of the mask should match the expected value status A status of less than or equal to 0 means that the command did not complete successfully A status of 1 indicates that the socket connection between the C testbench and the command core was successfully established It does not however indicate the successful completion of the command It is possible for the command to fail if the wrong path has been specified and the status will still be 1 Look for error messages in the simulation transcript when you first use th
36. u c status If you specify the c option default behavior the C testbench starts model commands in coupled mode If you specify the u option the C testbench starts model commands in uncoupled mode Other options are ignored gt Note The u switch is useful only if you want to be in uncoupled mode for a single command stream This is not currently needed for FlexModels but will enable potential future enhancements 2 You can also use global FlexModel commands in your C testbench to set and get the coupling mode using the following syntax flex set coupling mode int instance int coupling mode int status flex get coupling mode int instance int amp coupling mode int status where coupling mode is one of these two constants o FLEX UNCOUPLED MODE sets mode to uncoupled o FLEX FULLY COUPLED MODE sets mode to coupled Here are some usage examples flex set coupling mode mpc8260 instl FLEX UNCOUPLED MODE amp status flex get coupling mode mpc8260 instl amp coupling mode amp status 3 You can also use the flex change setup global variable in your C testbench to enable or disable uncoupled mode This can be handy for interactive use with a C debugger int flex change setup Set the flex change setup variable to FLEX UNCOUPLED MODE or FLEX FULLY COUPLED MODE depending on the desired mode of operation You can use this global variable to interactively modify the simulation setup from within the debugger
37. 2001 Synopsys Inc 35 Chapter 2 Using FlexModels FlexModel User s Manual 3 The first command in the interrupt function must be a model get intr priority command This command returns a positive integer higher numbers indicate higher interrupt priorities You can decode this priority using case statements and then begin the processing appropriate for that interrupt priority level 4 Enclose all model commands for a particular model instance and interrupt priority in between paired model begin intr and model end intr commands with the same model instance handle and interrupt priority Example C Interrupt Routine For an extensive example of a C interrupt routine refer to C Testbench Example on page 103 The following example is smaller in scope but illustrates the basic structure required include flexmodel pkg h include model pkg h Interrupt Function Prototype void my intr handler int id NOTE id is global so it is visible in the interrupt routine main int status char Inst1 Begin Initialization Sequence flex get inst handle Instl amp id amp status flex start program amp status Register interrupt function with command core only command has been executed will the function be call interrupt occurs flex define intr function id my intr handler amp status i amp Continue model generic commands Verify C testbench is still running while HDL interrupts
38. E CEN RAO Ea d 66 Hos sot COUN NOES 660k xwed Erne eadenee dees Re ERREREYE X ERES 68 Hox od inst Dandie 5 ing ces ce bude edad dbs os bie eweGGRDS RERO ROCA S EM 69 ae a a ee epi a ee ee ee RR 71 Hex DUM IE oie oak bb Fa OR E AERE Ed dc dA A EES 73 iex m progra opservi os AY EEN oS OSS 69 cR db oe REER 75 Hx set coupling mod 9445s ech ee ein tines eater d EX Qd Cd wd ded TI i E E rrr Tr 78 ties sun I sauosaads RE kk CHARS LES REA EEN SEER OR EERE RRS 81 ix swith DUI OOMUDD iloskRaydeXxemEFersekid deddqy d EReqietddm bad EXes 82 ee Ue ee ee PROMESA ae 83 HE WEIL 240 ee ohne Edd eU Mu us RHE OE WA IO e dU MO dod E Ka a arde 85 D ABO oosskLERGSAAAMCRSEARAEEGEAASE HA REPAS EIE RAEAESeTUE 86 Chapter 5 FlexModel C Testbeneh Interface 5e ceuesxcutbckkntkkkkkkkbEkrrmtuk e 89 i ogg ee de edid qoas ded n dod a Pa dedi URGERE dee d dido e 89 Wit Att FLEX VEC VERON dcos kdexenxskdech d ER Eiche d RR d RP d dr a 89 Crame PLEX VEC VEOIUIS 4555 60s 654 65 4 S0 Sb SSO HSS SUE ESE SK RS 90 PLEX VEC Lexical Rules ii bn bn Reda kd ed C PAROLE dd 91 FLEX VEL Emor Handing Louauksd Edcka when KDHE EECA nE EE eed 92 FLEX VEC Command Descriptions cusdeso rie bRbpeXP REY RE YEAR ER ea sees 93 C Testb ench Example dua suseesn aad aka SER EC OI drn RUARO 103 Appendix A Reporting Problems ura ah Oed dE REC ERCEREUR RE AREE PES PV iE 109 dud c 45 bn eae TET TE TIT TT TO TUTTO T DET TT 109 Model versions an HIHO auae CEA Wa RR Cala al de REC PR 109 Running FlexM
39. FlexModel Timing FlexModels come with standard component based timing files just like regular SmartModels There is a timing file for each model that can accommodate multiple timing versions By selecting different timing versions for different instances of the same model you can have these instances behave differently in the design In addition to these standard timing files you can create custom component based timing files using the SmartModel user defined timing UDT process UDT is possible because a model s timing file is loaded at simulation startup For more information on UDT refer to the SmartModel Library User s Manual When you run a FlexModel in timing mode in general you are enabling propagation delays access delays and timing checks Bear in mind that FlexModels run up to 40 percent faster in function only mode so you may want to set timing mode on only for later simulation runs after functional verification is complete Selecting Function only or Timing Model By default FlexModels behave as function only models To enable timing mode for a FlexModel set the FlexTimingMode SWIFT parameter to FLEX_TIMING_MODE_ON prepend a backtick for Verilog If you are using Direct C Control set this parameter to 0 for timing mode off or 1 for timing mode on 28 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 2 Using FlexModels With timing mode on you can choose the desired timing version for the model by
40. LEX WAIT F status flex print msg inst This is a read req test status assert false report end of commands severity NOTE wait end process CMD STREAM Do not use multiple HDL command streams to control a single FlexModel instance this produces unpredictable model behavior In HDL Command Mode FlexModel commands are executed as procedure calls VHDL or task calls Verilog at the testbench level The testbench continues issuing commands to the models until it encounters one of the following e A result command or a command containing a wait mode parameter set to true This causes the testbench to wait for the model to complete the command before issuing the next command e Aflex run program command This transfers control to a C testbench Subsequent model commands in the HDL testbench are processed only after all model command in the C testbench have completed e Aflex synchronize command This causes the testbench to suspend command delivery to one or more models until the specified number of models execute corresponding flex synchronize commands See Using HDL Command Mode on page 39 gt Note In Verilog when you use the model read rslt command or any FLEX WAIT T command simultaneously from two instances of the same model you get corrupted results This is because Verilog tasks have a static scope within a module 40 Synopsys Inc August 28 2001 FlexModel User s Manual Ch
41. RA source file for the model specific ModelFx class The ModelFx Class Constructor The constructor for a ModelFx class expects two string arguments the FlexModel instance name and the clock signal The first argument the FlexModel instance name is the string instance name given to the FlexModel in the top level Verilog or VHDL testbench The constructor uses this argument to get an instance handle for the FlexModel If the instance name passed is invalid the model issues an error and sets a flag in the class indicating the severity of the error For information on accessing the error status see Accessing the Current Error Status on page 51 The second argument is the full path to the clock signal to be used in FlexModel commands This clock signal is used within commands that have associated wait behavior VERA creates a dynamic bind to this clock signal within the constructor using VERA s signal connect feature Because you are using VERA s signal connect function you must use the x switch with Verilog XL at runtime or use P VERA_HOME lib vera_pli_dyn tab for VCS at runtime For more information about the signal connect function refer to the Vera Verification System User s Manual August 28 2001 Synopsys Inc 49 Chapter 3 FlexModel Command Modes FlexModel User s Manual gt Note If VERA cannot find the clock signal in the design it issues a runtime error If you call the constructor at the sa
42. SYNOPSYS FlexModel User s Manual FlexModel User s Manual Copyright 2001 Synopsys Inc All rights reserved Printed in USA Information in this document is subject to change without notice SmartModel ModelAccess ModelTools SourceModel Library LM 1200 and Synopsys Eaglei are registered trademarks MemPro MemSpec MemScope FlexModel LM family LM 1400 Logic Model ModelSource and SourceModel are trademarks of Synopsys Inc All company and product names are trademarks or registered trademarks of their respective owners Synopsys Inc August 28 2001 FlexModel User s Manual Contents Contents luy eePr eR RHEE 9 POE This Mammal 6 eee cee dd AE X EdVCQP IE SC E IE AV E ERRARE d E d dq aired 9 EDU DOOR 4 ding 94 4 9 0 9040 63 9 274 A ARP D dn ede o bela 9 RI ESI METTI 10 Typographical and Symbol Conventions lleleele eese 10 EE e hcg he ie Gee E d OR ba RUD ed diat aria dor equ qd Pac rale 11 The Synopsys WODSME ci 6 6 x ode aw i uh OVS COR HOSES ORO Rd OUR CR ES 12 Synopsys Common Licensing SCL Document Set 4 12 EOD ag d dA pde odi DP XAR Eoo EE Dd qb p eq b ct 12 Chapter 1 Flex Model Overview Sad due ex wo EE REO EROR ACC ON EOLA RRO KR PACA C rl 13 What Are Flex Models 1 sd dicat dope RR AEn e op RO CR Ae cler ae E RR 13 Tics MIGUEL Structure and Interface 4uacaokddxod a d cd ERU CR YER ERA e Re 14 l stalling PlexMod
43. T VERA Testbench program model test ModelFx instl repeat 1 posedge CLOCK instl new my model top U1 CLK Accessing the Current Error Status When an error occurs within the model object it prints an error message to standard error The model object saves the error message and the severity of the error There are three possible severity levels e FLEX_VERA_NOERROR no errors e FLEX_VERA_WARNING warnings e FLEX_VERA_FATAL fatal errors You can use one of two methods to access the current error status e showStatus Returns the present error severity level e showErrors Prints any errors to standard out August 28 2001 Synopsys Inc 51 Chapter 3 FlexModel Command Modes FlexModel User s Manual Example Accessing Current Error Status The following example shows to get the current error status from a VERA testbench program model test ModelFx instl repeat 1 posedge CLOCK instl new my model top U1 CLK Ju f instl showStatus FLEX VERA FATAL instl showErrors Take suitable action else No fatal errors proceed program model_test FlexModel Logging from the VERA Class When FlexModel logging is turned on the VERA class creates a file and logs the versions of the objects This file is used by Customer Support for debugging purposes This file is named model_instance_name versions For example if the instance nam
44. WIFT integrations can also issue commands from a C program but use a different method called Direct C Control For more information refer to the Simulator Configuration Guide for Synopsys Models In C Command Mode FlexModels execute commands contained in an external C program C Command Mode is efficient because you don t have to recompile your simulator when you make changes to the model control program Note that the C programming language does not provide for concurrency or recognize the notion of simulation time For information on other limitations to be aware of when using C Command Mode refer to Pipelined Bus Operations on page 25 Figure 7 shows how to enable C Command Mode using the flex_run_program command to call an external C program from the HDL testbench the same ID HDL Testbench Instantiation of model main modelname ul FlexModelID gt int status Id char ModelID process flex_get_inst_han begin runs the C program ModelId amp Id amp stat flex run program a out stat Id is integer handle other HDL commands here flex start program amp stat runs next C program End of init sequence flex run program b out stat model cmd 1 more HDL commands here end Figure 7 Accessing a C Testbench from HDL In Figure 7 control returns from the C program back to the HDL testbench after the init sequence completes immediately following execution of the flex start
45. When run without the dir switch flexm_setup just prints the name of the versioned directory of the selected model s source files Lists name of versioned directory containing source files 9 flexm setup mpc860 fx When run with the dir switch pointing to your working directory flexm setup copies over all the versioned package files you need to that working directory Creates copy in flexmodel directory of model source files mkdir workdir flexm setup dir workdir mpc860 fx oo oo 18 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 2 Using FlexModels Setting Up the Model Next instantiate one or more FlexModels in your design using required SWIFT parameters as explained in the Simulator Configuration Guide for Synopsys Models You must allow at least one clock cycle to elapse in your testbench before you issue any FlexModel commands This allows the FlexModels to initialize After initialization FlexModels can accept commands from the testbench The first FlexModel command for each model instance must always be the flex_get_inst_handle command which returns a unique model instance identifier called the inst_handle The flex_get_inst_handle Command The flex get inst handle command makes an association between the FlexModelld you used to instantiate the model in your testbench and that specific instance of the model This is so that you can use more than one FlexModel or multiple instances of
46. a positive integer higher numbers indicate higher interrupt priorities Each process always block should check the returned interrupt priority Only one will match and execute its service routine August 28 2001 Synopsys Inc 33 Chapter 2 Using FlexModels FlexModel User s Manual All model commands in an interrupt service routine must be contained within paired model_begin_intr and model_end_intr commands that both specify the same model instance handle and interrupt priority In addition all interrupt commands contained between the model begin intr and model end intr commands must have their wait mode parameters set to false FLEX WAIT F You cannot set wait mode to true FLEX WAIT T or use results model rslt commands in HDL interrupt routines Example HDL Interrupt Routine The following VHDL example interrupt service routine for the tms320c6201_fx model can handle two interrupts INT1 and INT2 where INT2 has a higher priority than INT1 For Verilog replace the process statements with always blocks architecture signal model_int_signal std_logic begin process flex_define_intr_signal inst TOP tms320c6201_int_signal status end process tms320c6201 int signal PROCESS 1 tms320c6201 get intr priority inst priority status if priority 1 tms320c6201 begin intr inst priority status interrupt service routine for priority 1 tms320c6201 end intr inst priority status end end
47. apter 3 FlexModel Command Modes VHDL Control Model commands are VHDL procedures delivered in model specific packages These Synopsys provided FlexModel packages include the procedures and constants needed to call the model from the testbench You must specify an instance specific model identifier by setting a VHDL generic Model instances that do not have unique identifiers cause the Command Core to issue an error If there is only one model instance the default ID value is zero In HDL Command Mode you need to define a unique interrupt signal for each interrupt used by each model instance A particular model instance may also require multiple interrupt service routines See Developing HDL Interrupt Routines on page 33 for an example model interrupt service routine Verilog Control The Verilog control mechanism closely mirrors that of the VHDL implementation You must include Synopsys provided model specific Verilog source files to make the FlexModel tasks available to the testbench For information on getting FlexModels set up with their HDL package files refer to the Simulator Configuration Guide for Synopsys Models HDL Control Between Model and Testbench If you are using a simulator with a custom FlexModel integration individual FlexModels come with a set of HDL procedures or tasks that can be invoked from the HDL testbench These procedures communicate with the Command Core using the same HDL to C mechanism that the mod
48. asserted and again toggles the model int signal signal in the HDL testbench 5 This starts process 1 and process 2 again oo The model get intr priority command executes and returns the priority as 2 so process 1 exits and process 2 starts executing its commands At this point the model stops executing commands for INT1 and begins processing commands for INT2 because it has a higher priority When the model finishes executing all commands for INT2 it goes back and finishes executing commands for INTI Scenario 2 INT2 occurs before INT1 In the other case where the model samples INT2 and begins processing commands from process 2 before a lower priority INT interrupt occurs the model finishes processing all commands for INT2 before servicing the lower priority INTI Developing C Interrupt Routines To develop C interrupt service routines for use with Direct C Control or C Command Mode follow these steps 1 Define a function in the C testbench or program for the interrupt handler 2 Register this function with the model using the flex_switch_intr_control command This function is called by the model whenever it samples a supported interrupt signal asserted Note that you only need one interrupt function in your C testbench to handle all interrupts of any type for that model instance Attempts to register more than one interrupt function for the same model instance result in an error August 28
49. ate to 4 State Conversion 9 state 4 state 0 L 0 1 H 1 U X W X Z Z e For integer variables use the FLEX INT 32 bit unsigned data type e All functions other than the comparison functions have a return type of void Vector Strings Vector strings can be in hexadecimal or binary format h 0 9a fA FxXzZ hexadecimal b OIhHlLuUwWxXzZ binary where means one or more occurrences of the characters within the brackets Illegal characters are silently converted to Xs Here are some examples h01234 Hexadecimal literal 5011011 Binary literal 01234 Illegal vector literal Missing prefix h bOJM11011 Illegal char in binary vector gt bO0xx11011 bO1LLHUXW Z 9 state to 4 state gt b0101xxxxz August 28 2001 Synopsys Inc 91 Chapter 5 FlexModel C Testbench Interface FlexModel User s Manual Assigning Literals to FLEX_VEC Constants You can assign string literals to FLEX_VEC constants as shown in the following examples const FLEX VEC addrincr Assign a vector value addrlIncr h4 Assign a different vector value addrIncr hffffeeee If you assign a literal to a FLEX VEC vector instead of a FLEX VEC constant you lose the memory allocation for the vector To assign a literal to a FLEX VEC vector created by the FLEX DEFINE command use the flex assign operators documented on page 93 Note that ar
50. cription Given a model inst_handle and cmd_tag the flex_get_cmd_status command returns the valid_f true if the specified command is active or pending Prototypes C void flex get cmd status const int inst handle const int cmd tag int valid f int status VHDL procedure flex get cmd status inst handle in integer cmd tag in integer valid f Out boolean status cout integer 66 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 4 FlexModel Command Reference Verilog task flex_get_cmd_status input 31 0 inst_handle input 31 0 cmd_tag output valid_f output 31 0 status VERA task get_cmd_status integer cmd_tag var integer valid_f var integer status Examples The following examples return valid_f true because the preceding specified commands are valid VHDL Example arm7tdmi read req inst addrl 0 FLEX WAIT F tagl flex get cmd status inst tagl valid f status Verilog Example arm7tdmi read req inst addrl 0 FLEX WAIT F tagl flex get cmd status inst tagl valid f status C Example arm7tdmi read req inst addrl 0 FLEX WAIT F amp tag1 flex get cmd status inst tagl amp valid f amp status NERA Example model object read req addrl 0 FLEX WAIT F tagl model object get cmd status tagl valid f status This last command returns valid f false because tag2 did not get assigned to any command yet and th
51. d ia 4 OxOeeeffff count 4 Reset ia ia 0 ia 1 ia 2 ia 3 0 count 2 flex to int array datal28 amp count ia Issues a warning about only reading the 2 rightmost FLEX INTs while the actual vector is 4 FLEX INTs wide ia 0 OxO0cccddd ia 1 OxOeeeffff ia 2 0 ia 3 O count 2 flex to int list The flex to int list command extracts count number of 32 bit integers from vec and puts them into a list with the right most bits going to A nt and the left most bits to rhInt void flex to int list const FLEX VEC vec unsigned int count FLEX INT JhInt FLEX INT rnhInt For example FLEX INT myInt 0 unsigned int count int i FLEX INT ia 4 0 0 0 O y FLEX INT il i2 i3 i4 FLEX DEFINE data128 128 h0 flex assign int list datal128 4 0x8889999 Oxaaabbbb Oxcccddd Oxeeeffff Using flex to int list count 0 flex to int list datal128 amp count amp il amp i2 amp i3 amp i4 August 28 2001 Synopsys Inc 101 Chapter 5 FlexModel C Testbench Interface FlexModel User s Manual i0 0x08889999 i2 Ox0aaabbbb i3 0x00cceddd i4 OxOeeeffff count 4 Reset FLEX INTs i0 il i2 i3 0 count 8 flex to int list datal128 amp count amp il amp i2 amp i3 amp i4 Issues a warning about only reading 4 FLEX
52. d result command With other result commands you use the addr parameter returned by a paired request command to specify the starting address for the data to retrieve The idea in both cases is to uniquely identify the data you want to retrieve by using values returned by a preceding model request command When you use an addr parameter with a result command and more than one request command for the same address has posted the result command returns data for the first request command received by the model before returning data for the second result command received and so on For example read req 00000000 request data from address 00000000 and the data is a sated some other stuff or just time delay during which time the data at 00000000 changed to b read req 00000000 request data from address 00000000 and the data is b read rs1t 00000000 return data get the data requested back to the testbench print return data the data printed is a read rs1t 00000000 return data get the data requested back to the testbench print return data the data printed is p To avoid this behavior use command tag result identifiers whenever possible Refer to the command reference sections of the individual model datasheets for more information about the supported model request and result commands and the result identifiers available with each one August 28 2001 Synopsys Inc 55 Chapter 4 FlexMode
53. del eee eee 28 Selecting Cydle based Mode cusa sk aod RE RR DERE A SOEUR RA ECKE RR A 29 Controlling Timing Checks and Delays iiioses desees RR hn 30 PFlexModel Oe 1a oe cher ce oc der aoe aeons eR REEL Rae db 31 Interrupt Service ROUDBDR us dy ous OG eR VOR Kv eee ee ENS ROGA REOR ees 31 Detecting and Servicing IMIS 2 ck deni ence du ckiweee sey eednrcenes TA 31 Developing HDL Interrupt Routines 26 06500040eadeendnaesens eend 33 Developing C Interrupt Routines Lissacas uxaREAREARRESAGORER RAS RA RAE 35 Developing VERA Interrupt Routnes 4deeceseuweeeckxsecex td d EERTO Y 37 Chapter 3 FlexModel Command Modes ic cid s keke i cee SCE ERNE ERI CER ERE RACER AE ROR ne 39 MOG cues ete PE 39 Usine HDL Command Mode cosaekedett3btUse ks kia Xd RE IPED tpi 39 VEHDL TEUER rere srr rey tS rr er ne TT E I EE EEER 4 P PI Id eA 4 bo so d oo rm 4 HDL Control Between Model and Testbench vita da wcdeenaeiedeuwes ands 41 Usines C Command Mode 1agasaedaeda queam tbededausxitcewrtapstede 5058645 43 Creating an External C File uua desde SER REOR Sh RR AS tS a Rc dor re d RR 44 Compilne an External C Fil uuucska spe ker CER Od wee Ra I oC d 45 Switching Control to an External C Program Lausasekadrk Xx RA cheeses 47 Using VERA Command Mode coiuusosauA e nara nener 47 PEXMDEM VER ALA desap eeeedahuatdax deer ip iid iea epeta pEi 48 VERA Files in the LMC HOME Tree 564 05 6 dsdebene RR UR E RO 49 The Sows Class C nstr ctor nn oh ERK
54. del_get_intr_priority 33 36 Interrupt Service Routine 31 118 FlexModel User s Manual definition 31 invocation 31 priority specific 31 process always block 33 Interrupts C Command Mode description 33 C Command Mode setup 33 clock edges 31 detection 31 handler synchronization 27 nesting of 33 reset 31 VHDL control 41 VHDL example 33 Interrupts and Exceptions 31 L Licensing 15 Linux compiling C files 46 LMC_HOME tree 15 Logging 109 bidirectional pins 113 cmd model_instname log 111 command format 111 commands 111 commands not logged 111 enabling for instance 110 log file examples 111 message logfile 113 messages 113 model logger v file 112 msg model instname log 111 pin model instname log 111 stimulus 112 stimulus example 112 strategy 110 M MAX 29 MIN 29 Model Logging 110 model begin interrupt 36 Synopsys Inc August 28 2001 FlexModel User s Manual model_end_interrupt 36 model_pkg h 44 model_set_timing_control 30 Multiple command sources 27 Multiple Command Streams in C testbench 21 N Non pipelined transfers example 24 NT compiling C files 46 num_instance parameter 27 P Parameters DelayRange 29 inst_handle 55 num_instance 27 sig_name 64 status 56 sync_label 27 sync_tag 83 sync_timeout 83 sync_total 83 Timing Version 29 valid_f 66 wait flag 56 wait_mode 40 Pipelined bus operations 25 Pipelining delayed result checking 27 39 phase diagram 25 request pha
55. dix A Reporting Problems FlexModel User s Manual Running FlexModel Diagnostics It is possible that the model behavior you are seeing is caused by a faulty installation or from using an older version of a FlexModel If you do call Customer Support and assuming there is no immediate solution to your problem you will most likely be asked to run the swiftcheck diagnostic tool to verify the model version that you are using and check your environment For information on how to run swiftcheck refer to Checking SmartModel Installation Integrity in the SmartModel Library User s Manual This tool produces a swiftcheck out file Send this file to Customer Support along with the other model logging files as described in Sending the Log Files to Customer Support on page 113 Creating FlexModel Log Files To create the FlexModel log files needed by Customer Support to debug model problems follow these steps Attention For FlexModels that end with an _fz extension refer to the SmartModel Library User s Manual for the applicable model logging procedures The logging mechanism described in this procedure applies only to models that end with an fx extension 1 For each FlexModel in your testbench use the model specific model_set_msg_level commands to set the message levels all the way up 2 In the directory where you run your simulation use the UNIX touch command or create an empty file that conforms to the following syntax
56. e ERA 56 Table 4 Global FlexModel Command Summary 0000 00 59 Table 5 Returned Values and Corresponding Net States of value for flex get value 71 Table 6 Hex seb Vals path Syntax Examples 2 6 cae ake b xe t RR E Ua IRR 78 Table 7 Allowed Values of value forflex set value lesen 78 Table 8 Syntax Examples for the path Parameter 20 ce eee ee eeees 86 Table 9 VHDL 9 State to 4 Stale Conversion 2 40ss ese re ed ee RR 91 Table 10 Stimulus Logging Format ax kd cn cdh eo oaws ine ee deri e REA ao HCAS wR 112 8 Synopsys Inc August 28 2001 FlexModel User s Manual Preface Preface About This Manual This manual explains how use FlexModels in your test environment FlexModels are a type of SmartModel and they share many characteristics in common with them but there are significant differences For example FlexModels have advanced features like the ability to issue model commands from an HDL C or VERA testbench Those capabilities and other enhancements to traditional SmartModel usage are explained in this manual This manual works in tandem with the individual FlexModel datasheets General information that pertains to all FlexModels is presented here whereas information that is specific to individual FlexModels is documented in the model datasheets Related Documents For general information about SmartModel Library documentation or to navigate to a different online document
57. e 20 e FlexModel Timing on page 28 e FlexModel Interrupts on page 31 SystemC SWIFT Support Synopsis provides a SystemC SWIFT interface that supports Flex Models SystemC is a C class library used for creating cycle accurate models of software algorithms hardware architecture and interfaces for System on Chip SoC and system level designs As part of its class library SystemC provides a cycle simulation environment is designed to work with event driven logic simulators and provides extensive support for modeling device timing accurately For more details see the SmartModel Products Application Notes Manual August 28 2001 Synopsys Inc 17 Chapter 2 Using FlexModels FlexModel User s Manual Running flexm_setup First run the flexm_setup script to copy the FlexModel s interface files to your working directory You need to run flexm_setup for each FlexModel you want to use in your design and you must rerun this script after updating your LMC_HOME with new or revised FlexModels This ensures that you pick up the latest package files for the most recent versions of the models Syntax flexm_setup help dir path model Argument model Pathname to the FlexModel you want to set up Switches help Prints help information d ir path Copies the contents of the FlexModel s versioned src verilog and src vhd directories into path src verilog and path src vhdl The directory specified by path must already exist Examples
58. e for the tms320c6201 is inst1 then the file created is named tms320c6201_inst1 versions For more information on FlexModel logging see Reporting Problems on page 109 52 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 4 FlexModel Command Reference 4 FlexModel Command Reference Introduction This chapter explains the different types of FlexModel commands and their common elements and provides a complete command reference for the global FlexModel commands This information is presented in the following major sections e Model Specific and Global Commands on page 53 e About the Commands on page 54 e Global FlexModel Command Descriptions on page 61 Model Specific and Global Commands You use FlexModels by issuing commands to model instances in your testbench There are two basic kinds of FlexModel commands as shown in Table 2 Table 2 FlexModel Command Types Command Type Used To How to Identify Where Documented Model specific Exercise processor or bus Command prefix equals Individual model protocol functions the model name For datasheets example mpc860 write Global Control program flow or Command prefix is flex In this manual Refer to handle general housekeeping For example Global FlexModel functions flex_get_inst_handle Command Descriptions on page 61 later in this chapter August 28 2001 Synopsys Inc 53 Chapter 4 FlexModel Command Refere
59. e synchronizes the model with the testbench process that contains model commands so that the model is prevented from advancing to the next simulation time step when the next command is not available In uncoupled mode the model does advance to the next time step even when the next command is not yet available In this state the model continues to poll for new commands thereby preventing gridlock conditions for multi model or multi stream simulations FlexModels start up in coupled mode by default There are three methods of changing the default mode Using a SWIFT model parameter for simulators with standard integrations or using the flex run program command for simulators with custom integrations as shown in the following examples Standard Integrations Using SWIFT parameter in the model instantiation for _fz models defparam ul FlexModelSrc command stream path to C file u c where command stream is the name of the command stream as defined in the model datasheet For models with multiple command streams use two defparams with each one pointing to a unique command stream in the model 22 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 2 Using FlexModels Using SWIFT parameter in the model instantiation for fx models defparam ul FlexCFile path to C file u c Custom Integrations Using flex run program command from a Verilog or VHDL testbench flex run program path to C file
60. e third attempt The workaround is to turn off model logging Transferring Control to a C Testbench You can transfer control from an HDL or VERA testbench to a C testbench using the flex_run_program command The model receives all commands from the C testbench before any subsequent model commands in that VHDL process or Verilog block When you have multiple command streams operating at the same time there are a few things to keep in mind Non model commands such as Verilog display statements following the flex_run_program command are processed immediately You cannot issue model request commands _req in one command source and model result commands _rslt in another For example if you want to make a read request for a FlexModel and then fetch the results keep both FlexModel commands in either your C or HDL testbench It is best to organize your commands to minimize switching in and out of the same command source For example if you want to use a C program for two separate command sequences to be performed at two different points in the simulation create two separate C command files You cannot have multiple VERA VHDL or Verilog processes providing commands to the same model instance You cannot use the flex run program command to switch between different HDL or VERA command sources For more information on the flex run program command see flex run program on page 75 Using Multiple Command Streams in a C Testbench A C te
61. ecify an address variable addr or something like that You can use the FLEX DEFINE function to create the data structure in C for that addr variable and then issue the model specific FlexModel command to exercise the model Data structures created with FLEX DEFINE are called FLEX VEC vectors This definition process is necessary because C does not provide variables that are handy for manipulating vectors such as the 32 bit data or address buses needed to work with processor models for example Also although C does provide many operators for manipulating integers and strings those operators do not work with the FLEX VEC vectors you create for use with FlexModel commands So FlexModels come with comparable FlexModel C operators that work with the FLEX VEC vectors you create August 28 2001 Synopsys Inc 89 Chapter 5 FlexModel C Testbench Interface FlexModel User s Manual Creating FLEX VEC Vectors You create FLEX VEC vectors using either the FLEX DEFINE command or the FLEX VEC SIZEOF command Use the FLEX DEFINE command for vectors that only need to be used in the local scope of the function If you need to create FLEX VEC vectors dynamically with a global scope use the FLEX VEC SIZEOF command FLEX DEFINE The FLEX DEFINE command creates a FLEX VEC vector named vecName that is vecSize bits wide with an initial value of initVal You must specify a vector string literal or the FLEX NULL VEC macro in the initVal argument Use FLEX
62. el read req inst handle address data wait mode status would look like this in VERA Command Mode modelObject read req address data wait mode status 58 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 4 FlexModel Command Reference Global FlexModel Commands Global FlexModel commands are available to all FlexModels They either perform supervisory functions switching command sources handling interrupts printing messages or operate globally on all models synchronizing models clearing queues and enabling tagging The prefix flex is common to all of these commands Table 4 lists the global FlexModel commands Some commands are available only in specific command modes as shown in the Command Mode column The commands are described in detail in Global FlexModel Command Descriptions on page 61 Table 4 Global FlexModel Command Summary Command Command Name Mode Description flex_clear_queue All Clears the queues for the model flex_define_intr_function C Defines a C interrupt function for the model flex define intr signal HDL VERA Defines the testbench interrupt signal for the model flex get cmd status All Checks the status of a model command flex get coupling mode C Checks the coupling mode for the model flex get inst handle All Gets an inst_handle for the model flex_get_value C Gets the single bit value of a specified net
63. els ois ise dua ERA REX Ge REOR RR E Rap deed RR cR EERE ES 14 FlexModel Installation Tre ao 5 nds nce end ds necds nee onde Sead ERA tekisi 15 Pee IA rre 15 FlexModel Limitations Lusia quay ass Or RACE aed VOR SOR ER RC RR away hn 16 Chapter 2 Usine Fl xModeih s xsAsues dusd exdsdtukatibik xeEeTuEeRab AX EREK ES WAR ee 17 BOO eer ee one d Pact CR Ea Oe FRA eer are eee ee meee AR lee n 17 System S WIFE SUPPO iuasxusashketi tam AARAU AREARE NATS 17 Runnings Herm s Merc rrr PIT 18 SH Up ihe Model ab 604 bdo dedicado edid Up el dio EE es 19 The flex set met handle Command o cs4sd de cases ars dud REOR OR ERR ROCA 19 Using Multiple FlexModel Instances uossoto ue t hu o E ERR RR EXEAT ERAS 19 Controlling the FlexModel Command Flow ans 604 4 sache rrr es e 20 Resetting the Simulation ccc as dug edd XA DEP REA Na e RERA RACE Aa 21 Transferring Control to a C Testbench sues cugRek E EY ARE RE RPREW PERS 21 Using Multiple Command Streams ina C Testbench 21 Using Uncoupled Mode in a C Testbench iiscolosuosss RR ERR RR 242 ln Wi co I p 24 Non pipelined Bus Operations oko 4 og Fab Rp REPARARE RR Ra 24 Pipelined Bus Operations quessauesacasAd x ashbuacta mxsduA RR RA ERAS 25 Synchronizing the Command Flow uusaasaquctyrtearsaXyrxikvrie4 P X ERG Zi August 28 2001 Synopsys Inc 3 Contents FlexModel User s Manual Peele DIM 1doscesdXuweseaaxteiersZxbyixPiqkdrU XR LEA Rad erae 28 Selecting Function only or Timing Mo
64. els use The HDL testbench and the model do not attempt to access the Command Core at the same time preventing conflicts FlexModels interact with the Command Core on falling clock edges while the HDL testbench procedures or tasks use the rising edges August 28 2001 Synopsys Inc 41 Chapter 3 FlexModel Command Modes FlexModel User s Manual Figure 5 illustrates a simple read req read rslt pair from the HDL testbench without pipelining The testbench and model activity are synchronized to the rising edges of the clock but the interaction between the FlexModel and the Command Core only occurs on the falling edge The user sees a single clock cycle delay before the first command starts and a one cycle delay before the results of the operation are available to the testbench read req read rslt Figure 5 Read req read rslt Pair for Testbench Figure 6 shows how multiple model state commands can occur in a single clock cycle reg req reg req reg rslit reg rslit Figure 6 Multiple Commands within a Single Clock Cycle The mechanism illustrated in Figure 6 guarantees that the model is in a stable state when the register values are posted 42 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 3 FlexModel Command Modes Using C Command Mode The following description of C Command Mode applies just to simulators with custom FlexModel integrations Customers with standard S
65. ench examples 50 using 47 VERA classes 48 VERA interrupt routines 37 Verilog cycle based setup 29 task calls 40 timing example 30 timing setup 29 Verilog control 41 VHDL cycle based setup 30 procedure calls 40 120 FlexModel User s Manual testbench example 39 timing example 30 timing setup 29 VHDL control 41 Visual C 47 W wait Flag 56 Wait in C Command Mode 85 timing diagram 85 wait mode example 26 wait mode parameter 40 Websites Synopsys 12 Synopsys Inc August 28 2001
66. ent Fe KK A KK IK A KA A AA A A A A I KA I ke e f Define interrupt function with the command core For more information on this refer to the section on Interrupts flex define intr function nId my intr function amp nStatus flex fprintf Using flex fprintf to print a debug message stderr Beginning my C Command Stream n RR KK IK I KKK KKK KKK I KKK Ck KKK KKK KK CC KK CK KICK CK KICK KKK K K Test 1 Do a read and verify the results Desc Demonstrates passing of addresses data to commands KCKCKCKCKCK kCkCkCk KC KK A A A A A I I A I A I KK IK Issue a model_read and pass address directly to command model read req nlId b00001111111111111111111111110000 FLEX WAIT T amp nStatus Read the results ret data is the array we defined earlier using FLEX DEFINE Note This time pass in a hex address model read rslt nId hOffffffO0 0O ret data amp nStatus Use flex eq to compare the results if flex eq b10101010101010101010101010101010 ret data flex fprintf stderr Test 1 Failure Mismatch Found n J KCKCKCKCKCKCkCkCk KKK KKK kk KC I A I I I KK KKK KK C KC KKK KKK KKK KKK KKK KKK KKK ke Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 5 FlexModel C Testbench Interface Test 2 Do a read and verify the results Desc Demonstrates storing addresses as vectors and then passing the
67. erview information in the intro pdf file Additional Synopsys documentation is available at this URL http www synopsys com products Im doc Datasheets for models are available using the Model Directory http www synopsys com products Im modelDir html 2 Visit the online Support Center at this URL http www synopsys com support Im support html This site gives you access to the following resources o SOLV IT the Synopsys automated problem resolution system o product specific FAQs frequently asked questions o the ability to open a support help call o the ability to submit a delivery request for some product lines August 28 2001 Synopsys Inc 11 Preface FlexModel User s Manual 3 If you still have questions you can call the Support Center North American customers Call the Synopsys Eaglei and Logic Modeling Products Support Center hotline at 1 800 445 1888 or 1 503 748 6920 from 6 30 AM to 5 PM Pacific Time Monday through Friday International customers Call your local sales office The Synopsys Website General information about Synopsys and its products is available on the Web http www synopsys com Synopsys Common Licensing SCL Document Set Synopsys common licensing SCL software is delivered on a CD that is separate from the tools that use this software to authorize their use The SCL documentation set includes the following publications which are located in root docs scl on the SCL CD and also avai
68. etection with C Testbenches To allow simulation time to advance while your C testbench is running and thus enable interrupt servicing set the wait_mode parameter of the last model bus cycle command to true FLEX_WAIT_T As an alternative you can use the flex_wait command to achieve the same effect Otherwise the C program will simply run to completion before any interrupts can be serviced by the model Note that interrupt service routines in C testbenches can use result model_rslt commands and model commands with the wait_mode parameter set to true FLEX_WAIT_T These are not allowed in HDL Command Mode When a FLEX_WAIT_T command is executing in a C interrupt service routine other interrupts of higher priorities can be serviced Developing HDL Interrupt Routines To develop a VHDL or Verilog interrupt service routine follow these steps 1 Define a signal or reg in your testbench called My nt or something similar 2 Use the flex_define_intr_signal command to register this signal with the FlexModel You only need one testbench signal regardless of the number of interrupt types the model supports FlexModels toggle this signal when any supported interrupt pin is asserted 3 Write process MylInt or always MylInt blocks for VHDL or Verilog respectively You need one block for each interrupt priority you want to support The first command in each process always block must be a model get intr priority command This command returns
69. eve the results from those reads in any order This process is illustrated in Figure 3 Hu m FP Request Phase Qo Request command provided to model DataPhase Result is available Figure 3 Pipelined Bus Operations There are two ways to get pipelined bus operations with FlexModels e Pipelining With wait_mode Behavior on page 26 e Pipelining With Delayed Results Checking on page 26 August 28 2001 Synopsys Inc 25 Chapter 2 Using FlexModels FlexModel User s Manual Pipelining With wait_mode Behavior FlexModel request and result commands work together to retrieve data from the model Request commands have a req suffix and result commands have a rslt suffix Request commands cause the model to post the data and result commands retrieve the results Testbench operations wait or proceed based on how you set the wait mode parameter in the request command For example e If the wait mode in a request command is false FLEX WAIT F the model immediately proceeds to the next command e If the wait mode in a request command is true FLEX WAIT T the model waits until the command completes before proceeding to the next command You can use this wait behavior to pipeline multiple request commands as shown in the following VHDL example variable datal data2 data3 bit vector 31 downto 0 COMMAND 1 model read req inst X 00000004 X O FLEX WAIT F status COMMAND 2 model
70. ex to int array command extracts count number of 32 bit integers from vec and puts them in the iaf array If count is 0 the entire contents of vec are extracted The int pointed to by count is set to the number of integers extracted The right most 32 bits in vec are put in the last array element and the left most bits are placed in the Oth array element Make sure that the receiving array is large enough to hold all the integers in vec If count is higher than the number of integers in vec its value is changed to the actual number of integers extracted Here is the syntax void flex to int array const FLEX VEC vec unsigned int count FLEX INT ia For example FLEX INT myInt 0 unsigned int count int i FLEX INT ia 4 0 0 0 O y FLEX INT il i2 i3 i4 FLEX DEFINE data128 128 h0 flex assign int list datal128 4 0x8889999 Oxaaabbbb Oxcccddd Oxeeeffff Using flex to int array count 0 flex to int array datal28 amp count ia ia 0 0x08889999 100 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 5 FlexModel C Testbench Interface ia 2 OxOaaabbbb ia 3 0x00cccddd ia 4 OxOeeeffff count 4 Reset ia ia 0 ia 1 ia 2 ia 3 0 count 8 flex to int array datal28 amp count ia Issues a warning about only reading 4 FLEX INTs ia 0 0x08889999 ia 2 OxOaaabbbb ia 3 0x00cccdd
71. f const char formatStr In this example buf must be a character array large enough to hold the resulting string The maximum string length is 255 characters The 96H and B Conversions These print functions work just like the ANSI C printf utility In addition they support H and a B formatting conversions that you can use to print a FLEX VEC vectors or const FLEX VEC literals These conversions support the same formatting features as the C s conversion The H and B conversions print vectors without the h ora b prefixes For example you could print the contents of different variables to standard error as follows flex fprintf stderr Extracted datal28 h H into Mn i1 x i2 x 13 S x 14 x n datal28 il i2 i3 i4 This produces output that looks like the following Extracted datal28 h0x088899990aaabbbb00cccddd0eeeffff into 11 0x8889999 i2 0xaaabbbb i3 0xcccddd i4 0xeeeffff C Testbench Example The following C testbench example illustrates how to use the FLEX VEC vectors described in this chapter to set up and process interrupts and to perform a variety of general FlexModel functions include model pkg h include flexmodel pkg h define MODEL ADDRBUS WIDTH 32 define MODEL DATABUS WIDTH 32 Interrupt Function void my intr function Global Id define so that it is visible in the intr function int nId void main int
72. fits of the powerful VERA verification language In VERA Command Mode you can use any FlexModel command or feature available in HDL Command Mode The FlexModel to VERA command interface is a direct connection to the C part of the hybrid HDL C FlexModel architecture Because the connection is not through the simulator PLI FLI it runs faster VERA Command Mode syntax differs slightly from that of HDL Command Mode For more information see Command Syntax Differences in VERA Command Mode on page 58 The following sections document how to use VERA with FlexModels For general information about using VERA refer to the Vera Verification System User s Manual August 28 2001 Synopsys Inc 47 Chapter 3 FlexModel Command Modes FlexModel User s Manual FlexModel VERA Classes VERA is an object oriented language The FlexModel VERA command interface uses the inheritance feature to construct a model class hierarchy At the top of the hierarchy is a general model class Other model classes inherit from this general class Figure 8 shows the model hierarchy LstModel SwiftModel Flex ModelFx Figure 8 VERA Model Class Hierarchy The LstModel SwiftModel and Flex classes are abstract or virtual classes These classes cannot be instantiated directly in VERA testbenches Only an instance of a ModelFx class can be created in a VERA testbench The commands used to control FlexMode
73. gcs o executable name your C file c workdir src C x86 linux model pkg o LMC HOME lib x86 linux lib flexmodel pkg o Iworkdir src C IS LMC HOME sim C src oo oo On NT you need to link in a Windows socket library as shown in the following example md workdir gt flexm setup dir workdir model fx gt cl 02 MD DMSC DWIN32 Feexecutable name your C file c workdir sre C pent model_pkg obj LMC_HOME 1ib pent 1ib flexmodel_pkg obj I LMC_HOME sim C src Iworkdir sre C WSOCk32 1lib Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 3 FlexModel Command Modes gt Note The entire compilation expression must appear on the same line The NT example was tested using Microsoft s Visual C compiler v5 0 Switching Control to an External C Program You switch model control to an external C program using the flex run program command in your HDL testbench The following example shows a FlexModel command process that executes an external C program CMD STREAM process begin wait for CLK PERIOD assert false report Running C Program severity NOTE flex run program a out status assert false report Finished Running C Program severity NOTE wait end process CMD STREAM Using VERA Command Mode FlexModels come with an object oriented VERA command interface that lets you control them from a VERA testbench When you use FlexModel from VERA you get all the bene
74. gging and report problems to Customer Support Typographical and Symbol Conventions e Default UNIX prompt Represented by a percent sign e User input text entered by the user Shown in bold monospaced type as in the following command line example cd LMC_HOME bin e System generated text prompts messages files reports Shown in mon ospaced type as in the following system message VALIDAT ON PASSEI D No Mismatches during simulation Synopsys Inc August 28 2001 FlexModel User s Manual Preface e Variables for which you supply a specific value Shown in italic type as in the following command line example setenv LMC HOME prod dir In this example you substitute a specific name for prod_dir when you enter the command e Command syntax Choice among alternatives is shown with a vertical bar as in the following termination style 0 1 In this example you must choose one of the two possibilities 0 or 1 Optional parameters are enclosed in square brackets as in the following pinl pin2 pinN In this example you must enter at least one pin name pin but others are optional pin2 pinN Getting Help If you have a question while using Synopsys products use the following resources 1 Start with the available product documentation installed on your network or located at the root level of your Synopsys CD ROM Every documentation set contains ov
75. guments of type const FLEX VEC do not have any allocated storage since FLEX DEFINE has not been used Therefore they can only be used as input values not for result values FLEX VEC Error Handling The FLEX VEC commands documented in FLEX VEC Command Descriptions do not return error status Instead they increment internal error warning and note message counters To retrieve the current counts use the flex errors flex warnings and flex notes commands Using incorrect command syntax or violating any of the FLEX VEC Lexical Rules will result in an error Most error types generate informative error messages on your screen You can check the error counts as often as you want but checking error status only at critical points in your testbench will result in a more readable coding style You may want to run the following commands at the end of your C testbench to ensure that the program executed as expected e flex errors e flex warnings e flex notes The following example shows how to use the flex fprintf command to print the values of the three internal counters flex fprintf stderr Status d error s d warning s d note s n flex errors flex warnings flex notes 92 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 5 FlexModel C Testbench Interface FLEX VEC Command Descriptions Following are descriptions of the FLEX VEC commands flex assign The flex assign command assigns
76. h is specified Buses can be accessed one bit at a time To set a value of a bus flex_get_value needs to be called explicitly for each bit of the bus value The command returns the value of a net specified by path Table 5 lists returned integer values and the corresponding net states Table 5 Returned Values and Corresponding Net States of value for flex_get_value Returned Corresponding Interger Net Value State 0 FLEX_LOGIC_VALUE_0 1 FLEX LOGIC VALUE 1 2 FLEX_LOGIC_VALUE_Z 3 FLEX_LOGIC_VALUE_X 4 FLEX_LOGIC_VALUE_U 5 FLEX_LOGIC_VALUE_W 6 FLEX_LOGIC_VALUE_L 7 FLEX_LOGIC_VALUE_H 8 FLEX_LOGIC_VALUE_DC August 28 2001 Synopsys Inc 71 Chapter 4 FlexModel Command Reference FlexModel User s Manual status A status of less than or equal to 0 means that the command did not complete successfully A status of 1 indicates that the socket connection between the C testbench and the command core was successfully established It does not however indicate the successful completion of the command It is possible for the command to fail if the wrong path has been specified and the status will still be 1 Look for error messages in the simulation transcript when you first use this command to make sure that you provided the correct hierarchical path to the signal you want to get on Description This command gets the value of a specified net in the design The net does not need to be connected t
77. handle returned by the flex get inst handle command queue select Specify one of the following constants FLEX ALL QUEUES Clear all queues FLEX CMD QUEUE Clear only the command queue FLEX RSLT QUEUE Clear only the result queue status A status of 1 means the command completed successfully A status less than or equal to 0 means the command did not complete successfully Negative integers provide error code information For more information on command status see The status Parameter on page 56 Description The flex clear queue command clears the queue s for the specified model instance It executes immediately and overrides any commands that are in wait mode except in C Command Mode where there is no concurrency Prototypes C void flex clear queue const int inst handle const int queue select int status August 28 2001 Synopsys Inc 61 Chapter 4 FlexModel Command Reference 62 VHDL procedure flex_clear_queue inst_handle queue_select in in integer integer status out integer Verilog task flex clear queue input 31 0 inst handle input 31 0 queue select output 31 0 status VERA task clear queue integer queue select var integer status Examples FlexModel User s Manual The following examples clear just the command queue for the model instance specified by the inst inst handle Verilog Example flex_clear_queue inst
78. ided that the full hierarchical path is specified Buses can be accessed one bit at a time To set a value of a bus flex_set_value needs to be called explicitly for each bit of the bus Table 6 flex_set_value path Syntax Examples Simulator Single Bit Form Bus or Part of Bus Form Verilog Simulators VCS top a top b 0 top b 5 MTIVLOG top a top b 0 top b 5 VXL top a Not supported VHDL Simulators MTI top a Not supported SCIROCCO top a top b 0 top b 5 VSS CYCLONE Not supported Not supported value Net value Allowed values are specified in Table 7 Table 7 Allowed Values of value for flex set value FLEX LOGIC VALUE 0 FLEX LOGIC VALUE 1 78 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 4 FlexModel Command Reference Table 7 Allowed Values of value for flex set value FLEX LOGIC VALUE Z FLEX LOGIC VALUE X FLEX LOGIC VALUE U FLEX LOGIC VALUE W FLEX LOGIC VALUE L FLEX LOGIC VALUE H FLEX LOGIC VALUE DC status A status of less than or equal to 0 means that the command did not complete successfully A status of 1 indicates that the socket connection between the C testbench and the command core was successfully established It does not however indicate the successful completion of the command It is possible for the command to fail if the wrong path has been specified and the status will s
79. information about setting up and using the FLEXIm licensing software August 28 2001 Synopsys Inc 15 Chapter 1 FlexModel Overview FlexModel User s Manual FlexModel Limitations FlexModels do have some limitations compared to traditional SmartModels FlexModels do not support fault simulation Component based user defined timing UDT is supported in FlexModels but instance based UDT is not SmartModel model logging is not supported for models that have an _fx extension FlexModels of this type have a different model logging mechanism that is described in Creating FlexModel Log Files on page 110 SmartModel windows are not supported in FlexModels Instead use the robust FlexModel command set to access and change internal register information Flexmodels do not support save and restore operations Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 2 Using FlexModels 2 Using FlexModels Introduction This chapter explains how to set up one or more FlexModels and coordinate the flow of FlexModel commands from multiple sources It also explains how to set up and use FlexModel timing and interrupt service routines This information is organized in the following sections e SystemC SWIFT Support on page 17 e Running flexm_setup on page 18 e Setting Up the Model on page 19 e Using Multiple FlexModel Instances on page 19 e Controlling the FlexModel Command Flow on pag
80. initialized exception queue 309 A flex_synchronize command was received with a NULL sync_tag string 310 Two flex synchronize commands were received they had the same sync tags but different sync totals See flex synchronize on page 83 for the correct syntax 311 A second attempt was made to assign a sync fag to a model instance that already had one 312 A sync fag associated with too many flex synchronize commands was received 313 The executable file specified by the flex run program command could not be found Chapter 4 FlexModel Command Reference Note that FlexModel C functions return a status of 1 when they complete successfully and do not return at all on fatal errors August 28 2001 Synopsys Inc 57 Chapter 4 FlexModel Command Reference FlexModel User s Manual Command Syntax Differences in VERA Command Mode In VERA Command Mode the model functions are called through a model object therefore the model name is not a part of the command name in VERA So a command that would look like this in HDL Command Mode model read req would look like this in VERA Command Mode modelObject read req The modelObject is an instance of the ModelFx class that you create in your VERA testbench The FlexModel class encapsulates the inst handle value therefore the inst handle argument is not required in FlexModel commands from VERA So a command that would look like this in HDL Command Mode mod
81. instl con 1 2 arm7tdmi read req inst2 con 3 arm7tdmi read req inst2 con Synchronize instance 1 with identical to wait on sync ex synchronize instl 2 Synchronize instance 2 with identical to trigger sync 84 ex synchronize inst2 2 syncl fig read X 00000004 1 X 0 FLEX FALSE FLEX WAIT F X 00000000 status fig read X 00000004 1 FLEX FALSE FI xm 0 n 7 EX WAIT F X 00000000 status fig read X 00000004 1 FI EX FALSE FI XO EX_WAI X 00000000 T F status 2 instances with the sync label syncl 7 B wv syncl 0 status label 2 instances with the sync 7 r 0 status Synopsys Inc syncl FlexModel User s Manual 0 0 0 August 28 2001 FlexModel User s Manual Chapter 4 FlexModel Command Reference flex_wait Temporarily halts command execution in a C testbench Syntax flex_wait clock_cycles status Parameters clock_cycles The number of clock periods to halt the C testbench status A status of 1 means the command completed successfully A status less than or equal to 0 means the command did not complete successfully Description The flex_wait command halts execution in the C testbench for the specified number of clock_cycles This means that the next command in the queue will only be seen by the model
82. is command to make sure that you provided the correct hierarchical path to the signal you want to wait on A status of 2 means that expected value or mask did not fit the width of the signal specified by path A warning is issued and the expected value or the mask is modified to match the signal width Description The flex wait on node command blocks the command stream in the C program until the specified value is assigned to the specified design net You can use this command for any single bit net or for supported simulators bus in the design and you can mask expected value using mask Net value is sampled once every clock cycle This command allows the C program to wait for any net in the design to be set to expected value before proceeding with the execution of the remaining commands August 28 2001 Synopsys Inc 87 Chapter 4 FlexModel Command Reference FlexModel User s Manual The flex_wait_on_node command only works with simulators that support both HDL and C command control To enable this command you need to establish a connection between the simulator and the command core This is done by invoking the flex_get_inst_handle command from the HDL testbench For information on FlexModel supported simulators refer to SmartModel Library Supported Simulators and Platforms Prototype C void flex wait on node const char path FLEX VEC expected value FLEX VEC mask int status Examples Verilog flex wait on node
83. l Command Reference FlexModel User s Manual The wait mode Parameter Many FlexModel commands allow you to specify a wait mode parameter If you set this parameter to true FLEX WAIT T the model pauses until the command completes If you set the wait mode parameter to false FLEX WAIT F the model proceeds directly to the next command in the queue without waiting for the first command to complete The status Parameter All FlexModel commands return a status parameter Depending on the command type this parameter can convey two different types of information e Type 1 Commands that do not return results to the control process For this type the models return a status of 1 if the command completes successfully e Type 2 Commands that return results to the control process For this type the models return a positive integer in the status parameter if the command completes successfully This integer increments by one with each new command of this type so that you can use the status value as a tag to uniquely identify the results you want with results commands as explained in Command Result Identifiers on page 55 For commands of either type that do not complete successfully FlexModels return a status of 0 or a negative integer Negative integers indicate specific error types that you can look up in Table 3 Table 3 Status Parameter Error Codes Error Code Description Fatal Errors Status value range 100 through 199
84. lable on the Synopsys FTP server ftp ftp synopsys com e Licensing QuickStart 142K PDF file This booklet provides instructions for obtaining an electronic copy of your license key file and for installing and configuring SCL on UNIX and Windows NT e Licensing Installation and Administration Guide 2 08M PDF file This guide provides information about installation and configuration key concepts examples of license key files migration to SCL maintenance and troubleshooting You can find general SCL information on the Web at http www synopsys com keys Comments To report errors or make suggestions please send e mail to doc synopsys com To report an error that occurs on a specific page select the entire page including headers and footers and copy to the buffer Then paste the buffer to the body of your e mail message This will provide us with information to identify the source of the problem 12 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 1 FlexModel Overview 1 FlexModel Overview What Are FlexModels FlexModels are binary simulation models that represent the bus functionality of microprocessors cores digital signal processors and bus interfaces FlexModels are essentially advanced SmartModels and therefore use the SWIFT interface FlexModels have the following features e Built with a cycle accurate core and a controllable timing shell so that you can run the model in function
85. lexModel log files and send debug information to Customer Support in the following major sections e Model Versions and History on page 109 e Running FlexModel Diagnostics on page 110 e Creating FlexModel Log Files on page 110 e Sending the Log Files to Customer Support on page 113 For FlexModels that end with an fz extension refer to the SmartModel Library User s Manual for the applicable model logging procedures The logging mechanism described in this chapter applies only to models that end with an fx extension Model Versions and History If you believe a FlexModel is not working correctly first verify the version number of the model you are working with by using the Browser tool SLMC HOMBE bin sl browser to access the model datasheet The History and Version Addendum located at the back of all FlexModel datasheets lists the model s MDL version number You can then compare reported fixes for subsequent versions of that model by reading the model history section in the latest datasheet The latest FlexModel datasheets are available via the Model Directory on the Web http www synopsys com products Im modelDir html For more information on model history refer to the SmartModel Library User s Manual You can contact Customer Support to request the latest version of any model For details on how to get in touch with us refer to Getting Help on page 11 August 28 2001 Synopsys Inc 109 Appen
86. ls are public methods of the ModelFx class You can send FlexModel commands from VERA to the model only through an instance of the ModelFx class Global FlexModel commands see Global FlexModel Command Descriptions on page 61 must also be sent through an instance of the ModelFx class The ModelFx class automatically inherits any new features that are added to the LstModel and SwiftModel classes 48 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 3 FlexModel Command Modes VERA Files in the LMC_HOME Tree Table 1 describes the VERA files installed in your LMC_HOME tree Table 1 VERA Files in the LMC HOME Directory File Name Location Description Istmodel vrh LMC_HOME sim vera src External class declaration for LstModel class swiftmodel vrh LMC_HOME sim vera src External class declaration for SwiftModel class flexmodel_pkg vrh LMC HOME sin vera src External class declaration for the Flex class model pkg vrh LMC HOME models model fx mo del fxversion src vera External class declaration for the model specific ModelFx class Istmodel vr LMC HOME sim vera src Source file for the LstModel class swiftmodel vr LMC_HOME sim vera src Source file for the SwiftModel class flexmodel_pkg vr LMC HOME sin vera src Source file for the Flex class model pkg vr LMC HOME models model fx mo del fxversion src vera VE
87. ls with the different command modes e Using HDL Command Mode on page 39 e Using C Command Mode on page 43 e Using VERA Command Mode on page 47 Using HDL Command Mode In HDL Command Mode FlexModels execute VHDL or Verilog commands contained in the top level system testbench file HDL Command Mode gives you control over the model that is tightly integrated with events in the simulation In this mode you can generate command results create test sequences that loop or branch on command results and synchronize the command flow of several models in a testbench When you use HDL Command Mode the Command Core queues model commands and executes them in the order received Multiple commands can be active simultaneously waiting for results if the model supports pipelining To use HDL Command Mode instantiate a Flex Model in your testbench and then create a command process for the model that includes the FlexModel commands that you want the model to execute Here is a VHDL example of a command process for a FlexModel executing in HDL Command Mode August 28 2001 Synopsys Inc 39 Chapter 3 FlexModel Command Modes FlexModel User s Manual CMD_STREAM process begin wait for CLK_PERIOD assert false report loading commands severity NOTE model configure inst cls code X 112233 status Class Code model configure inst dev id X 4500 status model idle inst 5 FLEX WAIT F status model read req inst X 00000004 X O F
88. me time you create the Mode Fx object the constructor returns at the next positive edge of the clock signal passed in This delay is necessary because the testbench cannot obtain the FlexModel s instance handle until at least one clock period has elapsed If you create the model object and call the new function after some time has elapsed the constructor returns immediately Examples with Top level Testbenches The following two VERA testbench examples show a VERA testbench paired with a Verilog testbench and a VERA testbench paired with a VHDL testbench Note that in the Verilog example the model s constructor advances to the next positive edge of top U1 CLK the clock signal passed in to the constructor before returning In the VHDL example however the model s constructor returns immediately because the testbench has already waited for one clock Example VERA Testbench Paired with Verilog Testbench Verilog Testbench module top myfxmodel U1 CLK CLK RST RST defparam Ul FlexModelId my model VERA Testbench program model test ModelFx instl new my model top U1 CLK 50 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 3 FlexModel Command Modes Example VERA Testbench Paired with Top level VHDL Testbench VHDL Testbench entity top if end top architecture test of top is Ul myfxmodel generic map FlexModelId gt my model port map CLK gt CLK RST gt RS
89. n cannot recognize any other commands During this time the model stores exception information in the Command Core exception queue It is up to the interrupt service routine that you develop to process this exception information after the synchronization occurs For information on developing interrupt service routines refer to FlexModel Interrupts on page 31 August 28 2001 Synopsys Inc 27 Chapter 2 Using FlexModels FlexModel User s Manual If a reset occurs FlexModels execute the reset behavior and either proceed to the next command or resume waiting for the synchronization point if it still hasn t occurred If the number of flex synchronize commands with the same sync_label does not match the num_instance parameter the Command Core reports an error Synchronization Timeouts If not enough flex_synchronize calls are made several models may get stuck waiting for the last call To prevent this problem the flex_synchronize command includes a timeout value When a model receives a flex_synchronize call it waits for timeout clock cycles before declaring that the synchronization operation is complete When this happens all other models waiting on the same sync_label are allowed to proceed Subsequent calls using the same sync label return with an error and are ignored In addition the same label sync_label cannot be used twice For more information about the flex_synchronize command refer to flex_synchronize on page 83
90. n off the hold check from CLKOUT 1h to INT7 ha tms320c6201 set timing control inst VTMS320C6201 TH CLKOUT1 LH INT7 HA FLEX DISABLE status VHDL Example Timing previously enabled with FlexTimingMode parameter for inst Turn off all setup timing checks tms320c6201 set timing control inst TMS320C6201 SETUP FLEX DISABLE status Turn off the hold check from CLKOUT 1h to INT7 ha tms320c6201 set timing control inst TMS320C6201 TH CLKOUT1 LH INT7 HA FLEX DISABLE status 30 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 2 Using FlexModels FlexModel Interrupts Most FlexModels support interrupts of various types based on the physical devices they model For information on the specific interrupt types supported by individual FlexModels refer to the model datasheets This chapter explains how interrupts are detected and serviced by FlexModels and how to write interrupt routines in VHDL Verilog VERA and C Interrupt Service Routines If you want a FlexModel to respond to interrupts you must write an interrupt service routine that specifies how the model handles interrupts of different priorities Check the example testbenches that come with all FlexModels Many of them have basic interrupt service routines that you can copy and modify as needed based on how you want to control FlexModel interrupts in your own testbench e VHDL LMC_HOME models model modelver
91. nand command does a bitwise nand operation on vec and vec2 and puts the result in result Here is the syntax result vecl amp vec2 void flex nand FLEX VEC result const FLEX VEC vecli const FLEX VEC vec2 flex xor The flex xor command does a bitwise xor operation on vec and vec2 and puts the result in result Here is the syntax result vecl vec2 void flex xor FLEX VEC result const FLEX VEC vecli const FLEX VEC vec2 flex xnor The flex xnor command does a bitwise xnor operation on vec and vec2 and puts the result in result Here is the syntax result vecl vec2 void flex xnor FLEX VEC result const FLEX VEC vecli const FLEX VEC vec2 August 28 2001 Synopsys Inc 99 Chapter 5 FlexModel C Testbench Interface FlexModel User s Manual flex to int The flex to int command extracts the right most 32 bits from vec and puts them in the FLEX INT pointed to by i Here is the syntax void flex to int const FLEX VEC vec FLEX INT i For example FLEX INT myInt 0 int i FLEX DEFINE data128 128 h0 flex assign int list datal128 4 0x8889999 Oxaaabbbb Oxcccddd Oxeeeffff data128 h088899990aaabbbbO0cccdddOeeeffff Read the rightmost int from datal28 Extracts Ox 0eeefff into myInt with a warning about the fact that datal28 wider than a single FLEX INT flex to int datal28 amp myInt myInt Ox0eeefff flex to int array The fl
92. nce FlexModel User s Manual Model specific and global commands can generally be used in all FlexModel command modes including HDL Command Mode VERA Command Mode C Command Mode and Direct C Control In addition FlexModels support a set of C functions and operators for use with model commands when working in C Command Mode or with Direct C Control These C functions also have the flex prefix For details on the supported C functions and operators refer to FlexModel Command Reference on page 53 gt Note In VERA Command Mode you use the modelObject prefix instead of the model prefix For more information refer to Command Syntax Differences in VERA Command Mode on page 58 About the Commands FlexModel commands are built with a common underlying architecture to aid readability For example we already saw that model specific commands are easy to identify because they all have the model name as their prefix And of course the command names are intended to describe the functions performed Understanding the meaning of other command components can help improve your productivity working with FlexModels so let s take a look at the key features of FlexModel commands Bus and Zero Cycle Commands Not all FlexModel commands generate bus cycles For example commands that check or modify model characteristics are called zero cycle commands You can execute multiple zero cycle commands without advancing simulator time Commands
93. nstance ModelInstName inst handle status Parameters InstName C instance VHDL ModelInstName Verilog The unique instance name specified as the SWIFT FlexModelID parameter when the model is instantiated inst handle An integer value used as a unique model instance identifier This value must be used in all subsequent FlexModel commands for this model instance status A status of 1 means the command completed successfully A status less than or equal to 0 means the command did not complete successfully Negative integers provide error code information see Table 3 on page 56 Description The flex get inst handle command returns a unique instance handle for use in all subsequent FlexModel commands This must be the first command issued for each FlexModel instance in your design This command can be used in HDL Command Mode or C Command Mode but not in VERA Command Mode see Command Syntax Differences in VERA Command Mode on page 58 In VERA Command Mode you do not need to use this command because the instance handle is automatically issued when an instance of the model s class is created Prototypes C void flex get inst handle const char InstName int inst handle int status August 28 2001 Synopsys Inc 69 Chapter 4 FlexModel Command Reference FlexModel User s Manual VHDL procedure flex get inst handle instance in string inst handle inout integer status out integer Verilog
94. ny is determined by the length of the result vector Empty bit positions are set to zeros Here is the syntax result vec gt gt shiftCnt void flex rshift FLEX VEC result const FLEX VEC vec unsigned int shiftCnt For example FLEX DEFINE rslt8 8 h0 flex lshift rslt8 hf 4 equivalent C rslt8 Oxf lt lt 4 rslt8 hf0 flex Ishift The flex Ishift command shifts the vec vector shiftCnt bits to the left and puts the result in result Truncation if any is determined by the length of the result vector Empty bit positions are set to zeros Here is the syntax result vec lt lt shiftCnt void flex lshift FLEX VEC result const FLEX VEC vec unsigned int shiftCnt For example FLEX DEFINE rslt8 8 h0 August 28 2001 Synopsys Inc 97 Chapter 5 FlexModel C Testbench Interface FlexModel User s Manual flex lshift rslt8 hf 4 equivalent C rslt8 Oxf lt lt 4 rslt8 hf0 flex rrot The flex rrot command rotates the vec vector shiftCnt bits to the right and puts the result in result The rotation point is determined by the size of the result vector Here is the syntax result right rotate vec by shiftCnt void flex rrot FLEX VEC result const FLEX VEC vec unsigned int shiftCnt For example FLEX DEFINE rslt8 8 h0 flex rrot rslt8 rslt8 5 left rotate a rslt8 by 5 bits rslt8 b00010110 rslt8 h07 flex lIrot The flex lrot
95. o a FlexModel The command can only get the value of a single bit net This command provides access to the value of any net in the design from the C program The flex_get_value command only works with simulators that support both HDL and C command control To enable this command you need to establish a connection between the simulator and the command core This is done by invoking the flex_get_inst_handle command from the HDL testbench For information on FlexModel supported simulators refer to SmartModel Library Supported Simulators and Platforms Prototype C void flex get value const char path int value int status Examples flex get value top a amp value amp status 72 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 4 FlexModel Command Reference flex_print_msg Prints a message to the screen Used in all command modes Syntax flex_print_msg inst_handle text status Parameters inst_handle An integer instance handle returned by the flex_get_inst_handle command text A literal string that specifies the message to be output must be enclosed in quotation marks status A status of 1 means the command completed successfully A status less than or equal to 0 means the command did not complete successfully Negative integers provide error code information see Table 3 on page 56 Description The flex print msg command prints the specified text to the screen Prototypes
96. occur void my_intr_handler int valid id priority Get the Model Id and Priority for the interrupt that occured model get intr id priority id amp valid amp priority amp status switch priority case 1 model begin intr id priority amp status Issue commands HERE for priority 1 model end intr id priority amp status case 2 Issue commands HERE for priority 2 break default break end switch priority after this d when an 36 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 2 Using FlexModels Developing VERA Interrupt Routines To use interrupts in VERA Command Mode follow the same procedures described in Developing HDL Interrupt Routines on page 33 However do not include the interrupt signal in the VERA testbench Instead define the interrupt signal in the top level VHDL or Verilog testbench just as if you were in HDL Command Mode Note that in VERA as in HDL you cannot use model commands with the wait_mode parameter set to true FLEX_WAIT_T or result model rslt commands within interrupt routines Defining the Interrupt Signal When you define the interrupt signal in the VERA testbench you must pass in the full path to the signal in the top level VHDL testbench or reg in the top level Verilog testbench The following example shows how to define an
97. odel Diagnostics ined YR CAO HECHO CREAR EROR 110 Creating FlexModel Log Files ouaesctusrkesarakaES A PREGA RR re me 110 Comomad ne 15g d 49d A Ea PIER CIS REOR ORA CR ba dC 111 DONDE LOSTIN 5a XR EE E LESCRRERPARA E RRARRUAERELEREERES AE QR SEA 112 Message LUESIUES suresisrerirsa iperito x dada dr Pee dtes a 113 Sending the Log Files to Customer Support ns danse eed doo ACER CR Ga eos 113 August 28 2001 Synopsys Inc 5 Contents FlexModel User s Manual 6 Synopsys Inc August 28 2001 FlexModel User s Manual Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figures FlexModel Structure and Interface 6945s eee aeee dee 14 FlexModel Structure in LMC HOME Tree o 2sces0casvewsacaveca 13 Pipelmed Bus perations ooreeseded a ededecpibetbekebks dX de dnd 25 Interrupt Detection and Servicing agp de Y HORE ee ERR Y E RES 32 Read req read reli Pair for Testbench lt asisccs das duasniaoredan ds 42 Multiple Commands within a Single Clock Cycle 42 Accessing a C Tesib nch from HDL oo nab cies ed deed 4 Y e XAR ew 43 VERA Model Class Hierarchy 22 46 4c4ivisebsevsssadwneses ave cs 48 August 28 2001 Synopsys Inc 7 Tables FlexModel User s Manual Tables Table 1 VERA Files in the LMC HOME Directory iiis ak ERR ERROR 49 Table 2 Fiex Model Command Types 66 06 6846 name RE RACER ROCA KE dao s 53 Table 3 Status Parameter Error Codes 44 524 dichceoe ne der iR dr
98. only mode for higher performance or with timing mode on when you need to check delays You can switch between timing modes dynamically during simulation using simple commands in your testbench e Feature multiple different control mechanisms You can coordinate model behavior with simulation events synchronize different command processes and control several FlexModels simultaneously using a single command stream e Allow you to use different command sources You can send commands to FlexModels using processes in a Verilog or VHDL testbench a C program or a VERA testbench You can switch between the HDL or VERA testbench and a compiled C program as the source for commands gt Note Multiple command sources are available on simulators that have custom FlexModel integrations Customers using Direct C Control through the standard SWIFT integration must stick with C For more information refer to the Simulator Configuration for Synopsys Models August 28 2001 Synopsys Inc 13 Chapter 1 FlexModel Overview FlexModel User s Manual FlexModel Structure and Interface FlexModels use the SWIFT interface for event based communication with the simulator FlexModels also use a central Command Core that queues model commands for one or more FlexModels in your design The Command Core provides high performance model control without burdening the SWIFT interface Figure 1 illustrates the FlexModel interface HDL Testbench DUT
99. or the lower priority interrupt You can nest interrupt processing this way with as many different interrupt priorities as you want Resets always have the highest priority and cannot be masked FlexModels complete any previously started bus cycle before servicing interrupts as specified in your interrupt service routine For example consider a command stream with nine bus commands Interrupt detection and servicing might proceed as shown in Figure 4 CMD1 CMD2 CMD3 _ INT detected CMD4 CMD5 CMD6 __INT detected INT Serviced CMD7 CMD8 CMD9 INT detected INT Serviced Figure 4 Interrupt Detection and Servicing Once an interrupt is detected and reported FlexModels wait until the interrupt is deasserted and reasserted before recognizing the same interrupt again 32 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 2 Using FlexModels Using Multiple Models You can have more than one FlexModel or multiple instances of the same FlexModel in one HDL testbench If so create separate interrupt service routines for each model instance However you cannot have more than one FlexModel or multiple instances of the same FlexModel in the same C program With C you need to create separate model instantiations Direct C Control or separate programs that you launch with the flex_run_program command HDL Command Mode Each process should have its own interrupt service routine Interrupt D
100. out file you created as described in Running FlexModel Diagnostics on page 110 Then zip the tarball up using gzip and send the zipped log files to Customer Support as an e mail attachment Include your call number if you have one and a description of the problem in the body of your message August 28 2001 Synopsys Inc 113 Appendix A Reporting Problems FlexModel User s Manual 114 Synopsys Inc August 28 2001 FlexModel User s Manual A About This Manual 9 AIX compiling C files 46 B bit_vectors 44 Branching 20 Burst transfers 25 C C Command Mode compiling C file 45 concurrency 43 creating C file 44 errors example 45 example 103 initialization example 44 interrupt example 35 interrupts explanation 33 interrupts using 33 simulation time 43 switching to C 47 using 43 C Command Stream coupled mode 22 mutiple command streams 21 uncoupled mode 22 C interrupt function 63 C program compiling 45 running 75 switching to 47 75 Command Core 14 39 41 Command Interface 17 39 53 command modes 17 39 logging commands 111 organization 21 Command Mode August 28 2001 Index Index HDL defined 39 using HDL 20 39 Command Sequencing 24 Command Suffixes req 55 rslt 55 Command Syntax FLEX commands 59 model commands 61 result identifiers 55 status parameter 56 wait flag 56 Command Types request 26 result 25 26 55 Commands flex clear queue 61 flex define intr function 82
101. program command All model commands in the C program are executed by the model before any subsequent model commands in that VHDL process or Verilog block gt Note You cannot have multiple VHDL processes or Verilog blocks providing commands to the same model instance August 28 2001 Synopsys Inc 43 Chapter 3 FlexModel Command Modes FlexModel User s Manual Keep in mind that integers in HDL are integers in C In C Command Mode std logic vectors and bit vectors used as input values to functions are represented using the FLEX VEC CONST type while return values are represented using the FLEX VEC type Also C functions with return values require you to pass in the address For information about creating and using FLEX VEC vectors for use with FlexModel commands refer to FlexModel C Testbench Interface on page 89 To use C Command Mode refer to the following procedures Creating an External C File on page 44 2 Compiling an External C File on page 45 3 Switching Control to an External C Program on page 47 Creating an External C File Create the external C file according to the following procedure 1 Include the two Synopsys provided header files o flexmodel pkg h This file contains the function prototypes for the generic FlexModel functions Location SLMC HOMEBE sim C src o model pkg h This file contains model specific function prototypes and constants that make the commands easier to use Location
102. provide error code information see Table 3 on page 56 Description The flex run program command switches control to the filename compiled C program The model receives all commands from the C program before any subsequent HDL commands in that VHDL process or Verilog always block gt Note You cannot have multiple VHDL processes or Verilog always blocks providing commands to the same model instance Prototypes VHDL procedure flex run program filename in string status out integer Verilog task flex run program input 8 FLEX CHARMAXCNT 2 1 filename output 31 0 status VERA task run program input filename var integer status August 28 2001 Synopsys Inc 75 Chapter 4 FlexModel Command Reference 76 Examples FlexModel User s Manual The following examples all switch control to a compiled C program named myprogramfile VHDL Example Verilog Example VERA Example flex run program proj asic23 myprogramfile status flex run program proj asic23 myprogramfile status model object run program proj asic23 myprogramfile status Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 4 FlexModel Command Reference flex_set_coupling mode Sets the coupling mode for a model while in C Command Mode Syntax flex_set_coupling_mode inst_handle coupling_mode status Parameters inst_handle An integer instance handle re
103. ram status Parameter status A status of 1 means the command completed successfully A status less than or equal to 0 means the command did not complete successfully Description The flex start program command signals to the Command Core that the C testbench has obtained all the model instance handles needed and is ready to send model commands You must run the flex get inst handle command to retrieve the model instance handle before issuing the flex run program command Also you cannot send other commands to the model until after you run flex start program In summary use the commands in this order 1 flex get inst handle 2 flex start program 3 Other FlexModel commands Prototype C void flex start programQ int status Example C Example main int status int id flex start program amp status Now you can issue model commands August 28 2001 Synopsys Inc 81 Chapter 4 FlexModel Command Reference FlexModel User s Manual flex switch intr control Switches interrupt control to an HDL testbench Used only in C Command Mode Syntax flex switch intr control inst handle status Parameters inst handle An integer instance handle for the model instance under C control status A status of 1 means the command completed successfully A status less than or equal to 0 means the command did not complete successfully Description The flex switch intr control command switches interrupt control for the
104. refer to the Guide to SmartModel Documentation For the latest information on supported platforms and simulators refer to SmartModel Library Supported Simulators and Platforms For detailed information about specific models in the SmartModel Library use the Browser tool SLMC HOME bin sl browser to access the online model datasheets August 28 2001 Synopsys Inc 9 Preface Manual Overview This manual contains the following chapters Preface Chapter 1 FlexModel Overview Chapter 2 Using FlexModels Chapter 3 FlexModel Command Modes Chapter 4 FlexModel Command Reference Chapter 5 FlexModel C Testbench Interface Chapter A Reporting Problems FlexModel User s Manual Describes the contents of this manual and provides references to other sources of information about FlexModels Also describes conventions and terminology used in this manual General information about FlexModel architecture features and benefits How to set up one or more FlexModels in a testbench and use model commands to coordinate the command flows Also how to use FlexModel timing and interrupts How to use the HDL VERA and C command modes to control FlexModels Common features of FlexModel commands and a command reference for global FlexModel commands How to use the FlexModel C functions and operators to define and manipulate FLEX_VEC vectors for use with FlexModel commands How to enable FlexModel lo
105. s we are expecting interrupts to occur so we need to keep the C Testbench running and then switch out of C interrupt mode Desc Demonstrates using flex_ wait and flex_switch_intr_control KCKCKCKCCKCKCKCKCCkCkCk I A AA AA AA A A A A I A I I A f Call flex_wait and tell it to pause for 50 clock cycles We expect all interrupts to be over by this time flex_wait 50 amp nStatus Indicate that now interrupts for instance with id nId needs to be controlled from HDL NOTE This automatically happens once the testbench exits flex switch intr control nId amp nStatus BRK KK KKK KK IK KK I I KK KC I KK A Kk CK K k kK k k kK k kK k k kk kk k Kk kk kk k kk kk k k k k Test 6 Use the slice operations to get parts of a vector Desc Demonstrates use of the slice operations 1 The following loop reads some data from memory read_req and read_rslt 2 Uses the last 8 bits of this data as the increment address KAAKA A ee A AA I AA AA KAA I A I A I I I A f flex_assign ADDRESS hffff0000 for i 0 i lt 16 i A temporary FLEX_VEC with storage FLEX_DEFINE SMALL_ADDRESS 8 FLEX_NULL_VEC model read req nld ADDRESS FLEX WAIT F amp nStatus model read rslt nlId ADDRESS 0 ret data amp nStatus Get bits 24 to 31 last 8 from ret data and save them in SMALL ADDRESS flex slice le SMALL ADDRESS ret data 24 31
106. se 25 results phase 25 Preface 9 Propagation delays 28 R Related documents 9 Request commands 26 Reset 21 28 August 28 2001 Index Result command 25 Results commands 26 55 delayed checking 27 39 from commands 26 model state 26 Results phase 25 S SLC Synopsys Common Licensing 12 SmartModel Browser tool 9 Solaris compiling C files 46 Status Parameter C Command Mode 57 definition 56 types of information 56 std logic vectors 44 Suspending command execution 83 SWIFT Interface 14 Switching to a C program 47 Switching command sources 25 Symbol Conventions 10 sync label parameter 27 Synchronizing command flow 27 39 Synopsys Common Licensing 12 SystemC SWIFT support 17 T Tag checking 66 68 77 Timing access delays 30 Access delays 28 checks checks for timing 28 controlling behavior 28 controlling messages 30 custom timing 28 function only 28 Synopsys Inc 119 Index introduction 28 propagation delays 28 relationships 28 UDT 28 user defined 28 Verilog example 30 VHDL example 30 Timing Version 29 Troubleshooting 109 message log 113 message logging 113 sending a log file 110 stimulus logging 112 trace messages 113 TYP 29 Typographical conventions 10 U User defined timing UDT 28 V Variables flex change setup 23 vector representation 89 Vector Representation in C 89 9 state to 4 state 91 void 91 VERA Command Mode class constructor 49 files in LMC HOME 49 testb
107. se vectors into commands KCKCKCKCKCK KK KK A AA AA A I I A I A IK KK KK Issue a model_read using flex_assign to store the address in ADDRESS and then pass this ADDRESS to the read command flex_assign ADDRESS p00001111111111111111111111110000 model read req nlId ADDRESS FLEX WAIT T amp nStatus Read the results ret data is the array we defined earlier using FLEX DEFINE use the same ADDRESS array defined earlier model read rslt nId ADDRESS 0 ret data amp nStatus Use flex assign to store the result in the array we defined earlier using FLEX DEFINE Note Passing a binary address flex assign act data b10101010101010101010101010101010 Use flex eq to compare the results if flex eq act data ret data flex fprintf stderr Test 2 Failure Mismatch Found n BK RK HK IK KKK KKK KKK KKK I KKK KKK KKK KK KKK KKK CK KICK KK KK K Test 3 Perform multiple Writes looping through the address Desc Demonstrates using the vector operations provided to loop compare e t c The while loop below behaves as follows i It loops as long as data is less than a certain data ii It breaks out of loop if address exceeded value iii If address is equal to a value it skips that address iv Otherwise it does a write increments the address and data KAkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Set
108. setting the Timing Version SWIFT parameter You can also set the timing range MIN TYP or MAX using the DelayRange SWIFT parameter For more information about setting FlexModel SWIFT parameters refer to the Simulator Configuration Guide for Synopsys Models The following examples enable timing mode on model instance my_inst_1 Verilog Example Example using SWIFT template generated by host simulator with timing Timing mode instantiation model defparam ul FlexModelId my inst 1 ul FlexTimingMode FLEX TIMING MODE ON ul TimingVersion timingversion ul DelayRange range ul model ports VHDL Example Example using SWIFT template generated by host simulator with timing U1 model generic map FlexModelID gt my inst 1 FlexTimingMode FLEX TIMING MODE ON TimingVersion timingversion DelayRange gt range port map model ports Selecting Cycle based Mode To enable cycle based mode for a FlexModel set the FlexTimingMode SWIFT parameter to FLEX TIMING MODE CYCLE prepend a backtick for Verilog If you are using Direct C Control set this parameter to 2 The following examples enable cycle based simulation on model instance my inst 1 Verilog Example Example using SWIFT template generated by host simulator Cycle based instantiation model defparam ul FlexModelId my inst 1 ul FlexTimingMode FLEX TIMING MODE CYCLE ul model ports
109. sion examples vhdl model_tst vhd e Verilog LMC_HOME models model modelversion examples verilog model_tst v e C LMC_HOME models model modelversion examples C model_c_commands c You can also use the example interrupt service routines documented in this chapter as starting points e Developing HDL Interrupt Routines on page 33 e Developing C Interrupt Routines on page 35 e Developing VERA Interrupt Routines on page 37 Detecting and Servicing Interrupts Interrupts can only be detected while the HDL or C command source is allowing simulation time to advance FlexModel interrupts are level sensitive the models check for and detect interrupts only on rising clock edges When a FlexModel detects a supported interrupt signal asserted it queues the servicing request To make a FlexModel detect an asynchronous interrupt latch the value so that the model can see the interrupt on the next rising clock edge August 28 2001 Synopsys Inc 31 Chapter 2 Using FlexModels FlexModel User s Manual While responding to an interrupt a FlexModel can detect another interrupt and call the interrupt service routine again as long as simulation time has advanced at least one clock cycle If the new interrupt has a higher priority than the one currently being serviced the model bumps the lower priority interrupt and completes the processing for the higher priority interrupt before returning to and finishing up the processing f
110. specified model instance from C Command Mode to HDL Command Mode Prototype C void flex switch intr control const int inst handle Tnt status Example C Example void my intr function main int status Dnt ra char inst 1 flex get inst handle Inst amp id amp status flex start program amp status flex define intr function id my intr function amp status Now switch interrupt control to HDL flex switch intr control id amp status 82 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 4 FlexModel Command Reference flex_synchronize Synchronize the operation of two or more FlexModels Used in all command modes Syntax flex_synchronize inst_handle sync_total sync_tag sync_timeout status Parameters inst_handle An integer instance handle returned by the flex_get_inst_handle command sync_total A positive integer that specifies the number of model instances to synchronize with sync_tag A text string that uniquely identifies the synchronization for example syncl sync timeout If the sync timeout number of clock cycles elapses before the model receives the sync total number of matching synchronize commands the command times out status A status of 1 means the command completed successfully A status less than or equal to 0 means the command did not complete successfully Negative integers provide error code information see Table 3 on page 56
111. stbench can provide commands to more than one model or model instance This allows two or more models to pass information between each other in proper sequence in a C testbench August 28 2001 Synopsys Inc 21 Chapter 2 Using FlexModels FlexModel User s Manual To use multiple command streams in one C testbench initialize all model instances with the flex get inst handle command before issuing the flex start program command as shown in the following example flex get inst handle InstNamel1 amp idl amp status flex get inst handle InstName2 amp id2 amp status flex start program amp status gt Note If more than one model instance sends commands from a single C testbench the mode is automatically set to uncoupled regardless of the settings used see methods 1 3 in Using Uncoupled Mode in a C Testbench on page 22 Using Uncoupled Mode in a C Testbench Uncoupled mode only affects the C command stream This applies to C Command Mode on simulators with custom integrations and Direct C Control on simulators with standard integrations For information on FlexModel simulator integration refer to the Simulator Configuration Guide for Synopsys Models Uncoupled mode is required to enable the use of multiple command streams in complex models with more than one bus for example It is also useful when you want to drive more than one instance of the same model or multiple models from a single C testbench Coupled mod
112. task flex get inst handle input U des CHARMAXCNT 8 1 ModelInstName output 31 0 inst handle output 31 0 status Examples The following examples return a unique instance handle to the variable tms 1 handle VHDL Example flex get inst handle tms 1 tms 1 handle status tms320c6201 idle tms 1 handle 2 FLEX WAIT T status Verilog Example flex_get_inst_handle ModelInstName tms_l_handle status tms320c6201 idle tms 1 handle 2 FLEX WAIT T status C Example HDL Testbench Instantiation of instance tms 1 model ul FlexModelId gt tms 1 process begin flex run program a out status Same end Name C Testbench main int id status char Inst tms 1 flex get inst handle Inst amp id amp status flex start program amp status 70 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 4 FlexModel Command Reference flex_get_value Gets the single bit value of a specified net in the design while in C Command Mode Syntax flex_get_value path value status Parameters path The hierarchical path of the specified net The path parameter syntax depends upon the simulator you are using Examples of the syntax are given in Table 6 where nets a and b are declared in the testbench which has a top level block called top The command can access any net in the design provided that the full hierarchical pat
113. that generate bus cycles like model write generally take at least one clock cycle to execute The inst handle Parameter Each FlexModel instance in your design needs a unique identifier called an inst handle which you obtain using the flex get inst handle command After you get an inst handle you use that value in the inst handle parameter of all subsequent FlexModel commands For more information refer to Setting Up the Model on page 19 Note that you do not use the inst handle parameter in VERA Command Mode See Command Syntax Differences in VERA Command Mode on page 58 54 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 4 FlexModel Command Reference The reg and rsit Command Suffixes The req and rs t command suffixes are used with request and result commands respectively You combine result commands with corresponding request commands to retrieve data from FlexModels Request commands direct the model to post the data and result commands retrieve the results For more information on how to use request and result commands refer to Pipelining With wait mode Behavior on page 26 Command Result Identifiers You use command result identifiers with result commands to access data posted by request commands There are two types of result identifiers command tags and addr parameters In many cases you use the integer returned in the status parameter of the request command as the cmd tag argument of the paire
114. the inst of the mpc860 fx model executed an idle command for one clock cycle Note that command logs always show the wait mode parameter as false FLEX WAIT F even if the command was issued with the wait mode set to true FLEX WAIT T Commands from a testbench that communicate directly with the Command Core are not logged For example the mpc860 read rslt command does not get logged since it is only accessing results information August 28 2001 Synopsys Inc 111 Appendix A Reporting Problems FlexModel User s Manual Stimulus Logging Model stimulus is logged in a file named model logger v The logger contains a process always block which is sensitive to all the input pins output pins and bidirectional pins This process always block is only invoked when logging is enabled The stimulus logging format is described in Table 10 Table 10 Stimulus Logging Format Entries in File Description timeformat units precision This entry is printed once at the top of the file It lists the time units and precision These values are needed to recreate reported model behavior t time value Time in units that pins were logged ppin number Entry for input pin iinput value ppin number Entry for output pin ooutput value rresolved value ppin number Entry for bidirectional pin bbidir value rresolved value Stimulus Log Example Here is an example of a stimulus log file
115. the same FlexModel in a design without getting the command streams confused After you get an inst handle you use that integer in all subsequent FlexModel commands It is typically the first required argument gt Note You do not use the inst handle parameter in VERA Command Mode See Command Syntax Differences in VERA Command Mode on page 58 Using Multiple FlexModel Instances You can have multiple instances of the same FlexModel in the same simulation If so you must use separate command streams to avoid conflicts Caution You cannot have multiple command streams VERA Verilog VHDL or C sending commands into any one model instance at the same time To use more than one instance of a FlexModel in the same simulation follow these steps for Verilog testbenches 1 When using multiple instances of a FlexModel within one or more top level Verilog testbenches VCS Verilog XL you may see the message Error undefined symbol flex cmd name gt testbench line lt number gt To work around this error add the line undef FLEXMODEL CMDS INC August 28 2001 Synopsys Inc 19 Chapter 2 Using FlexModels FlexModel User s Manual before the line that reads include model pkg inc 2 Qualify all FlexModel commands with their corresponding instance names For example The two instances are called il and i2 mpc740 il The first instance mpc740 i2 The second instance
116. the vec2 value to vec For example void flex assign FLEX VEC veci const FLEX VEC vec2 vecl vec2 flex assign int The flex assign int command assigns the i integer value to vec For example void flex assign int FLEX VEC veci FLEX INT i vecl i flex assign int array The flex assign int array command assigns an integer array to vec using count number of integers from intArray The Oth element of intArray is treated as the left most number and the count 1 th element is treated as the right most number Syntax void flex assign int array FLEX VEC vecl unsigned int count FLEX INT intArray l For example FLEX INT intArray Oxffffeeee Oxddddcccc Oxbbbbaaaa 0x99998888 FLEX DEFINE bigBus 128 FLEX NULL VEC FLEX DEFINE halfAsBigBus 64 FLEX NULL VEC Assign the whole value from the intArray to bigBus flex assign int array bigBus 4 intArray bigBus hffffeeeeddddccccbbbbaaaa99998888 Try to assign the whole value from the intArray to halfAsBigBus flex assign int array halfAsBigBus 4 intArray halfAsBigBus hbbbbaaaa99998888 truncated from left Assign the first two elements from the intArray to halfAsBigBus flex assign int array halfAsBigBus 2 intArray halfAsBigBus hhffffeeeeddddcccc takes the first two elements flex assign int list The flex assign int list command assigns an integer list to vec using count number of FLEX INT
117. till be 1 Look for error messages in the simulation transcript when you first use this command to make sure that you have provided the correct hierarchical path to the signal you want to set on Description The flex set value command sets the value of a specified net in the design The net does not need to be connected to FlexModel The value can only be set for a single bit net This command provides a mechanism to set any design net from the C program The flex set value command only works with simulators that support both HDL and C command control To enable this command you need to establish a connection between the simulator and the command core This is done by invoking the flex get inst handle command from the HDL testbench For information on FlexModel supported simulators refer to SmartModel Library Supported Simulators and Platforms Prototypes C void flex set value const char path const int value int status August 28 2001 Synopsys Inc 79 Chapter 4 FlexModel Command Reference 80 Examples f f lex set val lue top a F lex set val lue top a F EX jOGIC VALUE 1 amp status EX jOGIC VALUE 0 amp status Synopsys Inc FlexModel User s Manual August 28 2001 FlexModel User s Manual Chapter 4 FlexModel Command Reference flex start program Start a C program for a FlexModel Used only in C Command Mode Syntax flex start prog
118. turned by the flex_get_inst_handle command coupling_mode Specify the coupling_mode using one of the following two constants FLEX UNCOUPLED MODE sets mode to uncoupled FLEX FULLY COUPLE MODE sets mode to coupled status A status of 1 means the command completed successfully A status less than or equal to 0 means the command did not complete successfully Negative integers provide error code information see Table 3 on page 56 Description Given a model inst handle the flex set coupling mode command sets the coupling mode for the model FlexModels start up in coupled mode by default Prototype C void flex set coupling mode const int inst handle const int coupling mode int status Example The following example sets the coupling mode to uncoupled for the mpc8260 instl model instance C Example flex set coupling mode mpc8260 instl FLEX UNCOUPLED MODE amp status August 28 2001 Synopsys Inc 77 Chapter 4 FlexModel Command Reference FlexModel User s Manual flex_set_value Sets the single bit value of a specified net in the design while in C Command Mode Syntax flex_set_value path value status Parameters path The hierarchical path of the specified net The path syntax depends upon the simulator you are using Examples of the syntax are given in Table 6 where nets a and b are declared in the testbench which has a top level block called top The command can access any net in the design prov
119. up the start address data bad address and increments flex assign ADDRESS h0000ff00 flex assign DATA h00000000 while flex lte DATA hOO00fffff Check if we have exceeded the address space if flex_gte ADDRESS h0000ffff break Check if address is same as the address we wish to avoid if flex_eq ADDRESS BADADDR flex_incr ADDRESS ADDR INCR continue Else do a write model_write nId ADDRESS DATA FLEX WAIT T amp nStatus Increment the address and data flex incr ADDRESS ADDR INCR flex incr DATA DATA INCR BR KK I KKK kk I IK Ck KK I A KK KKK Ck KKK KKK KKK KKK KKK KKK KKK ke Test 4 Wait for 5 Clks to expire and then synchronize August 28 2001 Synopsys Inc 105 Chapter 5 FlexModel C Testbench Interface FlexModel User s Manual 106 with the HDL testbench Desc Demonstrates using flex wait and synchronize KK A A I eA AA AA Ck KC KC Ck KK CK Kok CK I I I I Stop sending commands for 5 clks flex_wait 5 amp nStatus Synchronize this instance with another instance which is being controlled from HDL both instances are synchronizing on the tag SYN_2 and we are going to wait for 12 clks for the synchronize to complete flex synchronize nlId 2 SYN 2 12 amp nStatus KK IK HK I IK A I I A I KKK KK KKK KKK KKK KKK KKK KKK KKK KKK KKK KK Test 5 Stop the C Testbench a
120. us is not valid flex get cmd status inst tag2 valid f status August 28 2001 Synopsys Inc 67 Chapter 4 FlexModel Command Reference FlexModel User s Manual flex_get_coupling_mode Checks the coupling mode for a model while in C Command Mode Syntax flex_get_coupling_mode inst_handle coupling_mode status Parameters inst_handle An integer instance handle returned by the flex_get_inst_handle command coupling_mode The command returns a coupling_mode value FLEX_UNCOUPLED_MODE FLEX_FULLY_COUPLE_MODE status A status of 1 means the command completed successfully A status less than or equal to 0 means the command did not complete successfully Negative integers provide error code information see Table 3 on page 56 Description Given a model inst handle the flex get coupling mode command returns the coupling mode for the model FlexModels start up in coupled mode by default Prototype C void flex get coupling mode const int inst handle const int coupling mode int status Example The following example returns the coupling mode for the mpc8260 inst1 model instance C Example flex get coupling mode mpc8260_instl amp coupling mode amp status 68 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 4 FlexModel Command Reference flex_get_inst_handle Returns a unique instance handle for the model Not used in VERA Command Mode Syntax flex get inst handle nstName i
121. values from hInt to rhInt For example void flex assign int list FLEX VEC vecli unsigned int count FLEX INT lhiInt FLEX INT rhInt August 28 2001 Synopsys Inc 93 Chapter 5 FlexModel C Testbench Interface FlexModel User s Manual flex incr The flex incr command increments the incrVec vector and puts the result in result For example vec incrVec void flex incr FLEX VEC result const FLEX VEC incrVec flex decr The flex decr command decrements the decrVec vector and puts the result in result For example vec decrVec void flex decr FLEX VEC result const FLEX VEC decrVec flex add The flex add command adds vec and vec2 and puts the result in result For example result vecl vec2 void flex add FLEX VEC result const FLEX VEC vecli const FLEX VEC vec2 flex sub The flex sub command subtracts vec2 from vec and puts the result in result For example result vecl vec2 void flex sub FLEX VEC result const FLEX VEC vecli const FLEX VEC vec2 flex eq The flex eq command returns true if vec is equal to vec2 For example int flex eq const FLEX VEC veci const FLEX VEC vec2 vecl vec2 flex ne The flex ne command returns true if vec is not equal to vec2 For example int flex ne const FLEX VEC vecl const FLEX VEC vec2 vecl vec2 flex It The flex lt command returns true if vec is less than vec2 For example 94 Synopsys Inc August 28
122. versal rsltl16 b1110100100010111 middle 8 bits get changed the others unchanged flex assign rslti16 b1110111111110111 Reinitialize flex slice le offset rsltl6 b0110100100010111 4 11 bit reversal rsltl16 b1110100010010111 middle 8 bits get changed the others unchanged 96 Synopsys Inc August 28 2001 FlexModel User s Manual Chapter 5 FlexModel C Testbench Interface flex slice be offset The flex slice be offset operator does a big endian copy of a bit slice from fromVec to result starting with the specified offset of resultOffsetIdx bit in the result vector Truncation if any occurs on the left side If you specify AIdx greater than rhIdx the bits are reversed in the result vector Here s the syntax void flex slice be offset FLEX VEC result unsigned int resultOffsetIdx const FLEX VEC fromVec unsigned int lhIdx unsigned int rhIdx For example FLEX DEFINE rslt16 16 b1110111111110111 Big endian flex assign rslti16 b1110111111110111 Reinitialize flex slice be offset rs1t16 b0110100100010111 4 11 no bit reversal rsltl6 b1110100100010111 flex assign rslti16 b1110111111110111 Reinitialize flex slice be offset rsltl16 b0110100100010111 11 4 bit reversal rsl1t16 b1110100010010111 flex rshift The flex rshift command shifts the vec vector shiftCnt bits to the right and puts the result in result Truncation if a

FlexModel User`s Manual

Contents

Download Pdf Manuals

Related Search

Related Contents