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SED1355 TECHNICAL MANUAL

1. Issue Date 99 05 18 X23A A 001 11 Page 90 Epson Research and Development Vancouver Design Center FPFRAME gt FPLINE t5 MOD Sync Timing Data Timing FPLINE t6 t8 t9 Di t14 Di t10 gt vk FPSHIFT t12 113 UDIS 0 1 7 LD 3 0 Figure 7 37 8 Bit Dual Monochrome Passive LCD Panel A C Timing Table 7 29 8 Bit Dual Monochrome Passive LCD Panel A C Timing Symbol Parameter Min Typ Max Units t1 FPFRAME setup to FPLINE pulse trailing edge note 2 t2 FPFRAME hold from FPLINE pulse trailing edge 14 Ts note 1 D FPLINE period note 3 t4 FPLINE pulse width 9 Ts t5 MOD delay from FPLINE pulse trailing edge note 4 t6 FPSHIFT falling edge to FPLINE pulse leading edge note 5 t7 FPSHIFT falling edge to FPLINE pulse trailing edge note 6 t8 FPLINE pulse trailing edge to FPSHIFT falling edge t14 2 Ts t9 FPSHIFT period 4 Ts t10 FPSHIFT pulse width low 2 Ts t11 FPSHIFT pulse width high 2 Ts t12 UD 3 0 LD 3 0 setup to FPSHIFT falling edge 2 Ts t13 UD 3 0 LD 3 0 hold to FPSHIFT falling edge 2 Ts t14 FPLINE pulse trailing edge to FPSHIFT rising edge 12 Ts 1 Ts pixel clock period memory clock memory
2. Epson Research and Development Page 87 Vancouver Design Center 7 5 6 16 Bit Single Color Passive LCD Panel Timing la VDP P VNDP gt FPFRAME FPLINE j l fl ESA l l l fl MOD X ges X UD 7 0 LD 7 0 UNE X LINE2 X LINES X LINE4 X XLINE479 LINE480 UNE X LINE2 FPLINE D WI MOD X I HDP pig HN E y SSES Na eg M UD7 A 1 R1 X Bn ES Y 1 G635 x UD6 B1 Y 1 R7 X 1 G12 Y Mi T G636 UD5 G2 X 1 87 X 1 R13 X as x 1 R637 UD4 A 1 R3 Y 1 68 X 11 813 Y Y 1 B637 UD3 A 183 X 1 R9 X 1 G14X X KE 1 G638 UD2 K 1 64 X 1 B9 YX 1 R15 Y YE e __ 1 R639 y UD1 1 R5 X 1 G10 Y 1 B15 Y e X X1 B639 UDO A 1 85 Y 1 R11X 1 G16 Y Na Y 1 G640 y LD7 1 G1 Y 1B6 Y 1 R12 Ve Y 1 R636 LD6 1 R2 X 1 67 X 1 812 D air 111 8636 LD5 1 82 Y 1 R8 Y 1 G13 A x X1 G637 LD4 LTN 188 Y 1 R12Y Y X LD LD3 1 R4 Y 1 G9 X 1 B14 K erz Pe LD2 1 B4 X1 R10X1 G15 X L X AG LD1 A 165 Y 1 B10X 1 R16X D Y1 R640 LDO KX 1 R6 X1 G11X 1 B16 a Ven d Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7 34 16 Bit Single Color Passive LCD Panel Timing VDP Vertical Display Period REG 09h bits 1 0 REG O8h bits 7 0 1 VNDP Vertical Non Display Period REG OAh bits 5 0 1 HDP Horizontal Display Period
3. Power Oscillator Management Generic BUS a gt A 27 21 KN Decoder O KN MIRE z 4 FPDAT 15 8 LN UDIZ 0 5 FPDAT 7 0 LN LDI 7 0 CSn P CS ao FPSHIFT FPSHIFT 4 8 16 bit A 20 0 gt gt AB 20 0 LCD D 15 0 4 Kl DB 15 0 FPFRAME LK FPFRAME Display FPLINE gt FPLINE DRDY LR MOD WEO N WEO SED1 355F0A A WE1 KH WEIS LCDPWR RD P RD L p RDWRE RED GREEN BLUE gt WAITH lq WAITH HRTC NM CRT Ster VETE Display BCLK p BUSCLK 28 sn P RESET z EDIS P RESET EWERS IREF 4 REF H HE za Fas 1Mx16 FPM EDO DRAM Figure 3 5 Typical System Diagram Generic Bus Power Oscillator Management MIPS i BUS E A 25 21 KN Decoder O KN MIRE z 4 FPDAT 15 8 LN UD Z 0 5 FPDAT 7 0 LN LDI 7 0 CSntt KM CS n FPSHIFT p epsHirt 4 8 16 bit A 20 0 KN AB 20 0 LCD D 15 0 4 Kl DE 15 0 FPFRAME FPFRAME Display FPLINE FPLINE DRDY mop MEMW KN WEO SED1 355FOA A SBHE gt WEI LCDPWR gt MEMR RD VDD RED GREEN BLUE __ T rowers Here p CRT RDY 4 WAIT Jere Display BCLK KN BUSCLK RESET po P RESET IREF 4 REF A 11 0 w MA 11 0 D 15 0 wu MD 15 0 WE ld WER RAS RASH LCAS LCAS UCAS UCAS x16 DO DRAM are m FPM
4. VDP VNDP FPFRAME e a8 FPLINE l fl flara l fl l fl l f MOD X ER X UD 3 0 LINE X LINE2 X LINES X LINE4 X XLINE239XLINE240 UNE X LINE2 FPLINE MOD D Ss HDP HNDP d Ha FPSHIFT UD3 Le E EE ME E A A SI X UD2 SS E EE O ER 1318A X UD1 ae 13X17 X X Ne KX 1319 X UDO Se EE E X X gt XX 0 X Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320x240 panel Figure 7 24 4 Bit Single Monochrome Passive LCD Panel Timing VDP Vertical Display Period REG 09h bits 1 0 REG O8h bits 7 0 1 VNDP Vertical Non Display Period REG OAH bits 5 0 1 HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period REG O5h bits 4 0 1 8Ts Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 78 Epson Research and Development Vancouver Design Center ti t2 Sync Timing FPFRAME t3 t4 FPLINE i t5 MOD Data Timing FPLINE t6 t7 t8 d t9 LLN t1 t12 FPSHIFT t13 t14 gt UD 3 0 d 2 X Figure 7 25 4 Bit Single Monochrome Passive LCD Panel A C Timing Table 7 23 4 Bit Single Monochrome Passive LCD Panel A C Timing Symbol Parameter Min Typ
5. z Mono 4 Bit 3 Color 8 Bit Register Mono eel EL EEN Format 2 Notes te 320X240 60Hz E 320X240 60Hz REG O2h 0000 0000 1000 0000 0001 0100 0001 1100 set panel type REG O3h 0000 0000 0000 0000 0000 0000 0000 0000 set MOD rate REG 04h 0010 0111 0010 0111 0010 0111 0010 0111 set horizontal display width REG O5h 0001 0111 0001 0111 0001 0111 0001 0111 set horizontal non display period REG O8h 1110 1111 1110 1111 1110 111 1110 111 set vertical display height bits 7 0 REG 09h 0000 0000 0000 0000 0000 0000 0000 0000 set vertical display height bits 9 8 REG OAh 0011 1110 0011 1110 0011 1110 0011 1110 set vertical non display period REG ODh 0000 1101 0000 1101 0000 1101 0000 1101 set 8 bpp and LCD enable REG 19h 0000 0011 0000 0011 0000 0011 0000 0011 set MCLK and PCLK divide REG 1Bh 0000 0001 0000 0001 0000 0001 0000 0001 disable half frame buffer REG 24h 0000 0000 0000 0000 0000 0000 0000 0000 set Look Up Table address to 0 REG 26h load LUT load LUT load LUT load LUT load Look Up Table Table 12 2 Passive Single Panel E 640x480 with 40MHz Pixel Clock Mono 8 Bit Color 8 Bit Color 16 Bit Register Notes 640X480 60Hz 640X480 60Hz 640X480 60Hz REG 02h 0001 0000 0001 0100 0010 0100 set panel type REG O3h 0000 0000 0000 0000 0000 0000 set MOD rate REG
6. Register Value Notes See Also OB 0000 0000 FPFRAME start position only required for CRT or TFT D TFD 0C 0000 0000 FPFRAME polarity set to active high 0D EE Display mode hardware portrait mode disabled 8 bpp and CN LCD disabled enable LCD in last step of this example OE 1111 1111 Line compare Regs 0Eh and OFh set to maximum allowable OF 0000 0011 value We can change this later if we want a split screen 10 0000 0000 111 nooo BORG Screen 1 Start Address Regs 10h 11h and 12h set to 0 SER ____ This will start the display in the first byte of the display buffer 12 0000 0000 13 0000 0000 14 sean anon Screen 2 Start Address Regs 13h 14h and 15h to offset SEN J0 Screen 2 Start Address in not used at this time 15 0000 0000 16 0100 0000 Memory Address Offset Regs 17h 16h 640 pixels 640 bytes 320 words 140h words Note When setting a horizontal resolution greater than 767 17 0000 0001 pixels with a color depth of 15 16 bpp the Memory Offset Registers REG 16h REG 17h must be set to a virtual horizontal pixel resolution of 1024 18 0000 0000 Set pixel panning for both screens to 0 19 ett Clock Configuration set PCIk to MCIk 2 the specification says Ref j that for a dual color panel the maximum PCIk is MCIk 2 1A 0000 0000 Enable LCD Power 1C 0000 0000 MD Co
7. Power Oscillator Management MC68000 BUS se E SH P Decoder O KN M R z a FPDAT 15 8 ______ _uDI7 0 5 FPDAT 7 0 gt LD 7 0 Lp Decoder O _ CS Si FPSHIFT LN FpsHirt 4 8 16 bit A 20 1 K AB 20 1 LCD D 15 0 4 wl DB 15 0 FPFRAME FPFRAME Display FPLINE gt FPLINE DRDY mop Lose gt ap SED1355F0A A UDS N WEIR LCDPWR ASH Dp Ben RIW P RD WR RED GREEN BLUE _ gt DTACK JW WAIT HRTC LK CRT Arte Display SCHER P BUSCLK S 2 335 RESET KH RESET lt e2 53 REF 4 IREF see D GG 5288 256Kx16 FPM EDO DRAM Figure 3 3 Typical System Diagram MC68K Bus 1 16 Bit 68000 Power Oscillator Management MC68030 BUS a se eel D Decoder O p MIRE z a FPDAT 15 8 LN UD 7 0 5 FPDAT 7 0 LN LDI 7 0 __ Decoder _ CS D FPSHIFT Ll FPsHiFT 4 8 16 bit A 20 0 P AB 20 0 LCD D 3t 16 4 Kl DB 15 0 FPFRAME FPFRAME Display FPLINE gt FPLINE DS KN WEIS DRDY Lu MOD ASH P BSH 4 RW P RD WR SED1355F0A LCDPWR SIZ1 KM RD Sizo P Weo RED GREEN BLUE gt DSACK1 14 WAITH HRTC LN CRT VETO Display 5 HD BOL P BUSCLK E 3 3353 RESET P RESET SEKR DI IREF S KE 256Kx16 FPM EDO DRAM Figure 3 4 Typical System Diagram MC68K Bus 2 32 Bit 68030 SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 17 Vancouver Design Center
8. 00 Pa 4 bit Blue Data 01 1 d FC FD FE EE mes geg geg pen 1 bit per pixel data from Image Buffer Figure 11 4 1 Bit per pixel Color Mode Data Output Path SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 131 Vancouver Design Center 2 Bit per pixel Color Mode Red Look Up Table 256x4 4 bit Red Data EH 00 4 bit Green Data 01 gt 02 10 03 L 11 FC FD SEA FF Gs 00 4 bit Blue Data 01 gt 02 10 03 11 Ec es ED FE FF 2 bit per pixel data from Image Buffer Figure 11 5 2 Bit per pixel Color Mode Data Output Path Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 132 Epson Research and Development Vancouver Design Center 4 Bit per pixel Color Mode Red Look Up Table 256x4 00 m 0000 01 kt 0001 02 0010
9. Epson Research and Development Page 85 Vancouver Design Center 7 5 5 8 Bit Single Color Passive LCD Panel Timing Format 2 P VDP e VNDP gt FPFRAME a a FPLINE l I l l l I j j l I j MOD X S X UD 3 0 LD 3 0 UNE X LINE2 X LINES X LINE4 XLINE479XLINE480 A UNE X LINE2 FPLINE pl MOD X i k HDP 5d HNDP gt FPSHIFT S AAA AA E des UD3 R1 X 1 B3 Y 1 66 X X X RES Sg UD2 as 1 61 YX 1 R4 Y 1 B6 X Y 1 B638 ase UD1 AER AECH YX AA X D X o D Pe UDO R2 X _1 B4X_1 G7X X D X1 G639 WW x X LD3 1 X 1 R5 X_1 87 X X Y 1 B639 SECH 4 Xx LD2 821 XBLA X OS pe 2256 LD1 R3 X 1 B5 X 1 68 X x X Ga E LDO 1 63 X 1 R6 X 1 B8 X 1 B640 o Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7 32 8 Bit Single Color Passive LCD Panel Timing Format 2 VDP Vertical Display Period REG 09h bits 1 0 REG O8h bits 7 0 1 VNDP Vertical Non Display Period REG OAh bits 5 0 1 HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period REG O5h bits 4 0 1 8Ts Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 86 Sync Timing FPFRAME FPLINE Epson Research and Development Vancouver Design Center MOD Data Timing FPLINE FPSHIFT
10. 15 bpp color The Look Up Table is bypassed at this color depth hence programming the LUT is not necessary 16 bpp color The Look Up Table is bypassed at this color depth hence programming the LUT is not necessary SED1355 Programming Notes and Examples X23A G 003 05 Issue Date 99 04 27 Epson Research and Development Page 21 Vancouver Design Center Gray Shade Modes This discussion of gray shade monochrome modes only applies to the panel interface Monochrome mode is selected when register 01 bit 2 0 In this mode the output value to the panel is derived solely from the green component of the LUT The CRT image will continue to be formed from all three RGB Look Up Table components Note In order to match the colors on a CRT with the colors on a monochrome panel it is important to ensure that the red and blue components of the Look Up Table be set to the same intensity as the green component 1 bpp gray shade In 1 bpp gray shade mode only the first two entries of the green LUT are used All other LUT entries are unused Table 4 6 Recommended LUT Values for 1 Bpp Gray Shade Address Required to match CRT to panel Unused entries 2 bpp gray shade In 2 bpp gray shade mode the first four green elements are used to provide values to the panel The remaining indices are unused Table 4 7 Suggested Values for 2 Bpp Gray Shade Required to match
11. 512K Byte Buffer AB 20 0 2M Byte Buffer 000000h Image Buffer Ink Cursor Buffer Half Frame Buffer O7FFFFh Image Buffer 080000h Image Buffer Ink Cursor Buffer Half Frame Buffer OFEFFFh 100000h Image Buffer Ink Cursor Buffer Half Frame Buffer 17EFFFh 180000h Image Buffer EES EE Ink Cursor Buffer Half Frame Buffer LEFFEFh Half Frame Buffer Figure 9 1 Display Buffer Addressing Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 124 Epson Research and Development Vancouver Design Center 9 1 Image Buffer The image buffer contains the formatted display mode data see Display Mode Data Formats The displayed image s could take up only a portion of this space the remaining area may be used for multiple images possibly for animation or general storage See Display Configuration on page 125 for the relationship between the image buffer and the display 9 2 Ink Cursor Buffers The Ink Cursor buffers contain formatted image data for the Ink or Cursor There may be several Ink Cursor images stored in the display buffer but only one may be active at any given time See Ink Cursor Architecture on page 134 for details 9 3 Half Frame Buffer SED1355 In dual panel mode with the half frame buffer enabled the top of the display buffer is allocated to the half frame buffer The size of the half frame buffer is a functio
12. REG 01h RW Refresh Rate Refresh Rate Refresh Rate n a Bit 2 Bit 1 Bit 0 n a WE Control n a Memory Type bits 6 4 DRAM Refresh Rate Select Bits 2 0 These bits specify the divisor used to generate the DRAM refresh rate from the input clock CLKI Table 8 2 DRAM Refresh Rate Selection DRAM Refresh Rate CLKIFrequency Example Refresh Rate 2mple period for Select Bits 2 0 Divisor for CLKI 33MHz 220 refresh cycles at 7 CLKI 33MHz 000 64 520 kHz 0 5 ms 001 128 260 kHz 1 ms 010 256 130 kHz 2 ms 011 512 65 kHz 4 ms 100 1024 33 kHz 8 ms 101 2048 16 kHz 16 ms 110 4096 8 kHz 32 ms 111 8192 4 kHz 64 ms bit 2 WE Control When this bit 1 2 WE DRAM is selected When this bit 0 2 CAS DRAM is selected bit O Memory Type Hardware Functional Specification When this bit 1 FPM DRAM is selected When this bit 0 EDO DRAM is selected This bit should be changed only when there are no read write DRAM cycles This condition occurs when all of the following are true the Display FIFO is disabled REG 23h bit 7 1 and the Half Frame Buffer is disabled REG 1Bh bit 0 1 and the Ink Cursor is inactive Reg 27h bits 7 6 00 This condition also occurs when the CRT and LCD enable bits Reg ODh bits 1 0 have remained 0 since chip reset For further programming information see SED1355 Programming Notes and Examples document number X23A G 003 xx Issue Date 99 05 18 SED1355 X23A A 001 1
13. ROR KKK KK KKK E E E hh RRA e e E I e e e E I I Ae d enum DISP_MODE_LCD 0 DISP_MODE_CRT DISP_MODE_SIMULTANEOUS MAX_DISP_MODE y typedef struct tagHalStruct char szIdString 16 WORD wDetectEndian WORD wSize WORD wDefaultMode BYTE Regs MAX_DISP_MODE MAX_REG 1 DWORD dwClkI Input Clock Frequency in kHz DWORD dwBusClk Bus Clock Frequency in kHz DWORD dwRegAddr Starting address of registers DWORD dwDispMem Starting address of display buffer memory WORD wPanelFrameRate Desired panel frame rate WORD wCrtFrameRate Desired CRT rate WORD wMemSpeed Memory speed in ns WORD wTrc Ras to Cas Delay in ns WORD wTrp Ras Precharge time in ns WORD wTrac Ras Access Charge time in ns WORD wHostBusWidth Host CPU bus width in bits HAL STRUCT typedef HAL STRUCT PHAL_STRUCT ifdef INTEL typedef HAL _STRUCT far LPHAL_ STRUCT telse typedef HAL STRUCT LPHAL_STRUCT tendif Programming Notes and Examples SED1355 Issue Date 99 04 27 X23A G 003 05 Page 98 Epson Research and Development Vancouver Design Center x af FUNCTION PROTO TYPES 27 JE HAL Support Af int seInitHal void int seGetDetectedBusWidth int bits int seRegisterDevice const LPHAL_STRUCT lpHalInfo int Device int seG
14. void main void unsigned char pRegs unsigned char pMem unsigned char pLUT SED1355 X23A G 003 05 218 REGIST ER_OFFSET OxFO 0x00 0x00 0x00 0x00 xFO xFO xFO 0x00 x30 x70 xBO xFO Ore O O x30 x70 xBO Epson Research and Development Vancouver Design Center OxFO 0x30 0x70 OxBO OxFO 0x30 0x70 OxBO O O CO CH ZEO 0x30 0x70 OxBO xFO OxFO OxFO OxFO OxFO 0x30 0x70 OxBO OxFO x30 x70 xBO xFO OxFO 0x30 0x70 OxBO OxFO OxFO OxFO OxFO OxFO OxFO 8192 Programming Notes and Examples Issue Date 99 04 27 nk Cursor Start Address Select Register Epson Research and Development Page 83 Vancouver Design Center unsigned char pTmp unsigned char pCursor long lpCnt int idx int rgb long x y Initialize the chip Step 1 Enable the host interface kk Register 1B Miscellaneous Disable host interfac nabled half frame RE buffer enabled pRegs 0x1B 0x00 0000 0000 Step 2 Disable the FIFO pRegs 0x23 0x80 1000 0000 Step 3 Set Memory Configuration kk Register 1 Memory Configuration 4 ms refresh EDO Af pRegs 0x01 0x30
15. Figure 7 33 8 Bit Single Color Passive LCD Panel A C Timing Format 2 Table 7 27 8 Bit Single Color Passive LCD Panel A C Timing Format 2 Symbol Parameter Min Typ Max Units ti FPFRAME setup to FPLINE pulse trailing edge note 2 t2 FPFRAME hold from FPLINE pulse trailing edge 14 Ts note 1 t3 FPLINE period note 3 t4 FPLINE pulse width 9 Ts t5 MOD delay from FPLINE pulse trailing edge note 4 t6 FPSHIFT falling edge to FPLINE pulse leading edge note 5 t7 FPSHIFT falling edge to FPLINE pulse trailing edge note 6 t8 FPLINE pulse trailing edge to FPSHIFT falling edge t14 2 t9 FPSHIFT period 2 Ts t10 FPSHIFT pulse width low 1 Ts t11 FPSHIFT pulse width high 1 Ts t12 UD 3 0 LD 3 0 setup to FPSHIFT falling edge 1 Ts t13 UD 3 0 LD 3 0 hold to FPSHIFT falling edge 1 Ts t14 FPLINE pulse trailing edge to FPSHIFT rising edge 20 Ts 1 Ts pixel clock period memory clock memory clock 2 memory clock 3 memory clock 4 see REG 1 9h bits 1 0 2 tlmin t8min 14Ts 3 t8min REG 04h bits 6 0 1 8 REG O5h bits 4 0 1 8 Ts 4 tBmin REG 04h bits 6 0 1 8 REG O5h bits 4 0 1 8 1 Ts 5 t6min REG O5h bits 4 0 1 8 28 Ts 6 t7min REG O5h bits 4 0 1 8 19 Ts SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18
16. Symbol Parameter Min Max Units tl Internal memory clock period 25 ns Random read cycle REG 22h bit 6 5 00 5t1 ns t2 Random read cycle REG 22h bit 6 5 01 4t1 ns Random read cycle REG 22h bit 6 5 10 3t1 ns RAS precharge time REG 22h bits 3 2 00 2t1 3 ns 13 RAS precharge time REG 22h bits 3 2 01 1 45t1 3 ns RAS precharge time REG 22h bits 3 2 10 1t1 3 ns RAS to CASH delay time REG 22h bit 4 0 and oH 3 ge bits 3 2 00 or 10 t4 RAS to CASH delay time REG 22h bit 4 1 and un 3 E bits 3 2 00 or 10 RAS to CAS delay time REG 22h bits 3 2 01 1 4511 3 ns t5 CAS precharge time 0 45t1 3 ns t6 CAS pulse width 0 45t1 3 ns t7 RAS hold time 111 3 ns Row address setup time REG 22h bits 3 2 00 2 45 t1 ns t8 Row address setup time REG 22h bits 3 2 01 2t1 ns Row address setup time REG 22h bits 3 2 10 1 45 t1 ns S io address hold time REG 22h bits 3 2 00 or 0 4511 3 AS Row address hold time REG 22h bits 3 2 01 111 3 ns t10 Column address setup time 0 45 t1 3 ns t11 Column address hold time 0 45 t1 3 ns Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 66 Epson Research and Development Vancouver Design Center Table 7 15 EDO DRAM Read Write Read Write Timing Symbol Parameter Min Max Units Read Command Setup REG 22h bit 4
17. configuration for NEC V832 microprocessor Interfacing to the NEC V832 Microprocessor SED1355 Issue Date 99 05 05 X23A G 012 01 Page 14 Epson Research and Development Vancouver Design Center 4 3 NEC V832 Configuration The NEC V832 should access the SED1355 in non burst mode only This is ensured by using any one of the CS3 to CS6 lines to control the SED1355 and setting that line to respond to IO operations using the NEC V832 BCTC register For example if line CS5 is designated to control the SED1355 then bit 5 CT5 of the BCTC register should be set to 1 IO cycle The NEC V832 data bus should be programmed to use 16 bits as the maximum width for SED1355 bus transactions This does not affect the width of other NEC V832 data bus transactions Data bus width is set in the NEC V832 DBC register For example if line CS4 is designated to control the SED1355 then bit 4 BW4 of the DBC register should be set to 1 16 bit bus width Depending on bus clock frequencies a different number of wait states may be required These need to be programmed into the NEC V832 PWCO and PWC1 registers in the bit field corresponding to the CSn line chosen for the SED1355 For example if CS3 controls the SED1355 and one wait state is required then bits 14 12 of the NEC V832 PWCO register WS3 must be set to 001b one wait state If CS6 controls the SED1355 and no wait state is needed then bits 11 8 of the NEC V832 PWC1 register WS6 m
18. 128 Figure 11 2 2 Bit per pixel Monochrome Mode Data Output Pa 128 Figure 11 3 4 Bit per pixel Monochrome Mode Data OutputPath 129 Figure 11 4 1 Bit per pixel Color Mode Data Output bah 130 Figure 11 5 2 Bit per pixel Color Mode Data Output bah 131 Figure 11 6 4 Bit per pixel Color Mode Data Output bah 132 Figure 11 7 8 Bit per pixel Color Mode Data Output bah 133 Figure 12 1 Ink Cursor Data Format 134 Figure 12 2 Cursor Positioning E Beddoes ORR Ae ks Ra ok ae 135 Figure 13 1 Relationship Between The Screen Image and the Image Residing in the Display Buffer 136 Figure 16 1 Mechanical Drawing QFPI5 2 2 e 149 SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 11 Vancouver Design Center 1 Introduction 1 1 Scope This is the Hardware Functional Specification for the SED1355 Embedded RAMDAC LCD CRT Controller Included in this document are timing diagrams AC and DC characteristics register descriptions and power management descriptions This document is intended for two audiences Video Subsystem Designers and Software Developers This specification will be updated as appropriate Please check the Epson Electronics America Website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email
19. Figure 3 6 Typical System Diagram NEC VR41xx MIPS Bus Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 18 Epson Research and Development Vancouver Design Center Power Oscillator Management Philips il PR31500 gt PR31700 BUS C mee F a FPDAT 15 8 p UDO E BS 2 FPDAT 7 0 3 gt LD 7 0 L AB 16 13 D FPSHIFT p FpsHirt 4 8 16 bit A 12 0 B AB 12 0 LCD D 31 16 k DB 15 0 FPFRAME CC FPFRAME Display ALE gt AB20 FPLINE FPLINE CARDREG ki AB19 DRDY _ MOD CARDIORD P AB18 SED1 355FOA CARDIOWR Kap a ARA CARDxCSH w s PERRAS CARDxCSL P RD WR RED GREEN BLUE __ RD P RD S CRT WE P WEo Display CARDxWAIT W WAITH VRTC p DCLKOUT gt BUSCLK 22 85 H RESET KH RESET SEKR IREF 4 REF ee amp GG TETEE lt A 3 35 1Mx16 FPM EDO DRAM Figure 3 7 Typical System Diagram Philips PR31500 PR31700 Bus Power Oscillator Management Toshiba TX3912 BUS MIRE ei Ces z a FPDAT 15 8 LN UD 7 0 SE S FPDAT 7 0 LN LD 7 0 AB 16 13 2 p eeshirr 4 8 16 bit A 12 0 P AB 12 0 al D 23 16 4 p gt DB 15 8 LCD D 31 24 4 P DB 7 0 FPFRAME FPFRAME Disp
20. Hi Z Figure 2 1 NEC V832 Read Write Cycles Interfacing to the NEC V832 Microprocessor Issue Date 99 05 05 SED1355 X23A G 012 01 Page 10 3 SED1355 Host Bus Interface The SED1355 directly supports multiple processors The SED1355 implements a 16 bit PC Card PCMCIA Host Bus Interface which is most suitable for direct connection to the 3 1 Host Bus Interface Pin Mapping SED1355 X23A G 012 01 V832 microprocessor Epson Research and Development Vancouver Design Center The PC Card host bus interface is selected by the SED1355 on the rising edge of RESET After releasing reset the bus interface signals assume their selected configuration For details on SED1355 configuration see Section 4 2 SED1355 Hardware Configuration on page 13 Note At reset the Host Interface Disable bit in the Miscellaneous Disable Register REG 1Bh bit 7 is set to 1 This means that only REG 1 Ah read only and REG 1Bh are accessible until a write to REG 1Bh sets bit 7 to 0 making all regis ters accessible When debugging a new hardware design this can sometimes give the appearance that the interface is not working so it is important to remember to clear this bit before proceeding with debugging The following table shows the functions of each host bus interface signal Table 3 1 Host Bus Interface Pin Mapping SED1355 Pin Name NEC V832 Pin Name AB 20 1
21. Evaluation Board User Manual Issue Date 98 10 30 SDU1355 D9000 X23A G 002 03 Page 14 Epson Research and Development Table 3 1 Connectors Pinout for Channel A7 Continued Vancouver Design Center Channel A7 Pin FPGA Signal SED1355 Signal Pin FPGA Signal SED1355 Signal SmZ 1 chA7p11 N C 21 GND GND 2 chA7p12 N C 22 GND GND 3 chA7p13 A20 23 chA7p34 A19 4 chA7p14 A18 24 GND GND 5 chA7p15 A17 25 GND GND 6 chA7p16 A16 26 GND GND 7 chA7p17 N C 27 chA7p33 A15 8 chA7p18 A14 28 GND GND 9 chA7p19 A13 29 GND GND 10 chA7p20 A12 30 GND GND 11 chA7p21 A11 31 chA7p32 A10 12 chA7p22 AQ 32 GND GND 13 chA7p23 A8 33 GND GND 14 chA7p24 A7 34 GND GND 15 chA7p25 A6 35 GND GND 16 chA7p26 A5 36 chA7p31 A4 17 chA7p27 A3 37 GND GND 18 chA7p28 A2 38 GND GND 19 chA7p29 Al 39 GND GND 20 chA7p30 AO 40 GND GND SDU1355 D9000 X23A G 002 03 Evaluation Board User Manual Issue Date 98 10 30 Epson Research and Development Vancouver Design Center Table 3 2 Connectors Pinout for Channel A6 Page 15 Channel A6 Pin FPGA Signal SED1355 Signal Pin FPGA Signal SED1355 Signal SmXY 1 chA6p1 CS 21 dc5v DC5V 2 chA6p2 BS 22 GND GND 3 chA6p3 WEO 23 dc3v DC3V H chA6p4 RD WR 24 GND GND 5 chA6p5 WAIT 25 dc3v DC3V 6 chA6p6 N C 26 GND GND 7 chA6p7 N
22. Figure 4 1 Typical Implementation of PC Card to SED1355 Interface SED1355 Interfacing to the PC Card Bus X23A G 005 05 Issue Date 99 05 05 Epson Research and Development Vancouver Design Center 4 2 SED1355 Hardware Configuration Page 15 The SED1355 latches MD15 through MDO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the SEDI355 Hardware Functional Specification document number X23A A 001 xx The table below shows only those configuration settings important to the PC Card host bus interface Table 4 1 Summary of Power On Reset Options Po configuration for PC Card host bus interface 4 3 Performance SED1355 value on this pin at rising edge of RESET is used to configure 1 0 Pin Name 1 0 MDO 8 bit host bus interface MD 3 1 MD4 Big Endian MD5 WAIT is active high 1 insert wait state MD11 Alternate Host Bus Interface Selected f l MD12 BUSCLK input divided by two The SED1355 PC Card Interface specification supports a BCLK up to 50MHz and therefore can provide a high performance display solution Interfacing to the PC Card Bus Issue Date 99 05 05 SED1355 X23A G 005 05 Page 16 Epson Research and Development Vancouver Design Center 4 4 Register Memory Mapping SED1355 X23A G 005 05 The SED1355 is a memory mapped device The internal registers require 47 bytes and
23. SDU1355B0C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date D Se z EE 8661 Z2 oen epr owd a Ian u wnoog gl peog uopenjeag sng YSI D08SSELNAS ouj eu deene Eessen uosda Vancouver Design Center Epson Research and Development Hr Issue Date 98 10 30 SDU1355B0C Rev 1 0 ISA Bus Evaluation Board User Manual SED1355B0C Schematic Diagram 2 of 4 Figure 2 ASE Age YZZZZL NN d 10d 400 Bo Cha ED d 619 HIJA A ONS x00 EI ho la anro SCH FETE 819 ed D 9 2222 00 lt Do 8 o 6666 22 5 386 TEE DOAS xor o oa 55 3 zz 938 E ze EE 2 a TOON m ar WD gt e umdao7 seu oons yh boy z 104 MOOT eza D MOS Ar BR mosanzy e aosany Zb yoy Ag any E Lio 910 sio E yo D HAGA ruu meee ONS 2 E hoe Hehee rr anyo elo os Z 9999999 23 Y oO H D ZZZZzZZ m o H Si 0000000 S E I ec ge SOK 43834 3 3 m x a H 91SON lt _ a0n awa SH Sean THOT ap sanaasns i Ser a en Sal St Zev Sec Ti GI d Rea n kee Sie S SP OS39WLO LIN SSA 30 te LIT Zi Cal a pax erx mmx T am DIN ji isvon ES T sp aen 8 dia MS Fer 5 SLON y UF ELO TT 9 eran H SAN r yan vr EAN
24. The HAL library detected that the requested color depth bit per pixel will violate the SED1355 hardware specification for clocks To reprogram the clocks run 1355CFG and select the desired color depth bit per pixel 1355BMP Demonstration Program SED1355 Issue Date 98 10 30 X23A B 006 03 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 1355BMP Demonstration Program X23A B 006 03 Issue Date 98 10 30 EPSON SED1355 Embedded RAMDAC LCD CRT Controller 1355PWR Software Suspend Power Sequencing Utility Document Number X23A B 007 02 Copyright 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 1355PWR Software Suspend Power Sequencing Utility X23A B 007 02 Issue Date 98 10 30 Epson Resear
25. int seMoveCursor int seReservedl long x long y int seSetCursorColor int seReservedl int index DWORD color int seSetCursorPixel int seReservedl long x long y DWORD color int seDrawCursorLine int seReservedl long xl long yl long x2 long y2 DWORD color int seDrawCursorRect int seReservedl long xl long yl long x2 long y2 DWORD color BOOL SolidFill int seDrawCursorEllipse int seReservedl long xc long yc long xr long yr DWORD color BOOL SolidFill int seDrawCursorCircle int seReservedl long xCenter long yCenter long radius DWORD color BOOL SolidFill Hardware Ink Layer int seInitInk int seReservedl int seInkOff int seReservedl int seGetInkStartAddr int seReservedl DWORD addr int seSetInkColor int seReservedl int index DWORD color int seSetInkPixel int seReservedl long x long y DWORD color Programming Notes and Examples SED1355 Issue Date 99 04 27 X23A G 003 05 Page int i int int 0 100 seDrawInkLine int seReservedl long x1 long yl seDrawInkRect int seReservedl long x1 long yl seDrawInkEllipse int seReservedl long xc long yc or BOOL SolidFill int col ji i BOOL SolidFill d e i r long x2 long x2 long xr Epson Research and Development Vancouver Design Center long y2 DWORD color long y2 DWORD color long yr DWORD seDrawInkCircle i
26. 0011 0000 JK Step 4 Set Performance Enhancement 0 register Wi pRegs 0x22 0x24 0010 0100 Step 5 Set the rest of the registers in order x Register 2 Panel Typ 16 bit format 1 color dual passive el pRegs 0x02 0x26 0010 0110 Register 3 Mod Rate Wi pRegs 0x03 0x00 0000 0000 Jk Register 4 Horizontal Display Width HDP 640 pixels SCH 640 8 1 79t 4Fh El pRegs 0x04 0x4f 0100 1111 Ex Register 5 Horizontal Non Display Period HNDP ER PCLK Programming Notes and Examples SED1355 Issue Date 99 04 27 X23A G 003 05 Page 84 kk d Pp kk d p kk d SE kk kk d p p kk kk kk kk d L kk d Pp kk d p kk d p kk kk d LE is achieved Regs 0x05 Register 6 Regs 0x06 Register 7 Regs 0x07 Epson Research and Development Vancouver Design Center Frame Rat Ka HDP HNDP VDP VNDP 16 500 000 Ox1F HRTC FPLINE 0x00 HRTC FPLINE 640 HNDP 480 VNDP HNDP and VNDP must be calculated such that the desired frame rate 0001 1111 Start Position applicable to CRT TFT only 0000 0000 Pulse Width applicable to CRT TFT only 0x00 Registers 8 Regs 0x08 Regs 0x09 Register A Regs 0x0A Register B Regs 0x0B Register C
27. Address input AB18 should be connected to the PR31500 PR31700 signal CARDIORD Either AB18 or the RD input must be asserted for a read operation to take place Address input AB17 should be connected to the PR31500 PR31700 signal CARDIOWR Either AB17 or the WEO input must be asserted for a write operation to take place Address inputs AB 16 13 and control inputs M R CS and BS must be tied to Vpp as they are not used in this interface mode Address inputs AB 12 0 and the data bus DB 15 0 connect directly to the PR31500 PR31700 address and data bus respectively MD4 must be set to select the proper endian mode on reset see Section 4 2 SED1355 Configuration on page 10 Because of the PR31500 PR31700 data bus naming convention and endian mode SED1355 DB 15 8 must be connected to PR31500 PR31700 D 23 16 and SED1355 DB 7 0 must be connected to PR31500 PR31700 D 31 24 Control inputs WE1 and RD WR should be connected to the PR31500 PR31700 signals CARDxCSH and CARDxCSL respectively for byte steering Input RD should be connected to the PR31500 PR31700 signal RD Either RD or the AB 18 input CARDIORD must be asserted for a read operation to take place Input WEO should be connected to the PR31500 PR31700 signal WR Either WEO or the AB17 input CARDIOWR must be asserted for a write operation to take place WAIT is a signal output from the SED1355 that indicates the host CPU must wait until data is ready
28. gt RDY t13 5 t14 i D 15 0 write t15 t16 gt es D 15 0 read Figure 7 1 SH 4 Timing Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 42 Epson Research and Development Vancouver Design Center Note The SH 4 Wait State Control Register for the area in which the SED1355 resides must be set to a non zero value The SH 4 read to write cycle transition must be set to a non zero value with ref erence to BUSCLK Table 7 1 SH 4 Timing 3 0V 5 0VP Symbol Parameter Min Max Min Max Units D Clock period 15 15 ns t2 Clock pulse width high 6 6 ns t3 Clock pulse width low 6 6 ns H A 20 0 M R RD WR setup to CKIO 3 3 ns t5 A 20 0 M R RD WR hold from CS 0 0 ns t6 BSF setup 4 4 ns t7 BS hold 1 1 ns t8 CSn setup 4 4 ns 19 Falling edge RD to D 15 0 driven 0 0 ns t10 Rising edge CSn to RDY tri state 5 25 2 5 10 ns t11 Falling edge CSn to RDY driven 0 15 0 10 ns t12 CKIO to WAIT delay 4 20 3 6 12 ns t13 D 15 0 setup to 2 4 CKIO after BS write cycle 10 10 ns t14 D 15 0 hold write cycle 0 0 ns t15 D 15 0 valid to RDY falling edge read cycle 0 0 ns t16 Rising edge RD to D 15 0 tri state read cycle 5 25 2 5 10 ns 2 Two Software WAIT States Required b One Software WAIT State Required 1
29. on page 22 The bus can support both normal and burst cycles Burst memory cycles are used to fill on chip cache memory and for certain on chip DMA operations Normal cycles are used for all other data transfers SED1355 Interfacing to the Motorola MPC821 Microprocessor X23A G 008 03 Issue Date 99 05 05 Epson Research and Development Page 9 Vancouver Design Center 2 2 1 Normal Non Burst Bus Transactions TSIZ 0 1 AT O 3 X A Dina KXXXMXAXMAAXMAXMAAXMAXMAAX AKA Sampled when TA low Transfer Start Wait States Transfer Next Transfer Complete Starts A data transfer is initiated by the bus master by placing the memory address on address lines AO through A31 and driving TS Transfer Start low for one clock cycle Several control signals are also provided with the memory address e TSIZ 0 1 Transfer Size indicates whether the bus cycle is 8 16 or 32 bit e RD WR set high for read cycles and low for write cycles e AT 0 3 Address Type Signals provides more detail on the type of transfer being attempted When the peripheral device being accessed has completed the bus transfer it asserts TA Transfer Acknowledge for one clock cycle to complete the bus transaction Once TA has been asserted the MPC821 will not start another bus cycle until TA has been de asserted The minimum length of a bus transaction is two bus clocks Figure 2 1 Power PC Memory Read Cycle on page 9 illustrates a typical me
30. pixels The value of Color must be 0 to 3 Values 0 and 1 refer to the two user definable colors If Color is 2 then the pixel will be transparent and if the value is 3 the pixel will be an inversion of the underlying screen color Currently seDrawCursorCircle does not support the solid fill option Parameters DevID aregistered device ID x y center of the circle in pixels Radius radius of the circle in pixels Color 0 to 3 value to draw the circle with SolidFill flag to solid fill the circle currently not used Return Value ERR_OK operation completed with no problems The functions in this section support the hardware ink layer Overall these functions are nearly identical to the hardware cursor routines In fact the same SED1355 hardware is used for both features which means that only the cursor or the ink layer can be active at any given time The difference between the hardware cursor and the ink layer is that in cursor mode the image is a maximum of 64x64 pixels and can be moved around the display while in ink layer mode the image is as large as the physical size of the display and is in a fixed position Both the Ink layer and Hardware cursor have the same number of colors and handle these colors identically int selnitInk int DevID Description This routine prepares the ink layer for use This consists of determining the start address for the ink layer setting the ink layer to the transparent colo
31. 0000 0000 set MOD rate REG 04h 0100 1111 0100 1111 0100 1111 0100 1111 set horizontal display width REG O5h 0000 0101 0000 0101 0000 0101 0000 0101 set horizontal non display period REG 08h 1110 1111 1110 1111 1110 1111 1110 1111 set vertical display height bits 7 0 REG 09h 0000 0000 0000 0000 0000 0000 0000 0000 set vertical display height bits 9 8 REG OAh 0011 1110 0011 1110 0011 1110 0011 1110 set vertical non display period REG ODh 0000 1101 0000 1101 0000 1101 0000 1101 set 8 bpp and LCD enable REG 19h 0000 0010 0000 0010 0000 0010 0000 0010 set MCLK and PCLK divide REG 1Bh 0000 0000 0000 0000 0000 0000 0000 0000 enable half frame buffer REG 24h 0000 0000 0000 0000 0000 0000 0000 0000 set Look Up Table address to 0 REG 26h load LUT load LUT load LUT load LUT load Look Up Table Table 12 4 TFT Single Panel 640x480 with 25 175 MHz Pixel Clock A Color 16 Bit Register SiOx OH Notes REG 02h 0010 0101 set panel type REG 03h 0000 0000 set MOD rate REG 04h 0100 1111 set horizontal display width REG 05h 0001 0011 set horizontal non display period REG 06h 0000 0001 set HSYNC start position REG 07h 0000 1011 set HSYNC polarity and pulse width REG O8h 1101 1111 set vertical display height bits 7 0 REG O9h 0000 0001 set vertical display height bits 9 8 REG OAh 0010 1011 set vertical non display period REG OBh 0000 1001 set VSYNC start position REG OCh 0000 0001 set VSYNC polari
32. 3 2 00 Read Command Setup REG 22h bit 4 0 and bits 3 45 11 3 As ae 3 2 01 or 10 Read Command Setup REG 22h bit 4 1 and bits 3 45 11 3 de 3 2 00 Read Command Setup REG 22h bit 4 1 and bits 3 2 01 or 10 2 45t1 3 ns Read Command Hold REG 22h bit 4 0 and bits 3 411 3 ns 2 00 Read Command Hold REG 22h bit 4 0 and bits 3 311 3 ns H3 2 01 or 10 Read Command Hold REG 22h bit 4 1 and bits 3 311 3 ns 2 00 Read Command Hold REG 22h bit 4 1 and bits 3 211 3 ns 2 01 or 10 t14 Read Data Setup referenced from CAS 5 ns t15 Bus Tri State 3 t1 5 ns t16 Write Command Setup 0 45 t1 3 ns t17 Write Command Hold 0 45 t1 3 ns t18 Write Data Setup 0 45 t1 3 ns t19 Write Data Hold 0 45 t1 3 ns t20 MD Tri state 0 45 t1 0 45t1 21 ns 121 CASH to WE active during Read Write cycle 0 45 t1 3 ns SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Vancouver Design Center 7 3 5 FPM DRAM CAS Before RAS Refresh Timing t1 Memory Clock t2 D RAS t4 t5 t6 Page 73 Figure 7 20 FPM DRAM CAS Before RAS Refresh Timing Table 7 19 FPM DRAM CAS Before RAS Refresh Timing Symbol Parameter Min Max Units ti Internal memory clock period 40 ns iS RAS precharge time REG 22h bits 3 2 00 2 45 11 3 ns RAS precharge tim
33. 4 2 Look Up Table Organization e The Look Up Table treats the value of a pixel as an index into an array of colors or gray shades For example a pixel value of zero would point to the first LUT entry a pixel value of 7 would point to the eighth LUT entry e The value inside each LUT entry represents the intensity of the given color or gray shade This intensity can range in value between 0 and OFh e The SED1355 Look Up Table is linear increasing the LUT entry number results in a lighter color or gray shade For example a LUT entry of OFh into the red LUT entry will result in a bright red output while a LUT entry of 5 would result in a dull red Table 4 1 Look Up Table Configurations Display Mode 4 Bit Wide Look Up Table Eflective Gray Shade Colors on an Passive Panel RED GREEN BLUE 1 bpp gray E 2 2 gray shades 2 bpp gray 4 4 gray shades 4 bpp gray 16 16 gray shades 8 bpp gray 16 16 gray shades 15 bpp gray 16 gray shades 16 bpp gray 16 gray shades 1 bpp color 2 2 2 2 colors 2 bpp color 4 4 4 4 colors 4 bpp color 16 16 16 16 colors 8 bpp color 256 256 256 256 colors 15 bpp color 4096 colors 16 bpp color 4096 colors On an active matrix panel the effective colors are determined by the interface width i e 9 bit 512 12 bit 4096 18 bit 64K colors Passive panels are limited to 12 bits through the Frame Rate Modulator SF
34. CS5 to O5FF FFFFh 0520 0000h Display buffer 2M bytes 0600 0000h 0600 0000h Registers CS6 to OGFF FFFFh 0620 0000h Display buffer 2M bytes Each address range is 16M bytes therefore the SED1355 is aliased four times over the address range Interfacing to the NEC V832 Microprocessor SED1355 Issue Date 99 05 05 X23A G 012 01 Page 16 Epson Research and Development Vancouver Design Center 5 Software Test utilities and Windows CE v2 0 display drivers are available for the SED1355 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 1355CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The SED1355 test utilities and Windows CE v2 0 display drivers are available from your sales support contact or www eea epson com SED1355 Interfacing to the NEC V832 Microprocessor X23A G 012 01 Issue Date 99 05 05 Epson Research and Development Page 17 Vancouver Design Center 6 References 6 1 Documents NEC Electronics Inc V832 Preliminary Users Manual Document Number U13577EJ1 VOUMOO Epson Research and Development Inc SED1355 Hardware Functional Specification Document Number X23A A 001 xx Epson Research and Development Inc SDUI355BOC Rev 1 0 ISA B
35. Email wince erd epson com we http www erd epson com Taiwan R O C Epson Taiwan Technology 8 Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 VDC Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft Windows and the Windows CE Logo are registered trademarks of Microsoft Corporation ey X23A C 002 13 3 EPSON SED1355 Embedded RAMDAC LCD CRT Controller Hardware Functional Specification Document Number X23A A 001 11 Copyright 1998 1999 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims
36. Min Max Units ti Clock period 20 20 ns t2 Clock pulse width high 6 6 ns t3 Clock pulse width low 6 6 ns t4 A 20 0 M R setup to first CLK where CS 0 and either 10 10 AS RDO RD1 WE0 or WE1 0 15 A 20 0 M R hold from rising edge of either RDO RD1 WE0 or 0 0 ns WEI 0 t6 CS hold from rising edge of either RDO RD1 WE0 or WEIS 0 0 0 ns t71 Falling edge of either RDO RD1 WE0 or WE1 to WAIT driven low 0 15 0 10 ns t8 Rising edge of either RDO RD1 WE0O or WE1 to WAIT tri state 5 25 25 10 ns 19 D 15 0 setup to third CLK where CS 0 and WEO WE1 0 write 10 10 ae cycle t10 D 15 0 hold write cycle 0 0 ns t117 Falling edge RDO RD1 to D 15 0 driven read cycle 0 0 ns t12 D 15 0 setup to rising edge WAIT read cycle 0 0 ns t13 Rising edge of RDO RD1 to D 15 0 tri state read cycle 5 25 5 10 ns 1 Ifthe SED1355 host interface is disabled the timing for WAIT driven low is relative to the falling edge of RDO RD1 WEO WEIS or the first positive edge of CLK after A 20 0 M R becomes valid whichever one is later 2 Ifthe SED1355 host interface is disabled the timing for D 15 0 driven is relative to the falling edge of RDO RD 1 or the first positive edge of CLK after A 20 0 M R becomes valid whichever one is later SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 53 Vancouver Design Center 7 1
37. One bit pixels provide two gray shade color possibilities For monochrome panels the two gray shades are generated by indexing into the first two elements of the green component of the Look Up Table LUT For color panels the two colors are derived by indexing into positions O and 1 of the Look Up Table 3 1 2 Memory Organization for Two Bit Per Pixel 4 Colors Gray Shades Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pixel 0 Bit 1 Pixel 0 Bit 0 Pixel 1 Bit 1 Pixel 1 Bit O Pixel 2 Bit 1 Pixel 2 Bit O Pixel 3 Bit 1 Pixel 3 Bit 0 SED1355 X23A G 003 05 Figure 3 2 Pixel Storage for 2 Bpp 4 Colors Gray Shades in One Byte of Display Buffer In this memory format each byte of display buffer contains four adjacent pixels Setting or resetting any pixel will require reading the entire byte masking out the appropriate bits and if necessary setting the bits to 1 Two bit pixels are capable of displaying four gray shade color combinations For monochrome panels the four gray shades are generated by indexing into the first four elements of the green component of the Look Up Table For color panels the four colors are derived by indexing into positions 0 through 3 of the Look Up Table Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 13 Vancouver Design Center 3 1 3 Memory Organization for F
38. REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period REG O5h bits 4 0 1 8Ts Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 88 Epson Research and Development Vancouver Design Center Sync Timing uw d S FPFRAME H 13 FPLINE t5 MOD Data Timing FPLINE FPSHIFT UD 7 0 LD 7 0 Figure 7 35 16 Bit Single Color Passive LCD Panel A C Timing Table 7 28 16 Bit Single Color Passive LCD Panel A C Timing Symbol Parameter Min Typ Max Units ti FPFRAME setup to FPLINE pulse trailing edge note 2 t2 FPFRAME hold from FPLINE pulse trailing edge 14 Ts note 1 t3 FPLINE period note 3 t4 FPLINE pulse width 9 Ts t5 MOD delay from FPLINE pulse trailing edge note 4 t6 FPSHIFT falling edge to FPLINE pulse leading edge note 5 t7 FPSHIFT falling edge to FPLINE pulse trailing edge note 6 t8 FPLINE pulse trailing edge to FPSHIFT falling edge t14 3 Ts t9 FPSHIFT period 5 Ts t10 FPSHIFT pulse width low 2 Ts t11 FPSHIFT pulse width high 2 Ts t12 UD 7 0 LD 7 0 setup to FPSHIFT falling edge 2 Ts t13 UD 7 0 LD 7 0 hold to FPSHIFT falling edge 2 Ts t14 FPLINE pulse trailing edge to FPSHIFT rising edge 20 Ts 1 Ts pixel clock period memory clock memory clock 2 memory clock 3 memory clock 4 see REG 1 9h bits 1 0 2 tlmin t8min 14Ts 3 tSmin
39. REG 1Eh GENERAL IO PINS CONFIGURATION REGISTER 0 RW GPIO3 Pin GPIO2 Pin GPIO1 Pin n a n a n a na 10 Config 10 Config 10 Config n a REG 1Fh GENERAL IO PINS CONFIGURATION REGISTER 1 RW REG 20h GENERAL IO PINS CONTROL REGISTER 0 n a n a n a n a GPIO3 Pin IO Status GPIO2 Pin IO Status GPIO1 Pin IO Status Screen 1 Line Compare nla bla n a ES ila n a Ge es REG 21h GENERAL IO PINS CONTROL REGISTER 1 RW f pen n a n a n a n a n a n a n a REG 10h SCREEN 1 DISPLAY START ADDRESS REGISTER 0 RW Bit 7 Bit 6 Bit 5 Bit 4 Screen 1 Start Address Bit 3 Bit 2 Bit 1 Bit 0 Page 1 REG 2Fh INK CURSOR C OLOR 1 REGISTER 1 Bit 15 Bit 14 REG 30h INk CURSOR START ADDRESS SELECT REGISTER Bit 13 Cursor Bit 12 Bit 7 WO Bit 6 Bit 5 Ink Cursor Start Address Select Bit 4 Bit 3 REG 31h ALTERNATE FRM REGISTER RW Alternate Frame Range Modulation Select Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes 1 These bits are used to identify the SED1355 For the SED1355 the product code should be 3 The host interface must be enabled before reading this register set REG 1B b7 0 2 N A bits should be writte n 0 Reserved bits must be written 0 98 09 15 SED1355F0A Register Summary 3 DRAM Refresh Rate Select Rate Select Bits alli RatoforCLKlz 256 refresh cycles
40. Table 8 13 Table 8 14 Table 8 15 Table 8 16 Table 8 17 Table 8 18 Table 8 19 Table 9 1 Table 12 1 Table 12 2 Table 13 2 Table 14 1 Table 14 2 Table 14 3 Table 14 4 Table 14 5 Table 14 6 Table 15 1 Table 15 2 SED1355 X23A A 001 11 Epson Research and Development Vancouver Design Center 8 Bit Single Color Passive LCD Panel A C Timing Format 2 o oo 86 16 Bit Single Color Passive LCD Panel A C Timing 88 8 Bit Dual Monochrome Passive LCD Panel A C TiMidg8 o 90 8 Bit Dual Color Passive LCD Panel A C Timing e 92 16 Bit Dual Color Passive LCD Panel A C Timing 94 TET D TED A C Timings eae kay Hie are e A A AA a ads 97 SED1393 Addressing 4 5 845 eee A eee tr do ed 100 DRAM Refresh Rate Selection 2 2 20 00 0000000000002 e eae 101 Panel Data Width Selection 102 EPEINE Polarity Selection eier aa eee Fe ALP ER OA Ste AI da BR Os 104 FPFRAME Polarity Selecti0d e 106 Simultaneous Display Option Selection e 107 Bit per pixel Selection comica Sad a BSR eg SE do 108 Pixel P nning Selection sorai oe aer ve Baw ea bee bed ee hei bee CN 111 PCEK Divide S lection satsi eech a Dk RA Me Mie Sa ee ey Bed 112 Suspend Refresh Selection 2 2 0 ee 112 MA GPIO Pin Functionality 2 ee ee 114 Minimum Memory Timing Selection 00000000000
41. The following commands are valid within the 1355PLAY program b 8116 z command f w addrl addr2 data h lines i LCD CRT l index red green blue la m bpp SED1355 X23A B 005 03 1355PLAY Diagnostic Utility Issue Date 98 10 30 Epson Research and Development Page 5 Vancouver Design Center p 110 Set power mode hardware suspend 1 set hardware suspend 0 reset hardware suspend This command is only supported on a SDU1355 evaluation board for the PC platform q Quits the 1355PLAY utility r w addr count Reads number of bytes or words w from the address specified by addr If count is not specified then 16 bytes words are read v Calculates the frame rate from VNDP count PC w w addr data platform only Writes bytes or words w of data to the address specified by addr Data can be multiple values e g W 0 1 2 3 4 writes the byte values 1 2 3 4 starting at address 0 x w index data Reads writes bytes or words w to from the registers xa 1355PLAY Example A Writes data to REG index when data is specified Reads data from REG index when data is not specified Some platforms may provide upredictable results when non aligned word addresses are entered Reads all registers Displays Help information Type 1355PLAY to start the program Type for help Type i to initialize the registers Type xa to
42. and click on Properties to bring up the X86 DEMO7 Properties window i Replace the string DEMO1 under the entry Target with DEMO7 j Click on OK to finish Create a sub directory named SED1355 under wince platform cepc drivers display Copy the source code to the SED1355 subdirectory Add an entry for the SED1355 in the file wince platform cepc drivers display dirs Modify the file CONFIG BIB using any text editor such as NOTEPAD to set the system RAM size the SED1355 IO port and display buffer address mapping Note that CONFIG BIB is located in X wince platform cepc files where X is the drive letter Since the SDU1355BOC maps the IO port to OxE00000 and memory to 0xC00000 the CEPC machine should use the CMOS setup to create a 4M byte hole from address 0xC00000 to OxFFFFFF The following lines should be in CONFIG BIB NK 80200000 00500000 RAMIMGE RAM 80700000 00500000 RAM Note SED 1355 H should include the following define PhysicalVmemSize 0x00200000L define PhysicalPortAddr Ox00E00000L define PhysicalVmemAddr Ox00C00000L Edit the file PLATFORM BIB located in X wince platform cepc files to set the default dis play driver to the file SED1355 DLL SED1355 DLL will be created during the build in step 13 You may replace the following lines in PLATFORM BIB IF CEPC_DDI_VGA2BPP ddi dll _FLATRELEASEDIR ddi_vga2 dll NK SH ENDIF Windows CE Display
43. between the endpoints x1 y1 and x2 y2 The value of Color must be 0 to 3 Values 0 and 1 refer to the two user definable colors If Color is 2 then the pixel will be transparent and if the value is 3 the pixel will be an inversion of the underlying screen color Parameters DevID aregistered device ID x1 y1 first endpoint of the line in pixels x2 y2 second endpoint of the line in pixels Color a value from 0 to 3 to draw the line with Return Value ERR Ok operation completed with no problems int seDrawInkRect int DevID long x1 long y1 long x2 long y2 DWORD Color BOOL SolidFill Description Draws a rectangle of color Color and optionally fills it The upper left corner of the rectangle is the point x1 y1 and the lower right corner of the rectangle is the point x2 y2 The value of Color must be 0 to 3 Values 0 and 1 refer to the two user definable colors If Color is 2 then the pixel will be transparent and if the value is 3 the pixel will be an inversion of the underlying screen color Parameters DevID aregistered device ID x1 y1 upper left corner of the rectangle in pixels x2 y2 lower right corner of the rectangle in pixels Color a two bit value 0 to 3 to draw the rectangle with SolidFill a flag to indicate that the interior should be filled Return Value ERR_OK operation completed with no problems Programming Notes and Examples SED1355 Issue Date 99 04 27
44. 0 Display Buffer Size 1024 n 255 1 Display Buffer Size n x 8192 X23A R 001 02 98 09 15 EPSON SED1355 Embedded RAMDAC LCD CRT Controller 1355CFG Configuration Program Document Number X23A B 001 02 Copyright 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Microsoft and Windows are registered trademarks of Microsoft Corporation Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 1355CFG Configuration Program X23A B 001 02 Issue Date 98 10 30 Epson Research and Development Page 3 Vancouver Design Center Table of Contents e A A RR a 7 SED1355 Supported Evaluation Platforms Installation Usage ez o Ro ad A A A A id 1355CFG Configuration Pages mo 8 General age ein ios la ei ke a a A a a O Memory Page kes cie te ia Se
45. 0x00 0xF0 0x00 Black to blue 0x00 0x00 0x00 0x00 0x00 0x10 0x00 0x00 0x20 0x00 0x00 0x30 0x00 0x00 0x40 0x00 0x00 0x50 0x00 0x00 0x60 0x00 0x00 0x70 0x00 0x00 0x80 0x00 0x00 0x90 0x00 0x00 0xA0 0x00 0x00 OxBO 0x00 0x00 0xC0 0x00 0x00 OxDO 0x00 0x00 OxEO 0x00 0x00 OxFO Blue to cyan blue and green 0x00 0x00 OxFO 0x00 0x10 OxFO 0x00 0x20 OxF0 0x00 0x30 OxFO 0x00 0x40 OxFO 0x00 0x50 OxFO 0x00 0x60 OxFO 0x00 0x70 OxFO 0x00 0x80 OxFO 0x00 0x90 OxFO 0x00 0xA0 OxFO 0x00 0xB0 OxFO 0x00 0xC0 OxFO 0x00 OxDO 0xF0 0x00 0xE0 OxFO 0x00 0xF0 OxFO Cyan blue and green to green 0x00 OxFO OxFO 0x00 OxFO OxEO 0x00 OxFO OxDO 0x00 OxFO OxC0 0x00 OxFO OxBO 0x00 OxFO OXxAO 0x00 OxFO 0x90 0x00 0xF0 0x80 0x00 OxFO 0x70 0x00 OxFO 0x60 0x00 OxFO 0x50 0x00 0xF0 0x40 0x00 OxFO 0x30 0x00 OxFO 0x20 0x00 0xF0 0x10 0x00 0xF0 0x00 Green to yellow red and green 0x00 OxFO 0x00 0x10 0xF0 0x00 0x20 0xF0 0x00 0x30 0xF0 0x00 0x40 OxFO 0x00 0x50 0xF0 0x00 0x60 OxFO 0x00 0x70 0xF0 0x00 0x80 OxFO 0x00 0x90 OxFO 0x00 OxA0 OxFO 0x00 0xB0 0xF0 0x00 OxCO OxFO 0x00 OxDO OxFO 0x00 OxEO OxFO 0x00 OxFO OxFO 0x00 Yellow red and green to red OxFO OxFO 0x00 OxFO OxEO 0x00 OxFO OxDO 0x00 OxFO 0xC0 0x00 OxFO OxBO 0x00 OxFO OxA
46. 1 To show a test grid over the color pattern type the following 1355SHOW b 8 g The program will display the 8 bit per pixel color pattern overlaid with a one pixel wide white grid and then exit The grid makes it obvious if the image is shifted or if pixels are missing Note the grid is not aligned with the color pattern therefore the color boxes will not match the grid boxes The g switch can be used in combination with other command line switches 2 To test background memory reads type the following 1355SHOW b 16 read The program will test screen reads If there is a problem with memory access the displayed pattern will appear different than when the read switch is not used If there is a problem check the configuration parameters of 1355SHOW using the utility 1355CFG See the 1355CFG user guide document number X23A B 001 xx for more information The read switch should be used in combination with the b setting otherwise the test will always start with the 16 bit per pixel screen To exit the program after using read press ESC and wait for a couple of seconds the keystroke is checked after reading a full screen 1355SHOW Demonstration Program SED1355 Issue Date 98 10 29 X23A B 002 04 Page 6 Epson Research and Development Vancouver Design Center Comments 1355SHOW cannot show a greater color depth than the display allows Portrait mode is available only for 8 15 and 16 bit per pi
47. 15 Power Save Modes Three power save modes are incorporated into the SED1355 to meet the important need for power reduction in the hand held device market Table 15 1 Power Save Mode Function Summary Power Save Mode PSM Function Normal GE 0 Software Hardware Active CRTEnable 8 0 Suspend Suspend Display Active Yes No No No Register Access Possible Yes Yes Yes No Memory Access Possible Yes Yes No No LUT Access Possible Yes Yes Yes No Table 15 2 Pin States in Power save Modes Pin State Pins Normal pe Display Software Hardware S LCDEnable 0 Active CRTEnable 0 Suspend Suspend Active 2 2 2 LCD outputs LCDEnable 1 Forced Low Forced Low Forced Low On LCDPWR LCDEnable 1 Off Off Off DRAM outputs Active DE Refresh Only Refresh Only Active S e CRT DAC outputs CRTEnable 1 Disabled Disabled Disabled Host Interface outputs Active Active Active Disabled 1 Refresh method is selectable by REG 1Ah Supported methods are CBR refresh self refresh or no refresh at all 2 The FPFRAME and FPLINE signals are set to their inactive states during power down The in active states are determined by REG 07h bit 6 and REG OCh bit 6 A problem may occur if the inactive state is high typical TFT D TFD configuration and power is removed from the LCD panel For software suspend the problem can be solved in the following manner At power down fi
48. 7 2 NEC Electronics Inc VR4121 e 17 Interfacing to the NEC VR4121 Microprocessor SED1355 Issue Date 99 05 05 X23A G 011 03 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 Interfacing to the NEC VR4121 Microprocessor X23A G 011 03 Issue Date 99 05 05 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping 2 0 0 0 20 eee eee 10 Table 4 1 Summary of Power On Reset Options 002000000000 13 List of Figures Figure 2 1 NEC VR4121 Read Write Cycles o o e ee ee 9 Figure 4 1 NEC VR4121 to SED1355 Configuration Schematic o a 12 Interfacing to the NEC VR4121 Microprocessor SED1355 Issue Date 99 05 05 X23A G 011 03 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 Interfacing to the NEC VR4121 Microprocessor X23A G 011 03 Issue Date 99 05 05 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment necessary to provide an interface between the SED1355 Embedded RAMDAC LCD CRT Controller and the NEC Vr4121 uPD30121 microprocessor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Pl
49. E E E E E E E E E E E E E E E EE E ES REG O9h REG O8h 1 lines NN 0 NS SES LINO U SISSI S S N EE REG OER D Screen 2 gt REG OFh REG 04h 1 8 pixels CY e oO SE SE a A G a SE SE O lt SE H o EELS Se be A A oO pa MM EEE E 10 LM EEE S O E 5 Ss CI N Ww o SILAAA AAA DADA AAA RARA AAA RARA Ce 1 L Si Ed a AAA DAA AAA AAA AA AAA AA AAA AAN CO EH gt y SE E iti q GE E oe WH ES S Ze E E O E Ye EG E T GA a O EZ ty DE GA ke L gt BZ Dz E BZ D GA A gt Ze B S GA SE SA O A c eee A A G ks LLL DY A LO gt N ZA O R GUR a gt FER y I a E EE 0 U A E N E FS E UI SE ED o ha CO E E 10 IEEE EE EE E E a LLL TTT dd AAA DARA NN E E E SE E E EE Figure 10 3 Image Manipulation REG 18h bits 7 4 Screen 2 REG 17h REG 16h 99 05 18 Hardware Functional Specification Issue Date Epson Research and Development Page 128 Vancouver Design Center 11 Look Up Table Architecture The following figures are intended to show the display data output path only 11 1 Monochrome Modes The green Look Up Table LUT is used for all monochrome modes 1 Bit per pixel Monochrome mode Green Look Up Table 256x4 00 lo 4bit Grey Data 01 hd 1
50. E Ee Haf y taw a ASL ASL ASL ASL ASL ASL ASL ASL ASL ASL oa 268 dam 28 98 dom dr gew dem u Je gem A J Ist olaw 3A 8 D 9 S T y E H L Page 20 SED1355 X23A G 004 04 Page 21 Epson Research and Development Vancouver Design Center SED1355 X23A G 004 04 Figure 3 SED1355BOC Schematic Diagram 3 of 4 g L 9 S y y E z L A JO E ESTE 8661 bz REECH aed DL a en Joquinn wewnoog_ eg pleog uopenjeag sng yS Ooasse NOS ouj 1uaudojarag yo1essoy uosda a ASLAN le AM AE Zb Ag Any Ski pony le vo Ei Sei F zo F nazi oo oo oo G NOO Lv O NOO LV m ano sias Ly y 44 EC vias H DM AS sias L X JE zias 3 SH 2w uas L t SK ES oras Ze X SEO eas s SKY soua sas Ser Sr EH WE rop 03M F coa anaw Ls 408 lt r 0N9Va A te TP Ou HA KE so AE KS 21081 ECK w pil AX HOI L y u SHA oI ON gt SK 9150011 OM 9 Ison H SISCH anas ES 290A sr PI ees LaM XOL gt DA eeu Uz lezy e gt leroy Froe LI Su LY v NOO 1V H ONE ovs ve x 280 Ws y Ast avs L Le ava lt awa evs Le OL eae Der de Se SH DEN svS EE AS ECH avs x SK EH NS y SE Ke SOYI evs hz GC SK SCH evs a Lou ows weng SES Les H S 8 RECH SC HS3u338 zivs t Ge EG Ee evs L y SH powo rivs LE Ai S54 coya S
51. FPFRAME Polarity Selection FPFRAME Polarity Select Passive LCD FPFRAME Polarity TFT D TFD FPFRAME Polarity 0 active high active low 1 active low active high bits 2 0 SED1355 X23A A 001 11 VRTC FPFRAME Pulse Width Bits 2 0 For CRT and TFT D TFD these bits specify the pulse width of VRTC and FPFRAME respectively For passive LCD FPFRAME is automatically created and these bits have no effect VRTC FPFRAME pulse width lines VRTC FPFRAME Pulse Width Bits 2 0 1 Note This register must be programmed such that REG OAH bits 5 0 1 gt REG OBh 1 REG OCH bits 2 0 1 Hardware Functional Specification Issue Date 99 05 18 Epson Research and Development Vancouver Design Center Page 107 8 2 4 Display Configuration Registers Display Mode Register REG ODh RW Simultaneous Simultaneous SwivelView Display Display Bit per pixel Bit per pixel Bit per pixel Enable Option Select Option Select Select Bit 2 Select Bit 1 Select Bit 0 SRT Enable EOP Enable Bit 1 Bit 0 bit 7 SwivelView Enable When this bit 1 all CPU accesses to the display buffer are translated to provide clockwise 90 hardware rotation of the display image Refer to Section 13 SwivelView for application and limi tations bits 6 5 Simultaneous Display Option Select Bits 1 0 These bits are used to select one of four different simultaneous display mode
52. For Toshiba TX3912 Bus pins 15 8 are connected to D 23 16 and pins 7 0 are connected to D 31 24 e For PowerPC Bus these pins are connected to D 0 15 e For PC Card PCMCIA Bus these pins are connected to D 15 0 See Host Bus Interface Pin Mapping for summary See the respective AC Timing diagram for detailed functionality WE1 CS TS Hi Z This is a multi purpose pin e For SH 3 SH 4 Bus this pin inputs the write enable signal for the upper data byte WE1 e For MC68K Bus 1 this pin inputs the upper data strobe UDS e For MC68K Bus 2 this pin inputs the data strobe DS e For Generic Bus this pin inputs the write enable signal for the upper data byte WE1 e For MIPS ISA Bus this pin inputs the system byte high enable signal SBHE e For Philips PR31500 31 700 Bus this pin inputs the odd byte access enable signal CARDxCSh e For Toshiba TX3912 Bus this pin inputs the odd byte access enable signal CARDxCSH For PowerPC Bus this pin outputs the burst inhibit signal Bl e For PC Card PCMCIA Bus this pin inputs the card enable 2 signal CE2 See Host Bus Interface Pin Mapping for summary See the respective AC Timing diagram for detailed functionality M R Hi Z e For Philips PR31500 31700 Bus this pin is connected to Von e For Toshiba TX3912 Bus this pin is connected to Von For all other busses this input pin is used to select between the dis
53. Ifthe SED1355 host interface is disabled the timing for RD Y driven is relative to the falling edge of CSn or the first positive edge of CKIO after A 20 0 M R becomes valid whichever one is later 2 Ifthe SED1355 host interface is disabled the timing for D 15 0 driven is relative to the falling edge of RD or the first positive edge of CKIO after A 20 0 M R becomes valid whichever one is later SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 43 Vancouver Design Center 7 1 2 SH 3 Interface Timing t1 t2 t3 Era CKIO t4 t5 A 20 0 M R RD WR X t6 t7 BS SE t8 t12 CSn t9 t10 e WEn RD t11 t12 p gt WAIT E t13 R t14 i D 15 0 write t15 t16 gt WM ECH D 15 0 read D Figure 7 2 SH 3 Timing Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected Note The SH 3 Wait State Control Register for the area in which the SED1355 resides must be set to a non zero value Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 44 Epson Research and Development Vancouver Design Center Table 7 2 SH 3 Timing 3 0V4 5 0v Symbol Parameter Min Max Min Max Units D Clock period 15 1 15 1 ns t2 Clock pu
54. Ink Cursor Start Address bit 6 Ink Cursor Start Address bit 5 Ink Cursor Start Address bit 4 Ink Cursor Start Address bit 3 Ink Cursor Start Address bit 2 Ink Cursor Start Address bit 1 Ink Cursor Start Address bit O Register 30h determines the location in the display buffer where the cursor ink layer will be located Table 7 2 can be used to determine this location Note Bit 7 is write only when reading back the register this bit reads a 0 Table 7 2 Cursor Ink Start Address Encoding Ink Cursor Start Address Bits 7 0 Start Address Bytes 0 Display Buffer Size 1024 1 FER Display Buffer Size n 8192 Programming Notes and Examples Issue Date 99 04 27 SED1355 X23A G 003 05 Page 36 Epson Research and Development Vancouver Design Center 7 3 Limitations There are limitations for using the hardware cursor ink layer which should be noted 7 3 1 Updating Hardware Cursor Addresses All hardware cursor addresses must be set during VNDP vertical non display period Check the VNDP status bit REG OAh bit 7 to determine if you are in VNDP then update the cursor address register 7 3 2 Reg 29h And Reg 2Bh Bit seven of registers 29h and 2Bh are write only and must always be set to zero as setting these bits to one will cause undefined cursor behavior 7 3 3 Reg 30h Bit 7 of register 30h is write only there
55. PCMCIA Bus this pin is connected to CLKI See Host Bus Interface Pin Mapping for summary See the respective AC Timing diagram for detailed functionality BS l CS Hi Z This is a multi purpose pin e For SH 3 SH 4 Bus this pin inputs the bus start signal BS e For MC68K Bus 1 this pin inputs the address strobe AS e For MC68K Bus 2 this pin inputs the address strobe AS e For Generic Bus this pin is connected to Vpp e For MIPS ISA Bus this pin is connected to Vpp e For Philips PR31500 31700 Bus this pin is connected to Vpp For Toshiba TX3912 Bus this pin is connected to Vpp e For PowerPC Bus this pin inputs the Transfer Start signal TS e For PC Card PCMCIA Bus this pin is connected to Vpp See Host Bus Interface Pin Mapping for summary See the respective AC Timing diagram for detailed functionality RD WR l 10 CS Hi Z This is a multi purpose pin e For SH 3 SH 4 Bus this pin inputs the read write signal RD WR The SED1355 needs this signal for early decode of the bus cycle e For MC68K Bus 1 this pin inputs the read write signal R W e For MC68K Bus 2 this pin inputs the read write signal R W For Generic Bus this pin inputs the read command for the upper data byte RD1 e For MIPS ISA Bus this pin is connected to Vpp e For Philips PR31500 31700 Bus this pin inputs the even byte access enable signal CARDxCSL
56. Power Oscillator Management PC Card il BUS He E A 25 21 P Decoder O K MRE z FPDAT 15 8 LN UDI 7 0 5 FPDAT 7 0 LN LDI 7 0 p Decoder O cs D FPSHIFT p FpsHirt 4 8 16 bit A 20 0 KN AB 20 0 LCD D 15 0 4 Kl DB 15 0 FPFRAME FPFRAME Display FPLINE FPLINE DRDY MOD WE V wee SED1355F0A 4 CE2 P WEI LCDPWR OE KM RD CE1 KN RDWRE RED GREEN BLUE p WAIT 4 WAIT HRTC NM CRT veto Display a gt BCLK gt BUSCLK 28 gb RESET po P RESET ES SS IREF 4 IREF ESES zee EES 1Mx16 FPM EDO DRAM Figure 3 10 Typical System Diagram PC Card PCMCIA Bus Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 20 4 Internal Description 4 1 Block Diagram Showing Datapaths Epson Research and Development Vancouver Design Center CPU MPU Register i 16 bit FPM EDO DRAM Memory Controller i R W Display FIFO Cursor FIFO Power Save Look Up Tables LCD CRT Clocks 4 2 Block Descriptions 4 2 1 Register The Register block contains all the register latches 4 2 2 Host Interface 4 2 3 CPU R W SED1355 X23A A 001 11 The Host Interface I F block provides the means for the CPU MPU to communicate with the display buffer and internal registers via one of the suppor
57. REG 12h Screen 1 Display Start Address Register 2 n a n a n a n a Bit 19 Bit 18 Bit 17 Bit 16 Finally set the memory address offset registers to 1024 pixels In 16 bpp mode load registers 17h 16h with 1024 and in 8 bpp mode load the registers with 512 REG 16h Memory Address Offset Register 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 17h Memory Address Offset Register 1 n a n a n a n a n a Bit 10 Bit 9 Bit 8 8 4 Limitations SED1355 X23A G 003 05 The following limitations apply to Hardware Portrait Mode e Only 8 bpp and 16 bpp modes are supported 1 2 4 bpp modes are not supported e Cursor and ink images are not rotated software rotation must be used Hardware Portrait Mode must be turned off when the programmer is accessing the Cursor or the ink layer e Split screen images appear side by side i e the portrait display is split vertically e Pixel panning works vertically Note Drawing into the hardware cursor ink layer with rotation enabled does not work without some form of address manipulation The easiest way to ensure correct cursor ink images is to disable Hardware Portrait Mode draw in the cursor ink memory then re enable hardware portrait mode While writing the cursor ink memory each pixel must be transformed to its rotated position Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 39 Vanco
58. RW n a n a n a n a n a n a n a n a This register position is reserved for future use SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 115 Vancouver Design Center General IO Pins Control Register 0 REG 20h RW ia wa a n GPIO3 Pin GPIO2 Pin GPIO1 Pin af IO Status IO Status IO Status bit 3 GPIO3 Pin IO Status When GPIO3 is configured as an output see REG 1Eh a 1 in this bit drives GPIO3 high and a 0 in this bit drives GPIO3 low When GPIO3 is configured as an input a read from this bit returns the status of GPIO3 bit 2 GPIO2 Pin IO Status When GPIO2 is configured as an output see REG 1Eh a 1 in this bit drives GPIO2 high and a 0 in this bit drives GPIO2 low When GPIO2 is configured as an input a read from this bit returns the status of GPIO2 bit 1 GPIO1 Pin IO Status When GPIO is configured as an output see REG 1Eh a 1 in this bit drives GPIO1 high and a 0 in this bit drives GPIO1 low When GPIO1 is configured as an input a read from this bit returns the status of GPIO1 General IO Pins Control Register 1 REG 21h RW GPO Control n a n a n a n a n a n a n a bit 7 GPO Control This bit is used to control the state of the SUSPEND pin when it is configured as General Purpose Output GPO When this bit 0 the GPO
59. S9 file for non Intel platforms The file must have been compiled using a valid version of the 1355 HAL library SED1355 1355CFG Configuration Program X23A B 001 02 Issue Date 98 10 30 Epson Research and Development Page 15 Vancouver Design Center Save As Dialog Box Save As Save in Y intel D Ka c ee SS 13555H0W exe File name 355SHOW exe Save as type Executable Files T exe s9 D Cancel When the Save As button is pressed on the main window 1355CFG checks for any invalid config uration values and shows any appropriate warning or error messages If it is possible to save the values the Save As Dialog Box is shown The configuration values can be saved to a specific EXE file for Intel platforms and to a specific S9 file for non Intel platforms The file must have been compiled using a valid version of the 1355 HAL library The configuration values can also be saved to an ASCII header file ie 1355reg h for use by the software hardware developer 1355CFG Configuration Program SED1355 Issue Date 98 10 30 X23A B 001 02 Page 16 Example SED1355 X23A B 001 02 Epson Research and Development Vancouver Design Center Configure for an 8 bit color single passive 640x480 LCD panel and the SDU1355 BOC Evaluation Board on a PC General Page Register Address 0xE00000 Memory Addr
60. SED1355 Interfacing to the Toshiba MIPS TX3912 Processor X23A G 010 03 Issue Date 99 05 05 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 TX3912 Host Bus Interface Pin Mapping aaa 9 Table 4 1 SED1355 Configuration for Direct Connection o soo 12 Table 4 2 TX3912 to PC Card Slots Address Remapping for Direct Connection 13 List of Figures Figure 4 1 Typical Implementation of Direct Comnecti0d o o e 11 Figure 5 1 IT8368E Implementation Block Diagram o oo e 14 Interfacing to the Toshiba MIPS TX3912 Processor SED1355 Issue Date 99 05 05 X23A G 010 03 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 Interfacing to the Toshiba MIPS TX3912 Processor X23A G 010 03 Issue Date 99 05 05 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment necessary to provide an interface between the SED1355 Embedded RAMDAC LCD CRT Controller and the Toshiba MIPS TX3912 Processor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any developmen
61. Table 7 4 MC68030 Timing 3 0V 5 0V Symbol Parameter Min Max Min Max Units t1 Clock period 20 20 ns t2 Clock pulse width high 6 6 ns t3 Clock pulse width low 6 6 ns t4 A 20 0 SIZ 1 0 M R setup to first CLK where CS 0 AS 10 10 hs 0 and either UDS 0 or LDS 0 t5 A 20 0 SIZ 1 0 M R hold from AS 0 0 ns t6 CS hold from AS 0 ns t7 R W setup to DS 10 10 ns 18 R W hold from AS 0 ns to AS 0 and CS 0 to DSACK1 driven high 0 0 ns t10 AS high to DSACK1 high 3 18 3 12 ns t11 First BCLK where AS 1 to DSACK1 high impedance 5 25 2 5 10 ns t12 D 31 16 valid to third CLK where CS 0 ASH 0 and either 10 10 hs UDS 0 or LDS 0 write cycle t13 D 31 16 hold from falling edge of DSACK1 write cycle 0 0 ns t142 Falling edge of UDS 0 or LDS 0 to D 31 16 driven read 0 0 ng cycle t15 D 31 16 valid to DSACK1 falling edge read cycle 0 0 ns t16 UDS and LDS high to D 31 16 invalid high impedance read 5 25 25 10 ns cycle t17 AS high setup to CLK 2 2 ns 1 Ifthe SED1355 host interface is disabled the timing for DSACK1 driven high is relative to the falling edge of CS AS or the first positive edge of CLK after A 20 0 M R becomes valid whichever one is later 2 If the SED1355 host interface is disabled the timing for D 31 16 driven is relative to the falling edge of UDS LDS or the first positive edge of CLK
62. WAIT RESET RESET RESET RESET RESET RESET d RESET PON RESET eee Note The bus signal AO is not used by the SED1355 internally SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 35 Vancouver Design Center Table 5 7 Memory Interface Pin Mapping FPM EDO DRAM scare Sym 256Kx16 Asym 256Kx16 Sym 1Mx16 Asym 1Mx16 2 CAS 2 WE 2 CAS 2 WE 2 CAS 2 WE 2 CAS 2 WE MD 15 0 D 15 0 MA 8 0 A 8 0 MA9 GPIO3 AQ AQ MA10 GPIO1 A10 MA11 GPIO2 A11 UCAS UCAS UWE UCAS UWE UCAS UWE UCAS UWE LCAS LCAS CAS LCAS CAS LCAS CAS LCAS CAS WE WE LWE WE LWE WE LWE WE LWE RAS RAS Note All GPIO pins default to input on reset and unless programmed otherwise should be connected to either Vss or IO Vpp if not used Table 5 8 LCD Interface Pin Mapping Monochrome Passive Color Passive Panel SED1355 pana Color TFT D TFD Panel Pin Single Dual Single Single Single Single Dual Names Format 1 Format 2 4 bit 8 bit 8 bit 4 bit 8 bit 8 bit 16 Bit 8 bit 16 bit 9 bit 12 bit 18 bit FPFRAME FPFRAME FPLINE FPLINE FPSHIFT FPSHIFT DRDY MOD EH MOD DRDY FPDATO DO LDO DO DO DO LDO LDO R2 R3 R5 FPD
63. WR WAIT LCDRDY RESET connected to system reset Interfacing to the NEC VR4102 VR4111 Microprocessors Issue Date 99 05 05 Epson Research and Development Page 11 Vancouver Design Center 3 2 Host Bus Interface Signals Descriptions The SED1355 MIPS ISA Host Bus Interface requires the following signals BUSCLK is a clock input which is required by the SED1355 Host Bus Interface It is separate from the input clock CLKD and is typically driven by the host CPU system clock The address inputs AB 20 0 and the data bus DB 15 0 connect directly to the VR4102 VR4111 address ADD 20 0 and data bus DAT 15 0 respectively MD4 must be set to select the proper endian mode upon reset M R memory register selects between memory or register access It may be connected to an address line allowing system address ADD21 to be connected to the M R line Chip Select CS must be driven low by LCDCS whenever the SED1355 is accessed by the VR4102 VR4111 WE1 connects to SHB the high byte enable signal from the VR4102 VR4111 which in conjunction with address bit 0 allows byte steering of read and write operations WEO connects to WR the write enable signal from the VR4102 VR4111 and must be driven low when the VR4102 VR4111 is writing data to the SED1355 RD connects to RD the read enable signal from the VR4102 VR4111 and must be driven low when the VR4102 VR4111 is reading data from the SED1355 WAIT co
64. X EA FPDATO UDO o 241 R2X241 G3 241 B4X241 R6X241 67 241 B8L X pale 7 Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7 38 8 Bit Dual Color Passive LCD Panel Timing VDP Vertical Display Period REG 09h bits 1 0 REG O8h bits 7 0 1 VNDP Vertical Non Display Period REG OAH bits 5 0 1 HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period REG O5h bits 4 0 1 8Ts Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 92 Epson Research and Development Vancouver Design Center tl t2 Sync Timing FPFRAME t4 t3 FPLINE t5 MOD Data Timing FPLINE t9 tl1 t10 FPSHIFT UDI3 0 a LD 3 0 Figure 7 39 8 Bit Dual Color Passive LCD Panel A C Timing Table 7 30 8 Bit Dual Color Passive LCD Panel A C Timing Symbol Parameter Min Typ Max Units t1 FPFRAME setup to FPLINE pulse trailing edge note 2 t2 FPFRAME hold from FPLINE pulse trailing edge 14 Ts note 1 t3 FPLINE period note 3 t4 FPLINE pulse width 9 Ts t5 MOD delay from FPLINE pulse trailing edge note 4 t6 FPSHIFT falling edge to FPLINE pulse leading edge note 5 t7 FPSHIFT falling edge to FPLINE pulse trailing edge note 6 t8 FPLINE pulse trailing edge to FPSHIFT falling edge t14 t11 Ts t9 FPSHIFT perio
65. X23A G 003 05 Page 70 Epson Research and Development Vancouver Design Center int seDrawInkEllipse int DevID long xc long yc long xr long yr DWORD Color BOOL SolidFill Description Parameters This routine draws an ellipse with the center located at xc yc The xr and yr param eters specify the x and y radii in pixels respectively The ellipse will be drawn in the color specified by Color The value of Color must be 0 to 3 Values 0 and 1 refer to the two user definable colors If Color is 2 then the pixel will be transparent and if the value is 3 the pixel will be an inversion of the underlying screen color This solid fill option is not yet available for this function DevID aregistered device ID XC yC center point for the ellipse in pixels xr horizontal radius of the ellipse in pixels yr vertical radius of the ellipse in pixels Color a two bit value 0 to 3 to draw the rectangle with SolidFill flag to enable filling the interior of the ellipse currently not used Return Value ERR OK operation completed with no problems int seDrawInkCircle int DeviD long x long y long Radius DWORD Color BOOL SolidFill Description Parameters This routine draws a circle in the ink layer display buffer The center of the circle will be at x y and the circle will have a radius of Radius pixels The value of Color must be 0 to 3 Values 0 and 1 refer to the two user def
66. dor oz ue o OPE 6h HAY BE 8 anyo anyo anyo xose D SE FEH o Di am e J vi 2001 JE EE ee eL zeo 0809 Geh E i Gleb 9 0 DL EE Ae e qe s x A z H HH 2 9 as s Lem ve v neoa o ez Lg zz z A0 A g z L gt gt oa sar Le m Joe Oe AXUS Lg Ea SK AN o anro TI D anco 1 S 620 Da 90 aor SL A Ano SE Zeg Szo NA Krk zo F t ux x a Mo XOL D suen IS 413838 NEDO e DEI DE 88 0u 590 4 4 80 HN wok Zap ely ozu m gt iroa aoa A0 la 8 Z 9 S A Figure 5 3 SDU1355 D9000 Schematic Diagram 3 of 3 SDU1355 D9000 Evaluation Board User Manual Issue Date 98 10 30 X23A G 002 03 Vancouver Design Center Epson Research and Development Page 22 6 Component Placement N O gt Cue EN oo es ee Y ooe ee ee EE De SS Den eo eo oo Z ee meme moMo gt MATO n CN rk WS E S o CR s seg d DW Chemin Z 1 Wal CH ER BR ERE caine moe 00S o PIL np ms 618 E AO 2 LCDVCC1 o o mpFPS2 U4 LCDI Figure 6 1 Component Placement Evaluation Board User Manual SDU1355 D9000 X23A G 002 03 Issue Date 98 10 30 EPSON SED1355 Embedded RAMDAC LCD CRT Controller Power Consumption Document Number X23A G 006 02 Copyright O 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject t
67. or 2048 15 16 bpp to reflect the 1024 x 1024 virtual area of the rotated memory Parameters DevID registered device ID pBytes pointer to an integer which indicates the number of bytes per scan line Return Value ERR_OK operation completed with no problems ERR_FAILED returned when this function is called for rotated display modes other than 8 15 or 16 bpp int seGetScreenSize int DevID UINT Width UINT Height Description Gets the width and height in pixels of the display surface The width and height are derived by reading the horizontal and vertical size registers and calculating the dimensions When the display is in portrait mode the dimensions will be swapped i e a 640x480 display in portrait mode will return a width and height of 480 and 640 respectively Parameters DevID registered device ID Width unsigned integer to receive the display width Height unsigned integer to receive the display height Return value ERR OK the operation completed successfully int seSelectBusWidth int DevID int Width Description Call this function to select the interface bus width on the ISA evaluation card Selectable widths are 8 bit and 16 bit Parameters DevID registered device ID Width desired bus width Must be 8 or 16 Return Value ERR_OK the operation completed successfully ERR_FAILED the function was called on a non ISA platform or width was not set to 8 or 16 Note This call applies to the SED13
68. pixels_per_word 640 4 160 AOh We now know how much to add to the start address to scroll down one line 2 Increment the start address by the number of words per virtual line start_address start_address words 3 Separate the start address value into three bytes Write the LSB to register 10h and the MSB to register 12h 5 3 Split Screen Occasionally the need arises to display two distinct images on the display For example we may write a game where the main play area will rapidly update and we want a status display at the bottom of the screen The Split Screen feature of the SED1355 allows a programmer to setup a display for such an appli cation The figure below illustrates setting a 320x240 panel to have Image 1 displaying from scan line 0 to scan line 99 and image 2 displaying from scan line 100 to scan line 239 Although this example picks specific values image 1 and image 2 can be shown as varying portions of the screen Scan Line 0 ie Image 1 Scan Line 99 Scan Line 100 Image 2 Scan Line 239 Figure 5 5 320x240 Single Panel For Split Screen SED1355 Programming Notes and Examples X23A G 003 05 Issue Date 99 04 27 Epson Research and Development Page 29 Vancouver Design Center 5 3 1 Registers The other registers required for split screen operations 10h through 12h Screen 1 Display Start Address and 18h Pixel Panning Register are described in Section 5 2 1 on page
69. pointer to string of HAL statusRevision None const char pVersion pStatus pStatusRevision seGetHalVersion amp pVersion amp pStatus amp pStatusRevision This document was written for HAL version 1 04 so any later versions should be a superset of the functions described here Programming Notes and Examples Issue Date 99 04 27 SED1355 X23A G 003 05 Page 50 SED1355 X23A G 003 05 Epson Research and Development Vancouver Design Center void seGetLibseVersion int Version Description Retrieves the LIBSE library version for non x86 platforms The return pointer in parameter Version is valid if the function return value is ERR_OK Parameters Version pointer to an int to store LIBSE version code Return Value ERR_OK no problems encountered version code is valid ERR_FAILED unable to complete operation Probably on x86 platform where LIBSE is not used int seGetMemSize int DevID DWORD pSize Description This routine returns the amount of installed video memory The memory size is determined by reading the status of MD6 and MD7 pSize will be set to either 80000h 512 KB or 200000h 2 MB Parameters DevID registered device ID pSize pointer to a DWORD to receive the size Return Value ERR OK the operation completed successfully Note Memory size is only checked when calling seRegisterDevice seSetDisplayMode or seSetInit Afterwards the memory size is stored and made avail
70. qe ASH t11 lt gt UDS LDS t7 ts R W pa t9 pto DTACK pa t12 t13 gt W gt D 15 0 write t14 t15 t16 ka gt D 15 0 read Figure 7 3 MC68000 Timing Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 46 Epson Research and Development Vancouver Design Center Table 7 3 MC68000 Timing 3 0V 5 0V Symbol Parameter Min Max Min Max Units t1 Clock period 20 20 ns t2 Clock pulse width high 6 6 ns t3 Clock pulse width low 6 6 ns t4 A 20 1 M R setup to first CLK where CS 0 ASH 0 and 10 10 AS either UDS 0 or LDS 0 t5 A 20 1 M R hold from AS 0 0 ns t6 CS hold from AS 0 0 ns t7 R W setup to before to either UDS 0 or LDS 0 10 10 ns 18 R W hold from AS 0 0 ns to AS 0 and CS 0 to DTACK driven high 0 0 ns t10 AS high to DTACK high 3 18 3 12 ns t11 First BCLK where AS 1 to DTACK high impedance 25 10 ns t12 D 15 0 valid to third CLK where CS 0 AS 0 and either 10 10 hs UDS 0 or LDS 0 write cycle t13 D 15 0 hold from falling edge of DTACK write cycle 0 0 ns t142 Falling edge of UDS 0 or LDS 0 to D 15 0 driven read 0 0 ris cycle t15 D 15 0 valid to DTACK falling edge read cycle 0 0 ns t16
71. read cycle or accepted write cycle on the host bus Since the host CPU accesses to the SED1355 may occur asynchronously to the display update it is possible that contention may occur in accessing the SED1355 internal registers and or display buffer The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete Interfacing to the Philips MIPS PR31500 PR31700 Processor Issue Date 99 05 05 Epson Research and Development Page 9 Vancouver Design Center 4 Direct Connection to the Philips PR31500 PR31700 The SED1355 was specifically designed to support the Philips MIPS PR31500 PR31700 processor When configured the SED1355 will utilize one of the PC Card slots supported by the processor 4 1 Hardware Description In this example implementation the SED1355 occupies one PC Card slot and resides in the Attribute and IO address range The processor provides address bits A 12 0 with A 23 13 being multiplexed and available on the falling edge of ALE Peripherals requiring more than 8K bytes of address space would require an external latch for these multiplexed bits However the SED1355 has an internal latch specifically designed for this processor making additional logic unnecessary To further reduce the need for external components the SED1355 has an optional BUSCLK divide by 2 feature allowing the high speed DCLKOUT from the processor to be directly connected to the BUSCLK input of the S
72. saan L 1 Stivad aA 1 o N ZE plivdds eaaa L t t GE Zaoa GN Sage vaan L E Ka Ka Ges neoa 7 g z GK 61V0d3 mm Y Y sivadd 59 DOSEN E E von re esava kom jk a osna rer xoa a za ta vada KS E SU L t zivadd rer ENN HLZHNEEE EE izo LIVOda 80 Si 80 Ino an9 SS EI i i 7 stolivada lt Sum C eum TON ON 0 ASO pe ZLAIHSd4 OL Se 413838 Lo lt age sn Ed SEO 458 Le ssa uudioo god tena E aud S Suds 404 4 tau sam E f ie LS ZHNEEE EE CA DEA Jino ano Le moved TZ aNadsns UWGY Hor 48Was oN on ty umaa umaao K Sr siga ab an nai eraa ia 3M zisa Gs e H SEN eu 6ga seoa sad 180 SION 98a YIAN saa claw vaa zian eaa LLON zaa oran tad san oga san K iroa Bad ozav san ECH saw EA raw Ze an grav zaw stay 1an EG oaw BEA HE ZO1d5 t WW uav TOId9 0 en orgy Old 6VN 6av Seit sav Zen Lav gen 98 Seit sav rent vay Cent eav Sen zav Ly vay ow ogy Du Epson Research and Development 5 Schematic Diagrams Vancouver Design Center Figure 5 1 SDU1355 D9000 Schematic Diagram 1 of 3 98 10 30 Evaluation Board User Manual Issue Date Vancouver Design Center Epson Research and Development Page 20 8 Z I 9 A y y E z L yo z
73. the system designer should be aware of all conditions that may reset the SED1355 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 NEC Vr4102 Vr4111 to SEDI355 Configuration Schematic Note For pin mapping see Table 3 1 Host Bus Interface Pin Mapping on page 10 SED1355 Interfacing to the NEC VR4102 VR4111 Microprocessors X23A G 007 05 Issue Date 99 05 05 Epson Research and Development Page 13 Vancouver Design Center 4 2 SED1355 Hardware Configuration The SED1355 latches MD15 through MDO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the SEDI355 Hardware Functional Specification document number X23A A 001 xx The table below shows those configuration settings important to the NEC Vr4102 Vr4111 CPU interface Table 4 1 Summary of Power On Reset Options SED1355 value on this pin at rising edge of RESET is used to configure 1 0 Pin Name 1 0 MDO 8 bit host bus interface MD 3 1 MD4 Big Endian MD5 WAIT is active high 1 insert wait state MD11 Alternate Host Bus Interface Selected Primary Host Bus Interface Selected E configuration for NEC VR4102 VR4111 microprocessor 4 3 NEC Vr4102 V24111 Configuration NEC Vr4102 Vr4111The NEC Vr4102 Vr4111 provides the internal address decoding necessary to map an external LCD cont
74. typedef WORD far LPWORD typedef DWORD far LPDWORD else typedef BYTE LPBYTE typedef WORD LPWORD typedef DWORD LPDWORD tendif ifndef LOBYT define LOBYT tendif FEIL w BYTE w ifndef HIBYTI define HIBYTI endif DL El w BYTI E UINT w gt gt 8 OXFF ifndef LOWORD define LOWORD 1 WORD DWORD 1 kendif ifndef HIWORD Programming Notes and Examples SED1355 Issue Date 99 04 27 X23A G 003 05 Page 94 kk kk kk E define endif ifndef define endif ifndef define endif ifndef define endif ifndef define endif define define ifndef ifdef define N else define N endif endif Epson Research and Development Vancouver Design Center HIWORD 1 WORD DWORD 1 gt gt 16 OXFFFF TR TR FALSI FALSI A EWORD EWORD lo hi WORD WORD lo WORD hi lt lt 8 ELONG ELONG lo hi long WORD 10 DWORD WORD hi lt lt 16 Se Gl Di OFF 0 ON N 1 LL _ cplusplus LL 0 LL void 0 SE SIZE F SIZI a SIZE F _V S _R define SIZE ERSION is the size of the version string eg 1 00 TATUS is the size of the status string eg b for beta EVISION is
75. y L y EJE B661 rz DEE ot a nay Jequinn Meumeg azig an a pleog uogenjeag sng WS D08SSELNAS Yl OVE ALAL uj quouldojoneg yo1eosoy vosda ow 68 EE A avae 3118833 v zzLanny PON gu a YOJSSELOIS oO a AQ nL anoo anyo 69 89 9 HOLOANNOO Z Sd 1 081 OS zi 081 Tor 7 E ayaa 2118434 BI KI SH E ZSSA OVO o H EI ISSA VA E a oon oe OLEA 8SSA 6 va SSA 7 EI SH vag 3118433 Ko e A A sor ama essa L A EA i A z e vag 3118833 ER nko anyo anyo nko anyo 2 NeW 99 so 9 9 zo EE H d eaan7ova a eg 3118833 zaan ova A A S L wor u vdan zg CL E Ei Ei Ei Ei D n e gaan saga Ly Siivdd4 TO0A Sg SS o Me Se vLivdda eaan L gt elivdds ZOA DRGeCH 1AA EI anvo isos Zeie ds OLlvdds Cep pno ino an9 Y Y 81V0d3 X ziwads 7 MN EU EH 6 enva eave pang D D Bierg osna weng a za a Bert F S 2 Dep Ela LIVM Ey gt HLIVM Bert Livads 89 89 SONY olvad r stoluvads KO lt Sum Z14IHSd4 37 Ma 13838 Hp lt 13838 IHSd 4 LsIHSd4 JNda 57 Nilda 88 by e 2 weg 3 WV84d4 EIER 04 08 04M b 03M HIM re DEI anaasns 17 aNadsns 00 Lor SM DEEM gc SZ aen 8 viga eiga sam Ham ziga svon svon tga Ge Te svor orga au 7 SV8 6ga saa 180 98a saa vaa ega zaa D s oga Isrola ozav CO HO ziav ISO siav vigy oan gigy DO SOMuL ein Law Pi LOIdD OLWN orgy COMES cay EN say Zei E IVN sav SYN sav oN vay ev cay avn zav e lav OVA Km erch DUR E E 9 S El y E z T
76. 0 0 ns t13 Rising edge of MEMR toSD 15 0 tri state read cycle 5 25 5 10 ns 1 If the SED1355 host interface is disabled the timing for IOCHRDY driven low is relative to the falling edge of MEMR MEMW or the first positive edge of BUSCLK after LatchA20 SA 19 0 M R becomes valid whichever one is later 2 Ifthe SED1355 host interface is disabled the timing for SD 15 0 driven is relative to the falling edge of MEMR or the first positive edge of BUSCLK after LatchA20 SA 19 0 M R becomes valid whichever one is later SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 55 Vancouver Design Center 7 1 8 Philips Interface Timing e g PR31500 PR31700 t1 t2 t3 CN DCLKOUT 14 t5 gt gt ADDR 12 0 X t6 t7 ALE t8 CARDREG CARDxCSH CARDxCSL CARDIORD CARDIOWR Sf WE RD t9 t10 gt E wv CARDxWAIT t11 t12 gt e gt D 31 16 write t13 t14 t15 si D 31 16 read X Figure 7 8 Philips Timing Hardware Functional Specification SED1355 X23A A 001 11 Issue Date 99 05 18 Page 56 Epson Research and Development Vancouver Design Center Table 7 8 Philips Timing 3 0V 5 0V Symbol Parameter Min Max Min Max Units ti Clock period 13 3 13 3 ns t2 Clock pulse width low 6 6 n
77. 04h 0100 1111 0100 1111 0100 1111 set horizontal display width REG O5h 0000 0011 0000 0011 0000 0011 set horizontal non display period REG O8h 1101 1111 1101 1111 1101 1111 set vertical display height bits 7 0 REG O9h 0000 0001 0000 0001 0000 0001 set vertical display height bits 9 8 REG OAh 0000 0010 0000 0010 0000 0010 set vertical non display period REG ODh 0000 1101 0000 1101 0000 1101 set 8 bpp and LCD enable REG 19h 0000 0001 0000 0001 0000 0001 set MCLK and PCLK divide REG 1Bh 0000 0001 0000 0001 0000 0001 disable half frame buffer REG 24h 0000 0000 0000 0000 0000 0000 set Look Up Table address to 0 REG 26h load LUT load LUT load LUT load Look Up Table SED1355 X23A G 003 05 Programming Notes and Examples Issue Date 99 04 27 Page 102 Epson Research and Development Vancouver Design Center Table 12 3 Passive Dual Panel 640x480 with 40MHz Pixel Clock Mono 4 Bit EL Mono 8 Bit Color 8 Bit Color 16 Bit Register Notes 640X480 60Hz 640X480 60Hz 640X480 60Hz 640X480 60Hz REG 02h 1000 0010 0001 0010 0001 0110 0010 0110 set panel type REG 03h 0000 0000 0000 0000 0000 0000
78. 13 SwivelView 13 1 Concept Computer displays are refreshed in landscape from left to right and top to bottom computer images are stored in the same manner When a display is used in SwivelView it becomes necessary to rotate the display buffer image by 90 SwivelView rotates the image 90 clockwise as it is written to the display buffer This rotation is done in hardware and is transparent to the programmer for all display buffer reads and writes SwivelView uses a 1024 x 1024 pixel virtual image The following figures show how the programmer sees the image and how the image is actually stored in the display buffer The display is refreshed in the following sense C A D B The application image is written to the SED1355 in the following sense A B C D The SED1355 rotates and stores the application image in the following sense C A D B the same sense as display refresh X23A A 001 11 1024 pixels 1024 pixels lt gt lt gt A Oh A a gt lt u display 5 S H start S E portrait e address 2 c window e Y w a lt gt a W D C v H v image seen by programmer image in display buffer Figure 13 1 Relationship Between The Screen Image and the Image Residing in the Display Buffer Note The image must be written with a 1024 pixel offset between adjacent lines e g 1024 bytes for 8 bpp mode or 2048 bytes for 16 bpp mode and a display start address that is non ze
79. 2 Bit 1 Bit 0 bits 7 0 Ink Cursor Start Address Select Bits 7 0 These bits define the start address for the Ink Cursor buffer The Ink Cursor buffer must be posi tioned where it does not conflict with the image buffer and half frame buffer see Memory Map ping for details The start address for the Ink Cursor buffer is programmed as shown in the following table where Display Buffer Size represents the size in bytes of the attached DRAM device see MD 7 6 in Summary of Configuration Options Table 8 18 Ink Cursor Start Address Encoding Ink Cursor Start Address Bits 7 0 Start Address Bytes 0 Display Buffer Size 1024 n 255 1 Display Buffer Size n x 8192 The Ink Cursor image is stored contiguously The address offset from the starting word of line n to the starting word of line n 1 is calculated as follows Ink Address Offset words REG 04h 1 Cursor Address Offset words 8 Alternate FRM Register REG 31h RW Alternate Alternate Alternate Alternate Alternate Alternate Alternate Alternate FRM FRM FRM FRM FRM FRM FRM FRM Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 bits 7 0 Alternate Frame Rate Modulation Select Register that controls the alternate FRM scheme When all bits are set to zero the default FRM is selected For single passive or dual passive with the half frame buffer enabled either the original or the
80. 2 description STN TFT Select between a passive LCD and TFT D TFD panel EL Enable EL panel support Panel Interdace Select panel interface width in bits The bit width values will change when selecting between STN and TFT D TFD panels FPline Polarity Select the polarity of the FPLINE pulse FPframe Polarity Select the polarity of the FPFRAME pulse Dimensions Select the width and height of the panel in pixels Frame Rate Select the desired frame rate 1355CFG Configuration Program SED1355 Issue Date 98 10 30 X23A B 001 02 Page 12 Epson Research and Development Vancouver Design Center CRT Page gt 1355Cfg 1355test exe ES General Memory Panel CRT Defaut Simultaneous Display Options CRT Dimensions CRT Frame Rate Normal e mia Line Doubling Interlace C Even Scan Only Open Save As Exit Figure 4 CRT Page The CRT Page allows the user to select the following settings CRT Page Select the desired resolution See Comments on page 17 if the CRT Dimensions d desired CRT dimensions are grayed out CRT Frame Rate Select the desired frame rate See Comments on page 17 to determine valid CRT frame rates For simultaneous display only Will be grayed out if simultaneous display is not supported based on the other Simultaneous Display e i e Options configuration settings For summary of Simultaneous Display options see the Hardware Functiona
81. 26 REG 0E Screen 1 Line Compare Register 0 Line Line Line Line Line Line Line Line Compare Compare Compare Compare Compare Compare Compare Compare Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG OF Screen 1 Line Compare Register 1 Line Line n a n a n a n a n a n a Compare Compare Bit 9 Bit 8 Figure 5 6 Screen 1 Line Compare These two registers form a value known as the line compare When the line compare value is equal to or greater than the physical number of lines being displayed there is no visible effect on the display When the line compare value is less than the number of physically displayed lines display operation works like this 1 From the end of vertical non display to the number of lines indicated by line compare the dis play data will be from the memory pointed to by the Screen 1 Display Start Address 2 After line compare lines have been displayed the display will begin showing data from Screen 2 Display Start Address memory REG 13h Screen 2 Display Start Address Register 0 Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 14h Screen 2 Display Start Address Register 1 Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 REG 15h Screen 2 Display Start Address Registe
82. 33 5 2 2 60 40 4 15 2 FPM 70 50 3 15 1 Reserved This reserved bit must be set to 0 Hardware Functional Specification Issue Date 99 05 18 SED1355 X23A A 001 11 Page 118 Epson Research and Development Vancouver Design Center Performance Enhancement Register 1 REG 23h RW CPU to CPU to d A Display FIFO Display FIFO Display FIFO Display FIFO Display FIFO Display FIFO Memory Wait Memory Wait Threshold Threshold Threshold Threshold Threshold Ge siete atale Bit 4 Bit3 Bit 2 Bit 1 Bit 0 Bit 1 Bit 0 bit 7 Display FIFO Disable When this bit 1 the display FIFO is disabled and all data outputs are forced to zero e the screen is blanked This accelerates screen updates by allocating more memory bandwidth to CPU accesses When this bit 0 the display FIFO is enabled Note For further performance increase in dual panel mode disable the half frame buffer see section 8 2 7 and disable the cursor see section 8 2 9 bit 6 5 CPU to Memory Wait State Bits 1 0 These bits are used to optimize the handshaking between the host interface and the memory con troller The bits should be set according to the relationship between BCLK and MCLK see the table below where Tp and Ty are the BCLK and MCLK periods respectively Table 8 16 Minimum Memory Timing Selection Wait State Bits 1 0 Condition 00 no restrictions default 01 2Tm 4ns gt Tg 10 undef
83. 44 CRT Timing VDP Vertical Display Period REG O9h bits 1 0 REG O8h bits 7 0 1 VNDP Vertical Non Display Period REG OAH bits 5 0 1 HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period HNDP HNDP gt REG O5h bits 4 0 1 8Ts Note The signals RED GREEN and BLUE are analog signals from the embedded DAC and represent the color components which make up each pixel SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Vancouver Design Center Page 99 VRTC bk pt3 E aa eg Zeg Figure 7 45 CRT A C Timing Symbol Parameter Min Typ Max Units ti VRTC cycle time note 1 t2 VRTC pulse width low note 2 13 VRTC falling edge to FPLINE falling edge note 3 phase difference 1 t8 min REG O9h bits 1 0 REG O8h bits 7 0 1 REG OAh bits 6 0 1 lines 2 t9min REG OCH bits 2 0 1 lines 3 t12min REG 06h bits 4 0 1 8 Ts Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 100 8 Registers Epson Research and Development Vancouver Design Center 8 1 Register Mapping The SED1355 registers are memory mapped The system addresses the registers through the CS M R and AB 5 0 input pins When CS 0 and M R 0 the registers are mapped by address bits A
84. 5 Figure 7 6 Figure 7 7 Figure 7 8 Figure 7 9 Figure 7 10 Figure 7 11 Figure 7 12 Figure 7 13 Figure 7 14 Figure 7 15 Figure 7 16 Figure 7 17 Figure 7 18 Figure 7 19 Figure 7 20 Figure 7 21 Figure 7 22 Figure 7 23 Figure 7 24 Figure 7 25 Figure 7 26 Figure 7 27 Figure 7 28 Figure 7 29 Hardware Functional Specification Issue Date 99 05 18 Page 9 List of Figures Typical System Diagram SH 4 BUS e 15 Typical System Diagram SH 3 Bus 15 Typical System Diagram MC68K Bus 1 16 Bit 68000 o 16 Typical System Diagram MC68K Bus 2 32 Bit 68030 o 16 Typical System Diagram Generic Bus aoaaa 17 Typical System Diagram NEC VR41xx MIPS BUS o o 17 Typical System Diagram Philips PR31500 PR31700 Bus oo 18 Typical System Diagram Toshiba TX3912 BUS o o 18 Typical System Diagram Power PC Bus 19 Typical System Diagram PC Card PCMCIA Bus 19 Pinout Diagrams sesana eg Se a Beek See Se ge BP ae ee ee 22 External Circuitry for CRT Interface 36 SHA TUS A a A ds Sat E ESA A A A 41 SHS TIOS e A AT A a a e Mas ee reals 43 MC68000 Timing E A a A ee ES 45 MC 68030 Timing ic is Re RE Mow EE 47 PC Card Timing o at a A Benes o A Se SE eee BE Beet d 49 Generic TIMIDE es me es Oe ees RA EU ae E Rea e Roe eS 3 51 MIBS ISA Timing e a A A a O A AE ASE 3 53 Philips Timing
85. 7 32 8 Bit Single Color Passive LCD Panel Timing Format 2 o o 85 Figure 7 33 8 Bit Single Color Passive LCD Panel A C Timing Format 2 o 86 Figure 7 34 16 Bit Single Color Passive LCD Panel Timing 87 Figure 7 35 16 Bit Single Color Passive LCD Panel A C Timing 88 Figure 7 36 8 Bit Dual Monochrome Passive LCD Panel Timing 89 Figure 7 37 8 Bit Dual Monochrome Passive LCD Panel A C Timing 90 Figure 7 38 8 Bit Dual Color Passive LCD Panel Timing 91 Figure 7 39 8 Bit Dual Color Passive LCD Panel A C Timing 92 Figure 7 40 16 Bit Dual Color Passive LCD Panel Timing 93 Figure 7 41 16 Bit Dual Color Passive LCD Panel A C Timing o 94 Figure 7 42 16 Bit TFT D TFD Panel Timing 95 Figure 7 43 TEI D TFD A C Timing 200 002 e E E a e e Dee a a 96 Figure TAk CRT Timings s erg A A A A RA e A Ss 98 Figure 7 45 CRT A C Timing oo cc coo ara a EE 99 Figure 9 1 Display Buffer Addressing a 123 Figure 10 1 1 2 4 8 Bit per pixel Format Memory Organization 000 125 Figure 10 2 15 16 Bit per pixel Format Memory Organization 200 126 Figure 10 3 Image Manipulation 0 0 0 00000 00000000000 000 127 Figure 11 1 1 Bit per pixel Monochrome Mode Data OutputPath
86. 7 MIPS ISA Interface Timing t1 t2 13 a BUSCLK I t4 t5 LatchA20 SA 19 0 X M R SBHE t6 CS e O MEMR MEMW Bi SR al t8 IOCHRDY WE t9 t10 SD 15 0 write t11 t12 t13 SD 15 0 read Figure 7 7 MIPS ISA Timing Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 54 Epson Research and Development Vancouver Design Center Table 7 7 MIPS ISA Timing 3 0V 5 0V Symbol Parameter Min Max Min Max Units ti Clock period 20 20 ns t2 Clock pulse width high 6 6 ns t3 Clock pulse width low 6 6 ns t4 LatchA20 SA 19 0 M R SBHE setup to first BUSCLK where 10 10 ee CS 0 and either MEMR 0 or MEMW 0 5 LatchA20 SA 19 0 M R SBHE hold from rising edge of 0 0 ris either MEMR or MEMW t6 CS hold from rising edge of either MEMR or MEMW 0 0 ns EX ert edge of either MEMR or MEMW to IOCHRDY driven 0 0 he ow t8 Rising edge of either MEMR or MEMW to IOCHRDY tri state 5 25 2 5 10 ns 9 Si 5 0 setup to third BUSCLK where CS 0 MEMW 0 10 10 Ss write cycle t10 SD 15 0 hold write cycle 0 0 ns t117 Falling edge MEMR to SD 15 0 driven read cycle 0 0 ns t12 SD 15 0 setup to rising edge IOCHRDY read cycle
87. A 20 1 A0 GND DB 15 0 D 15 0 WEIS LUBEN M R A21 CS CS3 CS4 CS5 or CSE BUSCLK SDCLKOUT BS Connected to VDD 3 3V RD WR CLBEN RD IORD WE0 TOWR WAIT READY RESET connected to system reset Note The bus signal AO is not used by the SED1355 internally Interfacing to the NEC V832 Microprocessor Issue Date 99 05 05 Epson Research and Development Page 11 Vancouver Design Center 3 2 Host Bus Interface Signal Descriptions The SED1355 PC Card Host Bus Interface requires the following signals BUSCLK is a clock input which is required by the SED1355 Host Bus Interface It is driven by the V832 signal SDCLKOUT The address inputs AB 20 0 and the data bus DB 15 0 connect directly to the V832 address A 20 0 and data bus D 15 0 respectively MD4 must be set to select little endian mode upon reset M R memory register selects between memory or register access It may be connected to an address line allowing system address A21 to be connected to the M R line Chip Select CS must be driven low by CSx where x is the V832 chip select used whenever the SED1355 is accessed by the V832 WE1 and RD WR connect to LUBEN and LLBEN the byte enables for the high order and low order bytes They are driven low when the V832 is accessing the SED1355 RD connects to IORD the read enable signal from the V832 WBO connects to IOWR the write enable signal from the V832 WAIT is a signal o
88. AD Epson Research and Development Inc SED1355 Hardware Functional Specification Document Number X23A A 001 xx e Epson Research and Development Inc SDUI355B0B Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X19A G 001 xx 6 2 Document Sources e Motorola Literature Distribution Center 800 441 2447 e Epson Electronics America Website www eea epson com SED1355 Interfacing to the Motorola MPC821 Microprocessor X23A G 008 03 Issue Date 99 05 05 Epson Research and Development Vancouver Design Center 7 Technical Support 7 1 EPSON LCD CRT Controllers SED1355 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http www epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 7 2 Motorola MPC821 Processor e Motorola Design Line 800 521 6274 Local Motorola sales office or authorized distributor Interfacing to the Motorola MPC821 Microprocessor Issue Date 99 05 05 Page 23 Taiwan R O C Epson Taiwan Technology
89. AM A Beier Pie Boe Gee A 21 4 2 9 EG Interface 2 27 DEES oka ee EE elo eee cece eo oe ak 21 AD AO DAC A iP se to ets Reds owe ek oe A e ek e Guede ek Ee ee 21 A2 TI Eemer Saves ciclo tee eB aoa Re a A Ai wah ae 21 ek UCEIOCKS fee BS ee ate hho oe ee oS Ob te SA hoe le eed 21 LG PINS o EE 22 5 1 Pinout Diagram 22 5 2 Pin Description Othe As AS Git te a a Oe A ee ee hE Bn o a ZO 5 2 1 Host Interfaces uba tt BS dee beh Be th eset Ae e bl AAE 23 5 2 2 Memory Interface lt i eet ee oaks oh eee A eee oe A baie a 29 32 3 LGD Interface ota 2 ots Pe kk Ae oe Be Pe Bele ee PER Ghee a wales 31 ILA SORT Interface geg Se arid Sige Ge aL de Sl oe Bo le Re Ele ie Se BCR Go usecase Se 31 5 23 Miscellaneous 32 a ak A eth ERM Ba Gee PE eee ees 32 5 3 Summary of Configuration Options is 33 5 4 Multiple Function Pin Mapping 34 5 5 CRT Interface 36 6 D C Characteristics ue E a ELE a ee ee ed eee a ee CNS 37 Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 4 Epson Research and Development Vancouver Design Center 7 A C Characteristics 7 1 72 7 3 7 4 7 5 8 1 8 2 SED1355 8 2 1 8 2 2 8 2 3 8 2 4 CPU Interface Timing 7 1 1 SH 4 Interface Timing 7 1 2 SH 3 Interface Timing 7 1 3 7 1 4 7 1 5 PC Card Interface Timing 7 1 6 Generic Interface Timing 7 1 7 MIPS SA Interface Timing 7 1 8 7 1 9 Toshiba Interface Timing e g TX3912 7 1 10 Clock I
90. Address Starting address of the registers in hexadecimal Memory Address Starting address of the display buffer in hexadecimal CPU Bus Width Host CPU bus width applicable only to PC CM Clock frequency Bus Clk Host bus clock frequency Also displayed is the memory clock frequency and the pixel clock frequencies for the following modes LCD CRT and simultaneous display These clock values will change based on settings on both the General Page and other configuration pages These clock frequencies are useful in determining why a particular display mode cannot be set See the SED1355 Hardware Functional Specification document number X23A A 001 xx for more details 1355CFG Configuration Program SED1355 Issue Date 98 10 30 X23A B 001 02 Page 10 Epson Research and Development Vancouver Design Center Memory Page 22 gt 1355Cfg 1355test exe General Memory Panel CRT Default Memory Configuration a a ns e EDO 2CAstt Refresh time CPM O WER 32 Xi ms C 7Ons Memory Performance Default Suspend Mode Refresh Tre 104 4104 ns CAS before RAS Self Refresh C No Refresh Tp 40 40 ns fo Trac 60 feo Open Save As Exit Figure 2 Memory Page The Memory Page allows the user to select the following settings Memory Page Timing ns Access time for memory Memory Type EDO or FPM WE Control 2 CAS or 2 WE Refresh
91. C 27 dc3vs N C 8 chA6p8 N C 28 GND GND 9 chA6p9 N C 29 dc12v DC12V 10 chA6p10 N C 30 GND GND 11 ib1 XL 31 battery N C 12 ib2 XR 32 GND GND 13 ib3 YU 33 dcXA N C 14 ib4 YL 34 base5vDc N C 15 ib5 N C 35 dcXB N C 16 ib6 N C 36 GND GND 17 ib7 N C 37 dcXC N C 18 ib8 XY 38 GND GND 19 GND GND 39 senseH N C 20 GND GND 40 senseL N C Evaluation Board User Manual Issue Date 98 10 30 SDU1355 D9000 X23A G 002 03 Page 16 Epson Research and Development Table 3 2 Connectors Pinout for Channel A6 Continued Vancouver Design Center Channel A6 Pin FPGA Signal SED1355 Signal Pin FPGA Signal SED1355 Signal SmZ 1 chA6p11 M R 21 GND GND 2 chA6p12 RD 22 GND GND 3 chA6p13 WE1 23 chA6p34 N C 4 chA6p14 RESET 24 GND GND 5 chA6p15 N C 25 GND GND 6 chA6p16 N C 26 GND GND 7 chA6p17 N C 27 chA6p33 D15 8 chA6p18 D14 28 GND GND 9 chA6p19 D13 29 GND GND 10 chA6p20 D12 30 GND GND 11 chA6p21 D11 31 chA6p32 D10 12 chA6p22 D9 32 GND GND 13 chA6p23 D8 33 GND GND 14 chA6p24 D7 34 GND GND 15 chA6p25 D6 35 GND GND 16 chA6p26 D5 36 chA6p31 D4 17 chA6p27 D3 37 GND GND 18 chA6p28 D2 38 GND GND 19 chA6p29 D1 39 GND GND 20 chA6p30 DO 40 GND GND SDU1355 D9000 X23A G 002 03 Evaluation Board User Manual Issue Date 98 10 30 Epson Research and Development Page 17 Vancouver Design Center 3 1 2 Memo
92. CAS Figure 7 21 FPM DRAM Self Refresh Timing Table 7 20 FPM DRAM CBR Self Refresh Timing Symbol Parameter Min Max Units tl Internal memory clock 40 ns e RAS precharge time REG 22h bits 3 2 00 2 45 t1 1 ns RAS precharge time REG 22h bits 3 2 01 or 10 1 45 1 1 ns e RAS to CAS precharge time REG 22h bits 3 2 00 2 tl ns RAS to CAS precharge time REG 22h bits 3 2 01 or 10 1t1 ns H CAS setup time CASH before RAS refresh 0 45t1 2 ns SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 75 Vancouver Design Center 7 4 Power Sequencing 7 4 1 LCD Power Sequencing SUSPEND or LCD Enable Bit LCDPWR t2 t3 gt FPFRAME FPLINE FPSHIFT FPDATA DRDY t4 CLKI S Figure 7 22 LCD Panel Power OO Power On Timing Drawn with LCDPWR set to active high polarity Table 7 21 LCD Panel Power Off Power On Symbol Parameter Min Max Units t1 SUSPEND or LCD ENABLE BIT low to LCDPWR off e ns t2 SUSPEND or LCD ENABLE BIT low to FPFRAME inactive 1 Frames t3 FPFRAME inactive to FPLINE FPSHIFT FPDATA DRDY inactive 128 Frames t4 SUSPEND to CLKI inactive 130 Frames 5 SUSPEND or LCD ENABLE BIT high to FPLINE FPSHIFT TFPERAME FPDATA DRDY active 8TPcLK FPLINE FPSHIFT FPDATA DRDY active to LCDPWR on and t6 EPFRAME active 128 Frames t7 CLKI active to SUSPEND inac
93. CRT displays Passive LCD displays are limited to using the four most significant bits from each of the red green and blue portions of each color The result is 4096 24 EM 2 possible colors Should monochrome mode be chosen at this color depth the output reverts to sending the four most significant bits of the green LUT component to the modulator for a total of 16 possible gray shades In this situation one might as well use four bit per pixel mode and conserve display buffer 3 1 6 Memory Organization for Sixteen Bit Per Pixel 65536 Colors 16 Gray Shades Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Red Bit 4 Red Bit 3 Red Bit 2 Red Bit 1 Red Bit 0 Green Bit 5 Green Bit 4 Green Bit 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Green Bit 2 Green Bit 1 Green Bit 0 Blue Bit 4 Blue Bit 3 Blue Bit 2 Blue Bit 1 Blue Bit 0 SED1355 X23A G 003 05 Figure 3 6 Pixel Storage for 16 Bpp 65536 Colors 16 Gray Shades in Two Bytes of Display Buffer In 16 bit per pixel mode the SED 1355 is capable of generating 65536 colors The 65536 color pixel is divided into three parts five bits for red six bits for green and five bits for blue In this mode the Look Up Table is bypassed and output goes directly into the Frame Rate Modulator The full color range is only available on TFT D TFD or CRT displays Passive LCD
94. Capacitance 12 pF SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 39 Vancouver Design Center Table 6 4 Electrical Characteristics for VDD 3 3V typical Symbol Parameter Condition Min Typ Max Units lobos Quiescent Current Quiescent Conditions 290 uA liz Input Leakage Current 1 1 uA loz Output Leakage Current 1 1 uA VDD min i lol 2mA Type1 Vou High Level Output Voltage 4mA Type2 Vop 0 3 V 6mA Type3 VDD min loL 2mA Type1 VoL Low Level Output Voltage 4mA Type2 0 3 V 6mA Type3 Vin High Level Input Voltage CMOS level Vpp max 2 2 V Vu Low Level Input Voltage CMOS level Vpp min 0 8 V CMOS Schmitt Vr High Level Input Voltage Vpp 3 3V 2 4 V CMOS Schmitt Vr Low Level Input Voltage Von 3 3V 0 6 V d CMOS Schmitt Vu Hysteresis Voltage Vpp 3 3V 0 1 V Rpp Pull Down Resistance Vi Vop 90 180 360 kQ Ci Input Pin Capacitance 12 pF Co Output Pin Capacitance 12 pF Cio Bi Directional Pin Capacitance 12 pF Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 40 Epson Research and Development Vancouver Design Center Table 6 5 Electrical Characteristics for VDD 3 0V typical Symbol Parameter Condition Min Typ Max Units Ipps Quiescent Current Quiescent Conditions
95. Epson Research and Development Vancouver Design Center 3 2 PC Card Host Bus Interface Signals The SED1355 PC Card host bus interface is designed to support processors which interface the SED1355 through the PC Card bus The SED1355 PC Card host bus interface requires the following signals from the PC Card bus e BUSCLK is a clock input which is required by the SED1355 host bus interface It is separate from the input clock CLKD and is typically driven by the host CPU system clock Since PC Card signalling is independent of any clock BUSCLK can come from any oscillator already implemented For example the source for the CLKI input of the SED1355 may be used e The address inputs AB 20 0 and the data bus DB 15 0 connect directly to the PC Card address A 20 0 and data bus D 15 0 respectively MD4 must be set to select little endian mode upon reset e M R memory register selects between memory or register access It may be connected to an address line allowing system address A21 to be connected to the M R line e Chip Select CS must be driven low whenever the SED1355 is accessed by the PC Card bus WEIS and RD WR connect to CE2 and CE1 the byte enables for the high order and low order bytes They are driven low when the PC Card bus is accessing the SED1355 e RD connects to OE the read enable signal from the PC Card bus e WEO connects to WE the write enable signal from the PC Card bus e WAIT is
96. For Toshiba TX3912 Bus this pin inputs the even byte access enable signal CARDxCSL e For PowerPC Bus this pin inputs the read write signal RD WR e For PC Card PCMCIA Bus this pin inputs the card enable 1 signal CE1 See Host Bus Interface Pin Mapping for summary See the respective AC Timing diagram for detailed functionality SED1355 X23A A 001 11 Hardware Functional Specification Issue Date 99 05 18 Epson Research and Development Vancouver Design Center Page 27 Table 5 1 Host Interface Pin Descriptions Continued Pin Name Type Pin Cell RESET State Description RD CS Hi Z This is a multi purpose pin For SH 3 SH 4 Bus this pin inputs the read signal RD For MC68K Bus 1 this pin is connected to Vpp For MC68K Bus 2 this pin inputs the bus size bit 1 SIZ1 For Generic Bus this pin inputs the read command for the lower data byte RDO For MIPS ISA Bus this pin inputs the memory read signal MEMR For Philips PR31500 31700 Bus this pin inputs the memory read command RD For Toshiba TX3912 Bus this pin inputs the memory read command RD For PowerPC Bus this pin inputs the transfer size O signal TSIZO For PC Card PCMCIA Bus this pin inputs the output enable signal OE See Host Bus Interface Pin Mapping for summary See the respective AC Timing diagram for detailed functionality WEO CS Hi
97. J J L l l ll MOD Si UD 3 0 LD 3 0 UNE XLINE2 LINES X LINE4 X XLINE479XLINE480 LINE1 X LINE2 FPLINE MOD X ER HDP HNDP je Ka gt PESRIRI A JL Pe l UD3 mY 19 Y X X 1 683 X UD2 1 2 X 1 10 a Y 1 634 UD1 13 X 1 11 X SA NN X 1 635 X UDO T4 Y 112 Y E GER GE 1 636 A A LD3 15 X H138X Y A X 1 637 X LD2 16 X 1 14 X X X 1 638 x X LD1 Ee EE 1 X X 1639 KX LDO 18 X 1 16 K X 1 640 x x Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7 26 8 Bit Single Monochrome Passive LCD Panel Timing VDP Vertical Display Period REG 09h bits 1 0 REG O8h bits 7 0 1 VNDP Vertical Non Display Period REG OAN bits 5 0 1 HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period REG O5h bits 4 0 1 8Ts Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 80 Epson Research and Development Vancouver Design Center tl t2 Sync Timing FPFRAME t3 t4 gt FPLINE t5 MOD Data Timing FPLINE t8 t11 j t12 FPSHIFT UDI3 0 3 LD 3 0 Figure 7 27 8 Bit Single Monochrome Passive LCD Panel A C Timing Table 7 24 8 Bit Single Monochrome Passive LCD Panel A C Timing Symbol Parameter Min Typ Max Units t1 FPFRAME setup to FPLIN
98. OW E E p E E 7 E le ho fi 12 19 14 15 16 17 18 19 20 21 22 20 24 2526 27 28 2o30 a1 a2 Figure 5 1 Pinout Diagram 128 pin QFP15 surface mount package SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 23 Vancouver Design Center 5 2 Pin Description Key O U CD CS COx TSx TSxD CNx Input Output Bi Directional Input Output Analog Power pin CMOS level input CMOS level input with pull down resistor typical values of 100KQ 180KQ at 5V 3 3V respectively CMOS level Schmitt input CMOS output driver x denotes driver type see tables 6 3 6 4 6 5 for details Tri state CMOS output driver x denotes driver type see tables 6 3 6 4 6 5 for details Tri state CMOS output driver with pull down resistor typical values of 100KQ 180KQ at 5V 3 3V respectively x denotes driver type see tables 6 3 6 4 6 5 for details CMOS low noise output driver x denotes driver type see tables 6 3 6 4 6 5 for details 5 2 1 Host Interface Table 5 1 Host Interface Pin Descriptions Pin Name RESET Type Pin Cell Description State ABO e For SH 3 SH 4 Bus this pin inputs system address bit O AO e For MC68K Bus 1 this pin inputs the lower data strobe LDS e For MC68K Bus 2 this pin inputs system address bit 0 AO e For Generic Bus this pin inputs system address bit 0 AO e For MIPS ISA Bus this pin inpu
99. Parameter Min Max Units CAS Hold to RAS REG 22h bit 6 5 00 and bits 24511 3 ns 3 2 00 CAS Hold to RAS REG 22h bit 6 5 00 and bits 3t1 3 ns 3 2 01 CAS Hold to RAS REG 22h bit 6 5 00 and bits 3 4511 3 hs 3 2 10 CAS Hold to RAS REG 22h bit 6 5 01 and bits 14511 3 SE 3 2 00 16 CAS Hold to RAS REG 22h bit 6 5 01 and bits 24 3 hs 3 2 01 CAS Hold to RAS REG 22h bit 6 5 01 and bits 24511 3 Se 3 2 10 CAS Hold to RAS REG 22h bit 6 5 10 and bits 0 45t1 3 s 3 2 00 CAS Hold to RAS REG 22h bit 6 5 10 and bits 1t1 3 ns 3 2 01 CAS Hold to RAS REG 22h bit 6 5 10 and bits 1 4511 3 ns 3 2 10 SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Vancouver Design Center Page 69 7 3 3 EDO DRAM Self Refresh Timing Stopped for Restarted for suspend mode active mode Memory Ee be Sg Clock t2 RAS a If D H t5 CAS Figure 7 17 EDO DRAM Self Refresh Timing Table 7 17 EDO DRAM Self Refresh Timing Symbol Parameter Min Max Units tl Internal memory clock period 25 ns RAS precharge time REG 22h bits 3 2 00 2t1 3 ns t2 RAS precharge time REG 22h bits 3 2 01 1 45t1 3 ns RAS precharge time REG 22h bits 3 2 10 1t1 3 ns S RAS to CAS precharge time REG 22h bits 3 2 00 1 45t1 3 ns RAS to CAS precharge t
100. Polarity Slct n a REG 08h VERTICAL DISPLAY HEIGHT R n a EGISTER 0 HRTC FPLINE Pulse Width 8 REG 1 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 REG 09h VERTICAL DISPLAY HEIGHT R Vertical Display Height REG Bit 4 EGISTER 1 Bit 3 RW X23A R 001 02 REG 11h SCREEN 1 DISPLAY START ADDRESS REGISTER 1 Bit 15 Bit 14 Bit 13 Screen 1 Start Address Bit 12 Bit 11 Bit 10 Bit 9 RW Bit 8 REG 12h SCREEN 1 DISPLAY START ADDRESS REGISTER 2 REG 13h SCREEN 2 DISPLAY START ADDRESS REGISTER 0 Screen 1 Start Address Bit 18 Bit 17 RW Bit 7 Bit 6 Bit 5 Bit 4 Screen 2 Start Address Bit 3 REG 14h SCREEN 2 DISPLAY START ADDRESS REGISTER 1 Bit 15 Bit 14 Bit 13 Bit 12 Screen 2 Start Address Bit 11 REG 15h SCREEN 2 DISPLAY START ADDRESS REGISTER 2 RW Screen 2 Start Address n a n a n a n a R E p z Bit 19 Bit 18 Bit 17 Bit 16 REG 16h MEMORY ADDRESS OFFSET REGISTER 0 RW Memory Address Offset Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O REG 17h MEMORY ADDRESS OFFSET REGISTER 1 RW n a n a n a n a n a Mem Bit 10 Bit 9 ory Address Offset Bit 8 REG 18h PIXEL PANNING REGISTER Screen 2 Pixel Panning Bit 2 Bit 1 REG 19h CLOCK CONFIGURATION REGISTER Screen 1 Pi Bit 2 xel Panning Bit 1 RW RW Reserved n a n a n a REG 1Ah Power SAVE CONFIGURATION R
101. R636 UD2 o B1 X 1 P2 ARO 1 G7 X1 G12X LEI D 1 B636 LD G2 X 1 B2 Y 1 B7 X 1 88 X1 R13 AEN X KEEA e UDO WW R3 X 1 G3 X 1 68 X 1 88 Y 1 B13X RI D mes OO i Y LD3 o 83 X 14 LP LS X1 G14 X 1B14 4 V De AX LD2 AN G4 Y 1 B4 Y 1B9 X1 RIO Y 1 RI5 AE X Geng LD1 o R5 Y 1 65 Y 1 G10X 1 810 Y 1 815 X 1 RI64 Y 1 R640 7 x LDO D B5 X 1 R6 X 1 R11X 1 G11X1 G16X 1 Biex Y X 1 8640 Se x D Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7 30 8 Bit Single Color Passive LCD Panel Timing Format 1 VDP Vertical Display Period REG 09h bits 1 0 REG O8h bits 7 0 1 VNDP Vertical Non Display Period REG OAH bits 5 0 1 HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period REG O5h bits 4 0 1 8Ts Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 84 Epson Research and Development Vancouver Design Center tl Sync Timing Kg FPFRAME gt t3 t4 FPLINE i Data Timing FPLINE y t5a 139 t6 t7 t8a le t9 FPSHIFT d t8b gt FPSHIFT2 DN E O t12 t13 KN UDI3 0 8 y S LD 3 0 Figure 7 31 8 Bit Single Color Passive LCD Panel A C Timing Format 1 Table 7 26 8 Bit Single Color Passive LCD Pane
102. Save The Power Save block contains the power save mode circuitry 4 2 12 Clocks The Clocks module is the source of all clocks in the chip Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 22 Epson Research and Development Vancouver Design Center 5 Pins 5 1 Pinout Diagram lee fos oa oa 92 fo feo feo se a se es ea ee aoa lso ze ze z7 ze zs za zs ez zo eo ee e7 ee es N u T TUU TT TU TUVO TU TU ins us Blus Blus Blus us le ene D CO 0 0 OC Dm C oo gt gt gt oO DD DD DD DD op D DD DD DD oo yg UCmMTOSSOO0OAO Ga S h 334333333 3433333333 EIZ oom ee e 00 Jo o bo M e mn m Z T Z 97 o E Go HM A O D m E 64 21 VDD g MA5 Li 63 28 pacvss Mar E _ 99 DACVDD MA6 62 _ 100 ED mao BI 101 IREF MA7 E _102 DACVDD MA10 ES 103 GREEN MAS a 104 104 bacvoD MA11 Ge 05 BLUE MA9 EC 106 pacvss VDD SE 107 upre RAS 108 ver WE LG 109 vop UCAS ra AHO yss LCAS 50 a2 2 SE 113 Ges e 48 1 asia SED1 355 MS E 114 47 el 4817 MD6 iors U5 apie MD9 CG era AB15 MD5 E AB14 MD10 Li 1181 Ap mp4 119 42 AB12 MD11 120 AB11 mba 121 AB10 mo12 0 122 39 a e ABs mp13 28 124 37 i AB7 eg 125 ape mota 36_ AB4 vpus L 12 128 aps vop L DD w Z Z 2G 5 ZS ooOoooo lt lt lt SSSSSBSRmMs MS ORS 2PVFGHVaGogssysgssgysE NOR 2 a HF OKA OK o bk o MA GO oO AAN DOAK ANH A
103. UDS and LDS high to D 15 0 invalid high impedance read 5 25 25 10 ae cycle t17 AS high setup to CLK 2 2 ns 1 Ifthe SED1355 host interface is disabled the timing for DTACK driven high is relative to the falling edge of CS AS or the first positive edge of CLK after A 20 1 M R becomes valid whichever one is later 2 Ifthe SED1355 host interface is disabled the timing for D 15 0 driven is relative to the falling edge of UDS LDS or the first positive edge of CLK after A 20 1 M R becomes valid whichever one is later SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 47 Vancouver Design Center 7 1 4 MC68K Bus 2 Interface Timing e g MC68030 t1 t2 t3 a EE t4 t5 gt lt A 20 0 SIZ 1 0 M R t6 CS t17 gt lt AS t11 DS t7 t8 gt e R W t9 t10 gt dE Es DSACK1 Be t12 t13 h gt le gt D 31 16 write t14 t15 t16 gt e gt D 31 16 read Figure 7 4 MC68030 Timing Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 48 Epson Research and Development Vancouver Design Center
104. V VouT Output Voltage Vss 0 3 to Vpp 0 5 Ter Storage Temperature 65 to 150 C Tso Solder Temperature Time 260 for 10 sec max at lead C Table 6 2 Recommended Operating Conditions Symbol Parameter Condition Min Typ Max Units Vop Supply Voltage Vsg 0V 2 7 3 0 3 3 5 0 5 5 V Vin Input Voltage Vss Vop Topr Operating Temperature 40 25 85 C Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 38 Epson Research and Development Vancouver Design Center Table 6 3 Electrical Characteristics for VDD 5 0V typical Symbol Parameter Condition Min Typ Max Units lbos Quiescent Current Quiescent Conditions 400 uA liz Input Leakage Current 1 1 uA loz Output Leakage Current 1 1 uA VDD min i lo 4mA Type1 i VoH High Level Output Voltage 8mA Type2 Vop 0 4 V 12mA Type3 VDD min lot 4mA Type VoL Low Level Output Voltage 8mA Type2 0 4 V 12mA Type3 Vin High Level Input Voltage CMOS level Vpp max 3 5 Vit Low Level Input Voltage CMOS level Vpp min 1 0 l CMOS Schmitt Vi High Level Input Voltage Vpp 5 0V 4 0 V CMOS Schmitt Vr Low Level Input Voltage Vpp 5 0V 0 8 V CMOS Schmitt Vu Hysteresis Voltage Von 5 0V 0 3 V Rpp Pull Down Resistance Vi Vpp 50 100 200 kQ Ci Input Pin Capacitance 12 pF Co Output Pin Capacitance 12 pF Cio Bi Directional Pin
105. VNDP then update the register Hardware Functional Specification Issue Date 99 05 18 Epson Research and Development Page 121 Vancouver Design Center Cursor Y Position Register 0 REG 2Ah RW Cursor Y Cursor Y Cursor Y Cursor Y Cursor Y Cursor Y Cursor Y Cursor Y Position Bit 7 Position Bit 6 Position Bit5 Position Bit 4 Position Bit 3 Position Bit 2 Position Bit 1 Position Bit 0 Cursor Y Position Register 1 REG 2Bh RW Cursor Y Cursor Y Reserven SS wg Ss na de Position Bit 9 Position Bit 8 REG 2Bh bit 7 Reserved REG 2Ah bits 7 0 REG 2Bh bits 1 0 This bit must be set to 0 left pixel This register must be set to 0 in Ink mode Note Cursor Y Position Bits 9 0 In Cursor mode this 10 bit register is used to program the vertical pixel position of the Cursor s top The Cursor Y Position register must be set during VNDP vertical non display period Check the VNDP status bit REG OAh bit 7 to determine if you are in VNDP then update the register REG 2Ch Ink Cursor Color 0 Register 0 RW Cursor Color 0 Bit 7 Cursor Color 0 Bit 6 Cursor Color 0 Bit 5 Cursor Color 0 Bit 4 Cursor Color 0 Bit 3 Cursor Color 0 Bit 2 Cursor Color 0 Bit 1 Cursor Color 0 Bit O Ink Cursor Color 0 Register 1 REG 2Dh RW Cursor Color Cursor Color Cursor
106. X OHEA e X UD2 LD2 21182 a X X Ye a D VE UD1 LD1 e E EE GES den Ee E V sai UDO LDO CH AH O QU PA REA X Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7 40 16 Bit Dual Color Passive LCD Panel Timing VDP Vertical Display Period REG 09h bits 1 0 REG O8h bits 7 0 1 VNDP Vertical Non Display Period REG OAH bits 5 0 1 HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period REG O5h bits 4 0 1 8Ts Hardware Functional Specification Issue Date 99 05 18 SED1355 X23A A 001 11 Page 94 Sync Timing FPFRAME Epson Research and Development Vancouver Design Center t3 FPLINE t5 MOD Data Timing FPLINE t7 FPSHIFT t14 gt UD 7 0 112 t13 t11 t10 KM LD 7 0 Figure 7 41 16 Bit Dual Color Passive LCD Panel A C Timing Table 7 31 16 Bit Dual Color Passive LCD Panel A C Timing Symbol Parameter Min Typ Max Units t1 FPFRAME setup to FPLINE pulse trailing edge note 2 t2 FPFRAME hold from FPLINE pulse trailing edge 14 Ts note 1 t3 FPLINE period note 3 t4 FPLINE pulse width 9 Ts t5 MOD delay from FPLINE pulse trailing edge note 4 t6 FPSHIFT falling edge to FPLINE pulse leading edge note 5 t7 FPSHIFT falling edge to FPLINE pulse tra
107. amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 SED1355 X23A G 008 03 Page 24 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 Interfacing to the Motorola MPC821 Microprocessor X23A G 008 03 Issue Date 99 05 05 EPSON SED1355 Embedded RAMDAC LCD CRT Controller Interfacing to the Toshiba MIPS TX3912 Processor Document Number X23A G 010 03 Copyright 1998 1999 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 Interfacing to the Toshiba MIPS TX3912 Processor X23A G 010 03 Issue Date 99 05 05 Eps
108. and D15 are the most significant bits for the address and data busses respectively Support is provided for on chip DMA controllers To find further information on these topics refer to Section 6 References on page 18 PC Card bus signals are asynchronous to the host CPU bus signals Bus cycles are started with the assertion of the CE1 and or the CE2 card enable signals The cycle ends once these signals are de asserted Bus cycles can be lengthened using the WAIT signal Note The PCMCIA 2 0 JEIDA 4 1 and later PC Card Standard support the two signals WAIT and RESET which are not supported in earlier versions of the standard The WAIT signal allows for asynchronous data transfers for memory attribute and IO access cycles The RESET signal allows resetting of the card configuration by the reset line of the host CPU 2 1 2 Memory Access Cycles SED1355 X23A G 005 05 A data transfer is initiated when a memory address is placed on the PC Card bus and one or both of the card enable signals CE1 and CE2 are driven low REG must be inactive If only CE1 is driven low 8 bit data transfers are enabled and AO specifies whether the even or odd data byte appears on data bus lines D 7 0 If both CE1 and CE2 are driven low a 16 bit word transfer takes place If only CE2 is driven low an odd byte transfer occurs on data lines D 15 8 Interfacing to the PC Card Bus Issue Date 99 05 05 Epson Research and Development Pa
109. and inverse This leaves two colors which are user definable DevID aregistered device ID Index the cursor index to set Valid values are 0 and 1 Color a DWORD value which hold the requested color ERR OK operation completed with no problems ERR_FAILED returned if Index if other than 0 or 1 int seSetCursorPixel int DeviD long x long y DWORD Color Description Parameters Return Value Draws a single pixel into the hardware cursor The pixel will be of color Color located at x y pixels relative to the top left of the hardware cursor The value of Color must be 0 to 3 Values 0 and 1 refer to the two user definable colors If Color is 2 then the pixel will be transparent and if the value is 3 the pixel will be an inversion of the underlying screen color DevID aregistered device ID x y draw coordinates in pixels relative to the top left corner of the cursor Color a value of 0 to 3 to draw the pixel with ERR OK operation completed with no problems int seDrawCursorLine int DeviD long x1 long y1 long x2 long y2 DWORD Color Description Parameters Return Value Programming Notes and Examples Issue Date 99 04 27 Draws a line between the two endpoints x1 y1 and x2 y2 in the hardware cursor display buffer using color Color The value of Color must be 0 to 3 Values 0 and 1 refer to the two user definable colors If Color is 2 then the pixel will be transparen
110. any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 INTOdUCHON ek SL GER E E Se ee e a Eer rt Poo en SE 11 1 1 Scope 11 1 2 Overview Description 11 2 Features x she ter a ala a a dd aa aaa ate 12 2 1 Memory Interface 12 2 2 CPU Interface 12 2 3 Display Support 13 2 4 Display Modes 13 2 5 Display Features 13 2 6 Clock Source 13 2 7 Miscellaneous 14 Typical System Implementation Diagrams ees 15 Internal Description a 20 4 1 Block Diagram Showing Datapaths 20 42 Block Descriptions his Wie S 1b soba Seek Gh a gl ALL EE 20 ek gt Hostimtertace ts ai ef ta e ia o Pe dee Be eed 20 ADS EE CA ta o a ee EE 20 4 2 4 Memory Controller ic 45 be e A o e AA 21 42 5 Display AA Ee E Sed pe et Ad ease eR reg 21 4 2 6 Cursor FIFO 2 2 da ied ee ee a ee a wai dee d RA 21 4 2 1 Weook Up Tables vice o od EE ee eds 21 ADS ERIC Bee ete Aere A SO
111. appealing output For further information on the half frame buffer and the Alternate FRM Register see the SED1355 Hardware Functional Specification document number X23A A 001 xx Programming Notes and Examples SED1355 Issue Date 99 04 27 X23A G 003 05 Page 12 Epson Research and Development Vancouver Design Center 3 Memory Models The SED1355 is capable of several color depths The memory model for each color depth is packed pixel Packed pixel data changes with each color depth from one byte containing eight consecutive pixels up to two bytes being required for one pixel 3 1 Display Buffer Location The SED 1355 requires either a 512K byte or 2M byte block of memory to be decoded by the system System logic will determine the location of this memory block See Section 9 of the Hardware Functional Specification document number X23A A 001 xx for details 3 1 1 Memory Organization for One Bit Per Pixel 2 Colors Gray Shades Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 5 Pixel 6 Pixel 7 Figure 3 1 Pixel Storage for 1 Bpp 2 Colors Gray Shades in One Byte of Display Buffer In this memory format each byte of display buffer contains eight adjacent pixels Setting or resetting any pixel will require reading the entire byte masking out the appropriate bits and if necessary setting the bits to l
112. assume their selected configuration For details on SED 1355 configuration see Section 4 2 SED1355 Hardware Configuration on page 15 Note At reset the Host Interface Disable bit in the Miscellaneous Disable Register REG 1Bh bit 7 is set to 1 This means that only REG 1Ah read only and REG 1Bh are accessible until a write to REG 1Bh sets bit 7 to 0 making all regis ters accessible When debugging a new hardware design this can sometimes give the appearance that the interface is not working so it is important to remember to clear this bit before proceeding with debugging 3 1 PC Card Host Bus Interface Pin Mapping The following table shows the functions of each host bus interface signal Table 3 1 PC Card Host Bus Interface Pin Mapping SED1355 Pin Name PC Card PCMCIA AB 20 0 A 20 0 DB 15 0 D 15 0 WEI CE2 M R External Decode CS External Decode BUSCLK n a BS Vop RD WR CE1 RD OE WEO WE WAIT WAIT RESET Inverted RESET Note The bus signal AO is not used by the SED1355 internally Although a clock is not directly supplied by the PC Card interface one is required by the SED 1355 PC Card host bus interface For an example of how this can be accom plished see the discussion on BUSCLK in Section 3 2 PC Card Host Bus Interface Signals on page 12 Interfacing to the PC Card Bus SED1355 Issue Date 99 05 05 X23A G 005 05 Page 12
113. at 2 0 33MHz CLKI 33MHz 520 kHz 0 5 ms 260 kHz 1ms 130 kHz 2ms 65 kHz 4ms 33 kHz 8ms 16 kHz 16 ms 8 kHz 32 ms 4 kHz 64 ms 4 Panel Data Width Selection Panel Data Width Bits Passive LCD Panel Data Width TFT Panel Data Width Size 1 0 Size 00 4 bit 9 bit 8 bit 12 bit 16 bit 16 bit Reserved Reserved 5 Simultaneous Display Option Selection Simultaneous Display Option Select Bits 1 0 Simultaneous Display Mode 00 Normal 11 Line Doubling Interlace Even Scan Only 6 Number of Bits Per Pixel Selection Bit Per Pixel Select Bits 2 0 Color Depth Bit Per Pixel 110 111 Reserved 7 PCLK Divide Selection PCLK Divide Select Bits 1 0 MCLK PCLK Frequency Ratio 8 Suspend Refresh Selection Suspend Refresh Select Bits 1 0 00 1 1 01 2 1 10 3 1 11 4 1 DRAM Refresh Type REG 22h Bits 6 5 00 CAS before RAS CBR Refresh 01 Self Refresh 1x No Refresh Minimum Random Cycle Width tac 00 11 Reserved Reserved 10 RAS to CAS Delay Timing Select REG 22h Bit 4 RAS to CAS Delay trcn 0 2 Page 2 11 RAS Precharge Timing Select REG 22h Bits 3 2 Ne RAS Precharge Width trp 00 2 2 01 15 15 10 1 1 11 Reserved Reserved 12 Ink Cursor Start Address Encoding Ink Cursor Start Address Bits 7 0 Start Address Bytes
114. contain some platform setup code stacks chip selects and jumps into the main entry point of the C code that is contained in the C file entry c For our example the assembler file is STARTSH3 S and it performs only some stack setup and a jump into the code at _mainEntry entry c In the embedded targets printf in file rprintf c putchar putchar c and getch kb c resolve to serial character input output For SH3 much of the detail of handling serial IO is hidden in the monitor of the evaluation board but in general the primitives are fairly straight forward providing the ability to get characters to from the serial port For our target example the nmake makefile is makesh3 mk This makefile calls the Gnu compiler at a specific location TOOLDIR enumerates the list of files that go into the target and builds a a library file as the output of the build process With nmake exe in your path run nmake fmakesh3 mk Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Vancouver Design Center 11 6 2 Building the HAL library for the target example Page 73 Building the HAL for the target example is less complex because the code is written in C and requires little platform specific adjustment The nmake makefile for our example is makesh3 mk This makefile contains the rules for building sh3 objects the files list for the library and the library creation rules The Gnu compiler tools are pointed to b
115. devices The SED1355 architecture is designed to meet the low cost low power requirements of the embedded markets such as Mobile Communications Hand Held PCs and Office Automation The SED1355 supports multiple CPUs all LCD panel types CRT and additionally provides a number of differentiating features Products requiring a Portrait mode display can take advantage of the Hardware Portrait Mode feature Simultaneous Virtual and Split Screen Display are just some of the display modes supported while the Hardware Cursor Ink Layer and the Memory Enhancement Registers offer substantial performance benefits These features combined with the SED1355 s Operating System independence make it an ideal display solution for a wide variety of applications MW FEATURES Memory Interface e 16 bit EDO DRAM or FPM DRAM interface e Memory size options 512K bytes using one 256Kx16 device 2M bytes using one 1Mx16 device e Addressable as a single linear address space CPU Interface e Supports the following interfaces Hitachi SH 4 Hitachi SH 3 Motorola M68K Philips MIPS PR31500 PR31700 Toshiba MIPS TX3912 Motorola Power PC MPC821 NEC MIPS VR4102 VR4111 Epson E0C33 PC Card PCMCIA StrongARM PC Card ISA bus MPU bus interface with programmable READY e CPU write buffer Display Support e 4 8 bit monochrome passive LCD interface e 4 8 16 bit color passive LCD interface Single panel single drive displays e Dual panel du
116. displays are limited to using the four most significant bits from each of the red green and blue portions of each color The result is 4096 24 Ma SEH possible colors When monochrome mode is selected the green component of the LUT is used to determine the gray shade intensity The green indices with only four bits can resolve 16 gray shades In this situation one might as well use four bit per pixel mode and conserve display buffer Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 15 Vancouver Design Center 4 Look Up Table LUT This section is supplemental to the description of the Look Up Table architecture found in the SED1355 Hardware Functional Specification Covered here is a review of the LUT registers recom mendations for the color and gray shade LUT values and additional programming considerations for the LUT Refer to the SED1355 Hardware Functional Specification document number X23A A 001 xx for more detail The SED1355 Look Up Table is used for both the CRT and panel interface and consists of 256 indexed red green blue entries Each entry is 4 bits wide Two registers at offsets 24h and 26h control access to the LUT Color depth affects how many indices will be used for image display In color modes pixel values are used as indices to an RGB value stored in the Look Up Table In monochrome modes only the green component of the LUT is used The value in the display buffer index
117. draw a filled rectangle KA seDelay DevId DWORD 2 Centre the rectangle at 1 4 x y and 3 4 x y EY xl width 4 x2 width 2 x1 yl height 4 y2 height 2 yl seDrawRect Devld xl yl x2 y2 color_red TRU E a Draw a box around the screen K if seDrawLine Devid 0 0 width 1 0 color_blue ERR_OK seDrawLine Devld 0 height 1 width 1 height 1 color_blue ERR_OK seDrawLine Devld 0 0 0 height 1 color_blue ERR_OK seDrawLine Devld width 1 0 width 1 height 1 color_blue ERR_OK printf r nERROR Unable to draw box r n return 1 An Load a cursor with a blue outlined green rectangle seInitCursor Devld seCursoroff Devld seSetCursorColor DevId 0 GREEN16BPP seSetCursorColor Devld 1 BLUE16BPP seDrawCursorRect DeviId 0 0 63 63 1 FALSE seDrawCursorRect Devld 1 1 62 62 0 TRUE seCursoron DevId jx Delay for 2 seconds seDelay DeviId DWORD 2 An Sg Move the cursor Programming Notes and Examples SED1355 Issue Date 99 04 27 X23A G 003 05 Page 76 Epson Research and Development Vancouver Design Center seMoveCursor Devid width 1 63 0 return 0 SED1355 Programming Notes and Examples X23A G 003 05 Issue Date 99 04 27 Epson Research and Development Page 77 Vancouver Design Center 12 Sample Code 12 1 Introduction There are two included e
118. enabled a 16M byte portion of the system PC Card attribute and IO space is allocated to address the SED1355 When the IT8368E senses that the SED1355 is being accessed it does not propagate the PC Card signals to its PC Card device This makes SED1355 accesses transparent to any PC Card device connected to the same slot For mapping details refer to Section 4 3 Memory Mapping and Aliasing on page 13 For further information on configuring the IT8368E refer to the T8368E PC Card GPIO Buffer Chip Specification 5 3 SED1355 Configuration For SED1355 configuration refer to Section 4 2 SED1355 Configuration on page 12 Interfacing to the Toshiba MIPS TX3912 Processor SED1355 Issue Date 99 05 05 X23A G 010 03 Page 16 Epson Research and Development Vancouver Design Center 6 Software Test utilities and Windows CE v2 0 display drivers are available for the SED1355 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 1355CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The SED1355 test utilities and Windows CE v2 0 display drivers are available from your sales support contact or on the internet at http www eea epson com SED1355 Interfacing to the Toshiba MIPS TX39
119. exceed 33 MHz for 60ns EDO DRAM and MCIk cannot exceed 25 MHz for 60ns FPM DRAM If MCIk exceeds the maximum value the MCLK value is set to the source clock divided by two MCIk source clock 2 Otherwise the MCLK value is set to the source clock MCIk source clock 1355CFG shows the MCIk value on the General Page 2 The divide ratio for MCIk PCIk is determined based on Table 14 1 Maximum PCLK Fre quency with EDO DRAM and Table 14 2 Maximum PCLK Frequency with FPM DRAM Once this ratio is determined PCIKk MCIK ratio Note that there are two PCIk divide ra tios based on the three display modes panel CRT and simultaneous display CRT and si multaneous display use the same ratio 1355CFG shows the PCIk values for these three modes on the General Page 3 The HNDP and VNDP values are calculated based on the desired frame rate for each of the three modes panel CRT simultaneous the display s HDP X resolution VDP Y resolution and maximum PCLK as calculated in step 3 F Rites PCLK ramenale HDP HNDP x VDP VNDP 4 Tfitis not possible to reach the desired frame rate within 5 an error message is shown when saving the configuration e When configuring either the CRT or TFT D TFD panel the PCIk must be the same as the required VESA frequency for the given VESA mode The following VESA modes are supported 3 Frame Resolution Rate Hz PCLK MHz Supported DRAM Types 50ns EDO 60ns EDO 640x480 60 25 175 70ns ED
120. host CPU system clock The address inputs AB 20 0 and the data bus DB 15 0 connect directly to the PowerPC bus address A 11 31 and data bus D 0 15 respectively MD4 must be set to select the proper endian mode upon reset M R memory register selects between memory or register access It may be connected to an address line allowing system address A21 to be connected to the M R line Chip Select CS must be driven low whenever the SED1355 is accessed by the PowerPC bus WEO and WE1 connect to TSIZ1 and BI the write enables for the low order and high order bytes They must be driven low when the PowerPC bus is writing data to the SED1355 These signals must be generated by external hardware based on the control outputs from the PowerPC bus RD and RD WR connect to TSIZO and RD WR the read enables for the low order and high order bytes They must be driven low when the PowerPC bus is reading data from the SED 1355 These signals must be generated by external hardware based on the control outputs from the PowerPC bus WAIT connects to TA and is a signal output from the SED1355 that indicates the PowerPC bus must wait until data is ready read cycle or accepted write cycle on the host bus Since the PowerPC bus accesses to the SED1355 may occur asynchronously to the display update it is possible that contention may occur in accessing the SED1355 internal registers and or display buffer The WAIT line resolves these
121. minimum display buffer size is based on the image buffer and the half frame buffer only it does not take into account the hardware cursor ink layer and so it may or may not be sufficient to support it this is noted in the table The hardware cursor requires 1K byte of memory and the 2 bit ink layer requires W x H 4 bytes of memory both must reside at 16K byte boundaries but only one is supported at a time The table shows only one possible sprite ink layer location at the highest possible 16K byte boundary below the half frame buffer which is always at the top SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 139 Vancouver Design Center Table 13 2 Minimum DRAM Size Required for Swivel View Panel Size Panel Type Display Display Her Minimu Se bla inh Cursor yP Mode Buffer Size ___ DRAM Size y Layer Location Buffer Size Size 8 bpp 240KB Color i 16 bpp 480KB Single OKB 496KB 480KB 8 bpp 240KB Mono 165 480KB er 8b 240KB 512KB EE 480KB 464KB Color PE 18 75KB 16 bpp 480KB 480KB Dual 8 bpp 240KB Mono 4 69KB 496KB 480KB 16 bpp 480KB Color 8 bpp 480KB 496KB 16 bpp 960KB 2MB 2032KB 1968KB Single OKB 8 bpp 480KB 512KB 496KB Mone 466 960KB 640 x 480 PP 1KB 75KB 8 bpp 480KB 2MB 2032K 1968K Color 75KB Dual 16 bpp 960KB b 480KB 12KB 496K B
122. ns town Input Clock Pulse Width High 11 3 ns Lou Input Clock Pulse Width Low 11 3 ns t Input Clock Fall Time 10 90 ns t Input Clock Rise Time 10 90 ns Note When CLKI is more than 40MHz REG 19h bit 2 must be set to 1 MCLK CLKI 2 Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 64 Epson Research and Development Vancouver Design Center 7 3 Memory Interface Timing 7 3 1 EDO DRAM Read Write Read Write Timing t1 Memory i Clock t2 Lei RAS 13 t4 ka 5 e t ka t7 gt CAS t8 t9 t10 t11 t10t11 4 a kk MA R dp C1 02 03 XX t12 t13 4 gt bw WES read t14 t15 t16 t17 MD read i EIN d3 t18 ge WE write 120 121 122 MD write di d2 d3 gt Figure 7 14 EDO DRAM Read Write Timing SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Vancouver Design Center Page 65 t3 t4 des G i a t8 la t10 ka MA d R dp Ci de C2 XX C3 Ci v t23 X c2 WX 03 X t12 e t19 WE t14 5 t25 126 MD Read di d2 d3 t20 t21 t22 MD Write di d2 XX d3 Figure 7 15 EDO DRAM Read Write Timing Table 7 15 EDO DRAM Read Write Read Write Timing
123. o o 15 List of Figures Figure 2 1 NEC V832 Read Write Cycles o e a 9 Figure 4 1 NEC V832 to SED1355 Configuration Schematic o o 12 Interfacing to the NEC V832 Microprocessor SED1355 Issue Date 99 05 05 X23A G 012 01 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 Interfacing to the NEC V832 Microprocessor X23A G 012 01 Issue Date 99 05 05 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to provide an interface between the SED1355 Embedded RAMDAC LCD CRT Controller and the NEC V832 microprocessor uPD705102 The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Electronics America Website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs erd epson com Interfacing to the NEC V832 Microprocessor SED1355 Issue Date 99 05 05 X23A G 012 01 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the NEC V832 2 1 The NEC V832 System Bus This section provides an overview of the operation of the CPU bus in orde
124. occurs if the ink layer was used while the cursor was disabled Parameters DevID a registered device ID Return Value ERR OK operation completed with no problems int seCursorOff int DevID Description This routine disables the cursor While disabled the cursor is invisible Parameters DevID aregistered device ID Return Value ERR OK operation completed with no problems int seGetCursorStartAddr int DeviD DWORD Offset Description This function retrieves the offset to the first byte of hardware cursor memory Parameters DevID aregistered device ID Offset a DWORD to hold the return value Return Value ERR OK the operation completed with no problems int seMoveCursor int DeviD long x long y Description Moves the upper left corner of the hardware cursor to the pixel position x y Parameters DevID aregistered device ID x y the x y position in pixels to move the cursor to Return Value ERR OK operation completed with no problems Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Vancouver Design Center Page 65 int seSetCursorColor int DevID int Index DWORD Color Description Parameters Return Value Sets the color of the specified ink cursor index to Color The user definable hardware cursor colors are 16 bit 5 6 5 RGB colors The hardware cursor image is always 2 bpp or four colors Two of the colors are defined to be transparent
125. of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the SED1I355 Hardware Functional Specification document number X23A A 001 xx The following table shows those configuration settings important to the MPC821 host bus interface Table 4 2 Summary of Power On Reset Options SED1355 value on this pin at rising edge of RESET is used to configure 1 0 Pin Name 1 0 MDO 8 bit host bus interface MD 3 1 MD4 Little Endian MD5 Wait signal is active low MD9 Reserved MD11 Alternate Host Bus Interface Selected Primary Host Bus Interface Selected L J required settings for MPC821 support 4 4 Register Memory Mapping The DRAM on the MPC821 ADS board extends from address 0 through 3F FFFFh so the SED1355 is addressed starting at 40 0000h A total of 4M bytes of address space is used where the lower 2M bytes is reserved for the SED1355 on chip registers and the upper 2M bytes is used to access the SED1355 display buffer SED1355 Interfacing to the Motorola MPC821 Microprocessor X23A G 008 03 Issue Date 99 05 05 Epson Research and Development Page 19 Vancouver Design Center 4 5 MPC821 Chip Select Configuration Chip select 4 is used to control the SED1355 The following options are selected in the base address register BR4 e BA 0 16 0000 0000 0100 0000 0 set starting address of SED1355 to 40 0000h e AT 0 2 0
126. operating in big endian mode typically the case for embedded systems Burst Cycles Burst memory cycles are used to fill on chip cache memory and to carry out certain on chip DMA operations They are very similar to normal bus cycles with the following exceptions e Always 32 bit e Always attempt to transfer four 32 bit words sequentially e Always address longword aligned memory i e A30 and A31 are always 0 0 e Do not increment address bits A28 and A29 between successive transfers the addressed device must increment these address bits internally Interfacing to the Motorola MPC821 Microprocessor X23A G 008 03 Issue Date 99 05 05 Epson Research and Development Page 11 Vancouver Design Center If a peripheral is not capable of supporting burst cycles it can assert Burst Inhibit BT simultaneously with TA and the processor will revert to normal bus cycles for the remaining data transfers Burst cycles are mainly intended to facilitate cache line fills from program or data memory They are normally not used for transfers to from IO peripheral devices such as the SED1355 therefore the interfaces described in this document do not attempt to support burst cycles However the example interfaces include circuitry to detect the assertion of BDIP and respond with BI if caching is accidently enabled for the SED1355 address space 2 3 Memory Controller Module 2 3 1 General Purpose Chip Select Module GPCM The General Purpos
127. operation completed with no problems int seGetReg int DeviD int Index BYTE pValue Description Reads the value in the register specified by index Parameters DevID registered device ID Index register index to read pValue return value of the register Return Value ERR_OK operation completed with no problems int seGetWordReg int DevID int Index WORD pValue Description Reads the WORD sized value in the register specified by index Parameters DevID registered device ID Index register index to read pValue return value of the register Return Value ERR_OK operation completed with no problems int seGetDwordReg int DeviD int Index DWORD pValue Description Reads the DWORD sized value in the register specified by index Parameters DevID registered device ID Index register index to read pValue return value of the register Return Value ERR_OK operation completed with no problems Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 57 Vancouver Design Center int seWriteDisplayBytes int DevID DWORD Offset BYTE Value DWORD Count Description This routine writes one or more bytes to the display buffer at the offset specified by Offset If a count greater than one is specified all bytes will have the same value Parameters DevID registered device ID Offset offset from start of the display buffer Value BYTE value to write Count number of b
128. ous SE EERKEHEH aed 09 a en Joquinnuewnoog eg 00060 SSE NAS an ONI LNSWdO7 3430 ANY HOWWESSY NOSd3 op auuoo 097 d vg ZLAIHSdd ast 218 NSO 10d D 3 NV8ida neoan Sl negianez y00z Agut vor S 3NMd3 020 elo Loe DESCH iad au nz LsIHSd4 Aztoa HO ERD K tino Lo HH0VE0I 1 D HOGA 4 nsoG M00 i a A Ello k ke o lt Z 9999999 m Y OO OO 2222222 m oO 000000 als 8 6 eg G2 Jojeiaue6 seig OC Ss E ziro lt st olivadW mn L Jojseuuoo een syonoL ZXE YJ0YJH lo NEE TOS 9IXIHAVEO zy SSA SSA anyo anyo anyo ZE SSA sng 9 9 aaua Ven T yem 69 89 9 Wud 91 x WI aas ger 42 uid DDA ES snq soy Arewud y pios asou Lnperg eg ER MWh K tam Buugeu 0 10 1 0 LO X 1 00 Ezan SVO1 svon au la ASL ASL ASL ASL ASL ASL du E Di E EN Ei bg ozu Ken K st olaw neda Figure 5 2 SDU1355 D9000 Schematic Diagram 2 of 3 Evaluation Board User Manual SDU1355 D9000 X23A G 002 03 Issue Date 98 10 30 Page 21 Epson Research and Development Vancouver Design Center 8 L 9 S y JO Doug SE EERKEHEH aed 09 a y eg um yuaunoeg ER 00060 SSELNOS any ONI INN 3430 ANY HOBV3S38 NOS d3 d AXUS OLV
129. pea che ecm ie hace gs e an US da e ete 22 6 1 Documents lt 4246018 fo Ade OR A a ds Ae wa TAR 6 27 DOCUMeNtSOUICES e kG ee ee Ap ee a eB OE r A bs ea r aA 7 Technical Support 2 sce ee eRe eee o NR 23 7 1 EPSON LCD CRT Controllers SED1355 2 2 2 2 we 23 7 2 Motorola MPC821 Processor 23 Interfacing to the Motorola MPC821 Microprocessor SED1355 Issue Date 99 05 05 X23A G 008 03 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 Interfacing to the Motorola MPC821 Microprocessor X23A G 008 03 Issue Date 99 05 05 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 PowerPC Host Bus Interface Pin Mapping 13 Table 4 1 List of Connections from MPC821ADS to SEDI353 ooo 16 Table 4 2 Summary of Power On Reset Options e 18 List of Figures Figure 2 1 Power PC Memory Read Cycle 9 Figure 2 2 Power PC Memory Write Cycle o o ee 10 Figure 4 1 Typical Implementation of MPC821 to SED1355 Interface 15 Interfacing to the Motorola MPC821 Microprocessor SED1355 Issue Date 99 05 05 X23A G 008 03 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 Interfacing to the Motorola MPC821 Microprocessor X23A G 008 03 Issue Date 99 05 05 Epson Research and Development Page 7 Vancouver Design Center 1 Introdu
130. per pixel value from 16 to 15 bit per pixel 3 Repeat step 2 for the following bit per pixel values 16 15 8 4 2 and 1 4 Press lt ESC gt to exit the program e When using a PC with the SDU1355 evaluation board the PC must not have more than 12M bytes of system memory Program Messages 1355VIRT Display Utility Issue Date 98 10 30 ERROR Did not find a 1355 device The HAL was unable to read the revision code register on the SED1355 Ensure that the SED1355 hardware is installed and that the hardware platform has been set up correctly ERROR Too many devices registered There are too many display devices attached to the HAL The HAL currently supports only one device ERROR Could not register SED1355FOA device A 1355 device was not found at the configured addresses Check the configuration address using the 1355CFG configuration program ERROR Not enough display buffer memory for BPP There was not enough memory for a virtual screen SED1355 X23A B 004 03 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 1355VIRT Display Utility X23A B 004 03 Issue Date 98 10 30 EPSON SED1355 Embedded RAMDAC LCD CRT Controller 1355PLAY Diagnostic Utility Document Number X23A B 005 03 Copyright 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this doc
131. programmed to vertical resolution of the display 2 1 e g EFh for a 480 line display e For all simultaneous display modes this register is programmed to vertical resolution of the CRT 1 e g 1DFh for a 480 line CRT Vertical Non Display Period Register REG OAh RW vertical SE Vertical Non Vertical Non Vertical Non Vertical Non Vertical Non Vertical Non Display A S y f E Period Status n a Display Display Display Display Display Display RO Period Bit 5 Period Bit 4 Period Bit 3 Period Bit 2 Period Bit 1 Period Bit 0 bit 7 bits 5 0 Hardware Functional Specification Vertical Non Display Period Status This is a read only status bit When this bit 1 a vertical non display period is indicated When this bit 0 a vertical display period is indicated Vertical Non Display Period Bits 5 0 These bits specify the vertical non display period Vertical non display period lines Vertical Non Display Period Bits 5 0 1 Note This register must be programmed such that REG OAh gt 1 and REG OAh bits 5 0 1 gt REG OBh 1 REG OCh bits 2 0 1 Issue Date 99 05 18 SED1355 X23A A 001 11 Page 106 Epson Research and Development Vancouver Design Center VRTC FPFRAME Start Position Register REG OBh RW VRTC VRTC VRTC VRTC VRTC VRTC hfa ia FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME Start P
132. register seGetDwordReg Read a Dword value from the specified SED1355 register seWriteDisplayBytes Write one or more bytes to the display buffer at the specified offset seWriteDisplayWords Write one or more words to the display buffer at the specified offset seWriteDisplayDwords Write one or more dwords to the display buffer at the specified offset seReadDisplayByte Read a byte from the display buffer from the specified offset seReadDisplayWord Read a word from the display buffer from the specified offset seReadDisplayDword Read a dword from the display buffer from the specified offset seSetLut Write to the Look Up Table LUT entries starting at index 0 seGetLut Read from the LUT starting at index 0 seSetLutEntry Write one LUT entry red green blue at the specified index seGetLutEntry Read one LUT entry red green blue from the specified index seSetBitsPerPixel Set the color depth seGetBitsPerPixel Determine the current color depth seSetPixel Draw a pixel at x y in the specified color seGetPixel Read pixel s color at x y seDrawLine Draw a line from x1 y1 to x2 y2 in specified color seDrawRect Draw a rectangle from x1 y1 to x2 y2 in specified color seDrawEllipse Draw an ellipse centered at xc yc of radius xr yr in specified color seDrawCircle Draw a circle centered at x y of radius r in specified color selnitCursor Initialize hardware cursor registers
133. register BCUCNTREG3 bit LCD32 ISA32 to 0 Note Setting the register BCUCNTREG3 bit LCD32 ISA32 to 0 affects both the LCD con troller and high speed ISA memory access The frequency of BUSCLK output is programmed from the state of pins TxD CLKSEL2 RTS CLKSEL1 and DTR CLKSELO during reset and from the PMU Power Management Unit configuration registers of the NEC Vr4121 The SED1355 works at any of the frequencies provided by the NEC Vr4121 Interfacing to the NEC VR4121 Microprocessor SED1355 Issue Date 99 05 05 X23A G 011 03 Page 14 Epson Research and Development Vancouver Design Center 4 4 Memory Mapping and Aliasing SED1355 X23A G 011 03 The NEC Vr4121 provides the internal address decoding required by an external LCD controller The physical address range from OA00 0000h to OAFF FFFFh 16M bytes is reserved for use by an external LCD controller e g SED1355 The SED1355 supports up to 2M bytes of display buffer The NEC Vr4121 address line ADD21 connected to M R is used to select between the SED1355 display buffer ADD21 1 and the SED1355 internal registers ADD21 0 NEC Vr4121 address lines ADD 23 22 are ignored thus the SED1355 is aliased four times at 4M byte intervals over the LCD controller address range Address lines ADD 25 24 are set at 10b and never change while the LCD controller is being addressed Interfacing to the NEC VR4121 Microprocessor Issue Date 99 05 05 Epson Research and Developm
134. specify the number Nec of MCLK periods Ty used to create tac Ngc should be chosen to meet pc as well as tras the RAS pulse width Use the following two formulae to calculate Ngc then choose the larger value Note these formulae assume an MCLK duty cycle of 50 5 Ngc Round Up tac Tyy Ngc Round Up tras Tm Nrp if Nrp 10r2 Round Up tras TM 1 55 if Nrp 15 The resulting tac is related to Npc as follows tRC Nec Tm Table 8 12 Minimum Memory Timing Selection REG 22h bits 6 5 Nac dll Pro Cycle 00 5 5 01 4 4 10 3 3 11 Reserved Reserved RAS to CAS Delay Value Npcp This bit selects the DRAM RAS to CAS delay parameter trop This bit specifies the number Necp of MCLK periods Ty used to create tacp Ngcp must be chosen to satisfy the RAS access time trac Note these formulae assume an MCLK duty cycle of 50 5 Nrcp Round Up tr ac 5 Ty 1 if EDO and Npp 1 or 2 2 if EDO and Npp 1 5 Round Up trac Ty 1 if FPM and Npp 1 or 2 Round Up trac Ty 0 45 if FPM and Npp 1 5 Note that for EDO DRAM and Npp 1 5 this bit is automatically forced to O to select 2 MCLK for Necp This is done to satisfy the CAS address setup time Aer The resulting tac is related to Npcp as follows tRCD Neco Tm if EDO and Npp 1 or 2 tRCD 1 5 Tu if EDO and Npp 1 5 RCD Necp 0 5 Tm if FPM and Npp 1 or 2 tRCD Naco Tu if FPM and Npp 1 5 T
135. the following 1355SHOW a The program will display 16 bit per pixel mode Each screen is shown for approximately 1 second then the next screen is automatically shown The program exits after the last screen is shown To exit the program immediately press CTRL BREAK 1355SHOW Demonstration Program Issue Date 98 10 29 Epson Research and Development Page 5 Vancouver Design Center 3 To show a color pattern for a specific bit per pixel mode type the following 1355SHOW b mode where mode 1 2 4 8 15 or 16 The program will display the requested screen and then exit 4 To show the color patterns in portrait mode type the following 1355SHOW p The program will display 16 bit per pixel mode Press any key to go to the next screen The program will next display 15 bit per pixel mode and then 8 bit per pixel mode Since portrait mode is limited to 8 15 and 16 bit per pixel mode the program exits To exit the program im mediately press ESC The p switch can be used in combination with other command line switches 5 To show solid vertical stripes type the following 1355SHOW ie The program will display 16 bit per pixel mode Press any key to go to the next screen The program will display 15 bit per pixel mode Once all screens are shown the program exits To exit the program immediately press ESC The s switch can be used in combination with other command line switches Using 1355SHOW For Testing
136. the Red LUT Accesses to the LUT Data Register automatically increment the pointer For example writing a value 03h into the LUT Address Register sets the pointer to R 3 A subse quent access to the LUT Data Register accesses R 3 and moves the pointer onto G 3 Subsequent accesses to the LUT Data Register move the pointer onto B 3 R 4 G 4 B 4 R 5 etc Note that the RGB data is inserted into the LUT after the Blue data is written i e all three colors must be written before the LUT is updated Look Up Table Data Register REG 26h RW LUT Data LUT Data LUT Data LUT Data Ag wa ia nja Bit 3 Bit 2 Bit 1 Bit O bits 7 4 LUT Data Hardware Functional Specification Issue Date 99 05 18 This register is used to read write the RGB Look Up Tables This register accesses the entry at the pointer controlled by the Look Up Table Address Register REG 24h see above Accesses to the Look Up Table Data Register automatically increment the pointer Note that the RGB data is inserted into the LUT after the Blue data is written i e all three colors must be written before the LUT is updated SED1355 X23A A 001 11 Page 120 Epson Research and Development Vancouver Design Center 8 2 9 Ink Cursor Registers Ink Cursor Control Register REG 27h RW Ink Cursor Ink Cursor Cursor High Cursor High Cursor High Cursor High Mode Mo
137. the height of Screen 1 Height of Screen 1 lines Screen 1 Line Compare Bits 9 0 1 If the height of Screen 1 is less than the display height then the remainder of the display is taken up by Screen 2 For normal operation no split screen this register must be set greater than the Vertical Display Height register e g set to the reset value of 3FFh See Display Configuration for details Screen 1 Display Start Address Register 0 REG 10h RW Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Screen 1 Display Start Address Register 1 REG 11h RW Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Screen 1 Display Start Address Register 2 REG 12h RW ge ds NS E Start Address Start Address Start Address Start Address Bit 19 Bit 18 Bit 17 Bit 16 REG 10h bits 7 0 REG 1 1h bits 7 0 REG 12h bits 3 0 Screen 1 Start Address Bits 19 0 These registers form the 20 bit address for the starting word of the Screen 1 image in the display buffer Note that this is a word address A combination of this register and the Pixel Panning register REG 18h can be used to uniquely identif
138. the logical address of the start of the display buffer This address may be used in programs for direct control over the display buffer device registered device ID pDispLogicalAddr logical address is returned in this variable ERR OK operation completed with no problems 11 5 2 Advanced HAL Functions Advanced HAL functions include the functions to support split and virtual screen operations and are the same features that were described in the section on advanced programming techniques int seSplitinit int DevID DWORD Scrn1 Addr DWORD Scrn2Addr Description Parameters Return Value Note This function prepares the system for split screen operation In order for split screen to function the starting address in the display buffer for the upper portion screen 1 and the lower portion screen 2 must be specified Screen 1 is always displayed above screen 2 on the display regardless of the location of their respective starting addresses DevID registered device ID SernlAddr offset in display buffer in bytes to the start of screen 1 Scrn2Addr offset in display buffer in bytes to the start of screen 2 ERR OK operation completed with no problems It is assumed that the system has been properly initialized prior to calling seSplitInit Programming Notes and Examples Issue Date 99 04 27 SED1355 X23A G 003 05 Page 54 SED1355 X23A G 003 05 Epson Research and Development Vancouver Design Center
139. the off state The LCDPWR On Off polarity is configured by MD10 at the rising edge of RESET MD10 0 configures LCDPWR 0 as the Off state MD10 1 configures LCDPWR 1 as the Off state bits 2 1 Suspend Refresh Select Bits 1 0 These bits specify the type of DRAM refresh to use in Suspend mode Table 8 10 Suspend Refresh Selection Suspend Refresh Select Bits 1 0 DRAM Refresh Type 00 CAS before RAS CBR refresh 01 Self Refresh 1X No Refresh Note These bits should not be changed while suspend mode is active SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 113 Vancouver Design Center bit 0 Software Suspend Mode Enable When this bit 1 software Suspend mode is enabled When this bit 0 software Suspend mode is disabled See Section 15 Power Save Modes for details 8 2 7 Miscellaneous Registers Miscellaneous Register REG 1Bh RW Host Interface n a n a n a n a n a n a Halt Frame Buffer Disable Disable bit 7 Host Interface Disable This bit is set to 1 during power on reset This bit must be programmed to 0 to enable the Host Interface When this bit is high all memory and all registers except REG 1 Ah read only and REG 1Bh are inaccessible bit O Half Frame Buffer Disable This bit is used to disable the Half Frame Buffer When this bit 1 the Half Frame Buffer is disabled When this bit 0 the Half F
140. the rectangle with Color Return Value ERR OK operation completed with no problems int seDrawCursorEllipse int DevID long xc long yc long xr long yr DWORD Color BOOL SolidFill Description Parameters This routine draws an ellipse within the hardware cursor display buffer The ellipse will be centered on the point xc yc and will have a horizontal radius of xr and a vertical radius of yr The value of Color must be 0 to 3 Values 0 and 1 refer to the two user definable colors If Color is 2 then the pixel will be transparent and if the value is 3 the pixel will be an inversion of the underlying screen color Currently seDrawCursorEllipse does not support solid fill of the ellipse DevID aregistered device ID xc yc center of the ellipse in pixels xr horizontal radius in pixels yr vertical radius in pixels Color 0 to 3 value to draw the pixels with SolidFill flag to solid fill the ellipse not currently used Return Value ERR OK operation completed with no problems SED1355 X23A G 003 05 Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 67 Vancouver Design Center 11 5 7 Ink Layer int seDrawCursorCircle int DeviD long x long y long Radius DWORD Color BOOL SolidFill Description This routine draws a circle in hardware cursor display buffer The center of the circle will be at x y and the circle will have a radius of Radius
141. time ms DRAM Refresh Rate time for 256 refresh cycles Tre Use the values in the DRAM specification For the SDU1355 BOx Evaluation Board use the values shown in the Default column The values in the Default column will change based on the Memory Timing Suspend Mode Refresh Type of DRAM refresh used in suspend mode Trp Trac SED1355 1355CFG Configuration Program X23A B 001 02 Issue Date 98 10 30 Epson Research and Development Page 11 Vancouver Design Center Panel Page u gt 1355Cfg 1355test exe El General Memory Panel car Default Single Mono STN i4 bit Polarity Lo Hi Dual Color CIFT pp FPline CS F Disable IT Fomat2 TEL C 16bit FPframe Dimensions 60 EE A DEE Frame Rate Hz Open Save s Exit Figure 3 Panel Page The Panel Page allows the user to select the following settings Panel Page Single Dual Select between a single and dual panel If no panel exists select single A The half frame buffer is used only for dual panels Disabling the Disable Halt kame half frame buffer is not recommended as this will reduce the buffer display quality Select between a monochrome and color panel If no panel Mono Color e exists select color Select color passive LCD panel format 2 See the SED1355 Format 2 Hardware Functional Specification document number X23A A 001 xx for format 1 format
142. to enough memory to hold Count x 3 bytes of data Count the number of LUT elements to read Return Value ERR_OK operation completed with no problems Programming Notes and Examples SED1355 Issue Date 99 04 27 X23A G 003 05 Page 60 SED1355 X23A G 003 05 Epson Research and Development Vancouver Design Center int seSetLutEntry int DeviD int Index BYTE pEntry Description Parameters Return Value This routine writes one LUT entry Unlike seSetLut the LUT entry indicated by Index can be any value from 0 to 255 A Look Up Table entry consists of three bytes one each for Red Green and Blue The color information is stored in the four most significant bits of each byte DevID registered device ID Index index to LUT entry 0 to 255 pEntry pointer to an array of three bytes ERR OK operation completed with no problems int seGetLutEntry int DeviD int index BYTE pEntry Description Parameters Return Value This routine reads one LUT entry from any index DevID registered device ID Index index to LUT entry 0 to 255 pEntry pointer to an array of three bytes ERR OK operation completed with no problems int seSetBitsPerPixel int DevID UINT BitsPerPixel Description Parameter Return Value This routine sets the system color depth Valid arguments for BitsPerPixel is are 1 2 4 8 15 and 16 After performing validity checks for the requested color depth the a
143. use of an embedded RAMDAC allowing simultaneous display of both the CRT and LCD displays In this design the SED1355 has a 3 3V supply voltage for both logic and the embedded RAMDAC For complete details on register functionality and programming refer to the SED1355 Hardware Functional Specification document number X23A A 001 xx and the SED1355 Programming Notes and Examples document number X23A G 003 xx 2 1 1 Display Buffer The SED1355 supports a 512K byte or 2M byte FPM DRAM or EDO DRAM display buffer On the SDU 1355 D9000 evaluation board a 1Mx16 EDO DRAM 2M byte is used to provide memory for all supported display resolutions and when smaller display sizes are used to provide multiple pages of memory SDU1355 D9000 Evaluation Board User Manual X23A G 002 03 Issue Date 98 10 30 Epson Research and Development Page 9 Vancouver Design Center 2 1 2 LCD Display Support The SED1355 provides a wide range of flexibility for display type and resolution Display types include e 4 8 bit monochrome passive e 4 8 16 bit color passive e 9 12 18 bit Active matrix TFT D TFD e other EL REC etc Display resolutions range from 4x1 to 800x600 with color depths from black and white to 64K colors The LCD connector is a 2 x 20 pin 0 100 straight header Pinout assignment is shown in the following table LCD Connector Pinout Evaluation Board User Manual SDU1355 D9000 Issue Date 98 10 30 X23A G 002 03 Pag
144. 0 0000 0000 pRegs 0x15 0x00 0000 0000 Register 16 17 Memory Address Offset this address represents the Kg starting WORD At 8BPP our 640 pixel width is 320 ER WORDS Wi pRegs 0x16 0x40 0100 0000 pRegs 0x17 0x01 0000 0001 Register 18 Pixel Panning Af pRegs 0x18 0x00 0000 0000 JK Register 19 Clock Configuration In this case we must divide EA PCLK by 2 to arrive at the best frequency to set KA our desired panel frame rate Wi pRegs 0x19 0x01 0000 0001 Jk Register 1A Power Save Configuration enable LCD power CBR refresh ER not suspended El pRegs 0x1A 0x00 0000 0000 Jk Register 1C 1D MD Configuration Readback these registers ar Kg read only but it s OK to write a 0 to keep ae the register configuration logic simpler Wi pRegs 0x1C 0x00 0000 0000 pRegs 0x1D 0x00 0000 0000 Register 1E 1F General I O Pins Configuration ate pRegs 0x1E 0x00 0000 0000 pRegs 0x1F 0x00 0000 0000 Programming Notes and Examples SED1355 Issue Date 99 04 27 X23A G 003 05 Page 86 Epson Research and Development Vancouver Design Center Register 20 21 General I O Pins Control El pRegs 0x20 0x00 0000 0000 pRegs 0x21 0x00 0000 0000 Registers 24 26 LUT control RR For this example do a typical 8 BPP LUT setup kk S
145. 0 11 12 13 14 15 16 8 2 5 Clock Configuration Register 8 2 6 Power Save Configuration Registers 8 2 7 Miscellaneous Registers o o 8 2 8 Look Up Table Registers 8 2 9 Ink Cursor Registers o Display Buffer 9 1 Image Buffer 9 2 Ink Cursor Buffers 9 3 Half Frame Buffer Display Configuration 10 1 10 2 Look Up Table Architecture 11 1 11 2 Ink Cursor Architecture 12 1 12 2 12 3 SwivelView 13 1 13 2 13 3 13 4 Clocking 14 1 14 2 14 3 Power Save Modes Mechanical Data Display Mode Data Format Image Manipulation Monochrome Modes Color Modes Ink Cursor Buffers Ink Cursor Data Format Ink Cursor Image Manipulation 12 31 InkImage 22256 Gah bee be Bee AE A e 12 3 2 Cursor Image Concept GENEE Image Manipulation in SwivelView Physical Memory Requirement Limitations Maximum MCLK PCLK Ratios Frame Rate Calculation Bandwidth Calculation Hardware Functional Specification Issue Date 99 05 18 Page 5 SED1355 X23A A 001 11 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Vancouver Design Center Table 5 1 Table 5 2 Table 5 2 Table 5 3 Table 5 4 Table 5 5 Table 5 6 Table 5 7 Table 5 8 Table 6 1 Table 6 2 Table 6 3 T
146. 0 0x00 OxFO 0x90 0x00 OxFO 0x80 0x00 OxFO 0x70 0x00 OxFO 0x60 0x00 OxFO 0x50 0x00 OxFO 0x40 0x00 OxFO 0x30 0x00 0xF0 0x20 0x00 OxFO 0x10 0x00 0xF0 0x00 0x00 Red to magenta blue and red OxFO 0x00 0x00 OxFO 0x00 0x10 OxFO 0x00 0x20 OxFO 0x00 0x30 OxFO 0x00 0x40 OxFO 0x00 0x50 OxFO 0x00 0x60 OxFO 0x00 0x70 OxFO 0x00 0x80 OxFO 0x00 0x90 OxFO 0x00 0xA0 OxFO 0x00 OxBO OxFO 0x00 OxC0O OxFO 0x00 OxDO OxFO 0x00 OxEO OxFO 0x00 OxFO Magenta blue and red to blue OxFO 0x00 OxFO OxEO 0x00 OxFO OxDO 0x00 OxFO OxCO 0x00 OxFO OxBO 0x00 OxFO OxA0 0x00 OxFO 0x90 0x00 OxFO 0x80 0x00 OxFO 0x70 0x00 OxFO 0x60 0x00 OxFO 0x50 0x00 OxFO 0x40 0x00 OxFO 0x30 0x00 OxFO 0x20 0x00 OxFO 0x10 0x00 0xF0 0x00 0x00 OxFO Black to magenta blue and red 0x00 0x00 0x00 0x10 0x00 0x10 0x20 0x00 0x20 0x30 0x00 0x30 0x40 0x00 0x40 0x50 0x00 0x50 0x60 0x00 0x60 0x70 0x00 0x70 0x80 0x00 0x80 0x90 0x00 0x90 0xA0 0x00 0xA0 0xB0 0x00 OxBO Programming Notes and Examples SED1355 Issue Date 99 04 27 X23A G 003 05 Page 82 OxCO 0x00 0xC0 0xD0 0x00 OxDO OxEO 0x00 OxEO Black to cyan blue and green 0x00 0x00 0x00 0x00 0x10 0x10 0x00 0x20 0x20 0x00 0x40 0x40 0x00 0x50 0x50 0x00 0x60 0x60 0x00 0x80 0x80 0x00 0
147. 0 30 Epson Research and Development Page 3 Vancouver Design Center Table of Contents T TINTOAUCHON lt a a A EA E Met EN EN Mee a aa 7 2 Features 200 ia EE 8 2 1 SED1355 Embedded RAMDAC LCD CRT Controller 2 2 2 8 ZELT Display Buffer cis be ea da e EE a a da ES E E g 8 2 1 2 CD Display Support EE EEN A ENN 9 21 3 Touchscreen Support s s4 peage o a Re 11 ZLA lA eak eie eos ah a ie A EE eb O Eh E E 11 2 1 5 JumperSelectiOn ra 4c nu ii e E e A 11 2 1 6 Adjustable LCD BIAS Power Supp 11 3 D9000 Specifies miar sera ess dined o Bice ee E e Bx 13 3 1 InterfaceSignals e 13 3 1 1 Connector Pinout for Channel A6 and A7 2 ee 13 3 1 2 Memory Address CS M R Decoding e 17 3 2 FPGACode Functionality e 17 33 Board Dimensions 0 0 00 eee 17 Parts DISE Aere ti Sar ae raat sete ag Tee fay See ga ag a A Se ted er cal PAS ier er tate oh et 18 Schematic Diagrams noia a ee ee a Sa ae 19 Component Placement mm 22 Evaluation Board User Manual SDU1355 D9000 Issue Date 98 10 30 X23A G 002 03 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SDU1355 D9000 Evaluation Board User Manual X23A G 002 03 Issue Date 98 10 30 Epson Research and Development Table 2 1 Table 2 2 Table 2 3 Table 3 1 Table 3 2 Figure 5 1 Figure 5 2 Figure 5 3 Vancouver Design Center List of Tables LCD Conn
148. 00 116 RAS to CAS Delay Timing Select 116 RAS Precharge Timing Select e 117 Optimal NRC NRP and NRCD values at maximum MCLK frequency 117 Minimum Memory Timing Selection e 118 Ink Cursor Selection 0 05 4 oad Ge Daweh ee Ve Ba Pee re ba e Bw 120 Ink Cursor Start Address Encoding 000000000022 eee eee 122 Recommended Alternate FRM Scheme 00000000000 00 122 SED1355 Addressing lt p o oee 534 48 So h we eR we ee eG 123 Ink Cursor Start Address Encoding 134 Ink Eursor Color elect cb a a A ee ee Oe Ie Bw t 135 Minimum DRAM Size Required for SwivelVieW o o 139 Maximum PCLK Frequency with EDO DRAM 140 Maximum PCLK Frequency with FPM DRAM 141 Example Frame Rates with Ink Disabled o o e eee e 142 Number of MCLKs required for various memory ACCESS 144 Total MCLKs taken for Display refresh 145 Theoretical Maximum Bandwidth M byte sec Cursor Ink disabled 146 Power Save Mode Function Summary soaa 148 Pin States in Power save Modes a 148 Hardware Functional Specification Issue Date 99 05 18 Epson Research and Development Vancouver Design Center Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Figure 3 9 Figure 3 10 Figure 5 1 Figure 5 3 Figure 7 1 Figure 7 2 Figure 7 3 Figure 7 4 Figure 7
149. 00 uses a portion of the PC Card Attribute and IO space to access the SED1355 The SED1355 responds to both PC Card Attribute and IO bus accesses thus freeing the programmer from having to set the PR31500 PR31700 Memory Configuration Register 3 bit CARDIIOEN or CARD2IOEN if slot 2 is used As a result the PR31500 PR31700 sees the SED1355 on its PC Card slot as described in the table below Table 4 2 PR31500 PR31700 to PC Card Slots Address Remapping for Direct Connection SED1355 Uses PC Card Slot Philips Address Size Function 0800 0000h 16M byte Card 1 IO or Attribute SED1355 registers 0900 0000h 8M byte aliased 4 times at 2M byte intervals 1 SED1355 display buffer 0980 0000h 8M byte aliased 4 times at 2M byte intervals 0A00 0000h 32M byte Card 1 10 or Attribute 6400 0000h 64M byte Card 1 Memory 0C00 0000h 16M byte Card 2 IO or Attribute SED1355 registers 0D00 0000h 8M byte l l aliased 4 times at 2M byte intervals 2 SED1355 display buffer 0D80 0000h 8M byte l i aliased 4 times at 2M byte intervals 0E00 0000h 32M byte Card 2 IO or Attribute 6800 0000h 64M byte Card 2 Memory Interfacing to the Philips MIPS PR31500 PR31700 Processor Issue Date 99 05 05 SED1355 X23A G 001 06 Page 12 Epson Research and Development Vancouver Design Center 5 System Design Using the IT8368E PC Card Buffer In a system design using one or two ITE IT8368E PC Card and multiple function
150. 00h to registers 10h 11h and 12h 3 Calculate the size of the screen 1 image so we know where the screen 2 image is located This calculation must be performed on the virtual size offset register of the display Since a virtual size was not specified assume the virtual size to be the same as the physical size offset pixels_per_line pixels_per_word 640 16 40 words per line screenl_size offset lines 40 480 19 200 words 4B00h words 4 Set the screen 2 start address to the value we just calculated Write the screen 2 start address registers 15h 14h and 13h with the values 00h 4Bh and 00h respectively Programming Notes and Examples X23A G 003 05 Issue Date 99 04 27 Epson Research and Development Page 31 Vancouver Design Center 6 LCD Power Sequencing and Power Save Modes 6 1 Introduction to LCD Power Sequencing LCD Power Sequencing allows the LCD power supply to discharge prior to shutting down the LCD signals Power sequencing is required to prevent long term damage to the panel and to avoid unsightly lines on power down and power up The SED1355 performs automatic power sequencing when the LCD is enabled or disabled through the LCD Enable bit in register ODh For most applications the internal power sequencing is the appropriate choice There may be situations where the internal time delay is insufficient to discharge the LCD power supply before the LCD signals are shut down T
151. 0111 Microprocessors The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Electronics America Website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs erd epson com Interfacing to the NEC VR4102 VR4111 Microprocessors SED1355 Issue Date 99 05 05 X23A G 007 05 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the VR4102 VR4111 2 1 The NEC VR4102 VR4111 System Bus 2 1 1 Overview SED1355 X23A G 007 05 The VR Series family of microprocessors features a high speed synchronous system bus typical of modern microprocessors Designed with external LCD controller support and Windows CE based embedded consumer applications in mind the VR4102 VR4111 offers a highly integrated solution for portable systems This section provides an overview of the operation of the CPU bus in order to establish interface requirements The NEC VR4102 VR4111 is designed around the RISC architecture developed by MIPS This microprocessor is based on the 66MHz VR4100 CPU core which supports 64 bit processing The CPU communicates with the Bus Control Unit BCU using its internal SysAD bus The BCU in turn communicates with external devices usi
152. 03 0011 04 0100 Ge 0101 0110 bj 07 0111 4 bit Red Data 08 1000 09 1001 DA 1010 0B 1011 DC 1100 0D 1101 OE 1110 OF 1111 e e ED FE FF Green Look Up Table 256x4 00 0000 01 0001 02 0010 03 0011 04 0100 de 0101 0110 bi 07 0111 4 bit Green Data R 08 1000 09 1001 DA 1010 0B 1011 DC 1100 0D 1101 OE 1110 OF 1111 FC FD FE FF Blue Look Up Table 256x4 00 0000 01 0001 02 0010 03 0011 04 0100 Ge 0101 0110 bi 07 0111 4 bit Blue Data z 08 1000 09 1001 DA 1010 0B 1011 DC 1100 DD 1101 0E 1110 OF 1111 FC FD e FE FF 4 bit per pixel data from Image Buffer Figure 11 6 4 Bit per pixel Color Mode Data Output Path SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 133 Vancouver Design Center 8 Bit per pixel Color Mode Red Look Up Table 256x4 00 i 0000 0000 01 i 0000 0001 02 i 0000 0010 03 0000 0011 04 0000 0100 05 0000 0101 06 00000110 07 0000 0111 i 4 bit Red Data F8 1111 1000 F9 1111 1001 FA 1111 1010 FB 1111 1011 FC 1111 1100 FD 1111 1101 FE 11111110 FF 1111 1111 00 0000 0000 01 0000 0001 02 0000 0010 03 0000 0011 04 0000 0100 05 0000 0101 0
153. 05 Page 10 Epson Research and Development Vancouver Design Center 3 SED1355 Host Bus Interface The SED1355 directly supports multiple processors The SED1355 implements a 16 bit MIPS ISA Host Bus Interface which is most suitable for direct connection to the VR4102 VR4111 microprocessor The MIPS ISA host bus interface is selected by the SED1355 on the rising edge of RESET After releasing reset the bus interface signals assume their selected configuration For details on SED1355 configuration see Section 4 2 SED1355 Hardware Configu ration on page 13 Note At reset the Host Interface Disable bit in the Miscellaneous Disable Register REG 1Bh bit 7 is set to 1 This means that only REG 1 Ah read only and REG 1Bh are accessible until a write to REG 1Bh sets bit 7 to 0 making all regis ters accessible When debugging a new hardware design this can sometimes give the appearance that the interface is not working so it is important to remember to clear this bit before proceeding with debugging 3 1 Host Bus Interface Pin Mapping SED1355 X23A G 007 05 The following table shows the functions of each host bus interface signal Table 3 1 Host Bus Interface Pin Mapping SED1355 Pin Name NEC VR4102 VR4111 Pin Name AB20 ADD20 AB 19 0 ADD 19 0 DB 15 0 DAT 15 0 WE1 SHB M R ADD21 CS LCDCS BUSCLK BUSCLK BS Connected to Von RD WR Connected to Von RD RD WE0
154. 0ns Simultaneous CRT Dual Sg 1 2 4 8 jo 32 247 E EDO DRAM Monochrome Color Panel with Half 7 15 16 56 242 E Frame Buffer Disabled 1 2 4 8 32 243 MCIk 40MHz 480x320 Npc 4 15 16 56 232 Nap 1 5 SN 1 2 4 8 32 471 x Neco 2 15 16 56 441 z e Dual Color with Half Frame Buffer 23 1 2 4 8 20 32 80 Enabled SE A ET 13 3 32 53 e Dual Mono with Half Frame Buffer 1 2 4 8 E 32 123 Enabled i 640x480 15 16 13 3 32 82 SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Vancouver Design Center Table 14 3 Example Frame Rates with Ink Disabled Continued Page 143 Maximum Maximum Frame Minimum 1 D SE Zeg Display Resolution sor Weer Panel Rate Hz 4 e Single Panel 300x6002 1 2 4 8 32 66 55 e CRT S 15 168 56 65 55 e Dual Mono Color Panel with Half Frame Buffer Disabled 640x480 d E 101 ye e Simultaneous CRT Single Panel 15 16 56 98 78 e Si 1 2 4 8 32 203 60ns OS CRT Dual 640x240 33 EDO DRAM ono Color Panel with Half Frame 15 16 56 200 Buffer Disabled 1 2 4 8 32 200 MCIk 383MHz 480x320 Bac 15 16 56 196 Npp 1 5 300x040 1 2 4 8 32 388 a x Naco 2 15 16 56 380 8 e Dual Color with Half Frame Buffer 300x60023 1 2 4 8 16 5 32 66 X bs SE 15 168 11 32 43 Dual Mono with Half Frame Buffer
155. 1 Page 102 Epson Research and Development Vancouver Design Center 8 2 3 Panel Monitor Configuration Registers Panel Type Register REG 02h RW EL Panel E Panel Data Panel Data Panel Data Color Mono Dual Single ae GE Enable Width Bit 1 Width Bit O Format Select Panel Select Panel Select Select bit 7 EL Panel Mode Enable When this bit 1 EL Panel support mode is enabled Every 262143 frames approximately 1 hour at 60Hz frame rate the identical panel data is sent to two consecutive frames i e the frame rate modulation circuitry is frozen for one frame bits 5 4 Panel Data Width Bits 1 0 These bits select the LCD interface data width as shown in the following table Table 8 3 Panel Data Width Selection Panel Data Width Bits 1 0 Passive LCD Panel Data TFT D TFD Panel Data Width Width Size Size 00 4 bit 9 bit 01 8 bit 12 bit 10 16 bit 16 bit 11 Reserved Reserved bit 3 Panel Data Format Select When this bit 1 color passive LCD panel data format 2 is selected When this bit 0 passive LCD panel data format 1 is selected bit 2 Color Mono Panel Select When this bit 1 color passive LCD panel is selected When this bit 0 monochrome passive LCD panel is selected bit 1 Dual Single Panel Select When this bit 1 dual passive LCD panel is selected When this bit 0 single passive LCD panel is selected bit 0 TFT Passive LCD Panel Select When this bit
156. 1 TFT D TFD panel is selected When this bit 0 passive LCD panel is selected MOD Rate Register REG 03h RW as Got MOD Hate MOD Hate MOD Rate MOD Rate MOD Rate MOD Rate Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 bits 5 0 MOD Rate Bits 5 0 When the DRDY pin is configured as MOD this register controls the toggle rate of the MOD out put When this register is zero the MOD output signal toggles every FPFRAME When this register is non zero its value represents the number of FPLINE pulses between toggles of the MOD output signal SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 103 Vancouver Design Center Horizontal Display Width Register REG 04h RW Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal n a Display Width Display Width Display Width Display Width Display Width Display Width Display Width Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 bits 6 0 Horizontal Display Width Bits 6 0 These bits specify the LCD panel and or the CRT horizontal display width as follows Contents of this Register Horizontal Display Width 8 1 For passive LCD panels the Horizontal Display Width must be divisible by 16 and for TFT LCD panels CRTs the Horizontal Display Width must be divisible by 8 The maximum horizontal dis play width is 1024 pixels Note This register mus
157. 1 2 4 8 165 32 103 Enabled 640x480 15 16 11 32 68 e Single Panel 800x6002 1 2 4 8 32 50 x e CRT 15 168 56 48 S e Dual Mono Color Panel with Half Frame Buffer Disabled 640x480 ene ee a 60 e Simultaneous CRT Single Panel 15 16 56 75 60 Simultaneous CRT Dual 1 2 4 8 32 142 gt Mono Color Panel with Half Frame 640x240 15 16 25 56 136 S 60n Buffer Disabled S 1 2 4 8 32 152 FPM DRAM 480x320 15 16 56 145 MCIk 25MHz 1 2 4 8 32 294 Npc 4 320x240 N 4 5 15 16 56 280 Naco 2 Dual Mono with Half Frame Buffer 800x600 1 2 4 8 15 16 12 5 32 50 SE 640x480 1 2 4 8 15 16 125 32 77 640x400 1 2 4 8 15 16 12 5 32 92 e Dual Color with Half Frame Buffer g00xe0023 1 2 4 8 12 5 32 50 X 3 Bane 15 16 8 33 32 33 1 2 4 8 12 5 32 77 640x480 15 16 8 33 32 51 1 Must set Ngc 4MCLK See REG 22h Performance Enhancement Register 2 800x600 16 bpp requires 2M bytes of display buffer for all display types 3 800x600 8 bpp on a dual color panel requires 2M bytes of display buffer if the half frame buffer is enabled Hardware Functional Specification Issue Date 99 05 18 SED1355 X23A A 001 11 Page 144 Epson Research and Development Vancouver Design Center 4 Optimum frame rates for panels range from 60Hz to 150Hz If the maximum refresh rate is too high for a panel MCLK should be reduced or PCLK should be divided down 5 Half Frame Buffer disabled by RE
158. 11 Hi Z e For the MIPS ISA Bus this pin inputs system address bit 20 Note that for the ISA Bus the unlatched LA20 must first be latched before input to AB20 e For Philips PR31500 31700 Bus this pin inputs the address latch enable ALE e For Toshiba TX3912 Bus this pin inputs the address latch enable ALE e For PowerPC Bus this pin inputs the system address bit 11 A11 e For all other busses this pin inputs the system address bit 20 A20 See Host Bus Interface Pin Mapping for summary See the respective AC Timing diagram for detailed functionality SED1355 X23A A 001 11 Hardware Functional Specification Issue Date 99 05 18 Epson Research and Development Vancouver Design Center Page 25 Table 5 1 Host Interface Pin Descriptions Continued Pin Name Type Pin Cell RESET State Description DB 15 0 16 31 C TS2 Hi Z These pins are the system data bus For 8 bit bus modes unused data pins should be tied to Vpp e For SH 3 SH 4 Bus these pins are connected to D 15 0 e For MC68K Bus 1 these pins are connected to D 15 0 e For MC68K Bus 2 these pins are connected to D 31 16 for 32 bit devices e g MC68030 or D 15 0 for 16 bit devices e g MC68340 For Generic Bus these pins are connected to D 15 0 e For MIPS ISA Bus these pins are connected to SD 15 0 e For Philips PR31500 31700 Bus these pins are connected to D 31 16
159. 12 Processor X23A G 010 03 Issue Date 99 05 05 Epson Research and Development Page 17 Vancouver Design Center 7 References 7 1 Documents e Toshiba America Electrical Components Inc TX3905 12 Specification Epson Research and Development Inc SED1355 Hardware Functional Specification Document Number X23A A 001 xx e Epson Research and Development Inc SDUI3553B0C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X23 A G 004 xx e Epson Research and Development Inc SED1355 Programming Notes and Examples Document Number X23A G 003 xx 7 2 Document Sources e Toshiba America Electrical Components Website http www toshiba com taec e Epson Electronics America Website http www eea epson com Interfacing to the Toshiba MIPS TX3912 Processor SED1355 Issue Date 99 05 05 X23A G 010 03 Page 18 8 Technical Support 8 1 EPSON LCD CRT Controllers SED1355 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http www epson co jp Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai
160. 16 3 R9 R10 R11 150 1 150 1 17 2 R12 R13 39 39 Ohms 18 1 R15 470K 470K 19 1 R16 200K Pot 200K potentiometer 20 4 R18 R19 R20 R27 10K 10K 21 1 R21 1 5K 1 1 5K 1 22 1 R22 1K 1 1K 1 23 1 R23 140 1 140 Ohms 1 24 1 TS1 Header Header 3x2 1 25 1 U1 SED1355F0A SED1355F0A 26 1 U2 DRAM1MX16 SOJ 3 3V eg EE Micon 27 1 U4 RD 0412 RD 0412 Xentek 28 1 U5 33 333MHz 33 333MHz 8 DIP Oscillator SDU1355 D9000 X23A G 002 03 Evaluation Board User Manual Issue Date 98 10 30 Page 19 SDU1355 D9000 X23A G 002 03 pa 9 S D E L E EZ MENGES EPUON ad a sequny uawnoog es o006a sseinas zi 091 EN ID eza zza ONI INSWdOT 3430 ONY HOUWSSSY NOSd3 LAS ALAN w D0NY iu ano 16 vosssela3s HOLO3NNO Z Sd 9 081 9 ost Tor 334 lata a d EI Ae A Ze ey ESSAZOVA Let t a ix ISSAZOVA L oY Ve sor OHA SSSA forr anro anro anro 96 E zo Dal EIN SSSA VA Zor essa LE man L zor ama essa Los A 4 r SA issa L sor M3389 a D er DEI CC e zaan ova EO anyo anto anyo anyo anvo anro S L y 4 aay raaa ova OL ovo 669 Es 99 so vo AMAS mr ee el 900 Let
161. 2 11 6 2 Building the HAL library for the target example e 73 11 6 3 Building a complete application for the target example o o 73 12 Sample Gode si ma e a ii a ee ee SE 77 12 1 Introduction 77 12 1 1 Sample code using the SED1355 HAL AR 77 12 1 2 Sample code without using the SED1355 HAL Ab 80 121 3 Header Files e 2 24 one eg Bed bh eee eee ba eee beth eu 4 90 Appendix A Supported Panel Values 02 000 eee eee 101 SED1355 X23A G 003 05 Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Vancouver Design Center Table 2 1 Table 4 1 Table 4 2 Table 4 3 Table 4 4 Table 4 5 Table 4 6 Table 4 7 Table 4 8 Table 5 1 Table 5 2 Table 7 1 Table 7 2 Table 11 1 Table 12 1 Table 12 2 Table 12 3 Table 12 4 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 5 1 Figure 5 2 Figure 5 3 Figure 5 4 Figure 5 5 Figure 5 6 Figure 5 7 Figure 11 1 Page 5 List of Tables SED1355 Initialization Sequence 2 a 8 Look Up Table Configurations 2 0 2 0 0 0 e 16 Recommended LUT Values for 1 Bpp Color Mode 17 Example LUT Values for 2 Bop Color Mode o o e 17 Suggested LUT Values to Simulate VGA Default 16 Color Palette 18 Suggested LUT Values to Simulate VGA Default 256 Color Palette 19 Recommended LUT Values for 1 Bpp Gray Sha
162. 2 MCLK 3 Half F Buffer Enable SE 3 MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 3 e Dual Color with Half Frame Buffer Enabled 5 MCLK 3 MCLK 3 MCLK 3 MCLK 3 MCLK 4 Simultaneous CRT Dual Color Panel with Half 4 MCLK 2 MCLK 2 MCLK 2 MCLK 3 MCLK 3 Frame Buffer Enable 3 MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 3 Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 142 Epson Research and Development Vancouver Design Center 14 2 Frame Rate Calculation The frame rate is calculated using the following formula PCLK max Framek ate _ _ HDP HNDP x VDP VNDP Where VDP Vertical Display Period REG 09h bits 1 0 REG O8h bits 7 0 1 VNDP Vertical Non Display Period REG OAh bits 5 0 1 in table below HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period REG O5h bits 4 0 1 8Ts given in table below Ts Pixel Clock PCLK Table 14 3 Example Frame Rates with Ink Disabled Maximum Minimum Maximum Frame 1 t Zeg Display Resolution ear one Panel AA Hz 4 MHz HNDP Ts Panel CRT e Single Panel ements 1 2 4 8 32 80 60 x e CRT 15 168 56 78 60 e Dual Monochrome Color Panel with Half Frame Buffer Disabled 640x480 de Se E 2 e Simultaneous CRT Single Panel 15 16 56 119 85 5
163. 2 6 13 6 14 Table of Contents Features ISA Bus Support Non ISA Bus Support DRAM Support Decode Logic D Clock Input Support Monochrome LCD Panel Support Color Passive LCD Panel Support Color TFT D TFD LCD Panel Support CRT Support Power Save Modes E E Adjustable LCD Panel Negative Power Supply Adjustable LCD Panel Positive Power Supply CPU Bus Interface Header Strips Schematic Notes SDU1355BO0C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 98 10 30 Page 3 SED1355 X23A G 004 04 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 SDU1355B0C Rev 1 0 ISA Bus Evaluation Board User Manual X23A G 004 04 Issue Date 98 10 30 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 2 1 Configuration DIP Switch Settings ee 8 Table 2 2 Host Bus Selection meai ece e was ci a e a a ed a EE dt 8 Table 2237 Jumper Setting S atre A A A AE A SR A NEE er A 8 Table 3 1 LCD Signal Connector J6 ee 9 Table 4 1 CPU BUS Connector H1 Pinout ee 10 Table 4 2 CPU BUS Connector H2 Pinout a 11 Table 5 1 CPU Interface Pin Mapping 12 List of Figures Figure 1 SED1355BOC Schematic Diagram 1 of 4 0 cee eee ae 19 Figure 2 SED1355BOC Schematic Diagram 2 of 20 Figure 3 SED1355BOC Schematic Diagram 3 of 21 Figure 4 SED1355BOC Schematic Diagram of 22 SDU1355B0C
164. 21 Microprocessor X23A G 011 03 Issue Date 99 05 05 Epson Research and Development Vancouver Design Center 7 Technical Support 7 1 Epson LCD CRT Controllers SED1355 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http www epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 7 2 NEC Electronics Inc VR4121 NEC Electronics Inc U S A Corporate Headquarters 2880 Scott Blvd Santa Clara CA 95050 8062 USA Tel 800 366 9782 Fax 800 729 9288 http www nec com http www vrseries com Interfacing to the NEC VR4121 Microprocessor Issue Date 99 05 05 Page 17 Taiwan R O C Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 SED1355 X23A G 011 03 Page 18 Epson Research and Development Vanc
165. 260 uA liz Input Leakage Current 1 1 uA loz Output Leakage Current 1 1 uA VDD min lot 1 8mA Type Vou High Level Output Voltage 3 5mA Type Vop 0 3 V 5mA Type3 VDD min lot 1 8mA Type1 VoL Low Level Output Voltage 3 5mA Type2 0 3 V 5mA Type3 Vin High Level Input Voltage CMOS level Vpp max 2 0 Vit Low Level Input Voltage CMOS level Vpp min 0 8 f CMOS Schmitt Vi High Level Input Voltage Vpp 3 0V 2 3 V CMOS Schmitt Vr Low Level Input Voltage Vpp 3 0V 0 5 V i CMOS Schmitt Vu Hysteresis Voltage Vpp 3 0V 0 1 V Rpp Pull Down Resistance Vi Vpp 100 200 400 kQ Ci Input Pin Capacitance 12 pF Co Output Pin Capacitance 12 pF Cio Bi Directional Pin Capacitance 12 pF SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 41 Vancouver Design Center 7 A C Characteristics Conditions Vpp 3 0V 10 and Vpp 5 0V 10 Ta 40 C to 85 C Trise and Te for all inputs must be lt 5 nsec 10 90 Cy 50pF CPU Interface unless noted C 100pF LCD Panel Interface C 10pF Display Buffer Interface Ci 10pF CRT Interface 7 1 CPU Interface Timing 7 1 1 SH 4 Interface Timing t1 t2 t3 Empe CKIO t4 t5 A 20 0 M R RD WR t6 t7 BS ye t8 t12 kees CSn t9 t10 e WEn RD t11 t12 gt es
166. 28 VEEH 30 Adjustable 24 14V negative LCD bias LCDVCC 32 Jumper selectable 3 3V 5V 12V 34 12V VDDH 36 Adjustable 15 38V positive LCD bias DRDY 38 DRDY MOD FPSHIFT2 MOD LCDPWR 40 LCDPWR SDU1355B0C Rev 1 0 ISA Bus Evaluation Board User Manual SED1355 Issue Date 98 10 30 X23A G 004 04 Page 10 4 CPU Bus Interface Connector Pinouts SED1355 X23A G 004 04 Table 4 1 CPU BUS Connector H1 Pinout Epson Research and Development Vancouver Design Center Connector manita Pin No 1 Connected to DBO of the SED1355 2 Connected to DB1 of the SED1355 3 Connected to DB2 of the SED1355 4 Connected to DB3 of the SED1355 5 Ground 6 Ground 7 Connected to DB4 of the SED1355 8 Connected to DB5 of the SED1355 9 Connected to DB6 of the SED1355 10 Connected to DB7 of the SED1355 11 Ground 12 Ground 13 Connected to DB8 of the SED1355 14 Connected to DB9 of the SED1355 15 Connected to DB10 of the SED1355 16 Connected to DB11 of the SED1355 17 Ground 18 Ground 19 Connected to DB12 of the SED1355 20 Connected to DB13 of the SED1355 21 Connected to DB14 of the SED1355 22 Connected to DB15 of the SED1355 23 Connected to RESET of the SED1355 24 Ground 25 Ground 26 Ground 27 12 volt supply 28 12 volt supply 29 Connected to WEO of the SED1355 30 Connected to WAIT of the SED1355 31 Connected to CS of the SED1355 32 Conne
167. 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Interfacing to the NEC V832 Microprocessor Issue Date 99 05 05
168. 31500 PR31700 processor The SED1355 can be successfully interfaced using one of the following configurations e Direct connection to the PR31500 PR31700 see Section 4 Direct Connection to the Philips PR31500 PR31700 on page 9 e System design using the ITE IT8368E PC Card GPIO buffer chip see Section 5 System Design Using the IT8368E PC Card Buffer on page 12 Interfacing to the Philips MIPS PR31500 PR31700 Processor Issue Date 99 05 05 Epson Research and Development Vancouver Design Center 3 SED1355 Host Bus Interface Page 7 The SED1355 implements a 16 bit host bus interface specifically for interfacing to the PR31500 PR31700 microprocessor The PR31500 PR31700 host bus interface is selected by the SED1355 on the rising edge of RESET After releasing reset the bus interface signals assume their selected configuration For details on SED1355 configuration see Section 4 2 SEDI355 Config uration on page 10 Note At reset the Host Interface Disable bit in the Miscellaneous Disable Register REG 1Bh bit 7 is set to 1 This means that only REG 1Ah read only and REG 1Bh are accessible until a write to REG 1Bh sets bit 7 to 0 making all regis ters accessible When debugging a new hardware design this can sometimes give the appearance that the interface is not working so it is important to remember to clear this bit before proceeding with debugging 3 1 PR31500 PR31700 Host Bus In
169. 55 ISA evaluation cards only Programming Notes and Examples SED1355 Issue Date 99 04 27 X23A G 003 05 Page 52 SED1355 X23A G 003 05 Epson Research and Development Vancouver Design Center int seGetHostBusWidth int DevID int Width Description Parameters This function retrieves the default as set by 1355CFG EXE value for the host bus interface width and returns it in Width DevID registered device ID Width integer to hold the returned value of the host bus width Return Value ERR OK the function completed successfully int seDisplayEnable int DevID BYTE State Description Parameters This routine turns the display on or off by enabling or disabling the ENABLE bit of the display device PANEL CRT or SIMULTANEOUS The Display Mode setting LCD CRT or SIMULTANEOUS determines which device s will be affected the default mode is stored in the HAL_STRUCT DevID registered device ID State set to ON or OFF to respectively enable or disable the display Return Value ERR OK the function completed successfully int seDisplayFifo int DevID BYTE State Description Parameters This routine turns the display on or off by enabling or disabling the display FIFO the hardware cursor and ink layer are not affected To quickly blank the display use seDisplayFifo instead of seDisplayEnable Enabling and disabling the display FIFO is much faster allowing full CPU bandwidth to the display bu
170. 6 0000 0110 07 0000 0111 4 bit Green Data F8 1111 1000 F9 1111 1001 FA 1111 1010 FB 1111 1011 EC 1111 1100 FD 1111 1101 FE 1111 1110 FF 1111 1111 00 0000 0000 01 0000 0001 02 0000 0010 03 0000 0011 04 0000 0100 05 0000 0101 06 0000 0110 07 0000 0111 4 bit Blue Data F8 1111 1000 F9 1111 1001 FA 1111 1010 FB 1111 1011 EC 1111 1100 FD 1111 1101 FE 11111110 FF 1111 1111 8 bit per pixel data from Image Buffer Figure 11 7 8 Bit per pixel Color Mode Data Output Path 15 16 Bit per pixel Color Modes The LUT is bypassed and the color data is directly mapped for this color mode See Display Configuration on page 125 Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 134 Epson Research and Development Vancouver Design Center 12 Ink Cursor Architecture 12 1 Ink Cursor Buffers The Ink Cursor buffers contain formatted image data for the Ink Layer or Hardware Cursor There may be several Ink Cursor images stored in the display buffer but only one may be active at any given time The active Ink Cursor buffer is selected by the Ink Cursor Start Address register REG 30h This register defines the start address for the active Ink Cursor buffer The Ink Cursor buffer must be positioned where it does not co
171. 6 5 5 5 5 5 5 5 55 3 25 11 5 5 5 5 5 5 5 5 5 5 e Simultaneous CRT Dual Monochrome Panel with Half Frame Buffer Enable 33 5 24 4 49 i e Dual Color Panel with Half Frame Buffer 16 5 5 5 5 5 5 5 5 17 enabled 11 55 55 55 55 185 SED1355 X23A A 001 11 Hardware Functional Specification Issue Date 99 05 18 Epson Research and Development Vancouver Design Center Table 14 6 Theoretical Maximum Bandwidth M byte sec Cursor Ink disabled Continued Page 147 DRAM Type Max Pixel Maximum Bandwidth M byte sec 640x480 Display Clock Speed Grade MHz 1 bpp 2bpp 4bpp 8bpp 16 bpp e CRT e Simultaneous CRT Single Panel Simultaneous CRT Dual 25 4 16 4 16 4 16 3 97 1 11 Monochrome Color Panel with Half Frame Buffer Disabled e Single Panel 25 4 16 4 16 4 16 3 92 0 26 e Dual Monochrome Color Panel with Half 60ns Frame Buffer Disabled 12 5 416 416 416 416 4 16 FPM DRAM MCLK 25MHz EE with Half Frame Buffer 25 3 92 3 19 S Nene 12 5 416 416 416 416 2 46 8 3 4 16 4 16 4 16 4 16 4 16 e Simultaneous CRT Dual Monochrome Panel with Half Frame Buffer Enable 25 3 97 3 40 i R 8 e Dual Color Panel with Half Frame Buffer 12 5 4 16 4 16 4 16 3 92 SES 8 33 416 416 416 416 4 16 Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 148 Epson Research and Development Vancouver Design Center
172. 63 1 FALSI seMoveCursor Device 101 101 exit 0 E x Programming Notes and Examples SED1355 Issue Date 99 04 27 X23A G 003 05 Page 80 Epson Research and Development Vancouver Design Center 12 1 2 Sample code without using the SED1355 HAL API kk kk Wi kk S Ka 0x00 0x00 0x00 0x10 0x10 0x10 0x20 0x20 0x20 0x40 0x40 0x40 0x50 0x50 0x50 0x60 0x60 0x60 0x80 0x80 0x80 0x90 0x90 0x90 0xA0 0xA0 0xA0 OxC0 OxC0O OxCO OxDO OxDO OxDO OxEO OxEO OXxEO INIT1355 C sample code demonstrating the initialization of the SED1355 Beta release 2 0 98 10 29 The code in this example will perform initialization to the following specification 640 x 480 dual 16 bit color passive panel 75 Hz frame rate 8 BPP 256 colors 33 MHz input clock 2 MB of 60 ns EDO memory This is sample code only This means 1 Generic C is used I assume that pointers can access the relevant memory addresses this is not always the case i e using the 1355B0B card on an x86 16 bit platform will require changes to use a DOS extender to access memory and registers 2 Register setup is done with discrete writes rather than being table driven This allows for clearer commenting A real program would probably store the register settings in an array and loop through the array writing each element to a control register 3 The pointer assignment
173. 64 http www epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 7 2 PC Card Standard PCMCIA North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 Personal Computer Memory Card International Association 2635 North First Street Suite 209 San Jose CA 95134 USA Tel 408 433 2273 Fax 408 433 9558 http www pc card com Interfacing to the PC Card Bus Issue Date 99 05 05 Page 19 Taiwan R O C Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 SED1355 X23A G 005 05 Page 20 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 Interfacing to the PC Card Bus X23A G 005 05 Issue Date 99 05 05 EPSON SED1355 Embedded RAMDAC LCD CRT Controller Interfacing to the NEC VR4102 VR4111 Microprocessors Document Number X23A G 007 05 Copyright 1998 1999 Epson Research and Development Inc All Rights Reserved Informatio
174. 8 1 loadcepc B 9600 C 1 D 2 c wince release nk bin d Confirm that NK BIN is located in c wince release e Reboot the system from the hard drive SED1355 Windows CE Display Drivers X23A E 001 04 Issue Date 98 10 30 Epson Research and Development Page 9 Vancouver Design Center Comments Windows CE Display Drivers Issue Date 98 10 30 Some of the D9000 systems may not be able to provide enough current for your LCD panel to operate properly If this is the case an external power supply should be connected to the panel The Seiko Epson Common Interface FPGA code assumes the display buffer starts at 0x 12200000 and IO starts at 0x 12000000 If the display buffer or IO location is modified the corresponding entries in the file SED1355 H have to be changed SED1355 H is located in X wince platform odo drivers display SED 1355 where X is the drive letter The driver is CPU independent but will require another ODO RBF file to support other CPUs when running on the Hitachi D9000 or ETMA ODO platform Please check with Seiko Epson for the latest supported CPU ODO files As the time of this printing the drivers have been tested on the SH 3 and x86 CPUs and have only been run with version 2 0 of the ETK We are constantly updating the drivers so please check our website at www erd epson com or contact your Seiko Epson or Epson Electronics America sales representative SED1355 X23A E 001 04 Page 10 Epson Research and
175. A 30 20 40 0B 50 FO FO 4B 70 FO DO 8B 70 60 30 CB 30 20 40 DC FO 50 50 4C 70 FO FO 8C 70 70 30 CC A0 20 40 oD FO 50 FO 4D 70 DO FO 8D 60 70 30 CD 40 20 30 0E FO FO 50 4E 70 BO FO 8E 50 70 30 CE 40 20 30 OF FO FO FO 4F 70 90 FO 8F 40 70 30 CF 40 20 20 10 00 00 00 50 BO BO FO 90 30 70 30 DO 40 20 20 11 10 10 10 51 Co BO FO 91 30 70 40 D1 40 20 20 12 20 20 20 52 DO BO FO 92 30 70 50 D2 40 30 20 13 20 20 20 53 EO BO FO 93 30 70 60 D3 40 30 20 14 30 30 30 54 FO BO FO 94 30 70 70 D4 40 40 20 15 40 40 40 55 FO BO EO 95 30 60 70 D5 30 40 20 16 50 50 50 56 FO BO DO 96 30 50 70 D6 30 40 20 17 60 60 60 57 FO BO Co 97 30 40 70 D7 20 40 20 18 70 70 70 58 FO BO BO 98 50 50 70 D8 20 40 20 19 80 80 80 59 FO CO BO 99 50 50 70 D9 20 40 20 1A 90 90 90 5A FO DO BO 9A 60 50 70 DA 20 40 30 1B AO AO AO 5B FO EO BO 9B 60 50 70 DB 20 40 30 1C BO BO BO 5C FO FO BO 9C 70 50 70 DC 20 40 40 1D co co co 5D EO FO BO 9D 70 50 60 DD 20 30 40 1E EO EO EO 5E DO FO BO 9E 70 50 60 DE 20 30 40 1F FO FO FO 5F CO FO BO 9F 70 50 50 DF 20 20 40 Programming Notes and Examples SED1355 Issue Date 99 04 27 X23A G 003 05 Page 20 Epson Research and Development Vancouver Design Center Table 4 5 Suggested LUT Values to Simulate VGA Default 256 Color Palette Continued Index R G B Index R G B Index R G B Index R G B 20 00 00 FO 60 BO FO BO AO 70 50 50 EO 20 20 40 21 40 00 FO 61 BO FO CO A1 70 50 50 El 30 20 40 22 70 00 FO 62 BO FO DO A2 70 60 50 E2 30 20 40 23 BO 00 FO 63 B
176. A bik ke ho at aie ae ate ae olde ela dolla et ds Bea eS 8 24 2 Access Cycles sas et yee BE Pa Roe a AA 9 3 SED1355 Host Bus Interface es 10 3 1 Host Bus Interface Pin Mapping 2 2 2 10 3 2 Host Bus Interface Signal Descriptions 2 2 11 4 V832 to SED1355 Interface EE 12 4 1 Hardware Description 2 ee ee LA 4 2 SED1355 Hardware Configuration 13 4 3 NEC V832 Configuration e 14 4 4 Memory Mapping and Aliasing 15 SoftWare ts he dida ey een Gr A es le rear Aes ade ee de da ye 16 ReTerentes sata aa AAA A a AAA 17 6 Documents E a a A A A a ts dl D DocumentSources som al a A tt a A 7 Techhical Support i a cai ore EEN a A ET er e 18 7 1 Epson LCD CRT Controllers SED1355 e 18 7 2 NEC Electronics Inc V832 e 18 Interfacing to the NEC V832 Microprocessor SED1355 Issue Date 99 05 05 X23A G 012 01 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 Interfacing to the NEC V832 Microprocessor X23A G 012 01 Issue Date 99 05 05 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping e 10 Table 4 1 Summary of Power On Reset Oppons 000 2 eee 13 Table 4 2 NEC V832 Wait States vs Bus Clock Frequency o o o 14 Table 4 3 NEC V832 IO Address Range For Each CSn Line
177. AS Lee ee Ree be E A 55 Clock Input Requirement sos ia rs PB ER Se eee 57 A AA E e ere tee ent 58 Clock Input Reqlitemente is ia A A A id 60 Power PC Timing EE A a ee ARAS 61 Clock Input Requirement 63 EDO DRAM Read Write Timing ooa 64 EDO DRAM Read Write Timing 0 2 0 0 0000000000 65 EDO DRAM CAS Before RAS Refresh Timing 67 EDO DRAM Self Refresh Timing 69 FPM DRAM Read Write Timing oaaae 70 FPM DRAM Read Write Timing ee 71 FPM DRAM CAS Before RAS Refresh Timing 73 FPM DRAM Self Refresh Timing 0 2 0 00000 0000008 74 LCD Panel Power Off Power On Timing Drawn with LCDPWR set to active high polarity 75 Power Save Status and Local Bus Memory Access Relative to Power Save Mode 76 4 Bit Single Monochrome Passive LCD Panel Timing 77 4 Bit Single Monochrome Passive LCD Panel A C Timing 78 8 Bit Single Monochrome Passive LCD Panel Timing 79 8 Bit Single Monochrome Passive LCD Panel A C Timing o 80 4 Bit Single Color Passive LCD Panel Timing 81 4 Bit Single Color Passive LCD Panel A C Timing 82 SED1355 X23A A 001 11 Page 10 Epson Research and Development Vancouver Design Center Figure 7 30 8 Bit Single Color Passive LCD Panel Timing Format 1 o 83 Figure 7 31 8 Bit Single Color Passive LCD Panel A C Timing Format l 84 Figure
178. AT1 D1 LD1 D1 D1 D1 LD1 LD1 R1 R2 R4 FPDAT2 D2 LD2 D2 D2 D2 LD2 LD2 RO R1 R3 FPDAT3 D3 LD3 D3 D3 D3 LD3 LD3 G2 G3 G5 FPDAT4 D4 UDO DO D4 D4 D4 UDO UDO G1 G2 G4 FPDAT5 D5 UD1 D1 D5 D5 D5 UD1 UD1 GO G1 G3 FPDAT6 D6 UD2 D2 D6 D6 D6 UD2 UD2 B2 B3 B5 FPDAT7 D7 UD3 D3 D7 D7 D7 UD3 UD3 B1 B2 B4 FPDAT8 D8 LD4 BO B1 B3 FPDAT9 D9 LD5 RO R2 FPDAT10 D10 LD6 R1 FPDAT11 D11 LD7 GO G2 FPDAT12 D12 UD4 G1 FPDAT13 D13 UD5 GO FPDAT14 D14 UD6 BO B2 FPDAT15 D15 UD7 Bi Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 36 Epson Research and Development Vancouver Design Center 5 5 CRT Interface The following figure shows the external circuitry for the CRT interface DAC Von 3 3V LN OR DAC Vpp 2 7V to 5 5V ZA 1 5kQ 1 1pF 4 6 mA 4 6 mA IREF 4 6 mA m 2N2222 V R LM334 1400 1kQ 1 1 Yo EC DAC Vss DAC Veg 290 200 gt 1 WE 1N457 1 R A DAC Vss DAC Ven G t To CRT B 150Q 1500 1500 1 1 1 DAC Vss DAC Ven DAC Vss Figure 5 3 External Circuitry for CRT Interface SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 37 Vancouver Design Center 6 D C Characteristics Table 6 1 Absolute Maximum Ratings Symbol Parameter Rating Units Vop Supply Voltage Vss 0 3 to 6 0 V DAC Vpp Supply Voltage Vss 0 3 to 6 0 V Vin Input Voltage Vss 0 3 to Vpp 0 5
179. AnERROR Could not register SED1355 device exit 1 Identify that this is indeed an SED1355 E seGetId Device amp ChipId if ID_SED1355F0A Chipld printf nERROR Did not detect SED1355 exit 1 Initialize the SED1355 This step will actually program the registers with values taken from the default register table in appcfg h SI if ERR OK seSetInit Device printf nERROR Could not initialize device exit 1 The default initialization clears the display Draw a 100x100 red rectangle in the upper left corner 0 0 of the display seDrawRect Device 0 0 100 100 1 TRUE Init the HW cursor The HAL performs several calculations to determine the best location to place the cursor image and will use that location from here on The background must be set to transparent seInitCursor Device seDrawCursorRect Device 0 0 63 63 2 TRU Gl SED1355 Programming Notes and Examples X23A G 003 05 Issue Date 99 04 27 Epson Research and Development Page 79 Vancouver Design Center Set the first user definable color to black and the second user definable color to white yd seSetCursorColor Device 0 0 seSetCursorColor Device 1 OXFFFFFFFF Jx Draw a hollow rectangle around the cursor and move the cursor to 101 101 SI seDrawCursorRect Device 0 0 63
180. B 5 0 e g REG OOh is mapped to AB 5 0 000000 REG 01h is mapped to AB 5 0 000001 See the table below Table 8 1 SED1355 Addressing CS M R Access Register access 0 0 REG 00h is addressed when AB 5 0 0 e REG 01h is addressed when AB 5 0 1 e REG n is addressed when AB 5 0 n 0 4 Memory access the 2M byte Display Buffer is addressed by AB 20 0 1 X SED1355 not selected 8 2 Register Descriptions Unless specified otherwise all register bits are reset to O during power on Reserved bits should be written 0 when programming unless otherwise noted 8 2 1 Revision Code Register Revision Code Register REG 00h RO Product Code Product Code Product Code Product Code Product Code Product Code Revision Revision Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Code Bit 1 Code Bit 0 bits 7 2 Product Code Bits 5 0 This is a read only register that indicates the product code of the chip The product code for the SED 1355 is 000011 bits 1 0 Revision Code Bits 1 0 This is a read only register that indicates the revision code of the chip The revision code for the SED 1355FO0A is 00 SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Vancouver Design Center 8 2 2 Memory Configuration Registers Page 101 Memory Configuration Register
181. B10 A22 P6 D28 AB9 A23 P6 A28 AB8 A24 P6 C27 AB7 A25 P6 A26 AB6 A26 P6 C26 AB5 A27 P6 A25 AB4 A28 P6 D26 AB3 A29 P6 B25 AB2 A30 P6 B19 AB1 A31 P6 D17 ABO DO P12 A9 DB15 D1 P12 C9 DB14 D2 P12 D9 DB13 D3 P12 A8 DB12 D4 P12 B8 DB11 D5 P12 D8 DB10 D6 P12 B7 DB9 D7 P12 C7 DB8 SED1355 X23A G 008 03 Interfacing to the Motorola MPC821 Microprocessor Issue Date 99 05 05 Epson Research and Development Page 17 Vancouver Design Center Table 4 1 List of Connections from MPC821ADS to SED1355 Continued MPC821 Signal Name MPC821ADS Connector and Pin Name SED1355 Signal Name D8 P12 A15 DB7 D9 P12 C15 DB6 D10 P12 D15 DB5 D11 P12 A14 DB4 D12 P12 B14 DB3 D13 P12 D14 DB2 D14 P12 B13 D I D15 P12 C13 DBO SRESET P9 D15 RESET SYSCLK P9 C2 BUSCLK CS4 P6 D13 CS TS P6 B7 BS TA P6 B6 WAIT R W P6 D8 RD WR TSIZO P6 B18 RD TSIZ1 P6 C18 WE0 Bl P6 B9 WE1 P12 A1 P12 B1 P12 A2 P12 B2 Gnd P12 A3 P12 B3 P12 A4 P12 B4 Vss P12 A5 P12 B5 P12 A6 P12 B6 P12 A7 Note Note that the bit numbering of the Power PC bus signals is reversed e g the most significant address bit is AO the next is Al A2 etc Interfacing to the Motorola MPC821 Microprocessor SED1355 Issue Date 99 05 05 X23A G 008 03 Page 18 Epson Research and Development Vancouver Design Center 4 3 SED1355 Hardware Configuration The SED1355 latches MD15 through MDO to allow selection
182. CRT to panel Unused entries Programming Notes and Examples SED1355 Issue Date 99 04 27 X23A G 003 05 Page 22 SED1355 X23A G 003 05 Epson Research and Development Vancouver Design Center 4 bpp gray shade The 4 bpp gray shade mode uses the first 16 LUT elements The remaining indices of the LUT are unused Table 4 8 Suggested LUT Values for 4 Bpp Gray Shade Index Red Green Blue 00 00 01 10 02 20 03 30 04 40 05 50 06 60 07 70 08 80 09 90 0A AO 0B BO OC CO oD DO 0E EO OF FO 10 00 00 TT WM Required to match CRT to panel Unused entries S bpp gray shade eaea When 8 bpp gray shade mode is selected the gray shade intensity is determined by the green LUT value The green portion of the LUT has 16 possible intensities There is no color advantage to selecting 8 bpp mode over 4 bpp mode however hardware rotate can be only used in 8 and 16 bpp modes 15 bpp gray shade The Look Up Table is bypassed at this color depth hence programming the LUT is not necessary As with 8 bpp there are limitations to the colors which can be displayed In this mode the four most significant bits of green are used to set the absolute intensity of the image Four bits of green resolves to 16 colors Now however each pixel requires two bytes 16 bpp gray The Look Up Table is bypassed at this color depth hence programming the LUT is not necessary As with 8 bpp there are limitations to the colors which can be
183. Color Cursor Color Cursor Color Cursor Color Cursor Color Cursor Color O Bit 15 0 Bit 14 0 Bit 13 0 Bit 12 O Bit 11 O Bit 10 0 Bit 9 0 Bit 8 REG 2C bits 7 0 Ink Cursor Color 0 Bits 15 0 REG 2D bits 7 0 These bits define the 5 6 5 RGB Ink Cursor color 0 REG 2Eh Ink Cursor Color 1 Register 0 RW Cursor Color 1 Bit 7 Cursor Color 1 Bit6 Cursor Color 1 Bit5 Cursor Color 1 Bit 4 Cursor Color 1 Bit 3 Cursor Color 1 Bit 2 Cursor Color 1 Bit 1 Cursor Color 1 Bito Ink Cursor Color 1 Register 1 REG 2Fh RW Cursor Color Cursor Color Cursor Color Cursor Color Cursor Color Cursor Color Cursor Color Cursor Color 1 Bit 15 1 Bit 14 1 Bit 13 1 Bit 12 1 Bit 11 1 Bit 10 1 Bit 9 1 Bits REG 2E bits 7 0 REG 2F bits 7 0 Ink Cursor Color 1 Bits 15 0 These bits define the 5 6 5 RGB Ink Cursor color 1 Hardware Functional Specification Issue Date 99 05 18 SED1355 X23A A 001 11 Page 122 Epson Research and Development Vancouver Design Center Ink Cursor Start Address Select Register REG 30h RW Ink Cursor Ink Cursor Ink Cursor Ink Cursor Ink Cursor Ink Cursor Ink Cursor Ink Cursor Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Select Select Select Select Select Select Select Select Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit
184. D where B number of MCLKs left available for CPU access after every 16 pixels drawn f MCLK f PCLK 16 Total MCLK for Display refresh units in MCLKs 16 pixels where C number of MCLKs required to service 1 CPU access 2 bytes of data 4 units in MCLKs 2 bytes where D time to draw 16 pixels 16 f PCLK units in 16 pixels The minimum function limits the bandwidth to the bandwidth available during non display period should the display fetches constitute a small percentage of the overall memory activity For 16 bpp single panel CRT dual panel with half frame buffer disable the number of MCLKs required to fetch 16 pixels when PCLK MCLK exceeds 16 In this case the display fetch does not allow any CPU access during the display period CPU access can only be achieved during non display periods All displays have a horizontal non display period and a vertical non display period The formula for calculating the percentage of non display period is as follows Percentage of non display period HTOT VTOT WIDTH HEIGHT HTOT VTOT Percentage of non display period for CRT 800 525 640 480 800 525 26 6 Percentage of non display period for single panel 680 482 640 480 680 482 6 2 Percentage of non display period for dual panel 680 242 640 240 680 242 6 6 Average Bandwidth Percentage of non display period Bandwidth during non display period 1 Percentage of non display period Bandwidth du
185. DAC LCD CRT Controller Interfacing to the Philips MIPS PR31500 PR31700 Processor Document Number X23A G 001 06 Copyright O 1998 1999 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 0 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 Interfacing to the Philips MIPS PR31500 PR31700 Processor X23A G 001 06 Issue Date 99 05 05 Epson Research and Development Page 1 Vancouver Design Center Table of Contents 1 INTOdUCHON 02 ot e A A A Ed S 5 Interfacing to the PR31500 PR31700 6 SED1355 Host Bus Interface 7 3 1 PR31500 PR31700 Host Bus Interface Pin Mapping 2 2 2 2 2 2 0 7 3 2 PR31500 PR31700 Host Bus Interface Signals 4 Direct Connection to the Philips PR31500 PR31700 9 4 1 Hardware
186. Description H 4 2 SED1335 Configuration JO 4 3 Memory Mapping and Aliasing 211 5 System Design Using the IT8368E PC Card Buffer 12 5 1 Hardware Description 1 5 2 IT8368E Configuration e 18 5 3 SED1355 Configuration ss o te aau ta o a ee 13 AT EENEG 14 References 4 do o A A ee BE a a a 15 Wel Documents ra eS Be e a ir ie e te LO Ta Document Sources ci ce ae Ges ear e a ee e a ee a at ee aa TD 8 Technical Support viccio bona ara ada a se 16 8 1 EPSON LCD CRT Controllers SED1355 16 8 2 Philips MIPS PR31500 PR31700 Processor 2 Ip Sc ITETISSOSE 86 4 sg 24 da ob tr Hoh ao Oh Bowe das cae ts LO Interfacing to the Philips MIPS PR31500 PR31700 Processor SED1355 Issue Date 99 05 05 X23A G 001 06 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 Interfacing to the Philips MIPS PR31500 PR31700 Processor X23A G 001 06 Issue Date 99 05 05 Epson Research and Development Page 3 Vancouver Design Center List of Tables Table 3 1 PR31500 PR31700 Host Bus Interface Pin Mapping 7 Table 4 1 SED1355 Configuration for Direct Connection s sooo 10 Table 4 2 PR31500 PR31700 to PC Card Slots Address Remapping for Direct Connection 11 List of Figures Figure 4 1 Typical Implementation of Direct Connection o o e 9 Figure 5 1 IT8368E Implementa
187. Design Using the IT8368E PC Card Buffer In a system design using one or two ITE IT8368E PC Card and multiple function IO buffers the SED1355 can be interfaced so as to share one of the PC Card slots 5 1 Hardware Description The IT8368E can be programmed to allocate the same portion of the PC Card Attribute and IO space to the SED1355 as in the direct connection implementation described in Section 4 Direct Connection to the Toshiba TX3912 on page 11 Following is a block diagram showing an implementation using the IT8368E PC Card buffer Kee SED1355 IT8368E PC Card Device IT8368E PC Card Device Figure 5 1 ITS368E Implementation Block Diagram SED1355 X23A G 010 03 Interfacing to the Toshiba MIPS TX3912 Processor Issue Date 99 05 05 Epson Research and Development Page 15 Vancouver Design Center 5 2 IT8368E Configuration The ITE IT8368E has been specifically designed to support EPSON LCD CRT controllers Older EPSON Controllers not supporting a direct interface to the Toshiba processor can utilize the IT8368E MFIO pins to provide the necessary control signals however when using the SED1355 this is not necessary as the Direct Connection described in Section 4 Direct Connection to the Toshiba TX3912 on page 11 can be used The IT8368E must have both Fix Attribute IO and VGA modes enabled When both these modes are
188. Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 Windows6 CE Display Drivers X23A E 001 04 Issue Date 98 10 30 EPSON SED1355 Embedded RAMDAC LCD CRT Controller SDU1355BOC Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X23A G 004 04 Copyright O 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 SDU1355B0C Rev 1 0 ISA Bus Evaluation Board User Manual X23A G 004 04 Issue Date 98 10 30 Epson Research and Development Vancouver Design Center oa DON 7 Parts List 8 Schematic Diagrams Introduction 1 1 Installation and Configuration LCD Interface Pin Mapping CPU Bus Interface Connector Pinouts Host Bus Interface Pin Mapping Technical Description 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 6 10 6 11 6 1
189. Development Page 67 Vancouver Design Center 7 3 2 EDO DRAM CAS Before RAS Refresh Timing ti Memory i y Clock t2 t3 RAS H t5 t6 CAS Figure 7 16 EDO DRAM CAS Before RAS Refresh Timing Table 7 16 EDO DRAM CAS Before RAS Refresh Timing Symbol Parameter Min Max Units ti Internal memory clock period 25 ns RAS precharge time REG 22h bits 3 2 00 2t1 3 ns t2 RAS precharge time REG 22h bits 3 2 01 1 45t1 3 ns RAS precharge time REG 22h bits 3 2 10 1t1 3 ns RAS pulse width REG 22h bit 6 5 00 and bits 3 2 31 3 He 00 Seng pulse width REG 22h bit 6 5 00 and bits 3 2 3 4511 3 ge Get pulse width REG 22h bit 6 5 00 and bits 3 2 4t1 3 ae RAS pulse width REG 22h bit 6 5 01 and bits 3 2 24 3 is 00 13 pulse width REG 22h bit 6 5 01 and bits 3 2 2 4511 3 nS cae pulse width REG 22h bit 6 5 01 and bits 3 2 3t1 3 Ge RAS pulse width REG 22h bit 6 5 10 and bits 3 2 1 3 ns 00 ipa pulse width REG 22h bit 6 5 10 and bits 3 2 1 45 t1 3 d Geng pulse width REG 22h bit 6 5 10 and bits 3 2 2t1 3 ae H CAS pulse width t2 ns E CAS setup time REG 22h bits 3 2 00 or 10 0 45 t1 3 ns t CAS setup time REG 22h bits 3 2 01 1t1 3 ns Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 68 Epson Research and Development Vancouver Design Center Table 7 16 EDO DRAM CAS Before RAS Refresh Timing Symbol
190. Disable Register REG 1Bh bit 7 is set to 1 This means that only REG 1Ah read only and REG 1Bh are accessible until a write to REG 1Bh sets bit 7 to 0 making all regis ters accessible When debugging a new hardware design this can sometimes give the appearance that the interface is not working so it is important to remember to clear this bit before proceeding with debugging 3 1 TX3912 Host Bus Interface Pin Mapping The following table shows the function of each host bus interface signal Table 3 1 TX3912 Host Bus Interface Pin Mapping SED Ise Toshiba TX3912 Pin Names AB20 ALE AB19 CARDREG AB18 CARDIORD AB17 CARDIOWR AB 16 13 Vop AB 12 0 A 12 0 DB 15 8 D 23 16 DB 7 0 D 31 24 WE1 CARDxCSH M R Vop BUSCLK DCLKOUT RD WR CARDxCSL RD RD WEO0 WE WAIT CARDxWAIT RESET PON Interfacing to the Toshiba MIPS TX3912 Processor Issue Date 99 05 05 SED1355 X23A G 010 03 Page 10 Epson Research and Development Vancouver Design Center 3 2 TX3912 Host Bus Interface Signals When the SED1355 is configured to operate with the TX3912 the host interface requires the following signals SED1355 X23A G 010 03 BUSCLK is a clock input required by the SED1355 host bus interface It is separate from the input clock CLKI and should be driven by the TX3912 bus clock output DCLKOUT Address input AB20 corresponds to the TX3912 signal AL
191. Drivers Issue Date 98 10 30 Epson Research and Development Page 7 Vancouver Design Center Windows CE Display Drivers Issue Date 98 10 30 10 11 12 13 IF CEPC_DDI_VGA8BPP ddi dll _FLATRELEASEDIR ddi_vga8 dll NK SH ENDIF IF CEPC_DDI_VGA2BPP IF CEPC_DDI_VGA8BPP ddi dll _FLATRELEASEDIR ddi_s364 dll NK SH ENDIF ENDIF with this line ddi dll FLATRELEASEDIR 1SED1355 d11 NK SH Edit the file MODE H located in X wince platform odo drivers display SED 1355 to set the desired screen resolution color depth bpp and panel type The sample code defaults to a 640x480 color dual passive 16 bit LCD panel To support one of the other listed panels change the define statement Edit the file PLATFORM REG to set the same screen resolution and color depth bpp as in MODE H PLATFORM REG is located in X wince platform cepc files The display driver section of PLATFORM REG should be Default for EPSON Display Driver 640x480 at 8bits pixel Useful Hex Values 1024 0x400 768 0x300 640 0x280 480 0x1E0 320 140 240 0xF0 HKEY_LOCAL_MACHINE Drivers Display SED1355 CxScreen dword 280 CyScreen dword 1E0 Bpp dword 8 Generate the proper building environment by double clicking on the sample project icon i e X86 DEMO7 Type BLDDEMO lt ENTER gt at the DOS prompt of the X86 DEMO7 window to gener
192. E address latch enable whose falling edge indicates that the most significant bits of the address are present on the multiplexed address bus AB 12 0 Address input AB19 should be connected to the TX3912 signal CARDREG This signal is active when either IO or configuration space of the TX3912 PC Card slot is being accessed Address input AB18 should be connected to the TX3912 signal CARDIORD Either AB18 or the RD input must be asserted for a read operation to take place Address input AB17 should be connected to the TX3912 signal CARDIOWR Either AB17 or the WEO input must be asserted for a write operation to take place Address inputs AB 16 13 and control inputs M R CS and BS must be tied to Vpp as they are not used in this interface mode Address inputs AB 12 0 and the data bus DB 15 0 connect directly to the TX3912 address and data bus respectively MD4 must be set to select the proper endian mode on reset see Section 4 2 SEDI355 Configuration on page 12 Because of the TX3912 data bus naming convention and endian mode SED1355 DB 15 8 must be connected to TX3912 D 23 16 and SED1355 DB 7 0 must be connected to TX3912 D 31 24 Control inputs WE1 and RD WR should be connected to the TX3912 signals CARDxCSH and CARDxCSL respectively for byte steering Input RD should be connected to the TX3912 signal RD Either RD or the AB18 input CARDIORD must be asserted for a read operation to take place In
193. E pulse trailing edge note 2 t2 FPFRAME hold from FPLINE pulse trailing edge 14 Ts note 1 D FPLINE pulse width 9 Ts t4 FPLINE period note 3 t5 MOD delay from FPLINE pulse trailing edge note 4 t6 FPSHIFT falling edge to FPLINE pulse leading edge note 5 t7 FPLINE pulse trailing edge to FPSHIFT falling edge t10 t11 Ts t8 FPSHIFT period 8 Ts t9 FPSHIFT falling edge to FPLINE pulse trailing edge note 6 t10 FPLINE pulse trailing edge to FPSHIFT rising edge 20 Ts t11 FPSHIFT pulse width high 4 Ts t12 FPSHIFT pulse width low 4 Ts t13 UD 3 0 LD 3 0 setup to FPSHIFT falling edge 4 Ts DA UD 3 0 LD 3 0 hold to FPSHIFT falling edge 4 Ts 1 Ts pixel clock period memory clock memory clock 2 memory clock 3 memory clock 4 see REG 1 9h bits 1 0 2 timin min 14Ts 3 Amin REG 04h bits 6 0 1 8 REG O5h bits 4 0 1 8 Ts 4 t5min REG O4h bits 6 0 1 8 REG O5h bits 4 0 1 8 1 Ts 5 t6min REG O5h bits 4 0 1 8 25 Ts 6 t9min REG O5h bits 4 0 1 8 16 Ts SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 81 Vancouver Design Center 7 5 3 4 Bit Single Color Passive LCD Panel Timing VDP VNDP FPFRAME FPLINE I es ste Sl l I l I MOD f X UD 3 0 UNE X LINE2 X LINES YX LINE4 LINE479 L
194. ED1355 An optional external oscillator may be used for BUSCLK since the SED1355 will accept host bus control signals asynchronously with respect to BUSCLK The following diagram shows a typical implementation of the interface V 3 3V PR31500 PR31700 0433 sED1355 e M R CSH BSH AB 16 13 A 12 0 gt AB 12 0 D 23 16 gt DB 15 8 D 31 24 ka DB 7 0 ALE AB20 CARDREG AB19 CARDIORD AB18 CARDIOWR AB17 CARDxCSH gt WE1 CARDxCSL gt RD WR RD gt RD WE V ulku gt WEO CARDxWAIT lw DO Fy BUR WAIT System RESET gt RESET ENDIAN Y DCLKOUT gt or Oscillator BUSCLK See text SCH Note When connecting the SED1355 RESET pin the system designer should be aware of all conditions that may reset the SED1355 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 Typical Implementation of Direct Connection Interfacing to the Philips MIPS PR31500 PR31700 Processor SED1355 Issue Date 99 05 05 X23A G 001 06 Page 10 Epson Research and Development Vancouver Design Center The host interface control signals of the SED1355 are asynchronous with respect to the SED1355 bus clock This gives the system designer full flexibility to choose the appropriate source or sources for CLKI and BUSCLK The choice of whether both clocks should be
195. EGISTER MCLK Divide Slct Bit 1 PCLK Divide Slct Bit O RW Suspend Ref resh Select REG 22h PERFORMANCE ENHANCEMENT REGISTER 0 RC Timing Value Y Bit 1 Bit 0 REG 23h PERFORMANCE RAS to ENHANCEMENT REGISTER 1 RAS Precharge Timing Bit 0 Reserved RW Reserved Display FIFO CPU to Memory Wait State Disable Bit O Displ Bit 4 Bit 3 lay FIFO Threshold Bit 2 Bit 1 REG 24h Look Up TABLE ADDRESS REGISTER RW Look Up Table Address Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O REG 26h Look Up TABLE DATA REGISTER RW Look Up Table Data Bit 3 Bit 2 Bit 1 Bit 0 n a n a n a n a REG 27h INK CURSOR CONTROL REGISTER Ink Cursor Mode n a Bit 1 Bit 0 n a Bit 3 Cursor High Threshold Bit 2 Bit 1 RW Bit 0 REG 28h CURSOR X POSITION REGISTER 0 REG 29h CURSOR X POSITION REGISTER 1 Bit 4 Cursor X Position Bit 3 RW RW Reserved n a n a REG 2Ah Cursor Y POSITION REGISTER 0 Cursor X Bit 9 Position Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Position Bit 3 Cursor Y REG 2Bh Cursor Y POSITION REGISTER 1 RW Cursor Y Position Reserved n a n a n a n a n a Bit 9 Bit 8 REG 2Ch INk CURSOR COLOR 0 REGISTER 0 RW h j j i Vertical Display Height Power sayo n a n a n a er Powe aro Cursor Color 0 n a n a n a n a ji ii Bit 9 Bits SS prec Bit 1 B
196. ELUKOA7 DRSEE ECE Obivdds 6lVGds 81v0d3 H33n DH EI EI ND 30A YAZ pve EAZ evz ZAZ eve LAZ bw PAL rei EAL evi ZAL evi LAL Lei Zn YOLOSNNOO M ONOW 4O109 Zivdds Sivad GESER elvdds zlvGds Livads Olvads st ollwads Page 22 Issue Date 98 10 30 SDU1355B0C Rev 1 0 ISA Bus Evaluation Board User Manual SED1355B0C Schematic Diagram 4 of 4 Figure 4 SED1355 X23A G 004 04 EPSON SDU1355 D9000 Evaluation Board User Manual Document Number X23A G 002 03 Copyright O 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Microsoft and Windows are registered trademarks of Microsoft Corporation Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SDU1355 D9000 Evaluation Board User Manual X23A G 002 03 Issue Date 98 1
197. EPSON SED1355 Embedded RAMDAC LCD CRT Controller SED1355 TECHNICAL MANUAL Document Number X23A Q 001 09 Copyright O 1998 1999 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 TECHNICAL MANUAL X23A Q 001 09 Issue Date 99 10 06 Epson Research and Development Page 3 Vancouver Design Center Customer Support Information Comprehensive Support Tools Seiko Epson Corp provides to the system designer and computer OEM manufacturer a complete set of resources and tools for the development of graphics systems Evaluation Demonstration Board e Assembled and fully tested graphics evaluation board with installation guide and schematics e To borrow an evaluation board please contact your local Seiko Epson Corp sales representative Chip Documentatio
198. FD these bits specify the pulse width of HRTC and FPLINE respectively For passive LCD FPLINE is automatically created and these bits have no effect HRTC FPLINE pulse width pixels HRTC FPLINE Pulse Width Bits 3 0 1 x 8 The maximum HRTC pulse width is 128 pixels Note This register must be programmed such that REG 05h 1 gt REG 06h 1 REG 07h bits 3 0 1 SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 105 Vancouver Design Center Vertical Display Height Register 0 REG 08h RW Vertical Vertical Vertical Vertical Vertical Vertical Vertical Vertical Display Display Display Display Display Display Display Display Height Bit 7 Height Bit 6 Height Bit5 Height Bit4 Height Bit3 Height Bit 2 Height Bit 1 Height Bit 0 Vertical Display Height Register 1 REG 09h RW Vertical Vertical n a n a n a n a n a n a Display Display Height Bit 9 Height Bit 8 REG 08h bits 7 0 REG 09h bits 1 0 Vertical Display Height Bits 9 0 These bits specify the vertical display height Vertical display height lines Vertical Display Height Bits 9 0 1 e For CRT TFT D TED and single passive LCD panel this register is programmed to vertical resolution of the display 1 e g EFh for a 240 line display e For dual panel passive LCD not in simultaneous display mode this register is
199. G 1Bh bit 0 6 When setting a horizontal resolution greater than 767 pixels with a color depth of 15 16 bpp the Memory Offset Registers REG 16h REG 17h must be set to a virtual horizontal pixel resolution of 1024 14 3 Bandwidth Calculation When calculating the average bandwidth there are two periods that must be calculated separately The first period is the time when the CPU is in competition with the display refresh fetches The CPU can only access the memory when the display refresh releases the memory controller The CPU bandwidth during this period is called the bandwidth during display period The second period is the time when the CPU has full access to the memory with no competition from the display refresh The CPU bandwidth during this period is called the bandwidth during non display period To calculate the average bandwidth calculate the percentage of time between display period and non display period The percentage of display period is multiplied with the bandwidth during display period The percentage of non display period is multiplied with the bandwidth during non display period The two products are summed to provide the average bandwidth Bandwidth during non display period Based on simulation it requires a minimum of 12 MCLKs to service one two byte CPU access to memory This includes all the internal handshaking and assumes that Ngc is set to 4MCLKs and the wait state bits are set to 10b B
200. Hong Kong Tel 2585 4600 Fax 2827 4346 8 2 Toshiba MIPS TX3912 Processor http www toshiba com taec nonflash indexproducts html 8 3 ITE IT8368E Integrated Technology Express Inc Sales amp Marketing Division 2710 Walsh Avenue Santa Clara CA 95051 USA Tel 408 980 8168 Fax 408 980 9232 http www iteusa com SED1355 X23A G 010 03 Epson Research and Development Vancouver Design Center Taiwan R O C Epson Taiwan Technology 8 Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Interfacing to the Toshiba MIPS TX3912 Processor Issue Date 99 05 05 EPSON SED1355 Embedded RAMDAC LCD CRT Controller Interfacing to the NEC VR4121 Microprocessor Document Number X23A G 011 03 Copyright 1998 1999 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or Internationa
201. INE480 K LINE1 X LINE2 e FPLINE l E MOD X HDP HNDP a gt FPSHIFT Sek Mia LJ AAA EE UD3 K 1 R1X 1 G2X 1 B3 LE V Xr B319 y UD2 1 G1X 1 82 X 1 R4 X Y1 R320 X UDI 1 B1 X 1 R3 X 1 G4 a Y V1 G320 o Y UDO 1 R2X 1 G3 1 B4 Y Y1 B320 Be D Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7 28 4 Bit Single Color Passive LCD Panel Timing VDP Vertical Display Period REG 09h bits 1 0 REG O8h bits 7 0 1 VNDP Vertical Non Display Period REG OAh bits 5 0 1 HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period REG O5h bits 4 0 1 8Ts Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 82 Epson Research and Development Vancouver Design Center tl t2 Sync Timing gl FPFRAME 13 H FPLINE 5 MOD Data Timing FPLINE FPSHIFT UD 3 0 Figure 7 29 4 Bit Single Color Passive LCD Panel A C Timing Table 7 25 4 Bit Single Color Passive LCD Panel A C Timing Symbol Parameter Min Typ Max Units ti FPFRAME setup to FPLINE pulse trailing edge note 2 t2 FPFRAME hold from FPLINE pulse trailing edge 14 Ts note 1 t3 FPLINE pulse width 9 Ts t4 FPLINE period note 3 t5 MOD delay from FPLINE pulse trailing edge note 4 t6 FPSHIFT falling edge to FPLINE pulse l
202. IO buffers the SED1355 can be interfaced so as to share one of the PC Card slots 5 1 Hardware Description The IT8368E can be programmed to allocate the same portion of the PC Card Attribute and IO space to the SED1355 as in the direct connection implementation described in Section 4 Direct Connection to the Philips PR31500 PR31700 on page 9 Following is a block diagram showing an implementation using the IT8368E PC Card buffer PR31500 PR31700 SED1355 IT8368E PC Card Device IT8368E PC Card Device Figure 5 1 ITS368E Implementation Block Diagram SED1355 X23A G 001 06 Interfacing to the Philips MIPS PR31500 PR31700 Processor Issue Date 99 05 05 Epson Research and Development Page 13 Vancouver Design Center 5 2 IT8368E Configuration The ITE IT8368E has been specifically designed to support EPSON LCD CRT controllers Older EPSON Controllers not supporting a direct interface to the Philips processor can utilize the IT8368E MFIO pins to provide the necessary control signals however when using the SED1355 this is not necessary as the Direct Connection described in Section 4 Direct Connection to the Philips PR31500 PR31700 on page 9 can be used The IT8368E must have both Fix Attribute IO and VGA modes enabled When both these modes are enabled a 16M byte portion of the system PC Card attribute and IO space is all
203. Indicates the Look Up Table is not used for that display mode SED1355 Programming Notes and Examples X23A G 003 05 Issue Date 99 04 27 Epson Research and Development Page 17 Vancouver Design Center Color Modes Programming Notes and Examples Issue Date 99 04 27 In color display modes depending on the color depth 2 through 256 index entries are used The selection of which entries are used is automatic 1 bpp color When the SED1355 is configured for 1 bpp color mode the LUT is limited to the first two entries The two LUT entries can be any two RGB values but are typically set to black and white Each byte in the display buffer contains 8 bits each pertaining to adjacent pixels A bit value of 0 results in the LUT 0 index value being displayed A bit value of l results in the LUT 1 index value being displayed The following table shows the recommended values for obtaining a black and white mode while in 1 bpp on a color panel Table 4 2 Recommended LUT Values for 1 Bpp Color Mode Index Red Green Blue 00 00 00 00 01 FO FO FO 02 FF se Indicates unused entries in the LUT 2 bpp color When the SED1355 is configured for 2 bpp color mode only the first 4 entries of the LUT are used These four entries can be set to any desired values Each byte in the display buffer contains 4 adjacent pixels Each pair of bits in the byte are used as an index into the LUT The following t
204. LINE setup to FPSHIFT falling edge 0 45 Ts t12 FPFRAME pulse leading edge to FPLINE pulse note 7 leading edge phase difference t13 DRDY to FPSHIFT falling edge setup time 0 45 Ts t14 DRDY pulse width note 8 t15 DRDY falling edge to FPLINE pulse leading note 9 edge t16 DRDY hold from FPSHIFT falling edge 0 45 Ts t17 FPLINE pulse leading edge to DRDY active note 10 250 Ts 1 Ts pixel clock period memory clock memory clock 2 memory clock 3 memory clock 4 see REG 19h bits 1 0 2 t6min REG 04h bits 6 0 1 8 REG O5h bits 4 0 1 8 Ts 3 Go REG 07h bits 3 0 1 8 Ts 4 t8 min REG 09h bits 1 0 REG O8h bits 7 0 1 REG OAh bits 5 0 1 lines 5 e REG OCH bits 2 0 1 lines 6 t10min REG 04h bits 6 0 1 8 Ts 7 tl2min REG O6h bits 4 0 8 1 Ts 8 t14 nin REG 04h bits 6 0 1 8 Ts 9 t15min REG 06h bits 4 0 1 8 2 Ts 10 117 min REG 05h bits 4 0 1 8 REG O6h bits 4 0 1 8 2 Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 98 Epson Research and Development Vancouver Design Center 7 5 11 CRT Timing VNDP VDP 4 pie gt VRTC We Hr U U L JU U U U RED GREEN BLUE LINE480 LINE1 X X_LINE480 HRTC BT A an gedo HNDP HDP j y e pe NDP y RED GREEN BLUE eet E Oh Example Timing for 640x480 CRT Figure 7
205. MIPS TX3912 Processor Issue Date 99 05 05 Epson Research and Development Page 13 Vancouver Design Center 4 3 Memory Mapping and Aliasing The TX3912 uses a portion of the PC Card Attribute and IO space to access the SED1355 The SED1355 responds to both PC Card Attribute and IO bus accesses thus freeing the programmer from having to set the TX3912 Memory Configuration Register 3 bit CARDIIOEN or CARD2IOEN if slot 2 is used As a result the TX3912 sees the SED1355 on its PC Card slot as described in the table below Table 4 2 TX3912 to PC Card Slots Address Remapping for Direct Connection SED1355 Uses PC Card Slot Toshiba Address Size Function 0800 0000h 16M byte Card 1 IO or Attribute SED1355 registers 0900 0000h 8M byte aliased 4 times at 2M byte intervals 1 SED1355 display buffer 0980 0000h 8M byte l l aliased 4 times at 2M byte intervals 0A00 0000h 32M byte Card 1 10 or Attribute 6400 0000h 64M byte Card 1 Memory 0C00 0000h 16M byte Card 2 IO or Attribute SED1355 registers 0D00 0000h 8M byte l l aliased 4 times at 2M byte intervals 2 SED1355 display buffer 0D80 0000h 8M byte l aliased 4 times at 2M byte intervals 0E00 0000h 32M byte Card 2 IO or Attribute 6800 0000h 64M byte Card 2 Memory Interfacing to the Toshiba MIPS TX3912 Processor SED1355 Issue Date 99 05 05 X23A G 010 03 Page 14 Epson Research and Development Vancouver Design Center 5 System
206. Max Units ti FPFRAME setup to FPLINE pulse trailing edge note 2 t2 FPFRAME hold from FPLINE pulse trailing edge 14 Ts note 1 t3 FPLINE pulse width 9 Ts t4 FPLINE period note 3 t5 MOD delay from FPLINE pulse trailing edge note 4 t6 FPSHIFT falling edge to FPLINE pulse leading edge note 5 t7 FPLINE pulse trailing edge to FPSHIFT falling edge t10 t11 Ts t8 FPSHIFT period 4 Ts t9 FPSHIFT falling edge to FPLINE pulse trailing edge note 6 t10 FPLINE pulse trailing edge to FPSHIFT rising edge 20 Ts t11 FPSHIFT pulse width high 2 Ts t12 FPSHIFT pulse width low 2 Ts t13 UDI3 0 setup to FPSHIFT falling edge 2 Ts t14 UD 3 0 hold to FPSHIFT falling edge 2 Ts 1 Ts pixel clock period memory clock memory clock 2 memory clock 3 memory clock 4 see REG 1 9h bits 1 0 2 tlmin t4min 14Ts 3 t4min REG O04h bits 6 0 1 8 REG O5h bits 4 0 1 8 Ts A t5min REG 04h bits 6 0 1 8 REG O5h bits 4 0 1 8 1 Ts 5 min REG O5h bits 4 0 1 8 27 Ts 6 t9min REG O5h bits 4 0 1 8 18 Ts SED1355 X23A A 001 11 Hardware Functional Specification Issue Date 99 05 18 Epson Research and Development Page 79 Vancouver Design Center 7 5 2 8 Bit Single Monochrome Passive LCD Panel Timing VDP VNDP FPFRAME FPLINE f l
207. Memory Interface Timing for detailed functionality MA10 59 C TS Output This is a multi purpose pin e For asymmetrical 2M byte DRAM this is memory address bit 10 MA10 e For symmetrical 2M byte DRAM and all 512K byte DRAM this pin can be used as general purpose IO pin 1 GPIO1 Note that unless configured otherwise this pin defaults to an input and must be driven to a valid logic level See Memory Interface Pin Mapping for summary See Memory Interface Timing for detailed functionality MA11 57 C TS Output This is a multi purpose pin e For asymmetrical 2M byte DRAM this is memory address bit 11 MA11 e For symmetrical 2M byte DRAM and all 512K byte DRAM this pin can be used as general purpose lO pin 2 GPIO2 Note that unless configured otherwise this pin defaults to an input and must be driven to a valid logic level See Memory Interface Pin Mapping for summary See Memory Interface Timing for detailed functionality SED1355 X23A A 001 11 Hardware Functional Specification Issue Date 99 05 18 Epson Research and Development Vancouver Design Center 5 2 3 LCD Interface Page 31 Table 5 2 LCD Interface Pin Descriptions Pin Name Type Pin Cell RESET State Description i 95 88 Panel data bus Not all pins are used for some panels see LCD SEBES E 86 79 ENG Output Interfa
208. Mone LEE 2 18 75KB LZ Se 16 bpp 960KB 2032KB 1968KB 8 bpp 600KB e ERE TE T2MB Single PE OKB 8 bpp 600KB E e eg 1L2MB 2MB 1KB 800 x 600 EP i 2032KB 1920KB 8 bpp 600KB 117 19KB Color 117 19KB 16 bpp 1 2MB me 8b 600KB Mono EP 29 30KB 16 bpp 12MB Where KB K bytes and MB 1024K bytes 13 4 Limitations The following limitations apply to SwivelView e Only 8 bpp and 16 bpp modes are supported 1 2 4 bpp modes are not supported e Hardware cursor and ink layer images are not rotated software rotation must be used Swivel View must be turned off when the programmer is accessing the sprite or the ink layer e Split screen images appear side by side i e the portrait display is split vertically e Pixel panning works vertically Hardware Functional Specification Issue Date 99 05 18 SED1355 X23A A 001 11 Page 140 Epson Research and Development Vancouver Design Center 14 Clocking 14 1 Maximum MCLK PCLK Ratios Table 14 1 Maximum PCLK Frequency with EDO DRAM Ink Display t N Maximum PCLK Allowed n ispla e EE RC Typen 2bpp 4bpp 8bpp 16 bpp e Single Panel e CRT e Dual Monochrome Color Panel with Half Frame Buffer Disabled 5 4 3 MCLK e Simultaneous CRT Single Panel e Simultaneous CRT Dual Monochrome Color Panel with Half Frame Buffer Disabled off 1 Dual Monochrome
209. NEC Electronics Inc Vr4102 V4111 NEC Electronics Inc U S A Corporate Headquarters 2880 Scott Blvd Santa Clara CA 95050 8062 USA Tel 800 366 9782 Fax 800 729 9288 http www nec com SED1355 X23A G 007 05 Epson Research and Development Vancouver Design Center Taiwan R O C Epson Taiwan Technology 8 Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Interfacing to the NEC VR4102 VR4111 Microprocessors Issue Date 99 05 05 EPSON SED1355 Embedded RAMDAC LCD CRT Controller Interfacing to the Motorola MPC821 Microprocessor Document Number X23A G 008 03 Copyright 1998 1999 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their
210. O 60ns FPM 72 31 500 50ns EDO 60ns EDO 75 31 500 50ns EDO 60ns EDO 85 36 000 50ns EDO 800x600 56 36 000 50ns EDO 60 40 000 50ns EDO e 1355CFG does not support 50ns FPM DRAM e 1355CFG programs TFT D TFD panels with the same VESA timings as a CRT so the CRT restrictions shown in the hardware specification also apply to TFT D TFD panels Consequently for TFT D TFD panels use the CRT frame rate and CRT PCLK as described above e For simultaneous display select a CRT VESA mode and use the CRT s frame rate for the panel s frame rate 1355CFG Configuration Program SED1355 Issue Date 98 10 30 X23A B 001 02 Page 18 Epson Research and Development Vancouver Design Center Sample Program Messages SED1355 X23A B 001 02 ERROR Panel frame rate must be greater than zero Select an appropriate panel frame rate as recommended in the panel specifications ERROR Unable to save current settings Could not save configuration values The reason why is generally given before this message is shown ERROR Invalid clock frequency selected The CIkI frequency is either too low or too high ERROR Max clock for 50ns FPM is unspecified 1355CFG does not support 50ns FPM DRAM WARNING Cannot set panel display mode This message is shown if the configuration settings do not meet the hardware specifications or if the desired frame rate cannot be reached within 5 See Comments on page 17 for more information WARNING Cannot
211. O FO E0 A3 70 60 50 E3 30 20 40 24 FO 00 FO 64 BO FO FO A4 70 70 50 E4 40 20 40 25 FO 00 BO 65 BO E0 FO A5 60 70 50 E5 40 20 30 26 FO 00 70 66 BO DO FO A6 60 70 50 E6 40 20 30 27 FO 00 40 67 BO CO FO A7 50 70 50 E7 40 20 30 28 FO 00 00 68 00 00 70 A8 50 70 50 E8 40 20 20 29 FO 40 00 69 10 00 70 A9 50 70 50 E9 40 30 20 2A FO 70 00 6A 30 00 70 AA 50 70 60 EA 40 30 20 2B FO BO 00 6B 50 00 70 AB 50 70 60 EB 40 30 20 2C FO FO 00 6C 70 00 70 AC 50 70 70 EC 40 40 20 2D BO FO 00 6D 70 00 50 AD 50 60 70 ED 30 40 20 2E 70 FO 00 6E 70 00 30 AE 50 60 70 EE 30 40 20 2F 40 FO 00 6F 70 00 10 AF 50 50 70 EF 30 40 20 30 00 FO 00 70 70 00 00 BO 00 00 40 FO 20 40 20 31 00 FO 40 71 70 10 00 B1 10 00 40 F1 20 40 30 32 00 FO 70 72 70 30 00 B2 20 00 40 F2 20 40 30 33 00 FO BO 73 70 50 00 B3 30 00 40 F3 20 40 30 34 00 FO FO 74 70 70 00 B4 40 00 40 F4 20 40 40 35 00 BO FO 75 50 70 00 B5 40 00 30 F5 20 30 40 36 00 70 FO 76 30 70 00 B6 40 00 20 F6 20 30 40 37 00 40 FO 77 10 70 00 B7 40 00 10 F7 20 30 40 38 70 70 FO 78 00 70 00 B8 40 00 00 F8 00 00 00 39 90 70 FO 79 00 70 10 B9 40 10 00 F9 00 00 00 3A BO 70 FO 7A 00 70 30 BA 40 20 00 FA 00 00 00 3B DO 70 FO 7B 00 70 50 BB 40 30 00 FB 00 00 00 3C FO 70 FO 7C 00 70 70 BC 40 40 00 FC 00 00 00 3D FO 70 DO 7D 00 50 70 BD 30 40 00 FD 00 00 00 3E FO 70 BO 7E 00 30 70 BE 20 40 00 FE 00 00 00 3F FO 70 90 7F 00 10 70 BF 10 40 00 FF 00 00 00
212. O and bits 445t1 3 AS 3 2 00 Read Command Setup REG 22h bit 4 O and bits 3 4511 3 he 3 2 10 t12 Read Command Setup REG 22h bit 4 1 and bits 3 45 11 3 e 3 2 00 Read Command Setup REG 22h bit 4 1 and bits 2454 3 Gs 3 2 10 Read Command Setup REG 22h bits 3 2 01 3 45 t1 3 ns Read Command Hold REG 22h bit 4 0 and bits 3 3 45 11 3 ne 2 00 Read Command Hold REG 22h bit 4 O and bits 3 245 11 3 ae 2 10 t13 Read Command Hold REG 22h bit 4 1 and bits 3 2454 3 D 2 00 Read Command Hold REG 22h bit 4 1 and bits 3 1451 3 NE 2 10 Read Command Hold REG 22h bits 3 2 01 2 45 t1 3 ns t14 Read Data Setup referenced from CAS 5 ns t15 Read Data Hold referenced from CAS 3 ns t16 Last Read Data Setup referenced from RAS 5 ns t17 Bus Turn Off from RAS 3 t1 5 ns t18 Write Command Setup 0 45 t1 3 ns t19 Write Command Hold 0 45 t1 3 ns t20 Write Data Setup 0 45 t1 3 ns t21 Write Data Hold 0 45t1 3 ns t22 MD Tri state 0 45 t1 0 45t1 21 ns t23 CAS to WE active during Read Write cycle 1t1 3 ns t24 Write Command Setup during Read Write cycle 1 45 t1 3 ns 125 Last Read Data Setup referenced from WE during 10 is Read Write cycle t26 Bus Tri state from WE during Read Write cycle 0 t1 5 ns SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and
213. OW Consult the 1355CFG users guide document number X23A B 001 xx for more information on configuring SED 1355 utilities This software is designed to work in both embedded and personal computer PC environments For the embedded environment it is assumed that the system has a means of downloading software from the PC to the target platform Typically this is done by serial communications where the PC uses a terminal program to send control commands and information to the target processor Alternatively the PC can program an EPROM which is then placed in the target platform Some target platforms can also communicate with the PC via a parallel port connection or an Ethernet connection SED1355 Supported Evaluation Platforms Issue Date 98 10 29 1355SHOW supports the following SED1355 evaluation platforms PC system with an Intel 80x86 processor M68332BCC Business Card Computer board revision B with a Motorola MC68332 processor M68ECOOOIDP Integrated Development Platform board revision 3 0 with a Motorola M68EC000 processor SH3 LCEVB board revision B with an Hitachi SH 3 HD6417780 processor Installation PC platform copy the file 1355SHOW EXE to a directory that is in the DOS path on your hard drive Embedded platform download the program 1355SHOW to the system 1355SHOW Demonstration Program SED1355 X23A B 002 04 Page 4 Usage PC platform at the prompt type Epson Research and Development Vancouve
214. P3P4P5P6P7 5 5 5 RGB bit 7 bit 0 Pa S R Gn 40 B 0 Panel Display Host Address Display Memory PoP P2P3P4P5P6P7 Ph RAF Gn 5 0 B Panel Display Host Address Display Memory Figure 10 2 15 16 Bit per pixel Format Memory Organization Note 1 The Host to Display mapping shown here is for a little endian system 2 For 15 16 bpp formats R G B represent the red green and blue color components SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Page 127 image or images d for Screen 1 REG 18h ing wor in the starti ing word for Screen 2 ixel with in the start ing pixe 1 with ing pixe 0 define the start ne the start 4 defi REG 15h REG 14h REG 13 defines the starting word of the Screen 2 e REG 18h bits 3 bits 7 e REG OFh REG OEh define the last line of Screen 1 the remainder of the display is taken up The figure below shows how Screen 1 and 2 images are stored in the image buffer and positioned on the display Screen 1 and Screen 2 can be parts of a larger virtual e REG 17h REG 16h defines the width of the virtual image s e REG 12h REG 1 1h REG 10 defines the starting word of the Screen 1 Epson Research and Development 10 2 Image Manipulation Vancouver Design Center SED1355 X23A A 001 11 AAA E E E E E E E E E
215. PR31500 PR31700 Processor Philips Semiconductors Handheld Computing Group 4811 E Arques Avenue M S 42 P O Box 3409 Sunnyvale CA 94088 3409 Tel 408 991 2313 http www philips com 8 3 ITE IT8368E Integrated Technology Express Inc Sales amp Marketing Division 2710 Walsh Avenue Santa Clara CA 95051 USA Tel 408 980 8168 Fax 408 980 9232 http www iteusa com SED1355 X23A G 001 06 Epson Research and Development Vancouver Design Center Taiwan R O C Epson Taiwan Technology 8 Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Interfacing to the Philips MIPS PR31500 PR31700 Processor Issue Date 99 05 05 EPSON SED1355 Embedded RAMDAC LCD CRT Controller Interfacing to the PC Card Bus Document Number X23A G 005 05 Copyright O 1998 1999 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain mat
216. Pan amp OFh WriteRegister 18h register SED1355 Programming Notes and Examples X23A G 003 05 Issue Date 99 04 27 Epson Research and Development Page 41 Vancouver Design Center 9 CRT Considerations 9 1 Introduction 9 1 1 CRT Only The SED1355 is capable of driving either an LCD panel or a CRT display or both simultaneously As display devices panels tend to be lax in their horizontal and vertical timing requirements CRT displays often cannot vary by more than a very small percentage in their timing requirements before the image is degraded Central to the following sections are VESA timings Rather than fill this section of the guide with pages full of register values it is recommended that the program 1355CFG EXE be used to generate a header file with the appropriate values For more information on VESA timings contact the Video Electronics Standards association on the world wide web at www vesa org All CRT output should meet VESA timing specifications The VESA specification details all the parameters of the display and non display times as well as the input clock required to meet the times Given a proper VESA input clock the configuration program 1355CFG EXE will generate correct VESA timings for 640x480 and for 800x600 modes 9 1 2 Simultaneous Display As mentioned in the previous section CRT timings should always comply to the VESA specifi cation This requirement implies that during simultaneous operation the t
217. Panel with Half Frame Buffer 5 MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 3 Enabled 4 MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 3 e Simultaneous CRT Dual Monochrome Panel with Half Frame Buffer Enable 3 MCLK MCLK MCLK 2 MCLK 2 MCLK 2 e Dual Color Panel with Half Frame Buffer Enabled 5 MCLK 2 MCLK 2 MCLK 2 MCLK 3 MCLK 3 e Simultaneous CRT Dual Color Panel with Half 4 MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 3 F Buffer Enable SE 3 MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 3 e Single Panel 5 MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 3 CRT 4 MCLK MCLK MCLK 2 MCLK 2 MCLK 2 e Dual Monochrome Color Panel with Half Frame Buffer Disabled e Simultaneous CRT Single Panel 3 MCLK MCLK MCLK MCLK 2 MCLK 2 e Simultaneous CRT Dual Monochrome Color Panel with Half Frame Buffer Disabled on Dual Monochrome Panel with Half Frame Buffer 5 MCLK 2 MCLK 3 MCLK 3 MCLK 3 MCLK 3 Enabled 4 MCLK 2 MCLK 2 MCLK 2 MCLK 3 MCLK 3 e Simultaneous CRT Dual Monochrome Panel with Half Frame Buffer Enable 3 MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 3 e Dual Color Panel with Half Frame Buffer Enabled 5 MCLK 3 MCLK 3 MCLK 3 MCLK 3 MCLK 4 e Simultaneous CRT Dual Color Panel with Half 4 MCLK 2 MCLK 2 MCLK 3 MCLK 3 MCLK 3 F Buffer Enable cried 3 MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 3 SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 141 Vanc
218. REG 04h bits 6 0 1 8 REG O5h bits 4 0 1 8 Ts 4 t5min REG 04h bits 6 0 1 8 REG O5h bits 4 0 1 8 1 Ts 5 min REG O5h bits 4 0 1 8 27 Ts 6 t7min REG O5h bits 4 0 1 8 18 Ts SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 VDP VNDP HDP HNDP Epson Research and Development Page 89 Vancouver Design Center 7 5 7 8 Bit Dual Monochrome Passive LCD Panel Timing VDP o VNDP FPFRAME FPLINE I MOD X UD 3 0 LD 3 0 LINE 1 241 X LINE 2 242 X LINE 3 243 X LINE 4 244 _ XLINE 239 479LINE 240 480 ALINE 1 241 LINE 2 242 FPLINE Di WW MOD X I lt HDP de HNDP FPSHIFT UD3 Ata X 15 X X X X 1 637 X UD2 12 X 16 X Y X 1 638 X UD 13 X 1 7 X AS gt Y X 1 639 A Y UDO 14 X 18 X X EN YX X 1 640 4 D LD3 241 1 X 241 5 Y X 241 63 7 4 Y LD2 ER 241 6 X Y D 241 638 X LD1 241 3 241 7 Y X X 241 639 X LDO 241 4 241 8 X X X 241 640 D Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7 36 8 Bit Dual Monochrome Passive LCD Panel Timing Vertical Display Period REG 09h bits 1 0 REG O8h bits 7 0 1 Vertical Non Display Period REG OAN bits 5 0 1 Horizontal Display Period REG 04h bits 6 0 1 8Ts Horizontal Non Display Period REG O5h bits 4 0 1 8Ts Hardware Functional Specification SED1355
219. RS 50 Generic A EENEG 52 MIPSASA TMB o mm ee E A bee eee EE we 54 Philips Er ENEE 56 Clock Input Requirements for BUSCLK using Philips local bus 57 Toshiba IO ien A A EE A a AA 59 Clock Input Requirements for BUSCLK using Toshiba local bus 60 Power PC TIMI Ng be ee e E EE A EE e a 62 Clock Input Requirements for CLKI divided down internally MCLK CLKI 2 63 Clock Input Requirements for CLLK 63 EDO DRAM Read Write Read Write Tunn 65 EDO DRAM CAS Before RAS Refresh TiMIN8 o 67 EDO DRAM Self Refresh Timing 2 2 0 0 0 0000000000000 000 69 FPM DRAM Read Write Read Write Timing 0 2 000000 71 FPM DRAM CAS Before RAS Refresh Tun 73 FPM DRAM CBR Self Refresh Im 74 LCD Panel Power OP Power On eee ee 75 Power Save Status and Local Bus Memory Access Relative to Power Save Mode 76 4 Bit Single Monochrome Passive LCD Panel A C Timing o 78 8 Bit Single Monochrome Passive LCD Panel A C TiMidg 80 4 Bit Single Color Passive LCD Panel A C Timing 82 8 Bit Single Color Passive LCD Panel A C Timing Formatl 84 SED1355 X23A A 001 11 Page 8 Table 7 27 Table 7 28 Table 7 29 Table 7 30 Table 7 31 Table 7 32 Table 8 1 Table 8 2 Table 8 3 Table 8 4 Table 8 5 Table 8 6 Table 8 7 Table 8 8 Table 8 9 Table 8 10 Table 8 11 Table 8 12
220. RTC_START_POSITION 0x06 define REG_HRTC_PULSE_WIDTH 0x07 define REG_VERT_DISP_HEIGHTO 0x08 define REG_VERT_DISP_HEIGHT1 0x09 define REG_VERT_NONDISP_PERIOD Ox0A define REG_VRTC_START_POSITION Ox0B define REG_VRTC_PULSE_WIDTH Ox0C Programming Notes and Examples SED1355 X23A G 003 05 Page 92 AX_REG must be the last available register define REG_DISPLAY_MODE define REG_SCRN1_LINE_COMPAREO define REG_SCRN1_LINE_COMPARE1 define REG_SCRN1_DISP_START_ADDRO define REG_SCRN1_DISP_START_ADDR1 define REG_SCRN1_DISP_START_ADDR2 define REG_SCRN2_DISP_START_ADDRO define REG_SCRN2_DISP_START_ADDR1 define REG_SCRN2_DISP_START_ADDR2 define REG_MEM_ADDR_OFFSETO define REG_MEM_ADDR_OFFSE define REG_PIXEL PANNING define REG_CLOCK_CONFIG define REG_POWER_SAVE_CONFIG define REG_MISC define REG_MD_CONFIG_READBACKO define REG_MD_CONFIG_READBACK1 define REG_GPIO_CONFIGO define REG_GPIO_CONFIG1 define REG_GPIO_CONTROLO define REG_GPIO_CONTROL1 define REG_PERF_ENHANCEMENTO define REG_PERF_ENHANCEMENT1 define REG_LUT_ADDR define REG_RESERVED_1 define REG_LUT_DATA define REG_INK_CURSOR_CONTROL define REG_CURSOR_X_POSITIONO defin
221. Regs 0x0C Register D Regs 0x0D Si Registers Regs 0x0E SED1355 X23A G 003 05 E F 9 Vertical 0000 0000 480 lines 480 2 J OxEF 0x00 Vertical Non This registe to arrive at frame rate 0x01 T VRIC FPFRAME 0x00 VRIC FPFRAME 0x00 Display Mode 0x0C Screen 1 split scr OxFF Display Heig VDP 239t 0x 8 EF JR LILO TITI 0000 0000 VNDP r must be programed with register 5 th Display Period HNDP closest to the desired frame rat 0000 0001 Start Position applicable to CRT TFT only 0000 0000 Pulse Width applicable to CRT TFT only 0000 0000 8 BPP LCD disabled 0000 1100 Line Compar unless setting up for een operation use Ox3FF 1111 1111 Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 85 Vancouver Design Center pRegs 0x0F 0x03 0000 0011 Registers 10 12 Screen 1 Display Start Address start at the first byte in display memory Wi pRegs 0x10 0x00 0000 0000 pRegs 0x11 0x00 0000 0000 pRegs 0x12 0x00 0000 0000 JK Register 13 15 Screen 2 Display Start Address not applicable KK unless setting up for split screen operation Af pRegs 0x13 0x00 0000 0000 pRegs 0x14 0x0
222. Rev 1 0 ISA Bus Evaluation Board User Manual SED1355 Issue Date 98 10 30 X23A G 004 04 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 SDU1355B0C Rev 1 0 ISA Bus Evaluation Board User Manual X23A G 004 04 Issue Date 98 10 30 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction 1 1 Features This manual describes the setup and operation of the SDU1355BOC Rev 1 0 Evaluation Board Implemented using the SED1355 Embedded RAMDAC LCD CRT Controller the SDU1355BOC is designed for the ISA bus environment It also provides CPU Bus interface connectors for non ISA bus support For more information regarding the SED1355 refer to the SED1355 Hardware Functional Specifi cation document number X23A A 001 xx 128 pin QFP15 surface mount package SMT technology for all appropriate devices 4 8 bit monochrome passive LCD panel support 4 8 16 bit color passive LCD panel support 9 12 18 bit LCD TFT D TFD panel support Embedded RAMDAC for CRT support 16 bit ISA bus support Oscillator support for CLKI up to 40 0MHz 5 0V 1M x 16 EDO DRAM 2M byte Support for software and hardware suspend modes On board adjustable LCD bias power supply 24 38V or 24 14V CPU Bus interface header strips for non ISA bus support SDU1355B0C Rev 1 0 ISA Bus Evaluation Board User Manual SED1355 Issue Date 98 10 30 X23A G 004 04 Page 8 2 Installation and Confi
223. SED1355 MIPS ISA Host Bus Interface requires the following signals BUSCLK is a clock input which is required by the SED1355 Host Bus Interface It is separate from the input clock CLKI and is typically driven by the host CPU system clock The address inputs AB 20 0 and the data bus DB 15 0 connect directly to the VR4121 address ADD 20 0 and data bus DAT 15 0 respectively MD4 must be set to select the proper endian mode upon reset M R memory register selects between memory or register access It may be connected to an address line allowing system address ADD21 to be connected to the M R line Chip Select CS must be driven low by LCDCS whenever the SED 1355 is accessed by the VR4121 WE1 connects to SHB the high byte enable signal from the VR4121 which in conjunction with address bit 0 allows byte steering of read and write operations WEO connects to WR the write enable signal from the VR4121 and must be driven low when the VR4121 bus is writing data to the SED1355 RD connects to RD the read enable signal from the VR4121 and must be driven low when the VR4121 bus is reading data from the SED1355 WAIT connects to LCDRDY and is a signal output from the SED1355 that indicates the VR4121 bus must wait until data is ready read cycle or accepted write cycle on the host bus Since VR4121 bus accesses to the SED1355 may occur asynchronously to the display update it is possible that contention may occur i
224. SED1355BOB ISA evaluation boards When hardware suspend mode is engaged the display is disabled and display buffer is inaccessible and the registers and LUT are inaccessible DevID aregistered device ID Suspend boolean flag to indicate which state to engage enter suspend mode when non zero and return to normal power when equal to zero Return Value ERR_OK operation completed with no problems 11 6 Porting LIBSE to a new target platform Building Epson applications like a simple HelloApp for a new target platform requires 3 things the HelloApp code the 1355HAL library and a some standard C functions portable ones are encapsu lated in our mini C library LIBSE HelloApp a HelloApp Source code C Library Functions LIBSE for embedded platforms 1355HAL Library Figure 11 1 Components needed to build 1355 HAL application Programming Notes and Examples Issue Date 99 04 27 SED1355 X23A G 003 05 Page 72 Epson Research and Development Vancouver Design Center For example when building HELLOAPP EXE for the x86 16 bit platform you need the HELLOAPP source files the 1355HAL library and its include files and some Standard C library functions which in this case would be supplied by the compiler as part of its run time library As this is a DOS EXE application you do not need to supply start up code that sets up the chip selects or interrupts etc What if you wanted to build the application for
225. Se to a higher value 5 pRegs 0x23 0x00 0000 0000 Register D Display Mode 8 BPP LCD enable Wi pRegs 0x0D 0x0D 0000 1101 Clear memory by filling 2 MB with 0 pMem DISP_MEM_OFFSET for lpCnt 0 lpCnt lt DISP_MEMORY_SIZE lpCnt pMem 0 pMem Draw a 100x100 red of the display rectangle in the upper left corner kk Si pMem DISP_MEM_OFFSET O y lt 100 y for pTmp for y pMem y 640L 0 x lt 100 x x pTmp Ox0c pImpt Init the HW cursor In this example the cursor memory wil immediately after display memory Why here Because it s 0 location to calculate and will not interfere with the hal Additionally easily from this location pRegs 0x30 CURSOR_START pImp pCursor pMem DISP_MEMORY_SIZE CURSOR_START Programming Notes and Examples Issue Date 99 04 27 0 ll be located an easy lf frame buffer the HW cursor can be turned into an ink layer quite 8192L SED1355 X23A G 003 05 Page 88 is transparent To do so The cursor is 2 bpp so a 64x64 cursor requires 64 4 64 1024 bytes of memory eL for lpCnt 0 lpCnt lt 1024 1pCnt pTmp OXAA pImp Set the first user definable cursor color to black and the second user definable cursor color to white Bi
226. T Display Utility Document Number X23A B 003 02 Copyright O 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 1355SPLT Display Utility X23A B 003 02 Issue Date 98 10 30 Epson Research and Development Page 3 Vancouver Design Center 1355SPLT 1355SPLT demonstrates SED1355 split screen capability by showing two different areas of display memory on the screen simultaneously Screen 1 shows horizontal bars and Screen 2 shows vertical bars Screen 1 memory is located at the start of the display buffer Screen 2 memory is located immedi ately after Screen in the display buffer On user input or elapsed time the line compare register value is changed to adjust the amount of area displayed on either screen The result is a movement up or down of screen 2 o
227. U1355B0C board supports a5 0V 1M x 16 symmetrical EDO DRAM 42 pin SOJ package This provides a 2M byte display buffer This board utilizes the MIPS ISA Interface of the SED1355 see the SED1355 Hardware Functional Specification document number X23A A 001 xx All required decode logic is provided through a 22V 10 PAL U4 socketed 6 5 Clock Input Support The SED1355 supports up to a 40 0Mhz input clock frequency A 40 0MHz oscillator U2 socketed is provided on the SDU1355 board as the clock CLKI source 6 6 Monochrome LCD Panel Support The SED1355 supports 4 and 8 bit dual and single monochrome passive LCD panels All necessary signals are provided on the 40 pin ribbon cable header J6 The interface signals on the cable are alter nated with grounds to reduce crosstalk and noise Refer to Table 3 1 LCD Signal Connector J6 on page 9 for connection information 6 7 Color Passive LCD Panel Support SED1355 X23A G 004 04 The SED1355 directly supports 4 8 and 16 bit dual and single color passive LCD panels All the necessary signals are provided on the 40 pin ribbon cable header J6 The interface signals on the cable are alternated with grounds to reduce crosstalk and noise Refer to Table 3 1 LCD Signal Connector J6 on page 9 for connection information SDU1355B0C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 98 10 30 Epson Research and Development Page 15 Vancouver Design Center 6 8 Col
228. Z This is a multi purpose pin For SH 3 SH 4 Bus this pin inputs the write enable signal for the lower data byte WEO For MC68K Bus 1 this pin must be connected to Von For MC68K Bus 2 this pin inputs the bus size bit 0 SIZO For Generic Bus this pin inputs the write enable signal for the lower data byte WEO For MIPS ISA Bus this pin inputs the memory write signal MEMW For Philips PR31500 31700 Bus this pin inputs the memory write command WE For Toshiba TX3912 Bus this pin inputs the memory write command WE For PowerPC Bus this pin inputs the Transfer Size 1 signal TSIZ1 For PC Card PCMCIA Bus this pin inputs the write enable signal WE See Host Bus Interface Pin Mapping for summary See the respective AC Timing diagram for detailed functionality Hardware Functional Specification Issue Date 99 05 18 SED1355 X23A A 001 11 Page 28 Epson Research and Development Vancouver Design Center Table 5 1 Host Interface Pin Descriptions Continued Pin Name Type Pin Cell RESET State Description WAIT 15 TS2 The active polarity of the WAIT output is configurable the state of MD5 on the rising edge of RESET defines the active polarity of WAIT see Summary of Configuration Options For SH 3 Bus this pin outputs the wait request signal WAIT MD5 must be pulled low during reset by the internal pull down resistor For SH 4 Bus t
229. a signal output from the SED1355 that indicates the PC Card bus must wait until data is ready read cycle or accepted write cycle on the host bus Since PC Card bus accesses to the SED1355 may occur asynchronously to the display update it is possible that contention may occur in accessing the SED1355 internal registers and or display buffer The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete For PC Card applications this signal should be set active low using the MD5 configuration input e The Bus Start BS signal is not used for the PC Card host bus interface and should be tied high connected to Vpp The RESET active low input of the SED1355 may be connected to the PC Card RESET active high using an inverter SED1355 Interfacing to the PC Card Bus X23A G 005 05 Issue Date 99 05 05 Epson Research and Development Page 13 Vancouver Design Center 4 PC Card to SED1355 Interface 4 1 Hardware Description The SED1355 is designed to directly support a variety of CPUs providing an interface to each processor s unique local bus However in order to provide support for processors not having an appropriate local bus the SED1355 supports a specific PC Card interface The SED1355 provides a glueless interface to the PC Card bus except for the following e The RESET signal on the SED1355 is active low and must be inverted to support the active high RESET p
230. able 6 4 Table 6 5 Table 7 1 Table 7 2 Table 7 3 Table 7 4 Table 7 5 Table 7 6 Table 7 7 Table 7 8 Table 7 9 Table 7 10 Table 7 11 Table 7 12 Table 7 13 Table 7 14 Table 7 15 Table 7 16 Table 7 17 Table 7 18 Table 7 19 Table 7 20 Table 7 21 Table 7 22 Table 7 23 Table 7 24 Table 7 25 Table 7 26 Hardware Functional Specification Issue Date 99 05 18 Page 7 List of Tables Host Interface Pin Descripti0ns ee 23 Memory Interface Pin Descriptions 0 0 0 0 a 29 LCD Interface Pin Descriptions ee 31 CRT Interface Pin Descriptions 2 2 2 0 00000 0 2000000000022 31 Miscellaneous Interface Pin Descriptions 2 2 2 20 00 0000 000000 32 Summary of Power On Reset Options 0000 eee ee ee eee 33 CPU Interface Pin Mappings cocos cc bE RY Pee e aap eae ee ea a ee 34 Memory Interface Pin Mapping 35 LCD Interface Pin Mapping 35 Absolute Maximum Ratings 2 2 2 ee 37 Recommended Operating Conditions s 2 0 00 0000 00 pee eee 37 Electrical Characteristics for VDD 5 0V typical 2 2 ee 38 Electrical Characteristics for VDD 3 3V typical 2 a 39 Electrical Characteristics for VDD 3 0V typical een 40 SHA DN da cers e Ree he ety she A fe ee Bie Bea ae 42 SH 3 TIMIS soes ep e aae e A dd a ti AR 44 MG otmen iz BA A Be cele ae Maa ARA 46 MC68030 Timing EE a A A a A e 48 PC Card Timing ia RR IA E EI AS RIA E
231. able 8 13 RAS to CAS Delay Timing Select REG 22h bit 4 Nrcp RAS to CAS Delay treo 0 2 2 7 7 7 Hardware Functional Specification Issue Date 99 05 18 Epson Research and Development Vancouver Design Center bits 3 2 bits 1 0 bit O RAS Precharge Timing Value Npp Bits 1 0 Minimum Memory Timing for RAS precharge These bits select the DRAM RAS Precharge timing parameter tgp These bits specify the number Npp of MCLK periods Ty used to create tgp see the following formulae Note these formulae assume an MCLK duty cycle of 50 5 Npp 1 1 5 2 if trp Tm lt 1 if 1 lt tap Ty lt 1 45 if tRp Ty 2 1 45 The resulting tgc is related to Npp as follows trp Nep 0 5 Tu trp Nprp TM for all other Reserved These bits must be set to 0 if FPM refresh cycle and Npp 1 or 2 Table 8 14 RAS Precharge Timing Select Page 117 REG 22h bits 3 2 Npp RAS Precharge Width tpp 00 2 2 01 1 5 1 5 10 1 1 11 Reserved Reserved Optimal DRAM Timing The following table contains the optimally programmed values of Ngc Npp and Ngcp for different DRAM types at maximum MCLK frequencies Table 8 15 Optimal Nee Npp and Nrcp values at maximum MCLK frequency DRAM Speed Tu Nac Nee Naco DRAM Type ns ns MCLK MCLK MCLK 50 25 4 1 5 2 EDO 60 30 4 1 5 2 70
232. able shows example values for 2 bpp color mode Table 4 3 Example LUT Values for 2 Bpp Color Mode Index Red Green Blue 00 00 00 00 01 70 70 70 02 AO AO AO 03 FO FO FO 04 FF SF Indicates unused entries in the LUT SED1355 X23A G 003 05 Page 18 SED1355 X23A G 003 05 4 bpp color Epson Research and Development Vancouver Design Center When the SED1355 is configured for 4 bpp color mode the first 16 entries in the LUT are used Each byte in the display buffer contains two adjacent pixels The upper and lower nibbles of the byte are used as indices into the LUT The following table shows LUT values that will simulate those of a VGA operating in 16 color mode Table 4 4 Suggested LUT Values to Simulate VGA Default 16 Color Palette Index Red Green Blue 00 00 00 00 01 00 00 0A 02 00 0A 00 03 00 0A 0A 04 0A 00 00 05 DA 00 0A 06 0A 0A 00 07 DA OA OA 08 00 00 00 09 00 00 OF 0A 00 OF 00 0B 00 OF OF DC OF 00 00 0D OF 00 OF 0E OF OF 00 OF OF OF OF 10 FF se Indicates unused entries in the LUT Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 19 Vancouver Design Center S bpp color When the SED1355 is configured for 8 bpp color mode all 256 entries in the LUT are used Each byte in display buffer corresponds to one pixel and is used as an index value in
233. able through seGet MemSize int seGetLastUsableByte int DevID DWORD pLastByte Description Calculates the offset of the last byte in the display buffer which can be used by appli cations Locations following LastByte are reserved for system use Items such as the half frame buffer hardware cursor and ink layer will be located in memory from GetLastUsableByte 1 to the end of memory It is assumed that the registers will have been initialized before calling seGetLastUs ableByte Factors such as the half frame buffer and hardware cursor ink layer being enabled dynamically alter the amount of display buffer available to an appli cation Call seGetLastUsableByte any time the true end of usable memory is required Parameters DevID registered device ID pLastByte pointer to a DWORD to receive the offset to the last usable byte of display buffer Return Value ERR_OK operation completed with no problems Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 51 Vancouver Design Center int seGetBytesPerScanline int DevID UINT pBytes Description Determines the number of bytes per scan line of the current display mode It is assumed that the registers have already been correctly initialized before seGetBytes PerScanline is called The number of bytes per scanline calculation includes the value in the offset register For rotated modes the return value will be either 1024 8 bpp
234. after A 20 0 M R becomes valid whichever one is later SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Vancouver Design Center 7 1 5 PC Card Interface Timing t1 t2 EE Page 49 CLK I A 20 0 M R A CE 1 0 CS OE WE WAIT D 15 0 write t9 t10 t11 D 15 0 read Note Figure 7 5 PC Card Timing The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected Hardware Functional Specification Issue Date 99 05 18 SED1355 X23A A 001 11 Page 50 Epson Research and Development Vancouver Design Center Table 7 5 PC Card Timing 3 0V 5 0V Symbol Parameter Min Max Min Max Units ti Clock period 20 20 ns t2 Clock pulse width high 6 6 ns t3 Clock pulse width low 6 6 ns t4 A 20 0 M R setup to first CLK where CS 0 and either OE 0 or 10 10 nS WE 0 t5 A 20 0 M R hold from rising edge of either OE or WE 0 0 ns t6 CS hold from rising edge of either OE or WE 0 0 ns t71 Falling edge of either OE or WE to WAIT driven low 0 15 0 10 ns t8 Rising edge of either OE or WE to WAIT tri state 5 25 25 10 ns t9 D 15 0 setup to third CLK where CS 0 and WE 0 write cycle 10 10 ns t10 D 15 0 hol
235. aia e ae a REOTerencesS o ee La 6 1 Documents 6 2 Document Sources 7 Technical Support 7 1 EPSON LCD CRT Controllers SED1355 7 2 NEC Electronics Inc VR4102 VR4111 Interfacing to the NEC VR4102 VR4111 Microprocessors Issue Date 99 05 05 Page 3 SED1355 X23A G 007 05 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 Interfacing to the NEC VR4102 VR4111 Microprocessors X23A G 007 05 Issue Date 99 05 05 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping e 10 Table 4 1 Summary of Power On Reset Oppons 13 List of Figures Figure 2 1 NEC VR4102 VR4111 Read Write Cycles o o ee 9 Figure 4 1 NEC VR4102 VR4111 to SED1355 Configuration Schematic 12 Interfacing to the NEC VR4102 VR4111 Microprocessors SED1355 Issue Date 99 05 05 X23A G 007 05 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 Interfacing to the NEC VR4102 VR4111 Microprocessors X23A G 007 05 Issue Date 99 05 05 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment necessary to provide an interface between the SED1355 Embedded RAMDAC LCD CRT Controller and the NEC Vr4102 uPD30102 or Vr4111 uPD3
236. al drive displays e Direct support for 9 12 bit TFT D TFD 18 bit TFT D TFD is supported up to 64K color depth 16 bit data e Embedded RAMDAC with direct analog CRT drive e Simultaneous display of CRT and passive or TFT D TFD panels e Maximum resolution of 800x600 pixels at a color depth of 16 bpp Display Modes e 1 2 4 8 16 bit per pixel bpp support on LCD CRT e Up to 16 shades of gray using FRM on monochrome passive LCD panels e Up to 4096 colors on passive LCD panels e Up to 64K colors on active matrix TFT D TFD LCD panels and CRT in 16 bpp modes e Split Screen Display allows two different images to be simultaneously viewed on the same display e Virtual Display Support displays images larger than the display size through the use of panning e Double Buffering multi pages provides smooth animation and instantaneous screen update e Hardware Portrait Mode direct hardware 90 rotation of display image for portrait mode display e Acceleration of screen updates by allocating full display memory bandwidth to CPU e Hardware 64x64 pixel 2 bit cursor or full screen 2 bit ink layer Clock Source e Single clock input for both pixel and memory clocks e Memory clock can be input clock or input clock 2 providing flexibility to use CPU bus clock as input e Pixel clock can be memory clock or memory clock 2 or memory clock 3 or memory clock 4 Power Down Modes e Software power save mode e LCD powe
237. alternate FRM scheme may be used The alternate FRM scheme may produce more visually appealing output The following table shows the recommended alternate FRM scheme values Table 8 19 Recommended Alternate FRM Scheme Panel Mode Register Value Single Passive 0000 0000 or 1111 1111 Dual Passive w Half Frame Buffer Enabled 0000 0000 or 1111 1010 Dual Passive w Half Frame Buffer Disabled 11111111 SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 123 Vancouver Design Center 9 Display Buffer The system addresses the display buffer through the CSF M R and AB 20 0 input pins When CS 0 and M R 1 the display buffer is addressed by bits AB 20 0 See the table below Table 9 1 SED1355 Addressing CS M R Access Register access 0 0 e REG 00h is addressed when AB 5 0 0 e REG 01h is addressed when AB 5 0 1 e REG n is addressed when AB 5 0 n 0 1 Memory access the 2M byte display buffer is addressed by AB 20 0 1 X SED1355 not selected The display buffer address space is always 2M bytes However the physical display buffer may be either 512K bytes or 2M bytes see Summary of Configuration Options The display buffer can contain an image buffer one or more Ink Cursor buffers and a half frame buffer A 512K byte display buffer is replicated in the 2M byte address space see the figure below
238. ameter Min Max Units Tosc Input Clock Period 13 3 ns town Input Clock Pulse Width High 5 4 ns Loun Input Clock Pulse Width Low 5 4 ns t Input Clock Fall Time 10 90 5 ns t Input Clock Rise Time 10 90 5 ns SED1355 X23A A 001 11 Hardware Functional Specification Issue Date 99 05 18 Epson Research and Development Vancouver Design Center 7 1 10 Power PC Interface Timing e g MPC8xx MC68040 Coldfire Page 61 A 11 31 RD WR TSIZ 0 1 M R CS TS TA Bl D O 15 write D 0 15 read CLKOUT i t1 t2 t3 a t4 t5 t6 t7 E id t8 t9 t10 t11 t12 t13 Mi gt A t14 t15 t16 E id gt t17 t18 j S p O t19 t20 lt Figure 7 12 Power PC Timing The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected Hardware Functional Specification Issue Date 99 05 18 SED1355 X23A A 001 11 Page 62 Epson Research and Development Vancouver Design Center Table 7 12 Power PC Timing 3 0V 5 0V Symbol Parameter Min Max Min Max Units D Clock period 25 20 ns t2 Clock pulse width low 6 6 ns D Clock pulse width high 6 ns t4 AB 11 31 RD WR TSIZ 0 1 M R setup 10 10 ns t5 AB 11 31 RD WR TSIZ 0 1 M R hold 0 0 ns t6 CS set
239. an SH 3 target one not running DOS Before you can build that application to load onto the target you need to build a C library for the target that contains enough of the Standard C functions like sprintf and strcpy to let you build the application Epson supplies the LIBSE for this purpose but your compiler may come with one included You also need to build the 1355HAL library for the target This library is the graphics chip dependent portion of the code Finally you need to build the final application linked together with the libraries described earlier The following examples assume that you have a copy of the complete source code for the SED1355 utilities including the nmake makefiles as well as a copy of the GNU Compiler v2 7 96q3a for Hitachi SH3 These are available on the Epson Electronics America Website at http www eea epson com 11 6 1 Building the LIBSE library for SH3 target example SED1355 X23A G 003 05 In the LIBSE files there are three main types of files e C files that contain the library functions e assembler files that contain the target specific code e makefiles that describe the build process to construct the library The C files are generic to all platforms although there are some customizations for targets in the form of ifdef LCEVBSH3 code the ifdef used for the example SH3 target Low Cost Eval Board SH3 The majority of this code remains constant whichever target you build for The assembler files
240. an be adjusted by R29 to supply an output voltage from 14V to 23V and is enabled disabled by the SED1355 control signal LCDPWR Determine the panel s specific power requirements and set the potentiometer accordingly before connecting the panel 6 12 Adjustable LCD Panel Positive Power Supply Most passive LCD passive color panels and most single monochrome 640x480 passive LCD panels require a positive power supply to provide between 23V and 40V 1 45mA For ease of imple mentation such a power supply has been provided as an integral part of this design The signal VDDH can be adjusted by R23 to provide an output voltage from 23V to 40V and is enabled disabled by the SED 1355 control signal LCDPWR Determine the panel s specific power requirements and set the potentiometer accordingly before connecting the panel SDU1355B0C Rev 1 0 ISA Bus Evaluation Board User Manual SED1355 Issue Date 98 10 30 X23A G 004 04 Page 16 Epson Research and Development Vancouver Design Center 6 13 CPU Bus Interface Header Strips All of the CPU Bus interface pins of the SED1355 are connected to the header strips H1 and H2 for easy interface to a CPU or bus other than ISA Refer to Table 4 1 CPU BUS Connector H1 Pinout on page 10 and Table 4 2 CPU BUS Connector H2 Pinout on page 11 for specific settings Note These headers only provide the CPU Bus interface signals from the SED1335 When another host bus interface is sel
241. and Examples Issue Date 99 04 27 Epson Research and Development Page 33 Vancouver Design Center 7 Hardware Cursor 7 1 Introduction 7 2 Registers The SED1355 provides hardware support for a cursor or an ink layer These features are mutually exclusive and therefore only one or the other may be active at any given time A hardware cursor improves video throughput in graphical operating systems by off loading much of the work typically assigned to software Take the actions which must be performed when the user moves the mouse On a system without hardware support the operating system must restore the area under the current cursor position then save the area under the new location and finally draw the cursor shape Contrast that with the hardware assisted system where the operating system must simply update the cursor X and cursor Y position registers An ink layer is used to support stylus or pen input Without an ink layer the operating system would have to save an area possibly all of the display buffer where pen input was to occur After the system recognized the user entered characters the display would have to be restored and the characters redrawn in a system font With an ink layer the stylus path is drawn in the ink layer where 1t overlays the displayed image After character recognition takes place the display is updated with the new characters and the ink layer is simply cleared There is no need to save and restore display d
242. and variables for use enable cursor seCursorOn Enable the cursor seCursorOff Disable the cursor seGetCursorStartAddr SE the offset of the first byte of cursor memory in the display buffer landscape seMoveCursor Move the cursor to the x y position specified seSetCursorColor Sets the specified cursor color entry 0 1 to color seSetCursorPixel Draw one pixel into the cursor memory at x y from top left corner of cursor seDrawCursorLine Draw a line into the cursor memory from x1 y1 to x2 y2 in specified color seDrawCursorRect Draw a rectangle into the cursor memory from x1 y1 to x2 y2 in specified color seDrawCursorEllipse Draw an ellipse into the cursor memory centered at xc yc of radius xr yr in specified color seDrawCursorCircle Draw a circle into the cursor memory centered at x y of radius r in specified color Programming Notes and Examples SED1355 Issue Date 99 04 27 X23A G 003 05 Page 46 Epson Research and Development Vancouver Design Center Table 11 1 HAL Functions Continued Function Description selnitink Initialize the Ink layer variables and registers enable ink layer selnkOn Enables the Ink layer selnkOff Disables the Ink layer seGetInkStartAddr Determine the offset of the first byte of Ink layer memory in the display buffer landscape mode seSetinkColor Sets the specified Ink layer color entry 0 1 to color seSetInkPixel Draw one pixel into the Ink layer memory
243. andwidth during non display period f MCLK 6 Mb s Bandwidth during display period The amount of time taken up by display refresh fetches is a function of the color depth and the display type Below is a table of the number of MCLKs required for various memory fetches to display 16 pixels Assuming Ngc 4MCLKs Table 14 4 Number of MCLKs required for various memory access Memory access Number of MCLKs Half Frame Buffer monochrome 7 Half Frame Buffer color 11 Display 1 bpp 4 Display 2 bpp 5 Display 4 bpp T Display 8 bpp 11 Display 16 bpp 19 CPU 4 SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 145 Vancouver Design Center Table 14 5 Total MCLKs taken for Display refresh MCLKs for Display Refresh Display 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp e Single Panel e CRT e Dual Monochrome Color Panel with Half Frame Buffer Disabled 4 5 7 41 19 Simultaneous CRT Single Panel e Simultaneous CRT Dual Monochrome Color Panel with Half Frame Buffer Disabled Dual Monochrome Panel with Half Frame Buffer Enabled Simultaneous CRT Dual Monochrome Panel with Half Frame 11 12 14 18 26 Buffer Enable Dual Color Panel with Half Frame Buffer Enabled 15 16 18 22 30 Average Bandwidth Bandwidth during display period MIN bandwidth during non display period B C
244. appe ri e 9 Interfacing to the PC Card Bus SED1355 Issue Date 99 05 05 X23A G 005 05 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 Interfacing to the PC Card Bus X23A G 005 05 Issue Date 99 05 05 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 PC Card Host Bus Interface Pin Mapping aaa aa 11 Table 4 1 Summary of Power On Reset Oppons e ee 15 Table 4 2 Register Memory Mapping for Typical Implementation 16 List of Figures Figure 2 1 PC Card Read Cycle 0 0002 a e y a ee ee 9 Figure 2 2 PC Card Write Cycle 10 Figure 4 1 Typical Implementation of PC Card to SED1355 Interface 14 Interfacing to the PC Card Bus SED1355 Issue Date 99 05 05 X23A G 005 05 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 Interfacing to the PC Card Bus X23A G 005 05 Issue Date 99 05 05 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to provide an interface between the SED1355 Embedded RAMDAC LCD CRT Controller and the PC Card PCMCIA bus The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Electro
245. arch and Development Page 15 Vancouver Design Center 7 References 7 1 Documents e Philips Electronics PR31500 PR31700 Preliminary Specifications Epson Research and Development Inc SED1355 Hardware Functional Specification Document Number X23A A 001 xx e Epson Research and Development Inc SDUI3553B0C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X23A G 004 xx e Epson Research and Development Inc SED1355 Programming Notes and Examples Document Number X23A G 003 xx 7 2 Document Sources e Philips Electronics Website http www us2 semiconductors philips com e Epson Electronics America Website http www eea epson com Interfacing to the Philips MIPS PR31500 PR31700 Processor SED1355 Issue Date 99 05 05 X23A G 001 06 Page 16 8 Technical Support 8 1 EPSON LCD CRT Controllers SED1355 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http www epson co jp Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 8 2 Philips MIPS
246. ardware Cursor e 36 TA AEXAMPIES 7 ot At a a RE AAA AL st S 8 Hardware Rotation lt lt Serge r a o a A AA rd eS 37 8 1 Introduction To Hardware Rotation Al 82 SED1355 Hardware Rotation 2 ee Al Programming Notes and Examples SED1355 Issue Date 99 04 27 X23A G 003 05 Page 4 Epson Research and Development Vancouver Design Center 8 3 Registers 37 8 4 Limitations 38 8 5 Examples 39 9 CRT Considerations aida ale ee Barns Car She Aa eee coh te eee By aed ek ee ds ee a 41 9 1 Introduction Sai Gh L 41 ON ERENNERT wee ta 41 9 1 2 Simultaneous Display 0000000 2 ee ee ee 41 10 Identifying the SED1355 o 42 11 Hardware Abstraction Layer HAL 2 4 43 11 1 Introduction e 43 11 2 Contents of the HAL_STRUCT 43 11 3 Using the HAL library 44 11 4 API for 1355HAL 44 11 5 Initialization 46 11 5 1 General HAL Sabin e da a e A e ot A 49 11 5 2 Advanced HAL Functions 0 eee 53 11 5 3 Register Memory Access 0 e aa aa aa eeh ee 55 11 5 4 Color Manipulation rr A A A 59 VALS Drawing csta seanna e A RS dd ed A 61 11 36 Hardware Cursor md Sa Se A ee ee ea AA ie a as 63 LESA mk Edye di AR A A a de 67 15 8 Rome ere E a a BU A e a e e 71 11 6 Porting LIBSE to a new target platform BOA A Ee Oe en ed eet ea 71 11 6 1 Building the LIBSE library for SH3 target EE Ras AR Me ete Beas 7
247. are mapped in the lower PC Card memory address space starting at zero The display buffer requires 2M bytes and is mapped in the third and fourth megabytes of the PC Card address space ranging from 200000h to 3FFFFFh A typical implementation as shown in Figure 4 1 Typical Implementation of PC Card to SED1355 Interface on page 14 has Chip Select CS connected to ground always enabled and the Memory Register select pin M R connected to address bit A21 This provides the following decoding Table 4 2 Register Memory Mapping for Typical Implementation CS M R A21 Address Range Function Internal Register 9 DETE PREEN Set decoded 1 20 0000h 3F FFFFh Display Buifer decode The PC Card socket provides 64M byte of address space Without further resolution on the decoding logic M R connected to A21 the entire register set is aliased for every 64 byte boundary within the specified address range above Since address bits A 25 22 are ignored the SED1355 registers and display buffer are aliased 16 times Note If aliasing is not desirable the upper addresses must be fully decoded Interfacing to the PC Card Bus Issue Date 99 05 05 Epson Research and Development Page 17 Vancouver Design Center 5 Software Test utilities and Windows CE v2 0 display drivers are available for the SED1355 Full source code is available for both the test utilities and the drivers The test utilities are config
248. at techpubs erd epson com 1 2 Overview Description The SED1355 is a color monochrome LCD CRT graphics controller interfacing to a wide range of CPUs and display devices The SED1355 architecture is designed to meet the low cost low power requirements of the embedded markets such as Mobile Communications Hand Held PCs and Office Automation The SED1355 supports multiple CPUs all LCD panel types CRT and additionally provides a number of differentiating features Products requiring a Portrait mode display can take advantage of the SwivelView feature Simultaneous Virtual and Split Screen Display are just some of the display modes supported while the Hardware Cursor Ink Layer and the Memory Enhancement Registers offer substantial performance benefits These features combined with the SED1355 s Operating System independence make it an ideal display solution for a wide variety of applications Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 12 2 Features 2 1 Memory Interface Epson Research and Development Vancouver Design Center es 16 bit DRAM interface EDO DRAM up to 40MHz data rate 80M bytes sec FPM DRAM up to 25MHz data rate 50M bytes sec e Memory size options 512K bytes using one 256Kx16 device 2M bytes using one 1Mx16 device e Performance Enhancement Register to tailor the memory control output timing for the DRAM device 2 2 CPU Interface e Suppor
249. at x y from top left corner of cursor seDrawInkLine Draw a line into the Ink layer memory from x1 y1 to x2 y2 in specified color seDrawInkRect Draw a rectangle into the Ink layer memory from x1 y1 to x2 y2 in specified color seDrawInkEllipse Draw an ellipse into the Ink layer memory centered at xc yc of radius xr yr in specified color seDrawInkCircle seSWSuspend Draw a circle into the Ink layer memory centered at x y of radius r in specified color Control SED1355 SW suspend mode enable disable seHWSuspend Control SED1355 HW suspend mode enable disable SED1355 X23A G 003 05 11 5 Initialization The following section describes the HAL functions dealing with initialization of the SED1355 Typically a programmer will only use the calls seRegisterDevice and seSetInit int seRegisterDevice const LPHAL_STRUC IpHallnfo int pDevice Description This function registers the SED1355 device parameters with the HAL library The device parameters include address range register values desired frame rate etc and are stored in the HAT STRUCT structure pointed to by IpHalInfo Additionally this routine allocates system memory as address space for accessing registers and the display buffer Parameters IpHallnfo pointerto HAL_STRUCT information structure as defined in appcfg h HalInfo pDevice pointer to the integer to receive the device ID Return Value ERR_OK operati
250. ata thus providing faster throughput The SED1355 hardware cursor ink layer supports a 2 bpp four color overlay image Two of the available colors are transparent and invert The remaining two colors are user definable There are a total of eleven registers dedicated to the operation of the hardware cursor ink layer Many of the registers need only be set once Others such as the positional registers will be updated frequently REG 27h Ink Cursor Control Register Ink Cursor Ink Cursor Cursor High Cursor High Cursor High Cursor High Mode Mode n a n a Threshold Threshold Threshold Threshold bit 1 bit O bit 3 bit 2 bit 1 bit O The Ink Cursor mode bits determine if the hardware will function as a hardware cursor or as an ink layer See Table 7 1 for an explanation of these bits Table 7 1 Ink Cursor Mode Register 27h Operating bit 7 bit 6 Mode 0 0 Inactive 0 1 Cursor 1 0 Ink 1 1 Reserved When cursor mode is selected the cursor image is always 64x64 pixels Selecting an ink layer will result in a large enough area to completely cover the display Programming Notes and Examples SED1355 Issue Date 99 04 27 X23A G 003 05 Page 34 Epson Research and Development Vancouver Design Center The cursor threshold bits are used to control the Ink Cursor FIFO depth to sustain uninterrupted display fetches REG 28h Cursor X Position Register 0 Cursor X Pos
251. ate 98 10 30 X23A B 004 03 Page 4 Epson Research and Development Vancouver Design Center Usage PC platform at the prompt type 1355virt w a Embedded platform execute 1355virt and at the prompt type the command line argument Where no argument panning and scrolling is performed manually w for manual mode specifies the width of the virtual display which must be a multiple of 8 and less than 2048 the default width is double the physical panel width the maximum height is based on the display memory a panning and scrolling is performed automatically 17 displays the help screen The following keyboard commands are for navigation within the program Manual mode T scrolls up y scrolls down pans to the left gt pans to the right CTRL scrolls up several lines CTRL scrolls down several lines CTRL pans to the left several lines CTRL pans to the right several lines HOME moves the display screen so that the upper right corner of the virtual screen shows in the display END moves the display screen so that the lower left corner of the virtual screen shows in the display Automatic and Manual modes b changes the color depth bit per pixel ESC exits 1355VIRT SED1355 1355VIRT Display Utility X23A B 004 03 Issue Date 98 10 30 Epson Research and Development Page 5 Vancouver Design Center 1355VIRT Example Comments 1 Type 1355virt a to automatically pan and scroll 2 Press b to change the bit
252. ate a Windows CE image file NK BIN SED1355 X23A E 001 04 Page 8 Epson Research and Development Vancouver Design Center Example Installation Installation for Hitachi D9000 and ETMA ODO Follow the procedures from your Hitachi D9000 or ETMA ODO manual and download the following to the D9000 platform 1 Download SEIKO EPSON s common interface FPGA code ODO RBF to the EEPROM of the D9000 system 2 Download the Windows CE binary ROM image NK BIN to the FLASH memory of the D9000 system Installation for CEPC Environment Windows CE v2 0 can be loaded on a PC using a floppy drive or a hard drive The two methods are described below 1 To load CEPC from a floppy drive a Create a DOS bootable floppy disk b Edit CONFIG SYS on the floppy disk to contain the following line only device a himem sys c Edit AUTOEXEC BAT on the floppy disk to contain the following lines mode com1 9600 n 8 1 loadcepc B 9600 C 1 D 2 c wince release nk bin d Copy LOADCEPC EXE from c wince public common oak bin to the bootable floppy disk e Confirm that NK BIN is located in c wince release f Reboot the system from the bootable floppy disk 2 To load CEPC from a hard drive a Copy LOADCEPC EXE to the root directory of the hard drive b Edit CONFIG SYS on the hard drive to contain the following line only device c himem sys c Edit AUTOEXEC BAT on the hard drive to contain the following lines mode com1 9600 n
253. awEllipse int DeviD long xc long yc long xr long yr DWORD Color BOOL SolidFill Description This routine draws an ellipse with the center located at xc yc The xr and yr param eters specify the x any y radii in pixels respectively The ellipse will be drawn in the color specified in Color Parameters DevID registered device ID xc yc The center location of the ellipse in pixels xr horizontal radius of the ellipse in pixels yr vertical radius of the ellipse in pixels Color The color to draw the ellipse At 1 2 4 and 8 bpp Color is an index into the Look Up Table At 15 16 bpp Color defines the color directly i e rrrrrggggggbbbbb for 16 bpp SolidFill unused Return Value ERR_OK operation completed with no problems Note The SolidFill argument is currently unused and is included for future considerations int seDrawCircle int DeviD long xc long yc long Radius DWORD Color BOOL SolidFill Description This routine draws an circle with the center located at xc yc and a radius of Radius The circle will be drawn in the color specified in Color Parameters DevID registered device ID XC yc The center of the circle in pixels Radius the circles radius in pixels Color The color to draw the ellipse At 1 2 4 and 8 bpp Color is an index into the Look Up Table At 15 16 bpp Color defines the color directly i e rrrrrggggggbbbbb for 16 bpp SolidFill unused R
254. ay in the structure are all the registers defined in the SED1355 Hardware Functional Specification document number X23A A 001 xx Using the 1355CFG EXE utility you can adjust the content of the registers contained in HAL_STRUCT to allow for different LCD panel timing values and other default settings used by the HAL In the simplest case the program only calls a few basic HAL functions and the contents of the HAL_STRUCT are used to setup the SED 1355 for operation see Section 11 6 3 Building a complete application for the target example on page 73 Programming Notes and Examples SED1355 Issue Date 99 04 27 X23A G 003 05 Page 44 Epson Research and Development Vancouver Design Center 11 3 Using the HAL library To utilize the HAL library the programmer must include two h files in their code Hal h contains the HAL library function prototypes and structure definitions and appcfg h contains the instance of the HAL_STRUCT that is defined in Hal h and configured by 1355CFG EXE Additionally hal_regs h can be included if the programmer intends to change the SED1355 registers directly using the seGetReg or seSetReg functions For a more thorough example of using the HAL see Section 12 1 1 Sample code using the SED1355 HAL APT on page 77 Note Many of the HAL library functions have pointers as parameters The programmer should be aware that little validation of these pointers is performed so i
255. bit per pixel data from Image Buffer Figure 11 1 1 Bit per pixel Monochrome Mode Data Output Path 2 Bit per pixel Monochrome Mode Green Look Up Table 256x4 e Se 4 bit Grey Data 02 10 03 11 az FC FD FE FF 2 bit per pixel data from Image Buffer Figure 11 2 2 Bit per pixel Monochrome Mode Data Output Path Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Epson Research and Development Vancouver Design Center 4 Bit per pixel Monochrome Mode 4 bit per pixel data from Image Buffer Green Look Up Table 256x4 t 0000 t 0001 t0010 t0011 t0100 10101 10110 10111 1000 1001 1010 1011 1100 1101 1110 1111 Figure 11 3 4 Bit per pixel Monochrome Mode Data Output Path Hardware Functional Specification Issue Date 99 05 18 4 bit Grey Data Page 129 SED1355 X23A A 001 11 Page 130 Epson Research and Development Vancouver Design Center 11 2 Color Modes 1 Bit per pixel Color Mode Red Look Up Table 256x4 00 lo 4 bit Red Data 01 J Cid gt 0 1 Green Look Up Table 256x4 00 4 bit Green Data 01 d Blue Look Up Table 256x4
256. bits are the start address value The following pans to the right by one pixel in 4 bpp display mode 1 This is a pan to the right Increment pan_value pan_value pan_value 1 2 Mask off the values from pan_value for the pixel panning and start address register portions In this case 4 bpp the lower two bits are the pixel panning value and the upper bits are the start address pixel_pan pan_value AND 3 start_address pan_value SHR 3 the fist two bits of the shift account for the pixel_pan the last bit of the shift converts the start_address value from bytes to words 3 Write the pixel panning and start address values to their respective registers using the proce dure outlined in the registers section Example 4 Scrolling Up and Down To scroll down increase the value in the Screen Display Start Address Register by the number of words in one virtual scan line To scroll up decrease the value in the Screen 1 Display Start Address Register by the number of words in one virtual scan line Programming Notes and Examples SED1355 Issue Date 99 04 27 X23A G 003 05 Page 28 Epson Research and Development Vancouver Design Center Example 5 Scroll down one line for a 16 color 640x480 virtual image using a 320x240 single panel LCD 1 To scroll down we need to know how many words each line takes up At 16 colors 4 bpp each byte contains two pixels so each word contains 4 pixels offset_words pixels_per_line
257. bus interface signals assume their selected configuration For details on SED1355 configuration see Section 4 3 SED1355 Hardware Configuration on page 18 Note At reset the Host Interface Disable bit in the Miscellaneous Disable Register REG 1Bh bit 7 is set to 1 This means that only REG 1Ah read only and REG 1Bh are accessible until a write to REG 1Bh sets bit 7 to 0 making all regis ters accessible When debugging a new hardware design this can sometimes give the appearance that the interface is not working so it is important to remember to clear this bit before proceeding with debugging 3 1 PowerPC Host Bus Interface Pin Mapping The following table shows the functions of each host bus interface signal Table 3 1 PowerPC Host Bus Interface Pin Mapping pin Names PowerPC AB 20 0 A 11 31 DB 15 0 D 0 15 WEIS BI M R External Decode CS External Decode BUSCLK CLKOUT BS TS RD WR RD WR RD TSIZO WEOR TSIZ1 WAIT TA RESET RESET Interfacing to the Motorola MPC821 Microprocessor Issue Date 99 05 05 SED1355 X23A G 008 03 Page 14 Epson Research and Development Vancouver Design Center 3 2 PowerPC Host Bus Interface Signals SED1355 X23A G 008 03 The interface requires the following signals BUSCLK is a clock input which is required by the SED1355 host bus interface It is separate from the input clock CLKTI and is typically driven by the
258. by 4 pixels 1 With portrait mode enabled the x and y control is rotated as well Simply swap the x and y co ordinates and calculate as if the display were not rotated Calculate the new start address and pixel pan values BytesPerScanline 1024 PixelPan newX amp 01h StartAddr newY BytesPerScanline 2 newX amp FFFEh gt gt 1 Write the start address during the display enabled portion of the frame a loop waiting for vertical non display b7 of register OAh high do register ReadRegister OAh while 80h register amp 80h b Loop waiting for the end of vertical non display do register ReadRegister 0Ah while 80h register amp 80h c Write the new start address SetRegister REG_SCRN1_DISP_START_ADDRO BYTE dwAddr amp FFh SetRegister REG_SCRN1_DISP_START_ADDR1 BYTE dwAddr gt gt 8 E FFh SED1355 X23A G 003 05 Page 40 Epson Research and Development Vancouver Design Center SetRegister REG_SCRN1_DISP_START_ADDR2 BYTE dwAddr gt gt 16 amp OFh do register ReadRegister OAh while 80h register amp 80h 4 Write the pixel pan value during the vertical non display portion of the frame a Coming from the above code wait for beginning of the non display period do register ReadRegister 0Ah while 80h register amp 80h b Write the new pixel panning value register ReadRegister 18h register amp FOh register Pixel
259. ce ERROR Could not register SED1355FOA device A SED1355 device was not found at the configured addresses Check the configuration address using the 1355CFG configuration program 1355PWR Software Suspend Power Sequencing Utility Issue Date 98 10 30 EPSON SED1355 Embedded RAMDAC LCD CRT Controller Windows CE Display Drivers Document Number X23A E 001 04 Copyright 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Microsoft and Windows are registered trademarks of Microsoft Corporation Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 Windows6 CE Display Drivers X23A E 001 04 Issue Date 98 10 30 Epson Research and Development Page 3 Vancouver Design Center WINDOWS CE DISPLAY DRIVERS The Windows CE display drivers are designed to support the SED1355 Embedded RAMDAC LCD CRT Con
260. ce Pin Mapping for details Unused pins are driven low FPFRAME JO 73 CN3 Output Frame pulse FPLINE O 74 CN3 Output Line pulse FPSHIFT O 77 CO3 Output Shift clock Output if LCD power control output The active polarity of this output is selected LCDPWR O 75 con MD 10 0 by the state of MD1 0 at the rising edge of RESET see Summary of Configuration Options This output is controlled by the power save 1 ifMD 10 1 mode circuitry see Power Save Modes for details This is a multi purpose pin e For TFT D TFD panels this is the display enable output DRDY e For passive LCD with Format 1 interface this is the 2nd Shift Clock DRDY O 76 CND Output FPSHIFT2 e For all other LCD panels this is the LCD backplane bias signal MOD See LCD Interface Pin Mapping and REG 02h for details 5 2 4 CRT Interface Table 5 3 CRT Interface Pin Descriptions RESET N Pin Name Type Pin Cell State Description HRTC IO 107 CN3 Output Horizontal retrace signal for CRT VRTC IO 108 CN3 Output Vertical retrace signal for CRT RED O 100 A Analog output for CRT color Red GREEN O 103 Analog output for CRT color Green BLUE O 105 A Analog output for CRT color Blue IREF 101 A Current reference for DAC see Analog Pins This pin must be left unconnected if the DAC is not needed Hardware Functional Specification Issue Date 99 05 18 SED1355 X23A A 001 11 Page 32 5 2 5 Miscellaneous Epson Research and Development Vancou
261. ch and Development Page 3 Vancouver Design Center 1355PWR 1355PWR is a diagnostic utility used to test some of the power save capabilities of the SED1355 1355PWR enables or disables the software suspend mode hardware suspend mode and the LCD allowing testing of the power sequencing in each mode To measure the timing for power sequencing GPIO pin 1 is used to trigger an oscilloscope at the point the requested power sequencing function is activated deactivated For further information on LCD Power Sequencing and Power Save Modes refer to the SED1355 Programming Notes and Examples document number X23A G 003 xx and the SED 1355 Functional Hardware Specifi cation document number X23A A 01 xx The 1355PWR software suspend power sequencing utility must be configured and or compiled to work with your hardware platform The program 1355CFG EXE can be used to configure 1355PWR Consult the 1355CFG users guide document number X23A B 001 xx for more information on configuring SED1355 utilities This software is designed to work in both embedded and personal computer PC environments For the embedded environment it is assumed that the system has a means of downloading software from the PC to the target platform Typically this is done by serial communications where the PC uses a terminal program to send control commands and information to the target processor Alternatively the PC can program an EPROM which is then placed in the target pla
262. cification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 114 Epson Research and Development Vancouver Design Center General IO Pins Configuration Register 0 REG 1Eh RW a e gi e GPIO3 Pin GPIO2 Pin GPIO1 Pin wa IO Config IO Config IO Config Pins MA9 MA10 MA11 are multi functional they can be DRAM address outputs or general purpose IO dependent on the DRAM type MD 7 6 are used to identify the DRAM type and configure these pins as follows Table 8 11 MA GPIO Pin Functionality MD 7 6 at Pin Function rising edge of RESET MA9 MA10 MA11 00 GPIO3 GPIO1 GPIO2 01 MA9 GPIO1 GPIO2 10 MA9 GPIO1 GPIO2 11 MA9 MA10 MA11 These bits are used to control the direction of these pins when they are used as general purpose IO These bits have no effect when the pins are used as DRAM address outputs bit 3 GPIO3 Pin IO Configuration When this bit 1 the GPIO3 pin is configured as an output pin When this bit 0 default the GPIO3 pin is configured as an input pin bit 2 GPIO2 Pin IO Configuration When this bit 1 the GPIO2 pin is configured as an output pin When this bit 0 default the GPIO2 pin is configured as an input pin bit 1 GPIO1 Pin IO Configuration When this bit 1 the GPIO1 pin is configured as an output pin When this bit 0 default the GPIO1 pin is configured as an input pin General IO Pins Configuration Register 1 REG 1 Fh
263. clock 2 memory clock 3 memory clock 4 see REG 19h bits 1 0 2 timin t3min 14Ts 3 t8min REG 04h bits 6 0 1 8 REG O5h bits 4 0 1 8 Ts 4 tOmin REG 04h bits 6 0 1 8 REG O5h bits 4 0 1 8 1 Ts 5 t6min REG O5h bits 4 0 1 8 19 Ts 6 min REG O5h bits 4 0 1 8 10 Ts SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 91 Vancouver Design Center 7 5 8 8 Bit Dual Color Passive LCD Panel Timing VDP o VNDP FPFRAME ESA 32 FPLINE j feel j j j I I MOD oe X UD 3 0 LD 3 0 LINE 1 241 X LINE 2 242 Y LINE 3 243 X LINE 4 244 LINE 239 479X LINE 240 480 X LINE 1 241 X LINE 2 242 FPLINE Di MOD X MA la HDP de HNDP FPSHIFT FPDAT7 UD3 SE A R1 X 1 62 X 1 83 X 1 R5 X 1 66 Y 1 87 X 1 B639 Ki FPDAT6 UD2 WM A 1 01 12 X 1 R4 X 1 as X 1 B6 ms A X1 R640 X FPDATS5 UD1 pm en as X FR ee EE FPDAT4 UDO o 1 R2 X 1 43 X 1 84 X 1 R6 X 1 67 Y 1 88 A 1 B640 X FPDAT3 LD3 o X241 R1 241 G2 241 B3 241 R5 X241 G6 241 B7 ae Gerbe i FPDAT2 UD2 D 241 G1X241 B2X241 R4X241 G5X241 86X241 R8 Se FPDAT1 UD1 SC 241 B1X241 R3X241 G4 X241 B5 X241 R7 241 G8
264. closed 1 closed 1 closed 1 PC Card PCMCIA recommended settings configured for ISA bus support Table 2 3 Jumper Settings Description 1 2 2 3 JP1 DRDY pin 76 SED1355 Pin 76 connected to J6 pin 38 Pin 76 connected to J6 pin 35 JP2 LCD Vpp Selection 5 0V LCD driver Vpp 3 3V LCD driver Vpp Note JP1 is for internal use only default setting is 1 2 SED1355 SDU1355B0C Rev 1 0 ISA Bus Evaluation Board User Manual X23A G 004 04 Issue Date 98 10 30 Epson Research and Development Vancouver Design Center 3 LCD Interface Pin Mapping Table 3 1 LCD Signal Connector J6 Page 9 Color TFT D TFD Color Passive Mono Passive SED1355 Connector Pin Names Pin No 9 bit 12 bit 18 bit 4 bit 8 bit 16 bit 4 bit 8 bit FPDATO 1 R2 R3 R5 LDO LDO LDO FPDAT1 3 R1 R2 R4 LD1 LD1 LD1 FPDAT2 5 RO R1 R3 LD2 LD2 LD2 FPDAT3 7 G2 G3 G5 LD3 LD3 LD3 FPDAT4 9 G1 G2 G4 UDO UDO UDO UDO UDO FPDAT5 11 GO G1 G3 UD1 UD1 UD1 UD1 UD1 FPDAT6 13 B2 B3 B5 UD2 UD2 UD2 UD2 UD2 FPDAT7 15 B1 B2 B4 UD3 UD3 UD3 UD3 UD3 FPDAT8 17 BO B1 B3 LD4 FPDAT9 19 RO R2 LD5 FPDAT10 21 R1 LD6 FPDAT11 23 GO G2 LD7 FPDAT12 25 G1 UD4 FPDAT13 27 GO UD5 FPDAT14 29 BO B2 UD6 FPDAT15 31 B1 UD7 FPSHIFT 33 FPSHIFT DRDY 35 FPSHIFT2 FPLINE 37 FPLINE FPFRAME 39 FPFRAME 2 26 END Even Pins GND N C
265. contentions by forcing the host to wait until the resource arbitration is complete The Bus Start BS signal connects to TS the transfer start signal Interfacing to the Motorola MPC821 Microprocessor Issue Date 99 05 05 Epson Research and Development Vancouver Design Center 4 MPC821 to SED1355 Interface 4 1 Hardware Description Page 15 The SED1355 provides native Power PC bus support making it very simple to interface the two devices This application note describes both the environment necessary to connect the SED1355 to the MPC821 native system bus and the connection between the SDU1355BOB Evaluation Board and the Motorola MPC821 Application Development System ADS Additionally by implementing a dedicated display buffer the SED1355 can reduce system power consumption improve image quality and increase system performance as compared to the MPC821 s on chip LCD controller The SED1355 through the use of the MPC821 chip selects can share the system bus with all other MPC821 peripherals The following figure demonstrates a typical implementation of the SED1335 to MPC821 interface MPC821 SED1355 A10 gt M R A 11 31 v ABI20 0 Dr DB 15 0 C84 p CS TS gt BS TA ka WAIT RD WR p RD WR TSIZO gt RD TSIZ1 gt WEO BI p WEIS SYSCLK gt BUSCLK System RESET RESET Note When connecting the SED1355 RESET pin the system d
266. cted to MR of the SED1355 33 Connected to WE1 of the SED1355 34 Not connected SDU1355B0C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 98 10 30 Epson Research and Development Vancouver Design Center Table 4 2 CPU BUS Connector H2 Pinout Connector Comment Pin No 1 Connected to ABO of the SED1355 2 Connected to AB1 of the SED1355 3 Connected to AB2 of the SED1355 4 Connected to AB3 of the SED1355 5 Connected to AB4 of the SED1355 6 Connected to AB5 of the SED1355 7 Connected to AB6 of the SED1355 8 Connected to AB7 of the SED1355 9 Ground 10 Ground 11 Connected to AB8 of the SED1355 12 Connected to AB9 of the SED1355 13 Connected to AB10 of the SED1355 14 Connected to AB11 of the SED1355 15 Connected to AB12 of the SED1355 16 Connected to AB13 of the SED1355 17 Ground 18 Ground 19 Connected to AB14 of the SED1355 20 Connected to AB14 of the SED1355 21 Connected to AB16 of the SED1355 22 Connected to AB17 of the SED1355 23 Connected to AB18 of the SED1355 24 Connected to AB19 of the SED1355 25 Ground 26 Ground 27 5 volt supply 28 5 volt supply 29 Connected to RD WR of the SED1355 30 Connected to BS of the SED1355 31 Connected to BUSCLK of the SED1355 32 Connected to RD of the SED1355 33 Connected to AB20 of the SED1355 34 Not connected SDU1355B0C Rev 1 0 ISA Bus Evaluatio
267. ction This application note describes the hardware and software environment required to provide an interface between the SED1355 Embedded RAMDAC LCD CRT Controller and the Motorola MPC821 processor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Electronics America Website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs Oerd epson com Interfacing to the Motorola MPC821 Microprocessor SED1355 Issue Date 99 05 05 X23A G 008 03 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the MPC821 2 1 The MPC8xx System Bus The MPC8xx family of processors feature a high speed synchronous system bus typical of modern RISC microprocessors This section provides an overview of the operation of the CPU bus in order to establish interface requirements 2 2 MPC821 Bus Overview The MPC8xx microprocessor family uses a synchronous address and data bus All IO is synchronous to a square wave reference clock called MCLK Master Clock This clock runs at the machine cycle speed of the CPU core typically 25 to 50 MHz Most outputs from the processor change state on the rising edge of this clock Similarly most inputs to the processor a
268. ctive low input that clears all internal registers and forces all outputs to their inactive states Note that active high RESET signals must be inverted before input to this pin SED1355 X23A A 001 11 Hardware Functional Specification Issue Date 99 05 18 Epson Research and Development Vancouver Design Center 5 2 2 Memory Interface Page 29 Table 5 2 Memory Interface Pin Descriptions Pin Name Type Pin Cell RESET State Description LCAS O 51 CO1 e For dual CAS DRAM this is the column address strobe for the lower byte LCAS e For single CAS DRAM this is the column address strobe CAS See Memory Interface Pin Mapping for summary See Memory Interface Timing for detailed functionality UCAS O 52 CO1 This is a multi purpose pin e For dual CAS DRAM this is the column address strobe for the upper byte UCAS e For single CAS DRAM this is the write enable signal for the upper byte UWE See Memory Interface Pin Mapping for summary See Memory Interface Timing for detailed functionality WE O 53 CO1 e For dual CAS DRAM this is the write enable signal WE e For single CAS DRAM this is the write enable signal for the lower byte LWE See Memory Interface Pin Mapping for summary See Memory Interface Timing for detailed functionality RAS O 54 CO1 Row address strobe see Memory Interface Timing for detai
269. d write cycle 0 0 ns 1112 Falling edge OE to D 15 0 driven read cycle 0 0 ns t12 D 15 0 setup to rising edge WAIT read cycle 0 0 ns t13 Rising edge of OE to D 15 0 tri state read cycle 5 25 5 10 ns 1 If the SED1355 host interface is disabled the timing for WAIT driven low is relative to the falling edge of OE WE or the first positive edge of CLK after A 20 0 M R becomes valid whichever one is later 2 Ifthe SED1355 host interface is disabled the timing for D 15 0 driven is relative to the falling edge of OE or the first positive edge of CLK after A 20 0 M R becomes valid whichever one is later SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 51 Vancouver Design Center 7 1 6 Generic Interface Timing tl GG E CLK I t4 t5 A 20 0 M R t6 CS RDO RD1 WEO WE1 t7 t8 e gt E WAIT d t9 t10 D 15 0 write t11 t12 t13 D 15 0 read Figure 7 6 Generic Timing Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 52 Epson Research and Development Vancouver Design Center Table 7 6 Generic Timing 3 0V 5 0V Symbol Parameter Min Max
270. d 1 Ts t10 FPSHIFT pulse width low 0 45 Ts t11 FPSHIFT pulse width high 0 45 Ts t12 UD 3 0 LD 3 0 setup to FPSHIFT falling edge 0 45 Ts t13 UD 3 0 LD 3 0 hold to FPSHIFT falling edge 0 45 Ts t14 FPLINE pulse trailing edge to FPSHIFT rising edge 13 Ts 1 Ts pixel clock period memory clock memory clock 2 memory clock 3 memory clock 4 see REG 1 9h bits 1 0 2 tlmin 18min 14Ts 3 t3min REG 04h bits 6 0 1 8 REG O5h bits 4 0 1 8 Ts 4 t5min REG 04h bits 6 0 1 8 REG O5h bits 4 0 1 8 1 Ts 5 t6min REG O5H bits 4 0 1 8 20 Ts 6 tZmin REG O5H bits 4 0 1 8 11 Ts SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 93 Vancouver Design Center 7 5 9 16 Bit Dual Color Passive LCD Panel Timing VNDP le VDP Ke gt FPFRAME FPLINE __ l l lo al Jl l ll l Jl l MOD S X UD 7 0 LD 7 0 N LINE 1 241 LINE 2 242 X LINE 3 243 X LINE 4 244 UNE 239 479XLINE 240 480 LINE 241 X LINE 2 242 FPLINE a eu MOD Y HDP HNDP a gt FPSHIFT Si K Lait KE E Dech l E UD7 LD7 dii 0 O O AJ A X UD6 LD6 SE BECH D X X X E ER D VP aS D UD5 LD5 re D IRA X X X K Neat Bn UD4 LD4 241 A2 X 24164 X Ke e X WE oe UD3 LD3 BH CH D D X Y
271. d Development Page 33 Vancouver Design Center 5 3 Summary of Configuration Options Table 5 5 Summary of Power On Reset Options Pin Name value on this pin at rising edge of RESET is used to configure 1 0 1 0 MDO 8 bit host bus interface 16 bit host bus interface Select host bus interface MD 11 0 000 SH 3 SH 4 bus interface 001 MC68K Bus 1 010 MC68K Bus 2 MD 3 1 011 Generic 100 Reserved 101 MIPS ISA 110 PowerPC 111 PC Card when MD11 1 Philips PR31500 PR31700 or Toshiba TX3912 Bus MD4 Little Endian Big Endian MD5 WAIT is active high 1 insert wait state WAIT is active low 0 insert wait state Memory Address GPIO configuration 00 symmetrical 256Kx16 DRAM MA 8 0 DRAM address MA 1 1 9 GPIO2 1 3 pins MD 7 6 01 symmetrical 1Mx16 DRAM MA 9 0 DRAM address MA 10 11 GPIO2 1 pins 10 asymmetrical 256Kx16 DRAM MA 9 0 DRAM address MA 10 11 GPIO2 1 pins 11 asymmetrical 1Mx16 DRAM MA 11 0 DRAM address MD8 Not used MD9 SUSPEND pin configured as GPO output SUSPEND pin configured as SUSPEND input MD10 Active low LCDPWR polarity or Active high LCDPWR polarity or active high GPO polarity active low GPO polarity MD11 Alternate Host Bus Interface Selected Primary Host Bus Interface Selected MD12 BUSCLK input divided by 2 BUSCLK input not divided MD 15 13 Not used Hardware Functional Specification SED1355 X23A A 001 11 Page 34 5 4 Multiple Function Pin Mapping Table 5 6 CPU In
272. d to configure 1355PLAY Consult the 1355CFG users guide document number X23A B 001 xx for more information on configuring SED1355 utilities This software is designed to work in both embedded and personal computer PC environments For the embedded environment it is assumed that the system has a means of downloading software from the PC to the target platform Typically this is done by serial communications where the PC uses a terminal program to send control commands and information to the target processor Alternatively the PC can program an EPROM which is then placed in the target platform Some target platforms can also communicate with the PC via a parallel port connection or an Ethernet connection SED1355 Supported Evaluation Platforms Installation 1355PLAY Diagnostic Utility Issue Date 98 10 30 1355PLAY supports the following SED1355 evaluation platforms PC system with an Intel 80x86 processor M68332BCC Business Card Computer board revision B with a Motorola MC68332 processor M68ECOOOIDP Integrated Development Platform board revision 3 0 with a Motorola M68EC000 processor SH3 LCEVB board revision B with an Hitachi SH 3 HD6417780 processor PC platform copy the file 1355PLAY EXE to a directory that is in the DOS path on your hard drive Embedded platform download the program 1355PLAY to the system SED1355 X23A B 005 03 Epson Research and Development Vancouver Design Center Embedded plat
273. de o o 21 Suggested Values for 2 Bpp Gray Shade 2 21 Suggested LUT Values for 4 Bpp Gray Shade o o e 22 Number of Pixels Panned Using Start Address o e e o 26 Active PixelP n BUS ut a A A a a Pow ee e Sa 26 Ink CursorMode e is a ae Be A Rs a a a laps aed 33 Cursor Ink Start Address Encoding 35 HAL Functions dit A e SP RE Ges 44 Passive Single Panel 320x240 with 40MHz Pixel Clock o o 101 Passive Single Panel 640x480 with 40MHz Pixel Clock o 101 Passive Dual Panel 640x480 with 40MHz Pixel Clock o ee 102 TFT Single Panel E 640x480 with 25 175 MHz Pixel Clock 102 List of Figures Pixel Storage for 1 Bpp 2 Colors Gray Shades in One Byte of Display Buffer 12 Pixel Storage for 2 Bpp 4 Colors Gray Shades in One Byte of Display Buffer 12 Pixel Storage for 4 Bpp 16 Colors Gray Shades in One Byte of Display Buffer 13 Pixel Storage for 8 Bpp 256 Colors 16 Gray Shades in One Byte of Display Buffer 13 Pixel Storage for 15 Bpp 32768 Colors 16 Gray Shades in Two Bytes of Display Buffer 14 Pixel Storage for 16 Bpp 65536 Colors 16 Gray Shades in Two Bytes of Display Buffer 14 Viewport Inside a Virtual Display e 23 Memory Address Offset Registers 24 Screen 1 Start Address Registers 26 Pixel Panning Register ecc 8
274. de int seReservedl int PowerSaveMode SED1355 Programming Notes and Examples X23A G 003 05 Issue Date 99 04 27 Epson Research and Development Page 99 Vancouver Design Center Memory Access ty int seReadDisplayByte int seReservedl DWORD offset BYTE pByte int seReadDisplayWord int seReservedl DWORD offset WORD pWord int seReadDisplayDword int seReservedl DWORD offset DWORD pDword int seWriteDisplayBytes int seReservedl DWORD addr BYTE val DWORD count int seWriteDisplayWords int seReservedl DWORD addr WORD val DWORD count int seWriteDisplayDwords int seReservedl DWORD addr DWORD val DWORD count Drawing int seGetInkStartAddr int seReservedl DWORD addr int seGetPixel int seReservedl long x long y DWORD pVal int seSetPixel int seReservedl long x long y DWORD color int seDrawLine int seReservedl long x1 long yl long x2 long y2 DWORD color int seDrawRect int seReservedl long x1 long yl long x2 long y2 DWORD color BOOL SolidFill int seDrawEllipse int seReservedl long xc long yc long xr long yr DWORD color BOOL SolidFill int seDrawCircle int seReservedl long xCenter long yCenter long radius DWORD color BOOL SolidFill Hardware Cursor int selnitCursor int seReservedl int seCursoroff int seReservedl int seGetCursorStartAddr int seReservedl DWORD addr
275. de n a n a Threshold Threshold Threshold Threshold Bit 1 Bit 0 Bit 3 Bit 2 Bit 1 Bit 0 bit 7 6 Ink Cursor Control Bits 1 0 These bits select the operating mode of the Ink Cursor circuitry See table below Table 8 17 Ink Cursor Selection REG 27h Operating Mode Bit 7 Bit 6 0 0 inactive 0 1 Cursor 1 0 Ink 1 1 reserved bit 3 0 Ink Cursor FIFO Threshold Bits 3 0 These bits specify the Ink Cursor FIFO depth required to sustain uninterrupted display fetches When these bits are all 0 the Ink Cursor FIFO depth is calculated automatically REG 28h Cursor X Position Register 0 RW Cursor X Cursor X Position Bit 7 Position Bit6 Position Bit 5 Position Bit 4 Position Bit 3 Position Bit 2 Position Bit 1 Position Bit O Cursor X Cursor X Cursor X Cursor X Cursor X Cursor X Cursor X Position Register 1 REG 29h RW Cursor X Cursor X Reserved ma na ES a va Position Bit 9 Position Bit 8 REG 29 bit 7 Reserved REG 28 bits 7 0 REG 29 bits 1 0 SED1355 X23A A 001 11 This bit must be set to 0 Cursor X Position Bits 9 0 In Cursor mode this 10 bit register is used to program the horizontal pixel position of the Cursor s top left pixel This register must be set to 0 in Ink mode Note The Cursor X Position register must be set during VNDP vertical non display period Check the VNDP status bit REG OAh bit 7 to determine if you are in
276. demark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 0 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 1355BMP Demonstration Program X23A B 006 03 Issue Date 98 10 30 Epson Research and Development Page 1 Vancouver Design Center 1355BMP 1355BMP is a demonstration utility used to show the SED1355 display capabilities by rendering bitmap images on the display The program will display any bitmap in Windows BMP file format and then exit 1355BMP also loads images to demonstrate the hardware cursor and ink layer 1355BMP is designed to operate on a personal computer PC in the DOS environment only Other embedded platforms are not supported due to the possible lack of system memory or structured file system The 1355BMP demonstration utility must be configured and or compiled to work with your hardware configuration The program 1355CFG EXE can be used to configure 1355BMP Consult the 1355CFG users guide document number X23A B 001 xx for more information on configuring SED1355 utilities SED1355 Supported Evaluation Platforms 1355BMP supports the following SED1355 evaluation platforms e PC system with an Intel 80x86 processor Note The 1355BMP source code may be modified by the OEM to support other evaluation platforms Installation Copy the file 1355BMP EXE to a directory that is in the DOS path on your hard drive Usage At the pro
277. device was not found at the configured addresses Check the configuration address using the 1355CFG configuration program ERROR Insufficient memory for bit per pixel The given display resolution requires a larger display buffer than is available to store the image Either increase the amount of display buffer or select a lower color depth bpp WARNING Clocks are too fast for given mode This message is only shown if the m command was entered and the MCLK PCLK frequencies violated the timings in the SED1355 Hardware Functional Specification document number X23A A 001 xx SED1355 X23A B 005 03 Page 8 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 1355PLAY Diagnostic Utility X23A B 005 03 Issue Date 98 10 30 EPSON SED1355 Embedded RAMDAC LCD CRT Controller 1355BMP Demonstration Program Document Number X23A B 006 03 Copyright 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered tra
278. ding an easy interface to the CPU A 16M byte block of memory is assigned for the LCD controller and its own chip select and ready signals are available Word or byte accesses are controlled by the system high byte signal SHB Interfacing to the NEC VR4121 Microprocessor Issue Date 99 05 05 Epson Research and Development Page 9 Vancouver Design Center 2 1 2 LCD Memory Access Cycles Once an address in the LCD block of memory is placed on the external address bus ADD 25 0 the LCD chip select LCDCS is driven low The read or write enable signals RD or WR are driven low for the appropriate cycle and LCDRDY is driven low to insert wait states into the cycle The high byte enable SHB in conjunction with address bit 0 allows for byte steering The following figure illustrates typical NEC VR4121 memory read and write cycles to the LCD controller interface TCLK E AE AUR NA MU E ADD 25 0 X VALID X SHB LCDCS WR RD D 15 0 write VALID D 15 0 read Hi Z d VALID A 1 LCDRDY Figure 2 1 NEC VR4121 Read Write Cycles Interfacing to the NEC VR4121 Microprocessor SED1355 Issue Date 99 05 05 X23A G 011 03 Page 10 3 SED1355 Host Bus Interface The SED1355 directly supports multiple processors The SED1355 implements a 16 bit MIPS ISA Host Bus Interface which is most suitable for direct connection to the VR4121 3 1 Host Bus I
279. display buffer seGetBytesPerScanline Determine the number of bytes or memory consumed per scan line in current mode seGetScreenSize Determine the height and width of the display surface in pixels seSelectBusWidth Select the bus width on the ISA evaluation card seGetHostBusWidth Determine the bus width set in the HAL_STRUCT seDisplayEnable Turn the display s on off seDisplayFifo Turn the FIFO on off seDelay Use the frame rate timing to delay for required seconds requires registers to be initialized seGetLinearDispAddr Get a pointer to the logical start address of the display buffer seSplitlnit Initialize split screen variables and setup start addresses seSplitScreen Set the size of either the top or bottom screen SED1355 X23A G 003 05 Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 45 Vancouver Design Center Table 11 1 HAL Functions Continued Function Description seVirtInit Initialize virtual screen mode setting x and y sizes seVirtMove pan scroll the virtual screen surface s seSetReg Write a Byte value to the specified SED1355 register seSetWordReg Write a Word value to the specified SED1355 register seSetDwordReg Write a Dword value to the specified SED1355 register seGetReg Read a Byte value from the specified SED1355 register seGetWordReg Read a Word value from the specified SED1355
280. display the contents of the registers Type x 5 to read register 5 Type x 3 10 to write 10h to register 3 Type f 0 ffff aa to fill the first FFFFh bytes of the display buffer with AAh Type f 0 1fffff aa to fill 2M bytes of the display buffer with AAh Type r 0 100 to read the first 100h bytes of the display buffer 10 Type q to exit the program 1355PLAY Diagnostic Utility Issue Date 98 10 30 SED1355 X23A B 005 03 Page 6 Scripting Comments SED1355 X23A B 005 03 Epson Research and Development Vancouver Design Center 1355PLA Y can be driven by a script file This is useful when e there is no display output and a current register status is required e various registers must be quickly changed to view results A script file is an ASCII text file with one 1355PLAY command per line All scripts must end with a q quit command On a PC platform a typical script command line might be 1355PLAY lt dumpregs scr gt results This causes the file dumpregs scr to be interpreted as commands by 1355PLAY and the results to be sent to the file results Example Create an ASCII text file that contains the commands i xa and q This file initializes the SED1355 and reads the registers Note after a semicolon all characters on a line are ignored Note all script files must end with the q command pl xa q e All numeric values are consider
281. displayed In this mode the four most significant bits of green are used to set the absolute intensity of the image Four bits of green resolves to 16 colors Now however each pixel requires two bytes Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 23 Vancouver Design Center 5 Advanced Techniques This section presents information on the following e virtual display e panning and scrolling e split screen display 5 1 Virtual Display Virtual display refers to the situation where the image to be viewed is larger than the physical display This can be in the horizontal the vertical or both dimensions To view the image the display 1s used as a window or viewport into the display buffer At any given time only a portion of the image is visible Panning and scrolling are used to view the full image The Memory Address Offset registers are used to determine the number of horizontal pixels in the virtual image The offset registers can be set for a maximum of 2 or 2048 words In 1 bpp display modes these 2048 words cover 16 384 pixels At 16 bpp 2048 words cover 1024 pixels The maximum vertical size of the virtual image is the result of a number of variables In its simplest the number of lines is the total display buffer divided by the number of bytes per horizontal line The number of bytes per line is the number of words in the offset register multiplied by two At maximum horizontal size
282. dr Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 11h Screen 1 Display Start Address 1 Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 REG 12h Screen 1 Display Start Address 2 ae a ha n a Start Addr Start Addr Start Addr Start Addr Bit 19 Bit 18 Bit 17 Bit 16 Figure 5 3 Screen 1 Start Address Registers These three registers form the address of the word in the display buffer where screen 1 will start displaying from Changing these registers by one will cause a change of 0 to 16 pixels depending on the current color depth Refer to the following table to see the minimum number of pixels affected by a change of one to these registers Table 5 1 Number of Pixels Panned Using Start Address Color Depth bpp Pixels per Word Number of Pixels Panned 1 16 16 2 8 8 4 H H 8 2 2 15 1 1 16 1 1 REG 18h Pixel Panning Register Screen 2 Screen 2 Screen 2 Screen 2 Screen 1 Screen 1 Screen 1 Screen 1 Pixel Pan Pixel Pan Pixel Pan Pixel Pan Pixel Pan Pixel Pan Pixel Pan Pixel Pan Bit 3 Bit 2 Bit 1 Bit 0 Bit 3 Bit 2 Bit 1 Bit 0 Figure 5 4 Pixel Panning Register The pixel panning register offers finer control over pixel pans than is available wi
283. e The HAL was unable to read the revision code register on the SED1355 Ensure that the SED1355 hardware is installed and that the hardware platform has been set up correctly ERROR Too many devices registered There are too many display devices attached to the HAL The HAL currently supports only one device ERROR Could not register SED1355FOA device A SED1355 device was not found at the configured addresses Check the configuration address using the 1355CFG configuration program ERROR Could not set bit per pixel display mode This message generally means that the given hardware software setup violates the timing limitations described in the SED1355 Hardware Functional Specification document number X23A A 001 xx SED1355 X23A B 003 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 1355SPLT Display Utility X23A B 003 02 Issue Date 98 10 30 EPSON SED1355 Embedded RAMDAC LCD CRT Controller 1355VIRT Display Utility Document Number X23A B 004 03 Copyright 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Techn
284. e REG 22h bits 3 2 01 or 10 1 4511 3 ns RAS pulse width REG 22h bits 6 5 00 and bits 3 2 45t1 3 ie 2 00 RAS pulse width REG 22h bits 6 5 00 and bits 3 34541 3 ne 2 01 or 10 RAS pulse width REG 22h bits 6 5 01 and bits 3 1 4511 3 n 2 00 RAS pulse width REG 22h bits 6 5 01 and bits 3 245t1 3 He 2 01 or 10 RAS pulse width REG 22h bits 6 5 10 and bits 3 0 4511 3 ag 2 00 RAS pulse width REG 22h bits 6 5 10 and bits 3 1 45 t1 3 Ae 2 01 or 10 e CAS pulse width REG 22h bits 3 2 00 2t1 3 ns CAS pulse width REG 22h bits 3 2 01 or 10 1t1 3 t5 CAS Setup to RAS 0 45t1 3 ns CAS Hold to RAS REG 22h bits 6 5 00 and bits 2450 3 as 3 2 00 CAS Hold to RAS REG 22h bits 6 5 00 and bits 3 4511 3 Ae 3 2 01 or 10 CAS Hold to RAS REG 22h bits 6 5 01 and bits 1 4511 3 Se 16 3 2 00 CAS Hold to RAS REG 22h bits 6 5 01 and bits 2450 3 ne 3 2 01 or 10 CAS Hold to RAS REG 22h bits 6 5 10 and bits 0 4511 3 Ss 3 2 00 CAS Hold to RAS REG 22h bits 6 5 10 and bits 1 45 t1 3 w 3 2 01 or 10 Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 74 7 3 6 FPM DRAM Self Refresh Timing Epson Research and Development Vancouver Design Center Stopped for Restarted for i suspend mode active mode Memory Gg Clock Y t2 RAS Sf t3 t4
285. e 10 Epson Research and Development Vancouver Design Center Table 2 1 LCD Connector Pinout Pin 4 SED1355F0A Color TFT D TFD Color STN Mono STN Comments Pin Names 9 bit 12 bit 18 bit 4 bit 8 bit 16 bit 4 bit 8 bit 1 FPDATI 0O R2 R3 R5 LDO LDO LDO 3 FPDAT 1 R1 R2 R4 LD1 LD1 LD1 5 FPDAT 2 RO R1 R3 LD2 LD2 LD2 7 FPDAT 3 G2 G3 G5 LD3 LD3 LD3 9 FPDAT 4 G1 G2 G4 UDO UDO UDO UDO UDO 11 FPDAT 5 GO G1 G3 UD1 UD1 UD1 UD1 UD1 13 FPDAT 6 B2 B3 B5 UD2 UD2 UD2 UD2 UD2 15 FPDAT 7 B1 B2 B4 UD3 UD3 UD3 UD3 UD3 17 FPDAT 8 BO B1 B3 LD4 19 FPDAT 9 RO R2 LD5 21 FPDAT 10 R1 LD6 23 FPDAT 1 1 GO G2 LD7 25 FPDAT 12 Gi UD4 27 FPDAT 13 GO UD5 29 FPDAT 14 BO B2 UD6 31 FPDAT 15 B1 UD7 33 FPSHIFT FPSHIFT 35 or 38 DRDY DRDY MOD FPSHIFT2 sumper selectable 37 FPLINE FPLINE 39 FPFRAME FPFRAME 2 4 6 8 10 12 14 16 18 20 OND 22 24 26 On Off 28 LCDBACK Control for Backlight Selectable 32 LCDVCC 3 3V 5V 34 12V 36 VDDH Sn bias On Off 40 LCDPWR Control for LCD Power SDU1355 D9000 Evaluation Board User Manual X23A G 002 03 Issue Date 98 10 30 Epson Research and Development Page 11 Vancouver Design Center 2 1 3 Touchscreen Support If the LCD panel being used has an integrated Touchscreen the touchscreen interface signals are connected to header strip TS1 These signals are then ro
286. e Chip Select Module GPCM is used to control memory and peripheral devices which do not require special timing or address multiplexing In addition to the chip select output it can generate active low Output Enable OE and Write Enable WE signals compatible with most memory and x86 style peripherals The MPC821 bus controller also provides a Read Write RD WR signal which is compatible with most 68K peripherals The GPCM is controlled by the values programmed into the Base Register BR and Option Register OR of the respective chip select The Option Register sets the base address the block size of the chip select and controls the following timing parameters The ACS bit field allows the chip select assertion to be delayed by 0 1 4 or 2 clock cycle with respect to the address bus valid The CSNT bit causes chip select and WE to be negated 1 2 clock cycle earlier than normal The TRLX relaxed timing bit will insert an additional one clock delay between assertion of the address bus and chip select This accommodates memory and peripherals with long setup times The EHTR Extended hold time bit will insert an additional 1 clock delay on the first access to a chip select Up to 15 wait states may be inserted or the peripheral can terminate the bus cycle itself by asserting TA Transfer Acknowledge Any chip select may be programmed to assert BI Burst Inhibit automatically when its memory space is addressed by the proces
287. e E AO Papel Paje e er a e ds A a o les Oh as er oe le tes lll CRT Page 1 204 rn a e a a As na dt ie E Initial Pages ocs eb a a e e ee 2 JE Open Dialogs Boxe sag Ae gee be Oa et eo BP as ee Sos ao ee Soya A Save AS Dialog Box si rr ae oe ae Shoe a a ee bee ae oe dS Example Hora E wee tk ede a e How ole Se Ae D Comments s La foe ee bo ee IA ee ea a ee ae JI Sample Program Messages e 18 1355CFG Configuration Program SED1355 Issue Date 98 10 30 X23A B 001 02 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 1355CFG Configuration Program X23A B 001 02 Issue Date 98 10 30 Epson Research and Development Vancouver Design Center Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 1355CFG Configuration Program Issue Date 98 10 30 Page 5 List of Figures General Pageta 2 42 54285 dd a A A ds AS ES 9 Memory Paces 6 vy waste E e E AIRIS A E RA ON AN 10 Panel ageet ech A RAR AA A A A A E 11 CRY Pages coito a AE ie ds e A Sb ad E ee ELE 12 Default Paje ori AS A ES AE eu dee ADE 3 13 SED1355 X23A B 001 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 1355CFG Configuration Program X23A B 001 02 Issue Date 98 10 30 Epson Research and Development Page 7 Vancouver Design Center 1355CFG 1355CFG is an interactive Windows 9x program that calculates the SED1355 register values for a user defined LCD panel CRT confi
288. e REG_CURSOR_X_POSITION1 define REG_CURSOR_Y_POSITIONO define REG_CURSOR_Y_POSITION1 define REG_INK_CURSOR_COLORO_0 define REG_INK_CURSOR_COLORO_1 define REG_INK_CURSOR_COLOR1_0 define REG_INK_CURSOR_COLOR1_1 define REG_INK_CURSOR_START_ADDR define REG_ALTERNATE_FRM WARNING M SG define MAX REG endif JA SED1355 X23A G 003 05 HAL _REGS_H 0x0 0x0 Ox0F 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D Ox2E Ox2F 0x30 0x31 w CO bi Do Dm Dm vw oO A o UD vs GA HA 3 C n 0x31 Epson Research and Development Vancouver Design Center The following header file defines the structures used in the SED1355 HAL API Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 93 Vancouver Design Center DAT H Created 1998 Epson Research amp Development Are Vancouver Design Center Copyright c Epson Research and Development Inc 1997 1998 All rights reserved kk xy ifndef _HAL_H_ define _HAL H_ pragma warning disable 4001 Disable the single line comment warning include hal_regs h al typedef unsigned char BYTE typedef unsigned short WORD typedef unsigned long DWORD typedef unsigned int UINT typedef int BOOL ifdef INTEL typedef BYTE far LPBYTE
289. eading edge note 5 t7 FPLINE pulse trailing edge to FPSHIFT falling edge t10 t11 Ts t8 FPSHIFT period 1 Ts t9 FPSHIFT falling edge to FPLINE pulse trailing edge note 6 t10 FPLINE pulse trailing edge to FPSHIFT rising edge 21 Ts t11 FPSHIFT pulse width high 0 45 Ts t12 FPSHIFT pulse width low 0 45 Ts t13 UD 3 0 setup to FPSHIFT falling edge 0 45 Ts t14 UD 3 0 hold from FPSHIFT falling edge 0 45 Ts 1 Ts pixel clock period memory clock memory clock 2 memory clock 3 memory clock 4 see REG 19h bits 1 0 2 min t4min 14Ts 3 t4min REG 04h bits 6 0 1 8 REG O5h bits 4 0 1 8 Ts 4 t5min REG O4h bits 6 0 1 8 REG O5h bits 4 0 1 8 1 Ts 5 min REG O5h bits 4 0 1 8 28 Ts 6 t9min REG O5h bits 4 0 1 8 19 Ts SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 83 Vancouver Design Center 7 5 4 8 Bit Single Color Passive LCD Panel Timing Format 1 r VDP z VNDP FPFRAME au a FPLINE l fl Lo fl l l UD 3 0 LD 3 0 A UNE X LINE2 Y LINES X LINE4 X XLINE479XLINEA480 UNE X LINE2 FPLINE TI HDP HNDP la Elia FPSHIFT FPSHIFT2 SS AAA AN E ec lo UD3 o R1 X 1 G1 X 1 66 X 1 B6 X1 B11 X 1 R12 X X1
290. ease check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs Oerd epson com Interfacing to the NEC VR4121 Microprocessor SED1355 Issue Date 99 05 05 X23A G 011 03 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the NEC VrR4121 2 1 The NEC VR4121 System Bus 2 1 1 Overview SED1355 X23A G 011 03 The VR Series family of microprocessors features a high speed synchronous system bus typical of modern microprocessors Designed with external LCD controller support and Windows CE based embedded consumer applications in mind the VR4121 offers a highly integrated solution for portable systems This section provides an overview of the operation of the CPU bus in order to establish interface requirements The NEC VR4121 is designed around the RISC architecture developed by MIPS This microprocessor is based on the 166MHz VR4120 CPU core which supports 64 bit processing The CPU communicates with the Bus Control Unit BCU using its internal SysAD bus The BCU in turn communicates with external devices using its ADD and DATA buses which can be dynamically sized to 16 or 32 bit operation The NEC VR4121 has direct support for an external LCD controller Specific control signals are assigned for an external LCD controller provi
291. ecessary To further reduce the need for external components the SED1355 has an optional BUSCLK divide by 2 feature allowing the high speed DCLKOUT from the processor to be directly connected to the BUSCLK input of the SED1355 An optional external oscillator may be used for BUSCLK since the SED1355 will accept host bus control signals asynchronously with respect to BUSCLK The following diagram shows a typical implementation of the interface V 3 3V TX3912 pp SED1355 e M R CSH BSH AB 16 13 A 12 0 AB 12 0 D 23 16 gt DB 15 8 D 31 24 k DB 7 0 ALE AB20 CARDREG p AB19 CARDIORD p AB18 CARDIOWR AB17 CARDxCSH gt i WE1 CARDxCSL gt RD WR RD gt RD WE V ulku gt WEO CARDxWAIT PD TG Pup WAIT System RESEF gt RESET ENDIAN V DCLKOUT gt or Oscillator BUSCLK See text SEN Note When connecting the SED1355 RESET pin the system designer should be aware of all conditions that may reset the SED1355 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 Typical Implementation of Direct Connection Interfacing to the Toshiba MIPS TX3912 Processor SED1355 Issue Date 99 05 05 X23A G 010 03 Page 12 Epson Research and Development Vancouver Design Center The host interface control signals of the SED1355 are asynchronous with
292. ected through MD3 1 configuration appropriate external decode logic MUST be used to access the SED1355 See the section Host Bus Interface Pin Mapping of the SED1355 Hardware Functional Specification document number X23A A 001 xx 6 14 Schematic Notes The following schematics are for reference only and may not reflect actual implementation Please request updated information before starting any hardware design SED1355 SDU1355B0C Rev 1 0 ISA Bus Evaluation Board User Manual X23A G 004 04 Issue Date 98 10 30 Epson Research and Development Page 17 Vancouver Design Center 7 Parts List Item Qty board Designation Part Value Description 1 16 bere ey ara 0 1uF 0805 ceramic capacitor 2 1 C8 0 01uF 0805 ceramic capacitor 3 2 C9 C30 tuF 6V Tantalum capacitor size A 4 2 C14 C19 47uF 6V Tantalum capacitor size D 5 3 C15 C16 017 4 7uF 50V Tantalum capacitor size D 6 1 C20 56uF 35V Low ESR electrolytic 7 4 C21 C22 C23 C24 4 7uF 16V Tantalum capacitor size B 9 3 D1 D2 D3 BAV99 Signal diode 10 2 H1 H2 HEADER 17X2 11 2 JP1 JP2 HEADER 3 12 1 J1 VGA connector 13 1 J2 AT CON A 14 1 J3 AT CON B 15 1 J4 AT CON C 16 1 J5 AT CON D 17 1 J6 CON40A 18 6 L1 L2 L3 L4 L5 L7 Ferrite bead Philips BDS3 3 8 9 4S2 19 L6 Inductor 1uH 20 2 Q1 Q3 MMBT2222A 21 1 Q2 MMBT2907A 22 10 PRERE a EE 10K 0805 resistor 23 2 R3 R4 39 O
293. ector Pinout e 10 Touchscreen Header TS1 Pinout 11 Touchscreen Header Pinout e 11 Connectors Pinout for Channel AJ 2 aaa a 13 Connectors Pinout for Channel Ap 15 List of Figures SDU1355 D9000 Schematic Diagram 1 of 3 2 2 2 ee ee 19 SDU1355 D9000 Schematic Diagram 2 of n 20 SDU1355 D9000 Schematic Diagram 3 of 3 aaa ee ee 21 Component Placement 2 me mas ets RA ee AOR See NEE A 22 Figure 6 1 Page 5 Evaluation Board User Manual SDU1355 D9000 X23A G 002 03 Issue Date 98 10 30 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SDU1355 D9000 Evaluation Board User Manual X23A G 002 03 Issue Date 98 10 30 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction The Hitachi D9000 Development System Microsoft Windows CE ODO Reference Platform uses expansion boards to interface peripherals to the FPGA processor combination This manual describes how the SDU1355 D9000 Evaluation Board is used to provide a color LCD CRT solution for the Windows CE environment Reference SED1355 Hardware Functional Specification document number X23A A 001 xx D9000 Development System Hardware User Manual Hitachi Evaluation Board User Manual SDU1355 D9000 Issue Date 98 10 30 X23A G 002 03 Page 8 Epson Research and Development Vancouver Design Center 2 Features SED1355 Embedded RAMDAC LCD CRT controller e 4 8 bit monochrome or 4 8 16 b
294. ed device ID D horizontal coordinate of the pixel starting from 0 y vertical coordinate of the pixel starting from 0 Color at 1 2 4 and 8 bpp Color is an index into the LUT At 15 and 16 bpp Color defines the color directly i e rrrrrggggggbbbbb for 16 bpp Return Value ERR Ok operation completed with no problems int seGetPixel int DeviD long x long y DWORD pColor Description Reads the pixel color at coordinates x y This routine can be used for any color depth Parameters DevID Registered device ID D horizontal coordinate of the pixel starting from 0 y vertical coordinate of the pixel starting from 0 pColor at 1 2 4 and 8 bpp pColor points to an index into the LUT At 15 and 16 bpp pColor points to the color directly i e rrrrrgegggggbbbbb for 16 bpp Return Value ERR_OK operation completed with no problems Programming Notes and Examples SED1355 Issue Date 99 04 27 X23A G 003 05 Page 62 SED1355 X23A G 003 05 Epson Research and Development Vancouver Design Center int seDrawLine int DevID long x1 long y1 long x2 long y2 DWORD Color Description Parameters Return Value This routine draws a line on the display from the endpoints defined by x1 y1 to x2 y2 in the requested Color seDrawLine supports horizontal vertical and diagonal lines DevID registered device ID xl yl top left corner of line x2 y2 bottom right corner of li
295. ed to any particular aspect of SED1355 operation int seGetld int DevID int pid Description Parameters Return Value Note Reads the SED1355 revision code register to determine the chip product and revisions The interpreted value is returned in pID DevID registered device ID pld pointer to the int to receive the controller ID For the SED1355 the return values are currently ID_SED1355_REVO ID_UNKNOWN Other HAL libraries will return their respective controller IDs upon detection of their controller ERR OK operation completed with no problems ERR_UNKNOWN_DEVICE returned when pID returns ID_UNKNOWN The HAL was unable to identify the display controller seGetId will disable hardware suspend on x86 platforms and will enable the host interface register 1Bh on all platforms void seGetHalVersion const char pVersion const char pStatus const char Description Parameters Return Value Example Note pStatusRevision Retrieves the HAL library version The return pointers are all to ASCU strings A typical return would be pVersion 1 01 HAL version 1 01 pStatus B The B is the beta designator pStatusRevision 5 The programmer need only create pointers of const char type to pass as parameters see Example below pVersion pointer to string of HAL version code pStatus pointer to string of HAL status code NULL is release pStatusRevision
296. ed to be hexadecimal unless identified otherwise For example 10 10h 16 decimal 10t 10 decimal 010b 2 decimal e Redirecting commands from a script file PC platform allows those commands to be executed as though they were typed e When using a PC with the SDU1355 evaluation board the PC must not have more than 12M bytes of system memory 1355PLAY Diagnostic Utility Issue Date 98 10 30 Epson Research and Development Page 7 Vancouver Design Center Program Messages 1355PLAY Diagnostic Utility Issue Date 98 10 30 WARNING Did not find a 1355 device The HAL was unable to read the revision code register on the SED1355 Ensure that the SED1355 hardware is installed and that the hardware platform has been set up correctly ERROR Failed to change to mode Could not change to CRT LCD or SIMUL mode This message generally means that the given hardware software setup violates the timing limitations described in the SED1355 Hardware Functional Specification document number X23A A 001 xx ERROR Could not change to bit per pixel This message generally means that the given hardware software setup violates the timing limitations described in the SED1355 Hardware Functional Specification document number X23A A 001 xx ERROR Too many devices registered There are too many display devices attached to the HAL The HAL currently supports only one device ERROR Could not register SED1355FOA device A SED1355
297. el Panning Bit 3 Bit 2 Bit 1 Bit 0 Bit 3 Bit 2 Bit 1 Bit 0 This register is used to control the horizontal pixel panning of Screen and Screen 2 Each screen can be independently panned to the left by programming its respective Pixel Panning Bits to a non zero value The value represents the number of pixels panned The maximum pan value is dependent on the display mode Table 8 8 Pixel Panning Selection Display Mode Maximum Pan Value Pixel Panning Bits active 1 bpp 16 Bits 3 0 2 bpp 8 Bits 2 0 4 bpp 4 Bits 1 0 8 bpp 1 Bit 0 15 16 bpp 0 none Smooth horizontal panning can be achieved by a combination of this register and the Display Start Address registers See Section 10 Display Configuration for details Screen 2 Pixel Panning Bits 3 0 Pixel panning bits for screen 2 Screen Pixel Panning Bits 3 0 Pixel panning bits for screen 1 8 2 5 Clock Configuration Register Clock Configuration Register REG 19h RW E be EI aa Ge MCLK Divide PCLK Divide PCLK Divide Select Select Bit 1 Select Bit 0 bit 7 Reserved This bit must be set to 0 Note There must always be a source clock at CLKI bit 2 MCLK Divide Select Hardware Functional Specification Issue Date 99 05 18 When this bit 1 the MCLK frequency is half of its source frequency When this bit 0 the MCLK frequency is equal to its source frequency The MCLK frequency should always be set to the maximum fre
298. emory address offset This offset is the number of words from the beginning of one line of the display to the beginning of the next line of the display Note that this value does not necessarily represent the number of words to be shown on the display The display width is set in the Horizontal Display Width register If the offset is set to the same as the display width then there is no virtual width To maintain a constant virtual width as color depth changes the memory address offset must also change At 1 bpp each word contains 16 pixels at 16 bpp each word contains one pixel The formula to determine the value for these registers is offset pixels_per_line pixels_per_word 5 1 2 Examples Example 1 Determine the offset value required for 800 pixels at a color depth of 8 bpp At 8 bpp each byte contains one pixel therefore each word contains two pixels pixels_per_word 16 bpp 16 8 2 Using the above formula offset pixels_per_line pixels_per_word 800 2 400 190h words Register 17h would be set to 01h and register 16h would be set to 90h Example 2 Program the Memory Address Offset Registers to support a 16 color 4 bpp 640x480 virtual display on a 320x240 LCD panel To create a virtual display the offset registers must be programmed to the horizontal size of the larger virtual image After determining the amount of memory used by each line do a calculation to see 1f there is enough memory to support the d
299. ent Page 15 Vancouver Design Center 5 Software Test utilities and Windows CE v2 0 display drivers are available for the SED1355 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 1355CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The SED1355 test utilities and Windows CE v2 0 display drivers are available from your sales support contact or on the internet at http www eea epson com Interfacing to the NEC VR4121 Microprocessor SED1355 Issue Date 99 05 05 X23A G 011 03 Page 16 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents e NEC Electronics Inc VR4121 Preliminary Users Manual Document Number Ul13569EJ1VOUMOO Epson Research and Development Inc SED1355 Hardware Functional Specification Document Number X23A A 001 xx e Epson Research and Development Inc SDUI3553B0C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X23A G 004 xx e Epson Research and Development Inc SED1355 Programming Notes and Examples Document Number X23A G 003 xx 6 2 Document Sources e NEC Electronics Website http www necel com e Epson Electronics America Website http www eea epson com SED1355 Interfacing to the NEC VR41
300. er location Return Value ERR_OK operation completed with no problems ERR_HAL_BAD_ARG if the value for Offset is greater than the amount of installed memory 11 5 4 Color Manipulation The functions in the Color Manipulation section deal with altering the color values in the Look Up Table directly through the accessor functions and indirectly through the color depth setting functions int seSetLut int DevID BYTE pLut int Count Description This routine can write one or more LUT entries The writes always start with Look Up Table index 0 and continue for Count entries A Look Up Table entry consists of three bytes one each for Red Green and Blue The color information is stored in the four most significant bits of each byte Parameters DevID registered device ID pLut pointer to an array of BYTE lut 16 3 lut x 0 RED component lut x 1 GREEN component 1 ut x 2 BLUE component Count the number of LUT entries to write Return Value ERR Ok operation completed with no problems int seGetLut int DevID BYTE pLUT int Count Description This routine reads one or more LUT entries and puts the result in the byte array pointed to by pLUT A Look Up Table entry consists of three bytes one each for Red Green and Blue The color information is stored in the four most significant bits of each byte Parameters DevID registered device ID pLUT pointer to an array of BYTE lut 16 3 pLUT must point
301. er primary color therefore this translates into 4096 possible colors when color mode is selected To display the fullest dynamic range of colors will require careful selection of the colors in the LUT indices and in the image to be displayed When monochrome mode is selected the green component of the LUT is used to determine the gray shade intensity The green indices with only four bits can resolve 16 gray shades In this situation one might as well use four bit per pixel mode and conserve display buffer SED1355 X23A G 003 05 Page 14 Epson Research and Development Vancouver Design Center 3 1 5 Memory Organization for Fifteen Bit Per Pixel 32768 Colors 16 Gray Shades Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reserved Red Bit 4 Red Bit 3 Red Bit 2 Red Bit 1 Red Bit 0 Green Bit 4 Green Bit 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Green Bit 2 Green Bit 1 Green Bit 0 Blue Bit 4 Blue Bit 3 Blue Bit 2 Blue Bit 1 Blue Bit 0 Figure 3 5 Pixel Storage for 15 Bpp 32768 Colors 16 Gray Shades in Two Bytes of Display Buffer In 15 bit per pixel mode the SED 1355 is capable of displaying 32768 colors The 32768 color pixel is divided into four parts one reserved bit five bits for red five bits for green and five bits for blue In this mode the Look Up Table is bypassed and output goes directly into the Frame Rate Modulator The full color range is only available on TFT D TFD or
302. erial protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 Interfacing to the PC Card Bus X23A G 005 05 Issue Date 99 05 05 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 IMPFOdUCHON EE ok da AD E A A A A e 7 2 Interfacing to the PC CardBus 2 2 eee 8 2 1 The PCCard System Bus EE ee ee oe Aur o ZKE PECard OVETVIEW s oe ima a Ala Wi A ee da G 8 2 1 2 Memory Access Cycles 2 o e e o 8 3 SED1355 Host Bus Interface lt 0 lt 1 11 3 1 PC Card Host Bus Interface Pin Mapping e 11 3 2 PC Card Host Bus Interface Signals e 12 4 PC Card to SED1355 Interface lt lt o 13 4 1 Hardware Description e 13 4 2 SED1355 Hardware Configuration o a a a a a a a eee eee 15 4 3 Performance s o EEN EE ee e J 4 4 Register Memory Mapping a oaoa a a a aaas 16 SoftWare nica E EE EE EEN 17 Referenc s sata aa a A A a AAA 18 61 Documents E 2 e ee Se A Sa A a a a ts 18 D DocumentSources som al a a da a eil A tr we FS 7 Technical Support i a ci re EEN eee e A ET er e 19 7 1 Epson LCD CRT Controllers SED1355 e 19 dds Bach et
303. es into the LUT and the amount of green at that index controls the intensity Monochrome mode look ups are done for the panel interface only The CRT interface always receives the RGB values from the Look Up Table 4 1 Look Up Table Registers REG 24h Look Up Table Address Register Read Write LUT Address LUT Address LUT Address LUT Address LUT Address LUT Address LUT Address LUT Address Bit 7 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O LUT Address The LUT address register selects which of the 256 LUT entries will be accessed Writing to this register will select the red bank After three successive reads or writes to the data register this register will be incremented by one REG 26h Look Up Table Data Register Read Write LUT Data LUT Data LUT Data LUT Data ges Ha ha D Bit 3 Bit 1 Bit 0 LUT Data This register is where the 4 bit red green blue data value is written or read With each successive read or write the internal bank select is incremented Three reads from this register will result in reading the red then the green and finally the blue values associated with the index set in the LUT address register After the third read the LUT address register is incremented and the internal index points to the red bank again Programming Notes and Examples SED1355 Issue Date 99 04 27 X23A G 003 05 Page 16 Epson Research and Development Vancouver Design Center
304. esigner should be aware of all conditions that may reset the SED1355 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 Typical Implementation of MPC821 to SED1355 Interface Interfacing to the Motorola MPC821 Microprocessor Issue Date 99 05 05 SED1355 X23A G 008 03 Page 16 Epson Research and Development Vancouver Design Center Table 4 1 List of Connections from MPC821ADS to SED1355 on page 16 shows the connections between the pins and signals of the MPC821 and the SED1355 Note The interface was designed using a Motorola MPC821 Application Development System ADS The ADS board has 5 volt logic connected to the data bus so the interface included two 74F245 octal buffers on D 0 15 between the ADS and the SED1355 In a true 3 volt system no buffering is necessary 4 2 Hardware Connections The following table details the connections between the pins and signals of the MPC821 and the SED1355 Table 4 1 List of Connections from MPC82IADS to SED1355 MPC821 Signal Name MPC821ADS Connector and Pin Name SED1355 Signal Name Vcc P6 A1 P6 B1 Vcc A10 P6 C23 M R A11 P6 A22 AB20 A12 P6 B22 AB19 A13 P6 C21 AB18 A14 P6 C20 AB17 A15 P6 D20 AB16 A16 P6 B24 AB15 A17 P6 C24 AB14 A18 P6 D23 AB13 A19 P6 D22 AB12 A20 P6 D19 AB11 A21 P6 A19 A
305. esired number of lines 1 Initialize the SED1353 registers for a 320x240 panel See Introduction on page 7 2 Determine the offset register value SED1355 Programming Notes and Examples X23A G 003 05 Issue Date 99 04 27 Epson Research and Development Page 25 Vancouver Design Center pixels_per_word 16 bpp 16 4 4 offset pixels_per_line pixels_per_word 640 4 160 words OAOh words Register 17h will be written with 00h and register 16h will be written with AOh 3 Check that we have enough memory for the required virtual height Each line uses 160 words and we need 480 lines for a total of 160 480 76 800 words This display could be done on a system with the minimum supported memory size of 512 K bytes It is safe to continue with these values 5 2 Panning and Scrolling The terms panning and scrolling refer to the actions used to move the viewport about a virtual display Although the image is stored entirely in the display buffer only a portion is actually visible at any given time Panning describes the horizontal side to side motion of the viewport When panning to the right the image in the viewport appears to slide to the left When panning to the left the image to appears to slide to the right Scrolling describes the vertical up and down motion of the viewport Scrolling down causes the image to appear to slide up and scrolling up causes the image to appear to slide down Both panning and scrolling a
306. esolution the vertical cursor range is 1024 pixels Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Vancouver Design Center Page 35 REG 2Ch Ink Cursor Color 0 Register 0 Cursor Color 0 bit 7 Cursor Color 0 bit 6 Cursor Color 0 bit 5 Cursor Color 0 bit 4 Cursor Color 0 bit 3 Cursor Color 0 bit 2 Cursor Color O bit 1 Cursor Color 0 bit O REG 2Dh Ink Cursor Color 0 Register 1 Cursor Color 0 bit 15 Cursor Color 0 bit 14 Cursor Color 0 bit 13 Cursor Color 0 bit 12 Cursor Color 0 bit 11 Cursor Color 0 bit 10 Cursor Color 0 bit 9 Cursor Color 0 bit 8 REG 2Eh Ink Cursor Color 1 Register 0 Cursor Color 1 bit 7 Cursor Color 1 bit 6 Cursor Color 1 bit 5 Cursor Color 1 bit 4 Cursor Color 1 bit 3 Cursor Color 1 bit 2 Cursor Color 1 bit 1 Cursor Color 1 bitO REG 2Fh Ink Cursor Color 1 Register 1 Cursor Color 1 bit 15 Cursor Color 1 bit 14 Cursor Color 1 bit 13 Cursor Color 1 bit 12 Cursor Color 1 bit 11 Cursor Color 1 bit 10 Cursor Color 1 bit 9 Cursor Color 1 bit 8 Acting in pairs Registers 2Ch 2Dh and registers 2Eh 2Fh are used to form the 16 bpp 5 6 5 RGB values for the two user defined colors REG 30h Ink Cursor Start Address Select Register Ink Cursor Start Address bit 7
307. ess 0xC00000 CPU Bus Width 16 bit Clkl 25175 kHz Bus Clk 8000 kHz Memory Page Timing ns 60 ns Memory Type EDO WE Control 2 CAS Refresh time ms 32 ms Tre 104 ns Trp 40 ns Trac 60 ns reuse Mode CAS before RAS Panel Page Single Dual Single Dese half frame unchecked Mono Color Color Format 2 unchecked STN TFT STN EL unchecked Panel Interface 8 bit FPline Polarity Hi FPframe Polarity Hi Dimensions 640 x 480 Frame Rate 60 CRT Page CRT Dimensions 640 x 480 CRT Frame Rate 60 SE de Normal Default Page Display Panel Color Depth 16 bpp Note The above configuration also supports simultaneous display and CRT only modes 1355CFG Configuration Program Issue Date 98 10 30 Epson Research and Development Page 17 Vancouver Design Center Comments e It is assumed that the 1355CFG user is familiar with SED1355 hardware and software Refer to the SED1355 Functional Hardware Specification document number X23A A 001 xx and the SED1355 Programming Notes and Examples document number X23A G 003 xx for details e 1355CFG verifies that the given configuration meets the limitations in the hardware specifica tion Part of this verification process is as follows 1 The divide ratio for the source clock MCIk is determined based on Table 14 3 Example Frame Rates with Ink Disabled from the Functional Hardware Specification According to this table MCIk cannot exceed 40 MHz for 50ns EDO DRAM MCIk cannot
308. etMemSize int seReservedl DWORD val define CLEAR_ME TRUE define DONT_CLEAR_MEM FALSE int int int seSetDisplayMode int device int DisplayMode int ClearMem seSetInit int device seGetId int seReservedl int pld void seGetHalVersion const char pVersion const char pStatus const char pSta tusRevision int int Chip Access a seGetReg int seReservedl int index BYTE pValue seSetReg int seReservedl int index BYTE value nt pe nt nt nt nt H H H H nt pe nt nt nt nt H H H H Misc E seSetBitsPerPixel int seReservedl UINT nBitsPerPixel seGetBitsPerPixel int seReservedl UINT pBitsPerPixel seGetBytesPerScanline int seReservedl UINT pBytes seGetScreenSize int seReservedl UINT width UINT height seHWSuspend int seReservedl BOOL val seSelectBusWidth int seReservedl int width seDelay int seReservedl DWORD Seconds seGetLastUsableByte int seReservedl DWORD LastByte seDisplayEnable int seReservedl BYTE NewState seSplitInit int seReservedl DWORD wScrnlAddr DWORD wScrn2Addr seSplitScreen int nReservedl int WhichScreen long VisibleScanlines seVirtInit int seReservedl DWORD xVirt DWORD yVirt seVirtMove int seReservedl int nWhichScreen DWORD x DWORD y int Power Sav ee seSetPowerSaveMo
309. etup the pointer to the LUT data and reset the LUT index register Then loop writing each of the RGB LUT data elements Ry pLUT LUT8 pRegs 0x24 0 for idx 0 idx lt 256 idx t for rgb 0 rgb lt 3 rgb pRegs 0x26 pLUT pLUT An Register 27 Ink Cursor Control disable ink cursor E pRegs 0x27 0x00 0000 0000 Registers 28 29 Cursor X Position pRegs 0x28 0x00 0000 0000 pRegs 0x29 0x00 0000 0000 Registers 2A 2B Cursor Y Position ef pRegs 0x2A 0x00 0000 0000 pRegs 0x2B 0x00 0000 0000 Registers 2C 2D Ink Cursor Color 0 blue pRegs 0x2C 0x1F 0001 1111 pRegs 0x2D 0x00 0000 0000 Registers 2E 2F Ink Cursor Color 1 green ae pRegs 0x2E OxE0 1110 0000 pRegs 0x2F 0x07 0000 0111 Register 30 Ink Cursor Start Address Select aa SED1355 Programming Notes and Examples X23A G 003 05 Issue Date 99 04 27 Epson Research and Development Vancouver Design Center Page 87 pRegs 0x30 0x00 0000 0000 Jk Register 31 Alternate FRM Register pRegs 0x31 0x00 Register 23 Performance Enhancement display FIFO enabled optimum KA performance The FIFO threshold is set to 0x00 for Kg set the FIFO threshold such as 0x1B 15 16 bpp modes
310. eturn Value ERR_OK operation completed with no problems Note The SolidFill argument is currently unused and is included for future considerations 11 5 6 Hardware Cursor The routines in this section support hardware cursor functionality Several of the calls look similar to normal drawing calls i e seDrawCursorLine however these calls remove the programmer from having to know the particulars of the cursor memory location layout and whether portrait mode 1s enabled Note that hardware cursor and ink layers utilize some of the same registers and are mutually exclusive Programming Notes and Examples SED1355 Issue Date 99 04 27 X23A G 003 05 Page 64 SED1355 X23A G 003 05 Epson Research and Development Vancouver Design Center int selnitCursor int DevID Description Prepares the hardware cursor for use This consists of determining a location in display buffer for the cursor setting cursor memory to the transparent color and enabling the cursor When this call returns the cursor is enabled the cursor image is transparent and ready to be drawn Parameters DevID aregistered device ID Return Value ERR OK operation completed with no problems int seCursorOn int DeviD Description This function enables the cursor after it has been disabled through a call to seCur sorOff After enabling the cursor will have the same shape and position as it did prior to being disabled The exception to the size and position
311. ffer DevID registered device ID State set to ON or OFF respectively to enable or disable the display FIFO Return Value ERR_OK the function completed successfully Note Disabling the display FIFO will force all display data outputs to zero but horizontal and vertical sync pulses and panel power supply are still active As stated earlier the hardware cursor and ink layer are not affected by disabling the FIFO Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Vancouver Design Center Page 53 int seDelay int DevID DWORD Seconds Description Parameters Return Value This function will delay for the number of seconds given in Seconds before returning to the caller This function was originally intended for non PC platforms Because information on how to access the timers was not always immediately available we use the frame rate for timing calculations The SED1355 registers must be initialized for this function to work correctly The PC platform version of seDelay calls the C timing functions and is therefore independent of the register settings DevID registered device ID Seconds time to delay in seconds ERR OK operation completed with no problems ERR_FAILED returned only on non PC platforms when the SED 1355 registers have not been initialized int seGetLinearDispAddr int device DWORD pDispLogicalAddr Description Parameter Return Value Determines
312. fferent processor platforms The HAL also allows for easier porting of programs between SED135X products Integral to the HAL is an information structure HAL_STRUCT that contains configuration data on clocks display modes and default register values This structure combined with the utility 1355CFG EXE allows quick customization of a program for a new target display or environment Using the HAL keeps sample code simpler although some programmers may find the HAL functions to be limited in their scope and may wish to program the SED1355 without using the HAL 11 2 Contents of the HAL_STRUCT The HAL_STRUCT below is contained in the file hal h and is required to use the HAL library typedef struct tagHalStruct char WORD WORD WORD BYTE DWORD DWORD DWORD DWORD WORD WORD WORD WORD WORD WORD WORD szIdString 16 wDetectEndian wSize wDefaul tMode Regs MAX_DISP_MODE MAX_REG 1 dwC1k1 Input Clock Frequency in kHz dwBusClk Bus Clock Frequency in kHz dwRegAddr Starting address of registers dwDispMem Starting address of display buffer memory wPanelFrameRate Desired panel frame rate wCrtFrameRate Desired CRT rate wMemSpeed Memory speed in ns wIrc Ras to Cas Delay in ns wTrp Ras Precharge time in ns wIrac Ras Access Charge time in ns wHostBusWidth Host CPU bus width in bits HAL_STRUCT Within the Regs arr
313. for the register offset does not work on x86 16 bit platforms Copyright c 1998 Epson Research and Development Inc All Rights Reserved Note that only the upper four bits of the LUT are actually used nsigned char LUT8 256 3 Primary and secondary colors xA0 0x00 0x00 0xA0 0x00 0xA0 0xA0 0xA0 0x00 OxA0 0xA0 OXxA0 x50 0x50 0x50 0x00 0x00 OxFO 0x00 OxFO 0x00 0x00 OxFO OxFO OxFO 0x00 0x00 OxFO 0x00 OxFO OxFO OxFO 0x00 OxFO OxFO OxFO u 0x00 0x00 0x00 0x00 0x00 0xA0 0x00 OxA0 0x00 0x00 OxAO OxAO 0 0 Gray shades x30 0x30 0x30 x70 0x70 0x70 xBO OxBO OxBO SPD OxFO OxFO SED1355 Programming Notes and Examples X23A G 003 05 Issue Date 99 04 27 Epson Research and Development Page 81 Vancouver Design Center Black to red 0x00 0x00 0x00 0x10 0x00 0x00 0x20 0x00 0x00 0x30 0x00 0x00 0x40 0x00 0x00 0x50 0x00 0x00 0x60 0x00 0x00 0x70 0x00 0x00 0x80 0x00 0x00 0x90 0x00 0x00 0xA0 0x00 0x00 OxBO 0x00 0x00 0xC0 0x00 0x00 0xD0 0x00 0x00 0xE0 0x00 0x00 0xF0 0x00 0x00 Black to green 0x00 0x00 0x00 0x00 0x10 0x00 0x00 0x20 0x00 0x00 0x30 0x00 0x00 0x40 0x00 0x00 0x50 0x00 0x00 0x60 0x00 0x00 0x70 0x00 0x00 0x80 0x00 0x00 0x90 0x00 0x00 0xA0 0x00 0x00 0xB0 0x00 0x00 0xC0 0x00 0x00 OxDO 0x00 0x00 0xE0 0x00
314. fore programs cannot determine the current cursor ink layer start address by reading register 30h It is suggested that values written to this register be stored elsewhere and used when the current state of this register is required 7 3 4 No Top Left Clipping on Hardware Cursor The SED1355 does not clip the hardware cursor on the top or left edges of the display For cursor shapes where the hot spot is not the upper left corner of the image the hourglass for instance the cursor image will have to be modified to clip the cursor shape 7 4 Examples See Section 12 Sample Code for hardware cursor programming examples SED1355 Programming Notes and Examples X23A G 003 05 Issue Date 99 04 27 Epson Research and Development Vancouver Design Center Page 37 8 Hardware Rotation 8 1 Introduction To Hardware Rotation Most computer displays operate in landscape mode In landscape mode the display is wider than it 1s high For instance a standard display size is 640x480 where the width is 640 pixels and the height 1s 480 pixels Portrait mode rotates the display image clockwise ninety degrees resulting in a display that is taller than it is wide Placing the 640x480 display in portrait mode will yield a display that is now 480 pixels wide and 640 pixels high 8 2 SED1355 Hardware Rotation 8 3 Registers The SED1355 provides hardware support for portrait mode output in 16 and 8 bpp modes The switch to portrait mode carrie
315. form execute 1355play and at the prompt type the command line argument Sets the ISA bus to 8 or 16 bits Only sets up the PAL on the SDU1355 evaluation board There is no readback capability Only supported on a SDU1355 evaluation board for the PC platform Switch 1 1 on the ealuation board must be set to the same bus width as used with this Fills bytes or words w from address 1 to address 2 with the data specified Data can be multiple values e g F 0 20 1 2 3 4 fills O to 0x20 with a repeating pattern of 1 2 3 4 Halts after lines of display This feature halts the display during long read operations to prevent data from scrolling off the display Similar to the DOS MORE command Set to 0 to disable this feature Initializes the chip with the specified configuration The configuration is embedded in the 1355PLA Y utility and can be changed using the 1355CFG utility See the 1355CFG guide document number X23A B 001 xx for instructions on changing the configuration If the output device is specified the user can select LCD CRT or both devices Reads writes Look Up Table LUT values Writes data to the LUT index when data is specified Reads the LUT index when the data is not specified Reads all LUT values Reads current mode information Sets the color depth bpp if bpp is specified Page 4 Usage PC platform at the prompt type 1355play Where displays program version information
316. g the LCD power supply After waiting a pre determined amount of time the software would Disable the LCD signals using the LCD Enable bit in register ODh SED1355 Programming Notes and Examples X23A G 003 05 Issue Date 99 04 27 Page 32 Epson Research and Development Vancouver Design Center 6 3 LCD Enable Disable Power On Enable Sequence The following is the recommended sequence for manually powering up an LCD panel These steps would be used if power supply timing requirements were larger than the timings built into the SED1355 power enable sequence 1 2 Set REG 1Ah bit 3 to 1 Ensure that LCD power is disabled Set REG ODh bit 0 to 1 Turn on the LCD outputs Count x Vertical Non Display Periods x corresponds the power supply discharge time converted to the equivalent vertical non dis play periods Set REG 1Ah bit 3 to 0 This enables LCD Power Power Off Disable Sequence SED1355 X23A G 003 05 The following is the recommended sequence for manually powering down an LCD panel These steps would be used if power supply timing requirements were larger than the timings built into the SED1355 power disable sequence 1 2 Set REG 1Ah bit 3 to 1 disable LCD Power Count x Vertical Non Display Periods x corresponds to the power supply discharge time converted to the equivalent vertical non display periods Set REG ODh bit 0 to 0 turn off the LCD outputs Programming Notes
317. ge 9 Vancouver Design Center During a read cycle OE output enable is driven low A write cycle is specified by driving OE high and driving the write enable signal WE low The cycle can be lengthened by driving WAIT low for the time needed to complete the cycle Figure 2 1 illustrates a typical memory access read cycle on the PC Card bus A 25 0 REG ADDRESS VALID CE1 CE2 OE WAIT D 15 0 Hi Z Hi Z Interfacing to the PC Card Bus Issue Date 99 05 05 DATA VALID Transfer Start Transfer Complete Figure 2 1 PC Card Read Cycle SED1355 X23A G 005 05 Page 10 Epson Research and Development Vancouver Design Center Figure 2 2 illustrates a typical memory access write cycle on the PC Card bus A 25 0 REG ADDRESS VALID CE1 CE2 OE WE WAIT Hi Z Hi Z D 15 0 i DATA VALID Transfer Start Transfer Complete Figure 2 2 PC Card Write Cycle SED1355 Interfacing to the PC Card Bus X23A G 005 05 Issue Date 99 05 05 Epson Research and Development Page 11 Vancouver Design Center 3 SED1355 Host Bus Interface The SED1355 implements a 16 bit PC Card PCMCIA host bus interface which is used to interface to the PC Card bus The PC Card host bus interface is selected by the SED1355 on the rising edge of RESET After releasing reset the bus interface signals
318. gel eRe edge ea ae e Be we RE 26 320x240 Single Panel For Split Screen 28 Screen 1 Line Compare sa otc tk elo o AA a g te eR a 29 Screen 2 Display Start Address ENEE AE a SEN a os 29 Components needed to build 1355 HAL application o a 71 SED1355 Programming Notes and Examples Issue Date 99 04 27 X23A G 003 05 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 Programming Notes and Examples X23A G 003 05 Issue Date 99 04 27 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This guide describes how to program the SED1355 Embedded RAMDAC LCD CRT Controller The guide presents the basic concepts of the LCD CRT controller and provides methods to directly program the registers It explains some of the advanced techniques used and the special features of the SED1355 The guide also introduces the Hardware Abstraction Layer HAL which is designed to simplify the programming of the SED1355 Most SED135x SED137x and SED 138x products support the HAL allowing OEMs to switch chips with relative ease This document will be updated as appropriate Please check the Epson Electronics America Website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs erd epson com Programming Notes and Examples SED1355 Iss
319. guration Epson Research and Development Vancouver Design Center The SED1355 has 16 configuration inputs MD 15 0 which are read on the rising edge of RESET Inputs MD 5 1 are fully configurable on this evaluation board for different host bus selections one eight position DIP switch is provided for this purpose All remaining configuration inputs are hard wired See the SED1355 Hardware Functional Specification document number X23A A 001 xx for more information The following settings are recommended when using the SDU1355BOC with the ISA bus Table 2 1 Configuration DIP Switch Settings Switch Signal Closed 1 Open 0 SW1 1 MD1 SW1 2 MD2 SW1 3 MD3 See Host Bus Selection table below See Host Bus Selection table below SW1 4 MD4 Little Endian Big Endian SW1 5 MD5 Wait signal is active high Wait signal is active low SW1 6 MD13 SW1 7 MD14 SW1 8 MD15 Reserved Table 2 2 Host Bus Selection MD3 SW1 3 MD2 SW1 2 MD1 SW1 1 Host Bus Interface open 0 open 0 open 0 SH 3 SH 4 bus interface open 0 open 0 closed 1 MC68K bus 1 interface e g MC68000 open 0 closed 1 open 0 MC68K bus 2 interface e g MC68030 open 0 closed 1 closed 1 Generic bus interface closed 1 open 0 open 0 Reserved closed 1 open 0 closed 1 MIPS ISA closed 1 closed 1 open 0 PowerPC
320. guration The SED1355 utilities can have their configurations opened changed and saved all from within 1355CFG 1355CFG is designed to work with the SED1355 utilities or any program designed by a software hardware developer using the Hardware Abstraction Layer HAL library The configu ration information can be saved directly into the utility or into a text header file for use by the software hardware developer Note Seiko Epson does not assume liability for any damage done to the display device as a result of software configuration errors SED1355 Supported Evaluation Platforms 1355CFG only runs on a PC system running Windows 9x 1355CFG can edit the executable files for the following SED1355 evaluation platforms e PC system with an Intel 80x86 processor e M68332BCC Business Card Computer board revision B with a Motorola MC68332 processor e M68ECOOOIDP Integrated Development Platform board revision 3 0 with a Motorola M68EC000 processor e SH3 LCEVB board revision B with an Hitachi SH 3 HD6417780 processor Installation Copy the file 1355CFG EXE to a directory on your hard drive that is in the DOS path Usage In Windows 95 double click the following icon 1355Cfg exe Or at the Windows DOS Prompt type 1355cfg 1355CFG Configuration Program SED1355 Issue Date 98 10 30 X23A B 001 02 Page 8 Epson Research and Development Vancouver Design Center 1355CFG Configuration Pages 1355CFG provides a serie
321. he mouse option a valid mouse driver must be loaded e If x and y coordinates are not specified for the Hardware Cursor the Hardware Cursor will be displayed starting in the top left corner position x 0 y 0 1355BMP Demonstration Program SED1355 X23A B 006 03 Page 4 Epson Research and Development Vancouver Design Center Program Messages SED1355 X23A B 006 03 ERROR Could not initialize device The given hardware software setup violates the timing specification as described in the SED1355 Hardware Functional Specification document number X23A A 001 xx ERROR Too many devices registered There are too many display devices attached to the HAL The HAL currently supports only one device ERROR Could not register SED1355F0A device A 1355 device was not found at the configured addresses Check the configuration address using the 1355CFG configuration program ERROR Did not detect SED1355 The HAL was unable to read the revision code register on the SED1355 Ensure that the SED1355 hardware is installed and that the hardware platform has been set up correctly ERROR Insufficient memory for bit per pixel The given display resolution requires more memory than is available to store one complete image Either increase the amount of display memory or select an image with a lower bit per pixel value ERROR Cannot use p option with hardware cursor and ink layer Instead rotate BMP file manually and load with
322. his pin outputs the ready signal RDY MD5 must be pulled high during reset by an external pull up resistor For MC68K Bus 1 this pin outputs the data transfer acknowledge signal DTACK MD5 must be pulled high during reset by an external pull up resistor For MC68K Bus 2 this pin outputs the data transfer and size acknowledge bit 1 DSACK1 MD5 must be pulled high during reset by an external pull up resistor For Generic Bus this pin outputs the wait signal WAIT MD5 must be pulled low during reset by the internal pull down resistor For MIPS ISA Bus this pin outputs the IO channel ready signal IOCHRDY MD5 must be pulled low during reset by the internal pull down resistor For Philips PR31500 31 700 Bus this pin outputs the wait state signal CARDxWAIT MD5 must be pulled low during reset by the internal pull down resistor For Toshiba TX3912 Bus this pin outputs the wait state signal CARDxWAIT MD5 must be pulled low during reset by the internal pull down resistor For PowerPC Bus this pin outputs the transfer acknowledge signal TA MD5 must be pulled high during reset by an external pull up resistor For PC Card PCMCIA Bus this pin outputs the wait signal WAIT MD5 must be pulled low during reset by the internal pull down resistor See Host Bus Interface Pin Mapping for summary See the respective AC Timing diagram for detailed functionality RESET 11 CS Output A
323. his section details the sequences to manually power up and power down the LCD interface Proper LCD power sequencing dictates that there must be a time delay between the time the LCD power is disabled and the time the LCD signals are shut down During power up the LCD signals must be active prior to applying power to the LCD This time interval varies depending on the power supply design The power supply on the SDU1355 Evaluation board requires 0 5 seconds to fully discharge Your power supply design may vary 6 2 Registers REG 0Dh Display Mode Register Deeg Simultaneous Simultaneous 8 Display Display Bit Per Pixel Bit Per Pixel Bit Per Pixel Portrait Moge Option Select Option Select Select Bit 2 Select Bit 1 Select Bit 0 CRT Enable EE Enang Bit 1 Bit 0 LCD Enable normally performs all the required power sequencing Upon setting LCD Enable to 0 the system will begin a series of events which include turning off the LCD power supply waiting for the power supply to discharge and finally turning off the LCD signals REG 1Ah Power Save Configuration Register Power Save LCD Power Suspend Suspend Software Status n a n a n a Disable Refresh Refresh Suspend Select Bit 1 Select BitO Mode Enable LCD Power Disable would be used to manually sequence the events leading to an LCD power down First the program would set LCD Power Disable to 1 to begin dischargin
324. hms 0805 resistor 24 3 R5 R6 R7 150 1 0805 resistor 25 1 R8 2 8K 1 0805 resistor 26 1 R9 1K 1 0805 resistor 27 1 R10 140 1 0805 resistor 28 10 dias e da 15K 0805 resistor 29 1 R22 470K 0805 resistor 30 1 R23 200K Pot 31 1 R24 14K 0805 resistor 32 1 R25 4 7K 0805 resistor 33 2 R28 R27 100K 0805 resistor 34 1 R29 100K Pot 35 1 S1 SW DIP 8 36 1 U1 SED1355F0A 37 1 U2 40MHz oscillator SDU1355B0C Rev 1 0 ISA Bus Evaluation Board User Manual SED1355 Issue Date 98 10 30 X23A G 004 04 Page 18 Epson Research and Development Vancouver Design Center Item Qty board Designation Part Value Description 38 1 U3 MT4C1M16E5DJS 5 50ns self refresh EDO DRAM 39 1 U4 PAL22V10 15 40 1 US RD 0412 Xentek RD 0412 41 1 U6 EPNOO1 Xentek EPNOO1 42 3 U7 U8 U9 74AHC244 43 1 U10 LT1117CM 3 3 5V to 3 3V regulator 800mA SED1355 SDU1355B0C Rev 1 0 ISA Bus Evaluation Board User Manual X23A G 004 04 Issue Date 98 10 30 Page 19 Epson Research and Development 8 Schematic Diagrams Vancouver Design Center SED1355 X23A G 004 04 1 of 4 iagram SEDI355BOC Schematic D Figure 1 98 10 30 9
325. ignore address type bits e PS 0 1 1 0 memory port size is 16 bit e PARE 0 disable parity checking e WP 0 disable write protect e MS 0 1 0 0 select General Purpose Chip Select module to control this chip select e V 1 set valid bit to enable chip select The following options were selected in the option register OR4 AM 0 16 1111 1111 1100 0000 0 mask all but upper 10 address bits SED1355 consumes 4M byte of address space ATM 0 2 0 ignore address type bits CSNT 0 normal CS WE negation ACS 0 1 1 1 delay CS assertion by Y2 clock cycle from address lines es BI 0 do not assert Burst Inhibit SCY 0 3 0 wait state selection this field is ignored since external transfer acknowl edge is used see SETA below SETA 1 the SED1355 generates an external transfer acknowledge using the WAIT line TRLX 0 normal timing EHTR 0 normal timing Interfacing to the Motorola MPC821 Microprocessor SED1355 Issue Date 99 05 05 X23A G 008 03 Page 20 Epson Research and Development Vancouver Design Center 4 6 Test Software BR4 OR4 MemStart DisableReg RevCodeReg Start Loop SED1355 The test software is very simple It configures chip select 4 CS4 on the MPC821 to map the SED1355 to an unused 4M byte block of address space Next it loads the appropriate values into the option register for CS4 and writes the value 0 to the SED1355 registe
326. iling edge note 6 t8 FPLINE pulse trailing edge to FPSHIFT falling edge t14 2 t9 FPSHIFT period 2 Ts t10 FPSHIFT pulse width low 1 Ts t11 FPSHIFT pulse width high 1 Ts t12 UD 7 0 LD 7 0 setup to FPSHIFT falling edge 1 Ts t13 UD 7 0 LD 7 0 hold to FPSHIFT falling edge 1 Ts t14 FPLINE pulse trailing edge to FPSHIFT rising edge 12 Ts 1 Ts pixel clock period memory clock memory clock 2 memory clock 3 memory clock 4 see REG 1 9h bits 1 0 2 min t8min 14Ts 3 t3min REG O4h bits 6 0 1 8 REG O5h bits 4 0 1 8 Ts A t5min REG 04h bits 6 0 1 8 REG O5h bits 4 0 1 8 1 Ts 5 min REG O5H bits 4 0 1 8 20 Ts 6 t7min REG O5H bits 4 0 1 8 11 Ts SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 95 Vancouver Design Center 7 5 10 16 Bit TFT D TFD Panel Timing VNDP VDP la rie gt FPFRAME a AAN FPLINE U Jl L y U R 5 1 G 5 0 B 5 1 UNE ue X XLinEaso FPLINE IT HNDP HDP HNDP gt WM Ka gt j4 FPSHIFT PEA IC Dk A ee DRDY S oo A CA o ee E e AN a oa SE A ee BB A ED oo Note DRDY is used to indicate the first pixel Example Timing for 640x480 panel Figure 7 42 16 Bit TFT D TFD Panel Timing VDP Vertical Display Peri
327. ime REG 22h bits 3 2 01 or 10 0 45t1 3 ns l CAS setup time REG 22h bits 3 2 00 or 10 0 45t1 3 ns CAS setup time REG 22h bits 3 2 01 1t1 3 ns 5 CAS precharge time REG 22h bits 3 2 00 2t1 3 ns CAS precharge time REG 22h bits 3 2 01 or 10 111 3 ns Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 70 7 3 4 FPM DRAM Read Write Read Write Timing Epson Research and Development Vancouver Design Center ti Memory Clock la t2 RAS a t3 t4 e ITA CASH la t8 H t10 ale MA R C1 CS C3 k t12 gt p t13 WE read t14 t15 MD read di d2 pa 8 t16 t17 gt WEH write 118 11 20 MD write di d2 d3 Figure 7 18 FPM DRAM Read Write Timing SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 71 Vancouver Design Center t1 Memory E Clock RAS t3 H A Se tl D CAS t8 S a MA R di C2 C3 C1 C2 C8 t12 t21 t16 t17 WE t14 t15 MD read di E i d3 t18 t19 t20 MD write E d2 d3 Figure 7 19 FPM DRAM Read Write Timing Table 7 18 FPM DRAM Read Write Read Write Timing Symbol Parameter Min Max Units t1 Internal memory clock period 40 ns Random read cycle REG 22h b
328. iming must still be VESA compliant For most panels being run at CRT frequencies is not a problem One side effect of running with these usually slower timings will be a flicker on the panel One limitation of simultaneous display is that should a dual panel be the second display device the half frame buffer must be disabled for correct operation Programming Notes and Examples SED1355 Issue Date 99 04 27 X23A G 003 05 Page 42 Epson Research and Development Vancouver Design Center 10 Identifying the SED1355 The SED1355 can only be identified once the host interface has been enabled The steps to identify the SED1355 are 1 If using an ISA evaluation board in a PC follow steps a and b a Ifareset has occurred confirm that 16 bit mode is enabled by writing to address F80000h b If hardware suspend is enabled then disable the suspend by writing to address F00000h 2 Enable the host interface by writing 00h to REG 1Bh 3 Read REG 00h 4 The production version of the SED1355 will return a value of OCh SED1355 Programming Notes and Examples X23A G 003 05 Issue Date 99 04 27 Epson Research and Development Page 43 Vancouver Design Center 11 Hardware Abstraction Layer HAL 11 1 Introduction The HAL is a processor independent programming library provided by Epson The HAL was developed to aid the implementation of internal test programs and provides an easy consistent method of programming the SED1355 on di
329. inable colors If Color is 2 then the pixel will be transparent and if the value is 3 the pixel will be an inversion of the underlying screen color Currently seDrawCursorCircle does not support the solid fill option DevID aregistered device ID X Y center of the circle in pixels Radius circle radius in pixels Color a two bit 0 to 3 value to draw the circle with SolidFill flag to fill the interior of the circle currently not used Return Value ERR OK operation completed with no problems SED1355 X23A G 003 05 Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Vancouver Design Center 11 5 8 Power Save Page 71 This section covers the HAL functions dealing with the Power Save features of the SED13553 int seSWSuspend int DevID BOOL Suspend Description Parameters Causes the SED1355 to enter software suspend mode When software suspend mode is engaged the display is disabled and display buffer is inaccessible In this mode the registers and the LUT are accessible DevID aregistered device ID Suspend boolean flag to indicate which state to engage enter suspend mode when non zero and return to normal power when equal to zero Return Value ERR_OK operation completed with no problems int seHWSuspend int DevID BOOL Suspend Description Parameters Causes the SED1355 to enter leave hardware suspend mode This option in only supported on
330. ined 11 undefined bits 4 0 Display FIFO Threshold Bits 4 0 These bits specify the display FIFO depth required to sustain uninterrupted display fetches When these bits are all 0 the display FIFO depth is calculated automatically These bits should always be set to 0 except in the following configurations Landscape mode at 15 16 bpp with MCLK PCLK Portrait mode at 8 16 bpp with MCLK PCLK When in the above configurations a value of 1Bh should be used Note The utility 1355CFG will given the correct configuration values automatically generate the correct values for the Performance Enhancement Registers 8 2 8 Look Up Table Registers Look Up Table Address Register REG 24h RW LUT Address LUT Address LUT Address LUT Address LUT Address LUT Address LUT Address LUT Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Vancouver Design Center bits 7 0 Page 119 LUT Address Bits 7 0 These 8 bits control a pointer into the Look Up Tables LUT The SED1355 has three 256 posi tion 4 bit wide LUTs one for each of red green and blue refer to Look Up Table Architecture for details This register selects which LUT entry is read write accessible through the LUT Data Register REG 26h Writing the LUT Address Register automatically sets the pointer to
331. ing loading default values into the color Look Up Tables LUTs DevID a valid registered device ID DisplayMode the HAL_STRUCT register set to use DISP_MODE_LCD DISP_MODE_CRT or DISP_MODE_SIMULTANEOUS flags Can be set to one or more flags Each flag added by using the logical OR command Do not add mutually exclusive flags Flags can be set to 0 to use defaults DONT_CLEAR_MEM default do not clear memory CLEAR_MEM clear display buffer memory DISP_FIFO_OFF turn off display FIFO blank screen except for cursor or ink layer DISP_FIFO_ON default turn on display FIFO ERR OK no problems encountered ERR PAI PD unable to complete operation Occurs as a result of an invalid register in the HAL_STRUCT seDisplayFifo for enabling disabling the FIFO seSetDisplayMode DevID DISP_MODE_LCD CLEAR_MEM DISP_FIFO_OFB The above example will initialize for the LCD and then clear display buffer memory and blank the screen The advantage to this approach is that afterwards the appli cation can write to the display without showing the image until memory is completely updated the application would then call seDisplayFIFO DevID ON See note from seSetInit Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Vancouver Design Center 11 5 1 General HAL Support Page 49 General HAL support covers the miscellaneous functions There is usually no more than one or two functions devot
332. int seSplitScreen int DevID int WhichScreen long VisibleScanlines Description Parameters Return Value Note Changes the relevant registers to adjust the split screen according to the number of visible lines requested WhichScreen determines which screen screen or screen 2 to change The smallest screen 1 can be set to is one line This is due to the way the register values are used internally on the SED1355 Setting the line compare register to zero results in one line of screen being displayed followed by screen 2 DevID registered device ID WhichScreen must be set to 1 or 2 or use the constants SCREEN or SCREEN2 to identify which screen to base calculations on VisibleScanlines number of lines to show for the selected screen ERR OK operation completed with no problems ERR_HAL_BAD_ARG argument VisibleScanlines is negative or is greater than vertical panel size or WhichScreen is not SCREEN or SCREEN 2 seSplitInitQ must be called before calling seSplitScreen Changing the number of lines for one screen will also change the number of lines in the other screen e g increasing screen 1 lines by 5 will reduce screen 2 lines by 5 int seVirtln Description Parameter Return Value Note it int DevID DWORD VirtX DWORD VirtY This function prepares the system for virtual screen operation The programmer passes the desired virtual width in pixels as VirtX When the routine returns VirtY will c
333. ion Display mode the resolution and color depth affect power consumption the higher the resolution color depth the higher the consumption Internal CLK divide internal registers allow the input clock to be divided before going to the internal logic blocks the higher the divide the lower the power consumption There are two power save modes in the SED1355 Software and Hardware SUSPEND The power consumption of these modes is affected by various system design variables DRAM refresh mode CBR or self refresh self refresh capable DRAM allows the SED1355 to disable the internal memory clock thereby saving power CPU bus state during SUSPEND the state of the CPU bus signals during SUSPEND has a substantial effect on power consumption An inactive bus e g BUSCLK low Addr low etc reduces overall system power consumption CLKI state during SUSPEND disabling the CLKI during SUSPEND has substantial power savings SED1355 X23A G 006 02 Page 4 Epson Research and Development Vancouver Design Center 1 1 Conditions Table 1 1 SED1355 Total Power Consumption below gives an example of a specific environment and its effects on power consumption Table 1 1 SED1355 Total Power Consumption Test Condition Total Power Consumption Gray Shades Vop 3 3V Colors S Power Save Mode ctive SA BUSASMHZ Software Hardware Input Clock 6MHz Black and White 18 6mW 1 LCD Panel 320x240 4 bit Sing
334. ion automatically 6 2 Non ISA Bus Support This evaluation board is specifically designed to support the standard 16 bit ISA bus However the SED 1355 directly supports many other host bus interfaces Header strips H1 and H2 have been provided and contain all the necessary I O pins to interface to these buses See Section 4 CPU Bus Interface Connector Pinouts on page 10 Table 2 1 Configuration DIP Switch Settings on page 8 and Table 2 3 Jumper Settings on page 8 for details When using the header strips to provide the bus interface observe the following e All I O signals on the ISA bus card edge must be isolated from the ISA bus do not plug the card into a computer Voltage lines are provided on the header strips e For the ISA bus a 22V10 PAL U4 socketed is currently used to provide the SED1355 CS pin 4 M R pin 5 and other decode logic signals This functionality must now be provided externally Remove the PAL from its socket to eliminate conflicts resulting from two different outputs driving the same input Refer to Table 2 2 Host Bus Selection on page 8 for connection details SDU1355B0C Rev 1 0 ISA Bus Evaluation Board User Manual SED1355 Issue Date 98 10 30 X23A G 004 04 Page 14 Epson Research and Development Vancouver Design Center 6 3 DRAM Support 6 4 Decode Logic The SED1355 supports 256K x 16 as well as 1M x 16 FPM EDO DRAM in symmetrical and asymmetrical formats The SD
335. it 0 Ke Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG OAh VERTICAL NON DISPLAY PERIOD REGISTER RW REG 1Bh MISCELLANIOUS REGISTER RW REG 2Dh INK CuRSOR COLOR 0 REGISTER 1 RW a Du a Host Half Frame VNDP Wa Vertical Non Display Period VNDP REG 1 Interface n a n a n a na n a n a Buffer Cursor Color 0 Status RO Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Disable Disable Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 REG 0Bh VRTC FPFRAME START POSITION REGISTER RW REG 1Ch MD CONFIGURATION READBACK REGISTER 0 RO REG 2Eh INK CURSOR COLOR 1 REGISTER 0 RW r j VRTC FPFRAME Start Position REG 1 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MDO Cursor Color 1 n a na Bit 5 Bit 4 Bit3 Bit 2 Bit 1 Bito Status Status Status Status Status Status Status Status Bit4 Bit3 REG 1Dh MD CONFIGURATION READBACK REGISTER 1 RO VRTC Polarity Slct REG ODh DISPLAY MODE REGISTER REG 0Ch VRTC FPFRAME PULSE Wi IDTH REGISTER FPFRAME Polarity Slct Bit 2 RW VRTC FPFRAME Pulse Width REG 1 Bit 1 Bit 0 RW Hardware Portrait Mode Enable REG 0Eh SCREEN 1 LINE COMPARE REGISTER 0 Simultaneous Display 5 Option Select Bit 1 Bit 0 Bit per pixel Seleci Bit 1 t CRT Enable LCD Enable Bit7 Bit 6 Bit 5 Bit 4 Screen 1 Line Compare Bit 3 REG OFh SCREEN 1 LINE COMPARE REGISTER 1 RW MD14 Status MD13 Status MD12 Status MD11 Status MD10 Status MD9 Status MD8 Status
336. it 4 Position Bit3 Position Bit 2 Position Bit 1 Position Bit O bits 4 0 HRTC FPLINE Start Position Bits 4 0 For CRT and TFT D TFD these bits specify the delay from the start of the horizontal non display period to the leading edge of the HRTC pulse and FPLINE pulse respectively HRTC FPLINE start position pixels HRTC FPLINE Start Position Bits 4 0 1 x 8 2 Note This register must be programmed such that REG 05h 1 gt REG 06h 1 REG 07h bits 3 0 1 HRTC FPLINE Pulse Width Register REG 07h RW HRTC HRTC HRTC HRTC GE ere nla nja FPLINE FPLINE FPLINE FPLINE SS SE Pulse Width Pulse Width Pulse Width Pulse Width Bit 3 Bit 2 Bit 1 Bit 0 bit 7 HRTC Polarity Select This bit selects the polarity of the HRTC pulse to the CRT When this bit 1 the HRTC pulse is active high When this bit 0 the HRTC pulse is active low bit 6 FPLINE Polarity Select This bit selects the polarity of the FPLINE pulse to TFT D TFD or passive LCD When this bit 1 the FPLINE pulse is active high for TFT D TFD and active low for passive LCD When this bit 0 the FPLINE pulse is active low for TFT D TFD and active high for passive LCD Table 8 4 FPLINE Polarity Selection FPLINE Polarity Select Passive LCD FPLINE Polarity TFT D TFD FPLINE Polarity 0 active high active low 1 active low active high bits 3 0 HRTC FPLINE Pulse Width Bits 3 0 For CRT and TFT D T
337. it 6 5 00 5t1 ns t2 Random read cycle REG 22h bit 6 5 01 4t1 ns Random read cycle REG 22h bit 6 5 10 3t1 ns RAS precharge time REG 22h bits 3 2 00 2t1 3 ns t3 RAS precharge time REG 22h bits 3 2 01 1 45t1 3 ns RAS precharge time REG 22h bits 3 2 10 1t1 3 ns RAS to CAS delay time REG 22h bit 4 1 and S bits 3 2 00 or 10 ASUS ns RAS to CAS delay time REG 22h bit 4 0 and A a Plis 3 2 00 or 10 eyes ne RAS to CAS delay time REG 22h bit 4 1 and un 3 Ag bits 3 2 01 RAS to CAS delay time REG 22h bit 4 0 and oH 3 sig bits 3 2 01 t5 CAS precharge time 0 45t1 3 ns t6 CAS pulse width 0 45t1 3 ns t7 RAS hold time 0 45t1 3 ns Row address setup time REG 22h bits 3 2 00 2t1 3 ns t8 Row address setup time REG 22h bits 3 2 01 1 45t1 3 ns Row address setup time REG 22h bits 3 2 10 1t1 3 ns Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 72 Epson Research and Development Vancouver Design Center Table 7 18 FPM DRAM Read Write Read Write Timing Symbol Parameter Min Max Units Row address hold time REG 22h bits 3 2 00 or tl 3 ns t9 10 Row address hold time REG 22h bits 3 2 01 0 45 1t1 3 ns t10 Column address setup time 0 45 t1 3 ns t11 Column address hold time 0 45 t1 3 ns Read Command Setup REG 22h bit 4 0 and bits 4 45 11 3 h
338. it Per Pixel 65536 Colors 16 Gray Shades 14 4 Eook Up Table LUT coins ri Sr ae a EN Ee Nu de Ne 15 4 1 Look Up Table Registers s s s m sovou sa eee LS 4 2 Look Up Table Organization 2 2 ee 16 5 Advanced Techniques 2 00 eee n 23 5 1 Virtual Display A Deel EA RN ES 24 ch Examples ciar A A hy oh ee pt bee A a A E oe ale 24 5 2 Panning and Scrolling o sen sieo e son su e orar a e 2 25 521 Registers serge bh eee BADER Se Ae does BER A aye he ee 26 322 EXAMP a di A a a A EE 27 313 SphtScereen 22k 2 lee a A ele da A es Zoot A e ZO 22 Registers i Sedo Wo A Sas wee Rte RAS CEG OE ad eA Soke erat ay Ale Bias Bt 29 5 3 2 Examples osu Swit hte wei SAY ee ee ee AE nie RE OA es 30 6 LCD Power Sequencing and Power Save Modes 2 2 0 0002 eee eee 31 6 1 Introduction to LCD Power Sequencing a a a eee Al 6 2 URBBISTEIS oe te ee ee ee A a E a Ae e BL 6 3 gt LED Enable Disable p lt a e aa Boe A EO Ao Bg aM eee S32 7 Hardware Cursor s aa ace See a A Sle areca Qe eae a as 33 Fels Introduction e ew Sen A eh we BOP al es oe A cw Boe A 6133 T2 Registers is oie d e ORS A BR A Aes eo a A ed Ae bod a Aes 2 33 TS EMOTICONOS E di Ba es AOR Ae WR A A Wicd ee de BE 7 3 1 Updating Hardware Cursor Addresses 36 7 3 2 Reg 29h And Reg 2Bb EEN RR AS Soe Ba Re eek ROR A 36 133 Ree BOB sees eh ee bee A eee eee ee EES A 36 7 3 4 No Top Left Clipping on H
339. it color LCD interface for single panel single drive displays 8 bit monochrome or 8 16 bit color LCD interface for dual panel dual drive displays Direct support for 9 12 bit TFT D TFD 18 bit TFT D TFD is supported to 64K colors 16 bit data Direct CRT support to 64K colors using the SED1355 embedded RAMDAC Up to 16 shades of gray using Frame Rate Modulation FRM on monochrome passive LCD panels Up to 4096 colors on color passive LCD panels three 256x4 Look Up Tables LUT are used to map 1 2 4 8 bpp modes into these colors 15 16 bpp modes are mapped directly using the four most significant bits of the red green and blue colors Up to 64K colors on TFT D TFD and CRT three 256x4 Look Up Tables are used to map 1 2 4 8 bpp modes into 4096 colors 15 16 bpp modes are mapped directly e On board 2M byte EDO DRAM display buffer e On board adjustable LCD bias voltage power supply e SmallTypeZ x 2 form factor requires two side by side SmallTypeZ slots 2 1 SED1355 Embedded RAMDAC LCD CRT Controller The SED1355 is a low cost low power color monochrome LCD CRT controller with an embedded RAMDAC capable of interfacing to a wide range of CPUs and LCD displays The SED1355 supports LCD interfaces with data widths up to 16 bits Using Frame Rate Modulation FRM it can display 16 shades of gray on monochrome panels up to 4096 colors on passive panels and 64K colors on active matrix TFT D TFD CRT support is handled through the
340. ition bit 7 Cursor X Cursor X Cursor X Cursor X Cursor X Cursor X Cursor X Position Position Position Position Position Position Position bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit O REG 29h Cursor X Position Register 1 Reserved Cursor X Cursor X n a n a n a n a n a Position Position bit 9 bit 8 Registers 28h and 29h control the horizontal position of the hardware cursor The value in this register specifies the location of the left edge of the cursor When ink mode is selected these registers should be set to zero Cursor X Position bits 9 0 determine the horizontal location of the cursor With 10 bits of resolution the horizontal cursor range is 1024 pixels REG 2Ah Cursor Y Position Register 0 Cursor Y Position bit 7 Cursor Y Cursor Y Cursor Y Cursor Y Cursor Y Cursor Y Cursor Y Position bit 6 Position bit5 Position bit 4 Position bit 3 Position bit 2 Position bit 1 Position bit O REG 2Bh Cursor Y Position Register 0 Reserved Cursor Y Cursor Y wa na na ma na Position bit9 Position bit 8 SED1355 X23A G 003 05 Registers 2Ah and 2Bh control the vertical position of the hardware cursor The value in this register specifies the location of the left edge of the cursor When ink mode is selected these registers should be set to zero Cursor Y Position bits 9 0 determine the location of the cursor With ten bits of r
341. ivs Seq DEI avs ary Se so zys Le 7 Sea MO give 7 Se EE vive em SK EE nav HX UND AGHHOO lt 7 HU mito OFT nert oas L I j E smo las L a X T ACL zas E Ova eas LE J o SH ns vas gt D el BEH sas ut H ast gas aa Lee Dez zas 3 D9A H ano OHOOW LX er EN Ob H SS SEL lt gt isrola El v E Zz 9 S y E z T SDU1355B0C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 98 10 30 EES 8661 yz WORN epson aed a Jaquin quawnoog azig peog uopenjeag sng YSI 908SS 1 as Vancouver Design Center Epson Research and Development 3u quewdojeneg yoreesay uosda leroy Isrola 2x2 k n gt SA k n x oe x pam son breng um 89 88 LIVM ia ez 0000 NEO O NT j 1as34 EA EU Pra PT EI zra T DI ora Orv ed 8d Y ke 97 E sd va a aw Ed za T Ta Kai H anro Ki G D9A ES MOZO om FrSOUNEL EI EI UJOVIH Zar pve EAZ evz ZAZ eve LAZ lve H vl EAL evi ZAL D LAL Lei HMC ELSE ND BEIER 14IHSdW UIOVIH bar ene VOYNOD vrzOHV L aNd Dz ODA EI HOGA YAZ vyz EAZ evz ZAZ BG LAZ lve PAL rei EAL EvL ZAL D LAL Lei Stivdds St UNO
342. l A C Timing Format 1 Symbol Parameter Min Typ Max Units t1 FPFRAME setup to FPLINE pulse trailing edge note 2 t2 FPFRAME hold from FPLINE pulse trailing edge 14 Ts note 1 t3 FPLINE pulse width 9 Ts t4 FPLINE period note 3 t5a FPSHIFT2 falling edge to FPLINE pulse leading edge note 4 t5b FPSHIFT falling edge to FPLINE pulse leading edge note 5 t6 FPLINE pulse trailing edge to FPSHIFT2 rising FPSHIFT falling t9 t10 Ts edge t7 FPSHIFT2 FPSHIFT period 4 Ts t8a FPSHIFT falling edge to FPLINE pulse trailing edge note 6 t8b FPSHIFT2 falling edge to FPLINE pulse trailing edge note 7 t9 FPLINE pulse trailing edge to FPSHIFT rising edge 20 Ts t10 FPSHIFT2 FPSHIFT pulse width high 2 Ts t11 FPSHIFT2 FPSHIFT pulse width low 2 Ts t12 UD 3 0 LD 3 0 setup to FPSHIFT2 rising FPSHIFT falling edge 1 Ts t13 UD 3 0 LD 3 0 hold from FPSHIFT2 rising FPSHIFT falling edge 1 Ts 1 Ts pixel clock period memory clock memory clock 2 memory clock 3 memory clock 4 see REG 1 9h bits 1 0 2 tlmin t4min 14Ts 3 t4min REG 04h bits 6 0 1 8 REG O5h bits 4 0 1 8 Ts 4 t5min REG 05h bits 4 0 1 8 27 Ts 5 Bmin REG O5h bits 4 0 1 8 29 Ts 6 t8min REG O5h bits 4 0 1 8 20 Ts 7 t8min REG O5H bits 4 0 1 8 18 Ts SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18
343. l Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Microsoft and Windows are registered trademarks of Microsoft Corporation Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 Interfacing to the NEC VR4121 Microprocessor X23A G 011 03 Issue Date 99 05 05 Epson Research and Development Page 3 Vancouver Design Center Table of Contents UN tg UO e EE KEE A A A A ENEE e 7 2 Interfacing to the NEC VR4121 8 2 1 The NEC VR4121 System Bus 0 2 2 8 ZERE CONEEVISW ar ds A a ad olds ele a ey AE dd 8 2 1 2 LCD Memory Access Cycles 9 3 SED1355 Host Bus Interface es 10 3 1 Host Bus Interface Pin Mapping e 10 3 2 Host Bus Interface Signal Descriptions 0 21 4 VR4121 to SED1355 Interface 2 2 lt lt 12 4 1 Hardware Description a ee LA 42 SED1355 Configuration oa ay a a ee A oe ee we OP ue e LN 4 3 NEC VR4121 Configuration e 18 4 4 Memory Mapping and Aliasing 14 SoftWare zes ds dica di eii le Bb ee ar Aes aa ee de da ae 15 ReTerentes sata aa AAA A a AAA 16 6 1 Documents ce 4 05 a a a a A a a eS ee 16 6 2 DoeumentSources il a a a e aaa a a TO 7 Techhical Support i a iore EEN ENEE ee ee A E er e 17 7 1 Epson LCD CRT Controllers SED1355 e 17
344. l Specification document number X23 A A 001 xx SED1355 1355CFG Configuration Program X23A B 001 02 Issue Date 98 10 30 Epson Research and Development Page 13 Vancouver Design Center Initial Page gt 1355Cfg 1355test exe General Memory Panel CRT Default Display Color Depth amp Panel C 1 bpp C 8bpp ei C 2bpp C 15bpp C 4bpp 16bpp NOTE These items are hints to the HAL After a program starts the display surface or color depth may change These settings are to ensure that initial register values meet timing specifications Open Save As Exit Figure 5 Default Page The Default Page allows the user to select the following settings Initial Page Select the default display device Three display modes LCD Display CRT and Simultaneous are saved but the SED1355 software initializes the registers based on the default mode Color Depth Select the default color depth 1355CFG Configuration Program SED1355 Issue Date 98 10 30 X23A B 001 02 Page 14 Epson Research and Development Vancouver Design Center Open Dialog Box Open 21 x Lookin intel el le E 1355test exe pR Fle pame _ Files of type Executable Files exe sl D Cancel When the OPEN button is pressed on the main window the Open Dialog Box is shown 1355CFG will read the configuration values from a specific EXE file for Intel platforms and from a specific
345. lay ALE gt AB20 FPLINE kb FPLINE CARDREG P AB19 DRDY MOD Caen p nore SED1355F0A CARDIOWR KAP fo foe CARDxCSH P weg pene CARDxCSL Kl RDWR RED GREEN BLUE py RD P RDF HRTC A CRT WE Kl WEO Display CARDxWaAIT W WAIT ao vaTc ____ DCLKOUT Kl BUSCLK 22 53 H RESET P RESET EE 6 8 IREF wn IREF soe SEEEER S CG 3 3 1Mx16 FPM EDO DRAM Figure 3 8 Typical System Diagram Toshiba TX3912 Bus SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 19 Vancouver Design Center Power Oscillator Management PowerPC BUS A 0 10 P Decoder O KN MIRA E FPDAT 15 8 p UDO E FPDAT 7 0 ku LD 7 0 Lp Decoder 0 cS E FPSHIET p FesHiFT 4 8 16 bit A t1 31 K AB 20 0 LCD D O 15 4 Kl DB 15 0 FPFRAME FPFRAME Display FPLINE FPLINE Blt 4 WE1 DRDY MOD TS P BS nomna da SED1355FOA coo TSIZO KM RD TSIZ1 KN wem RED GREEN BLUE __ TAH 4 WAITH HRTC pp CRT VETE Display E gt CLKOUT P BUSCLK S E 553 RESET KH RESET SSES DI IREF sidad lt a gt 256Kx16 FPM EDO DRAM Figure 3 9 Typical System Diagram Power PC Bus
346. le Monochrome 4 Gray Shades 20 3mW 4 29mw 0 33uWw 16 Gray Shades 22 8mW Input Clock 6MHz 4 Colors 22 3mW 2 LCD Panel 320x240 8 bit Single Color 16 Colors 25 3mW 4 32mw 0 33uWw 256 Colors 29 0mW Input Clock 25MHz 8 SG Black and White 58 5mW 1 2 3 LCD Panel 640x480 8 bit Dual Monochrome 16 Gray Shades 71 7mW 5 71mW 0 33uW Input Clock 25MHz 16 Colors 93 4mW 4 LCD Panel 640x480 16 bit Dual Color 256 Colors 98 1mW 5 74mw 0 331 W 64K Colors 101 3mW 16 Colors 221 1mW BE 256 Colors 234 0mW 6 34mW 0 33uW a 64K Colors 237 3mW Note 1 Conditions for Software SUSPEND e CPU interface active signals toggling e CLKI active e Self Refresh DRAM 2 Conditions for Hardware SUSPEND e CPU interface inactive high impedance e CLKI stopped e Self Refresh DRAM 2 Summary The system design variables in Section 1 SED1355 Power Consumption and in Table 1 1 SED 1355 Total Power Consumption show that SED1355 power consumption depends on the specific implementation Active Mode power consumption depends on the desired CPU perfor mance and LCD frame rate whereas Power Save Mode consumption depends on the CPU Interface and Input Clock state In a typical design environment the SED1355 can be configured to be an extremely power efficient LCD Controller with high performance and flexibility SED1355 Power Consumption X23A G 006 02 Issue Date 98 10 30 EPSON SED1355 Embedded RAM
347. led functionality MD 15 0 IO 34 36 38 40 42 44 46 48 49 47 45 43 41 39 37 35 C TS 1D Hi Z Bi Directional memory data bus During reset these pins are inputs and their states at the rising edge of RESET are used to configure the chip see Summary of Configuration Options Internal pull down resistors typical values of 100KQ 180KQ at 5V 3 3V respectively pull the reset states to 0 External pull up resistors can be used to pull the reset states to 1 See Memory Interface Timing for detailed functionality Hardware Functional Specification Issue Date 99 05 18 SED1355 X23A A 001 11 Page 30 Epson Research and Development Vancouver Design Center Table 5 2 Memory Interface Pin Descriptions Continued Pin Name Type Pin Cell RESET State Description MA 8 0 58 60 62 64 66 67 65 63 61 CO Output Multiplexed memory address see Memory Interface Timing for functionality MA9 56 C TS Output This is a multi purpose pin e For 2M byte DRAM this is memory address bit 9 MA9 e For asymmetrical 512K byte DRAM this is memory address bit 9 MA9 e For symmetrical 512K byte DRAM this pin can be used as general purpose IO pin 3 GPIO3 Note that unless configured otherwise this pin defaults to an input and must be driven to a valid logic level See Memory Interface Pin Mapping for summary See
348. lse width high 6 6 ns D Clock pulse width low 6 6 ns t4 A 20 0 M R RD WR setup to CKIO 3 3 ns t5 A 20 0 M R RD WR hold from CS 0 0 ns t6 BSF setup 4 4 ns t7 BS hold 1 1 ns t8 CSn setup 4 4 ns 197 Falling edge RD to D 15 0 driven 0 0 ns t10 Rising edge CSn to WAIT tri state 5 25 2 5 10 ns t11 Falling edge CSn to WAIT driven 0 15 0 10 ns t12 CKIO to WAIT delay 4 20 3 6 12 ns t13 D 15 0 setup to 2 4 CKIO after BS write cycle 10 10 ns t14 D 15 0 hold write cycle 0 0 ns t15 D 15 0 valid to WAIT rising edge read cycle 0 0 ns t16 Rising edge RD to D 15 0 tri state read cycle 5 25 2 5 10 ns 2 Two Software WAIT States Required gt One Software WAIT State Required 1 Ifthe SED1355 host interface is disabled the timing for WAIT driven is relative to the falling edge of CSn or the first positive edge of CKIO after A 20 0 M R becomes valid whichever one is later 2 Ifthe SED1355 host interface is disabled the timing for D 15 0 driven is relative to the falling edge of RD or the first positive edge of CKIO after A 20 0 M R becomes valid whichever one is later SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 45 Vancouver Design Center 7 1 3 MC68K Bus 1 Interface Timing e g MC68000 t1 t2 13 ox E EI t4 15 Lei 4 A 20 1 M R t6 A Cen t17
349. mory read cycle on the Power PC system bus SSA LI Tair O A Kr TS TA Ajo 31 Xo A RD WR ALA Figure 2 1 Power PC Memory Read Cycle Interfacing to the Motorola MPC821 Microprocessor SED1355 Issue Date 99 05 05 X23A G 008 03 Page 10 Epson Research and Development Vancouver Design Center 2 1 3 SED1355 SYSCLK Wf S TS TA A 0 31 X ROMA YA OO TSIZ 0 1 AT O 3 A D 0 31 A Valid XXX Transfer Start Wait States Transfer Next Transfer Complete Starts Figure 2 2 Power PC Memory Write Cycle on page 10 illustrates a typical memory write cycle on the Power PC system bus Figure 2 2 Power PC Memory Write Cycle If an error occurs TEA Transfer Error Acknowledge is asserted and the bus cycle is aborted For example a peripheral device may assert TEA if a parity error is detected or the MPC821 bus controller may assert TEA if no peripheral device responds at the addressed memory location within a bus time out period For 32 bit transfers all data lines D 0 31 are used and the two low order address lines A30 and A31 are ignored For 16 bit transfers data lines D 0 15 are used and address line A30 is ignored For 8 bit transfers data lines D 0 7 are used and all address lines A 0 31 are used Note This assumes that the Power PC core is
350. mpt type 1355bmp bmpfile t reg cursor ink x n y n buffer crt lcd mouse noclear noinit p v Where bmpfile filename of a windows format bmp image t reg regular display image cursor hardware cursor image ink ink layer image x n n Starting cursor x position default position 0 y n n Starting cursor y position default position 0 buffer enable double buffering image not displayed until completely loaded in memory crt displays the image on a CRT 1lcd displays the image on an LCD panel 1355BMP Demonstration Program SED1355 Issue Date 98 10 30 X23A B 006 03 Page 2 Epson Research and Development Vancouver Design Center mouse use mouse to move hardware cursor press ESC to exit program noclear don t clear display buffer memory noinit skips register initialization p portrait mode not available for hardware cursor or ink layer images Iv verbose mode provides information about the displayed images displays the Help screen Note 1355BMP will automatically finish execution and return to the prompt Hardware Cursor Ink Layer 1355BMP requires the BMP images for the Hardware Cursor and the Ink Layer to be stored in specific formats The Hardware Cursor BMP image must have a color depth of four bit per pixel and be 64x64 pixels in resolution The Ink Layer BMP image must have a color depth of four bit per pixel and be the same resolution as the displayed image Both image
351. n e Technical manual includes Data Sheet Application Notes and Programmer Reference Software e User Utilities OEM Utilities e Evaluation Software e To obtain these programs contact Application Engineering Support Application Engineering Support Engineering and Sales Support is provided by Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http www epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 TECHNICAL MANUAL Issue Date 99 10 06 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 Taiwan R O C Epson Taiwan Technology 8 Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 SED1355 X23A Q 001 09 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 TECHNICAL MANUAL X23A Q 001 09 Issue Date 99 10 06 Epson Research and Development Va
352. n for details Memory Address Offset Register 0 REG 16h RW Memory Memory Memory Memory Memory Memory Memory Memory Address Address Address Address Address Address Address Address Offset Bit 7 Offset Bit 6 Offset Bit 5 Offset Bit 4 Offset Bit 3 Offset Bit 2 Offset Bit 1 Offset Bit 0 Memory Address Offset Register 1 REG 17h RW Memory Memory Memory n a n a n a n a n a Address Address Address Offset Bit10 Offset Bit 9 Offset Bit 8 REG 16h bits 7 0 REG 17h bits 2 0 SED1355 X23A A 001 11 Memory Address Offset Bits 10 0 These bits form the 11 bit address offset from the starting word of line n to the starting word of line n 1 This value is applied to both Screen 1 and Screen 2 Note that this value is in words A virtual image can be formed by setting this register to a value greater than the width of the dis play The displayed image is a window into the larger virtual image See Section 10 Display Configuration for details Hardware Functional Specification Issue Date 99 05 18 Epson Research and Development Vancouver Design Center Page 111 bits 7 4 bits 3 0 Pixel Panning Register REG 18h RW Screen 2 Screen 2 Screen 2 Screen 2 Screen 1 Screen 1 Screen 1 Screen 1 Pixel Panning Pixel Panning Pixel Panning Pixel Panning Pixel Panning Pixel Panning Pixel Panning Pix
353. n 8 bpp mode scroll down up by 2 lines e Increment decrement Display Start Address register in 16 bpp mode scroll down up by 1 line e Increment decrement Pixel Panning register in 8 bpp or 16 bpp mode scroll down up by 1 line Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 138 Epson Research and Development Vancouver Design Center 13 3 Physical Memory Requirement Because the programmer must now deal with a virtual display the amount of image buffer required for a particular display mode has increased The minimum amount of image buffer required is Minimum Required Image Buffer bytes 1024 x H x 2 for 16 bpp mode 1024 x H for 8 bpp mode For single panel the required display buffer size is the same as the image buffer required For dual panel the display buffer required is the sum of the image buffer required and the half frame buffer memory required The half frame buffer memory requirement is Half Frame Buffer Memory bytes W x H 4 for color mode W x H 16 for monochrome mode The half frame buffer memory is always located at the top of the physical memory For simplicity the hardware cursor and ink layer memory requirement is ignored The hardware cursor and ink layer memory must be located at 16K byte boundaries and it must not overlap the image buffer and half frame buffer memory areas Even though the virtual display is 1024x1024 pixels the actual panel window is al
354. n Board User Manual Issue Date 98 10 30 Page 11 SED1355 X23A G 004 04 Page 12 5 Host Bus Interface Pin Mapping Table 5 1 CPU Interface Pin Mapping Epson Research and Development Vancouver Design Center SED SH 3 SH 4 MOGE mear Generic MIPS ISA PowerPC PCMCIA Pin Names Bus 1 Bus 2 AB20 A20 A20 A20 A20 A20 LatchA20 A11 A20 AB 16 13 A 19 13 A 19 13 A 19 13 A t9 13 A t9 13 SA 19 13 A 12 18 A 19 13 AB 12 1 A t2 1 A t2 1 A 12 1 A 12 1 A 12 1 SA 12 1 A t9 30 A t2 1 ABO AO AO LDS AO AO SAO A31 AO DB 15 0 D 15 0 D 15 0 D 15 0 D 31 16 D 15 0 SD 15 0 D O 15 D 15 0 WE1 WE1 WE1 UDS DS WE1 SBHE Bl CE2 M R External Decode CS External Decode BUSCLK CKIO CkKIO CLK CLK BCLK CLK CLKOUT CLKI BS BS BS AS AS VDD VDD TS VDD RD WR RD WR RD WR R W R W RD1 Vop RD WR CE1 RD RD RD Vop SIZ1 RDO MEMR TSIZO OE WEO WEO WEO Vop SIZO WEO MEMW TSIZ1 WE WAIT WAIT RDY DTACK DSACK1 WAIT IOCHRDY TA WAIT RESET RESET RESET RESET RESET RESET peer RESET EE SED1355 X23A G 004 04 SDU1355B0C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 98 10 30 Epson Research and Development Page 13 Vancouver Design Center 6 Technical Description 6 1 ISA Bus Support The SDU1355B0C directly supports the 16 bit ISA b
355. n Ku pw A 90 Vin VIL 10 tr gt L ty T T osc Figure 7 9 Clock Input Requirement Table 7 9 Clock Input Requirements for BUSCLK using Philips local bus Symbol Parameter Min Max Units Tosc Input Clock Period 13 3 ns town Input Clock Pulse Width High 6 ns tow Input Clock Pulse Width Low 6 ns t Input Clock Fall Time 10 90 ns t Input Clock Rise Time 10 90 ns Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 58 Epson Research and Development Vancouver Design Center 7 1 9 Toshiba Interface Timing e g TX3912 t1 t2 t3 ee toe DCLKOUT t4 t5 E ADDR 12 0 t6 t7 ALE t8 CARDREG CARDxCSH CARDxCSL CARDIORD CARDIOWR WE RD t9 t10 gt g gt CARDxWAIT Di t12 p gt le gt D 31 16 write t13 t14 t15 do ope D 31 16 read X Figure 7 10 Toshiba Timing SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Vancouver Design Center Table 7 10 Toshiba Timing Page 59 3 0V 5 0V Symbol Parameter Min Max Min Max Units ti Clock period 13 3 13 3 ns t2 Clock pulse width low 5 4 5 4 ns t3 Clock pulse width high 5 4 5 4 ns t4 ADDR 12 0 setup to first CLK of cycle 10 10 ns t5 ADDR 12 0 hold from command invalid 0 0 ns t6 ADDR 12 0 se
356. n accessing the SED1355 internal registers and or display buffer The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete The BS and RD WR signals are not used for the MIPS ISA Host Bus Interface and should be tied high connected to Vpp Interfacing to the NEC VR4121 Microprocessor SED1355 Issue Date 99 05 05 X23A G 011 03 Page 12 Epson Research and Development Vancouver Design Center 4 VrR4121 to SED1355 Interface 4 1 Hardware Description The NEC Vr4121 microprocessor is specifically designed to support an external LCD controller It provides all the necessary internal address decoding and control signals required by the SED1355 The diagram below shows a typical implementation utilizing the SED1355 NEC VR4121 SED1355 WR gt WEOH SHB gt WE1 RD gt RD LCDCS Pulbup gt CSH To LCDRDY WAIT System RESET gt RESET ADD21 l gt M R ADD 25 0 gt AB 20 0 DAT 15 0 lt gt DB 15 0 BUSCLK gt BUSCLK Vpp 3 3V BS 3 3V Vpp3 RD WR Vor 2 5V Von Note When connecting the SED1355 RESET pin the system designer should be aware of all conditions that may reset the SED1355 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 NEC Vr4121 to SEDI355 Configuration Schematic Note For pin mapping see Table 3 1 Ho
357. n in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Microsoft and Windows are registered trademarks of Microsoft Corporation Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 Interfacing to the NEC VR4102 VR4111 Microprocessors X23A G 007 05 Issue Date 99 05 05 Epson Research and Development Vancouver Design Center Table of Contents 1 introduction gt is ee Re ae a a E AC 2 Interfacing to the VR4102 VR4111 2 1 The NEC VR4102 VR4111 System Bus SEL OVERVIEW si a hcg a da da 2 1 2 LCD Memory Access Cycles o 3 SED1355 Host Bus Interface 3 1 Host Bus Interface Pin Mapping 3 2 Host Bus Interface Signals Descriptions 4 VR4102 VR4111 to SED1355 Interface 4 1 Hardware Description 4 2 SED1355 Hardware Configuration 4 3 NEC VR4102 VR4111 Configuration Dr Sowab Nik fo fetes ek ab ty zo
358. n of the panel resolution and whether the panel is color or monochrome type Half Frame Buffer Size in bytes panel width x panel length factor 16 where factor 4 for color panel 1 for monochrome panel For example for a 640x480 8 bpp color panel the half frame buffer size is 75K bytes In a 512K byte display buffer the half frame buffer resides from 6D400h to 7FFFFh In a 2M byte display buffer the half frame buffer resides from 1ED400h to 1 FFFFFh Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 125 Vancouver Design Center 10 Display Configuration 10 1 Display Mode Data Format The following diagrams show the display mode data formats for a little endian system 1 bpp bit 7 bit 0 PoP4 P2 P3P4P5P6P7 Panel Display Host Address Display Memory SR bit 7 bit 0 PoP PoP3P4P5P5P7 Panel Display Host Address Display Memory bitz DIED PoP1P2P3P4P5P6P7 Ph An Du Ch Dn Panel Display Host Address Display Memory PoP1P2P3P4P5P6P7 Ph ES An Bn Cr Dm En Fr Gn Hn Panel Display Host Address Display Memory Figure 10 1 1 2 4 8 Bit per pixel Format Memory Organization Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 126 Epson Research and Development Vancouver Design Center Daf P2
359. n the display The 1355SPLT display utility must be configured and or compiled to work with your hardware platform The program 1355CFG EXE can be used to configure 1355SPLT Consult the 1355CFG users guide document number X23A B 001 xx for more information on configuring SED1355 utilities This software is designed to work in both embedded and personal computer PC environments For the embedded environment it is assumed that the system has a means of downloading software from the PC to the target platform Typically this is done by serial communications The PC uses a terminal program to send control commands and information to the target processor Alternatively the PC can program an EPROM which is then placed in the target platform Some target platforms can also communicate with the PC via a parallel port connection or an Ethernet connection SED1355 Supported Evaluation Platforms Installation 1355SPLT Display Utility Issue Date 98 10 30 1355SPLT supports the following SED1355 evaluation platforms e PC system with an Intel 80x86 processor e M68332BCC Business Card Computer board revision B with a Motorola MC68332 processor e M68ECOOOIDP Integrated Development Platform board revision 3 0 with a Motorola M68EC000 processor e SH3 LCEVB board revision B with an Hitachi SH 3 HD6417780 processor PC platform copy the file 1355SPLT EXE to a directory that is in the DOS path on your hard drive Embedded platf
360. n the sample project icon Oe SH3 DEMO7 Type BLDDEMO lt ENTER gt at the DOS prompt of the SH3 DEMO7 window to generate a Windows CE image file NK BIN To build a Windows CE v2 0 display driver for the CEPC X86 platform using a SDU1355BOC evaluation board follow the instructions below Install Microsoft Windows NT v4 0 Install Microsoft Visual C C v5 0 Install the Microsoft Windows CE Embedded Toolkit ETK by running SETUP EXE from the ETK compact disc 1 SED1355 X23A E 001 04 Page 6 SED1355 X23A E 001 04 Epson Research and Development Vancouver Design Center Create a new project by following the procedure documented in Creating a New Project Directory from the Windows CE ETK v2 0 Alternately use the current DEMO project included with the ETK v2 0 Follow the steps below to create a X86 DEMO shortcut on the Windows NT v4 0 desktop which uses the current DEMO7 project a Right click on the Start menu on the taskbar b Click on the item Open All Users and the Start Menu window will come up c Click on the icon Programs d Click on the icon Windows CE Embedded Development Kit e Drag the icon X86 DEMO1 onto the desktop using the right mouse button f Click on Copy Here g Rename the icon X86 DEMO1 on the desktop to X86 DEMO by right clicking on the icon and choosing rename h Right click on the icon X86 DEMO7
361. ncouver Design Center Table of Contents INTRODUCTION SED1355 Embedded RAMDAC LCD CRT Controller Product Brief SPECIFICATION SED1355 Hardware Functional Specification PROGRAMMER S REFERENCE SED1355 Programming Notes and Examples SED1355 Register Summary UTILITIES 1355CFG Configuration Program 1355SHOW Demonstration Program 1355SPLT Display Utility 1355VIRT Display Utility 1355PLAY Diagnostic Utility 1355BMP Demonstration Program 1355PWR Software Suspend Power Sequencing Utility DRIVERS SED1355 Windows CE Display Drivers EVALUATION SDU1355BO0C Rev 1 0 ISA Bus Evaluation Board User Manual SDU1355 D9000 Evaluation Board User Guide APPLICATION NOTES Power Consumption Interfacing to the Philips MIPS PR31500 PR31700 Processor Interfacing to the PC Card Bus Interfacing to the NEC VR4102 VR4111 Microprocessor Interfacing to the Motorola MPC821 Microprocessor Interfacing to the NEC VR4121 Microprocessor Interfacing to the Toshiba MIPS TX3912 Processor Interfacing to the NEC V832 Microprocessor TECHNICAL MANUAL Issue Date 99 10 06 Page 5 SED1355 X23A Q 001 09 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 TECHNICAL MANUAL X23A Q 001 09 Issue Date 99 10 06 EPSON d GRAPHICS MESE SED1355 EMBEDDED RAMDAC LCD CRT CONTROLLER NW DESCRIPTION October 1998 The SED1355 is a color monochrome LCD CRT graphics controller interfacing to a wide range of CPUs and display
362. ne see note below Color color of line For 1 2 4 and 8 bpp Color refers to the pixel value which points to the respective LUT DAC entry For 15 and 16 bpp Color refers to the pixel value which stores the red green and blue intensities within a WORD ERR OK operation completed with no problems ERR_INVALID_REG_DEVICE device argument is not valid int seDrawRect int DeviD long x1 long y1 long x2 long y2 DWORD Color BOOL SolidFill Description Parameters Return Value This routine draws and optionally fills a rectangular area of display buffer The upper right corner of the rectangle is defined by x1 y1 and the lower right corner is defined by x2 y2 The color defined by Color applies to the border and to the optional fill DevID registered device ID xl yl top left corner of the rectangle in pixels x2 y2 bottom right corner of the rectangle in pixels Color The color to draw the rectangle outline and solid fill At 1 2 4 and 8 bpp Color is an index into the Look Up Table At 15 16 bpp Color defines the color directly i e rrrrreggeggbbbbb for 16 bpp SolidFill Flag whether to fill the rectangle or simply draw the border Set to 0 for no fill set to non 0 to fill the inside of the rectangle ERR OK operation completed with no problems Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 63 Vancouver Design Center int seDr
363. nfiguration Readback we write a 0 here to keep the 1D 0000 0000 register configuration logic simpler 1E 0000 0000 op SEH General UO Pins set to zero 20 0000 0000 Gu O General I O Pins Control set to zero Programming Notes and Examples SED1355 Issue Date 99 04 27 X23A G 003 05 Page 10 Epson Research and Development Vancouver Design Center Table 2 1 SED1355 Initialization Sequence Continued Register Value Notes See Also 24 0000 0000 26 0000 0000 27 0000 0000 28 0000 0000 29 E The remaining register control operation of the LUT and 2A 0000 0000 hardware cursor ink layer During the chip initialization none of 2B 000 0000 these registers needs to be set It is safe to write them to zero 2B 0000 0000 20 a000 000 as this is the power up value for the registers 2D 0000 0000 2E 0000 0000 2F 0000 0000 30 0000 0000 31 0000 0000 SED1355 Hardware 23 0000 0000 Enable FIFO mask in appropriate FIFO threshold bits Functional Specification document number X23A A 001 xx Sad Display mode hardware portrait mode disabled 8 bpp and 0D ER ALOI LCD enabled SED1355 Programming Notes and Examples X23A G 003 05 Issue Date 99 04 27 Epson Research and Development Page 11 Vancouver Design Center 2 1 Miscellaneous This section of the
364. nflict with the image buffer and half frame buffer The start address for the Ink Cursor buffer is programmed as shown in the following table Table 12 1 Ink Cursor Start Address Encoding Ink Cursor Start Address Bits 7 0 Start Address Bytes Comments 0 Display Buffer Size 1024 This default value is suitable for a cursor when there is no half frame buffer These positions can be used to position an Ink buffer at the top of the display buffer n 255 1 Display Buffer Size position an Ink buffer between the image n x 8192 and half frame buffers position a Cursor buffer between the image and half frame buffers e select from a multiple of Cursor buffers The Ink Cursor image is stored contiguously The address offset from the starting word of line n to the starting word of line n is calculated as follows Ink Address Offset words REG 04h 1 Cursor Address Offset words 8 12 2 Ink Cursor Data Format The Ink Cursor image is always 2 bit per pixel The following diagram shows the Ink Cursor data format for a little endian system 2 bpp bit 7 bit O PoPyP2P3P4P5PgP7 Ph An Bn Panel Display Host Address Ink Cursor Buffer Figure 12 1 Ink Cursor Data Format SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 135 Vancouver Design Center The image data for pi
365. ng its ADD and DAT buses which can be dynamically sized for 16 or 32 bit operation The NEC VR4102 VR4111 has direct support for an external LCD controller Specific control signals are assigned for an external LCD controller providing an easy interface to the CPU A 16M byte block of memory is assigned for the LCD controller and its own chip select and ready signals are available Word or byte accesses are controlled by the system high byte signal SHB Interfacing to the NEC VR4102 VR4111 Microprocessors Issue Date 99 05 05 Epson Research and Development Page 9 Vancouver Design Center 2 1 2 LCD Memory Access Cycles Once an address in the LCD block of memory is placed on the external address bus ADD 25 0 the LCD chip select LCDCS is driven low The read or write enable signals RD or WR are driven low for the appropriate cycle and LCDRDY is driven low to insert wait states into the cycle The high byte enable SHB in conjunction with address bit O allows for byte steering The following figure illustrates typical NEC VR4102 VR4111 memory read and write cycles to the LCD controller interface fe A A MU MU NR ADD 25 0 E VALID X SHB Ee D LCDCS WR RD D 15 0 write VALID os Hi Z d er Ma VALID y LCDRDY Figure 2 1 NEC VR4102 VR4111 Read Write Cycles Interfacing to the NEC VR4102 VR4111 Microprocessors SED1355 Issue Date 99 05 05 X23A G 007
366. nics America website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs erd epson com Interfacing to the PC Card Bus SED1355 Issue Date 99 05 05 X23A G 005 05 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the PC Card Bus 2 1 The PC Card System Bus PC Card technology has gained wide acceptance in the mobile computing field as well as in other markets due to its portability and ruggedness This section is an overview of the operation of the 16 bit PC Card interface conforming to the PCMCIA 2 0 JEIDA 4 1 Standard or later 2 1 1 PC Card Overview The 16 bit PC Card provides a 26 bit address bus and additional control lines which allow access to three 64M byte address ranges These ranges are used for common memory space IO space and attribute memory space Common memory may be accessed by a host system for memory read and write operations Attribute memory is used for defining card specific information such as configuration registers card capabilities and card use IO space maintains software and hardware compatibility with hosts such as the Intel x86 architecture which address peripherals independently from memory space Bit notation follows the convention used by most micro processors the high bit being the most significant Therefore signals A25
367. nnects to LCDRDY and is a signal output from the SED 1355 that indicates the VR4102 VR4111 must wait until data is ready read cycle or accepted write cycle on the host bus Since VR4102 VR4111 accesses to the SED1355 may occur asynchro nously to the display update it is possible that contention may occur in accessing the SED1355 internal registers and or display buffer The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete The BS and RD WRz signals are not used for the MIPS ISA Host Bus Interface and should be tied high connected to Vpp Interfacing to the NEC VR4102 VR4111 Microprocessors SED1355 Issue Date 99 05 05 X23A G 007 05 Page 12 Epson Research and Development Vancouver Design Center 4 VR4102 VR4111 to SED1355 Interface 4 1 Hardware Description The NEC Vr4102 Vr4111 Microprocessors are specifically designed to support an external LCD controller They provide the necessary internal address decoding and control signals The diagram below shows a typical implementation utilizing the SED1355 NEC VR4102 VR4111 SED1355 WRH gt WEOH SHB gt WE1 RD gt RD LCDCS Pulbup gt CS To LCDRDY j WAIT ADD21 5 gt M R System RESET gt RESET ADD 25 0 gt AB 20 0 DAT 15 0 gt DB 15 0 BUSCLK gt BUSCLK Von E BSt Von T RD WR Note When connecting the SED1355 RESET pin
368. notes contains recommendations which can be set at initialization time to improve display image quality At high color depths the display FIFO introduces two conditions which must be accounted for in software Simultaneous display while using a dual passive panel introduces another possible register change Display FIFO Threshold At 15 16 bit per pixel the display FIFO threshold bits 0 4 of register 23h must be programmed to a value other than 0 Product testing has shown that at these color depths a better quality image results when the display FIFO threshold is set to a value of 1Bh Memory Address Offset When an 800x600 display mode is selected at 15 or 16 bpp memory page breaks can disrupt the display buffer fetches This disruption produces a visible flicker on the display To avoid this set the Memory Address Offset Reg 16h and Reg 17h to 200h This sets a 1024 pixel line which aligns the memory page breaks and reduces any flicker Halt Frame Buffer Disable The half frame buffer is an SED1355 mechanism which pre digitizes display data for dual panel displays However for proper simultaneous display operation the half frame buffer HFB must be disabled When running simultaneous display with a dual panel the pattern used by the Frame Rate Modulator may need to be adjusted This can be accomplished using the Alternate FRM Register Reg 31h In this case the recommended value for Reg 31h of FFh may produce more visually
369. nput Requirements Memory Interface Timing E 7 3 1 EDO DRAM Read Write Read W 7 3 2 7 3 3 EDO DRAM Self Refresh Timing 7 3 4 FPM DRAM Read Write Read Write Timing 7 3 5 7 3 6 FPM DRAM Self Refresh Timing Power Sequencing 7 4 1 LCD Power Sequencing 7 4 2 Power Save Status Display Interface 7 5 1 4 Bit Single Monochr 7 5 2 7 5 3 4 Bit Single Color Passive LCD Panel Timing 7 5 4 7 5 5 7 5 6 7 5 7 7 5 8 8 Bit Dual Color Passive LCD Panel Timing 7 5 9 16 Bit Dual Color Passive LCD Panel Timing 7 5 10 16 Bit TFT D TFD Panel Timing TIAL CRT Timms ENNEN EE e 8 Registers Register Mapping Register Descriptions MC68K Bus 1 Interface Timing e g MC68000 MC68K Bus 2 Interface Timing e g MC68030 Philips Interface Timing e g PR3 1500 PR31700 Power PC Interface Timing e g MPC8xx MC68040 Coldfire EDO DRAM CAS Before RAS Refresh Timing FPM DRAM CAS Before RAS Refresh Timing ome Passive LCD Panel Timing 8 Bit Single Monochrome Passive LCD Panel Timing 8 Bit Single Color Passive LCD Panel Timing Format 1 8 Bit Single Color Passive LCD Panel Timing Format 2 16 Bit Single Color Passive LCD Panel Timing 8 Bit Dual Monochrome Passive LCD Panel Timing Revision Code Register Memory Configuration Registers Panel Monitor Configuration Registers Display Configuration Registers Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Vancouver Design Center 1
370. nt seReservedl long xCenter long yCenter long radius DWORD or BOOL SolidFill SZ Color int int int int seSetLut int seReservedl BYTE pLut int count seGetLut int seReservedl BYTE pLut int count seSetLutEntry int seReservedl int index BYTE p seGetLutEntry int seReservedl int index BYTE p EJ int int int C Like Support seDrawText int seReservedl char fmt sePutChar int seReservedl int ch seGetChar void S int int XLIB Support seGetLinearDispAddr int seReservedl DWORD pDispLogicalAddr InitLinear int seReservedl endif HAL H SED 1355 X23A G 003 05 Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Vancouver Design Center Page 101 Appendix A Supported Panel Values A 1 Supported Panel Values The following tables show related register data for different panels All the examples are based on 8 bpp and 2M bytes of 50 ns EDO DRAM Note The following settings may not reflect the ideal settings for your system configuration Power speed and cost requirements may dictate different starting parameters for your system e g 320x240078Hz using 12MHz clock Table 12 1 Passive Single Panel 320x240 with 40MHz Pixel Clock
371. nterface Pin Mapping SED1355 X23A G 011 03 microprocessor Epson Research and Development Vancouver Design Center The MIPS ISA host bus interface is selected by the SED1355 on the rising edge of RESET After releasing reset the bus interface signals assume their selected configuration For details on SED1355 configuration see Section 4 2 SED1355 Configuration on page 13 Note At reset the Host Interface Disable bit in the Miscellaneous Disable Register REG 1Bh bit 7 is set to 1 This means that only REG 1 Ah read only and REG 1Bh are accessible until a write to REG 1Bh sets bit 7 to 0 making all regis ters accessible When debugging a new hardware design this can sometimes give the appearance that the interface is not working so it is important to remember to clear this bit before proceeding with debugging The following table shows the functions of each host bus interface signal Table 3 1 Host Bus Interface Pin Mapping SED1355 Pin Name NEC VR4121 Pin Name AB20 ADD20 AB 19 0 ADD 19 0 DB 15 0 DAT 15 0 WEIS SHB M R ADD21 CS LCDCS BUSCLK BUSCLK BS Connected to Von RD WR Connected to Von RD RD WE0 WR WAIT LCDRDY RESET connected to system reset Interfacing to the NEC VR4121 Microprocessor Issue Date 99 05 05 Epson Research and Development Page 11 Vancouver Design Center 3 2 Host Bus Interface Signal Descriptions The
372. o 16 shades of gray using FRM on monochrome passive LCD panels Up to 4096 colors on passive LCD panels three 256x4 Look Up Tables LUT are used to map 1 2 4 8 bpp modes into these colors 15 16 bpp modes are mapped directly using the 4 most significant bits of the red green and blue colors Up to 64K colors on TFT D TFD LCD panels and CRT three 256x4 Look Up Tables are used to map 1 2 4 8 bpp modes into 4096 colors 15 16 bpp modes are mapped directly 2 5 Display Features 2 6 Clock Source SwivelView direct hardware 90 rotation of display image for portrait mode display Split Screen Display allows two different images to be simultaneously viewed on the same display Virtual Display Support displays images larger than the display size through the use of panning Double Buffering multi pages provides smooth animation and instantaneous screen update Acceleration of screen updates by allocating full display memory bandwidth to CPU see REG 23h bit 7 Hardware 64x64 pixel 2 bit cursor or full screen 2 bit ink layer Simultaneous display of CRT and passive panel or TFT D TFD panel e Normal mode for cases where LCD and CRT screen sizes are identical e Line doubling for simultaneous display of 240 line images on 240 line LCD and 480 line CRT e Even scan or interlace modes for simultaneous display of 480 line images on 240 line LCD and 480 line CRT Single clock input for both the pixel and memory clocks Memo
373. o change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 Power Consumption X23A G 006 02 Issue Date 98 10 30 Epson Research and Development Page 3 Vancouver Design Center 1 SED1355 Power Consumption Power Consumption Issue Date 98 10 30 SED1355 power consumption is affected by many system design variables Input clock frequency CLKI the CLKI frequency determines the LCD frame rate CPU perfor mance to memory and other functions the higher the input clock frequency the higher the frame rate performance and power consumption CPU interface the SED1355 current consumption depends on the BUSCLK frequency data width number of toggling pins and other factors the higher the BUSCLK the higher the CPU performance and power consumption Vpp Voltage level the voltage level affects power consumption the higher the voltage the higher the consumpt
374. ocated to address the SED1355 When the IT8368E senses that the SED1355 is being accessed it does not propagate the PC Card signals to its PC Card device This makes SED1355 accesses transparent to any PC Card device connected to the same slot For mapping details refer to Section 4 3 Memory Mapping and Aliasing on page 11 For further information on configuring the IT8368E refer to the IT8368E PC Card GPIO Buffer Chip Specification 5 3 SED1355 Configuration For SED1355 configuration refer to Section 4 2 SED1355 Configuration on page 10 Interfacing to the Philips MIPS PR31500 PR31700 Processor SED1355 Issue Date 99 05 05 X23A G 001 06 Page 14 Epson Research and Development Vancouver Design Center 6 Software Test utilities and Windows CE v2 0 display drivers are available for the SED1355 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 1355CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The SED1355 test utilities and Windows CE v2 0 display drivers are available from your sales support contact or on the internet at http www eea epson com SED1355 Interfacing to the Philips MIPS PR31500 PR31700 Processor X23A G 001 06 Issue Date 99 05 05 Epson Rese
375. od REG 09h bits 1 0 REG O8h bits 7 0 1 VNDP Vertical Non Display Period REG OAN bits 5 0 1 HDP Horizontal Display Period REG 04h bits 6 0 1 8Ts HNDP Horizontal Non Display Period HNDP HNDP gt REG O5h bits 4 0 1 8Ts Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Epson Research and Development Page 96 Vancouver Design Center t8 gt t9 gt H FPFRAME f t12 FPLINE a Vf V t6 a FPLINE t7 t15 WM e t17 DRDY t14 tl 2 13 ER t13 t16 FPSHIFT J J J J t t4 t5 R 5 1 G 5 0 1 2 XI 639 X 640 B 5 1 ge Note DRDY is used to indicate the first pixel Figure 7 43 TFT D TFD A C Timing Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Epson Research and Development Page 97 Vancouver Design Center Table 7 32 TFT D TFD A C Timing Symbol Parameter Min Typ Max Units t1 FPSHIFT period 1 Ts note 1 t2 FPSHIFT pulse width high 0 45 Ts t3 FPSHIFT pulse width low 0 45 Ts t4 data setup to FPSHIFT falling edge 0 45 Ts t5 data hold from FPSHIFT falling edge 0 45 Ts t6 FPLINE cycle time note 2 t7 FPLINE pulse width low note 3 t8 FPFRAME cycle time note 4 t9 FPFRAME pulse width low note 5 t10 horizontal display period note 6 t11 FP
376. ogram Issue Date 98 10 30 EPSON SED1355 Embedded RAMDAC LCD CRT Controller 1355SHOW Demonstration Program Document Number X23A B 002 04 Copyright 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 1355SHOW Demonstration Program X23A B 002 04 Issue Date 98 10 29 Epson Research and Development Page 3 Vancouver Design Center 1355SHOW 1355SHOW is designed to demonstrate and test some of the SED1355 display capabilities The program can cycle through all the color depths and display a pattern showing all available colors or the user can specify a color depth and display configuration The 1355SHOW demonstration program must be configured and or compiled to work with your hardware platform The program 1355CFG EXE can be used to configure 1355SH
377. ologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 1355VIRT Display Utility X23A B 004 03 Issue Date 98 10 30 Epson Research and Development Page 3 Vancouver Design Center 1355VIRT 1355VIRT demonstrates the virtual display capability of the SED1355 A virtual display is where the image to be displayed is larger than the physical display device CRT or LCD 1355VIRT uses panning and scrolling to allow the display device to show a window into the entire image The 1355VIRT display utility must be configured and or compiled to work with your hardware platform The program 1355CFG EXE can be used to configure 1355VIRT Consult the 1355CFG users guide document number X23A B 001 xx for more information on configuring SED1355 utilities This software is designed to work in both embedded and personal computer PC environments For the embedded environment it is assumed that the system has a means of downloading software from the PC to the target platform Typically this is done by serial communications where the PC uses a terminal program to send control commands and information to the target processor Alternatively 1355VIRT Display Utility SED1355 Issue D
378. on Research and Development Page 3 Vancouver Design Center Table of Contents 1 ANtFOGUCTION o r eec A A a uerg a aO SG 7 Interfacing to the TX3912 lt lt 8 SED1355 Host Bus Interface 0 ee 4 9 3 1 TX3912 Host Bus Interface Pin Mapping a a a a a a ee 9 3 2 TX3912 Host Bus Interface Signals 2 2 10 4 Direct Connection to the Toshiba TX3912 11 4 1 Hardware Description a a a a a a 11 4 2 SED1355 Configuration sas 62 be ae A Ee a a 1D 4 3 Memory Mapping and Aliasing e 13 5 System Design Using the IT8368E PC Card Buffer 14 5 1 Hardware Description a a a JA 5 2 IT8368E Configuration e 1S 5 3 SED1355 Configuration ss o e aas ta o a ee ee 1 EWEG 5 ti is EE a sees Ds ads E ae Tae 16 ReTerences e fie et ert e A A Da A 17 H Documents e m a E e ts Ee ta oe ee e ta e ER R2 Document SQUIC S aas coa a a aa he as A a E 8 Technical Support ies boa ara radar a a 18 8 1 EPSON LCD CRT Controllers SED1335 a 2 2 2 02 2 2 2 2 2 2 2 2 18 8 2 Toshiba MIPS TX3912 Processor a a ee ee ee ee ee 18 8 3 LITE ITS368E 42 hee ca te wk wwe A we Ba he aalt LG BUD Se et odode Gn Ab Se A TS Interfacing to the Toshiba MIPS TX3912 Processor SED1355 Issue Date 99 05 05 X23A G 010 03 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK
379. on Sequence Register Value Notes See Also 1B 0000 0000 Enable the host interface 23 1000 0000 Disable the FIFO Memory configuration 01 0011 0000 divide CIkI by 512 to get 4 ms for 256 refresh cycles this is 2 CAS EDO memory SED1355 Hardware 22 side A008 Performance Enhancement 0 refer to the hardware Functional Specification specification for a complete description of these bits document number X23A A 001 xx 02 0001 0110 Panel type non EL 8 bit data format 1 color dual passive 03 0000 0000 Mod rate used by older monochrome panels set to 0 04 0100 1111 Horizontal display size Reg 04 1 8 79 1 8 640 pixels 82 Note for REG 16h and REG 17h 05 boo bora Horizontal non display size Reg 05 1 8 3 1 8 32 pixels 06 0000 0000 FPLINE start position only required for CRT or TFT D TFD 07 0000 0000 FPLINE polarity set to active high 08 1110 1111 Vertical display size Reg 09 08 1 EE 0000 0000 11101111 1 09 0000 0000 _ 23941 240 lines total height 2 for dual panels 0A 0011 1000 Vertical non display size Reg 0A 1 57 1 58 lines SED1355 X23A G 003 05 Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Vancouver Design Center Table 2 1 SED1355 Initialization Sequence Continued Page 9
380. on completed with no problems Example seRegisterDevice amp HalInfo amp Deviceld Note No SED 1355 registers are changed by calling seRegisterDevice seRegisterDevice MUST be called before any other HAL functions Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Vancouver Design Center Page 47 int selnitHal void Description Parameters Return Value This function initializes the variables used by the HAL library This function or seRegisterDevice must be called once when an application starts Normally programmers do not have to concern themselves with seInitHal On PC platforms seRegisterDevice automatically calls seInitHal Consecutive calls to seRegisterDevice will not call seInitHal again On non PC platforms the start up code supplied by Epson will call seInitHal However if support code for a new operating platform is written the programmer must ensure that seInitHAL is called prior to calling other HAL functions None ERR OK operation completed with no problems seSetlnit int DevID Description Parameters Return Value Note This routine sets the SED1355 registers for operation using the default settings Initialization of the SED 1355 is a two step process consisting of initializing the HAL seInitHal and initializing the SED1355 registers seSetInit Unlike the HAL the registers do not necessarily require initialization at program s
381. ontain the maximum number of lines that can be displayed at the requested virtual width DevID registered device ID VirtX horizontal size of virtual display in pixels Must be greater or equal to physical size of display VirtY a return placeholder for the maximum number of lines available given VirtX ERR OK operation completed with no problems ERR_HAL_BAD_ARG returned in three situations 1 the virtual width VirtX is greater than the largest attainable width The maximum allowable xVirt is 7FFh 16 bpp 2 the virtual width is less than the physical width or 3 the maximum number of lines is less than the physical number of lines The system must have been properly initialized prior to calling seVirtInitO Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 55 Vancouver Design Center int seVirtMove int DeviD int WhichScreen DWORD x DWORD y Description This routine pans and scrolls the display In the case where split screen operation is being used the WhichScreen argument specifies which screen to move The x and y parameters specify in pixels the starting location in the virtual image for the top left corner of the applicable display Parameter DevID registered device ID WhichScreen must be set to 1 or 2 or use the constants SCREEN1 or SCREEN2 to identify which screen to base calculations on D new starting X position in pixels y new starting Y position in pixel
382. options Normal Line Doubling Interlace or Even Scan Only The purpose of these modes is to manipulate the vertical resolution of the image so that it fits on both the CRT typically 640x480 and LCD The following table describes the four modes using a 640x480 CRT as an example Table 8 6 Simultaneous Display Option Selection Simultaneous Display Option Select Bits 1 0 Simultaneous Display Mode Mode Description 00 Normal The image is not manipulated This mode is used when the CRT and LCD have the same resolution e g 480 lines It is necessary to suit the vertical retrace period to the CRT This results in a lower LCD duty cycle 1 525 compared to the usual 1 481 This reduced duty cycle may result in lower contrast on the LCD 01 Line Doubling Each line is replicated on the CRT This mode is used to display a 240 line image ona 240 line LCD and stretch it to a 480 line image on the CRT The CRT has a heightened aspect ratio It is necessary to suit the vertical retrace period to the CRT This results in a lower LCD duty cycle 2 525 compared to the usual 1 241 This reduced duty cycle is not extreme and the contrast of the LCD image should not be greatly reduced 10 Interlace The odd and even fields of a 480 line image are interlaced on the LCD This mode is used to display a 480 line image on the CRT and squash it onto a 240 line LCD The full image is viewed on the LCD but the interlacing ma
383. or TFT D TFD LCD Panel Support The SED1355 supports 9 12 and 18 bit active matrix color TFT D TFD panels All the necessary signals can also be found on the 40 pin LCD connector J6 The interface signals on the cable are alternated with grounds to reduce crosstalk and noise When supporting an 18 bit TFT D TED panel the SED1355 can display 64K of a possible 256K colors A maximum 16 of the possible 18 bits of LCD data are available from the SED1355 Refer to the SED1355 Hardware Functional Specification document number X23A A 001 xx for details Refer to Table 3 1 LCD Signal Connector J6 on page 9 for connection information 6 9 CRT Support This evaluation board provides CRT support through the SED1355 s embedded RAMDAC Refer to the SED1355 Hardware Functional Specification document number X23A A 001 xx for details 6 10 Power Save Modes The SED1355 supports one hardware suspend and one software suspend Power Save Mode The software suspend mode is controlled by the utility 1355PWR Software Suspend Power Sequencing The hardware suspend mode can be enabled by a memory read to location F00000h A memory write to the same location will disable it 6 11 Adjustable LCD Panel Negative Power Supply Most monochrome passive LCD panels require a negative power supply to provide between 18V and 23V Ijy 45mA For ease of implementation such a power supply has been provided as an integral part of this design The signal VLCD c
384. or summary See the respective AC Timing diagram for detailed functionality AB17 114 Hi Z e For Philips PR31500 31700 Bus this pin inputs the lO write command CARDIOWR e For Toshiba TX3912 Bus this pin inputs the IO write command CARDIOWR e For PowerPC Bus this pin inputs the system address bit 14 A14 s For all other busses this pin inputs the system address bit 17 A17 See Host Bus Interface Pin Mapping for summary See the respective AC Timing diagram for detailed functionality AB18 113 Hi Z e For Philips PR31500 31700 Bus this pin inputs the lO read command CARDIORD e For Toshiba TX3912 Bus this pin inputs the lO read command CARDIORDY e For PowerPC Bus this pin inputs the system address bit 13 A13 For all other busses this pin inputs the system address bit 18 A18 See Host Bus Interface Pin Mapping for summary See the respective AC Timing diagram for detailed functionality AB19 112 Hi Z e For Philips PR31500 31 700 Bus this pin inputs the card control register access CARDREG e For Toshiba TX3912 Bus this pin inputs the card control register CARDREG e For PowerPC Bus this pin inputs the system address bit 12 A12 For all other busses this pin inputs the system address bit 19 A19 See Host Bus Interface Pin Mapping for summary See the respective AC Timing diagram for detailed functionality AB20 1
385. orm download the program 1355SPLT to the system SED1355 X23A B 003 02 Page 4 Epson Research and Development Vancouver Design Center Usage PC platform at the prompt type 1355splt a Embedded platform execute 1355sp1t and at the prompt type the command line argument Where no argument enables manual split screen operation a enables automatic split screen operation 3 displays the help screen The following keyboard commands are for navigation within the program Manual mode T moves Screen 2 up one line moves Screen 2 down one line CTRL moves Screen 2 up several lines CTRL moves Screen 2 down several lines HOME Screen 2 moved up as high as possible END Screen 2 moved down as low as possible Automatic and Manual modes b changes the color depth bit per pixel ESC exits 1355SPLT 1355SPLT Example 1 Type 1355splt a to automatically move the split screen 2 Press b to change the bit per pixel value from 16 to 15 bit per pixel 3 Repeat step 2 for the remaining bit per pixel color depths 8 4 2 and 1 4 Press lt ESC gt to exit the program Comments e When using a PC with the SDU1355 evaluation board the PC must not have more than 12M bytes of system memory SED1355 1355SPLT Display Utility X23A B 003 02 Issue Date 98 10 30 Epson Research and Development Page 5 Vancouver Design Center Program Messages 1355SPLT Display Utility Issue Date 98 10 30 ERROR Did not find a 1355 devic
386. osition Start Position Start Position Start Position Start Position Start Position Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O bits 5 0 VRTC FPFRAME Start Position Bits 5 0 For CRT and TFT D TFD these bits specify the delay in lines from the start of the vertical non dis play period to the leading edge of the VRTC pulse and FPFRAME pulse respectively For passive LCD FPFRAME is automatically created and these bits have no effect VRTC FPFRAME start position lines VRTC FPFRAME Start Position Bits 5 0 1 The maximum start delay is 64 lines Note This register must be programmed such that REG OAh bits 5 0 1 gt REG OBh 1 REG OCH bits 2 0 1 For exact timing please use the timing diagrams in section 7 5 VRTC FPFRAME Pulse Width Register REG OCh RW VRTC VRTC VRTC VRTC Polarity aoe e Ss ais FPFRAME FPFRAME FPFRAME Select eto Pulse Width Pulse Width Pulse Width Bit 2 Bit 1 Bit 0 bit 7 VRTC Polarity Select This bit selects the polarity of the VRTC pulse to the CRT When this bit 1 the VRTC pulse is active high When this bit 0 the VRTC pulse is active low bit 6 FPFRAME Polarity Select This bit selects the polarity of the FPFRAME pulse to the TFT D TED or passive LCD When this bit 1 the FPFRAME pulse is active high for TFT D TFD and active low for passive When this bit 0 the FPFRAME pulse is active low for TFT D TED and active high for passive Table 8 5
387. ount 4 gt memory size this function will limit the writes to the end of memory int seReadDisplayByte int DevID DWORD Offset BYTE pByte Description Reads a byte from the display buffer at the specified offset and returns the value in pByte Parameters DevID registered device ID Offset offset in bytes from start of the display buffer pByte return value of the display buffer location Return Value ERR_OK operation completed with no problems ERR_HAL_BAD_ARG if the value for Offset is greater than the amount of installed memory int seReadDisplayWord int DevID DWORD Offset WORD pWord Description Reads a word from the display buffer at the specified offset and returns the value in pWord Parameters DevID registered device ID Offset offset in bytes from start of the display buffer pWord return value of the display buffer location Return Value ERR_OK operation completed with no problems ERR_HAL_BAD_ARG if the value for Offset is greater than the amount of installed memory Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 59 Vancouver Design Center int seReadDisplayDword int DevID DWORD Offset DWORD pDword Description Reads a dword from the display buffer at the specified offset and returns the value in pDword Parameters DevID registered device ID Offset offset from start of the display buffer pDword return value of the display buff
388. our Bit Per Pixel 16 Colors Gray Shades Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O Pixel 0 Pixel 0 Pixel 0 Pixel 0 Pixel 1 Pixel 1 Pixel 1 Pixel 1 Bit 3 Bit 2 Bit 1 Bit O Bit 3 Bit 2 Bit 1 Bit O Figure 3 3 Pixel Storage for 4 Bpp 16 Colors Gray Shades in One Byte of Display Buffer In this memory format each byte of display buffer contains two adjacent pixels Setting or resetting any pixel will require reading the entire byte masking out the upper or lower nibble 4 bits and setting the appropriate bits to T Four bit pixels provide 16 gray shade color possibilities For monochrome panels the gray shades are generated by indexing into the first 16 elements of the green component of the Look Up Table For color panels the 16 colors are derived by indexing into the first 16 positions of the Look Up Table 3 1 4 Memory Organization for Eight Bit Per Pixel 256 Colors 16 Gray Shades Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O One Pixel Programming Notes and Examples Issue Date 99 04 27 Figure 3 4 Pixel Storage for 8 Bpp 256 Colors 16 Gray Shades in One Byte of Display Buffer In eight bit per pixel mode each byte of display buffer represents one pixel on the display At this color depth the read modify write cycles of the lessor pixel depths are eliminated Each byte indexes into one of the 256 positions of the Look Up Table The SED1355 LUT supports four bits p
389. out p option Because the Hardware Cursor and Ink Layer are not automatically rotated in portrait mode 1355BMP does not support the p option Instead rotate the BMP with a paint program and then load the rotated image in landscape non portrait mode ERROR Cannot use buffer option without 2 Mbyte of display buffer memory The buffer option is not supported unless the platform has 2M bytes of memory ERROR Could not switch portrait buffer The HAL library reported an error when changing the screen 1 start address register ERROR Failed to open BMP file filename The BMP file could not be opened as a read only file ERROR filename is not a valid bitmap file The file does not contain a valid BMP format image ERROR Could not initialize hardware cursor The HAL library could not initialize the Hardware Cursor ERROR BMP file is bit per pixel hardware cursor requires 4 bit per pixel BMP file The Hardware Cursor BMP image must always have a color depth of four bit per pixel 1355BMP Demonstration Program Issue Date 98 10 30 Epson Research and Development Page 5 Vancouver Design Center ERROR Could not initialize ink layer The HAL library could not initialize the Ink Layer ERROR BMP file is bit per pixel ink layer requires 4 bit per pixel BMP file The Ink Layer BMP image must always have a color depth of four bit per pixel ERROR Could not change to bit per pixel
390. output is set to the reset state When this bit 1 the GPO output is set to the inverse of the reset state For information on the reset state of this pin see Miscellaneous Interface Pin Descriptions on page 32 and Summary of Power On Reset Options on page 33 Performance Enhancement Register 0 REG 22h RW RAS Precharge Timing Value Bit 1 RAS Precharge Timing Value Bit 0 RAS to CAS Delay Value RC Timing Value Bit 1 RC Timing Reserved Value Bit 0 Reserved Reserved Note Changing this register to non zero value or to a different non zero value should be done only when there are no read write DRAM cycles This condition occurs when all of the following are true the Display FIFO is disabled REG 23h bit 7 1 and the Half Frame Buffer is disabled REG 1Bh bit 0 1 and the Ink Cursor is inactive Reg 27h bits 7 6 00 This condition also occurs when the CRT and LCD enable bits Reg ODh bits 1 0 have remained 0 since chip reset For further programming information see SED1355 Programming Notes and Examples docu ment number X23A G 003 xx bit 7 Hardware Functional Specification Issue Date 99 05 18 Reserved SED1355 X23A A 001 11 Page 116 bits 6 5 bit 4 SED1355 X23A A 001 11 Epson Research and Development Vancouver Design Center RC Timing Value Nge Bits 1 0 These bits select the DRAM random cycle timing parameter tpc These bits
391. ouver Design Center THIS PAGE LEFT BLANK SED1355 Interfacing to the NEC VR4121 Microprocessor X23A G 011 03 Issue Date 99 05 05 EPSON SED1355 Embedded RAMDAC LCD CRT Controller Interfacing to the NEC V832 Microprocessor Document Number X23A G 012 01 Copyright 1999 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Microsoft and Windows are registered trademarks of Microsoft Corporation Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 Interfacing to the NEC V832 Microprocessor X23A G 012 01 Issue Date 99 05 05 Epson Research and Development Page 3 Vancouver Design Center Table of Contents UN tg UO e EE EE e A A A A AO ee ENEE a 7 2 Interfacing to the NEC V832 8 2 1 The NEC V832SystemBus 2 BR Delile ONCEVICW
392. ouver Design Center Table 14 2 Maximum PCLK Frequency with FPM DRAM Ink GE N Maximum PCLK allowed n ispla e EE RC 1bpp 2bpp 4bpp 8bpp 16 bpp e Single Panel e CRT e Dual Monochrome Color Panel with Half Frame Buffer Disabled 5 4 3 MCLK e Simultaneous CRT Single Panel e Simultaneous CRT Dual Monochrome Color Panel with Half Frame Buffer Disabled oh e Dual Monochrome with Half Frame Buffer Enabled 5 MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 3 e Simultaneous CRT Dual Monochrome Panel with 4 MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 2 Half Frame Buffer Enable 3 MCLK MCLK MCLK MCLK 2 MCLK 2 e Dual Color with Half Frame Buffer Enabled 5 MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 3 Simultaneous CRT Dual Color Panel with Half 4 MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 3 F Buffer Enable STEE 3 MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 2 e Single Panel 5 MCLK 2 MCLK 2 MCLK 2 MCLK 2 MCLK 3 CRT 4 MCLK MCLK MCLK 2 MCLK 2 MCLK 2 e Dual Monochrome Color Panel with Half Frame Buffer Disabled e Simultaneous CRT Single Panel 3 MCLK MCLK MCLK MCLK 2 MCLK 2 e Simultaneous CRT Dual Monochrome Color Panel with Half Frame Buffer Disabled Sc Dual Monochrome with Half Frame Buffer Enabled 5 MCLK 2 MCLK 2 MCLK 3 MCLK 3 MCLK 3 Simultaneous CRT Dual Monochrome Panel with 4 MCLK 2 MCLK 2 MCLK 2 MCLK
393. pRegs 0x2C 0 pRegs 0x2D 0 pRegs 0x2E OxFF pRegs 0x2F OxFF Draw a hollow rectangle around the cursor RI pImp pCursor for lpCnt 0 lpCnt lt 16 1pCnt pTmp 0x55 pImp for lpCnt 0 lpCnt lt 14 lpCnt pTmp 0x6A pTmp 15 pTmp OxA9 pTmp for lpCnt 0 lpCnt lt 16 1pCnt pTmp 0x55 pImp Move the cursor to 100 100 iar kk First we wait for the next vertical non display period before updating the position registers SE while pRegs Ox0A amp 0x80 wait while in VNDP while pRegs 0x0A 0x80 wait while in VDP SED1355 X23A G 003 05 Epson Research and Development Vancouver Design Center Set the contents of the cursor memory such that the cursor write a 10101010b pattern in each byte Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 89 Vancouver Design Center Now update the position registers z pRegs 0x28 100 Set Cursor X 100 pRegs 0x29 0x00 pRegs 0x2A 100 Set Cursor Y 100 pRegs 0x2B 0x00 Enable the hardware cursor Wi pRegs 0x27 0x40 Programming Notes and Examples SED1355 Issue Date 99 04 27 X23A G 003 05 Page 90 Epson Research and Development Vancouver Design Center 12 1 3 Header Files The following header files are included as they help
394. play buffer and register address spaces of the SED1355 M R is set high to access the display buffer and low to access the registers See Register Mapping See Table 5 6 CPU Interface Pin Mapping on page 34 CS Hi Z e For Philips PR31500 31700 Bus this pin is connected to Von e For Toshiba TX3912 Bus this pin is connected to Von e For all other busses this is the Chip Select input See Table 5 6 CPU Interface Pin Mapping on page 34 See the respective AC Timing diagram for detailed functionality Hardware Functional Specification Issue Date 99 05 18 SED1355 X23A A 001 11 Page 26 Epson Research and Development Vancouver Design Center Table 5 1 Host Interface Pin Descriptions Continued Pin Name Type Pin Cell RESET State Description BUSCLK 13 Hi Z This pin inputs the system bus clock It is possible to apply a 2x clock and divide it by 2 internally see MD12 in Summary of Configuration Options e For SH 3 SH 4 Bus this pin is connected to CKIO e For MC68K Bus 1 this pin is connected to CLK e For MC68K Bus 2 this pin is connected to CLK e For Generic Bus this pin is connected to BCLK e For MIPS ISA Bus this pin is connected to CLK e For Philips PR31500 31700 Bus this pin is connected to DCLKOUT e For Toshiba TX3912 Bus this pin is connected to DCLKOUT e For PowerPC Bus this pin is connected to CLKOUT e For PC Card
395. ppropriate registers are changed and the Look Up Table is set its default value This call is similar to a mode set call on a standard VGA DevID registered device ID BitsPerPixel desired color depth in bits per pixel ERR OK operation completed with no problems ERR_FAILED possible causes for this error message include 1 attempted to set other than 8 or 15 16 bpp in portrait mode portrait mode only supports 8 and 15 16 bpp 2 factors such as input clock and memory speed will affect the ability to set some color depths If the requested color depth cannot be set this call will fail Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 61 Vancouver Design Center 11 5 5 Drawing int seGetBitsPerPixel int DevID UINT pBitsPerPixel Description This function reads the SED1355 registers to determine the current color depth and returns the result in pBitsPerPixel Determines the color depth of current display mode Parameters DevID registered device ID pBitsPerPixel return value is the current color depth 1 2 4 8 15 16 bpp Return Value ERR_OK operation completed with no problems The Drawing section covers HAL functions that deal with displaying pixels lines and shapes int seSetPixel int DevID long x long y DWORD Color Description Draws a pixel at coordinates x y in the requested color This routine can be used for any color depth Parameters DevID Register
396. put WEO should be connected to the TX3912 signal WR Either WEO or the AB17 input CARDIOWR must be asserted for a write operation to take place WAIT is a signal output from the SED1355 that indicates the TX3912 must wait until data is ready read cycle or accepted write cycle on the host bus Since the TX3912 accesses to the SED1355 may occur asynchronously to the display update it is possible that contention may occur in accessing the SED1355 internal registers and or display buffer The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete Interfacing to the Toshiba MIPS TX3912 Processor Issue Date 99 05 05 Epson Research and Development Page 11 Vancouver Design Center 4 Direct Connection to the Toshiba TX3912 The SED1355 was specifically designed to support the Toshiba MIPS TX3912 processor When configured the SED1355 will utilize one of the PC Card slots supported by the processor 4 1 Hardware Description In this example implementation the SED1355 occupies one PC Card slot and resides in the Attribute and IO address range The processor provides address bits A 12 0 with A 23 13 being multiplexed and available on the falling edge of ALE Peripherals requiring more than 8K bytes of address space would require an external latch for these multiplexed bits However the SED1355 has an internal latch specifically designed for this processor making additional logic unn
397. quency allowed by the DRAM this provides maximum performance and minimum overall system power consumption SED1355 X23A A 001 11 Page 112 bits 1 0 Epson Research and Development Vancouver Design Center PCLK Divide Select Bits 1 0 These bits select the MCLK PCLK frequency ratio Table 8 9 PCLK Divide Selection PCLK Divide Select Bits 1 0 MCLK PCLK Frequency Ratio 00 EN 01 2 1 10 3 1 11 4 1 See section on Maximum MCLK PCLK Frequency Ratios for selection of clock ratios 8 2 6 Power Save Configuration Registers Power Save Configuration Register REG 1Ah RW Power Save Suspend Suspend Software Status n a n a n a aa Refresh Refresh Suspend RO Select Bit 1 Select Bit 0 Mode Enable bit 7 Power Save Status This is a read only status bit This bit indicates the power save state of the chip When this bit 1 the panel has been powered down and the memory controller is either in self refresh mode or is performing only CAS before RAS refresh cycles When this bit 0 the chip is either powered up in transition of powering up or in transition of powering down See Section 15 Power Save Modes for details bit 3 LCD Power Disable This bit is used to override the panel on off sequencing logic When this bit 0 the LCDPWR output is controlled by the panel on off sequencing logic When this bit 1 the LCDPWR output is directly forced to
398. r mats for details of how the pixels are mapped into the image buffer Table 8 7 Bit per pixel Selection Bit per pixel Select Bits 2 0 Color Depth bpp 000 1 bpp 001 2 bpp 010 4 bpp 011 8 bpp 100 15 bpp 101 16 bpp 110 111 Reserved bit 1 CRT Enable This bit enables the CRT monitor When this bit 1 the CRT is enabled When this bit 0 the CRT is disabled bit 0 LCD Enable This bit enables the LCD panel Programming this bit from a 0 to a 1 starts the LCD power on sequence Programming this bit from a to a 0 starts the LCD power off sequence SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Vancouver Design Center Page 109 Screen 1 Line Compare Register 0 REG OEh RW Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Line Line Line Line Line Line Line Line Compare Bit 7 Compare Bit 6 Compare Bit 5 Compare Bit 4 Compare Bit 3 Compare Bit 2 Compare Bit 1 Compare Bit 0 Screen 1 Line Compare Register 1 REG OFh RW n a n a n a n a n a Screen 1 Line Compare Bit 9 Screen 1 Line Compare Bit 8 REG 0Eh bits 7 0 REG OFh bits 1 0 Screen 1 Line Compare Bits 9 0 These bits are set to 1 during power on The display can be split into two images Screen 1 and Screen 2 with Screen 1 above Screen 2 This 10 bit value specifies
399. r REG 1Bh to enable the SED1355 host interface Lastly the software runs a tight loop that reads the SED 1355 Revision Code Register REG 00h This allows monitoring of the bus timing on a logic analyzer The following source code was entered into the memory of the MPC821ADS using the line by line assembler in MPC8BUG the debugger provided with the ADS board Once the program was executed on the ADS a logic analyzer was used to verify operation of the interface hardware It is important to note that when the MPC821 comes out of reset the on chip caches and MMU are disabled If the data cache is enabled then the MMU must be set so that the SED1355 memory block is tagged as non cacheable This ensures the MPC821 does not attempt to cache any data read from or written to the SED1355 or its display buffer equ 120 CS4 base register equ 124 CS4 option register equ 40 upper word of SED1355 start address equ lb address of SED1355 Disable Register equ 0 address of Revision Code Register mfspr cl IMMR get base address of internal registers andis cl rl Sffff clear lower 16 bits to 0 andis r2 r0 0 clear r2 oris r2 r2 MemStart write base address ori r2 r2 0801 port size 16 bits select GPCM enable stw r2 BR4 r1 write value to base register andis ES EE H Clear r oris r2 12 ffc0 address mask use upper 10 bits ori r2 r2 0608 normal CS negation delay CS clock no bu
400. r 2 ia Dr o og Start Addr Start Addr Start Addr Start Addr Bit 19 Bit 18 Bit 17 Bit 16 Figure 5 7 Screen 2 Display Start Address These three registers form the twenty bit offset to the first word in the display buffer that will be shown in the screen 2 portion of the display Screen 1 memory is always displayed first at the top of the screen followed by screen 2 memory The start address for the screen 2 image may be lower in memory than that of screen i e screen 2 could be coming from offset 0 in the display buffer while screen 1 was coming from an offset located several thousand bytes into the display buffer While not particularly useful it is possible to set screen and screen 2 to the same address Programming Notes and Examples Issue Date 99 04 27 SED1355 X23A G 003 05 Page 30 Epson Research and Development Vancouver Design Center 5 3 2 Examples SED1355 Example 6 Display 380 scanlines of image 1 and 100 scanlines of image 2 Image 2 is locat ed immediately after image 1 in the display buffer Assume a 640x480 display and a color depth of 1 bpp 1 The value for the line compare is not dependent on any other setting so we can set it immedi ately 380 17Ch Write the line compare registers OFh with 01h and register OEh with 7Ch 2 Screen is coming from offset 0 in the display buffer Although not necessary ensure that the screen start address is set to zero Write
401. r Design Center 1355show b a ert g 1cd noinit p read s Embedded platform execute 1355show and at the prompt type the command line argument Where b a crt Wei 1cd noinit p read s Note starts 1355SHOW at a user specified bit per pixel bpp level where can be 1 2 4 8 15 or 16 automatically cycles through all video modes displays the image on the CRT shows grid on the image displays the image on the LCD panel bypasses register initialization draws the image in portrait mode after drawing the image continually read from the screen for testing purposes displays vertical stripe pattern displays the help screen Pressing the ESC key will exit the program 1355SHOW Examples The 1355SHOW demonstration program is designed to both demonstrate and test some of the features of the SED1355 Some examples follow showing how to use the program in both instances Using 1355SHOW For Demonstration SED1355 X23A B 002 04 1 To show color patterns which must be manually stepped through all bit per pixel modes type the following 1355SHOW The program will display 16 bit per pixel mode Press any key to go to the next screen The program will display 15 bit per pixel mode Once all screens are shown the program exits To exit the program immediately press ESC 2 To show color patterns which automatically step through all bit per pixel modes type
402. r and enabling the ink layer When this function returns the ink layer is enabled transparent and ready to be drawn on Parameters DevID aregistered device ID Return Value ERR_OK operation completed with no problems ERR_FAILED if the ink layer cannot be enabled due to timing constraints this value will be returned Programming Notes and Examples SED1355 Issue Date 99 04 27 X23A G 003 05 Page 68 SED1355 X23A G 003 05 Epson Research and Development Vancouver Design Center int selnkOn int DeviD Description Enables the ink layer after a call to seInkOff If the hardware cursor has not been used between the time seInkOff was called and this call then the contents of the ink layer should be exactly as it was prior to the call to seInkOff Parameters DevID a registered device ID Return Value ERR OK operation completed with no problems int selnkOff int DevID Description Disables the ink layer When disabled the ink layer is not visible Parameters DevID aregistered device ID Return Value ERR OK operation completed with no problems int seGetinkStartAddr int DevID DWORD Offset Description This function retrieves the offset to the first byte of hardware ink layer memory Parameters DevID aregistered device ID Offset a DWORD to hold the return value Return Value ERR OK the operation completed with no problems int seSetInkColor int DevID int Index DWORD Color De
403. r sequencing General Purpose IO Pins e Up to 3 General Purpose IO pins are available Operating Voltage e 2 7 volts to 5 5 volts Package e 128 pin QFP15 surface mount package X23A C 002 13 3 RER E SYSTEM BLOCK DIAGRAM EDO DRAM FPM DRAM EPSON Analog Out lt gt Data and Kee Signals SED1 355 Digital Out Flat Panel Actual Size CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS SED1355 Technical Manual e SDU1355 Evaluation Boards e Windows CE Display Driver e CPU Independent Software Utilities Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http www epson co jp North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Hong Kong Europe Epson Hong Kong Ltd Epson Europe Electronics GmbH 20 F Harbour Centre Riesstrasse 15 25 Harbour Road 80992 Munich Germany Wanchai Hong Kong Tel 089 14005 0 Tel 2585 4600 Fax 089 14005 110 Fax 2827 4346 Copyright O 1998 Epson Research and Development Inc All Rights Reserved FOR SYSTEM INTEGRATION SERVICES FOR WINDOWS CE CONTACT Epson Research amp Development Inc Suite 320 11120 Horseshoe Way Richmond B C Canada V7A 5H7 Tel 604 275 5151 G Fax 604 275 2167 i y
404. r to establish interface requirements 2 1 1 Overview The NEC V832 is designed around the RISC architecture developed by MIPS This microprocessor is based on the 32 bit V830 CPU core The CPU communicates with external devices via the Bus Control Unit BCU The BCU in turn communicates using its ADD and DATA buses which can be dynamically sized to 16 or 32 bit operation The NEC V832 features dedicated chip select pins which allow memory mapped IO operations A 16M byte block of addressing space can be assigned for the LCD controller and its own chip select and ready signals are available Word or byte accesses are controlled by system byte enable signals LLBEN and LUBEN SED1355 Interfacing to the NEC V832 Microprocessor X23A G 012 01 Issue Date 99 05 05 Epson Research and Development Vancouver Design Center 2 1 2 Access Cycles A 23 1 Page 9 Once an address in the appropriate range is placed on the external address bus A 23 1 the corresponding chip select CSn is driven low The read or write enable signals IORD or IOWR are driven low and READY is driven low by the SED1355 to insert wait states into the cycle The byte enable signals LLBEN and LUBEN allow byte steering The following figure illustrates typical NEC V832 memory mapped IO access cycles SDCLKOUT ff Wil AE US AU AU O E VALID D 15 0 write D 15 0 read x VALID Hi Z VALID
405. rame Buffer is enabled When a single panel is selected the Half Frame Buffer is automatically disabled and this bit has no effect The half frame buffer is needed to fully support dual panels Disabling the Half Frame Buffer reduces memory bandwidth requirements and increases the supportable pixel clock frequency but results in reduced contrast on the LCD panel the duty cycle of the LCD is halved This mode is not normally used except under special circumstances such as simultaneous display on a CRT and dual panel LCD When this mode is used the Alternate Frame Rate Modulation scheme should be used see REG 31h For details on Frame Rate calculation see Section 14 2 Frame Rate Calcu lation on page 142 MD Configuration Readback Register 0 REG 1Ch RO MD 7 Status MD 6 Status MD 5 Status MD 4 Status MD 3 Status MD 2 Status MD 1 Status MD 0 Status MD Configuration Readback Register 1 REG 1 Dh RO MD 15 MD 14 MD 13 MD 12 MD 11 MD 10 MD 9 MD 8 Status Status Status Status Status Status Status Status REG 1Ch bits 7 0 MD 15 0 Configuration Status REG 1Dh bits 7 0 These are read only status bits for the MD 15 0 pins configuration status at the rising edge of RESET MD 15 0 are used to configure the chip at the rising edge of RESET see Pin Descrip tions and Summary of Configuration Options for details Hardware Functional Spe
406. re performed by modifying the start address register The start address refers to the word offset in the display buffer where the image will start being displayed from At color depths less than 15 bpp a second register the pixel pan register is required for smooth pixel level panning Internally the SED 1355 latches different signals at different times Due to this internal sequence there is an order in which the start address and pixel pan registers should be accessed during scrolling operations to provide the smoothest scrolling Setting the registers in the wrong sequence or at the wrong time will result in a tearing or jitter effect on the display The start address is latched at the beginning of each frame therefore the start address can be set any time during the display period The pixel pan register values are latched at the beginning of each display line and must be set during the vertical non display period The correct sequence for programing these registers is 1 Wait until just after a vertical non display period read register OAh and watch bit 7 for the non display status 2 Update the start address registers 3 Wait until the next vertical non display period 4 Update the pixel paning register Programming Notes and Examples SED1355 Issue Date 99 04 27 X23A G 003 05 Page 26 Epson Research and Development Vancouver Design Center 5 2 1 Registers REG 10h Screen 1 Display Start Address 0 Start Ad
407. re sampled on the rising edge Note The external bus can run at one half the CPU core speed using the clock control register This is typically used when the CPU core is operated above 50 MHz The MPC821 can generate up to eight independent chip select outputs each of which may be controlled by one of two types of timing generators the General Purpose Chip Select Module GPCM or the User Programmable Machine UPM Examples are given using the GPCM It should be noted that all Power PC microprocessors including the MPC8xx family use bit notation opposite from the convention used by most other microprocessor systems Bit numbering for the MPC8xx always starts with zero as the most significant bit and incre ments in value to the least significant bit For example the most significant bits of the address bus and data bus are AO and DO while the least significant bits are A31 and D31 The MPC8xx uses both a 32 bit address and data bus A parity bit is supported for each of the four byte lanes on the data bus Parity checking is done when data is read from external memory or peripherals and generated by the MPC8xx bus controller on write cycles All IO accesses are memory mapped meaning there is no separate IO space in the Power PC architecture Support is provided for both on chip DMA controllers and off chip other processors and peripheral controllers bus masters For further information on this topic refer to Section 6 References
408. respect to the SED1355 bus clock This gives the system designer full flexibility to choose the appropriate source or sources for CLKI and BUSCLK The choice of whether both clocks should be the same whether to use DCLKOUT as clock source and whether an external or internal clock divider is needed should be based on the desired e pixel and frame rates e power budget e part count e maximum SED1356 clock frequencies The SED1355 also has internal CLKI dividers providing additional flexibility 4 2 SED1355 Configuration The SED1355 latches MD15 through MDO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the SED1355 Hardware Functional Specification document number X23A A 001 xx The table below shows those configuration settings relevant to the Toshiba TX3912 host bus interface Table 4 1 SED1355 Configuration for Direct Connection SED1355 Pin Name Value on this pin at rising edge of RESET is used to configure 1 Vpp 0 Vss MDO MD 3 1 MD4 8 bit host bus interface Big Endian MD5 WAIT is active high 1 insert wait state MD11 Primary host bus interface selected MD12 B USCLK input divided by two use with DCLKOUT BUSCLK input not divided use with external oscillator configuration for Toshiba TX3912 host bus interface SED1355 X23A G 010 03 Interfacing to the Toshiba
409. respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 Interfacing to the Motorola MPC821 Microprocessor X23A G 008 03 Issue Date 99 05 05 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 INTOdUCHON 0 2 EE a a A A MA RR E 7 2 Interfacing to the MPC821 8 2 1 The MPC8xx System Bus BR 2 2 MPC821 Bus Overview s soa e s se s a era Poka e n 8 2 2 1 Normal Non Burst Bus Transactions e 9 2 3 Memory Controller Module Me et ok ie E E ei B L Gar AB 2 3 1 General Purpose Chip Select Module le GPCM seth nds A a daa 11 2 3 2 User Programmable Machine UPM o o 002050048 12 3 SED1355 Host Bus Interface 13 3 1 PowerPC Host Bus Interface Pin Mapping 2 2 2 2 2 2 2 13 3 2 PowerPC Host Bus Interface Signals 2 14 4 MPC821 to SED1355 Interface lt lt es 15 4 1 Hardware Description e WS 4 2 Hardware Connections a Mm e qe dads Se yay Dh er at ee L 4 3 SED1355 Hardware fia a A a Lee ALS 4 4 Register Memory Mapping 18 4 5 MPC821 Chip Select Configuration 2 2 ee ee ee 19 4 6 Test Softwar lua ee ed A ee ee a a e SU 5 Softwares ge eck eS eS E A ek we RO AA ee ee a 21 References ais aC es E
410. ring display period Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 146 Epson Research and Development Vancouver Design Center Table 14 6 Theoretical Maximum Bandwidth M byte sec Cursor Ink disabled DRAM Type Max Pixel Maximum Bandwidth M byte sec 640x480 Display Clock Speed Grade MHz 1bpp 2bpp 4bpp 8bpp 16 bpp e CRT e Simultaneous CRT Single Panel D Simultaneous CRT Dual 40 6 67 6 67 6 67 6 36 1 79 Monochrome Color Panel with Half Frame Buffer Disabled e Single Panel 40 6 67 6 67 6 60 6 27 0 41 e Dual Monochrome Color Panel with Half 50ns Frame Buffer Disabled 20 6 67 6 67 6 67 6 67 6 67 EDO DRAM MCLK 40MHz Gr GE Panel with Half Frame 40 6 27 5 11 F z S RE 20 6 67 6 67 6 67 6 67 3 94 13 3 6 67 6 67 6 67 6 67 6 67 e Simultaneous CRT Dual Mono Panel with Half Frame Buffer Enable 29 6 36 5 44 E e Dual Color Panel with Half Frame Buffer 20 6 67 6 67 6 27 6 27 Enabled 13 3 667 667 667 667 6 67 e CRT e Simultaneous CRT Single Panel e Simultaneous CRT Dual 33 5 5 5 5 5 5 5 24 1 47 Monochrome Color Panel with Half Frame Buffer Disabled Single Panel 33 5 5 5 5 5 5 5 17 0 34 e Dual Monochrome Color Panel with Half 60ns Frame Buffer Disabled 16 5 5 5 55 5 5 5 5 5 5 EDO DRAM MCLK 33MHz ae sc Panel with Half Frame 33 5 17 4 21 UIST Snapea 1
411. ro SED1355 Hardware Functional Specification Issue Date 99 05 18 Epson Research and Development Page 137 Vancouver Design Center 13 2 Image Manipulation in SwivelView Display Start Address It can be seen from Figure 13 1 that the top left pixel of the display is not at the top left corner of the virtual image i e it is non zero The Display Start Address register must be set accordingly Display Start Address words 1024 W for 16 bpp mode 1024 W 2 for 8 bpp mode Memory Address Offset The Memory Address Offset register must be set for a 1024 pixel offset Memory Address Offset words 1024 for 16 bpp mode 512 for 8 bpp mode Horizontal Panning Horizontal panning is achieved by changing the start address Panning of the portrait window to the right by 1 pixel is achieved by adding 1024 pixels to the Display Start Address register or subtracting if panning to the left e Panning to right by 1 pixel add current start address by 1024 16 bpp mode or 512 8 bpp mode e Panning to left by 1 pixel subtract current start address by 1024 16 bpp mode or 512 8 bpp mode How far the portrait window can be panned to the right is limited not only by 1024 pixels but also by the amount of physical memory installed Vertical Scrolling Vertical scrolling is achieved by changing the Display Start Address register and or changing the Pixel Panning register e Increment decrement Display Start Address register i
412. roller Physical address 0A00 0000h to OAFF FFFFh 16M bytes is reserved for an external LCD controller The SED1355 supports up to 2M bytes of display buffer The NEC Vr4102 Vr4111 address line A21 is used to select between the SED1355 display buffer A21 1 and internal registers A21 0 The NEC Vr4102 Vr4111 has a 16 bit internal register named BCUCNTREG2 located at address 0B00 0002h It must be set to the value of 0001h to indicate that LCD controller accesses using a non inverting data bus Interfacing to the NEC VR4102 VR4111 Microprocessors SED1355 Issue Date 99 05 05 X23A G 007 05 Page 14 Epson Research and Development Vancouver Design Center 5 Software Test utilities and Windows CE v2 0 display drivers are available for the SED1355 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 1355CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The SED1355 test utilities and Windows CE v2 0 display drivers are available from your sales support contact or on the internet at http www eea epson com SED1355 Interfacing to the NEC VR4102 VR4111 Microprocessors X23A G 007 05 Issue Date 99 05 05 Epson Research and Development Page 15 Vancouver Design Center 6 Reference
413. rovided by the PC Card interface e Although the SED1355 supports an asynchronous bus interface a clock source is required on the BUSCLK input pin In this implementation the address inputs AB 20 0 and data bus DB 15 0 connect directly to the CPU address A 20 0 and data bus D 15 0 M R is treated as an address line so that it can be controlled using system address A21 The PC Card interface does not provide a bus clock so one must be supplied for the SED1355 Since the bus clock frequency is not critical nor does it have to be synchronous to the bus signals it may be the same as CLKI BS bus start is not used and should be tied high connected to Vpp Interfacing to the PC Card Bus SED1355 Issue Date 99 05 05 X23A G 005 05 Page 14 Epson Research and Development Vancouver Design Center The following diagram shows a typical implementation of the PC Card to SED1355 interface PC Card socket SED1355 OE gt RDA WE gt WEO CE1 gt RD WR CE2 gt WE1 RESET RESET Vpp Bs CS SE M R A 21 0 A 20 0 ABr2o 0 D 15 0 gt DB 15 0 15K Tt WAIT E WAIT Ce BUSCLK Oscillator gt CLKI Note When connecting the SED1355 RESET pin the system designer should be aware of all conditions that may reset the SED1355 e g CPU reset can be asserted during wake up from power down modes or during debug states
414. rst enable software suspend then wait 120 VNDP and lastly reverse the polarity bits At power up first disable software suspend then revert the polarity bits back to the configuration state For hardware suspend an external hardware solution would be to use an AND gate on the sync signal One input of the AND gate is connected to a sync signal the other input would be tied to the panel s logic power supply When the panel s logic power supply is removed the sync signal is forced low SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 149 Vancouver Design Center 16 Mechanical Data 128 pin QFP15 surface mount package Unit mm 16 0 0 4 14 0 0 1 97 64 14 0 0 1 16 0 0 4 128 0 125 0 1 1 4 0 1 gt vk S f Figure 16 1 Mechanical Drawing QFP15 Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 150 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 EPSON SED1355 Embedded RAMDAC LCD CRT Controller Programming Notes and Examples Document Number X23A G 003 05 Copyright 1998 1999 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use thi
415. rst inhibit 1355 does this stw r2 OR4 r1 write to option register andis Eat D gr Glkeae ri oris r1 r1 MemStart point rl to start of SED1355 mem space stb r1 DisableReg r1 write 0 to disable register lbz r0 RevCodeReg r1 read revision code into rl b Loop branch forever end Note MPC8BUG does not support comments or symbolic equates these have been added for clarity Interfacing to the Motorola MPC821 Microprocessor X23A G 008 03 Issue Date 99 05 05 Epson Research and Development Page 21 Vancouver Design Center 5 Software Test utilities and Windows CE v2 0 display drivers are available for the SED1355 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 1355CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The SED1355 test utilities and Windows CE v2 0 display drivers are available from your sales support contact or on the internet at http www eea epson com Interfacing to the Motorola MPC821 Microprocessor SED1355 Issue Date 99 05 05 X23A G 008 03 Page 22 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents e Motorola Inc Power PC MPC821 Portable Systems Microprocessor User s Manual Motorola Publication no MPC821UM
416. ry Address CS M R Decoding The SED1355 is a memory mapped device for both the registers and the display buffer access The specific memory address is solely controlled by the CS and M R decode logic The memory space requirements are e A 2M byte linear address range for the display buffer e 47 bytes for the registers With the FPGA code that comes with this board the registers are located at 0x12000000 and the display buffer is located at 0x 12200000 3 2 FPGA Code Functionality The D9000 ODO is a flexible hardware software development system designed for use with the Microsoft Windows CE operating system It is designed so that an arbitrary set of peripherals may be quickly compiled in a way that is identical to the final product A 100K FPGA is at the center of the system and sits between the CPU and all other peripherals Most peripherals except analog components are implemented within the FPGA In order to support several different CPUs any peripherals that connect to the system have to use a common Register Interface This interface is similar to a standard bus in that it allows the CPU to read and write registers associated with the peripheral For each peripheral whether implemented internal or external to the FPGA a VHDL module has to be written to implement the register interface and to assign the necessary signals to the slot where the peripheral is going to be located The D9000 ODO platform supports 32 bit accesses
417. ry clock can be input clock or input clock 2 providing flexibility to use CPU bus clock as input Pixel clock can be the memory clock memory clock 2 memory clock 3 or memory clock 4 Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 14 2 7 Miscellaneous SED1355 X23A A 001 11 Epson Research and Development Vancouver Design Center The memory data bus MD 15 0 is used to configure the chip at power on Three General Purpose Input Output pins GPIO 3 1 are available if the upper Memory Address pins are not required for asymmetric DRAM support Suspend power save mode can be initiated by either hardware or software The SUSPEND pin is used either as an input to initiate Suspend mode or as a General Purpose Output that can be used to control the LCD backlight Power on polarity is selected by an MD configuration pin Operating voltages from 2 7 volts to 5 5 volts are supported 128 pin QFP15 surface mount package Hardware Functional Specification Issue Date 99 05 18 Epson Research and Development Vancouver Design Center 3 Typical System Implementation Diagrams Page 15 Power Oscillator Management SH 4 BUS A 21 MRE 5
418. s 6 1 Documents NEC Electronics Inc VR4102 Preliminary Users Manual Document Number U12739EJ2VOUMOO NEC Electronics Inc VR4111 Preliminary Users Manual Document Number U13137EJ2VOUMOO Epson Research and Development Inc SED1355 Hardware Functional Specification Document Number X23A A 001 xx Epson Research and Development Inc SDUI355B0C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X23 A G 004 xx Epson Research and Development Inc SED 355 Programming Notes and Examples Document Number X23A G 003 xx 6 2 Document Sources e NEC Electronics Website http www necel com e Epson Electronics America Website http www eea epson com Interfacing to the NEC VR4102 VR4111 Microprocessors SED1355 Issue Date 99 05 05 X23A G 007 05 Page 16 7 Technical Support 7 1 EPSON LCD CRT Controllers SED1355 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Avwww epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 7 2
419. s Return Value ERR Ok operation completed with no problems ERR_HAL_BAD_ARG there are several reasons for this return value 1 WhichScreen is not SCREEN1 or SCREEN2 2 the y argument is greater than the last available line Note seVirtInit must be called before calling seVirtMove 11 5 3 Register Memory Access The Register Memory Access functions provide access to the SED 1355 registers and display buffer through the HAL int seSetReg int DeviD int Index BYTE Value Description Writes Value to the register specified by Index Parameters DevID registered device ID Index register index to set Value value to write to the register Return Value ERR_OK operation completed with no problems int seSetWordReg int DevID int Index WORD Value Description Writes WORD sized Value to the register specified by Index Parameters DevID registered device ID Index register index to set Value value to write to the register Return Value ERR_OK operation completed with no problems Programming Notes and Examples SED1355 Issue Date 99 04 27 X23A G 003 05 Page 56 SED1355 X23A G 003 05 Epson Research and Development Vancouver Design Center int seSetDwordReg int DeviD int Index DWORD Value Description Writes DWORD sized Value to the register specified by Index Parameters DevID registered device ID Index register index to set Value value to write to the register Return Value ERR_OK
420. s t3 Clock pulse width high 6 6 ns t4 ADDR 12 0 setup to first CLK of cycle 10 10 ns t5 ADDR 12 0 hold from command invalid 0 0 ns t6 ADDR 12 0 setup to falling edge ALE 10 10 ns t7 ADDR 12 0 hold from falling edge ALE 5 5 ns 18 CARDREG hold from command invalid 0 0 ns to Falling edge of chip select to CARDxWAIT driven 0 15 0 9 ns t10 Command invalid to CARDxWAIT tri state 5 25 2 5 10 ns t11 D 31 16 valid to first CLK of cycle write cycle 10 10 ns t12 D 31 16 hold from rising edge of CARDxWAIT 0 0 113 Chip select to D 31 16 driven read cycle 1 1 ns t14 D 31 16 setup to rising edge CARDxWAIT read cycle 0 0 ns t15 Command invalid to D 31 16 tri state read cycle 5 25 2 5 10 ns 1 Ifthe SED1355 host interface is disabled the timing for CARDxWAIT driven is relative to the falling edge of chip select or the second positive edge of DCLKOUT after ADDR 12 0 becomes valid whichever one is later 2 Ifthe SED1355 host interface is disabled the timing for D 31 16 driven is relative to the falling edge of chip select or the second positive edge of DCLKOUT after ADDR 12 0 be comes valid whichever one is later SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 57 Vancouver Design Center Note The Philips interface has different clock input requirements as follows K ow
421. s are stored at a color depth of four bit per pixel allowing easy editing and saving in most paint programs To allow the two bit per pixel Hardware Cursor and Ink Layer to use the four bit per pixel images they are translated to two bit per pixel as in the following table Table 1 4 Bpp to 2 Bpp Translation Image Color Displayed Color white white black black red invert any other color transparent SED1355 1355BMP Demonstration Program X23A B 006 03 Issue Date 98 10 30 Epson Research and Development Page 3 Vancouver Design Center 1355BMP Examples Issue Date 98 10 30 To display a bmp image on a CRT type the following 1355BMP bmpfile bmp crt To display a bmp image on an LCD type the following 1355BMP bmpfile bmp Icd To display a bmp image on an LCD in portrait mode type the following 1355BMP bmpfile bmp lcd p To load a bmp image and a hardware cursor image on an LCD type the following 1355BMP lcd bmpfile bmp 1355BMP t cursor noinit arrow bmp To control the cursor with the mouse include the mouse option when loading the cursor image Comments e 1355BMP displays only Windows BMP format images e The PC must not have more than 12M bytes of memory when used with the SDU1355 evaluation board e A 24 bit true color bitmap will be displayed at a color depth of 16 bit per pixel e Only the green component of the image will be seen on a monochrome display e Prior to selecting t
422. s document but only for your ownuse in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 Programming Notes and Examples X23A G 003 05 Issue Date 99 04 27 Epson Research and Development Page 3 Vancouver Design Center Table of Contents T introduction sos a A eee NN a id 7 2 MitlalizatioN eg Ai Ki A A A eu e tata deg Ke 8 2 1 Miscellaneous 1 Lua e As A A a a Bee ke be Below He amp abd 3 Memory Modelen ee eee a a EN ee 12 3 1 Display Buffer Location e LA 3 1 1 Memory Organization for One Bit Per Pixel 2 Colors Gray Shades 12 3 1 2 Memory Organization for Two Bit Per Pixel 4 Colors Gray Shades 12 3 1 3 Memory Organization for Four Bit Per Pixel 16 Colors Gray Shades 13 3 1 4 Memory Organization for Eight Bit Per Pixel 256 Colors 16 Gray Shades 13 3 1 5 Memory Organization for Fifteen Bit Per Pixel 32768 Colors 16 Gray Shades 14 3 1 6 Memory Organization for Sixteen B
423. s of pages which can be selected by a tab at the top of the main window The pages are General Memory Panel CRT and Default At the bottom of the window are three buttons Open Save As and Exit The basic procedure for using 1355CFG is as follows 1 OPEN the configuration values from a current utility this step is optional 2 Change the configuration values as required see each page description for configuration details 3 SAVE the configuration values into the desired utilities or into an ASCII header file Each utility must be configured seperately Note 1355CFG is designed to work with utilities programmed using a given version of the HAL If the configuration structure is of a different version an error message is displayed SED1355 1355CFG Configuration Program X23A B 001 02 Issue Date 98 10 30 Epson Research and Development Page 9 Vancouver Design Center General Page 4352 1 355Cfg 1355test exe General Memory Panel CRT Default Memory Addresses CPU Bus Width C 8bit 16bit Register Address oe 00000 Memory Address Joxcoo000 Clock Information MCIk 25 175 MHz CIkI 251 75 D kH LCD PCIk 25 175 MHz Bus Clk e000 kHz simul CRT PCIk 25 175 MHz Save As Exit Figure 1 General Page The General Page allows the user to select the following general platform settings General Page Register
424. s several conditions e The virtual display offset must be set to 1024 pixels e The display start address is calculated differently in portrait mode e Calculations that would result in panning in portrait mode result in scrolling in portrait mode and vice versa This section will detail each of the registers used to setup portrait mode operations on the SED 1355 The functionality of most of these registers has been covered in previous sections but is included here to make this section complete The first step toward setting up portrait mode operation is to set the Hardware Portrait Mode Enable bit to 1 bit 7 of register ODh REG 0Dh Display Mode Register E Simultaneous Simultaneous Display Display Bit Per Pixel Bit Per Pixel Bit Per Pixel Pe eii eae Option Select Option Select Select Bit 2 Select Bit 1 Select Bit 0 CNT E DADIS EE Enable i e Bit 1 Bit 0 Programming Notes and Examples SED1355 Issue Date 99 04 27 X23A G 003 05 Page 38 Epson Research and Development Vancouver Design Center Step two involves setting the screen 1 start address registers Set to 1024 width for 16 bpp modes and to 1024 width 2 for 8 bpp modes REG 10h Screen 1 Display Start Address Register 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 11h Screen 1 Display Start Address Register 1 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
425. s this usage message Note 1355PWR will automatically finish execution and return to the prompt 1355PWR Examples SED1355 X23A B 007 02 To enable software suspend mode type the following 1355PWR software enable To disable software suspend mode type the following 1355PWR software disable To enable hardware suspend mode type the following 1355PWR hardware enable To disable hardware suspend mode type the following 1355PWR hardware disable To enable the LCD type the following 1355PWR lcd enable To disable the LCD type the following 1355PWR lcd disable 1355PWR Software Suspend Power Sequencing Utility Issue Date 98 10 30 Epson Research and Development Page 5 Vancouver Design Center Comments e The i argument is to be used when the registers have not been previously initialized e When using a PC with the SDU1355 evaluation board the PC must not have more than 12M bytes of system memory e GPIO1 is used to signal when the software suspend mode hardware suspend mode or LCD has been enabled or disabled e Hardware suspend is changed by reading or writing to a memory address decoded by the PAL on the SDU1355 evaluation board This PAL is currently only used for PC platforms so the SDU1355 evaluation board does not support hardware suspend on embedded platforms Program Messages ERROR Did not detect SED1355 The HAL was unable to read the revision code register on the SED 1355 En
426. scription Sets the color of the specified ink cursor index to Color The user definable hardware cursor colors are sixteen bit 5 6 5 RGB colors The hardware ink layer image is always 2 bpp or four colors Two of the colors are defined to be transparent and inverse This leaves two colors which are user definable Parameters DevID a registered device ID Index the index 0 or 1 to write the color to Color a sixteen bit RRRRRGGGGGGBBBBB color to write to Index Return Value ERR OK operation completed with no problems ERR_FAILED an index other than 0 or 1 was specified Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 69 Vancouver Design Center int seSetinkPixel int DevID long x long y DWORD Color Description Sets one pixel located at x y to the value Color The point x y is relative to the upper left corner of the display The value of Color must be 0 to 3 Values 0 and 1 refer to the two user definable colors If Color is 2 then the pixel will be transparent and if the value is 3 the pixel will be an inversion of the underlying screen color Parameters DevID aregistered device ID x y coordinates of the pixel to draw Color a0 to 3 value to draw the pixel with Return Value ERR_OK operation completed with no problems int seDrawinkLine int DeviD long x1 long y1 long x2 long y2 DWORD Color Description This routine draws a line in Color
427. set simul display mode This message is shown if the configuration settings do not meet the hardware specifications or if the desired frame rate cannot be reached within 5 See Comments on page 17 for more information WARNING Cannot set CRT display mode This message is shown if the configuration settings do not meet the hardware specifications or if the desired frame rate cannot be reached within 5 See Comments on page 17 for more information PC1k too slow to support 640 x 480 This message is shown after the Cannot set display mode message See Comments on page 17 to adjust the PCIk PClk too slow to support 800 x 600 This message is shown after the Cannot set display mode message See Comments on page 17 to adjust PCIKk Notice Invalid clock selected for VESA frequencies The monitor may not sync This message is shown in the CRT Page when the PCIK is not set to a standard VESA frequency See Comments on page 17 to adjust the PClk ERROR Unknown HAL version When reading from or writing to a SED1355 utility 1355CFG could not find the start of a valid configuration table ERROR Unable to open lt filename gt Possible cause no HAL information 1355CFG could not find the HAL configuration table ERROR encountered while reading S9 file The S9 file is corrupted ERROR while attempting to write S9 file The S9 file is corrupted 1355CFG Configuration Pr
428. sign Center LCDPWR is an output signal which follows a pre defined power up power down sequence designed to protect the LCD panel from damage caused by the power supply being enabled in the absence of control signals Determine the panel s specific power requirements and set the potentiometer accordingly before connecting the panel Evaluation Board User Manual SDU1355 D9000 Issue Date 98 10 30 X23A G 002 03 Epson Research and Development Vancouver Design Center Page 13 3 D9000 Specifics 3 1 Interface Signals The SDU1355 D9000 is designed to support the standard Register Interface of the Windows CE development platform together with the FPGA code that comes with the board 3 1 1 Connector Pinout for Channel A6 and A7 Table 3 1 Connectors Pinout for Channel A7 Channel A7 Pin FPGA Signal SED1355 Signal Pin FPGA Signal SED1355 Signal SmXY 1 chA7p1 BCLK 21 dc5v DC5V 2 chA7p2 N C 22 GND GND 3 chA7p3 N C 23 dc3v DC3V 4 chA7p4 N C 24 GND GND 5 chA7p5 N C 25 dc3v DC3V 6 chA7p6 N C 26 GND GND 7 chA7p7 N C 27 dc3vs N C 8 chA7p8 N C 28 GND GND 9 chA7p9 N C 29 dc12v DC12V 10 chA7p10 N C 30 GND GND 11 108 N C 31 battery N C 12 ib7 N C 32 GND GND 13 ib6 N C 33 dcXA N C 14 ib5 N C 34 base5vDc N C 15 ib4 N C 35 dcXB N C 16 ib3 N C 36 GND GND 17 ib2 N C 37 dcXC N C 18 ib1 N C 38 GND GND 19 GND GND 39 senseH N C 20 GND GND 40 senseL N C
429. sor core Interfacing to the Motorola MPC821 Microprocessor SED1355 Issue Date 99 05 05 X23A G 008 03 Page 12 Epson Research and Development Vancouver Design Center 2 3 2 User Programmable Machine UPM The UPM is typically used to control memory types such as Dynamic RAMs which have complex control or address multiplexing requirements The UPM is a general purpose RAM based pattern generator which can control address multiplexing wait state gener ation and five general purpose output lines on the MPC821 Up to 64 pattern locations are available each 32 bits wide Separate patterns may be programmed for normal accesses burst accesses refresh timer events and exception conditions This flexibility allows almost any type of memory or peripheral device to be accommodated by the MPC821 In this application note the GPCM is used instead of the UPM since the GPCM has enough flexibility to accommodate the SED 1355 and it is desirable to leave the UPM free to handle other interfacing duties such as EDO DRAM SED1355 Interfacing to the Motorola MPC821 Microprocessor X23A G 008 03 Issue Date 99 05 05 Epson Research and Development Vancouver Design Center 3 SED1355 Host Bus Interface The SED1355 implements a 16 bit native PowerPC host bus interface which is used to interface to the MPC821 microprocessor Page 13 The PowerPC host bus interface is selected by the SED1355 on the rising edge of RESET After releasing reset the
430. st Bus Interface Pin Mapping on page 10 SED1355 Interfacing to the NEC VR4121 Microprocessor X23A G 011 03 Issue Date 99 05 05 Epson Research and Development Page 13 Vancouver Design Center 4 2 SED1355 Configuration The SED1355 latches MD15 through MDO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the SEDI355 Hardware Functional Specification document number X23A A 001 xx The table below shows those configuration settings relevant to the MIPS ISA host bus interface used by the NEC Vr4121 microprocessor Table 4 1 Summary of Power On Reset Options SED1355 value on this pin at rising edge of RESET is used to configure 1 0 Pin Name 1 0 MDO 8 bit host bus interface MDI3 1 MD4 Big Endian MD5 WAIT is active high 1 insert wait state MD11 Alternate Host Bus Interface Selected Primary Host Bus Interface Selected configuration for NEC VR4121 microprocessor 4 3 NEC VR4121 Configuration The NEC Vr4121 register BCUCNTREG1 bit ISAM LCD must be set to 0 A 0 indicates that the reserved address space is for the LCD controller and not for the high speed ISA memory The register BCUCNTREG2 bit GMODE must be set to 1 to indicate that a non inverting data bus is used for LCD controller accesses The LCD interface must be set to operate using a 16 bit data bus This is accomplished by setting the NEC Vr4121
431. sure that the SED1355 hardware is installed and that the hardware platform has been set up correctly ERROR Unknown command line argument An invalid command line argument was entered Enter a valid command line argument ERROR Already selected SOFTWARE Command line argument software was selected more than once Select software only once ERROR Already selected HARDWARE Command line argument hardware was selected more than once Select hardware only once ERROR Already selected LCD Command line argument 1cd was selected more than once Select 1cd only once ERROR Already selected ENABLE Command line argument enable was selected more than once Select enable only once ERROR Already selected DISABLE Command line argument disable was selected more than once Select disable only once ERROR Select software hardware or lcd Did not select one of the following command line arguments software hardware or lcd Select software hardware or lcd ERROR Select enable or disable Neither command line argument enable or disable was selected Select enable or disable 1355PWR Software Suspend Power Sequencing Utility SED1355 Issue Date 98 10 30 X23A B 007 02 Page 6 SED1355 X23A B 007 02 Epson Research and Development Vancouver Design Center ERROR Too many devices registered There are too many display devices attached to the HAL The HAL currently supports only one devi
432. t We appreciate your comments on our documentation Please contact us via email at techpubs erd epson com Interfacing to the Toshiba MIPS TX3912 Processor SED1355 Issue Date 99 05 05 X23A G 010 03 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the TX3912 SED1355 X23A G 010 03 The Toshiba MIPS TX3912 processor supports up to two PC Card PCMCIA slots It is through this host bus interface that the SED1355 connects to the TX3912 processor The SED1355 can be successfully interfaced using one of the following configurations e Direct connection to the TX3912 see Section 4 Direct Connection to the Toshiba TX3912 on page 11 e System design using the ITE IT8368E PC Card GPIO buffer chip see Section 5 System Design Using the IT8368E PC Card Buffer on page 14 Interfacing to the Toshiba MIPS TX3912 Processor Issue Date 99 05 05 Epson Research and Development Vancouver Design Center 3 SED1355 Host Bus Interface Page 9 The SED1355 implements a 16 bit host bus interface specifically for interfacing to the TX3912 microprocessor The TX3912 host bus interface is selected by the SED1355 on the rising edge of RESET After releasing reset the bus interface signals assume their selected configuration For details on SED1355 configuration see Section 4 2 SED1355 Configuration on page 12 Note At reset the Host Interface Disable bit in the Miscellaneous
433. t RESET e gt M R A 25 1 AB 20 1 D 15 0 DB 15 0 SDCLKOUT BUSCLK Vop 3 3V BS 3 3V VDD_O VES 2 5V VDD ABO Note When connecting the SED1355 RESET pin the system designer should be aware of all conditions that may reset the SED1355 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 NEC V832 to SED1355 Configuration Schematic Note For pin mapping see Table 3 1 Host Bus Interface Pin Mapping on page 10 SED1355 Interfacing to the NEC V832 Microprocessor X23A G 012 01 Issue Date 99 05 05 Epson Research and Development Page 13 Vancouver Design Center 4 2 SED1355 Hardware Configuration The SED1355 latches MD15 through MDO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the SED1355 Hardware Functional Specification document number X23A A 001 xx The table below shows those configuration settings relevant to the PC Card host bus interface used by the NEC V832 microprocessor Table 4 1 Summary of Power On Reset Options SED1355 Value on this pin at rising edge of RESET is used to configure 1 0 Pin Name 1 MDO 8 bit host bus interface MD 3 1 MD4 Big Endian MD5 WAIT is active low 0 insert wait state MD11 Alternate Host Bus Interface Selected MD12 BUSCLK input divided by two
434. t and if the value is 3 the pixel will be an inversion of the underlying screen color DevID aregistered device ID x1 y1 first line endpoint in pixels x2 y2 second line endpoint in pixels Color a value of 0 to 3 to draw the pixel with ERR OK operation completed with no problems SED1355 X23A G 003 05 Page 66 Epson Research and Development Vancouver Design Center int seDrawCursorRect int DeviD long x1 long y1 long x2 long y2 DWORD Color BOOL SolidFill Description Parameters This routine will draw a rectangle in hardware cursor memory The upper left corner of the rectangle is defined by the point x1 y1 and the lower right is the point x2 y2 Both points are relative to the upper left corner of the cursor The value of Color must be 0 to 3 Values O and 1 refer to the two user definable colors If Color is 2 then the pixel will be transparent and if the value is 3 the pixel result will be an inversion of the underlying screen color If SolidFill is specified the interior of the rectangle will be filled with Color otherwise the rectangle is only outlined in Color DevID aregistered device ID x1 y1 upper left corner of the rectangle in pixels x2 y2 lower right corner of the rectangle in pixels Color a0 to 3 value to draw the rectangle with SolidFill flag for filling the rectangle interior if equal to 0 then outline the rectangle if not equal to O then fill
435. t be programmed such that REG 04h gt 3 32 pixels Note When setting a horizontal resolution greater than 767 pixels with a color depth of 15 16 bpp the Memory Offset Registers REG 16h REG 17h must be set to a virtual horizontal pixel resolution of 1024 Horizontal Non Display Period Register REG 05h RW Horizontal Horizontal Horizontal Horizontal Horizontal n a n a n a Non Display Non Display Non Display Non Display Non Display Period Bit 4 Period Bit 3 Period Bit 2 Period Bit 1 Period Bit 0 bits 4 0 Horizontal Non Display Period Bits 4 0 These bits specify the horizontal non display period Horizontal non display period pixels Horizontal Non Display Period Bits 4 0 1 x 8 The recommended minimum value which should be programmed into this register is 3 32 pixels The maximum value which can be programmed into this register is 1Fh which gives a horizontal non display period of 256 pixels Note This register must be programmed such that REG 05h gt 3 and REG 05h 1 gt REG 06h 1 REG 07h bits 3 0 1 SED1355 X23A A 001 11 Hardware Functional Specification Issue Date 99 05 18 Page 104 Epson Research and Development Vancouver Design Center HRTC FPLINE Start Position Register REG 06h RW HRTC HRTC HRTC HRTC HRTC n a n a n a FPLINE Start FPLINE Start FPLINE Start FPLINE Start FPLINE Start Position B
436. t is up to the programmer to ensure that they adhere to the interface and use valid pointers Programmers are recommended to use the highest warning levels of their compiler in order to verify the parameter types 11 4 API for 1355HAL This section is a description of the HAL library Application Programmers Interface API Updates and revisions to the HAL may include new functions not included in the following documentation Table 11 1 HAL Functions Function Description seRegisterDevice Registers the SED1355 parameters with the HAL calls selnitHal if necessary seRegisterDevice MUST be the first HAL function called by an application seGetld selnitHal Initialize the variables used by the HAL library called by seRegisterDevice Programs the SED1355 for use with the default settings calls seSetDisplayMode to do the seSetinit work clears display memory Note either seSetlnit or seSetDisplayMode MUST be called after calling seRegisterDevice seSetDisplayMode Programs the SED1355 for use with the passed display mode and flags Interpret the revision code register to determine chip id seGetHalVersion Return some Version information on the HAL library seGetLibseVersion Return version information on the LIBSE libraries for non x86 platforms seGetMemSize Determines the amount of installed video memory seGetLastUsableByte Determine the offset of the last unreserved usable byte in the
437. tartup and may be initialized as needed e g 1355PLAY EXE DevID registered device ID acquired in seRegisterDevice ERR OK operation completed with no problems ERR_FAILED unable to complete operation Occurs as a result an invalid register in the HAL_STRUCT This function calls seSetDisplayMode and uses the configuration designated to be the default by 1355CFG EXE wDefaultMode in HAL_STRUCT The programmer could call seSetDisplayMode directly allowing the selection of any DisplayMode configuration along with the options of clearing memory and blanking the display DISP_FIFO_OFF Note It is strongly recommended that the programmer call either seSetInit or seSetDisplayMode after seRegisterDevice before calling any other HAL functions If not the programmer must manually disable hardware suspend and enable the host interface before accessing the registers Programming Notes and Examples Issue Date 99 04 27 SED1355 X23A G 003 05 Page 48 SED1355 X23A G 003 05 Epson Research and Development Vancouver Design Center int seSetDisplayMode int DevID int DisplayMode int flags Description Parameters Return Value See Also Example Note This routine sets the SED1355 registers according to the values contained in the HAL_STRUCT register section Setting all the registers means that timing display surface dimensions and all other aspects of chip operation are set with this call includ
438. te a SH3 DEMO7 shortcut on the Windows NT v4 0 desktop which uses the current DEMO7 project a Right click on the Start menu on the taskbar b Click on the item Open All Users and the Start Menu window will come up c Click on the icon Programs d Click on the icon Windows CE Embedded Development Kit e Drag the icon SH3 DEMO1 onto the desktop using the right mouse button f Click on Copy Here g Rename the icon SH3 DEMO1 on the desktop to SH3 DEMO by right clicking on the icon and choosing rename h Right click on the icon SH3 DEMO and click on Properties to bring up the SH3 DEMO Properties window i Replace the string DEMO1 under the entry Target with DEMO7 j Click on OK to finish Create a sub directory named SED1355 under wince platform odo drivers display Copy the source code to the SED1355 subdirectory Add an entry for the SED1355 in the file wince platform odo drivers display dirs Modify the file PLATFORM BIB using any text editor such as NOTEPAD to set the default display driver to the file SED1355 DLL SED1355 DLL will be created during the build in step 12 Note that PLATFORM BIB is located in X wince platform odo files where X is the drive letter You may replace the following lines in PLATFORM BIB IF ODO_NODISPLAY IF ODO_DISPLAY_CITIZEN_8BPP ddi dll _FLATRELEASEDIR citi
439. tectEndian is used to determin whether th and least significant bytes ar most significant x define ENDIAN define REV_ENDIAN T 0x1234 0x3412 reversed by the given compiler Programming Notes and Examples Issue Date 99 04 27 SED1355 X23A G 003 05 Page 96 BORK RK KKK KK RAR RARA RRA RRA RRA RARA RR KARA Definitions for Internal calculations ERARIO define MIN_NON_DISP_X 32 define MAX_NON_DISP_X 256 define MIN_NON_DISP_Y 2 define MAX_NON_DISP_Y 64 JEA kkkkkkkk kk kkk kkk kkk kkk kkk k KARA RRA KI k k Definitions for seSetFont ARA RR RARA RR KARA RAR RAR RAR KARA RRA RAYS enum HAL_STDOUT HAL_STDIN HAL_DEVICE_ERR D I define FONT_NORMAL 0x00 define FONT_DOUBLE_WIDTH 0x01 define FONT_DOUBLE_HEIGHT 0x02 enum Q D ES D I BORK RR KKK KK KKK I RK kkk k Definitions for seSplitScreen kk enum SCREEN1 1 SCREEN2 y BOK KKK KKK KK RK I RRA RRA RAR KARA kkk k k k k Definitions for sePowerSaveMode ARA RIA RRA RRA RARA RRA RRA RARA RRA RRA AS SED1355 X23A G 003 05 Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 97 Vancouver Design Center define PWR_CBR_REFRESH 0x00 define PWR_SELF_REFRESH 0x01 define PWR_NO_REFRESH 0x02
440. ted bus interfaces The CPU R W block synchronizes the CPU requests for display buffer access If SwivelView is enabled the data is rotated in this block Hardware Functional Specification Issue Date 99 05 18 Epson Research and Development Page 21 Vancouver Design Center 4 2 4 Memory Controller The Memory Controller block arbitrates between CPU accesses and display refresh accesses as well as generates the necessary signals to interface to one of the supported 16 bit memory devices FPM DRAM or EDO DRAM 4 2 5 Display FIFO The Display FIFO block fetches display data from the Memory Controller for display refresh 4 2 6 Cursor FIFO The Cursor FIFO block fetches Cursor ink data from the Memory Controller for display refresh 4 2 7 Look Up Tables The Look Up Tables block contains three 256x4 Look Up Tables LUT one for each primary color In monochrome mode only the green LUT is selected and used This block contains anti sparkle circuitry The cursor ink and display data are merged in this block 4 2 8 CRTC The CRTC generates the sync timing for the LCD and CRT defining the vertical and horizontal display periods 4 2 9 LCD Interface The LCD Interface block performs Frame Rate Modulation FRM for passive LCD panels and generates the correct data format and timing control signals for various LCD and TFT D TFD panels 4 2 10 DAC The DAC is the Digital to Analog converter for analog CRT support 4 2 11 Power
441. terface Pin Mapping Epson Research and Development Vancouver Design Center SED1355 Philips S Pin SH 3 SH 4 ae pe Generic MIPS ISA pasisib cen PowerPC EAO Names PR31700 AB20 A20 A20 A20 A20 A20 LatchA20 ALE ALE A11 A20 AB19 A19 A19 A19 A19 A19 SA19 CARDREG CARDREG A12 A19 AB18 A18 A18 A18 A18 A18 SA18 CARDIORD CARDIORD A13 A18 AB17 A17 A17 A17 A17 A17 SA17 CARDIOWR CARDIOWR A14 A17 AB 16 13 A 16 13 A 16 13 A 16 13 A 16 13 A 16 13 SA 16 13 Von Vop A 15 18 A 16 13 AB 12 1 A 12 1 A t2 4 Apt2 1 Apr2 1 Apt2 1 SA 12 1 A 12 1 A 12 1 A 19 30 A 12 1 ABO Ao AO LDS AO Ao SAO Ao Ao A31 Ao DB 15 8 D 15 8 D 15 8 D 15 8 D 31 24 D 15 8 SD 15 8 D 31 24 D 31 24 D 0 7 D 15 8 DB 7 0 D 7 0 Do D 7 0 D 23 16 D 7 0 SD 7 0 D 23 16 D 23 16 D 8 15 D 7 0 WE1 WE1 WE1 UDS DS WEIS SBHE CARDxCSH CARDxCSH BI CE2 M R External Decode Vop External Decode CS External Decode Von External Decode BUSCLK CKIO CKIO CLK CLK BCLK CLK DCLKOUT DCLKOUT CLKOUT CLKI BS BS BS AS AS VDD VDD VDD Vip TS Von RD WR RD WR RD WR R W R W RD1 Vop CARDxCSL CARDxCSL RD WR CE1 RD RD RD Vop SIZ1 RDO MEMR RD RD TSIZO OE WEO WE0 WE0 Vop SIZO WEO MEMW WE WE TSIZ1 WE WAIT WAIT RDY DTACK DSACK1 WAIT IOCHRDY CARDxWAIT CARDxWAIT TA
442. terface Pin Mapping The following table shows the function of each host bus interface signal Table 3 1 PR31500 PR31700 Host Bus Interface Pin Mapping SED1355 Pin Name Philips PR31500 PR31700 AB20 ALE AB19 7CARDREG AB18 CARDIORD AB17 7CARDIOWR AB 16 13 Mee AB 12 0 A 12 0 DB 15 8 D 23 16 DB 7 0 D 31 24 WEI 7CARDxCSH M R Vip BUSCLK DCLKOUT RD WR CARDxCSL RDA RD WEO WE WAIT 7CARDxWAIT RESET RESET Interfacing to the Philips MIPS PR31500 PR31700 Processor Issue Date 99 05 05 SED1355 X23A G 001 06 Page 8 Epson Research and Development Vancouver Design Center 3 2 PR31500 PR31700 Host Bus Interface Signals SED1355 X23A G 001 06 When the SED1355 is configured to operate with the PR31500 PR31700 the host interface requires the following signals BUSCLK is a clock input required by the SED1355 host bus interface It is separate from the input clock CLKI and should be driven by the PR31500 PR31700 bus clock output DCLKOUT Address input AB20 corresponds to the PR31500 PR31700 signal ALE address latch enable whose falling edge indicates that the most significant bits of the address are present on the multiplexed address bus AB 12 0 Address input AB19 should be connected to the PR31500 PR31700 signal CARDREG This signal is active when either IO or configuration space of the PR31500 PR31700 PC Card slot is being accessed
443. tform Some target platforms can also communicate with the PC via a parallel port connection or an Ethernet connection SED1355 Supported Evaluation Platforms Installation 1355PWR supports the following SED1355 evaluation platforms e PC system with an Intel 80x86 processor e M68332BCC Business Card Computer board revision B with a Motorola MC68332 processor e M68ECOOOIDP Integrated Development Platform board revision 3 0 with a Motorola M68EC000 processor e SH3 LCEVB board revision B with an Hitachi SH 3 HD6417780 processor PC platform copy the file 1355PWR EXE to a directory that is in the DOS path on your hard drive Embedded platform download the program 1355PWR to the system 1355PWR Software Suspend Power Sequencing Utility SED1355 Issue Date 98 10 30 X23A B 007 02 Page 4 Usage Epson Research and Development Vancouver Design Center PC platform at the prompt type 1355pwr software hardware lcd enable disable i O 1 Embedded platform execute 1355pwr and at the prompt type the command line argument Where software selects software suspend hardware selects hardware suspend PC only 1lcd selects the LCD enable activates software suspend hardware suspend or the LCD disable deactivates software suspend hardware suspend or the LCD fa initializes registers 0 GPIO triggers on falling edge 1 gt 0 1 GPIO triggers on rising edge 0 gt 1 display
444. th the Start Address Registers Using this register it is possible to pan the displayed image one pixel at a time Depending on the current color depth certain bits of the pixel pan register are not used The following table shows this Table 5 2 Active Pixel Pan Bits Color Depth bpp Pixel Pan bits used 1 bits 3 0 2 bits 2 0 4 bits 1 0 8 bit 0 15 16 aay SED1355 Programming Notes and Examples X23A G 003 05 Issue Date 99 04 27 Epson Research and Development Page 27 Vancouver Design Center 5 2 2 Examples For the examples in this section assume that the display system has been set up to view a 640x480 pixel image in a 320x240 viewport Refer to Section 2 Initialization on page 8 and Section 5 1 Virtual Display on page 23 for assistance with these settings Example 3 Panning Right and Left To pan to the right increment the pixel pan value If the pixel pan value is equal to the current color depth then set the pixel pan value to zero and increment the start address value To pan to the left decrement the pixel pan value If the pixel pan value is less than zero set it to the color depth bpp less one and decrement the start address Note Scrolling operations are easier to follow if a value call it pan_value is used to track both the pix el pan and start address The least significant bits of pan_value will represent the pixel pan value and the more significant
445. the SED1355 with the defaults stored in the HAL_STRUCT if seSetInit DevId ERR_OK printf ArinERROR Unable to initialize the SED1355 r n return 1 Fa Determine the screen siz if seGetScreenSize Devid amp width amp height ERR_OK printf r nERROR Unable to get screen size r n return 1 Determine the Bpp mode and set colors appropriately Note if less than 15Bpp set the color Lookup Table LUT local color variables contain either index into LUT or RGB value seGetBitsPerPixel Devld amp Bpp if verbose printf Bpp is din Bpp switch Bpp case 1 Can t really do red and blue here seSetLut DevId BYTE amp RedBlueLut 0 0 3 color_red 1 color_blue 1 break Set the LUT to values appropriate to Black Red and Blue case 2 case 4 case 8 seSetLut DevId BYTE amp RedBlueLut 0 0 3 color_red 1 color_blue 2 break default 15 or 16 bpp color_red RED16BPP color_blue BLUE16BPP break Draw a Blue line from top left hand corner to bottom right hand corner Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 75 Vancouver Design Center Sec if seDrawLine Devld 0 0 width 1 height 1 color_blue ERR_OK printf r nERROR Unable to draw line r n return 1 Delay for 2 seconds and then
446. the greatest number of lines that can be displayed is 1024 Reducing the horizontal size makes memory available to increase the virtual vertical size In addition to the calculated limit the virtual vertical size is limited by the size and location of the half frame buffer and the ink cursor if present Seldom are the maximum sizes used Figure 5 1 Viewport Inside a Virtual Display depicts a more typical use of a virtual display The display panel is 320x240 pixels an image of 640x480 pixels can be viewed by navigating a 320x240 pixel viewport around the image using panning and scrolling 320x240 gt Viewport 640x480 Virtual Display Figure 5 1 Viewport Inside a Virtual Display Programming Notes and Examples SED1355 Issue Date 99 04 27 X23A G 003 05 Page 24 Epson Research and Development Vancouver Design Center 5 1 1 Registers REG 16h Memory Address Offset Register 0 Memory Memory Memory Memory Memory Memory Memory Memory Address Address Address Address Address Address Address Address Offset Offset Offset Offset Offset Offset Offset Offset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 17h Memory Address Offset Register 1 Memory Memory Memory n a ia ia ia wa Address Address Address Offset Offset Offset Bit 10 Bit 9 Bit 8 Figure 5 2 Memory Address Offset Registers Registers 16h and 17h form an 11 bit value called the m
447. the same whether to use DCLKOUT as clock source and whether an external or internal clock divider is needed should be based on the desired e pixel and frame rates e power budget e part count e maximum SED1356 clock frequencies The SED1355 also has internal CLKI dividers providing additional flexibility 4 2 SED1355 Configuration The SED1355 latches MD15 through MDO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the SED1355 Hardware Functional Specification document number X23A A 001 xx The table below shows those configuration settings relevant to the Philips PR31500 PR31700 host bus interface Table 4 1 SED1355 Configuration for Direct Connection SED1355 Pin Name Value on this pin at rising edge of RESET is used to configure 1 Vpp 0 Vss MDO MD 3 1 MD4 8 bit host bus interface Big Endian MD5 WAIT is active high 1 insert wait state MD11 Primary host bus interface selected MD12 B USCLK input divided by two use with DCLKOUT BUSCLK input not divided use with external oscillator configuration for Philips PR31500 PR31700 host bus interface SED1355 X23A G 001 06 Interfacing to the Philips MIPS PR31500 PR31700 Processor Issue Date 99 05 05 Epson Research and Development Vancouver Design Center 4 3 Memory Mapping and Aliasing Page 11 The PR31500 PR317
448. the size of the status revision string eg 00 F ERSION 5 define SIZI define SIZE F V bk STATUS 2 _ REVISION 3 ifdef ENABLE_DPF Debug_printf SED1355 X23A G 003 05 define DPF exp printf exp An define DPF1 exp printf texp d n exp define DPF2 expl exp2 printf texpl fexp2 Sd n expl exp2 define DPFL exp printf texp x n exp Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 95 Vancouver Design Center telse tdefine DPF exp tdefine DPF1 exp define DPFL exp void 0 void 0 void 0 endif enum tA D R_OK 0 R_FAILED E D es R_UNKNOWN_DEVICE R_INVALID_PARAMETER R_HAL_BAD_ARG R_TOOMANY_DEVS ea E HAND Bi zal D R_INVALID_STD_DEVICE D No error General purpose failure Z S call was successful E Si Ay Function was called with invalid parameter KOR KKK KK IK KK RRA RRA RRA RR OK I KK KK kkk Definitions for seGetId KARA RRA I RA RR KARA RA RRA RRA RR ARK RARA RARAS enum ID_UNKNOWN ID_SED1355 ID_SED1355F0A D I define MAX_DEVICE 10 SE RESERVED is for reserved devic define SE_RESERVED 0 De
449. tion Block Diagram o oo o 12 Interfacing to the Philips MIPS PR31500 PR31700 Processor SED1355 Issue Date 99 05 05 X23A G 001 06 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 Interfacing to the Philips MIPS PR31500 PR31700 Processor X23A G 001 06 Issue Date 99 05 05 Epson Research and Development Page 5 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment necessary to provide an interface between the SED1355 Embedded RAMDAC LCD CRT Controller and the Philips MIPS PR31500 PR31700 Processor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs erd epson com Interfacing to the Philips MIPS PR31500 PR31700 Processor SED1355 Issue Date 99 05 05 X23A G 001 06 Page 6 Epson Research and Development Vancouver Design Center 2 Interfacing to the PR31500 PR31700 SED1355 X23A G 001 06 The Philips MIPS PR31500 PR31700 processor supports up to two PC Card PCMCIA slots It is through this host bus interface that the SED1355 connects to the PR
450. tive 0 ns Note Where TrpERAME is the period of FPFRAME and Tpe1 x is the period of the pixel clock Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 76 Epson Research and Development Vancouver Design Center 7 4 2 Power Save Status Power Save Power Save Status Bit Memory Access allowed not allowed allowed Figure 7 23 Power Save Status and Local Bus Memory Access Relative to Power Save Mode Note Power Save can be initiated through either the SUSPEND pin or Software Suspend Enable Bit Table 7 22 Power Save Status and Local Bus Memory Access Relative to Power Save Mode Symbol Parameter Min Max Units t Power Save initiated to rising edge of Power Save Status and the 129 130 Frames last time memory access by the local bus may be performed t2 Power Save deactivated to falling edge of Power Save Status 12 MCLK 13 Falling edge of Power Save Status to the earliest time the local bus 8 MCLK may perform a memory access Note It is recommended that memory access not be performed after a Power Save Mode has been initiated SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 77 Vancouver Design Center 7 5 Display Interface 7 5 1 4 Bit Single Monochrome Passive LCD Panel Timing
451. to explain some of the structures used when programming the SED1355 The following header file defines the structure used to store the configuration information contained in all utilities using the SED1355 HAL API JARA RIA RRA RRA RRA RAR RAR RARA RAR RAR RAR I RRA RRA RRA RARA RRA RRA RA I RARAS 1355 HAL INF do not remove af HAL STRUCT Information generated by 1355CFG EXE Copyright c 1998 Epson Research and Development Inc All rights reserved ya za Include this file ONCE in your primary source file ed BORK ROKR KK KK RR I KA I A RK I I I I I I I HAL STRUCT HalInfo 1355 HAL EXE ID string 0x1234 Detect Endian sizeof HAL_STRUCT Size SS 0 Default Mode LCD 0x00 0x50 0x16 0x00 Ox4F 0x03 0x00 0x00 0 F 0x00 0x34 Ox00 0x00 0x0D OxFF 0x03 0 0x00 0x00 0x00 0x00 0x00 0x40 0x01 0x00 0x01 0x02 0x00 0x00 0x00 0x00 0x00 0 0x00 0x48 0x00 0x00 0x00 0x00 0x00 0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0 0x00 E DEE Sf 0x00 0x50 0x16 0x00 Ox4F 0x13 0x01 0x0B F 0x01 Ox2B 0x09 0X01 0x0E OxFF 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x40 0x01 0x00 0x00 0x02 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x48 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 SIMUL OxFF 0x50 0x16 0x00 Ox4F 0x13 0
452. to peripherals The SED1355 provides a 16 bt CPU interface and therefore the FPGA files provided with the SDU1355 D9000 convert any 32 bit accesses to back to back 16 bit cycles 3 3 Board Dimensions To obtain the required number of interface signals the SDU1355 D9000 utilizes two SmallTypeZ slots 6 and 7 Board dimensions are 2 65 x 3 20cm with both the CRT and LCD connectors acces sible on the outside edge Evaluation Board User Manual SDU1355 D9000 Issue Date 98 10 30 X23A G 002 03 Page 18 4 Parts List Epson Research and Development Vancouver Design Center Item 8 Qty Reference Part Description C1 C2 C3 C4 C5 C6 C7 1 20 C8 C9 C11 C21 C26 C27 C29 0 1uF 0 1uF ceramic capacitor C34 C35 C37 C38 C39 C40 2 5 C10 C24 C25 C32 C33 10uF 10uF tantalum capacitor 3 1 C17 47uF 10V 47uF 10V tantalum capacitor 4 1 C18 22uF 63V 22uF 63V electrolytic aluminum can capacitor 5 1 C20 10uF 63V 10uF 63V electrolytic aluminum can capacitor 6 2 C22 C30 4 7uF 4 7uF tantalum capacitor 7 3 D1 D2 D3 BAV99 BAV99 signal diode 8 2 FPS2 LCDVCC1 Header Header 3x1 1 9 4 JP2 JP3 JP4 JP5 D9000 EE Ee connector Samtec 10 1 J1 PS 2 Connector 15 pin VGA connector 11 1 LCD1 Header Header 20x2 1 12 5 L1 L2 L3 L4 L5 Ferrite bead Ferrite bead on wire 13 1 L6 1uH 1uH inductor 14 1 Q1 MMBT2222A MMBT2222A 15 7 R1 R2 R5 R6 R7 R8 R17 15K 15K
453. to the LUT The SED1355 LUT has four bits 16 intensities of intensity control per primary color while a standard VGA RAMDAC has six bits 64 intensities This four to one difference has to be considered when attempting to match colors between a VGA RAMDAC and the SED1355 LUT i e VGA levels 0 3 map to LUT level 0 VGA levels 4 7 map to LUT level 1 Additionally the significant bits of the color tables are located at different offsets within their respective bytes After calculating the equivalent intensity value the result must be shifted into the correct bit positions The following table shows LUT values that will approximate the VGA default color palette Table 4 5 Suggested LUT Values to Simulate VGA Default 256 Color Palette Index R G B Index R G B Index R G B Index R G B 00 00 00 00 40 FO 70 70 80 30 30 70 CO 00 40 00 01 00 00 AO 41 FO 90 70 81 40 30 70 C1 00 40 10 02 00 AO 00 42 FO BO 70 82 50 30 70 C2 00 40 20 03 00 AO AO 43 FO DO 70 83 60 30 70 C3 00 40 30 04 AO 00 00 44 FO FO 70 84 70 30 70 C4 00 40 40 05 AO 00 AO 45 DO FO 70 85 70 30 60 C5 00 30 40 06 AO 50 00 46 BO FO 70 86 70 30 50 C6 00 20 40 07 AO AO AO 47 90 FO 70 87 70 30 40 C7 00 10 40 08 50 50 50 48 70 FO 70 88 70 30 30 C8 20 20 40 09 50 50 FO 49 70 FO 90 89 70 40 30 C9 20 20 40 DA 50 FO 50 4A 70 FO BO 8A 70 50 30 C
454. troller running under the Microsoft Windows CE operating system Available drivers include 4 8 and 16 bit per pixel landscape modes and 8 and 16 bit per pixel portrait modes For updated source code visit Epson R amp D on the World Wide Web at www erd epson com or contact your Seiko Epson or Epson Electronics America sales representative Program Requirements Video Controller SED1355 Display Type LCD or CRT Windows Version CE Version 2 0 Windows CE Display Drivers SED1355 Issue Date 98 10 30 X23A E 001 04 Page 4 Epson Research and Development Vancouver Design Center Example Driver Builds Build for the Hitachi D9000 and ETMA ODO Evaluation Systems To build a Windows CE v2 0 display driver for the Hitachi D9000 or ETMA ODO platform follow the instructions below The instructions assume the SDU1355 D9000 evaluation board is plugged into slots 6 and 7 on the D9000 ODO platform and the SEIKO EPSON common interface FPGA ODO RBEF is used to interface with the SED1355 1 2 SED1355 X23A E 001 04 Install Microsoft Windows NT v4 0 Install Microsoft Visual C C v5 0 Install the Microsoft Windows CE Embedded Toolkit ETK by running SETUP EXE from the ETK compact disc 1 Create a new project by following the procedure documented in Creating a New Project Directory from the Windows CE ETK v2 0 Alternately use the current DEMO7 project included with the ETK v2 0 Follow the steps below to crea
455. ts system address bit O SAO e For Philips PR31500 31700 Bus this pin inputs system address bit 0 3 CS Hi Z AO e For Toshiba TX3912 Bus this pin inputs system address bit O A0 e For PowerPC Bus this pin inputs system address bit 31 A31 e For PC Card PCMCIA Bus this pin inputs system address bit O AO See Host Bus Interface Pin Mapping for summary See the respective AC Timing diagram for detailed functionality AB 12 1 e For PowerPC Bus these pins input the system address bits 19 through 30 A 19 30 119 128 e For all other busses these pins input the system address bits 12 1 2 C Hi Z through 1 A 12 1 See Host Bus Interface Pin Mapping for summary See the respective AC Timing diagram for detailed functionality Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 24 Epson Research and Development Vancouver Design Center Table 5 1 Host Interface Pin Descriptions Continued Pin Name Type Pin Cell RESET State Description AB 16 13 115 118 Hi Z e For Philips PR31500 31700 Bus these pins are connected to Vpp e For Toshiba TX3912 Bus these pins are connected to Vpp e For PowerPC Bus these pins input the system address bits 15 through 18 A 15 18 For all other busses these pins input the system address bits 16 through 13 A 16 13 See Host Bus Interface Pin Mapping f
456. ts the following interfaces 8 16 bit SH 4 bus interface 8 16 bit SH 3 bus interface 8 16 bit interface to 8 16 32 bit MC68000 microprocessors microcontrollers 8 16 bit interface to 8 16 32 bit MC68030 microprocessors microcontrollers Philips PR31500 PR31700 MIPS Toshiba TX3912 MIPS 16 bit Power PC MPC821 microprocessor 16 bit Epson E0C33 microprocessor PC Card PCMCIA StrongARM PC Card NEC VR41xx MIPS ISA bus e Supports the following interface with external logic GX486 microprocessor e One stage write buffer for minimum wait state CPU writes e Registers are memory mapped the M R pin selects between the display buffer and register address space e The complete 2M byte display buffer address space is addressable as a single linear address space through the 21 bit address bus SED1355 X23A A 001 11 Hardware Functional Specification Issue Date 99 05 18 Epson Research and Development Page 13 Vancouver Design Center 2 3 Display Support 2 4 Display Modes 4 8 bit monochrome passive LCD interface 4 8 16 bit color passive LCD interface Single panel single drive displays Dual panel dual drive displays Direct support for 9 12 bit TFT D TFD 18 bit TFT D TFD is supported up to 64K color depth 16 bit data Embedded RAMDAC DAC with direct analog CRT drive Simultaneous display of CRT and passive or TFT D TFD panels 1 2 4 8 15 16 bit per pixel bpp support on LCD CRT Up t
457. tup to falling edge ALE 10 10 ns t7 ADDR 12 0 hold from falling edge ALE 5 5 ns t8 CARDREG hold from command invalid 0 0 ns to Falling edge of chip select to CARDxWAIT driven 0 15 0 9 ns t10 Command invalid to CARDxWAIT tri state 5 25 2 5 10 ns t11 D 31 16 valid to first CLK of cycle write cycle 10 10 ns t12 D 31 16 hold from rising edge of CARDxWAIT 0 0 HS Chip select to D 31 16 driven read cycle 1 1 ns t14 D 31 16 setup to rising edge CARDxWAIT read cycle 0 0 ns t15 Command invalid to D 31 16 tri state read cycle 5 25 25 10 ns 1 If the SED1355 host interface is disabled the timing for CARDxWAIT driven is relative to the falling edge of chip select or the second positive edge of DCLKOUT after ADDR 12 0 becomes valid whichever one is later 2 Ifthe SED1355 host interface is disabled the timing for D 31 16 driven is relative to the falling edge of chip select or the second positive edge of DCLKOUT after ADDR 12 0 be comes valid whichever one is later Hardware Functional Specification Issue Date 99 05 18 SED1355 X23A A 001 11 Page 60 90 Wu Vu 10 Note The Toshiba interface has different clock input requirements as follows PWH PWL Epson Research and Development Vancouver Design Center Figure 7 11 Clock Input Requirement Table 7 11 Clock Input Requirements for BUSCLK using Toshiba local bus Symbol Par
458. ty and pulse width REG ODh 0000 1101 set 8 bpp and LCD enable REG 19h 0000 0000 set MCLK and PCLK divide REG 1Bh 0000 0001 disable half frame buffer REG 24h 0000 0000 set Look Up Table address to 0 REG 26h load LUT load Look Up Table SED1355 Programming Notes and Examples X23A G 003 05 Issue Date 99 04 27 SED1355F0A Register Summary REG 00h REVISION CODE REGISTER y For SED1355 Product Code 000011b Revision Code 00b RO Product Code Bit 3 Bit 2 Revisio Bit 1 n Code Bit 0 REG 01h MEMORY CONFIGURATION REGISTER 1 0 RW Refresh Rate n a 4 S S n a WE Control n a Memory Bit 2 Bit 1 Bit 0 Type REG 02h PANEL TYPE REGISTER 1 0 RW EL Panel Enable Panel Dat Bit 1 REG 03h Mop RATE REGISTER ta Width Bit 0 Color Mono Panel Slct Panel Data Format Slct Dual Single Panel Slct TFT Passive LCD Pan Glo n a n a Bit 5 Bit 4 REG 04h HORIZONTAL DISPLAY WIDTH n a Bit 6 Bit 5 REGISTER Bit 4 Horizontal Display Width 8 REG 1 Bit 3 Bit 2 Bit 1 RW Bit 0 REG 05h HORIZONTAL NON DISPLAY PERIOD REGISTER n a n a n a Bit 4 Bit 3 Bit 2 Bit 1 Horizontal Non Display Period 8 REG 1 RW Bit 0 REG 06h HRTC FPLINE START POSITION REGISTER REG 07h HRTC FPLINE PULSE WIDTH REGISTER HRTC FPLINE Start Position 8 REG 1 Bit 3 Bit 2 Bit 1 RW RW HRTC Polarity Slct FPLINE
459. ue Date 99 04 27 X23A G 003 05 Page 8 2 Initialization Epson Research and Development Vancouver Design Center This section describes how to initialize the SED1355 Sample code to perform the initialization is provided in the file INIT1355 C available from Epson SED1355 initialization can be broken into three steps First enable the SED1355 controller if necessary identify the specific controller Next set all the registers to their initial values Finally program the Look Up Table LUT with color values This section does not deal with programming the LUT see Section 4 of this manual for LUT programming details Note When using an ISA evaluation board in a PC i e SDU1355B0C there are two additional steps that must be carried out before initialization First confirm that 16 bit mode is enabled by writ ing to address F80000h Then if hardware suspend is enabled disable suspend mode by writing to FO0000h For further information on ISA evaluation boards refer to the SDUI355BOC Rev 1 0 ISA Bus Evaluation Board User Manual document number X23A G 004 xx The following table represents the sequence and values written to the SED1355 registers to control a configuration with these specifications e 640x480 color dual passive format 1 LCD E 75Hz e 8 bit data interface e 8 bit per pixel bpp 256 colors e 31 5 MHz input clock es 50 ns EDO DRAM 2 CAS 4 ms refresh CAS before RAS Table 2 1 SED1355 Initializati
460. ument but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 1355PLAY Diagnostic Utility X23A B 005 03 Issue Date 98 10 30 Epson Research and Development Page 3 Vancouver Design Center 1355PLAY 1355PLAY is a diagnostic utility which allows the user to read write to all the SED1355 Registers Look Up Tables and Display Buffer 1355PLAY is similar to the DOS DEBUG program commands are received from the standard input device and output is sent to the standard output device console for Intel terminal for embedded platforms This utility requires the target platform to support standard IO stdio 1355PLAY commands can be entered interactively by a user or be executed from a script file Scripting is a powerful feature which allows command sequences to be used repeatedly without re entry The 1355PLAY diagnostic utility must be configured and or compiled to work with your hardware platform The program 1355CFG EXE can be use
461. up 10 10 ns t7 CS hold 0 0 ns t8 TS setup 7 10 ns t9 TSH hold 5 0 ns t10 CLKOUT to TA driven 0 0 ns t11 CLKOUT to TA low 3 19 3 12 ns t12 CLKOUT to TA high 3 19 7 3 13 ns t13 negative edge CLKOUT to TA tri state 5 25 2 5 10 ns t14 CLKOUT to BI driven 0 18 0 11 ns t15 CLKOUT to BI high 3 16 3 10 ns t16 negative edge CLKOUT to BI tri state 5 25 2 5 10 ns t17 D 0 15 setup to 2nd CLKOUT after TS 0 write cycle 10 10 ns t18 D 0 15 hold write cycle 0 0 ns t19 CLKOUT to D 0 15 driven read cycle 0 0 ns t20 D 0 15 valid to TA falling edge read cycle 0 0 ns t21 CLKOUT to D 0 15 tri state read cycle 5 25 2 5 10 ns SED1355 Hardware Functional Specification X23A A 001 11 Issue Date 99 05 18 Epson Research and Development Page 63 Vancouver Design Center 7 2 Clock Input Requirements hi tw se tw gt 90 Vin Vu 10 f ty F gt o ty lt T osc gt Figure 7 13 Clock Input Requirement Table 7 13 Clock Input Requirements for CLKI divided down internally MCLK CLKI 2 Symbol Parameter Min Max Units Toso Input Clock Period 12 5 ns towy Input Clock Pulse Width High 5 6 ns Loun Input Clock Pulse Width Low 5 6 ns t Input Clock Fall Time 10 90 ns t Input Clock Rise Time 10 90 ns Table 7 14 Clock Input Requirements for CLKI Symbol Parameter Min Max Units Tosc Input Clock Period 25
462. urable for different panel types using a program called 1355CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The SED1355 test utilities and Windows CE v2 0 display drivers are available from your sales support contact or on the internet at http www eea epson com Interfacing to the PC Card Bus SED1355 Issue Date 99 05 05 X23A G 005 05 Page 18 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents PC Card PCMCIA Standard March 1997 Epson Research and Development Inc SED1355 Hardware Functional Specification Document Number X23A A 001 xx e Epson Research and Development Inc SED1355 Programming Notes and Examples Document Number X23A G 003 xx e Epson Research and Development Inc SDUI355B0C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X23A G 004 xx 6 2 Document Sources e PC Card Website http www pc card com e Epson Electronics America Website http www eea epson com SED1355 Interfacing to the PC Card Bus X23A G 005 05 Issue Date 99 05 05 Epson Research and Development Vancouver Design Center 7 Technical Support 7 1 Epson LCD CRT Controllers SED1355 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 55
463. us Evaluation Board User Manual Document Number X23 A G 004 xx Epson Research and Development Inc SED 355 Programming Notes and Examples Document Number X23A G 003 xx 6 2 Document Sources e NEC Electronics Website http www necel com e Epson Electronics America Website http www eea epson com Interfacing to the NEC V832 Microprocessor SED1355 Issue Date 99 05 05 X23A G 012 01 Page 18 7 Technical Support 7 1 Epson LCD CRT Controllers SED1355 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Avwww epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 7 2 NEC Electronics Inc V832 NEC Electronics Inc U S A Corporate Headquarters 2880 Scott Blvd Santa Clara CA 95050 8062 USA Tel 800 366 9782 Fax 800 729 9288 http www necel com SED1355 X23A G 012 01 Epson Research and Development Vancouver Design Center Taiwan R O C Epson Taiwan Technology 8 Trading Ltd 10F No 287 Nanking East Road Sec
464. us environment All the configuration options MD15 0 are either hard wired or selectable through the eight position DIP Switch S1 Refer to Table 2 1 Configuration DIP Switch Settings on page 8 for details Note 1 This evaluation board supports a 16 bit ISA bus only 2 The SED1355 is a memory mapped device with 2M bytes of linear addressed display buffer and a separate 47 byte register space On the SDU1355BOC the SED1355 2M byte display buffer has been mapped to a start address of CO0000h and the registers have been mapped to a start address of E00000h 3 When using this board in a PC environment system memory must be limited to 12M bytes to prevent the system addresses will conflict with the SED1355 display buffer register addresses 4 The hardware suspend enable disable address is at location FOOOOOh A read to this location will enable the hardware suspend a write to the same location will disable it Note Due to backwards compatibility with the SDU1355BOB Evaluation Board which supports both an 8 and a 16 bit CPU interface third party software must perform a write at address F80000h in order to enable a 16 bit ISA environment This must be done prior to initializing the SED1355 Failure to do so will result in the SED1355 being configured as a 16 bit device default power up with the ISA Bus interface supported through the PAL U4 configured for an 8 bit interface The Epson supplied software performs this funct
465. ust be set to 0000b zero wait state The table below shows the recommended wait states depending on the bus clock frequency Table 4 2 NEC V832 Wait States vs Bus Clock Frequency Wait States Maximum Frequency SDCLKOUT 0 12 5MHz 1 37MHz 2 No limit Note The host interface of the SED1355 is slower when disabled Therefore while the host interface is disabled REG 1Bh bit 7 1 an additional wait state is required to main tain the same respective frequency limits No idle state needs to be added The NEC V832 PICO and PIC1 register bit field corresponding to the CSn line chosen for the SED1355 must be set to zero For example if CS3 controls the SED1355 then bits 14 12 of the NEC V832 PICO register IS3 must be set to 000b no idle state SED1355 Interfacing to the NEC V832 Microprocessor X23A G 012 01 Issue Date 99 05 05 Epson Research and Development Page 15 Vancouver Design Center 4 4 Memory Mapping and Aliasing The CSn line selected determines the address range to be reserved for the SED1355 The table below summarizes the SED1355 address mapping Table 4 3 NEC V832 IO Address Range For Each CSn Line CSn Line NEC V832 IO Address SED1355 Function 0300 0000h 0300 0000h Registers CS3 to 03FF FFFFh 0320 0000h Display buffer 2M bytes 0400 0000h 0400 0000h Registers CS4 to 04FF FFFFh 0420 0000h Display buffer 2M bytes 0500 0000h 0500 0000h Registers
466. uted through JP3 and into the standard Platform II Audio Touch peripheral board Pinout assignment is described in the table below Table 2 2 Touchscreen Header TS1 Pinout Pin Signal 1 XR XL YU YL XY GND oj aj A j N 2 1 4 CRT Support The SED1355 has an embedded RAMDAC and provides complete one chip CRT support Refer to the Programmer s Notes and Examples document number X23A G 003 xx for programming details 2 1 5 Jumper Selection Jumpers labelled LCDVCC1 and FPS2 provide LCD logic supply voltage and connector pinout options respectively Jumper options are described in the table below Table 2 3 Touchscreen Header Pinout Jumper Function 1 2 2 3 LCDVCC1 LCD logic supply 3 3V 5V FPS2 FPSHIFT2 DRDY MOD Topin38 To pin 35 default settings Note Setting the panel supply voltage to 5V does not affect the signalling voltage which remains at 3 3V 2 1 6 Adjustable LCD BIAS Power Supply Many color passive LCD panels require a positive power supply to provide the LCD BIAS voltage Such a power supply has been provided as an integral part of this design The signal VDDH can be adjusted by R16 to provide an output voltage from 24V to 38V Uz 45mA and is enabled disabled by the SED1355 control signal LCDPWR Evaluation Board User Manual SDU1355 D9000 Issue Date 98 10 30 X23A G 002 03 Epson Research and Development Page 12 Vancouver De
467. utput from the SED1355 that indicates the V832 must wait until data is ready read cycle or accepted write cycle on the host bus Since V832 accesses to the SED1355 may occur asynchronously to the display update it is possible that contention may occur in accessing the SED1355 internal registers and or display buffer The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete For V832 applications this signal should be set active low using the MDS configuration input The Bus Start BS signal is not used for the PC Card Host Bus Interface and should be tied high connected to Vpp The RESET active low input of the SED1355 may be connected to the system RESET Interfacing to the NEC V832 Microprocessor SED1355 Issue Date 99 05 05 X23A G 012 01 Page 12 Epson Research and Development Vancouver Design Center 4 V832 to SED1355 Interface 4 1 Hardware Description The NEC V832 microprocessor features configurable chip select lines which can easily be used for an external LCD controller It provides all the necessary internal address decoding and control signals required by the SED1355 The diagram below shows a typical implementation utilizing the SED1355 NEC V832 SED1355 LLBEN gt RD WR LUBEN gt WE1 TORD gt RD IOWR gt WEOH CSn gt CS Pull up i READY jr WAIT System RESET g
468. uver Design Center 8 5 Examples Programming Notes and Examples Issue Date 99 04 27 Example 7 Enable portrait mode for a 640x480 display at 8 bpp Before switching to portrait mode display memory should be cleared to make the transition smoother Currently displayed images can not be simply rotated by hardware 1 The first step toward enabling portrait mode is to set the line offset to 1024 pixels The Line Offset register is the offset in words Write 200h to registers 17h 16h That is write 02h to register 17h and 00h to register 16h The second step to enabling portrait mode is to set the Display 1 Start Address The Display Start Address registers form a pointer to a word therefore the value to set the start Write COh 192 or 1024 480 2 to registers 10h 11h and 12h That is write Ch to reg ister 10h 00h to register 11h and 00h to register 12h Enable display rotation by setting bit 7 of register ODh The display is now configured for portrait mode use Offset zero into display memory will correspond to the upper left corner of the display The only difference seen by the programmer will be in acknowledging that the display offset is now 1024 pixels regardless of the physical dimensions of the display surface Example 8 Pan the above portrait mode image to the right by 3 pixels then scroll it up by 4 pixels Pan the above portrait mode image to the right by 3 pixels then scroll it up
469. ver Design Center Table 5 4 Miscellaneous Interface Pin Descriptions Pin Name Type Pin Cell RESET State Description SUSPEND 71 CS TS1 Hi Z if MD 9 0 High if MD 10 9 01 Low if MD 10 9 11 This pin can be used as a power down input SUSPEND or as an output possibly used for controlling the LCD backlight power e When MD9 0 at rising edge of RESET this pin is an active low Schmitt input used to put the SED1355 into Hardware Suspend mode see Section 15 Power Save Modes for details e When MD 10 9 01 at rising edge of RESET this pin is an output GPO with a reset state of 1 The state of GPO is controlled by REG 21h bit 7 e When MD 10 9 11 at rising edge of RESET this pin is an output GPO with a reset state of 0 The state of GPO is controlled by REG 21h bit 7 CLKI 69 Input clock for the internal pixel clock PCLK and memory clock MCLK PCLK and MCLK are derived from CLKI see REG 1 9h for details TESTEN 70 CD Hi Z Test Enable This pin should be connected to Vgg for normal operation VDD 12 33 55 72 97 109 DACVDD P 99 102 104 P VSS 14 32 50 68 78 87 96 110 DACVSS P 98 106 SED1355 X23A A 001 11 Hardware Functional Specification Issue Date 99 05 18 Issue Date 99 05 18 Epson Research an
470. was unable to read the revision code register on the SED1355 Ensure that the SED1355 hardware is installed and that the hardware platform has been set up correctly ERROR Continual screen read will not work with the a switch The continual screen read function reads one screen indefinitely so it is not possible to automatically cycle through the video modes WARNING b option used with noinit so bit per pixel and display memory will NOT be changed The b option requests that registers be changed for a given bit per pixel mode while the noinit option requests the opposite To resolve this contradiction 1355SHOW will not change either the registers or the display memory Consequently 1355SHOW b noinit is only useful for contin ually reading the display memory UNSUPPORTED MODE Cannot show bpp in portrait mode Only 8 15 16 bit per pixel modes are supported in portrait mode ERROR Could not change to bit per pixel The HAL library detected that the requested bit per pixel mode will violate the hardware specifica tions for clocks To reprogram the clocks run 1355CFG and select the desired bit per pixel mode 1355SHOW Demonstration Program SED1355 Issue Date 98 10 29 X23A B 002 04 Page 8 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1355 1355SHOW Demonstration Program X23A B 002 04 Issue Date 98 10 29 EPSON SED1355 Embedded RAMDAC LCD CRT Controller 1355SPL
471. ways smaller Thus it is possible for the display buffer size to be smaller than the virtual display but large enough to fit both the required image buffer and the half frame buffer memory This poses a maximum accessible horizontal virtual size limit Maximum Accessible Horizontal Virtual Size pixels Physical Memory Halt Frame Buffer Memory 2048 for 16 bpp mode Physical Memory Half Frame Buffer Memory 1024 for 8 bpp mode For example a 640x480 single panel running 8 bpp mode requires 480K byte of image buffer and OK byte of half frame buffer memory The virtual display size is 1024x1024 1M byte The programmer may use a 512K byte DRAM which is smaller than the 1M byte virtual display but greater than the 480K byte minimum required image buffer The maximum accessible horizontal virtual size is 512K byte OK byte 1024 512 The programmer therefore has room to pan the portrait window to the right by 512 480 32 pixels The programmer also should not read write to the memory beyond the maximum accessible horizontal virtual size because that memory is either reserved for the half frame buffer or not associated with any real memory at all The following table summarizes the DRAM size requirement for SwivelView using different panel sizes and display modes Note that DRAM size for the SED1355 is limited to either 512K byte or 2M byte The calculation is based on the minimum required image buffer size The calculated
472. x FPDAT 15 8 LN UDO a FPDAT 7 0 LN LD 7 0 CSn p cst 2 FPSHIFT p FpsHiet 4 8 16 bit A 20 0 gt AB 20 0 SE D 15 0 4 p DB 15 0 FPFRAME FPFRAME Display FPLINE FPLINE WE1 gt weg DRDY MOD BS gt pen SED1355FOA E RD WR KM RD WR LCDPWR RD Kl RDA WEO P WEG RED GREEN BLUE __ RDY 4 WAIT HRTC LN CRT vere Display m exo P BUSCLK g 3 333 A Ka RESETA KH RESETH sees mer f IREF gt Si ZE oe xa 25 256Kx EE FPM EDO DR Figure 3 1 Typical System Diagram SH 4 Bus Power Oscillator Management SH 3 BUS A 21 MRE 5 3 FPDAT 15 8 LN UD 7 0 H FPDAT 7 0 LN LD 7 0 Q CSn MN cst aA FPSHIFT FpsHirt 4 8 16 bit A 20 0 gt AB 20 0 LED D 15 0 4 gt Da 15 0 FPFRAME FPFRAME Display FPLINE FPLINE WE1 Kl WEIR DRDY LKH mop BSH H be SED1355F0A IT RD WR KN RD WR LCDPWR RD gt RD WEO P Weo RED GREEN BLUE __ WAITH 4 WAIT HRTC p CRT Were Display D m Eo P BUSCLK 38 DEER 2 2 RESET KM RESET ES S 339 IREF IREF gt SS E FEFEFE Q ay 256Kx16 FPM EDO DRAM Hardware Functional Specification Issue Date 99 05 18 Figure 3 2 Typical System Diagram SH 3 Bus SED1355 X23A A 001 11 Page 16 Epson Research and Development Vancouver Design Center
473. x01 0x0B OxDF 0x01 Ox2B 0x09 0x01 0x0F OxFF 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x40 0x01 0x00 0x01 0x02 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x48 0x00 0x00 0x00 0x00 0x00 SED1355 Programming Notes and Examples X23A G 003 05 Issue Date 99 04 27 Epson Research and Development Page 91 Vancouver Design Center y 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 ST Er C1kI kHz 8000 BusClk kHz 0OxE00000 Register Address 0xC00000 Display Address 60 Panel Frame Rate Hz 60 CRT Frame Rate Hz 50 Memory speed in ns 84 Ras to Cas Delay in ns 30 Ras Access Charge time in ns 50 RAS Access Charge time in ns 16 Host CPU bus width in bits The following header file defines the SED1355 HAL registers Issue Date 99 04 27 AK HAL_REGS H Created 1998 Epson Research amp Development Sc Vancouver Design Center Copyright c Epson Research and Development Inc 1997 1998 All rights reserved S ifndef HAL_REGS_H define HAL_REGS_H JE 1355 register names GE define REG_REVISION_CODE 0x00 define REG_MEMORY_CONFIG 0x01 define REG_PANEL_TYPE 0x02 define REG_MOD_RATE 0x03 define REG_HORZ_DISP_WIDTH 0x04 define REG_HORZ_NONDISP_PERIOD 0x05 define REG_H
474. x90 0x90 0x00 0xA0 0xA0 0x00 0xC0 0xC0 0x00 OxDO OxDO 0x00 OxEO OxEO Red to white OxFO 0x00 0x00 OxFO 0x10 0x10 OxFO 0x20 0x20 OxFO 0x40 0x40 OxFO 0x50 0x50 OxFO 0x60 0x60 OxFO 0x80 0x80 OxFO 0x90 0x90 OxFO 0xA0 0xA0 OxFO OxC0O OXCO OxFO OxDO OxDO OxFO OxEO OxEO Green to white 0x00 OxFO 0x00 0x10 OxFO 0x10 0x20 OxFO 0x20 0x40 OxFO 0x40 0x50 OxFO 0x50 0x60 OxFO 0x60 0x80 0xF0 0x80 0x90 OxFO 0x90 OxA0 OxFO 0xA0 OxCO OxFO 0xC0 0xD0 0xF0 OxDO 0xE0 0xF0 OXxEO Blue to white 0x00 0x00 OxFO 0x10 0x10 OxFO 0x20 0x20 OxFO 0x40 0x40 OxFO 0x50 0x50 OxFO 0x60 0x60 OxFO 0x80 0x80 OxFO 0x90 0X90 OxFO OxA0 OxAO OxFO OxC0 OxC0O OxFO OxDO OxDO OxFO OxEO OxEO OxFO y REGISTER_OFFSET points to the starting address of the SED1355 registers SE define REGISTER_OFFSET unsigned char 0x14000000 DISP_MEM_OFFSET points to the starting address of the display buffer memory SE define DISP_MEM_OFFSET unsigned char zi 0x4000000 DISP_MEMORY_SIZE is the size of display buffer memory define DISP_MEMORY_SIZE 0x200000 Calculate the value to put in I KE Offset DISP_MEM_SIZE X 8192 We want the offset to be just past the end of display memory so K 640 480 DISP_MEMORY_SIZE X 8192 kk CURSOR_START DISP_MEMORY_SIZE 640 480 define CURSOR_START
475. xamples of programming the SED1355 color graphics controller First is a demonstration using the HAL library and the second without These code samples are for example purposes only Lastly are three header files that may make some of the structures used clearer 12 1 1 Sample code using the SED1355 HAL API W Sample code using 1355HAL API ES ay kk Created 1998 Epson Research Development Vancouver Design Centre Copyright c Epson Research and Development Inc 1998 All rights reserved The HAL API code is configured for the following Zeck 25a E MES CIKI xx 640x480 8 bit dual color STN panel 60Hz xx 50 ns EDO 32 ms self refresh time Initial color depth 8 bpp kk SE tinclude lt stdio h gt tinclude lt stdlib h gt include lt string h gt include hal h Structures constants and prototypes include appcfg h HAL configuration information ae SC void main void int Chipld int Device An Initialize the HAL This step sets up the HAL for use but does not access the 1355 e switch seRegisterDevice amp HalInfo amp Device Programming Notes and Examples SED1355 Issue Date 99 04 27 X23A G 003 05 Page 78 Epson Research and Development Vancouver Design Center case ERR_OK break case HAL DEVICE_ERR printf AnERROR Too many devices registered exit 1 default printf
476. xel When using a PC with the SDU1355 evaluation board the PC must not have more than 12M bytes of system memory 1355SHOW uses the panel color setup to determine whether to display a mono or color image on both the panel and the CRT When editing in 1355CFG with CRT enabled and panel disabled select Color from the Panel dialog box if you want the CRT to show color For simultaneous display select both Icd and crt If the b option is not used 1355SHOW will cycle through all available bit per pixel modes SED1355 1355SHOW Demonstration Program X23A B 002 04 Issue Date 98 10 29 Epson Research and Development Page 7 Vancouver Design Center Program Messages ERROR Could not initialize device These messages generally mean that the given hardware software setup violates the timing limita tions described in the 1355 Hardware Functional Specification document number X23A A 001 xx ERROR Unknown command line argument An invalid command line argument was entered Refer to the help screen or documentation for valid command line arguments ERROR Too many devices registered There are too many display devices attached to the HAL The HAL currently supports only one device ERROR Could not register SED1355 device A 1355 device was not found at the configured addresses Check the configuration address using the 1355CFG configuration program ERROR Did not find a 1355 device The HAL
477. xel n A B selects the color for pixel n as follows Table 12 2 Ink Cursor Color Select A Bn Color Comments 00 Color 0 Ink Cursor Color O Register REG 2Dh REG 2Ch 01 Color 1 Ink Cursor Color 1 Register REG 2Fh REG 2Eh 10 Background Ink Cursor is transparent show background 41 Inverted Background ZER transparent show inverted 12 3 Ink Cursor Image Manipulation 12 3 1 Ink Image The Ink image should always start at the top left pixel 1 e Cursor X Position and Cursor Y Position registers should always be set to zero The width and height of the ink image are automatically calcu lated to completely cover the display 12 3 2 Cursor Image The Cursor image size is always 64x64 pixels The Cursor X Position and Cursor Y Position registers specify the position of the top left pixel The following diagram shows how to position a cursor P 0 0 WEBM P x 63 y P x y 63 P x 63 y 63 Figure 12 2 Cursor Positioning where X REG 29h bits 1 0 REG 28h REG 29h bit 7 0 y REG 2Bh bits 1 0 REG 2Ah REG 2Bh bit 7 0 Note There is no means to set a negative cursor position If a cursor must be set to a negative position this must be dealt with through software Hardware Functional Specification SED1355 Issue Date 99 05 18 X23A A 001 11 Page 136 Epson Research and Development Vancouver Design Center
478. y TOOLDIR With nmake in your path run nmake fmakesh3 mk 11 6 3 Building a complete application for the target example The following source code is available on the Epson Electronics America Website at http www eea epson com include lt stdio h gt include Hal h include Appcfg h include Hal_regs h int main void define RED1G6BPP 0xf800 define GREEN16BPP 0x07e0 define BLUEL6BPP 0x001f int main void T int DevId UINT height width Bpp const char pl p2 p3 DWORD color_red color_blue BYTE RedBlueLut 3 3 y BOOL verbose TRUE long xl x2 yl y2 An 0 0 Di Black OxFO 0 0 Red 0 0 OxFO Blue Call this to get hal c linked into the image and HaliInfoArray which is defined in hal c and used by other HAL pieces SC seGetHalVersion pl amp p2 amp p3 printf 1355 Hal version s n Register the devic IR pl with the HAL xx NOTE HalInfo is an instance of HAL STRUCT and is defined in Appcfg h K if seRegisterDevic Programming Notes and Examples Issue Date 99 04 27 amp HalInfo amp DevId l ERR_OK SED1355 X23A G 003 05 Page 74 SED1355 X23A G 003 05 Epson Research and Development Vancouver Design Center printf ArinERROR Unable to register device with HAL r n return 1 jx Init
479. y create flicker The LCD has a shortened aspect ratio It is necessary to suit the vertical retrace period to the CRT This results in a lower LCD duty cycle 2 525 compared to the usual 1 241 This reduced duty cycle is not extreme and the contrast of the LCD image should not be greatly reduced 11 Even Scan Only Only the even field of a 480 line image is displayed on the LCD This is an alternate method to display a 480 line image on the CRT and squash it onto a 240 line LCD Only the even scans are viewed on the LCD The LCD has a shortened aspect ratio It is necessary to suit the vertical retrace period to the CRT This results in a lower LCD duty cycle 2 525 compared to the usual 1 241 This reduced duty cycle is not extreme and the contrast of the LCD image should not be greatly reduced Hardware Functional Specification Issue Date 99 05 18 SED1355 X23A A 001 11 Page 108 Epson Research and Development Vancouver Design Center Note 1 Dual Panel Considerations When configured for a dual LCD panel and using Simultaneous Display the Half Frame Buffer Disable REG 1Bh bit 0 must be set to 1 This results in a lower contrast on the LCD panel which may require adjustment 2 The Line doubling option is not supported with dual panel bits 4 2 Bit per pixel Select Bits 2 0 These bits select the color depth bpp for the displayed data See Section 10 1 Display Mode Fo
480. y the start top left pixel within the Screen 1 image stored in the display buffer See Display Configuration for details Hardware Functional Specification Issue Date 99 05 18 SED1355 X23A A 001 11 Page 110 Epson Research and Development Vancouver Design Center Screen 2 Display Start Address Register 0 REG 13h RW Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O Screen 2 Display Start Address Register 1 REG 14h RW Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Screen 2 Display Start Address Register 2 REG 15h RW nla na na ia Start Address Start Address Start Address Start Address Bit 19 Bit 18 Bit 17 Bit 16 REG 13h bits 7 0 REG 14h bits 7 0 REG 15h bits 3 0 Screen 2 Start Address Bits 19 0 These registers form the 20 bit address for the starting word of the Screen 2 image in the display buffer Note that this is a word address A combination of this register and the Pixel Panning register REG 18h can be used to uniquely identify the start top left pixel within the Screen 2 image stored in the display buffer See Display Configuratio
481. ytes to write Return Value ERR Ok operation completed with no problems ERR_HAL_BAD_ARG if the value for Offset is greater than the amount of installed memory Note If offset count gt memory size this function will limit the writes to the end of memory int seWriteDisplayWords int DevID DWORD Offset WORD Value DWORD Count Description Writes one or more words to the display buffer Parameters DevID registered device ID Offset offset from start of the display buffer Value WORD value to write Count number of words to write Return Value ERR_OK operation completed with no problems ERR_HAL_BAD_ARG if the value for Offset is greater than the amount of installed memory Note If offset count 2 gt memory size this function will limit the writes to the end of memory Programming Notes and Examples SED1355 Issue Date 99 04 27 X23A G 003 05 Page 58 SED1355 X23A G 003 05 Epson Research and Development Vancouver Design Center int seWriteDisplayDwords int DevID DWORD Offset DWORD Value DWORD Count Description Writes one or more dwords to the display buffer Parameters DevID registered device ID Offset offset from start of the display buffer Value DWORD value to write Count number of dwords to write Return Value ERR_OK operation completed with no problems ERR_HAL_BAD_ARG if the value for Offset is greater than the amount of installed memory Note If offset c
482. zen dll NK SH Windows CE Display Drivers Issue Date 98 10 30 Epson Research and Development Vancouver Design Center Build For CEPC X86 Windows CE Display Drivers Issue Date 98 10 30 10 11 12 1 2 3 Page 5 ENDIF IF ODO_DISPLAY_CITIZEN_2BPP ddi dl1l S _FLATRELEASEDIR citizen dll NK SH ENDIF IF ODO_DISPLAY_CITIZEN_8BPP IF ODO_DISPLAY_CITIZEN_2BPP ddi dl1 _FLATRELEASEDIR Modo2bpp dl1 NK SH ENDIF ENDIF ENDIF with this line ddi dli _FLATRELEASEDIR 1SED1355 d11 NK SH Edit the file MODE H located in X wince platform odo drivers display SED1355 to set the desired screen resolution color depth bpp and panel type The sample code defaults to a 640x480 color dual passive 16 bit LCD panel To support one of the other listed panels change the define statement Edit the file PLATFORM REG to set the same screen resolution and color depth bpp as in MODE H PLATFORM REG is located in X wince platform odo files The display driver section of PLATFORM REG should be Default for EPSON Display Driver 640x480 at 8bits pixel Useful Hex Values 768 0x300 640 0x280 480 0x1E0 320 140 240 0xF0 1024 0x400 HKEY_LOCAL_MACHINE Drivers Display SED1355 CxScreen dword 280 CyScreen dword 1E0 Bpp dword 8 Generate the proper building environment by double clicking o

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