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IBM Dual Bridge and Memory Controller CPC710

1. SYS ADDR SYS TS SYS TA SYS DATA 4281 4 MUX_MDATA m 22 030 a MEM DATA DH D 1 D3 MEM DATA DL m U O 1 02 1A MEM STATUS 05005 5 75 aetiv Bust 4 prech activ jprechi E ESO EE EE WU a ee ee ee MEE MADDR SDRAS SDCAS WE SDDQM idis eS RS ERN m Ro Write 1 amp 2 3 amp 4 Page 214 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Write One Byte to Memory from CPU Read Modify Write 0 1 2 8 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 CLK100MHz LILILILIELILILILIT LI LELITLELITLELIT LE LIT LI LI LI LIT LI LI LI Ls SYS ADDR SYS TS dj SYS TA SYS DATA MUX MDATA i CCbWw 0 Modified DW 0 MEM DATA and EE NM mmm DW i Modified DWD MADDR MEM STATUS JD DD D Activ Read Write Prech
2. SYS_TS SYS_TA SYS_DATA O EA EEI MUX_MDATA MEM DATADH MET D3 MEM_DATA DL p 72 Da a MEM_STATUS a a o faan Meee Enel Ne ck 3074991 9 1 353 O7 V IBI MADDR SDRAS SDCAS WE SDDQM ee S228 MONROE SafoSRCEEREIESEE 6 26 2000 Page 211 of 209 IBM Dual Bridge and Memory Controller Read Page Miss from PowerPC CPU to SDRAM CLK100MHz SYS ADDR SYS_TS SYS_TA SYS_DATA MUX_MDATA MEM_DATA DH MEM_DATA DL MEM_STATUS MADDRESS SDRAS SDCAS WE SDDQM SDCKE Page 212 of 209 011 2 1314 5 16 7 8 9 110 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1I2 8 4 Dt Bs s ma at S Late 3 f4 IBM Dual Bridge and Memory Controller Write Burst Page Hit from PowerPC CPU to SDRAM
3. Reset Value x 3010 0000 Address x FF20 0000 Access Type Read Only 5 t o g 9 E 8 5 2 5 g 5 o c 5 8S zg 5 Es 9 o o t o 8 HE 3 8 5 B8 88 cs g E b EO Gc ke o Device Type zs E 25 Reserved us 2 g Y vovv ovv vov vov ovx vov ox 0 1 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 3 Device Type 0011 l O device 4 5 BUID Allocation Indicator 00 NO BUID Required 6 7 Reserved 8 11 Memory Allocation Indicator for Control Space 0001 1 MB 12 24 Reserved 25 26 Feature vpd ROM Size Characteristics 00 No Feature VPD ROM present Address Increment 27 29 900 4 byte Increment 30 31 Reserved 6 26 2000 Page 138 of 209 IBM Dual Bridge and Memory Controller Device ID Register DID This register provides specific device type information Reset Value x 08020 1100 Address x FF20 0004 Access Type Read Only 2 gt co a a Reserved Device ID Type Field Specific Device ID Ly voy voy Y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 IBM Device d IBM Device 1 7 Reserved 8 23 Device ID Type Field x 2011 Device PCI Bridge Specific Device ID 24 31 x 00 PCI 32 bridge x 01 PCI 64 bridge 6 26 2000 Page 139 of 209 CPC710 133 IBM Dual Bridge and Memory Controller Base Address Register BAR This registe
4. 189 PCI Master Memory Read Cycles essssisssesesseeeeeeeesen nennen nnnm nennen nnne essent nein snnt 190 PCI Master Memory Write Cycles essssesseseeeneneeeneneneen nene nnnm e nennen enne 191 GOMMGUFATION eiTe E 192 TYPE 0 Configuration Gycles rr t ae Re ue xcu m xu RR CURO du pu NER XRR S MEER RRR ME uy 193 Type 1 Configuration Cycles cuire caedere de th ert re Ente code roten ied ute danh ERR ne 193 PCI Address Data Bus for TYPE 0 Configuration Cycles eren 193 PCI Performance Estimates cure cieccceec cies ce eceeiim ec ces siio sm aa aA 194 PCI Master Error Handling cciiceecr ciiceae cruce tec xxu tenu kan aaa 195 System VO Interface e 197 CONTIG UN ATION m M 197 System I O Registers Application Presence Detect Bits cccccceeseseeeeeeeeeeeeeeeeeeeeeeeneeneenaees 197 Etiam no nS N 197 BOOUROM MT Rs 197 DMA Controler estie E ae abd EDD Diretto a aaae Eae ERN E eE 199 Introduction osisssa aE aE AAKE EEE NA EE ESAE AEEA 199 Mode of operation of the DMA sessi nennen nnne entr nnns n nnn nn nannamamma nnmnnn 199 EicunbDEGIeDu 199 Wrte in the XTAR TOISTOT perisis aani ee eee Ced etus sve rab ee te E gae Fee Du e runs eth ed dein
5. Bit s Description 0 31 User defined The read of this register results in the assertion of the PRES OE1 signal and a Read cycle through the PCI32 A D lines That permits a read of the outside buffers containing the presence detect bits Bit 0 of this register correspond to bit 31 on the PCI A D lines 6 26 2000 Page 129 of 209 CPC710 133 IBM Dual Bridge and Memory Controller DMA Registers Space DMA Global Control GSCR Reset Value x 0000 0000 Address User x FF1C 0020 Privileged x FF1E 0020 Access Type User Read Only Privileged Read Write Bit s Description DMA Transfer Enable 00 Reset DMA Controller to default power up mode Wd 10 DMA Controller disabled 11 DMA Controller is enabled 2 Reserved R W Interrupt Enable 3 When set generates an interrupt at the completion of a DMA transfer 0 IT2 disabled 1 IT2 enabled Interrupt Status 4 0 End of DMA transfer interrupt IT2 not asserted 1 End of DMA transfer interrupt IT2 asserted Software must write a 0 to Reset the IT2 Interrupt Extended DMA Transfer Enable 5 0 Single DMA transfer 1 Extended DMA Direction for Extended DMA 6 0 PCI to MEMORY ECOWX 1 MEMORY to PCI ECIWX 7 Reserved R W Must be left to 0 8 15 Reserved RO Number of DMA Transfer Loops to Do if Extended DMA is enabled 16 31 During an Extended DMA contains the number of loops remaining If bit 5 is enabled and this register is set to 0 the mode is a single
6. e reeeeeeeereenen nnne nnn nennen nnn nanne nnn nn 212 Write Burst Page Hit from PowerPC CPU to SDRAM senes 213 Write Burst Page Miss from PowerPC CPU to SDRAM eene nnne nnn nnn 214 Write One Byte to Memory from CPU Read Modify Write eere 215 CPU Access to the Boot ROM 11 cauce eiee c eccc etiem ccce ream ne creda an acra a kane ec a ak ame C a ak ame c cc a pase ca aax 216 Read of One Byte from the Boot ROM enses eene nennt nennen nurse nent naris 216 Write of One Byte to the Boot Flash esseeeeeeeeseeeeeee einen nennen nnns anne nnns innen nna rin nn nnns 216 PCI 64 external Master accessing the SDRAM Memory seen enne 217 217 READ 32 Bytes from the SDRAM by a PCI Master on PCI 64 66MHz bus 217 Write of 32 Bytes in the SDRAM from a PCI Master on the PCI 64 66MHz bus 218 Electrical Specifications eT T anene 219 Absolute Maximum Ratings 4 eeseeeeeeneeeeen enne nnne nnn nnn nnmnnn nnmnnn nenne nnmnnn ennnen nna 219 Recommended DC Operating Conditions esee eese nennen nennen nnns 219 Driver Receiver Specifications eeeeeeeeeeee senes een eee e
7. essen enne 99 Specific System Registers Space eeseseeeeeeeeseeee sense eene nnne nen nn nnn n innen nnn na nsns nnn nn nn 100 Universal System Control UCTL ssssssssessssseeene eene nenne onian nennen 100 Multi Processor Semaphore MPSR ssssssssssseseseseeenenre eene ene en nennen nnn rr en nnn nsn nnns 102 System VO Control SIOC M R 103 60x Arbiter Control Register ABCNTL ssssssssseeeeeeneeeeneenn eee enne nnne nnne enn 104 CPU Soft Reset Register SRST sessssssseeeeesee entente eren nnns nennen necne nns 106 Error Control Register ERRC ccceeescsceeeeensneeeeeeeaaeeeeeeeaaaeee essen ennt nant ennt ressent nennen tenens 107 System Error Status Register SESR sse eene nennen nnns 108 Table of Contents Page 2 of 209 6 26 2000 IBM Dual Bridge and Memory Controller System Error Address Register SEAR sss eene 110 Chip Programmability Register PGCHP essssssssssssssseseeeerere nnne nnne nnns 111 Free Register 1 RGBANT idit poete eR REN REM run eR ntu ua ke E una edu REN RN RU EN Teu a a Rueda unen es 113 Free Register 2 RGBAND ieri ERR RR HR RRKEXR NER ANRRE een NERERA NR SE aeaa RAE NEAR a rA Re NER ERRE 114 GPIO Direction Register GPDIR c ccccceceeeeeeeeeeeeaaeaeeeeeeeeeeececeaeaanaeeaeeeeeeeeseeeeeaencaeaeeeeeeetes 115 GPIO
8. SDRAS SE NS EE MEE SDCAS WE CAS Latency 3 s ie on pru crc M AS M ee SDDQM b OW a SDCKE 6 26 2000 Page 215 of 209 IBM Dual Bridge and Memory Controller CPU Access to the Boot ROM Read of One Byte from the Boot ROM oucioomiz TULLIUM UU UU UU UL SYS_ADDR AT SYS TSIZ d SYS TS SYS TA SYS DATA PCI_AD 31 0 MO A EN o vet XADR LAT hott ee ee aaae ens FLASH_OE XCVR_RD Write of One Byte to the Boot Flash cucoowuz SOUU UYU UU YUU UU UU UU UU Code1 2 3 Data T a i oh ted For d Fog dod bod FFFQ5555 FFF02AAA FRF05555 FFFO2000 to i p i p d E a bi Ak T SYS_ADDR i i E EC e E e p SYS TSIZ 1 i 1 E sets WU WU SYS_TA ZE qd cox Puis S aa c U SYS_DATA i i Code 1 oee a EM a docs a roam Code 0o NENNEN MEE FLASH WE box o 4 DU X o uS d p DIY 3 EEUU a PME l ee eee P T E M Write of the Data in the fla h after the 4th WE Q1 10 420 gt 430 gt 40 4 7 50 60 XCVR RD Page 216 of 209 6 26 2000 IBM Dual Bridge and Memory Controller PCI 64 external Master accessing the
9. sse ener en nerit en rentrer nennen nnns 81 System Address Space SIZE for PCI PSSIZE seen eene 82 System Base Address Register BARPS ssssssssssssesseseeeeeenn nennen nennen nnns 83 System Base Address Register for PCI 32 PSBAR seessssseeeeene enne 84 Bottom of Peripheral Memory Space With Potential Deadlock BPMDLK susssusss 85 Top of Peripheral Memory Space With Potential Deadlock TPMDLK sess 86 Bottom of Peripheral I O Space With Potential Deadlock BIODLK sees 87 Top of Peripheral I O Space With Potential Deadlock TIODLK ccccceeeeeeeeeeeeeeeeceeeeeeeeeees 88 Reset Addressed Interrupt Register IT ADD RESET seen eene 89 Set PCI 64 Interrupt Register INT SET sssssseseeeeeneneenn enemies 90 Channel Status Register CSR essssssssssssssseesee eee nennen nennen trennen nnns 91 Processor Load Store Status Register PLSSR sese 92 System Registers Space iicseicuiacessce kae eecucekkasaonse EAEE aa 93 Physical Identifier Register PIDR ssessseseseeeneneeeneeeeene nennen enne enne 96 Connectivity Configuration Register CNFR sss enemies 97 Connectivity Reset Register RSTR sse enne nn en nnn trennen rre nnns 98 Software Power On Reset Control Register SPOR
10. Reserved PSEM Semaphores for PCI 64 only IT ADD SET for PCI 64 only INT RESET for PCI 64 only Reserved 6 26 2000 Page 39 of 209 CPC710 133 IBM Dual Bridge and Memory Controller Standard PCI Configuration Register List Relative Address Name Use 00 to 01 VID Vendor ID Register 02 to 03 DEVID PCI Device ID Register 04 to 05 CMND Command Register 06 to 07 STAT Status Register 08 RID Revision ID 09 SPI Standard Programming Interface 00A SUBC Sub class Code 0B CLASS Base Class Code 0C CSIZE Cache Line Size oD LTIM Latency Timer 0E HDRT Header Type OF BIST Built In Self Test 10 PSBAR System Base Address Register for PCI 64 3C INTLN Interrupt Line 3D INTPIN Interrupt Pin 3E MINGNT Minimum Grant 3F MAXLT Maximum Latency 40 BUSNO Bus Number 41 SUBNO Subordinate Bus Number 42 DISCNT Disconnect Counter 50 RETRY Retry Counter s TEE 1 64 IT ADD SET Set PCI 64 Inter Processor INT1 Interrupt 68 INT_RESET Reset of INTA INTB INTC INTD on the PCI 64 Read Only Register write is ignored Writes will only reset bits in this register write data interpreted as 1 reset 0 ignore Only for PCI 32 Only for PCI 64 PONH Page 40 of 209 Page 41 41 42 44 46 46 47 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Notes 1 6 26 2000 IBM Dual Bridge and Memory Controller Vendor ID VID This register identifies the device manufacturer Reset V
11. IBM Dual Bridge and Memory Controller Channel Status Register CSR This register is used to log errors during PCI Master to system transfers Please see PCI Master Error Han dling on page 195 for additional details Reset Value x 0000 0000 Address BAR 000F 9800 Access Type Read Write E 2 o 2 o gt a gt 3 T Tog 2 TE z ges S o io c 5 as 5 m E E E 9 2523 9 Bee o o iu gt a gt gt EN zi 2 5 apg 5 Sas 3 of 3 oO 6 itrati R amp 5 a Arbitration Level eserved V i vy s e A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 1 Reserved PCI Bus Address Parity Detected 2 0 No Error 1 PCI Bridge detected address parity error SERR Detected 3 0 No Error 1 PCI Bridge detected G P_SERR during transaction Invalid Memory Address 4 0 No Error T PCI access occurred to invalid system memory address 5 7 Reserved Memory Error 8 0 No Error 1 Double bit ECC error occurred during memory access Bus Time out 9 0 No Error i PCI Bridge detected bus time out no IRDY detected see Disconnect Counter DISCNT on page 59 10 Reserved 11 15 Arbitration Level Encoded arbitration level of PCI device when error occurred 16 31 Reserved 6 26 2000 Page 91 of 209 CPC710 133 IBM Dual Bridge and Memory Controller Processor Load Store Status Register PLSSR T
12. IBM Dual Bridge and Memory Controller CPC710 100 User Manual Version 1 3 June 26 2000 Copyright International Business Machines Corporation 2000 All Rights Reserved Printed in the United States of America May 2000 The following are trademarks of International Business Machines Corporation in the United States or other coun tries or both IBM IBM logo PowerPC Other company product and service names may be trademarks or service marks of others All information contained in this document is subject to change without notice The products described in this docu ment are NOT intended for use in implantation or other life support applications where malfunction may result in injury or death to persons The information contained in this document does not affect or change IBM s product specifications or warranties Nothing in this document shall operate as an express or implied license or indemnity under the intellec tual property rights of IBM or third parties All information contained in this document was obtained in specific environ ments and is presented as an illustration The results obtained in other operating environments may vary THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN AS IS BASIS In no event will IBM be liable for damages arising directly or indirectly from any use of the information contained in this document IBM Microelectronics Division 1580 Route 52 Bldg 504 Hopewell Junct
13. URMIRD 155 INCL Ip 155 Qualified SYS BG Equallon rint rarae Eh one eae Nruna eeu une E AARAA NNE CARRAR 155 SYS TS ASSerlio eC rpE 155 SYS BR NEGANDO E 155 Qualified SYS DBG EquatliOn oie iieri E ERANA AAA AANA AAA 155 High Impedance After SYS LEA ccssctccsietties soseous sock wceanaestecduedcueesdeat ane svsnsuueecwedssveeceeuadeeenest 155 SYS DRIRY ASSGITIONN BER ER 155 Slave Data Bus Determination ccsctecccccsennteeccasenncezecusnneenecasnntenedun cone nneereseientesetsncuedoedatenuseeed 156 SYS L2 LIST Em 156 B s Enhancements sscan eene e Eee a een rete cane nsec E E 157 DBB not Required by Masters ccccccccesesecceeeeeeeecceeeeeseeceeeeeseaaeeeesnaaaeeeesneeaeseeenseaaeeeeeneaaees 157 Half Cycle Precharge not Required on SYS TA sees rernm 157 Half Cycle Precharge not Required on SYS TEA serere eene 157 SYS ARTRY PREV in QDBG Equation Eliminated scere 157 60x Bus Transfer Types and Sizes essssesssssssessseesennnee eee EEA nennen inen nn nnns 158 159 Data Gathering E 160 3 lecidudoc
14. Normally means that dummy zeros are returned for loads and write data is ignored 6 26 2000 Page 195 of 209 IBM Dual Bridge and Memory Controller PCI Master Error Handling Page 2 of 2 Operation Error Mode Invalid Address Detected SERR Active Access to System pps Enabled by con Detected PCI Bus Data a Parity Error during PCI Master Store Disabled Detected PERR during PCI Master Load Received Master Abort PCI Bus Timeout IRDY Count Expired Access to Internal Response Bus Device on Contains PCI Error 2nd PCI Bus Status Notes Notes Action Set invalid address error in MESR Set error address in MEAR Set invalid memory address bit in CSR Loads Target abort PCI transfer Set signaled target abort bit in PCI status register Signal Machine Check with MACHK Stores Signal Machine Check with MACHK Set SERR detected error bit in CSR register Save encoded ARB level in CSR register Target abort PCI transfer Set signaled target abort bit in PCI status register Signal Machine Check with MACHK Activate the PERR signal Set parity error bit 15 in PCI Status register Complete PCI transfer however Flush store data do not write to memory Set parity error bit 15 in PCI Status register Proceed normally with PCI transaction Proceed normally with PCI transaction 1 Proceed normally with PCI transaction 1 Target abort PCI transfer Set signaled target abort bit in PCI status regi
15. PCI bridge logic busy Is this the last location in the buffer No No there a store buffer available Wait for buffer to empty Yes v Reset first flag Initiate command to send store buffer data to PCI Page 160 of 209 6 26 2000 IBM Dual Bridge and Memory Controller SYNC and EIEIO When a processor executes a SYNC instruction a SYNC address only tenure is broadcast on the 60x bus to notify the system that a software placed barrier is present The system is responsible for ensuring all previ ously executed load and store operations are complete and all resultant actions are visible to the system The device satisfies this requirement by SYS ARTRYing the SYNC operation until all of its store buffers are empty all reads have been executed and all data have been placed in internal device buffers for requests issued by the same processor issuing SYNC When a processor broadcasts an EIEIO on the 60x bus the system is responsible for ensuring all previous transactions are complete before executing operations The device does not SYS ARTRY the EIEIO because the 60x logic dispatches bus transactions to the logic units in the order in which they occur on the System bus and each logic unit executes its commands in the order received For diagnostic purposes the device can be programmed to SYS_ARTRY the EIEIO in the same manner as SYNC see bit
16. 4Mx4 4Mx16 4Mx4 4Mx16 4Mx16 8Mx8 8Mx32 8Mx32 8Mx8 16Mx4 16Mx16 16Mx4 16Mx16 32Mx8 64Mx4 Number of Chips per Bank with ECC 4 1 8 1 2 1 2 1 8 1 16 2 4 1 16 2 4 1 4 1 8 1 2 1 2 1 8 1 16 2 4 1 16 2 4 1 8 1 16 2 DIMM Size MByte 16M Dual 32M Dual 64M Dual 128M Dual 256M Dual 512M Dual 1024M Dual IBM Dual Bridge and Memory Controller SDRAM Addressing bit Row Col Bank 11 8 1 11 9 1 11 9 1 11 8 2 12 8 1 11 10 1 11 10 1 12 8 2 12 9 1 13 8 1 12 9 2 12 9 2 13 8 2 13 9 1 12 9 2 12 10 2 12 10 2 12 10 2 13 10 1 13 9 2 13 10 2 13 10 2 13 11 2 Note The number of chips per MCER is double the number of chips per DIMM bank SDRAM Buffering Requirements SDRAM Number of Chips MB x I Os per Bank 1Mx16 2Mx8 2Mx32 2Mx32 2Mx8 4Mx4 4Mx16 4Mx16 4Mx4 4Mx16 8Mx8 8Mx32 8Mx32 8Mx8 8Mx16 16Mx4 16Mx8 16Mx16 16Mx4 16Mx16 32Mx8 32Mx4 64Mx4 with ECC 4 1 8 1 2 1 2 1 8 1 16 2 4 1 4 1 16 2 4 1 8 1 2 1 2 1 8 1 4 1 16 2 8 1 4 1 16 2 4 1 8 1 16 2 16 2 The SDRAM interface is designed to run in a 100 MHz environment Because signal loading is critical some outputs connect to four or eight pins The following table lists loads and running frequencies for all SDRAM signals that use the 60x bus clock 6 26 2000 Page 177 of 209 IBM Dual Bridge and Memo
17. IBM Dual Bridge and Memory Controller Sub Class Code SUBC Reset Value x 00 Address x 0A Access Type Read Only Sub Class Code v Y 7 6 5 4 3 2 1 0 Bit s Description Specifically identifies a particular function of the Base Class Code register Device always responds with x 00 for reads Pu to indicate a HOST type of bridge device Base Class Code CLASS Reset Value x 06 Address x OB Access Type Read Only Base Class Code Bit s Description Classifies the type of function this device performs Device always responds with x 06 for reads to indicate a Bridge device 6 26 2000 Page 47 of 209 CPC710 133 IBM Dual Bridge and Memory Controller Cache Line Size CSIZE Reset Value x 08 Address x 0C Access Type Read Only Cache Line Size v Y T 8 8 4 8 2 9 Bit s Description Specifies the cache line size in units of 32 bit words Device always responds with x 08 for reads to indicate that device FM will always disconnect from any PCI master burst operation that crosses a 32 byte boundary Page 48 of 209 6 26 2000 Latency Timer LTIM Description IBM Dual Bridge and Memory Controller Provides bus masters with a minimum guaranteed time slice on the PCI bus The value programmed into this register is Reset Value x 00 Address x 0D Access Type Read Write Latency Timer v Y 7 6 5432 10 Bit s 7 0 6 26 2000 the
18. unm nuu au pu uuu MDATA SDRAM DH SDRAM DL MADDR RAS CAS WE CKE 66MHz Clock CBE 7 0 PCI AD 63 32 fff PCI AD 31 0 OK G FRAME G IRDY G TRDY G STOP Page 218 of 209 14 34Pd p B4 78 7 Write Precharge 00 00 00 Ey 32 bit Word 1 32 bit Word TUE Az o Dai R Kad 10 20 E 00 2 5 40 5d WRITE to the SDRAM from a PCI Master on PCI 64 6 26 2000 IBM Dual Bridge and Memory Controller Electrical Specifications Absolute Maximum Ratings Symbol Parameter Min Max Units Vpp Supply Voltage 0 3 6 V ViN Input Voltage 0 3 6 V TsrG Storage Temperature Range 65 150 C Recommended DC Operating Conditions Symbol Parameter Min Typ Max Units Vpp Supply Voltage 3 135 3 3 3 465 V Vin Input Logic High 3 3 V receivers 2 0 Vpp V Vin Input Logic High 5 0 V receivers 2 0 5 0 V Vit Input Logic Low 0 0 0 8 V Vou Output Logic High 2 4 Vpp V VoL Output Logic Low 0 0 0 4 V li 4 Input Leakage Current 1 10 uA Gites I
19. 0 128 4 56 7 8 9 101112131415 16171819 20 21 22 23 24 2526 2728 29303132 CLK100MHz FEF FEREEHETTH EFLELFELPETEPRTETEFEFETLEERETFETEEETETEEEFETE ET ERE SYS ADDR gt E d1 2 3 44 SYS TS SYS TA ES SYS DATA mum 11314H 561718 MUX MDATA mE 12 13 4 5 6171 8 MEM DATADH 7 DS MEM DATADL EEEEEEEEEEEEEEENESESN D Dd MEM STATUS activ Bust 4CASlat2 5 5 5 5 5 prec MADDR SDRAS SDCAS WE SDDQM SDCKE 600 4 3 P0 ee ee eee o 0d 0 0 103 ee ee BOX 34 dr dk cy xk 9 cm CRM PS qoo deco de 9 ue Bk ooh xr HE Sonde p 6 26 2000 Page 213 of 209 IBM Dual Bridge and Memory Controller Write Burst Page Miss from PowerPC CPU to SDRAM 0 1 2 3456 78 9 10 11 12 13 14 15 16 17 18 19 20 21 2223 24 25 26 27 28 29 30 31 32 CLK100MHz nf Me ELS
20. 0 25 Contains the real address used by the device at the end of the DMA transfer operation to which the completion status is written 26 31 Reserved assumed to be zero Page 136 of 209 6 26 2000 IBM Dual Bridge and Memory Controller DMA Transfer Translated Address XTAR Reset Value x 0000 0000 Address User x FF1C 00A0 Privileged x FF1E 00A0 Access Type Read Only User and Privileged Translated Address Y Y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 31 Translated Address Contains the 32 bit real address presented on the processor bus during the ecowx eciwx transfer 6 26 2000 Page 137 of 209 CPC710 133 IBM Dual Bridge and Memory Controller System Standard Configuration Registers Space The registers listed in this section can only be accessed from the PowerPC processor Access through the 60x bus directed to the specific PCI bridge permits the PCI configuration Both PCI bridges inside device must be configured before any PCI configuration cycles can be issued The primary purpose of these regis ters is to provide a mechanism for firmware to identify the PCI bridge and the DCR and DID registers and to assign a 1 MB address space in the system memory map for the location of the PCI bridge facilities BAR reg ister Device Characteristics Register DCR This register identifies the type of device present
21. Bit s Description Enable PCI Control Space 0 0 PCI Bridge only responds to configuration cycles 1 PCI Bridge responds to address space specified in the BAR register 1 3 Reserved 4 31 Reserved 6 26 2000 Page 141 of 209 CPC710 133 IBM Dual Bridge and Memory Controller Page 142 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Addressing Model Address Maps Device address spaces can be programmed using the PowerPC REference Platform specification PREP Mode Also a highly Flexible PCI Host Bridge FPHB Mode is available The address map is highly program mable in either mode The following restrictions must be observed when programming the device The upper 16 MB is reserved for ROM system configuration DMA controller etc See System Register Space x FF00 0000 to x FFFF FFFF on page 33 for the definition of this address space Only PCI Memory spaces are allowed to overlap this area however they are not forwarded to the PCI bus Atleast 1MB of system memory must be available at address 0 Minimum granularity of DIMMs is 16MB System memory cannot be located above 2GB Access in the upper 2GB is not checked by the CPC710 and result is unpredictable Avoid overlapping system memory extents with PCI extents Hang conditions and unpredictable results can occur if a processor accesses an address contained in two different extents Memory Map 4GB FFFF FFFF 2GB 7FFF FFFF 16 MB 6 2
22. Cache line not modified in CPU data fro Receive memory write m PCI bus v Stop SYS_ARTRY of CPU accesses memory and stop SYS_ARTRY of CPU accesses to this line Initiate write to system v Retry PCI cycle 6 26 2000 Page 191 of 209 IBM Dual Bridge and Memory Controller Configuration Cycles The device implements Configuration Mechanism 1 as specified in the PCI Local Bus Specification 2 This mechanism uses an indirect addressing model with the CONFIG ADDRESS and CONFIG DATA regis ters The configuration target address is first written into CONFIG ADDRESS and then an access is made to CONFIG DATA to generate a configuration transfer Each PCI bridge has a separate set of these registers When each decodes an access to its CONFIG DATA register it performs different operations depending on the values stored in CONFIG ADDRESS PCI Configuration Cycle Matrix CONFIG ADDRESS Register Fields Action Notes Enable Bus Device Function Register Configuration not enabled Returns 0 s on loads and ignores write data Invalid Bus in CONFIG_ADDR BUS lt BUSNO x x x Returns 1 s on loads and ignores store data 1 2 No access made to PCI Bus Access to PCI Bridge configuration space 0 9 x Read Write to PCI Bridge configuration registers 1 21 x Configuration access to device on PCI Bus TYPE 0 configuration cycle on PCI bus BUS BUSNO Not suppor
23. Contains the top address for the CPU to PCI IO access with potential deadlock 10 31 Reserved Potential Deadlock management The normal mode of burst transfer from a PCI Master to the Memory is 32 Bytes The setting of bit O permit to have Long Burst of up to 4KBytes with no Disconnect RETRY during the Burst Page 88 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Reset Addressed Interrupt Register IT ADD RESET This Virtual register exists only for PCI 64 bridge Only the CPU can write to this register and reset the IT1 output interrupt signal Address BAR 000F 8300 Access Type Write Only Reset addit Reserved vov Y 0123456 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description Reset addit 0 7 1 Writing a 1 in one of these 8 bits resets the interrupt signal INT1 0 No action 8 31 Reserved 6 26 2000 Page 89 of 209 CPC710 133 IBM Dual Bridge and Memory Controller Set PCI 64 Interrupt Register INT SET This register exits only for PCI 64 Interrupt can be set only by the CPU Address BAR 000F 8310 Access Type Write Only Set It Reserved 4 vov v 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description Set It Writing 1 by the CPU set the bit corresponding Writing O has no action 0 3 BitO INTA Bit1 INTB Bit2 INTC Bit3 INTD 4 31 Reserved Page 90 of 209 6 26 2000
24. Description Status Double word 0 0 63 Reserved Status Double word 1 0 63 Undefined Status Double word 2 0 63 Undefined Status Double word 3 0 31 32 39 40 41 42 43 44 45 46 47 48 49 50 51 63 x 0000 0000 Poll Status Cache Line Valid Flag x 00 Initial value set by software Indicates status cache line is not valid x FF Written by hardware to indicate that the status cache line has been updated and is valid Transfer Complete 0 Transfer is not complete 1 Transfer is complete TLBSYNC Detected 0 No TLBSYNC Detected 1 TLBSYNC detected during DMA transfer Transfer Reserved Page Crossing Error 1 Page Crossing detected during DMA transfer Second DMA Transfer Halt 1 DMA transfer operation in progress was halted due to start of second DMA transfer operation Unaligned ecowx eciwx Address 1 Address associated with ECOWX ECIWX is not word aligned Unaligned Transfer Error 1 Address alignment error Address Increment Alignment Error 1 Improper alignment of addresses when Address Increment bit is off Invalid PCI Address 1 XPAR did not match any PCI extents Reserved Transfer Length This field contains the number of bytes remaining when the transfer was completed or aborted Page 202 of 209 6 26 2000 IBM Dual Bridge and Memory Controller DMA Procedure The DMA transfer process begins when the 60x logic detects an ecowx or eciwx
25. Disable Queue Same Page Override 0 Memory queue ordering can be overridden if an operation is to the same page 1 Memory queue always processed in order received MCCR Register Settings Register Bits Configuration Te ii Ux o or A ON DAROrA co t 0 o N o o o O c wo eo T rrr e N NN A A NN WH NN MNM SDRAM 10 00 Off 10 1 0000 01100 00 00 with tac 8 cycles Note Values written in bold font are mandatory for the specified configuration 6 26 2000 Page 181 of 209 IBM Dual Bridge and Memory Controller MCER Register The Memory Configuration Extent Registers MCER 0 7 program the start address and size of each bank The following table shows the relationship between the DIMMs and the MCER registers MCER to Program Functions of DIMMs Bank Definition DIMMs equipped Corresponding MCER Note DIMMO Bank1 and DIMM1 Bank1 MCERO DIMMO Bank2 and DIMM1 Bank2 MCER1 DIMM2 Bank1 and DIMM3 Bank1 MCER2 DIMM2 Bank2 and DIMM3 Bank2 MCER3 DIMM4 Bank1 and DIMM5 Bank1 MCER4 1 DIMM4 Bank2 and DIMM5 Bank2 MCER5 1 DIMM6 Bank1 and DIMM7 Bank1 MCER6 1 DIMM6 Bank2 and DIMM7 Bank2 MCER7 1 1 When using SDRAM and Data Mask Mode is active see MCCR bit 11 and device can support only up to four bank MCER 4 7 must be off To configure contiguous address spaces with different bank sizes software must put the largest bank sizes at the lowest addresses and continue in order to the smallest bank sizes To set up the MCER regi
26. IBM Dual Bridge and Memory Controller M Y 0 1 2 9 4 8 6 T 8 9 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s PCI I O Address Space Size xFFF 1 MB xFFE 2 MB xFFC 4MB xFF8 8 MB x FFO 16 MB 0 14 x FEO 32 MB x FCO 64 MB x F80 128 MB x F00 256 MB x EO0 512 MB x C00 1 GB x 800 2GB x 000 4 GB 12 31 Reserved 6 26 2000 Page 75 of 209 CPC710 133 IBM Dual Bridge and Memory Controller System Base Address for PCI Memory SMBAR Reset Value x A000 0000 Address BAR x 000F 7F80 Access Type Read Write System Base Address Reserved y yy Y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description System Base Address This register contains the upper bits of the SYSTEM address that PCI Memory is mapped to 0 11 Per Note Address must be aligned on a boundary equal to the size specified in PCI Memory Size register 12 31 Reserved Note Address is decoded only if the Master Enable bit in the PCI Command Register is on Page 76 of 209 6 26 2000 System Base Address for PCI I O SIBAR IBM Dual Bridge and Memory Controller Reset Value x 8000 0000 Address BAR x 000F 7FCO Access Type Read Write PCI Base Address Reserved Y vov Y o 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s System Base Address 0 11 This register conta
27. Optional Buffers MADDR 1 12 2 cycles signals L N gt ADDR EVEN 0 12 MADDRO EVEN BSO BS1 gt Memory Interface 8x SDDQM 5 4x SDRAS 4x SDCAS 4x WE gt 8x SDCKE SDCS 0 7 MUX CLKENA1 MUX CLKENA2 TI ALVCH162268 Eus MUX_CLKEN1B MUX 4B 0 71 MUX CLKEN2B MDATA O 71 A1 MUX OEA 6X B MUX OEB i DL 0 71 MUX SEL DH 0 71 ADDR EVEN 0 12 DL 0 71 MADDR ODD 0 12 SDCS2 SDCS3 SDCSO SDCS1 zm E DIMM Bank B DIMM Bank B pes m LLI 2 Q DIMM Bank A DIMM Bank A T Z ol L DIMM 0 gt DIMM 1 SDCS6 SDCS7 SDCS4 SDCS5 DIMM Bank B DIMM Bank B e i tc ge i I ui gig DIMM Bank A DIMM Bank A ur J L 2 DIMM 2 gt DIMM 3 SDRAS SDCAS WE SDCKE BS0 BS1 SDDQM CLK Note The input clock for the SDRAM is the 60x bus clock which is not driven by the device Page 176 of 209 6 26 2000 Supported SDRAM Organizations The CPC710 is fully compatible with the JEDEC Standard It supports the addressing listed in the following table Supported DIMMs DIMM Size MByte 8M Single 16M Single 32M Single 64M Single 128M Single 256M Single 512M Single SDRAM Addressing bit Row Col Bank 11 8 1 11 9 1 11 9 1 11 8 2 12 8 1 11 10 1 11 10 1 12 9 1 12 8 2 13 8 1 12 9 2 12 9 2 13 8 2 13 9 1 12 10 2 12 10 2 13 10 1 13 9 2 13 10 2 13 11 2 SDRAM Mbits x I Os 1Mx16 2Mx8 2Mx32 2Mx32 2Mx8
28. w LI LI UU LI WwW WwW LL on N e t wo oOo N 922222299 S 3 9 3 3 8 38 PPEPRPEPPEE Ztadate extktaeed Reserved vvv t v1 7415 Y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description ARB Level 0 Enable 0 0 ARB level is ignored T ARB level is enabled 1 ARB Level 1 Enable ARB Level 2 Enable ARB Level 3 Enable ARB Level 4 Enable ARB Level 5 Enable ARB Level 6 Enable oc A OON ARB Level 7 Enable Not supported in 32 bit PCI bridge Co Reserved 6 26 2000 Page 73 of 209 CPC710 133 IBM Dual Bridge and Memory Controller PCI Memory Address Space Size MSIZE Reset Value Address Access Type x FFFO 0000 BAR x 000F 7F40 Read Write PCI Memory Address Space Size Reserved Additional Address Space Y Y Y Y Y vov Y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s 12 31 PCI Memory Address Space Size xFFF xFFE xFFC x FF8 x FFO xFEO xFCO x F80 x F00 x EO0 x C00 x 800 x 000 1 MB 2MB 4MB 8MB 16 MB 32 MB 64 MB 128 MB 256 MB 512 MB 1GB 2GB 4GB Reserved Page 74 of 209 Description 6 26 2000 PCI I O Address Space Size IOSIZE Reset Value Address Access Type PCI I O Address Space Size x FFFO 0000 BAR x 000F 7F60 Read Write
29. 1 PCI Bridge has detected a target abort for one of its transactions Signaled Target Abort Slave 11 0 No Error 1 PCI Bridge as a slave has issued a target abort 10 9 DevSel Timing Read Only 01 PCI Bridge responds with Medium timing on P G_DEVSEL signal Data Parity Detected 0 No Error 8 T This bit is set if the following 3 conditions are met I PCI Bridge asserted or observed P G_PERR signal on PCI bus Il PCI Bridge acting as master IIl Bit 6 of Command Register set Page 44 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Bit s Description Target Fast Back to back Capable Read Only 7 Always returns a 1 to indicate that the PCI Bridge as a target will accept fast back to back transfers when the transfers are not to the same device 6 0 Reserved 6 26 2000 Page 45 of 209 CPC710 133 IBM Dual Bridge and Memory Controller Revision ID RID Reset Value x 00 Address x 08 Access Type Read Only Revision ID 4 v 765432 10 Bit s Description 7 0 Provides an extension to the PCI Device ID register Device always responds with x 00 for reads from this register Programming Interface SPI Reset Value x 00 Address x 09 Access Type Read Only Programming Interface Y Y 76543 2 1 0 Bit s Description 7 0 Defines a specific register level programming interface Device always responds with x 00 for reads from this register Page 46 of 209 6 26 2000
30. 161 Address Retry SYS ARTHRY iiicucciiiceeceeaccceece sce cccca sace cccua sicco cEcea pde c cU paa ccde cr paa ide cr DaRinds 161 Precharging SYS_ARTRY and SYS SHD eese nennen 161 CPC710SYS ARTRY ASSertions edet teret ree dece co Peer i aa ici s dingy dias acts cav ree dvd RE aadi 161 Recommended SYS ARTRY Procedure ccccccccccccesceseseeeseseseeeeeeeeeseeeeeeesesaeaeaeaeaeasaeeaeseeeeeeeees 161 Locking Signal DLK oso nase Foca eerie E A 162 BOX rXesninmiuiEEeEc cc v 163 Error Handling for CPU Initiated Transactions eese nnns 164 GHECKSIOD EMOS sareari iana RR 164 Memory Controlle uioiisipaidas idea ex unb DNA EHE aneneen aaaeeeaa UM URN AC OUI LIMEN NERO NUMEN AME 169 I4 p M 169 Bank Definitions Mee 171 SDRAM sr cg D 171 DIMM BAI KS e LE 172 Interleaved Banks 173 Memory Signal Connections cccccssssececeseeeeceeeeseeeeeeeesnneeeeeensecaeeeeesseaeeeseeseeeeesesseeeeeseeseeeeeeenseeeeeeees 174 SDRAM Subsystem Overview Aen 176 Supported SDRAM Organizations 4 eeseeeeseeeee senes enne nnn nennen nnn sanie nnns sn in nnns ins nnmnnn inan 177 SDRAM Buffering Requirements sssini isnan Enin AN aE NAE nnne nnn
31. AE07 AE08 AE09 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 Signal SYS DATA62 Vpop SYS_DATA56 SYS_DATA7 SYS_DATA52 Vpp SYS DATA44 SYS ADDR5 SYS ADDR7 Vpop SYS_ADDR12 SYS_ADDR14 Ground Vpp Ground Vpp No Connect SYS MACHK1 SYS_DATA21 SYS_DATA22 SYS_DATA14 SYS_DATA13 SYS_DATA30 SYS_DATA31 SYS_DATA32 SYS BR G INTA SYS BRO SYS DATA43 SYS DATA55 SYS_DATA50 SYS_DATA45 SYS_ADDR4 SYS_ADDR6 SYS_ADDR8 SYS_ADDR11 No Connect Vpp Ground Page 17 of 209 IBM Dual Bridge and Memory Controller Signal Pins Sorted by Signal Name Page 1 of 4 Signal Pin Signal Pin Signal Pin Signal Pin BSO OR10 G_ADH20 0J19 G ADL27 0D17 G_REQ2 AC21 BS1 OP10 G_ADH21 0H19 G ADL28 0H14 G_REQ3 0G12 CE TRST 0T14 G ADH22 0F23 G ADL29 0C20 G REQ4 0C09 CEO IO OF16 G_ADH23 0D25 G_ADL30 0D16 G REQ5 0K12 CEO TEST 0MO2 G ADH24 0D23 G ADL31 0A15 G REQ6 0H20 CE1 A OKO6 G ADH25 0C24 G ARB 0DO6 G REQ7 0T23 CE1 B 0MO8 G ADH26 OF20 G CBEO 0B19 G REQ64 OF08 CE1 C1 0K02 G_ADH27 OE19 G_CBE1 0A19 G RESETOUT 0V21 CE1 C2 OM06 G ADH28 0D22 G CBE2 0D19 G RST 0A11 CHKSTOP OF10 G ADH29 OF22 G_CBE3 0A18 G SERR 0J14 DH OTO4 G_ADH30 0B23 G CBE4 0C16 G STOP 0A14 DI2 OTO6 G_ADH31 0C22 G CBE5 0C21 G TRDY 0C14 DLK ACO2 G ADLO 0G17 G CBE6 0A17 Ground 0A25 RESERVED4 OR13 G ADL1 0H18 G CBE7 0A16 Ground 0B02 RESERVED5 0L13 G A
32. B c x amp oO o c z E E E p S E 2 o 2 7 x 2 o o o S S a S S a S 5 3 5 o 3 5 o 3 3 o z X z X z E gt y gt S gt x S E x S a x S E o N no e N on e N nO E D m 9 E D m 9 E D m E gt E 2 m e l l l l L5 l l l D 99 99 n g 99 99 a g 99 99 99 9 gt gt gt o gt gt gt o gt gt gt 7 7 N c N 7 no N 7 N yy Vide v4 y Y 4 vs Y 0 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 1718 19 20 21 22 23 24 25 26 2728 29 30 31 Bit s Description 0 4 SYS TT 0 4 Values for flush operation 5 7 SYS TSIZ 0 2 Values for flush operation 8 SYS TBST Value for flush operation 9 Reserved 10 14 SYS_TT 0 4 Values for kill operation 15 17 SYS TSIZ 0 2 Values for kill operation 18 SYS TBST Value for kill operation 19 Reserved 20 24 SYS_TT 0 4 Values for clean operation 25 27 SYS TSIZ 0 2 Values for clean operation 28 SYS TBST Value for clean operation 29 31 Reserved Page 118 of 209 6 26 2000 IBM Dual Bridge and Memory Controller programming the ATAS Address Transfer Attribute for Snoop Register register When the CPC710 100 generates the following snoop cycle with TT signal on the 60x bus the PowerPC 750 takes no action At the difference with the PowerPC604 the PowerPC 750 does not handle cache sys tem memory coherency TT 0 4 OperationAnswer from the 750 TT 0 4 Operation Answer from the 750 00000 Clean Sector No action 00100 Flush Sector No action
33. However Address Data 1 0 contains 01 to indicate a TYPE 1 configuration cycle 6 26 2000 Page 193 of 209 IBM Dual Bridge and Memory Controller PCI Performance Estimates PCI to Memory Sustained Throughput Read 96 PCI 64bit 66 MHz 18 1 1 1 PARL 53 PCI 32bit 33 MHz 12 1 1 1 1 1 1 1 PRAL Assumptions 4KBytes Burst PCI Master parked on PCI bus No other activity present Adapter supports fast back back transfers for stores to memory NoL1 or L2 cache hits PARL PCI Rearbitration Access Latency min 1 cycle CPU to PCI Sustained Throughput Loads 100 MHz Bus Operation PCI 32bit PCI 64bit 33 MHz 66 MHz Burst 32 bytes 71 194 Single 8 bytes 30 67 Single 4 bytes 17 33 Assumptions CPU is parked on 60x bus 1 Level Pipeline IBM25CPC710AB3A100 parked on PCI bus No other activity present Page 194 of 209 Write 132 12 1 1 1 PARL 58 Stores 100 MHz Bus PCI 32bit PCI 64bit 33 MHz 66 MHz 71 194 30 67 17 33 Units MByte sec 66MHz PCI Cycles MByte sec 33MHz PCI Cycles Units MB s MB s MB s 6 26 2000 PCI Master Error Handling IBM Dual Bridge and Memory Controller For PCI bus errors detected on CPU initiated transfers referto Error Handling for CPU Initiated Transactions on page 164 The following table describes the error handling performed for PCI master errors PCI Master Error Handling Page 1 of 2 Operation Error Mode En
34. IBM Dual Bridge and Memory Controller CONFIG ADDRESS Register CFGA This Little Endian register along with the CONFIG DATA register provides software with a means to config ure the PCI bus Device implements Configuration Mechanism 1 as specified in the PCI Local Bus Specifi cation See heading Configuration Cycles on page 192 for additional details Reset Value x 0000 0000 Address BAR x 000F 8000 Access Type Read Write o a S 5 5 wi B 2 g c E E B 9 E 3 3 o 5 z z e E z 5 5 2 E 8 2 S 5 3 z 4 8 Reserved Bus Number iE z Lv vv vx vov vov vy y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit s Description Configuration Enable 31 0 Disabled E Enabled accesses to the CONFIG_DATA register result in device executing a configuration access to itself or to the PCI bus 30 24 Reserved 23 16 Bus Number Specifies which PCI bus is being configured Device checks this field to determine the appropriate config uration action 15 11 Device Number Selects a particular device to be configured on a bus 10 8 Function Number For devices that implement more than one function this field specifies which function to configure within a device 7 2 Register Number Specifies which register out of the 256 byte PCI Configuration header to access 1 0 Always b 00 Page 80 of 209 6 26 2000 IBM Dual Bridge and Memory Controller CONFI
35. MADDR6 VDD PLL_LOCK G GNT2 PRES OEO VDD G_ADL23 Page 14 of 209 Pin 0B15 0B16 0B17 0B18 0B19 0B20 0B21 0B22 0B23 0B24 0B25 0C01 0C02 0C03 0C04 0C05 0C06 0C07 0C08 0C09 0C10 0C11 0C12 0C13 0C14 0C15 0C16 0C17 0C18 0C19 0C20 0C21 0C22 0C23 0C24 0C25 0D01 0D02 0D03 Signal G ADL25 TESTIN Vpop G_ADH11 G CBEO G ADH10 VDD G_ADL16 G_ADH30 Ground Vpp No Connect SDCKE3 Ground MADDR11 SYS HRESETO PRES OFE1 Ground FLASH OE G REQ4 MADDR5 Ground G_FRAME G_INTC G_TRDY Ground G_CBE4 G_ADL19 G_ADL18 Ground G_ADL29 G_CBE5 G_ADH31 Ground G_ADH25 No Connect MDATA47 MDATA65 MDATA66 Pin 0D04 0D05 0D06 0D07 0D08 0D09 0D10 0D11 0D12 0D13 0D14 0D15 0D16 0D17 0D18 0D19 0D20 0D21 0D22 0D23 0D24 0D25 0E01 0E02 0E03 0E04 0E05 0E06 0E07 0E08 0E09 0E10 0E11 0E12 0E13 0E14 0E15 0E16 0E17 Signal MUX_CLKENA2 MDATA67 G_ARB MADDR3 MUX_SEL MUX OEA SCAN GATE G_REQ1 G_GNT3 Ground PCG_CLK G_ADL26 G_ADL30 G_ADL27 G_ADHO G_CBE2 P_ADL20 G_ADH16 G_ADH28 G_ADH24 G_ADL15 G_ADH23 MDATA48 VoD MDATA37 SDCKE1 VoD SDCKE6 WE3 MADDR2 VDD MADDR4 MUX_CLKENA1 G DEVSEL G_GNT1 G_ADL22 G_ADH5 G_ADH4 Vpp Pin 0E18 0E19 0E20 0E21 0E22 0E23 0E24 0E25 OF01 OF02 OF03 OF04 OF05 OFO6 OFO7 OF08 OFO9 OF10 OF11 OF12 OF13 OF14 OF15 OF16 OF17 OF18 OF19 OF20 OF21 0F22 0F23 0F24 0F25 0G01 0G02 0G03 0G04 0G05 0G06 Signal G
36. MDATA68 MDATA69 MDATA70 MDATA71 MUX CLKEN1B IBM Dual Bridge and Memory Controller Pin 0Y03 ORO6 0H03 0E03 ONO9 0K05 OLO5 0H02 0H01 0G01 0K08 0G06 0H07 0DO1 0E01 OF02 OF01 0K07 0G02 0K03 0J03 0H04 0J06 0J01 0K01 OLO9 0H05 OF05 0K09 0J08 0H08 0D02 0D03 0D05 0H09 0G08 OFO7 0H10 0A05 Signal Pin MUX CLKEN2B 0A08 MUX_CLKENAT 0E11 MUX_CLKENA2 0D04 MUX OEA 0D09 MUX OEB 0A09 MUX SEL 0D08 No Connect 0A03 No Connect 0C01 No Connect 0C25 No Connect ACO1 No Connect AC25 No Connect AE03 No Connect AE23 No Connect 0A23 NODLK ABOS O GPIOO 0U13 O_GPIO1 0U12 O GPIO2 0Y08 P ADLO 0T24 P ADL1 0P20 P ADL2 0P22 P ADLS 0R22 P ADL4 O0R20 P ADL5 0Y23 P ADL6 0P24 P ADL7 OR24 P_ADL8 ON18 P ADL9 0U22 P_ADL10 ON19 P ADL11 ON25 P_ADL12 0L24 P ADL13 0L22 P ADL14 0M24 P ADL15 0M22 P ADL16 0M19 P ADL17 0L25 P ADL18 0K25 P ADL19 0L17 P ADL20 0D20 Page 19 of 209 IBM Dual Bridge and Memory Controller Signal Pins Sorted by Signal Name Page 3 of 4 Signal P ADL21 P ADL22 P ADL23 P ADL24 P ADL25 P ADL26 P ADL27 P ADL28 P ADL29 P ADL30 P ADL31 P CBEO P CBE1 P CBE2 P CBES3 P CFGO P CFG1 P CFG2 P DEVSEL P FRAME P ISA MASTER P LOCK P MEMACK P MEMREQ P PAR Page 20 of 209 Pin 0J20 0K24 0K23 0K18 0M17 ON17 0L18 0M18 0L20 0L21 ON23 0P18 0U25 0T25 0R17 0M15 ON15 OP15 0V20 0Y18 0T19 0T21 OR21 OT17 0T18 0U18 0K04 AB20 0P25 OR18 0T22 0T20 OR25
37. Max ns Min Max 2 1 6 9 6 6 0 3 3 1 4 7 4 7 PCI 64bit 66Mhz Spec Min Max 2 6 2 6 0 3 5 5 1 5 6 26 2000 IBM Dual Bridge and Memory Controller SDRAM Interface Timing Specification SDRAM Input Timings IBM25CPC710AB3B100 Signal Input Setup Input Hold Input Setup Input Hold 9 min ns min ns min ns min ns MDATA 0 71 3 0 0 1 SDRAM Output Timings IBM25CPC710AB3B100 Output Valid from Output Hold from Output Valid from Output Hold from SYS_CLK SYS_CLK SYS_CLK SYS_CLK Signal Max Load Min Load Max Load Min Load ns pf ns pf ns pf ns pf SYS_ADDR 0 31 6 9 30 pf 6 9 30 pf SYS DATA 0 63 7 5 30 pf 7 5 30 pf DATAP 0 7 6 5 30pf 6 5 30pf SYS ARTRY SYS SHD SYS AACK SYS BG 0 1 DBG 0 1 SYS TA SYS TEA 6 9 30 pf 6 9 30 pf CHKSTOP SYS GBL SYS HRESET 0 1 SYS MACHK 0 1 SRESET 0 1 SYS TBE SYS TBST SYS TSIZ 0 2 SYS TT 0 4 7 4 30 pf 7 4 30 pf 6 26 2000 Page 225 of 209 IBM Dual Bridge and Memory Controller FLASH Interface Timing Specification FLASH Output Timings IBM25CPC710AB3B100 Output Valid from Output Hold from Output Valid from Output Hold from SYS CLK SYS CLK SYS CLK SYS CLK Signal Max Load Min Load Max Load Min Load ns pf ns pf ns pf ns pf SYS ADDR 0 31 6 9 30 pf 6 9 30 pf SYS DATA 0 63 7 5 30 pf 7 5 30 pf DATAP 0 7 6 5 30pf 6 5 30pf SYS_ARTRY SYS_SHD SYS_AACK SYS BG 0 1 DBG 0 1 SYS TA SYS TEA 6 9 3
38. Set error address in SEAR register If PGCHP 26 0 Loads Signal Machine Check with 1 SYS_TEA Stores Signal Machine Check with SYS MACHK If PGCHP 26 1 Signal Machine Check with SYS MACHK Terminate CPU transaction normally Set data parity error bit 15 in PCI Status register Proceed normally with PCI transaction Proceed normally with CPU transaction Set received target abort bit in PCI Status register Set PCI error bit in SESR Set error address in SEAR register If PGCHP 26 0 Loads Signal Machine Check with SYS TEA Stores Signal Machine Check with SYS MACHK If PG CHP 26 1 Signal Machine Check with SYS MACHK Terminate CPU transaction normally 6 26 2000 IBM Dual Bridge and Memory Controller Error Handling for CPU Initiated Transactions Page 4 of 4 Operation Error PCI Bus timeout P G TRDY count expired Access to PCI bus cont d Retry count expired 1 A dummy 0 is returned for read operation For write data is ignored 6 26 2000 Mode Enabled Enabled Action Notes Master abort the PCI transaction Set master aborted bit 13 PCI Status register Set PCI bus time out error in PLSSR register Set PCI error bit in SESR Set error address in SEAR register If PGCHP 26 0 Loads Signal Machine Check with SYS TEA Stores Signal Machine Check with SYS MACHK If PGCHP 26 1 Signal Machine Check with SYS MACHK Terminate CPU transaction normally Stop retrying PCI transfer
39. Signal Pins Sorted by Signal Name cccceseeeeceseseeeeeeeeeseeeeeeeeseneeeeseesneeeseeeseneeseseesneeseesessneeseeeesnenes 18 VO Signals eee em ie aha re C C CN 23 Signal Descriptions a 24 ii 1010 mr e 33 Standard PCI Configuration Space register number x 00 to x 68 ssssssssssssussss 33 Specific PCI Host Bridges Space BAR x 000F 6110 to BAR x 000F 9810 ssss 33 System Register Space x FF00 0000 to x FFFF FFFF sseeeeeeneeeenn nnnm 33 Register Map 34 Standard PCI Configuration Register List cccessseccceseeeeeeeeseeeeeeeeeeeene eene nennt nennen 35 Specific PCI Host Bridge registers e lesse ence ee eeeeneeseeeeseneeseseesneeseesesneeeseeeeseeeeesenes 36 System Registers List ueecciiiiccceesice Aaa i 37 Standard PCI Configuration Registers eese eee eeneeee nennen nnne nn nnmnnn nnmnnn nnen nnn 39 MfeaBEau nc 41 Bru Memipjzuipy C 41 x eller iitepyme ES 42 PCI Status S TAT NEC M 44 Rovicion ID RID pem 46 Programming Interface SPI 5 ccrte cte sachet nont RE nS cree ko Rana E REN Sla gU RRR n IRE RR M bese RE 46 Sub Class Gode SU BO uteri roe e eter teer tede Dated
40. System Registers List Page 2 of 2 Address Name x FF00 1410 x FF00 1420 SIOR1 X FF00 1424 to x FF00 1FFF x FF00 2000 to x FF17 FFFF DMA Registers User Privilege X FF18 0000 to x FF1C 001F x FF1C 0020 GSCR x FF1C 0030 GSSR x FF1C 0040 XSCR x FF1C 0050 XSSR x FF1C 0070 XPAR x FF1C 0090 XWAR x FF1C 00A0 XTAR x FF1E 0020 GSCR x FF1E 0030 GSSR x FF1E 0040 XSCR x FF1E 0050 XSSR x FF1E 0070 XPAR x FF1E 0090 XWAR x FF1E 00A0 XTAR x FF1E 00A4 to xFF1F FFFF System Standard Configuration Registers x FF20 0000 DCR x FF20 0004 DID x FF20 0008 to x FF20 0014 Reserved x FF20 0018 BAR x FF20 0020 to x FF20 OFFF Reserved Device Specific Configuration Space x FF20 1000 PCIENB X FF20 1004 to x FFDF FFFF BOOT ROM x FFEO 0000 to x FFFF FFFF IPLROM Page 38 of 209 Use Reserved SIO Register 1 Planar DIMM CPU etc Reserved Reserved Reserved Global Control Register user Global Status Register user Transfer Control Register user Transfer Status Register user Transfer PCI Address Register user Transfer Write Back Address Register user Transfer Translated Address Register user Global Control Register priv Global Status Register priv Transfer Control Register priv Transfer Status Register priv Transfer PCI Address Register priv Transfer Write Back Address Register priv Transfer Translated Addre
41. TESTOUT 0G25 G ADL11 0J14 G SERR O0LO3 Ground 0M17 P ADL25 0HO1 MDATA42 0J15 G_ADH3 0LO4 SDCS12 0M18 P ADL28 0HO2 MDATA41 0416 G ADH7 OLO5 MDATA40 OM19 P ADL16 0HO3 MDATA36 0J17 Vpp oLo6 SDCS13 0M20 TMS 0HO4 MDATA55 0J18 G ADL2 0LO7 Ground 0M21 P REQ5 0HO5 MDATA60 0J19 G ADH20 0LOB SDCS15 OM22 P ADL15 0HO6 SDCS7 0J20 P_ADL21 OLO9 MDATA59 0M23 P REG4 0H07 MDATA46 0J21 Vpp 0L10 SDCKE4 OM24 P ADL14 0HO8 MDATA64 0J22 XCVR RD 0L11 Ground 0M25 P REQ3 0HO9 MDATA68 0J23 P RST 0L12 RESERVED3 ONO1 SDCS2 0H10 MDATA71 0J24 Vpp 0L13 RESERVED5 ONO2 Vpp 0H11 G CFGO 0J25 G_ADL7 0L14 Ground ONO3 SDCS5 0H12 G_CFG1 0K01 MDATA58 OL15 Ground ONO4 Ground 0H13 G ADL24 0K02 CE1 C1 0L16 G ADL10 0NO5 SDCS3 0H14 G ADL28 0K03 MDATA53 0L17 P ADL19 ONO6 Vpp 0H15 G_ADH1 0K04 P GNT6 OL18 P ADL27 ONO7 MDATA10 0H16 G ADH9 0K05 MDATA39 0L19 Ground ONO8 MDATA9 0H17 G ADH15 0K06 CE1 A OL20 P ADL29 ONO9 MDATA38 0H18 G ADL1 0K07 MDATAS51 OL21 P_ADL30 ON10 Vpp 0H19 G ADH 1 OKO8 MDATA44 0L22 P ADL13 ON11 SDRAS2 0H20 G REQ6 0K09 MDATA62 0L23 Ground 0N12 SYS CONFIGO 6 26 2000 Page 15 of 209 IBM Dual Bridge and Memory Controller Signal Pins Sorted by Pin Number Page 3 of 4 Pin Signal Pin Signal Pin Signal Pin Signal 0N13 Ground ORO2 MDATA11 OT16 PLL TUNE1 0VO5 MDATA28 0N14 SYS CONFIG1 ORO3 Groun
42. for PD definition and the device s supported values Flash Interface Boot Rom The Device s Boot ROM base address is fixed at x FFFO 0000 Accesses to the architected Boot ROM space within the size limit defined in the System I O Control Register System I O Control SIOC on page 103 are decoded as valid Boot ROM accesses If the ROM Size parameter is larger than the actual amount of installed Boot ROM the data will wrap An access within the architected Boot ROM space but outside the size limit SIOC x FF00 1020 results in a bus timeout Machine Check error The Boot ROM interface logic satis fies burst read requests from the processor by concatenating multiple bytes from the Boot ROM The device is designed to interface with 512 K 1 Mb 2Mb x8 3 3 V Flash memory with 80 to 120 ns access time The following figure shows Boot Flash with the bits used for Address and Data on the PCI 32 bus AD lines PCI AD bits 20 0 are used for Flash Address LSB starts at bit 0 Bits 15 8 of the PCI 32 bus AD lines are used for the 8 bit data The Boot Flash is accessed under control of the device s PCI 32 controller to generate non PCI cycles with FRAME not asserted Flash is read and written by setting bit 4 R W in the UCTL Register During the Flash access the PCI bus is clocked by the System Clock The address on the PCI bus is defined from 0 Lsb to 28 Msb 6 26 2000 Page 197 of 209 IBM Dual Bridge and Memory Controller Connection o
43. 0 will be forced to all zeros For reads byte 0 will contain the byte stored in the ECC byte not the data at byte 0 ECC checking is not enabled for reads in this mode This mode also allows firmware write single bit and multi bit errors into memory to allow for ECC logic testing 00 Normal generation and checking of ECC codes The device will generate the normal ECC code when writing to memory and check ECC when reading 01 ECC check disabled Byte lane 0 routed to from ECC check field Data byte 0 forced to all zeros This mode is provided to allow software direct read write access to the ECC byte that is associated with every dou bleword of data stored in memory and also provide a mechanism to verify the memory controller s ECC generation and checking logic In this mode byte lane 0 data MSB of a double word is written to the ECC byte instead of the normal ECC code byte Data byte 0 will be forced to all zeros For reads byte 0 will contain the byte stored in the ECC byte not the data at byte 0 ECC checking is not enabled for reads in this mode This mode also allows firm ware write single bit and multi bit errors into memory to allow for ECC logic testing The device will still generate normal ECC codes when writing to memory 10 ECC check disabled Normal routing of data and normal ECC code generation The device will still generate normal ECC codes when writing to memory 11 Reserved Row Cycle Time for SDRAM Auto refresh tpc Al
44. 10 1 1 1 400 MB s 5 1 1 1 6 26 2000 IBM Dual Bridge and Memory Controller Bank Definitions The word Bank covers a couple of different meanings depending on the point of view 1 SDRAM Banks 2 DIMM Banks 3 Interleaved Banks SDRAM Banks As shown in the following diagram SDRAMs contain memory arranged in two or four banks The Memory Controller selects these banks using Bank Select BS address pins SDRAM Bank Configuration KS N NS S NL BANK 0 N BANK 0 BANK 1 N A NL N N amp lp i o C NL BANK 1 N BS 1 BANK2 BANK3 BEBO A BS 0 gt N SDRAM with two banks SDRAM with 4 banks 6 26 2000 Page 171 of 209 IBM Dual Bridge and Memory Controller DIMM Banks As shown in the following diagram DIMMs are available in single bank and dual bank configurations DIMM Bank Configuration Single Bank DIMM Dual Bank DIMM Nothing on this side SDRAM Chip DIMM DIMM These 5 chips constitute DIMM Bank A These 5 chips constitute DIMM Bank B These 5 chips constitute DIMM Bank A Bank Representation DIMM Bank B DIMM Bank A DIMM Bank A Schematic Representation Schematic Representation Page 172 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Interleaved Banks An Interleaved Bank consists of two interleaved DIMM Banks The two DIMM Banks are called Odd and Even
45. 10 of the ABCNTL Register 60x Arbiter Control Register ABCNTL Page 104 The logic units are system memory PCI 32 bus bridge PCI 64 bus bridge system I O logic and DMA con troller logic EIEIO operations are valid for transfers to and from the same logic unit but execution order of load and store operations to different logic units cannot be guaranteed For example a store to the PCI 32 bus bridge followed by a PCI 64 store could be presented to the respective PCI buses in reverse order if a bus is busy To preserve the order among logic units software must issue a SYNC instead of an EIEIO Address Retry SYS ARTRY Precharging SYS_ARTRY and SYS SHD The IBM25CPC710AB3A100 device always precharges SYS ARTRY and SYS SHD All other devices on the 60x bus must disable their precharges of these signals The device negates SYS ARTRY and SYS SHD for a half bus cycle during the second cycle following the SYS ARTRY window s last cycle CPC710SYS ARTRY Assertions The device asserts SYS ARTRY for SYNC operations as described in the previous section EIEIO operations as described in the previous section XFERDATA when more than two transfers have been initiated a processor access to the PCI bus when a PCI ISA bus bridge requests the same PCI bus processor access to system memory when a DMA occurs to the same cache line processor access to system memory when a DMA operation occurs to the same line processor access into
46. 2 512 512 x 002 x 002 512 1 1024 Not equipped x 000 Off 1024 2 1024 1024 x 000 x 000 a DIMM size is the size in MB of one DIMM including Bank A and Bank B if dual bank DIMM 2 Number of banks per DIMM One for single bank DIMM i e DIMM equipped with Bank A only two for dual bank DIMM i e DIMM equipped with Bank A and Bank B 3 x in MCER x 0 2 4 or 6 4 a setting of off indicates that the bank must be disabled by setting MCER x Bit 0 0 6 26 2000 Page 183 of 209 IBM Dual Bridge and Memory Controller Error Handling The memory controller detects four errors 1 Single bit ECC 2 Multi bit ECC 3 Invalid address 4 Overlapping memory extents Errors 2 3 and 4 are considered hard errors If one occurs it is logged into MESR and MEAR and cannot be overwritten with a subsequent hard error Single bit ECC errors are considered soft and once logged into the MEAR and MESR can be overwritten with a subsequent hard error Single Bit ECC Error General Case The hardware procedure for this error is 1 Set the single bit error bit in the MESR register 2 If neither a double bit error nor an address error is present store the syndrome in the MESR and the address in MEAR 3 Corrected data is not written back to memory but forwarded to the requesting logic 4 When Chip Programmability Register PGCHP bit 17 1 a Machine Check is performed to signal the processor that it could rewrite
47. 2000 IBM Dual Bridge and Memory Controller Bus Enhancements DBB not Required by Masters Masters do not require DBB The arbiter does not grant the data bus to a requesting master if the bus is cur rently in use The device does not drive DBB since it acts as an address only bus master Half Cycle Precharge not Required on SYS TA The device can be programmed so the precharge of SYS TA is not required This requires all slaves to ini tially drive SYS TA active or inactive immediately following a data bus grant At the end of a data bus tenure a slave does not perform a precharge which requires a slave in the next data bus tenure to drive SYS TA in the first cycle of the tenure The ABCNTL 13 mode bit 60x Arbiter Control Register ABCNTL Page 104 forces the device to do a precharge if a slave on the 60x bus does not support this function Half Cycle Precharge not Required on SYS TEA The arbiter does not grant the data bus for two bus cycles following assertion of SYS TEAs This allows a slave to perform a full cycle precharge on SYS TEAs SYS ARTRY PREV in QDBG Equation Eliminated When SYS ARTRY is asserted the arbiter negates all bus grants in the cycle following SYS ARTRY This supplants the requirement for masters to qualify associated bus grants by asserting SYS ARTRY in a previ ous cycle 6 26 2000 Page 157 of 209 IBM Dual Bridge and Memory Controller 60x Bus Transfer Types and Sizes The following tables de
48. 6 5 4 3 2 1 O0 Bit s Description 31 24 System Base Address for PCI 64 Contains the upper bits of the System Base address that memory is mapped to 23 1 Reserved Enable Memory or IO Space copy of the bit 7 of the PSSIZE Register 0 0 Memory Space 1 IO Space Page 52 of 209 6 26 2000 Interrupt Line INTLN Reset Value x 00 Address x 3c Access Type Read Only Interrupt Line v Y 7 6 5 4 3 2 1 0 IBM Dual Bridge and Memory Controller Bit s Description Indicates interrupt routing information for devices that implement an interrupt The PCI bridge logic does not generate 7 0 interrupts and therefore this register is not implemented Device responds with x 00 to reads from this register and ignores Writes 6 26 2000 Page 53 of 209 CPC710 133 IBM Dual Bridge and Memory Controller Interrupt Pin INTPIN Reset Value x 00 Address x 3aD Access Type Read Only Interrupt Pin t Y T 8 8 4 39 2 0 Bit s Description Specifies which particular interrupt pin INTA INTB INTC or INTD is used to generate interrupts Since the PCI bridge Fog does not generate any interrupts Device responds with x 00 to reads from this register and ignores writes Page 54 of 209 6 26 2000 Minimum Grant MINGNT Reset Value x 00 Address x 3E Access Type Read Only Minimum Grant v Y 7654838 2 1 0 Bit s 59 responds with x 00 6 26 2000
49. DBGO SYS DBG1 SYS GBL SYS HRESETO SYS_HRESET1 SYS_L2_HIT SYS MACHKO SYS MACHK1 SYS SHD SYS SRESETO SYS_SRESET1 SYS_TA SYS_TBE SYS_TBST SYS_TEA SYS_TS SYS_TSIZO SYS TSIZ1 SYS TSIZ2 SYS TTO SYS_TT1 SYS_TT2 Pin AE16 AD14 AA13 AA15 AC13 0V13 0W13 AD12 AD11 0V10 0WO08 0V09 0WO09 AD04 AD03 AC04 ABO5 0WO06 owo1 AB21 0C05 0P07 AC12 0Y04 AE04 ACO5 0Y16 0Y10 AC14 0Y14 AB02 ABO6 AA14 AAO01 0WO05 ABO1 AA06 AB04 0Y06 Signal SYS TT3 SYS TT4 TCK TDI TDO TESTIN TESTOUT TMS TRST DD DD L L lt lt lt S lt x lt x lt lt lt lt lt lt lt lt lt lt lt x lt lt lt lt lt lt lt lt IBM Dual Bridge and Memory Controller Pin 0V08 AA04 0P06 0P04 0Y12 0B16 0M16 0M20 O0P08 0B01 0B05 0B09 0B17 0B21 0B25 0E02 0E05 0M14 AE02 0M12 ONO2 ONO6 ON10 ON16 ON20 ON24 0P12 0P14 OP16 OP17 0R12 0T13 0U02 0U05 0U09 0U14 0U17 0U21 0U24 Signal o U DD DD e xxx xx x lt x lt lt xxx x mx xx xxx xx xxx I xm lt lt DD VDDA WEO WE1 WE2 WE3 XADR_LAT XCVR_RD Pin 0Y13 AA02 AA03 AA05 AA09 AA17 AA21 AA24 ADO1 ADO5 ADO9 AD13 AD17 AD21 AD25 AE24 0A02 0A24 0B13 0E09 0E17 0E21 0E24 0F13 0J02 0J05 0J09 0J17 0J21 0J24 0K13 0K14 0K22 0G09 0B04 0A04 0E07 0G22 0J22 Page 21 of 209 IBM Dual Bridge and Memory Controller Page 22 of 209 6 2
50. DMA transfer Page 130 of 209 6 26 2000 IBM Dual Bridge and Memory Controller DMA Global Status GSSR Reset Value x 0000 0000 Address User x FF1C 0030 Privileged x FF1E 0030 Access Type User Read Only Privileged Read Only ud o a lt E c S lt 2 Reserved 14 Y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description DMA Transfer Aborted 0 0 No Error i DMA transfer aborted 1 31 Reserved 6 26 2000 Page 131 of 209 CPC710 133 IBM Dual Bridge and Memory Controller DMA Transfer Control XSCR Reset Value x 0000 0000 Address User x FF1C 0040 Privileged x FF1E 0040 Access Type Read Write User and Privileged T s o bL o E 9 2 o O o L 2 o 9 g Reserved Transfer Length Reserved o6 23 Reserved amp yY 4 ov vov Ws eee vov ov 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 2 Reserved Transfer Length 252 Contains the number of Bytes to be transferred in a Loop maximum is 4 K A value of 0 will transfer O bytes 16 20 Reserved Global Transfer 21 0 No snoop operations required for accesses to system memory T Accesses to system must be coherent 22 Reserved Address Increment 23 0 Do NOT increment I O address during DMA transfer 1 Increment I O address during DMA transfer 24 2
51. DMA transfer operation is underway 26 Transfer Halted 1 DMA transfer operation in progress was halted due to start of second DMA transfer operation 6 26 2000 Page 133 of 209 CPC710 133 IBM Dual Bridge and Memory Controller Bit s 27 28 29 30 31 Description Unaligned ECOWX ECIWX Address Error 1 Address associated with ECOWX ECIWX is not word aligned Unaligned Transfer Error 1 Address alignment error Page Crossing Error 1 Page Crossing detected during DMA transfer TLBSYNC Detected 0 No TLBSYNC Detected 1 TLBSYNC detected during DMA transfer Transfer Address Increment Alignment Error UE Improper alignment of addresses when Address Increment bit is off Page 134 of 209 6 26 2000 IBM Dual Bridge and Memory Controller DMA Transfer PCI Address XPAR Reset Value x 0000 0000 Address User x FF1C 0070 Privileged x FF1E 0070 Access Type User Read Only Read Write Privileged Read Write Read Only PCI Address Y v 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 31 PCI Address Contains the adapter I O address for the DMA transfer operation 6 26 2000 Page 135 of 209 CPC710 133 IBM Dual Bridge and Memory Controller DMA Transfer Write Back Address XWAR Reset Value x 0000 0000 Address User x FF1C 0090 Privileged x FF1E 0090 Access Type User Read Only Privileged Read Write Bit s Description Writeback Address
52. First 32 Bytes 32 Bytes lt PIBAR 64 KB SIBAR 1 32 Bytes Pr r 32 Bytes 32 Bytes 32 Bytes 32 Bytes t e PIBAR 6 26 2000 Page 145 of 209 IBM Dual Bridge and Memory Controller PCI to System Memory Two types of address mapping modes are available PowerPC Reference Platform PREP Mode and Flexi ble PCI Host Bridge FPHB Mode To select a mode program bit 0 for PCI 32 or bit 8 for PCI 64 in the Chip Programmability Register PGCHP on page 111 PowerPC Reference Platform PREP Mode In PREP Mode access from the PCI to the system can be performed with or without PCI address translation When translation is used the most common method is to translate addresses by complementing the upper 12 bits PCI addresses ranging from x 8000 0000 to x FFFF FFFF are translated to system memory addresses x 0000 0000 to x 7FFF FFFF In this mode only PCI access to Memory are decoded by the CPC710 Configuration and I O are not decoded PCI Master Address Operation Whenever the PCI bridge logic identifies addresses coming from ISA Masters when the P ISA MASTER signal is active 21 they are passed directly to system memory Otherwise the untranslated addresses are checked to determine whether they fall within a bridge s PCI memory address range by comparing the PCI address to the following registers PCI Base Address for Memory PMBAR on page 69 PCI Memory Adaress Space Size MSIZE on page 74 If there is no m
53. Input Value Register GPIN sse nennen etn nnn nnn tns s nnn 116 GPIO Output Value Register GROUT cceeeeeeceeeneeceeeeeeeeeeeeeeeeeaaeaaeeeeeeeeeeseeeenaeaaeeeeeeeeeeeeetees 117 Address Transfer Attribute for Snoop Register ATAS sse 118 programming the ATAS Address Transfer Attribute for Snoop Register register 119 Typical ATAS programming ATAS 0 31 OxX709C2508 sse 119 Diagnostic Register AVDG t 120 Memory Controller Control Register MCCR cccccceceeeeeeeeeeeeeeeeeeeeeseeeeeaaeaeeeeseseneeenaaeaeeeeeeeees 122 Memory Error Status Register MESR ceeeccecceceeeeeeeeeeeeeeaaaeaecaeeeeeseeeeseceecaeeaeeeseeeeeeeeetees 124 Memory Error Address Register MEAR 2 c eeeeccecceeeeeeeeeeeeeeaeaaeaeeeeeeeeeedeeceaaseeeneenaneeeeeeees 125 Memory Configuration Extent Registers MCER 0 7 sss 126 System I O Register 0 SIORO c ccceceeceeceeeeeeeeeeeeeeaaaeaeeeeeeeeeeeseseaaaaeaecaeeeeeeeeeeseeseensaaeeeeeeeees 128 System O Register 1 SIOR 2e one pex petuntur ate ne et teu ERR RR RE 129 DMA Registers Space e 130 DMA Global Control GSCR cee ceeeeeeeeeeeee ee eeeeeee eee eeneeee kanann nEaN ELAONA AAA EE nsn en nennen nns 130 DMA Global Status GSSR uiia eee n iedaets ives apu eta cup DV EE ACER ape ud da danielle 131 DMA
54. No 0 b No 1 b High for EVEN DH MUX_SEL Low for ODD DL No 1 b Memory Address Bit Definition for Non Row Column Addressing Bits Address Bit Definition 0 1 00 Base address of memory Interleaving Bit 28 0 Even DIMMs 0 2 4 or 6 1 Odd DIMMs 1 3 5 or 7 Page 174 of 209 6 26 2000 SDRAM Subsystem Signals BSO BS1 SDCS 0 7 SDDQNM 0 7 SDRAS O0 3 SDCAS O0 3 WE 0 3 SDCKE O 7 Signal Name Type SDRAM Bank Select Chip Select Data Mask Row Address Strobe Column Address Strobe Write Enable Clock Enable SDRAM DIMM Chip Select Connections SDCS 0 SDCS 1 SDCS 2 SDCS 3 SDCS 4 SDCS 5 SDCS 6 SDCS 7 6 26 2000 Signal Name DIMM 0 Bank A DIMM 1 Bank A DIMM 0 Bank B DIMM 1 Bank B DIMM 2 Bank A DIMM 3 Bank A DIMM 2 Bank B DIMM 3 Bank B IBM Dual Bridge and Memory Controller Comments See the following table for connections 8 pins for load purposes 4 pins for load purposes 4 pins for load purposes 4 pins for load purposes 8 pins for load purposes DIMM and DIMM Bank Page 175 of 209 IBM Dual Bridge and Memory Controller SDRAM Subsystem Overview MADDRO ODD ADDR ODD 0 12
55. No DEVSEL received Access to PCI bus Detected SERR active during PCI transaction 1 A dummy 0 is returned for read operation For write data is ignored 6 26 2000 Action Notes Set single bit error and syndrome in MESR Set error address in MEAR Return corrected data to CPU If PGCHP 17 1 and PGCHP 26 1 Set memory error bit in SESR Set memory error address in SEAR Signal Machine Check with SYS MACHK Set error in MESR Set error address in MEAR Set memory error bit in SESR Set memory error address in SEAR if PGCHP 26 0 Loads Signal Machine Check with SYS TEA Stores Signal Machine Check with SYS MACHK If PGCHP 26 1 signal Machine Check with SYS MACHK Set double bit error in MESR Set error address in MEAR Return uncorrected data to CPU Signal Machine Check with SYS MACHK if write less than eight bytes Master abort the PCI transaction Set master aborted bit 18 in PCI Status register Set device error bit in PLSSR register Set PCI error bit in SESR Set error address in SEAR register If PGCHP 26 0 Loads Signal Machine Check with SYS TEA Stores Signal Machine Check with SYS MACHK If PGCHP 26 1 Signal Machine Check with SYS MACHK Terminate CPU transaction normally Master abort the PCI transaction Set master aborted bit 13 in PCI Status register Set SERR detected error in PLSSR register Set PCI error bit in SESR Set error address in SEAR register If PGCHP 26 0 Loads Signal M
56. Register DID on page 139 Base Address Register BAR on page 140 PCI BAR Enable Register PCIENB on page 141 System PHB Registers The PCI bridge logic follows the PowerPC PCI Host Bridge PHB Architecture including the enhanced error detection and error reporting features The logic deviates from PHB Architecture only in its ability to recover from PCI errors Page 188 of 209 6 26 2000 IBM Dual Bridge and Memory Controller PCI Bus Commands The following table describes the subset of PCI bus commands supported by the device Supported PCI Commands C BE 3 0 Command Support as Initiator Support as Target 0000 Interrupt Acknowledge Yes No 0001 Special Cycle Yes No 0010 I O Read Cycle Yes No 0011 1 O Write Cycle Yes No 0100 Reserved 0101 Reserved 0110 Memory Read Yes Yes 0111 Memory Write Yes Yes 1000 Reserved 1001 Reserved 1010 Configuration Read Yes Yes PCI 64 only 1011 Configuration Write Yes Yes PCI 64 only 1100 Memory Read Multiple No Yes 1101 Dual Address Cycle No No 1110 Memory Read Line Yes Yes 1111 Memory Write and Invalidate Yes Yes 6 26 2000 Page 189 of 209 IBM Dual Bridge and Memory Controller PCI Master Memory Read Cycles When the device receives a memory read bus cycle from system memory it first initiates a CLEAN cache operation to the processor bus Processor accesses to this cache line are SYS ARTRYed until the memory read is finished If the cache line is determined to be stale in m
57. Register 2 RGBAN2 This register contains Data coming from the CPU Reset Value x 0000 0000 Address x FF00 1120 Access Type Read Write Data from CPU Y Y 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 Bit s Description 0 31 Data from CPU Page 114 of 209 6 26 2000 IBM Dual Bridge and Memory Controller GPIO Direction Register GPDIR This register sets the direction of signals input or output on pins GPIOO GPIO1 and GPIO2 Reset Value x 0000 0000 Address x FF00 1130 Access Type Read Write c 2 o 2 O c o ao Og 5 Reserved Y vov Y 0 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description GPIO 0 Pin Direction 0 0 Input 1 Output GPIO 1 Pin Direction 1 0 Input E Output GPIO 2 Pin Direction 2 0 Input E Output 3 81 Reserved 6 26 2000 Page 115 of 209 CPC710 133 IBM Dual Bridge and Memory Controller GPIO Input Value Register GPIN This register stores values of the signal on pins GPIOO GPIO1 GPIO2 if it is defined as input Reset Value x 0000 0000 Address x FF00 1140 Access Type Read Only 3 a gt z oO 5 N 22 e Og 5 Reserved Y vov 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 81 Bit s Description 0 GPIOO Input Pin Value 1 GPIO1 Input Pin Value 2 GPIO2 Input Pin Value 3 31 Reserved Page 116
58. Set retry count expired bit in PLSSR register Set PCI error bit is SESR Set error address in SEAR register If PGCHP 26 0 Loads Signal Machine Check with SYS TEA 1 Stores Signal Machine Check with SYS MACHK If PGCHP 26 1 Signal Machine Check with SYS MACHK Terminate CPU transaction normally Page 167 of 209 IBM Dual Bridge and Memory Controller Page 168 of 209 6 26 2000 Memory Controller Overview The device s memory controller controls processor and I O interactions with the memory system The memory controller supports SDRAM and is 2 way interleaved to allow the memory to burst data on every CPU bus cycle at 100 MHz 1 1 2 1 after initial latency using only one memory address bus To handle criti cal word load individual control of the LSB column address bits is required for the DIMM pair The controller supports up to eight dual DIMMs banks of interleaved 72 bit memory 64 bit Data 8 bit ECC To reduce pin count the controller requires a Texas Instruments Tl ALVCH162268 MUX to externally multiplex the 144 bit data to 72 bits for device input Programmable parameters allow a variety of memory organizations and timings ECC protection is provided for all 64 bits of the data bus detecting and correcting single and double bit errors Different SDRAM organizations can be mixed Supported SDRAM Organizations on page 177 60x bus operation is limited to 100 MHz Programmable parameters allow for a variety of me
59. correct data to memory Software must write zeros to the MESR to clear this error If more than one single bit ECC error occurs before the MESR clears only the first error is recorded When a double bit ECC error or an address error occurs the software overwrites the MESR and MEAR Single Bit ECC Error Special Case For non burst write transactions that do not span an entire aligned double word the Memory Controller per forms a read modify write sequence to memory If the read portion of the sequence results in a single bit ECC error the error is not logged into the MESR and MEAR for both the diagnostic and normal modes How ever the memory controller automatically writes corrected data to memory Invalid Address Error An Invalid Address error is detected by the Memory Controller when an address does not match one of the eight configuration extents The hardware procedure for this error is 1 If no hard errors are in the MESR register set the invalid address error bit 2 If no hard errors are in the MEAR register store the address 3 In diagnostic mode the Memory Controller responds with dummy data and indicates an Invalid Address error to the requesting logic To enable further error logging the software writes zeros into the MESR When more than one address error occurs before the MESR clears only the first error is recorded No Single or Double Bit ECC errors are logged into the MESR and MEAR if they occur after the Invalid A
60. directed to PCI 32 bus 11 SYS CONFIG3 Configuration access directed to PCI 64 bus See 60x Bus Configuration on page 163 for details on configuration bus cycles and procedures 6 26 2000 Page 97 of 209 CPC710 133 IBM Dual Bridge and Memory Controller Connectivity Reset Register RSTR This register provides a means to individually reset devices on the 60x bus Bits 0 and 1 directly control SYS HRESETO and SYS HRESET respectively The remaining two bits control reset signals that are inter nal to device Reset Value x C000 0000 Address x FF00 0010 Access Type Read Write Reserved Y 4 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 mo Reset for PCI 32 Bus Bridge w Reset for PCI 64 Bus Bridge o Reset for 1st Processor Reset for 2nd Processor Bit s Description Reset For 1st Processor 0 0 SYS HRESETO signal is active 1 SYS HRESETO signal is inactive Reset For 2nd Processor 1 0 SYS_HRESET1 signal is active 3 SYS_HRESET1 signal is inactive Reset for PCI 32 Bus Bridge 2 0 Reset signal active 1 Reset signal is inactive Reset for PCI 64 Bus Bridge 3 0 Reset signal active 3 Reset signal is inactive 4 31 Reserved Page 98 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Software Power On Reset Control Register SPOR This register provides a mechanism for software to initiate a hard reset to the system
61. exactly the same type and therefore only one DIMM presence detect pin of each pair are read in from this register The read of this register results in the assertion of the PRES OEO signal and a Read cycle through the PCI32 A D lines That permits a read of the outside buffers containing the presence detect bits Bit 0 of this register correspond to bit 31 on the PCI A D lines Reset Value x 0000 0000 Address x FF00 1400 Access Type Read Only User Defined Y Y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 31 User defined Example of usage DIMM Pair 0 DIMM Pair 1 DIMM Pair 2 DIMM Pair 3 Presence Detect Pins Presence Detect Pins Presence Detect Pins Presence Detect Pins 4 vov vov vov Y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 7 DIMM Pair 0 Presence Detect Pins PD1 PD8 8 15 DIMM Pair 1 Presence Detect Pins PD1 PD8 16 23 DIMM Pair 2 Presence Detect Pins PD1 PD8 24 31 DIMM Pair 3 Presence Detect Pins PD1 PD8 Please see MCER Register Initialization on page 182 for PD definition and device supported values Page 128 of 209 6 26 2000 IBM Dual Bridge and Memory Controller System I O Register 1 SIOR1 Address x FF00 1420 Access Type Read Only User Defined Y Y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
62. is always at 1 DISCNT counter is programmable see Disconnect Counter DISCNT on page 59 1 TRDY IRDY DISCNT Counters are ACTIVATED PCI 64 Master Abort 9 0 Window of Master Abort is reduced to one cycle avoid parasitic master abort detection 1 Window of Master Abort is not reduced PCI 64 Target Abort 10 0 Device detects Target abort The Frame output is taken 1 Device never detects Target Abort but retry indefinitely accesses Page 120 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Bit s Description PCI 64 DEVCNT 11 0 Stop the counter down when devsel is detected 1 No stop the counter down PCI 64 Access Completion 12 0 The completion is activated when device is master and not during external exchange 1 The completion appears when the data is not a last 13 15 Reserved Reserved Must be left to 0 17 31 Reserved 6 26 2000 Page 121 of 209 CPC710 133 IBM Dual Bridge and Memory Controller Memory Controller Control Register MCCR This register provides the primary control for the memory controller logic Reset Value x 0000 0000 Address x FF00 1200 Access Type Read Write Bit s Description Global System Memory Address Space Enable 0 0 Device will not respond to addresses specified in Memory Configuration Extent Register MCERx Ae System memory address space enabled Diagnostic Mode 1 0 Normal Mode Multi bit ECC error will generate Machine Check 1 Diagnostic Mode Multi bit ECC d
63. minimum number of PCI bus clocks that a master can own the PCI bus starting from the cycle that FRAME is acti vated This register is set to X 00 at reset Page 49 of 209 CPC710 133 IBM Dual Bridge and Memory Controller Header Type HDRT Reset Value x 00 Address x OE Access Type Read Only Header Type Y Y 765432 10 Bit s Description Specifies the layout of bytes x 10 through x 3F in the configuration header and whether or not a particular device con 7 0 tains multiple functions Device always responds with x 00 to reads to indicate Layout 0 Writes to this register are ignored Page 50 of 209 6 26 2000 Built in Self Test BIST Description IBM Dual Bridge and Memory Controller Provides status and control for a Built in Self Test which device does not support Device responds with x 00 to reads Reset Value x 00 Address x OF Access Type Read Only BIST 4 Y 7 6 5432 10 Bit s 7 0 from this register and ignores writes 6 26 2000 Page 51 of 209 CPC710 133 IBM Dual Bridge and Memory Controller System Base Address Register for PCI 64 PSBAR For PCI 64 only the function is the same as that for System Base Address Register for PCI 32 PSBAR on page 84 Reset Value x 0000 0000 Address x 10 Access Type Read Write Address Reserved Enable I O or Memory v vov Y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7
64. nennen enn nensis 177 Memory Controller Registers eeeseeeeeeeeeeeeeene eese nennen nennen nnne nnnnnr nan nnnn nnn nnne nnne nnne 180 MOOR REGISICN e 180 MOER at Te TL s 182 Error Pandino geee ce M 184 Single Bit ECC Error General Case ccccccccecceceeeeeeeeeenneaeeeeeeeeeeeeeeeaeaaeaaeaeeeeeeseseseeesenseaeeeeeeeeess 184 Single Bit ECC Error Special Case siesisssi andia rennin Nanni KaR A ANNEN AAEN R tenentes 184 Invalid Address Error asinasina aa aana a aE E EO EE DAE 184 Double Bit ECC Error General Case ssssesssssseseseeeee naaa N sse Aa 185 Double Bit ECC Error Special Case cccccccecceceeeeeeeeeeeeeeaeeeeceeeeeeeeseeseneaeaaeaeeeeeeeeeeeseeseesneaeess 185 Page 4 of 209 Table of Contents 6 26 2000 po IBM Dual Bridge and Memory Controller Overlapping Memory Extents ceci eee eni ieee ete ae Ee tue e ete ieee 185 PEIBUOUSS oai bibo bed abd dp bb ob ODD Dicke ila na E a ae aaa laden 187 oiu 187 Address Map m 187 System Standard Configuration Registers eese eene nennen nnne nnn 188 System PHB ciclo E 188 PCIBus Commands css ic 25 occ
65. of 209 6 26 2000 IBM Dual Bridge and Memory Controller GPIO Output Value Register GPOUT This register stores values of signal on pins GPIOO GPIO1 GPIO2 if defined as output Reset Value x 0000 0000 Address x FF00 1150 Access Type Read Write o 2 T gt c an 5909 Os Og 6 Reserved Y vov 4 0 1 23 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 GPIOO Output Pin Value 1 GPIO1 Output Pin Value 2 GPIO2 Output Pin Value 3 81 Reserved 6 26 2000 Page 117 of 209 CPC710 133 IBM Dual Bridge and Memory Controller Address Transfer Attribute for Snoop Register ATAS This register contains SYS TT SYS TSIZ and SYS TBST values that are used during a snoop transaction These values can be changed according to the type of PowerPC processor This register must be set if bit 25 of the PGCHP register is programmed to 1 See Chip Programmability Register PGCHP on page 111 Reset Value x 0000 0000 Address x FF00 1160 Access Type Read Write Programming Value x 709C 2508 b 0111 0000 1001 1100 0010 0101 0000 1000 This setting is recommended for the PowerPC750 which is not able to perform Cache memory coherency with Kill and Flush operation as the PowerPC 604 E S E 5 c o u 2 c 2 I c s 5 8 o S 8 9 o 8 o is g o w Q i2 5 Q uz 2 c o o m o La o si Gg S c 5 2 o z o 5 o o o oO
66. of the four bytes of the address bus Odd parity means that an odd number of bits includ ing the parity bit are driven high The signal assignments correspond to Internal the following Pull up AP 0 A 0 7 AP 1 A 8 15 AP 2 A 16 23 AP 3 A 24 31 Input Represents one bit of odd parity for each of the four bytes of the address bus A checkstop is generated if bad parity is detected and bit 8 is 1 in the error control register SYS ADDRP 0 3 1 0 Configuration SYS CONFIGO Indicate the current address tenure is a configuration cycle to the device asso SYS CONFIG O ciated with this signal The associated device must respond if present to addresses in the range FF20 0000 through FF20 1FFF Other addresses are responded to as normal Transfer Attribute Signals Transfer Type Output Indicates the type of transfer in progress The values are pro grammable according to the PowerPC type and stored in the ATAS register Input Indicates the type of transfer in progress Internal SYS TT 0 4 O Pull up Page 24 of 209 6 26 2000 60x Bus Interface Signals Page 2 of 3 Signal Name VO Type Internal SYS TSIZ 0 2 VO Pull up es Internal SYS_TBST VO Pull up m Tri state SYS BE O Int pull up Address Transfer Termination Signals SYS_AACK O SYS_ARTRY VO a Internal SYS_SHD VO Pull up SYS L2 HIT Internal Pull up Data Bus Arbitration Signals SYS_DBGO o SYS_DBG1 Data Transfer Signals I
67. the processor bus 3 Not supported on store operations Page 158 of 209 6 26 2000 Transfer Types TT 0 4 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 1011x 11000 11001 11010 11011 11100 11101 11110 11111 Operation Transaction Clean Sector Address only LARX Reservation Set Address only Write with Flush SBW or Burst Reserved arbiter will assume address only transaction Flush Sector Address only Reserved arbiter will assume address only transaction Write with Kill Burst Reserved arbiter will assume address only transaction SYNC Address only TLBSYNC Address only Read SBR or Burst RWNITC Read with no Intent to Cache SBR or Burst Kill Sector Address only ICBI Address only RWITM Read with Intent to Modify Burst Reserved arbiter will assume address only transaction EIEIO Address only Reserved arbiter will assume address only transaction Write with Flush Atomic SBW Reserved arbiter will assume address only transaction ECOWX Graphics Write SBW Reserved arbiter will assume address only transaction TLB Invalidate Address only Reserved arbiter will assume address only transaction Read Atomic SBR or Burst Reserved arbiter will assume address only transaction ECIWX Graphics Read SBR Reserved arbiter will assume address only transaction RWITM Atomic Burst Reserved arbiter wil
68. to normal SYS TA with machine check condition signaling on SYS MACHKO or SYS MACHK1 Input Informs the device s 60x bus arbiter that the current data bus tenure has been terminated Machine Check Indicates the device has detected an error condition and a machine check exception is desired Checkstop Indicates the device has detected a non recoverable error condi tion and has entered checkstop state Hard Reset 0 1 Indicates the device or card associated with this signal must initiate a complete hard reset All outputs should be released to tri state Dura tion of reset except for device hardware system reset is controlled by soft ware Soft Reset 0 1 Indicates the processor connected to this signal will take a reset exception Occurs following a write to the CPU soft reset register SRST that has the appropriate bit set Timebase Enable Indicates the processor time bases should continue count ing Reflects bit 12 of the UCTL 12 register x FFOO 1000 System Normal operation when up 1 General System Reset when down 0 Interrupt Interrupt generated after writing a 1 in the IT ADD SET interrupt register This interrupt can be used by an external interrupt controller The writ ing can be made from the CPU in configuration mode or from the PCI 64 bus Only the PowerPC CPU can reset the interrupt by writing a 1 in the IT ADD RESET interrupt reset register Interrupt Indicates the end of the DMA dat
69. would otherwise be needed if the DMA operated in real address mode Execution of an eciwx or ecowx instruction involves the same sequence as a normal cache inhibited load and store with a few exceptions The processor calculates an effective address translates it and presents the resulting real address to the system bus as normal However this address bus does not select the slave The address is passed to the slave to be used on a subsequent transfer The slave is selected by a 4 bit Resource ID RID that is placed on the SYS TBST and SYS TSIZ 0 2 signals by the processor 6 26 2000 Page 199 of 209 IBM Dual Bridge and Memory Controller The device is selected for these transactions when the RID on the bus matches Configuration Register bits 8 11 in the device s System Control Register The bus transaction is always a single beat regardless of the SYS TBST signal setting While the DMA is occurring the device monitors the bus for a TLB Sync resulting from normal page maintenance by the OS kernel to terminate the transfer Software can then restart the transfer at the faulting address The DMA Controller transfers data between system memory and PCI only It cannot perform memory to memory transfers DMA operation is transparent to the PCI adapter which behaves as a PIO slave device Although eciwx and ecowx both initiate DMA the preferred instruction is ecowx because it writes to the sys tem bus eciwx is provided to avoid access violatio
70. 0 Page 85 of 209 CPC710 133 IBM Dual Bridge and Memory Controller Top of Peripheral Memory Space With Potential Deadlock TPMDLK Reset Value x 0000 0000 Address BAR x 000F 8210 Access Type Read Write Reserved Top of Peripheral Memory Space 4 vov v 012345 6 7 8 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description Top of Peripheral Memory Space Contains the top address for the CPU to PCI MEMORY access with potential deadlock 10 31 Reserved Page 86 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Bottom of Peripheral I O Space With Potential Deadlock BIODLK Reset Value x 0000 0000 Address BAR x 000F 8220 Access Type Read Write Reserved Bottom of Peripheral I O Space 4 vov v 012345 6 7 8 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description Bottom of Peripheral IO Space Contains the bottom address for the CPU to PCI IO access with potential deadlock 10 31 Reserved 6 26 2000 Page 87 of 209 CPC710 133 IBM Dual Bridge and Memory Controller Top of Peripheral I O Space With Potential Deadlock TIODLK This register exists on PCI 32 and PCI 64 Reset Value x 0000 0000 Address BAR x 000F 8230 Access Type Read Write Reserved Top of Peripheral I O Space v vov v 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Description Top of Peripheral I O Space
71. 0 pf 6 9 30 pf CHKSTOP SYS GBL SYS HRESET 0 1 SYS MACHK 0 1 SRESET 0 1 SYS TBE SYS TBST SYS TSIZ 0 2 SYS TT 0 4 7 4 30 pf 7 4 30 pf For FLASH Data Input Output Timings refer to signals P ADL 0 31 into PCI 32 bit bus Timing Specification section Page 226 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Packaging Information Package Dimensions 32 5mm BGA Standard JEDEC 32 5 0 2mm gt 30 48 0 2mm x 290OOO0O00O000000000000000000 OOOOOOOOOOOOOOOOOOOOOOOOO OOOOOOOO0O0O0O0O0O0O00O00O00000000O0 OOOOOOOOOOOOOOOOOOOOOOOO0O OOOOOOOOOOOOOOOOOOOOOOO0O00O0 OOOOOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOOOOO 25 x 25 Pad Array OOOOOOOOOOOOOOOOOOOOOOOO0O0 624 Total pads OOOOOOOOOOOOOOOOOOOOOOOO00O0 480 Signal I Os OOOOOOOOOOOOOOOOOOOOOOOOO 116 Power OOOOOOOOOOOOOOOOOOCOOOOOOO Md QOOOOOOOOOOOOOOOOOOOOOOOO 8 No Connect 32 5 30 48 OOOOOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOOO0O0O0 OOOOOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOOO0O00 OOOOOOOOOOOOOOOOOOOOOOOO0O0 OOOOOOOOOOOOOOOOOOOOOOO000O0 OOOOOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOOOO00O0 OOOOOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOOOO0O0 OOOOOOOO0O0O0O0O0O0
72. 01100 Kill sector No action To verify the coherency between Cache and System memory with a PowerPC 750 it is necessary for the CPC710 bridge chip to modify the TT 0 4 and thus oblige the PowerPC750 to react on snoop operations with the Address only cycles on the 60x bus It is possible to program the ATAS register such that the Clean Flush Kill code are modified in a Snoop code for PowerPC750 Typical changes of TT 0 4 code for the PowerPC750 Clean TT 0 4 00000 Read TT 0 4 201010 Flush TT 0 4 00100 gt RWITM TT 0 4 2 201110 Kill TT 0 4 01100 gt RWITM TT 0 4 2 201110 After modification to perform Cache Memory coherency the new Address only cycles are TT 0 4 OperationAnswer from the 750 TT 0 4 Operation Answer from the 750 01010 Read Flush or Kill 01110 RWITM Flush or Kill 01110 RWITM Flush or Kill Typical ATAS programming ATAS 0 31 0x709C2508 TSIZ 0 2 and TBST can be programmed on the Address only cycles to the following recommended values TSIZ 0 2 000 et TBST 1 Flush modification to RWITM ATAS 0 4 01110 ATAS 5 7 000 ATAS 8 lt 1 Kill modification to RWITM ATAS 10 14 2 01110 ATAS 15 17 lt 000 ATAS 18 lt 1 Clean modification to READ ATAS 20 24 lt 01010 ATAS 25 27 lt 000 ATAS 28 lt 1 The modification is active only if bit 25 of the PGCHP is set to 1 PGCHP 25 1 FF001100 Processor type 750 on 6 26 2000 Page 119 of 209 CPC710 133 IBM
73. 0V22 0P23 0P21 0P19 0M25 0M23 Signal P REQ5 P REQ6 P RST P SERR P STOP P TRDY PCG CLK PCI CLK PLL LOCK PLL RESET PLL TUNEO PLL TUNE1 PLN RTC CLK POWERGOOD PRES OEO PRES OE1 RESERVED1 RESERVED2 RESERVED3 RESERVED7 RESERVED8 RI SCAN GATE SDCASO SDCAS1 SDCAS2 SDCAS3 SDCKEO SDCKE1 SDCKE2 SDCKE3 SDCKE4 SDCKE5 SDCKE6 SDCKE7 SDCSO SDCS1 SDCS2 SDCS3 Pin 0M21 0T12 0J23 0U23 0W22 AA23 0D14 0P02 0B10 oM11 OR16 OT16 AA22 0TO2 0B12 0CO06 0U16 0M13 0L12 ABO8 0Y09 0M04 0D10 0K10 0K11 0J12 0J13 0J07 0E04 OFO9 0C02 0L10 OFO6 OE06 0B03 OLO1 0MO1 ONO1 ONO5 Signal SDCS4 SDCS5 SDCS6 SDCS7 SDCS8 SDCS9 SDCS10 SDCS11 SDCS12 SDCS13 SDCS14 SDCS15 SDRASO SDRAS1 SDRAS2 SDRAS3 SYS_AACK SYS_ADDRO SYS ADDR1 SYS_ADDR2 SYS_ADDR3 SYS_ADDR4 SYS_ADDR5 SYS_ADDR6 SYS_ADDR7 SYS_ADDR8 SYS_ADDR9 SYS_ADDR10 SYS_ADDR11 SYS_ADDR12 SYS_ADDR13 SYS_ADDR14 SYS_ADDR15 SYS_ADDR16 SYS_ADDR17 SYS_ADDR18 SYS_ADDR19 SYS_ADDR20 SYS ADDR 1 Pin 0P09 ONO3 0F03 0H06 0M05 OM03 OLO2 0J04 OLO4 OLO6 0G04 OLO8 0M09 0M10 ON11 0P11 0WO02 0V17 0Y19 0V16 0W16 AE19 AD19 AE20 AD20 AE21 0W18 0W 1 AE22 AD22 AC22 AD23 0Y22 0V24 AA25 0Y24 0Y25 0W24 0W25 Signal SYS ADDR22 SYS ADDR23 SYS ADDR24 SYS ADDR25 SYS ADDR26 SYS ADDR27 SYS ADDR28 SYS ADDR29 SYS_ADDR30 SYS_ADDR31 SYS_ADDRPO SYS_ADDRP1 SYS_ADDRP2 SYS_ADDRP3 SYS_ARTRY SYS_BGO SYS_BG1 SYS BRO SYS BR S
74. 199 The write in the XTAR register results in the start of a DMA operation 199 CCIW Or SCOWX INSIMUCTION ERE cm 199 DMA Transfer He6glslters oreo EE aE a 201 DMA Transfer Status Cache Line eeeeesissesssseeeeeeseseeeenn nennen nennen nennt einn nnas 202 DMA der eee 203 Special Boundary GonditlOlts scsi coudre ecce det c ditte Ute e gue cee een lasts 204 ullis r4 iilo erro 205 Power Up SQqQueinCe 205 ii HDUESEDT gE 205 EE Ee aa aN Ae Oem RINT ROLE et nT NDS ET Oe Oe 206 POWERGOOD Power On Reset 2 ssssecceeseeeseeeeeeeeeesenaeeeeeceesaaesasneaeseaaesasneaeeesaeeeseaaeeneeeeeseaaeseseeeeneas 206 Reset individual devices a ccsct ieee eceeleteec ct iile crine dee evveditonaavucsuneg svcouueoueveveceuaeevvuddueree 206 Reset in Multiprocessor mode s sccccceseeeeeeeeeeneeeeeeeseeeeeeenseeaeeeeeeseaeeaeeeeeeseeeeeeseseeeeeeseseeeeeeeenseseeeees 207 4 Way MUltiprOCesSOF creer EE En ere NE E AOE prune E RE ERR 207 Hcnrico A tE n 211 e dlboa up 211 Read Page Hit from PowerPC CPU to SDRAM neeeeseeeeee enne nnne ennt nnn nri nn nnn inn 211 Table of Contents 6 26 2000 Page 5 of 209 IBM Dual Bridge and Memory Controller Read Page Miss from PowerPC CPU to SDRAM
75. 22 11 000 5 00 00 00 00 00 11 22 33 4 33 22 11 00 000 TSIZE 4 Bytes 0 11 22 33 44 00 00 00 00 0 44 33 22 11 0000 1 00 11 22 33 44 0000 00 BURST O 33221100 000 4 00 00 00 44 1110 2 00 00 11 22 33 44 00 00 BURST 0 22110000 001 4 00 00 44 33 1100 3 00 00 00 11 22 33 44 00 BURST 0 11 00 00 00 011 4 00 44 33 22 1000 4 00 00 00 00 11 22 33 44 4 44 33 22 11 0000 TSIZE 5 Bytes 0 11 22 33 44 55 00 00 00 BURST 0 44 33 22 11 0000 4 00 00 00 55 10 1 00 11 22 33 44 55 00 00 BURST 33 22 11 00 0001 4 00 00 55 44 00 2 00 00 11 22 33 44 55 00 BURST O 22110000 0011 4 00 55 44 33 000 3 00 00 00 11 22 33 44 55 BURST O 11 00 00 00 0111 4 55 44 33 22 000 TSIZE 6 Bytes 0 11 22 33 44 55 66 00 00 BURST 0 44 33 22 11 0000 4 00 00 66 55 00 1 00 11 22 33 44 55 66 00 BURST 0 33 22 11 00 0001 4 00 66 55 44 000 2 00 00 11 22 33 44 55 66 BURST O0 22110000 0011 4 66 55 44 33 0000 TSIZE 7 Bytes 0 11 22 33 44 55 66 77 00 BURST 0 44 33 22 11 0000 4 00 77 66 55 1000 1 00 11 22 33 44 55 66 77 BURST O0 33 22 11 00 0001 4 77 66 55 44 0000 TSIZE 8 Bytes 0 11 22 33 44 55 66 77 88 BURST 0 44 33 22 11 0000 6 26 2000 Page 151 of 209 IBM Dual Bridge and Memory Controller Processor Behavior Mode The CPC710 supports PowerPC 604 and 750 processors operating in Big Endian BE and Little Endian LE modes The mode determines the order in which a multibyte scalar is stored in memory or I O In BE mode the specified address contains the scalar s most significant b
76. 27 28 29 30 31 Bit s Description 0 1 Reserved Checkstop Error 2 0 No Error 1 Device initiated checkstop occurred Flash Write Error 3 0 No Error ds Write to flash occurred when not enabled DMA Controller Access Error 4 0 No Error 1 Access performed to DMA Controller when not enabled see DMA Global Control GSCR on page 130 Page 108 of 209 6 26 2000 6 12 20 21 22 23 24 25 26 31 6 26 2000 IBM Dual Bridge and Memory Controller Description Access to Disabled System I O Address Space Error 0 No Error 1 Access performed to System I O address space that is not enabled Reserved Address Bus Parity Error 0 No Error 1 60x bus address parity error detected by device Data Bus Parity Error 0 No Error 1 60x bus data parity error detected by device Addressing Error Detected for CPU 0 0 No Error 1 Addressing error CPU to PCI Bus Access Error for CPU 0 0 No Error T Error occurred on PCI bus while servicing processor load store request PCI 32 Bus Master Error 0 No Error 3 Error occurred during PCI master initiated operation PCI 64 Bus Master Error 0 No Error 1 Error occurred during PCI master initiated operation DMA Error for CPU 0 0 No Error d Error occurred during DMA transfer Data Bus Timeout Error 0 No Error 1 Indicates that the CPC710 has detected a 8ms time out between DBG to last SYS TA or SYS TEA In this case of error the CPC710 activates also t
77. 6 2000 I O Signals I O Signal Diagram SYS BR 0 SYS BR 2 3 SYS 2 HIT POWERGOOD CHKSTOP 4 SYS HRESET 0 1 4 SYS SRESET 0 1 SYS MACHK 0 1 SYS TBE SYS CONFIG 0 1 INT1 INT2 4 GPIOO GPIO1 GPIO2 gt G REQ 0 7 G GNT 0 7 4 PCG CLK GLOCK G CFG 0 2 G ARB G IDSEL gt P REQ 0 6 P GNT 0 6 P_LOCK gt PCI CLK _ P ISA MASTER gt P MEMREQ P MEMACK 4 P CFG 0 2 4 MUX CLKEN 1B 2B A1 A2 MUX OEA MUX OEB e MUX SEL 4 4 BS 0 1 4 SYS CLK gt CET AB gt CE1 C1 C2 gt PLN RTC CLK X Di 1 2 TDI TCK TMS TRST TESTIN y PLL RESET gt PLL TUNE 0 1 gt 2 2 2 32 1 5 1 4 2 60x 1 2 Interface l 2 1 1 2 64 1 8 1 2 2 2 SIO 1 3 Interface 1 2 64 8 8 8 2 2 1 PCI 64 1 1 Interface 3 33 66 MHz 1 1 2 1 2 4 7 32 7 4 1 1 f PCI 32 1 1 Interfac
78. 6 2000 16 MB 16 MB range not forwarded to PCI bus Area to map PCI I O spaces Area to map System Memory Area to map PCI Memory Spaces Page 143 of 209 IBM Dual Bridge and Memory Controller CPU to PCI Addressing Model PREP and FPHB Modes Programmable registers in the Specific PCI Host Bridge Space Specific PCI Host Bridges Space BAR x 000F 6110 to BAR x 000F 9810 on page 33 map PCI Memory and PCI I O address spaces into the 4 GB System address space Each PCI bridge in the device contains a set of these registers allowing firmware to program PCI address spaces anywhere in memory rather than at fixed PCI address spaces For example the registers can be configured to have PCI address spaces in system memory follow the fixed Sandalfoot PCI addressing model CPU to PCI Addressing Model PREP and FPHB Modes Processor View PCI I O Space PCI Memory Space 4GB 4GB 16MB c Peripheral MSIZE Memory Space BL o 2 m SMEAR PCI Memory L o PMBAR E E S 9 IOSIZE Peripheral e I O Space SIBAR PCI I O PIBAR 16MB eet deeem 0 As the figure above shows the device monitors addresses on the processor bus to determine whether a CPU address falls within the ranges specified by the following SMBAR MSIZE and SIBAR IOSIZE registers PCI Memory Adaress Spac
79. 6 MHz Dual Clocked Logic Page 10 of 209 6 26 2000 Internal Buffering and Data Flow 60x Bus 60x Bus Interface Logic gt gt 1 0 LE BE LE Byte Swap Byte Swap AAA IBM Dual Bridge and Memory Controller System Bus Clock 66 MHz CLK PCI 64 Bus i i 64 bytes lt 4 I O Uren Memory Bus System Bus Clock f gt 64 bytes v VO 64 bytes A L_ 64 bytes lt PCI 64 Bridge Logic Command Queue Rotating priority A new arbitration after each 32 Byte Memory Control Logic PCI 32 Bridge Logic 6 26 2000 v System Bus Clock DMA Controller 32 bytes SIO 64 bytes lt vO S Ww A P gt A 33 MHz CLK PCI 32 Bus Page 11 of 209 IBM Dual Bridge and Memory Controller Page 12 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Pin Information Pin assignment Top View Through Ceramic For specific pin assignments see Signal Pins Sorted by Pin Number on page 14 and Signal Pins Sorted by Signal Name on page 18 CLODOUCCUDUDLCUg 218 2 6 6 6 6 ee OS OOSOOOSODODOODOSODOO0SOOSO OCOODOOOODOUDOCNWCU OCC ODUOOCCO OOeOooo eoooeocoo eooo eooo0eoo CUOCC
80. 7FDO CTLRW Configuration Register R W 78 BAR x 000F 7FEO CTLRO Configuration Register R O 79 1 BAR x 000F 8000 CFGA CONFIG ADDR 80 2 BAR x 000F 8010 CFGD CONFIG DATA 81 2 BAR x 000F 8100 PSSIZE PCI to System CPU Address space Size 82 BAR x 000F 8120 BARPS CPU Base Address Register 83 BAR x 000F 8140 PSBAR System Base Address Register for PCI 32 84 3 BAR x 000F 8200 BPMDLK m of Peripheral Memory space with potential dead 85 BAR x 000F 8210 TPMDLK Top of Peripheral Memory space with potential deadlock 86 BAR x 000F 8220 BIODLK Bottom of Peripheral I O space with potential deadlock 87 BAR x 000F 8230 TIODLK Top of Peripheral I O space with potential deadlock 88 BAR x 000F 8300 IT_ADD_RESET PCI 64 Reset Interrupt INT1 Addressed Register 89 4 BAR x 000F 8310 INT_SET Set of G INTA G_INTB G_INTC G_INTD on PCI 64 90 BAR x 000F 9800 CSR Channel Status Register 91 BAR x 000F 9810 PLSSR Processor Load Store Status Register 92 Read Only Register write is ignored Little Endian registers Only for PCI 32 Only for PCI 64 ANH Page 64 of 209 6 26 2000 IBM Dual Bridge and Memory Controller PCI Slave Error Address Register PSEA This register is used to log the PCI address when an error occurs during Device PCI slave transfer See PCI Master Error Handling on page 195 for additional details This register is reset to zero after a POWERGOOD or when one of the bit RS
81. 9 19 19 19 19 19 19 19 19 19 19 19 19 6 26 2000 IBM Dual Bridge and Memory Controller DIMM Column and Bank Address Derivation for SDRAM x72 Width BETA DIMM Column Address ig patie Addressing 11 10 9 8 7 6 5 4 3 2 1 o 1 0 13 11 2 2 3 6 20 21 22 23 24 25 26 27 5 8 13 10 2 3 6 20 21 22 23 24 25 26 27 5 8 13 9 2 3 6 20 21 22 23 24 25 26 27 5 8 13 10 1 5 6 20 21 22 23 24 25 26 27 8 13 9 1 6 20 21 22 23 24 25 26 27 8 13 8 2 20 21 22 23 24 25 26 27 5 8 13 8 1 i 20 21 22 23 24 25 26 27 8 12 10 2 i 4 6 20 21 22 23 24 25 26 27 5 8 12 9 2 6 20 21 22 23 24 25 26 27 5 8 12 8 2 i 20 21 22 23 24 25 26 27 6 8 12 9 1 6 20 21 22 23 24 25 26 27 8 12 8 1 i 20 21 22 23 24 25 26 27 8 11 10 1 y 6 7 20 21 22 23 24 25 26 27 8 11 91 7 20 21 22 23 24 25 26 27 8 11 8 2 20 21 22 23 24 25 26 27 7 8 11 8 1 i 20 21 22 23 24 25 26 27 8 1 The Memory Controller interleaves with only one memory address bus To handle critical word load individual control of the LSB column address bits is required for the DIMMs MADDRO ODD is used for the LSB address of the even and odd DIMMs 2 Bit 10 is never used as address during CAS phase 6 26 2000 Page 179 of 209 IBM Dual Bridge and Memory Controller Memory Controller Registers MCCR Register The Memory Controller Control Register contains all the parameters to fit the Memory Controller to the Syn chro
82. 9 Reserved 30 31 Byte Offset Specifies the byte offset associated with the DMA transfer real address Page 132 of 209 6 26 2000 IBM Dual Bridge and Memory Controller DMA Transfer Status XSSR Reset Value x 0000 0000 Address User x FF1C 0050 Privileged x FF1E 0050 Access Type Read Only User and Privileged S wi o wx 5 3 ui E s o 5 uoa o lt 2 v Z5 amp Bez Sogob E Oo x 2 5 0 S 2 o SPP 55 He GO 5 ow WwW 6s NM Toop GOOF Of pp pe 26 9h 9 n 9 5 99 62b9 9S o0 5 5 9 FG om o Reserved Transfer Length Reserved 29 20e 8 558p 2 v9 v vov V4 i44 0 1 23 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 2 Reserved 3 15 Transfer Length Contains the number of bytes remaining when the transfer was completed or aborted 16 19 Reserved 20 Invalid PCI Address 1 XPAR did not match any PCI extents PCI Bus Error 21 1 Error detected during PCI bus transaction No Interrupt generated only MACHK Machine Check Signal is acti vated 22 Address Error 1 Invalid memory address detected no Interrupt generated only MACHK is activated 23 ECC Error i Double bit ECC error detected in memory no Interrupt gen only MACHK is activated Transfer Complete 24 0 Transfer is not complete 1 Transfer is complete for Memory Interface Transfer Status 25 0 No DMA transfer in progress 1
83. ADH6 G_ADH27 G_ADH17 Vpp G ADH19 INT2 Vpp G PAR64 MDATAS50 MDATA49 SDCS6 MADDR12 MDATA61 SDCKE5 MDATA70 G_REQ64 SDCKE2 CHKSTOP G REQO G CFG2 Vpp G ADL20 G ADL21 CEO IO G ADH2 G GNT5 G ADH13 G ADH26 G_ADL4 G_ADH29 G_ADH22 G_ADL14 G_ADL13 MDATA43 MDATA52 Ground SDCS14 MADDRO_ODD MDATA45 6 26 2000 IBM Dual Bridge and Memory Controller Signal Pins Sorted by Pin Number Page 2 of 4 Pin Signal Pin Signal Pin Signal Pin Signal 0G07 Ground 0H21 G ADL6 0K10 SDCASO OL24 P ADL12 0G08 MDATA69 0H22 G ADL8 0K11 SDCAS1 OL25 P_ADL17 0G09 WEO 0H23 G PAR 0K12 G REQ5 0MO1 SDCS1 0G10 MADDRO EVEN 0H24 G ADL9 0K13 Vpp 0MO2 CEO TEST 0G11 Ground 0H25 Ground 0K14 Vpp 0MO3 SDCS9 0G12 G REQ3 0J01 MDATA57 0K15 SYS BR 0MO4 RI 0G13 G LOCK 0J02 Vpp 0K16 G ADH18 0M05 SDCS8 0G14 G ACK64 0J03 MDATA54 0K17 SYS BR3 0MOG CE1 C2 0G15 Ground 0J04 SDCS11 0K18 P ADL24 OMO7 MDATA7 0G16 G ADH8 0J05 Vpp 0K19 FLASH WE OMO8 CE1 B 0G17 G ADLO 0J06 MDATA56 0K20 SYS_CLK 0MO9 SDRASO 0G18 G ADH14 007 SDCKEO 0K21 Ground 0M10 SDRAS1 0G19 Ground 0J08 MDATA63 0K22 VDDA OMi1 PLL RESET 0G20 G ADL3 0J09 Vpp 0K23 P ADL23 0M12 Vpp 0G21 G_ADL5 0J10 MADDR1 0K24 P ADL22 0M13 RESERVED2 0G22 XADR LAT 0J11 G_GNT4 0K25 P_ADL18 0M14 Vpp 0G23 Ground 0J12 SDCAS2 0LO1 SDCSO 0M15 P CFGO 0G24 G ADL12 0J13 SDCAS3 0LO2 SDCS10 0M16
84. Address Register PSEA eesssessssseseseeeeeenne enne nnne nnne nnn 65 PCI Diagnostic Register FP OIDQ iscst roter eter be RRERE sh dadeeds UEEUEEEE HIR EERR GRE SEXEERR I BERERR ARA SERE uERE 66 Interrupt Acknowledge Cycle INTACK ssesessseeneeneeenennen nennen nnn nensi nnns 67 PCI Base Address for I O PIBAR essen enne nennen enne nennen nnne 68 PCI Base Address for Memory PMBAR sss nennen nnne rns nnn nennen 69 Component Reset Register CRR sse nnne eren nnrnrrt nennen nnns 70 Personalization Register PR eiii ise asiste ca quet EL LU HR E A dd Rea d apu 71 Arbiter Control Register ACR eecccceeeeeeeeeceeeencneeeeeeeaeeeeeeeaaaeeeeeeeaaeeeeeeeaaaeeeseeeaaeeeeeeeaaeeeeeeeeaeeneeaas 73 PCI Memory Address Space Size MSIZE sssssssseeseseeenen nene 74 PCI I O Address Space Size IOSIZE sse nnne nnne 75 System Base Address for PCI Memory SMBAR sseseeeeeeenenn eee nennen nnns 76 System Base Address for PCI I O SIBAR sss eene eee nennen nennen nnns 77 PHB Configuration Register CTLRW sssssessseseseeeeeneenen eee nennen enne nnne 78 PHB Configuration Register CTLRO sssssssesssseseeee ener ennt ne nnne 79 CONFIG ADDRESS Register CFGA esssssssssesessssesenenen nennen entente sen nennen nnns 80 CONFIG DATA Register CFGD
85. As shown in the following figures MCER registers must be programmed according to the DIMM Bank configuration used Since the device works in an interleaved way the minimum equipment required is two Single or Dual DIMM Banks Programming with Single Bank DIMMs T zI Interleaved Bank 1 W ce g empty tr DIMM Bank A DIMM Bank A a rod Interleaved amp Banko programmed Single Bank DIMM Odd Single Bank DIMM Even MCERO for Interleaved Bank 0 must be programmed MCERO for Interleaved Bank 1 must be empty or bit 0 set to 0 All unused MCERx locations must be empty Programming with Dual Bank DIMMs Interleaved DIMM Bank B DIMM Bank B is Bank 1 rogrammed DIMM Bank A DIMM Bank A T 3 prog uj Q Interleaved Banko programmed Dual Bank DIMM Odd Dual Bank DIMM Even MCERO and MCER1 for Interleaved Banks 0 and 1 must be programmed 6 26 2000 Page 173 of 209 IBM Dual Bridge and Memory Controller Memory Signal Connections SDRAM Common Signals Signal Name Type MDATA 0 71 72 bit Data MADDRTI 12 MADDRO ODD Address MADDRO EVEN External MUX Controller for Memory Data Signal Name Toggle for Reads Toggle for Writes MUXCLKEN1B Yes No tb MUXCLKEN2B Yes No 1 b MUXCLKENA1 No 1 b Yes MUXCLKENA2 No 1 b Yes MUX OEA No 1 b No 0 b MUX OEB
86. Bus LLEEEEELEEEEEELEEEEEELEEEELLELES CLLEEEELLEEELELLEEEEELLELELLL LT I 0 78 15 16 2324 31 0 78 1516 23 24 31 6 26 2000 Page 153 of 209 IBM Dual Bridge and Memory Controller 60x Bus Arbiter Description The arbiter in the device has the following characteristics Arbitration for three devices two levels for external masters and one for internal device requests No half cycle precharge required for SYS TA SYS_TEA ABB and DBB Highly programmable address pipeline control Data streaming capability for external devices Programmable address bus parking capability Programmable timing on SYS AACK Rotating address bus request priority scheme Rotating Priority Resolution The device s 60x arbiter implements an algorithm that rotates priorities when the address bus is granted to a master When multiple masters request the bus the arbiter grants the bus to the master with the highest pri ority during the arbitration period then downgrades that priority to the lowest level for the next period The arbitration period occurs during the SYS AACK assertion cycle If two masters continuously request the bus they receive alternate control This logic is satisfactory unless a master implements a 64 byte cache line and needs to issue two 32 byte burst transfers to fill the cache In this case the device has a programmable mode whereby the arbiter allows one bus master to perform a pair of back to back address tenures ev
87. Bytes a TT Swap Butter PCI 64 BUS PCI 32 Bridge Logi Big Endian 64 Bytes Memory Data Buffers Byte Boi T Swap ytes Saa A Address Buffer PCI 32 BUS Memory 32 lt _ gt Control gt Bytes gt 19 64 Data Buffer uM Little Endian IBM25CPC710AB3A100 The following table shows how the Data are transmitted from the CPU to the PCI 32 bus for various size of bytes Page 150 of 209 6 26 2000 IBM Dual Bridge and Memory Controller TSIZE 1 Byte 0 110000 00 00 00 00 00 0 00 00 00 11 110 1 00 11 00 00 00 00 00 00 0 00 00 11 00 101 2 00 00 11 00 00 00 00 00 0 00 11 00 00 011 3 00 00 00 11 00 00 00 00 0 11 00 00 00 0111 4 00 00 00 00 11 00 00 00 4 00 00 00 11 110 5 00 00 00 00 00 11 00 00 4 00 00 11 00 101 6 00 00 00 00 00 00 11 00 4 00 11 00 00 011 7 00 00 00 00 00 00 00 11 4 11 00 00 00 0111 TSIZE 2 Bytes 0 11 22 00 00 00 00 00 00 0 00 00 22 11 00 1 00 11 22 00 00 00 00 00 0 00 22 11 00 00 2 00 00 11 22 00 00 00 00 0 22110000 001 3 0000001122 00 00 00 BURST O 11000000 011 4 00 00 00 22 10 4 00 00 00 00 11 22 00 00 4 00 00 22 11 00 5 00 00 00 00 00 11 22 00 4 00 22 11 00 00 6 00 00 00 00 00 00 11 22 4 22110000 001 TSIZE 3 Bytes 0 1122 33 00 00 00 00 00 0 0033 22 11 000 1 001122 33 00 00 00 00 0 33221100 000 2 00001122 33 00 00 00 BURST O 22110000 001 4 00 00 00 33 110 3 0000001122 33 00 00 BURST 0 11000000 011 4 00 00 33 22 100 4 00 00 00 00 11 22 33 00 4 00 33
88. C 0090 0 31 R FF1E 0090 0 31 R W Writeback Address Register XTAR FF1C 00A0 0 31 R FF1E 00A0 0 31 R Translated Address Register The steps for executing a DMA transfer with software are 1 Initialize XSCR to indicate length and direction of transfer 2 Initialize XPAR with the PCI address The PCI logic takes the address in the XPAR register and applies the translation as described in CPU to PCI Adaressing Model PREP and FPHB Modes on page 144 Initialize XWAR with the address to which the device writes to indicate status following transfer Clear cache line status in memory at address specified in XWAR Execute the ecowx instruction or eciwx if read only page to start transfer o oa A O Wait until an End of DMA transfer interrupt IT occurs then read the status on the memory address specified in XWAR Reset bit 4 of the GSCR register to acknowledge the IT Alternatively perform cache polling to the memory address specified in XWAR and wait until the cache status flag changes from x 00 to x FF 6 26 2000 Page 201 of 209 IBM Dual Bridge and Memory Controller DMA Transfer Status Cache Line The following table shows the definition of the 64 bit of status stored in main memory at the address defined by the XWAR register Only bits 32 63 of the second double word of the Write Back Status cache line are valid All other bytes in the cache line must be ignored DMA Transfer Status Cache Line Definition Bit s
89. C Reference Platform PREP Mode esee 146 PCI Master Address Operation scsssieceniiusnia seen nennen tnmen nen nnne nnn nnns 146 Translation Enable ienis ir keen ia dn e vna a beca eve on va dua eda Drs de da d PU ER EL ER 147 Translation Disabled m 147 Flexible PCI Host Bridge FPHB Mode u eeeceeseeeeeseeeeeeeeeneeeeeeeaaaeeeeeeeaaeaeeeeeaaaeeeseeeaesaeeeeneanaees 148 60x Interface essai dninkx aia QUE UU Eu nananana xU CHEF REN MM MN CHEN DUERME NM E MEE naana annadsa 149 eun ee E 149 ISI IEDESITI Tg d 150 Processor Behavior Mode cccccecesssececececsssscecceceeuseececceaneuseecececauaescecscenaaseceeeceaeaeseseeeaeanseseess 152 Processor Behavior in LE Mode mirren a E E a E E aaa 152 Endian Behavior ccccccccesssssceececeenseseecceaneeseecececeuuascececeseasseeceeceauaeseeeseasaaseseececeuansseeeeeseasseseeeeeas 152 Table of Contents 6 26 2000 Page 3 of 209 IBM Dual Bridge and Memory Controller 60x Bus Arbiter DescripllOn 2 oer concerted ceacerecssenasedexeceancicescaccedsvedcoacereresducustescenanevexscacueny 154 Rotating Priority FResolutlOn 2 etre te Ease egE AREE de qquE Ru cena RM RR EE EH age Educa 154 Address Bus PIPING unco eterne EY T A ated REENT vue Te RERO 154 Arbiter FROGQUING IMO MUS
90. CFGA 0xff4f8000 write 0x04000080 CFGD Oxff4f8010 write 0x5601 PCI32 Interface registers setup Ay PR PIBAR Oxff5f7800 write 0x1c000000 PMBAR write 0x1a000000 PR write 0x0000c000 ACR write Oxfe000000 MSIZE write Oxfe000000 example with 32 MB IOSIZE write Oxff800000 example with 8 MB SMBAR write 0xc0000000 SIBAR write 0x80000000 CSR write 0x00000000 PLSSR write 0x00000000 BPMDLK write 0xc0400000 TPMDLK write 0xc0800000 BIODLK write 0x80400000 TIODLK write 0x80800000 PCI32 Command register setup CFGA 0xff5 8000 write 0x04000080 CFGD 0xf 5 8010 write 0x5601 Wait for SDRAM initialization is complete MCCR 2 goes to a 1 Release external reset to PCI32 bus agents CRR Oxff5f7ef0 write Oxfc000000 Release external reset to PCI64 bus agents CRR Oxff4f7ef0 write Oxfc000000 End of CPC710 100 registers setup sequence 6 26 2000 Page 209 of 209 IBM Dual Bridge and Memory Controller Page 210 of 209 6 26 2000 Timing Diagrams CPU to Memory Read Page Hit from PowerPC CPU to SDRAM 0 1 2 8 4 85 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CLK100MHz AnA SYS_ADDR
91. CPUs and I O devices All device I O pins go to tri state After a POWERGOOD cycle outputs on all interfaces are either floating or driven to their inactive state except for the reset signals sent to the board as described below 1 PowerPC bus HRESETO and HRESET 1 are driven Low for the same duration as the POWERGOOD active pulse low level 2 PCI 64 bus G_RST is driven Low from the beginning of the POWERGOOD assertion and remains active after POWERGOOD is deasserted G_RST is deactivated when the processor writes a 1 into bit 0 of the Component Reset Register CRR Page 70 BAR x 000F 7EFO for PCI 64 G_RST is deactivated within a period that complies with the PCI Specification 2 for the 64 bit interface 3 PCI 32 bus P RST is driven Low from the beginning of the POWERGOOD assertion and remains active after POWERGOOD is deasserted P RST is deactivated when the processor writes a 1 into bit O of the Component Reset Register CRR Page 70 BAR x 000F 7EFO for PCI 32 after several PCI clocks Reset individual devices The Connectivity Reset Register RSTR at the address x FF00 0010 provides a means to individually reset devices on the 60x bus Bits 0 and 1 directly control SYS HRESETO and SYS_HRESET1 respectively The remaining two bits control PCI 32 and PCI 64 reset signals that are outputs of the CPC710 PCI32 bus example When bit 2 of register RSTR is asserted low the PCI32 bus goes to reset After
92. CTL Universal Control Register 100 x FF00 1010 MPSR Multi Processor Semaphore Register 102 x FF00 1020 SIOC System I O Control 103 x FF00 1030 ABCNTL 60x Arbiter Control Register 104 x FFOO 1040 SRST CPU Soft Reset Register 106 7 x FFOO 1050 ERRC Error Control Register 107 x FF00 1060 SESR System Error Status Register 108 x FF00 1070 SEAR System Error Address Register 110 x FFOO 1080 Reserved x FF00 1100 PGCHP Chip program Register 111 x FF00 1110 RGBAN1 Free Register 1 113 x FFOO 1120 RGBAN2 Free Register 2 114 x FFOO 1130 GPDIR GPIO Direction Register 115 x FF00 1140 GPIN GPIO Input Register 116 x FF00 1150 GPOUT GPIO Output Register 117 x FFOO 1160 ATAS Address Transfer Attribute for Snoop Reg 118 x FFOO 1170 AVDG Device Diagnostic Register 120 x FFOO 1174 to x FFOO 11FF Reserved x FF00 1200 MCCR Memory Controller Control Register 122 x FFOO 1210 Reserved x FFOO 1220 MESR Memory Error Status Register 124 x FFOO 1230 MEAR Memory Error Address Register 125 x FFO0 1300 MCERO Memory Configuration Extent Register 0 126 RO Read Only Register All bits can be read Only bits 4 31 can be written All bits can be read Only bits 0 3 can be written Four beat burst read operations allowed to this address space Single byte writes only Not decoded by system logic Byte accesses allowed WO Write Only Register Range that IBM Dual Bridge a
93. Contained in SESR Page 110 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Chip Programmability Register PGCHP This register allows the device to be programmed in order to provide additional functions Reset Value x 0000 0000 Address x FF00 1100 Access Type Read Write Machine Check Detected Signal When Single Bit Error co S E E 5 as e o 2 3 28 3 3 g u E 5 3 z 2 2 h gt 0 2 2 o Ee o0 lt x lt n a otg o o oco 9 e 2 2 9 3 2 9592939 g9 887 5 Ww 2 TEE BB 2 zeg 85 9r E 9 t a I E I aes E E 90 oO a L S d st E a E oO o oO Oo F o 0 o l o o 8 o 2 88 9 sz 8 2 85 a c Reserved amp d cS Reserved Ec Reserved 75 G Reserved ty bh 9 4 4 M44 4 0 11 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description PCI 32 Host Bridge Address Map Type Controls which address map is used See Address Maps on page 143 0 0 PREP mode 1 FPHB mode Specific Base address on PCI 32 is used 1 Reserved Must be left to 0 2 7 Reserved PCI 64 Host Bridge Address Map Type Controls which address map is used See PCI to System Memory Address ing Model FPHB Mode on page 148 8 0 PREP mode i FPHB mode Specific Base address on PCI 64 is used External Arbiter on PCI 64 Enable Read only status bit 9 0 Internal arbiter is activated 1 Internal arbiter is de
94. DATA20 AAO8 SYS DATA15 6 26 2000 Pin AA09 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 ABO1 AB02 AB03 AB04 AB05 AB06 AB07 AB08 AB09 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 Signal Vpp SYS DATA10 SYS DATA11 SYS ARTRY SYS DATA57 SYS TS SYS DATAS58 SYS DATA1 Vpop SYS_DATA46 SYS DATAO G INTD VDD PLN RTC CLK P TRDY VDD SYS_ADDR17 SYS_TSIZ2 SYS_TBST NODLK SYS TT1 SYS DATAP7 SYS TEA SYS DATA12 RESERVED7 SYS DATA36 SYS DATA9 SYS DATAS SYS DATA39 Ground SYS DATA40 SYS DATA6 SYS DATA2 SYS DATAS5 SYS_DATA54 SYS_DATA47 P_IRDY SYS_GBL SYS_ADDRPO Pin AB23 AB24 AB25 ACO1 ACO2 ACOS AC04 ACO5 ACO6 ACO7 ACO8 ACO9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 ADO1 ADO2 ADOS AD04 AD05 ADO6 ADO7 ADO8 ADO9 AD10 AD11 IBM Dual Bridge and Memory Controller Signal SYS_ADDR29 SYS_ADDR28 SYS_ADDR27 No Connect DLK Ground SYS_DATAP6 SYS_SHD SYS_DATA34 Ground SYS_DATA33 SYS_DATA27 SYS_DATA25 Ground SYS_L2_HIT SYS_DATA59 SYS_TA Ground INT1 SYS DATAS51 SYS DATA42 Ground SYS DATA3 G_REQ2 SYS_ADDR13 Ground SYS_ADDR30 No Connect Vpp Ground SYS DATAP5 SYS DATAP4 Vpop SYS_DATA18 SYS DATA23 SYS DATA24 VDD SYS_DATA26 SYS_DATA63 Pin AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AE01 AE02 AE03 AE04 AE05 AE06
95. DIMM CPU etc Reserved Reserved Reserved Global Control Register user Global Status Register user Transfer Control Register user Transfer Status Register user Transfer PCI Address Register user Transfer Write Back Address Register user Transfer Translated Address Register user Global Control Register priv Global Status Register priv Transfer Control Register priv Transfer Status Register priv Transfer PCI Address Register priv Transfer Write Back Address Register priv Transfer Translated Address Register priv Reserved Device Characteristics Register Device ID Register All bits can be read Only bits 4 31 can be written All bits can be read Only bits 0 3 can be written Four beat burst read operations allowed to this address space Single byte writes only Not decoded by system logic Range that IBM Dual Bridge and Memory Controller responds to is programmable Page 126 126 126 126 126 126 126 128 129 130 131 132 133 135 136 137 130 131 132 133 135 136 137 138 139 Notes 6 26 2000 IBM Dual Bridge and Memory Controller System Registers List Page 3 of 3 Address Name Use Page Notes x FF20 0018 BAR Base Address Register 140 See p 33 x FF20 0020 to xFF20 OFFF Reserved Device Specific Configuration Space x FF20 1000 PCIENB PCI BAR Enable Register 141 X FF20 1004 to x FFDF FFFF Reserved BOOT ROM x FFEO 0000
96. DL2 0418 G CFGO 0H11 Ground 0B24 RESERVED6 0P13 G ADL3 0G20 G CFG1 0H12 Ground 0C03 FLASH_OE 0CO8 G_ADL4 OF21 G CFG2 OF12 Ground 0C07 FLASH_WE 0K19 G_ADL5 0G21 G_DEVSEL 0E12 Ground 0C11 G ACK64 0G14 G ADL6 0H21 G FRAME 0C12 Ground 0C15 G_ADHO 0D18 G ADL7 0J25 G GNTO 0A13 Ground 0C19 G_ADH1 0H15 G ADL8 0H22 G_GNT1 0E13 Ground 0C23 G_ADH2 OF17 G_ADL9 0H24 G GNT2 0B11 Ground 0D13 G_ADH3 0J15 G_ADL10 0L16 G GNT3 0D12 Ground 0G03 G_ADH4 OE16 G_ADL11 0G25 G_GNT4 0J11 Ground 0G07 G ADH5 OE15 G ADL12 0G24 G GNT5 OF18 Ground 0G11 G_ADH6 0E18 G ADL13 OF25 G GNT6 0W14 Ground 0G15 G_ADH7 0J16 G ADL14 OF24 G GNT7 ON21 Ground 0G19 G_ADH8 0G16 G ADL15 0D24 G IDSEL 0U19 Ground 0H25 G ADH9 0H16 G ADL16 0B22 G_INTA AE13 Ground 0K21 G_ADH10 0B20 G_ADL17 0A20 G_INTB 0A10 Ground OLO3 G_ADH11 0B18 G ADL18 0C18 G INTC 0C13 Ground 0LO7 G ADH12 0A21 G ADL19 0C17 G INTD AA20 Ground OL11 G ADH13 OF19 G ADL20 OF14 G_IRDY 0A12 Ground OL14 G_ADH14 0G18 G_ADL21 OF15 G LOCK 0G13 Ground 0L15 G ADH15 0H17 G ADL22 0E14 G PAR 0H23 Ground 0L19 G ADH16 0D21 G ADL23 0B14 G PAR64 OE25 Ground 0L23 G ADH17 OE20 G ADL24 0H13 G PERR 0A22 Ground ONO4 G_ADH18 0K16 G ADL25 0B15 G REQO OF11 Ground ON13 G ADH19 0E22 G ADL26 0D15 G REQ1 0D11 Ground ON22 Page 18 of 209 6 26 2000 Signal Pins Sorted by Signal Name Page 2
97. Description IBM Dual Bridge and Memory Controller Specifies the length of a device s burst period in 0 25 usecs Device has no specific requirements and therefore always Page 55 of 209 CPC710 133 IBM Dual Bridge and Memory Controller Maximum Latency MAXLT Reset Value x 00 Address x 3F Access Type Read Only Maximum Latency v Y 7 6884 8 2 1 0 Bit s Description Specifies how often the device needs to gain access to the PCI bus in 0 25 us Device has no specific requirements and PM therefore always responds with x 00 Page 56 of 209 6 26 2000 Bus Number BUSNO Reset Value x 00 Address x 40 Access Type Read Write Bus Number v Y 7 6 5432 1 0 Bit s Description P9 uration cycles directed to this bridge After reset this register contains a value of x 00 6 26 2000 IBM Dual Bridge and Memory Controller Contains the assigned bus number for this bridge Device uses this number to determine what action to take for config Page 57 of 209 CPC710 133 IBM Dual Bridge and Memory Controller Subordinate Bus Number SUBNO Reset Value x 00 Address x 44 Access Type Read Write Subordinate Bus Number v Y T 8 8 4 8 2 1t 9 Bit s Description 7 0 Specifies the largest bus number beneath this bridge After reset this register contains a value of x 00 Page 58 of 209 6 26 2000 Disconnect Counter DISCNT Reset Value x 00 Ad
98. Dual Bridge and Memory Controller Diagnostic Register AVDG Reset Value x 0000 0000 Address x FF00 1170 Access Type Read Write c c o 9 o o D 255 E 255 E Q 2250 Cg2b0 oO o Z o GO x x Z uU E 8g ooOO g E oO 8 a88a 8 28a 8 OoO2zra lt lt OoO2zra ez 9 N N N N N tr wt wt t 2 CR Xy GRO 82 Soy see NS o MA C ECCE LEE E E o 2 99 9 9 Reserved 9 9 Q Q QD Reserved 2 Reserved yb v4 iv vvv Y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description PCI 32 Counter Disable 0 0 TRDY IRDY DISCNT Counters are not activated The MSB is always at 1 he DISCNT counter is programmable see Disconnect Counter DISCNT on page 59 1 TRDY IRDY DISCNT Counters are ACTIVATED PCI 32 Master Abort 1 0 Window of Master Abort is reduced to one cycle avoid parasitic master abort detection 1 Window of Master Abort is not reduced PCI 32 Target Abort 2 0 Device detects Target abort The Frame output is taken 4 Device never detects Target Abort but retry indefinitely accesses PCI 32 DEVCNT 3 0 Stop the counter down when devsel is detected d Do not stop the counter down PCI 32 Access Completion 4 0 The completion is activated when device is master and not during external exchange 1 The completion appears when the data is not the last one 5 7 Reserved PCI 64 Counter Disable 8 0 TRDY IRDY DISCNT Counters are not activated the MSB
99. Dual Bridge and Memory Controller Connectivity Configuration Register CNFR The CNFR register described below is used to support the initialization and configuration of devices on the 60x bus This register provides the unique setup signal required to insure that only one device will respond to configuration addresses at a time Software must adhere to the following restrictions for configuration Awrite to the CNFR register must be followed by a SYNC operation or a read of the register Software must issue a read to the Device Characteristics Register DCR at x FF20 0000 to determine if a device is present If software receives a x F000 0000 response from the DCR read this indicates that no device is present and therefore no other configuration registers should be accessed Access to other configurations regis ters will result in a bus time out condition Reset Value x 0000 0000 Address x FF00 000C Access Type Read Write o E D c oO wi iL E z S 5 B 3 t t 8 Reserved S 1 3 Vox 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description Configuration Enable 0 0 Inactivate all SYS_CONFIG n signals 1 Activate appropriate SYS CONFIG n as described in bits 30 31 1 29 Reserved Configuration Field 00 SYS CONFIGO SYS CONFIGO signal driven active 30 31 01 SYS CONFIG1 SYS_CONFIG1 signal driven active 10 SYS CONFIG2 Configuration access
100. ED3 O External Pull Up recommended RESERVED4 l Pull Up External Pull Up recommended RESERVED5 l Pull Up External Pull Up recommended RESERVED6 O External Pull Up recommended RESERVED7 l Pull Up External Pull Up recommended RESERVED8 O External Pull up recommended 6 26 2000 Page 31 of 209 IBM Dual Bridge and Memory Controller Page 32 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Registers The registers for the device are specified in three regions Except for the Standard PCI Configuration Space which uses indirect addressing all the registers can be defined in the upper 16 MB of the 4 GB address range Standard PCI Configuration Space register number x 00 to x 68 There are two sets of PCI Configuration Space registers one for each PCI bridge These registers are accessed by a R W of the CFGD with the address of the target register of the corresponding PCI bus in the CFGA Configuration Address register which specifies the register number and operation to perform The table Standard PCI Configuration Register List on page 40 describes the Specific PCI Host Bridge Reg isters supported by the device The register PSBAR can be accessed and configured by the CPU or the PCI 64 bus through configuration cycles Each of these registers is described in detail on pages 40 through 63 Specific PCI Host Bridges Space BAR x 000F 6110 to BAR x 000F 9810 There are two almost identical sets of r
101. Enable 0 Disabled 9 d PCI Bridge issues fast back to back transfers without regard to which target is being addressed providing that the previous transaction was a write Note This bit should be set if all slaves on the PCI bus support this capability SERR Enable 8 0 PCI Bridge will not assert P G SERR upon detecting an error 1 PCI bridge will assert P G SERR for PCI address parity error 7 Add Wait States Read Only Always returns 0 Device does not support address data stepping PCI Bus Parity Enable 6 0 Device will disable all parity checking on the PCI bus f Device will detect and report parity errors on the PCI bus 5 VGA Palette Snoop Read Only Always returns 0 Device is not VGA compatible Memory Write amp Invalidate Command Enable 4 0 Device does not generate this type of cycle 32 byte transfers use the Memory Write command 1 Device generates this cycle as a master for any 32 byte transfer 3 Special Cycle Enable Read Only Always returns 0 Device will not respond to Special Cycle commands Page 42 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Description Bus Master Enable 0 PCI Bridge master capability is disabled 1 PCI Bridge performs as a PCI master for accesses to its address spaces Enable Memory Space Slave 0 PCI Bridge will not respond to memory accesses on the PCI bus 1 PCI Bridge will respond to memory accesses on the PCI bus Enable I O Space Slave 0 PCI Bridge will not respond to IO a
102. G DATA Register CFGD Reset Value x 0000 0000 Address BAR x 000F 8010 Access Type Read Write CFGD 4 Y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o Bit s Description Virtual 32 bit Register When this Little Endian register is accessed in Read or Write the device initiates a PCI Config 31 0 uration Read or Write cycle of external PCI devices the address of which is provided by the PCI CONFIG_ADDRESS Register 6 26 2000 Page 81 of 209 CPC710 133 IBM Dual Bridge and Memory Controller System Address Space SIZE for PCI PSSIZE This is the same definition for 32 bit PCI and 64 bit PCI Reset Value Address Access Type Reserved x 0000 0000 BAR x 000F 8100 Read Write Reserved System Address Space Size vv Y 0 1 2 3 4 5 4 lt Enable Memory or I O Space v 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s 0 6 24 31 Reserved Enable Memory Or IO Space 0 1 Memory Space IO Space Reserved System Address Space Size xFF xFE xFC x F8 x FO x EO x C0 x 80 x 00 Page 82 of 209 16 MB 32 MB 64 MB 128 MB 256 MB 512 MB 1 GB 2 GB 4 GB Description 6 26 2000 IBM Dual Bridge and Memory Controller System Base Address Register BARPS The definition is the same for 32 bit PCI and 64 bit PCI
103. Grant Active To Frame Active Time out Disable PCI Master Address Translation Disable e e e Q o x o p amp E S 8 E 8 o Q e D 9 5 E gt o o J E 5 a 3 D c o r tc 5 Z d e x o en n a 5 1 a X IO IO ao Reserved vy V 8 Y 4 e i 0 1 3 5 6 7 8 9 10 11 12 13 14 15 16 17 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description Parking Control 0 1 Ox Bus is parked on device 10 MRU algorithm for parking 11 Park specified ARB level below in bits 5 7 Deadlock Avoidance Signal Selection PCI 32 Bridge Only To avoid deadlocks with PCI ISA bridges on the PCI 32 bit bridge the bridge must indicate to the device that a PCI access is about to occur before the P GNT signal is activated Any posted PCI 32 bit bus transfers must be flushed prior to activating the P GNT signal and any accesses to the PCI 32 bit bus must be disabled after the GNT is given and con tinue disabled until the PCI access is complete and the P GNT signal is removed The PCI ISA bridge must not grant 2 the secondary ISA bridge until device has activated the P GNT signal Device provides two input signals for this purpose that are selectable with this bit 0 Selects the P REQ 5 signal P GNT 5 indicates buffers flushed and any PCI Transfers will be disabled on the 60x bus until the P REQ 5 signal is deactivated 1 Selects the P REQ signal P REQ indicates buffers flushed and any PC
104. I Transfers will be disabled on the 60x bus until the P REQ signal is deactivated Machine Check Processor If an error is detected as a target during a PCI access operation the device generates a Machine Check to the proces 3 Sor specified by the value of this register 0 PCI bridge logic machine checks processor 0 1 PCI bridge logic machine checks processor 1 PCI Master Address Translation Disable 0 PCI Master addresses are always translated before being presented to system memory see Base Address Register BAR on page 140 1 PCI Master addresses are NOT translated and sent directly to system memory 6 26 2000 Page 71 of 209 CPC710 133 IBM Dual Bridge and Memory Controller Bit s Description 5 7 ARB Level To Park Contains the encoded arbitration level to park when bus is idle level 000 is for agent 0 level 001 for agent 1 and so on IRDY Count 8 11 Contains the number of PCI clocks times 8 that device waits before detecting a time out condition A value of zero dis ables the time out check TRDY Count 12 15 Contains the number of PCI clocks times 8 that device waits before detecting a time out condition A value of zero dis ables the time out check PCI Queue Enable 16 0 PCI logic does not queue requests 1 PCI logic queues up to two operations PCI ISA Bridge Deadlock Avoidance Disable 0 PCI ISA Bridge is present in the system Therefore device will 1 NOT deactivate P GNT 5 even if other REQs become ac
105. Internal SYS_TA VO Pull up Internal SYS_TEA VO Pull up Miscellaneous Signals SYS_MACHKO o SYS MACHK1 CHKSTOP Oo Open Drain SYS HRESETO o SYS_HRESET1 SYS SRESETO o SYS_SRESET1 SYS_TBE O Internal POWERGOOD l Pull up INT1 0 INT2 O GPIOO GPIO1 GPIO2 y o LK O NODLK l Page 26 of 209 Description Data Parity Bus Represents one bit of odd parity for each of the eight bytes of the data bus Odd parity means that an odd number of bits including the parity bit are driven high The signal assignments correspond to the following DP 0 D 0 7 DP 4 D 32 39 DP 1 D B 15 DP 5 D 40 47 DP 2 D 16 23 DP 6 D 48 55 DP 3 D 24 31 DP 7 D 56 63 Transfer Acknowledge Output Indicates a single beat of data transfer between device and a master on the 60x bus For read transfers indicates the data bus is valid with read data and the master must latch it in For writes indicates device has latched in write data from the data bus Device asserts the signal for each beat in a burst transfer Input Indicates a single beat of data transfer has occurred The device arbiter uses this signal and the address transfer attribute signals to determine the end of the data bus tenure Transfer Error Acknowledge Output Indicates device has detected an error condition and that a machine check exception is desired Assertion of this signal terminates the current data bus tenure Device can be set up to transform any SYS TEA
106. MPIC Not required POWERGOOD IDSEL7 1 See External IDSEL Signal Logic for PCI 32 on page 193 for description of these signals Address Map There are two PCI bus bridges in the device Both implement the register maps listed in the following table The PCI Host Bridge Standard configuration space is Little Endian PCI Bus Bridge Configuration Address Map Area Real Address Name Note Use Page x FF20 0000 DCR 1 Device Characteristics Register 138 Ed x FF20 0004 DID 1 Device ID Register 139 EM x FF20 0018 BAR Base Address Reg for Bridge Registers 140 x FF20 001C to x OFFF Reserved Device Specific x FF20 1000 PCIENB PCI BAR Enable Register 141 Configuration Space X FF20 1004 to x 1FFF Reserved 1 Read Only Register write is ignored 6 26 2000 Page 187 of 209 IBM Dual Bridge and Memory Controller System Standard Configuration Registers System Standard Configuration Registers can only be accessed with 60x bus configuration cycles directed to a specific PCI bridge Both of the device s PCI bridges must be configured before any PCI configuration cycles can be issued The registers provide a mechanism for firmware to identify the PCI bridge and the DCR and DID registers and assign a 1 MB address space in the system memory map for the location of the PCI bridge facilities BAR register For detailed descriptions of these registers refer to the following Device Characteristics Register DCR on page 138 Device ID
107. O00O00O00000000O0 OOOOOOOOOOOOOOOOOOOOOOOOO 01000000000000000000000000 Decoupling Capacitance 47nF Device d Ceramic Substrate 9 0mm x 9 05mm C4 Encapsulant fillet 1 05mm t i 2 78mm gt lt 0 87mm k 1 27mm 0 9mm All measurements are in millimeters unless otherwise noted Drawing is not to scale 6 26 2000 Page 227 of 209 IBM Dual Bridge and Memory Controller References 1 PC SDRAM Specification Revision 1 63 October 1998 Intel 2 PCI Local Bus Specification Revision 2 1 June 1st 1995 PCI Special Interest Group Page 228 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Revision Log Revision Date Contents of Modification 09 08 99 Initial release 00 release 1 0 PCI 64 REQ setting to disable arbiter XATS removed P ISA MASTER must be tied to GND to be inactive Initialization PowerUp at time 0 SOM amp SOI2 space access unpredictable results See UCTL Register ATAS init programing value for PowerPC750 Memory Cache coherency Firecoral replaced by PCI ISA bridge Boot ROM data on PCI AD 8 15 Access to SDRAM from PCI or CPU performed in rotating priority MADDRO LSB split in MADDRO ODD amp MADDR1 EVEN G_CBE 0 7 amp P CBE 0 3 active low CMND Reg reset values reversed MCER Reg extended code bank for 4 amp 8 MB PCI to PCI transfers unpredictable results PPSIZE amp BARPP amp PPBAR Regs removed POWERGOOD Active high
108. OCOUDCLECOUC OCC 6 616 2 2 OL O OSOOSOOOSODODOOODOSOCOOSOOSO QOCOOCODOOOOCQ OO XODOOOUDOOOC QU OO eOoooeooeeocooeooo eooo0e 00 OOOOOOOOOOSSOSOOOOOODOOOO OS OOOSODOOSOOOODOSOOOSOOOSO OOOOOOODOSDOSOSOSOOOODOOOOO OOeoooeooeeocooeoooeooo0eo00o OOOOOOOOOOOSSOOOOOOOOOODOO OSOOSOOOSODOSOODOSOOOSOOSO CQOQDODCOUODCOCGOCOLQCODCGOQOCGQOCUDCOLCGC QU OOe eOoo0o0 eoooeocoo eooo eooo0e o00 OOOOOOOOOOOOSOOOOOOOOOOOO OSOOSOOOSODOOOOODOSOOO0SOOSO DOP DEEDS TEDD 6 t LL eo oeoooeoooeocooeoooeoooeoce SOOOSOOOSOCOOSOOOSOCOOSOOOS oOSe00o0000000000O00000000e eS 0 AE AD AC AB AA OY OW OV OU OT OR OP ON OM OL OK OJ OH OG OF OE OD OC OB OA No Connect SS Von Ground C VO Signal Pin Summary 6 26 2000 Pin Type Number of Pins Vpp 62 Ground 54 Test Pins 20 No Connect 8 Total Module Signal I Os 480 Total Pins 625 E hv 13 17 19 Page 13 of 209 IBM Dual Bridge and Memory Controller Signal Pins Sorted by Pin Number Page 1 of 4 Pin 0A01 0A02 0A03 0A04 0A05 0A06 0A07 0A08 0A09 0A10 0A11 0A12 0A13 0A14 0A15 0A16 0A17 0A18 0A19 0A20 0A21 0A22 0A23 0A24 0A25 0B01 0B02 0B03 0B04 0B05 0B06 0B07 0B08 0B09 0B10 0B11 0B12 0B13 0B14 Signal Locator VDD No Connect WE2 MUX_CLKEN1B MADDR9 MADDR7 MUX_CLKEN2B MUX OEB G INTB G RST G IRDY G GNTO G STOP G ADL31 G CBE7 G CBE6 G CBE3 G CBE1 G ADL17 G ADH12 G PERR No Connect VoD Ground Vpp Ground SDCKE7 WE1 VDD MADDR10 MADDR8
109. R CNFR RSTR SPOR x FF00 0000 4 GB 16 MB x 0000 0000 0 31 Standard PCI Configuration Space Register number is specified in the CFGA Configuration Address VID SPI HDRT MINGNT RETRY DEVID SUBC PSBAR MAXLT DLKRETRY CMND CLASS BUSNO STAT CSIZE INTLN SUBNO IT ADD SET RID LTIM INTPIN DISCNT INT RESET PCI 64 Register x128 PCI 32 Register x 68 Register x 00 31 0 Note BOXED registers are key registers that define PCI bus configuration and register settings Page 34 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Standard PCI Configuration Register List Relative Address Name Use Page Notes 00 to 01 VID Vendor ID Register 41 1 02 to 03 DEVID PCI Device ID Register 41 1 04 to 05 CMND Command Register 42 06 to 07 STAT Status Register 44 2 08 RID Revision ID 46 1 09 SPI Standard Programming Interface 46 1 00A SUBC Sub class Code 47 1 0B CLASS Base Class Code 47 1 0C CSIZE Cache Line Size 48 1 oD LTIM Latency Timer 49 0E HDRT Header Type 50 1 OF BIST Built In Self Test 51 10 PSBAR System Base Address Register for PCI 64 52 4 3C INTLN Interrupt Line 53 3D INTPIN Interrupt Pin 54 3E MINGNT Minimum Grant 55 1 3F MAXLT Maximum Latency 56 1 40 BUSNO Bus Number 57 41 SUBNO Subordinate Bus Number 58 42 DISCNT Disconnect Counter 59 50 RETRY Retry Counter 60 s iam eo p ug 64 IT ADD SET Set PCI 64 Inter Processor INT1 Interrupt 62 4 68 IN
110. Reserved Disable Page Mode 30 0 Memory controller will perform fast page accesses for back to back operations if appropriate 1 Memory controller will perform fast page access only within a burst operation It will NOT perform fast page accesses for back to back bursts even if they occur to the same RAS page Disable Queue Same Page Override 31 0 Memory queue ordering can be overidden if an operation is to the same page 1 Memory queue always processed in order received 6 26 2000 Page 123 of 209 CPC710 133 IBM Dual Bridge and Memory Controller Memory Error Status Register MESR This register provides error status information on memory errors In order to log additional errors software must clear the register by writing zeros throughout Reset Value x 0000 0000 Address x FF00 1220 Access Type Read Write co E o E 2 S 5 o o S228 Se Es E u i 3 a op o Q o6 2 o S8 E 223 8 2 Bn 26 Reserved 0 tlidy vox y 0 1 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description Double Bit Error Flag 0 0 No Error 1 Double Bit ECC error occurred Single Bit Error Flag 1 0 No Error 1 Single bit ECC error occurred Address Error Flag 2 0 No Error 1 Address error occurred Overlapped Memory Extents 3 0 No Error As An access occurred to an address that is mapped in two different memory configuration extents 4 23 Reserv
111. Reset Value x 0000 0000 Address BAR x 000F 8120 Access Type Read Write Reserved System Base Address v E Y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 23 Reserved 24 81 System Base Address Contains the upper bits of the system Base address that Memory is mapped to 6 26 2000 Page 83 of 209 CPC710 133 IBM Dual Bridge and Memory Controller System Base Address Register for PCI 32 PSBAR Only the PCI 32 bit bridge has this register Reset Value x 0000 0000 Address BAR x 000F 8140 Access Type Read Write Reserved System Base Address for PCI 32 v vov Y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 23 Reserved 24 81 System Base Address for PCI 32 Contains the upper bits of the System Base address that memory is mapped to Page 84 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Bottom of Peripheral Memory Space With Potential Deadlock BPMDLK Reset Value x 0000 0000 Address BAR x 000F 8200 Access Type Read Write Reserved Bottom of Peripheral Memory Space 4 vov v 012345 6 7 8 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description Bottom of Peripheral Memory Space Contains the bottom address for the CPU to PCI MEMORY access with poten tial deadlock 10 31 Reserved 6 26 200
112. Reset when low SIORO amp SIOR1 registers controls PRES OEO amp PRES_OE1 signals External Mux control signals renamed Temperature range 20 to 105 C Read and write Waveforms for the PCI 64 66MHz access to the memory Typical Register Setup sequence P LOCK amp G LOCK are Input only LOCK on PCI busses not fully supported MCERO to 7 address corrected 12 17 99 Release 1 1 PCI are 3 3V I OS with 5V compliance PCI 64 INTA B C D Signals are Outputs 3 I Os GPIO1 2 3 Inputs G LOCK amp P LOCK are reserved 6 26 00 JTAG TDO amp TMS Semaphore Register PSEM 60 is reserved Endian decription enhanced DMA operation enhanced SIOA1 amp SIOA2 space now reserved 6 26 2000 Page 229 of 209 IBM Dual Bridge and Memory Controller Page 230 of 209 6 26 2000
113. SDRAM Memory READ 32 Bytes from the SDRAM by a PCI Master on PCI 64 66MHz bus cucine AALAN A Ahnen JU JU ru utn Tut UU i ooa pO E 6 8 SDRAM DH 12 a al SDRAM DL BEES mE 75 MADDR RAS aa ee 3 a E x 3 E u s d 1 1 1 Rea 1 1 1 1 1 1 1 1 1 1 CAS TEM a Precharge d dos 4 0h a WE i UD CE S EOD TATE MEE CES GUCKEN EC GU CE US CKE l iode o6 ek t SENE EN bie i 66MHz Clock LULU LU UT CBE 7 0 00 Z 00 7 M Tc UE 00 Z Zz 00 Ifffff PCI AD 63 32 fffff 32 bit Word 1 w loan e PCI_ADJ 31 0 Add 32 bit Word 2 G FRAME i ee NE TEE DA lo AddH G_IRDY G TRDY ww xc 39x xe mE OE ase tae bbs ee ces heer ee E e v9 49 s ox x 930 s x o 338 o x a a o3 o 1 Bg Note 1 2 3 refers to 1st 2nd third 32 bit word READ the SDRAM from a PCI Master on PCI 64 6 26 2000 Page 217 of 209 IBM Dual Bridge and Memory Controller Write of 32 Bytes in the SDRAM from a PCI Master on the PCI 64 66MHz bus CLK100MHz TULIN rrr nuu rundum uut
114. SYS DBG when DBB is active The arbiter monitors transaction sizes to determine the end of a data bus tenure and waits until the previous data tenure is com plete before issuing a SYS_DBG to the next master Note QDGB can only be negated by an SYS ARTRY of the address tenure associated with the QDBG data bus tenure Therefore once the SYS ARTRY window has passed for an address tenure the data bus tenure associated with that address tenure cannot be negated by SYS ARTRY from a subsequent address tenure High Impedance After SYS TEA Masters and slaves must execute all data bus signals as high impedance within two bus clocks from SYS TEA assertion SYS DRTRY Assertion 6 26 2000 Page 155 of 209 IBM Dual Bridge and Memory Controller Slaves are not allowed to drive SYS DRTRY active The device arbiter does not receive SYS DRTRY Slave Data Bus Determination To determine whether the data bus is currently in use by a previous address tenure a slave must sample DBB from its master during the TS active cycle If DBB is active the slave must wait for DBB to go inactive in a one level pipeline mode for at least one cycle before providing read data or accepting write data SYS L2 Hit Assertion For the device to determine whether an addressing error has occurred all slaves on the 60x bus must assert SYS L2 HIT when selected by an address on the 60x bus Warning The SYS L2 HIT signal is subject to timing constraints Page 156 of 209 6 26
115. TA26 0U17 Vpp 0W06 SYS DBGO OP15 P CFG2 oT04 DM 0U18 P GNT5 0WO07 Ground 0P16 Vpp OTO5 MDATA25 0U19 G IDSEL owos SYS DATAP1 0P17 Vpp OTOG DI2 0U20 SYS_ADDRP1 owog SYS DATAP3 0P18 P CBEO 0TO7 MDATA3 0U21 Vpp owi0 SYS DATA17 0P19 P_REQ2 OTOB MDATA20 0U22 P ADL9 0OW11 Ground OP20 P ADL1 OTO9 MDATA19 0U23 P SERR 0W12 SYS DATA38 0P21 P REQM 0T10 MDATA27 0U24 Vpp 0W13 SYS_DATA61 OP22 P ADL2 OT11 Ground 0U25 P CBE1 0W14 G GNT6 0P23 P REQO 0T12 P REQ6 OVO1 MDATA24 0W15 Ground 0P24 P ADL6 0T13 Vpp 0VO2 MDATA23 0W16 SYS ADDR3 0P25 P ISA MASTER 0T14 CE TRST 0V03 MDATA4 0W17 SYS ADDRP3 ORO1 MDATA5 0T15 Ground 0VO4 MDATA17 owi8 SYS ADDR9 Page 16 of 209 6 26 2000 Signal Pins Sorted by Pin Number Page 4 of 4 Pin Signal OW19 Ground ow20 SYS_ADDR24 ow21 SYS ADDR10 0W22 P STOP OW23 Ground ow24 SYS ADDR20 0W25 SYS_ADDR21 0YO SYS BGO 0YO2 SYS BG1 0YO3 MDATA34 0YO4 SYS MACHKO 0YO5 MDATA21 0YO6 SYS TT2 0YO7 SYS DATA19 0YOB8 O GPIO2 0YO9 RESERVED8 0Y10 SYS_SRESET1 0Y11 SYS_DATA35 0Y12 TDO 0Y13 Vpp 0Y14 SYS TBE 0Y15 SYS DATA41 0Y16 SYS SRESETO 0Y17 SYS DATA49 0Y18 P FRAME 0Y19 SYS ADDR1 0Y20 SYS ADDRP2 0Y21 SYS ADDR23 0Y22 SYS ADDR15 0Y23 P ADL5 0Y24 SYS ADDR18 0Y25 SYS ADDR19 AAO1 SYS TSIZO AA02 Vpp AA03 Vpp AA04 SYS_TT4 AA05 Vpp AAO6 SYS TTO AA07 SYS
116. TR 2 of the Connectivity Reset Register RSTR Page 98 for PCI 32 or bit RSTR 3 for PCI 64 is forced to zero or from a Software Power On Reset Control Register SPOR Page 99 reset Reset Value x 0000 0000 Address BAR x 000F 6110 Access Type Read Only PCI To Memory Error Address Y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description PCI To Memory Error Address 31 f Weg Contains the address present on the PCI bus when an error occurs during a PCI transfer 6 26 2000 Page 65 of 209 CPC710 133 IBM Dual Bridge and Memory Controller PCI Diagnostic Register PCIDG This register contains two mode bits that are used for special modes of operation Reset Value PCI 32 x 4000 0000 PCI 64 x C000 0000 Address BAR x 000F 6120 Access Type Read Write 2 o Q o G S m Ww o g ii 5 lt i B Reserved Must Leave at 0 vov ov Y 01 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 64 bit Mode Enable only for PCI 64 0 0 Operates as a 32 bit bridge G REQ64 and G_ACK64 never activated by device 1 Operates as a 64 bit bridge G_REQ64 always activated for device initiated transfers DMA Pipeline Enable 1 0 DMA transfers are NOT pipelined internal to device Results in significantly lower bandwidth to PCI bus 1 DMA transfers are pipelined internal to device for maximu
117. T_RESET Reset of INTA INTB INTC INTD on the PCI 64 63 4 Read Only Register write is ignored Writes will only reset bits in this register write data interpreted as 1 reset 0 ignore Only for PCI 32 Only for PCI 64 RON 6 26 2000 Page 35 of 209 CPC710 133 IBM Dual Bridge and Memory Controller Specific PCI Host Bridge registers Real Address BAR x 000F 6110 BAR x 000F 6120 BAR x 000F 7700 BAR x 000F 7800 BAR x 000F 7810 BAR x 000F 7EFO BAR x 000F 7F20 BAR x 000F 7F30 BAR x 000F 7F40 BAR x 000F 7F60 BAR x 000F 7F80 BAR x 000F 7FCO BAR x 000F 7FDO BAR x 000F 7FEO BAR x 000F 8000 BAR x 000F 8010 BAR x 000F 8100 BAR x 000F 8120 BAR x 000F 8140 BAR 4 x 000F 8200 BAR x 000F 8210 BAR x 000F 8220 BAR x 000F 8230 BAR 4 x 000F 8300 BAR 4 x 000F 8310 BAR x 000F 9800 BAR x 000F 9810 Only for PCI 32 Only for PCI 64 Bom Page 36 of 209 Name PSEA PCIDG INTACK PIBAR PMBAR CRR PR ACR MSIZE IOSIZE SMBAR SIBAR CTLRW CTLRO CFGA CFGD PSSIZE BARPS PSBAR BPMDLK TPMDLK BIODLK TIODLK IT ADD RESET INT SET CSR PLSSR Read Only Register write is ignored Little Endian registers Use PCI Slave Error Address PCI Diagnostic Register Interrupt Acknowledge Cycle PCI Base Address for I O PCI Base Address for Memory Component Reset Register Personalization Register Arbiter Control Register PCI Memory Address S
118. The device will activate resets to all processors and I O devices Reset Value x 0000 0000 Address x FF00 00E8 Access Type Write Only Generate Hard Reset v Y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Definition Generate Hard Reset 0 31 eee A write to this register will initiate a power on reset 6 26 2000 Page 99 of 209 CPC710 133 IBM Dual Bridge and Memory Controller Specific System Registers Space Universal System Control UCTL This register tions is used to enable address ranges to be decoded by the CPC710 and processor related opera Reset Value x 0008 0080 Address x FF00 1000 Access Type Read Write 2 a s c Lu eo o c ce o O0 a 2 D E E as m g q 3 S LLI i S o 8 s u o o 0 5C 90 7o 9 o o 2 5 0 o o 8 o p b o o 9 gt z z LF gez m eg eg uc O oO X d oO oO oO ow S 9 9 8 929 p E E a R EC Level 8 amp B a Resource amp cf eserved eve yyy ete v4 4 s Vos Y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 Reserved 1 Reserved R W 2 3 Reserved R W Must be left to 0 Boot Flash Write Disable 4 0 Indicates that writes are allowed to Boot FLASH space 1 Writes to Boot FLASH space are inhibited DMA Transfer Address Space Enable 5 0 Accesses to DMA Address R
119. Transfer Control XSCR scssi ainai en nnn nen in nennen sinere nnne ees 132 DMA Transfer Status XSSR ieri esee trei iece nt edie teed tee dee Duc t de suce eve Ede tes 133 DMA Transfer PCI Address XPAR sse eene eene en nnns nennen nsn enne 135 DMA Transfer Write Back Address XWAR sese enne enne 136 DMA Transfer Translated Address XTAR sess enne nn nnne nns 137 System Standard Configuration Registers Space eres 138 Device Characteristics Register DCR sss eene nnne enne 138 Device ID Register DID ne cre mte nh pec werte eee tite cee ete at UR aad Ev D DERE 139 Base Address Register BAR c s ccceeesseeceeeeeeeeeeeeeeaeeeeeeeeaeaeeeessaaeaeeeeesaeeeeeeeneaeeeeeenneaeeesaes 140 Device Specific Configuration Space sse nnne nnne nnne nnns 141 PCI BAR Enable Register PCIENB sssini n a E nn tenente intense nns 141 Addressing MOEN M iaai aai 143 LOBRICCER La rm E i 143 CPU to PCI Addressing Model eee ce ener e eee ei knna Aaaa NE 144 PREP and FPHB MOSS iustitie ttr aduana tud cv Ph a t d RV Ea esp ave Dn dnd Cu Dea nare a RR TERR 144 Peripheral I O Address Translation ceccceceeseeeeceeeeeeneeeeeeseeeeeeeeeaaeeeeeesaeeeeeeseaaeeeeeeseneeeeeeseeeneees 145 PCIto System Memory E 146 PowerP
120. YS BR2 SYS BR3 SYS CLK SYS CONFIGO SYS_CONFIG1 SYS_DATAO SYS_DATA1 SYS_DATA2 SYS DATA3 SYS DATA4 SYS DATAS SYS DATA6 SYS DATA7 SYS DATA8 SYS DATA9 SYS DATA10 SYS DATA11 SYS DATA12 SYS DATA13 SYS DATA14 Pin 0V25 0Y21 0W20 0V19 0V18 AB25 AB24 AB23 AC24 0V23 AB22 0U20 0Y20 0W17 AA12 0YO01 0Y02 AE14 AE12 0K15 0K17 0K20 ON12 ON14 AA19 AA16 AB16 AC20 0V14 AB17 AB15 AD15 AB11 AB10 AA10 AA11 ABO7 AE08 AE07 6 26 2000 Signal Pins Sorted by Signal Name Page 4 of 4 Signal SYS DATA15 SYS DATA16 SYS DATA17 SYS DATA18 SYS DATA19 SYS DATA20 SYS_DATA21 SYS_DATA22 SYS_DATA23 SYS_DATA24 SYS_DATA25 SYS_DATA26 SYS_DATA27 SYS_DATA28 SYS_DATA29 SYS_DATA30 SYS_DATA31 SYS_DATA32 SYS_DATA33 SYS_DATA34 SYS_DATA35 SYS_DATA36 SYS_DATA37 SYS_DATA38 SYS_DATA39 SYS_DATA40 SYS_DATA41 SYS_DATA42 SYS_DATA43 SYS_DATA44 SYS_DATA45 SYS_DATA46 SYS_DATA47 SYS_DATA48 SYS_DATA49 SYS_DATA50 SYS DATAS51 SYS_DATA52 SYS_DATA53 SYS_DATA54 6 26 2000 Pin AA08 0U10 0W10 ADO6 0Y07 AA07 AE05 AE06 ADO7 ADO8 AC10 AD10 ACO9 0U11 0V11 AE09 AE10 AE11 ACO8 ACO6 0Y11 ABO9 0V12 0W12 AB12 AB14 0Y15 AC18 AE15 AD18 AE18 AA18 AB19 0U15 0Y17 AE17 AC17 AD16 0V15 AB18 Signal SYS DATA55 SYS DATA56 SYS DATA57 SYS_DATA58 SYS_DATA59 SYS_DATA60 SYS_DATA61 SYS_DATA62 SYS_DATA63 SYS_DATAPO SYS_DATAP1 SYS_DATAP2 SYS_DATAP3 SYS_DATAP4 SYS_DATAP5 SYS_DATAP6 SYS_DATAP7 SYS
121. YS MACHK 0 1 SRESET 0 1 SYS TBE SYS TBST SYS TSIZ 0 2 SYS TT 0 4 Page 222 of 209 PowerPC 8p 750 IBM25CPC710AB3B100 dine Timing Setup min Hold min Setup min Hold min Tp max ns Tp min ns ns ns ns ns 50 pf 0 pf 5 2 0 0 5 00 1 00 5 2 0 0 4 50 1 00 4 6 0 0 5 00 1 00 IBM25CPC710AB3B100 PowerPC Output Valid Output Hold Output Valid Output Hold 9P 750 Timing Max Load Min Load Max Load Min Load Setup Hold ns pf ns pf ns pf ns pf ns ns 6 9 30pf 1 5 10pf 2 5 4 0 6 7 5 80pf 1 7 10pf 2 5 4 0 6 65 30pf 1 1 10pf 2 5 4 0 6 6 9 30pf 12 10pf 2 5 4 0 6 7 4 80pf 1 3 10pf 2 5 4 0 6 6 26 2000 IBM Dual Bridge and Memory Controller PCI 32 bit Bus Timing Specification 33 MHz PCI 32 bit Bus Timings NM IBM25CPC710AB3B100 SEM aoe Min ns Max ns Min Max Min Max Output Valid Bused Signals 2 1 6 9 2 6 Output Valid Point To Point 6 6 2 6 Input Hold 0 3 0 Input Setup Bused Signals 3 1 3 Input Setup GNT 4 7 5 Input Setup REQ 4 7 5 Clock Skew 1 System Prop 5 6 26 2000 Page 223 of 209 IBM Dual Bridge and Memory Controller PCI 64 bit Bus Timing Specification 66 MHz PCI 64 bit Bus Timings Description Output Valid Bused Signals Output Valid Point To Point Input Hold Input Setup Bused Signals Input Setup GNT Input Setup REQ Clock Skew System Prop Page 224 of 209 IBM25CPC710AB3B100 Min ns
122. a range of PCI 32 or PCI 64 addresses defined as potential deadlock Recommended SYS ARTRY Procedure A master that has had its address tenure retried should negate its SYS BR n for at least one bus cycle in the cycle immediately following detection of an active SYS ARTRY A master that has retried an address tenure due to a snoop hit should activate its SYS BR n in the cycle immediately following the detection of an active SYS ARTRY This ensures the master that retries is ser viced before the master that was retried 6 26 2000 Page 161 of 209 IBM Dual Bridge and Memory Controller Locking Signal DLK The device can set the DLK output for CPU access to the PCI 32 or PCI 64 bus when input NODLK is not active 1 the access is within the address range defined by the selected bridge s registers SMDLK1 2 or SIDLK1 2 bit 24 of the PGCHP register is 1 The 60x CPU can then receive an SYS ARTRY when the NODLK signal becomes active 0 Page 162 of 209 6 26 2000 IBM Dual Bridge and Memory Controller 60x Bus Configuration The system uses configuration cycles to identify and configure BUCs on the 60x bus The following rules apply to configuration cycles All configuration cycles must use the Basic Transfer Protocol The BUC responds to addresses in the configuration space only when its SYS CONFIG n is active All configuration cycles must be single beat word aligned word accesses except for accesses to t
123. a transfer Corresponds to assertion of bit 4 in the GSCR status register V O General purpose I O signals Deadlock Asserted when processor range of address is out of the non dead lock zone An address SYS ARTRY is sent to the PowerPC when DLK is set Deadlock Disable Used only when the deadlock address range checking is programmed Asserted 20 it disables checking Tie to high level 21 the deadlock checking can be performed 6 26 2000 IBM Dual Bridge and Memory Controller Memory Interface Signals Signal Name 1 0 Type Description MDATA 0 63 y o Memory Data MDATA 64 7 1 VO Memory Data ECC bits MADDRO_ODD O Memory Address bit 0 for Odd DIMMs MADDRO EVEN O Memory Address bit 0 for Even DIMMs MADDR 1 12 O Memory Address bits 1 to 12 SDCS 0 7 O SDRAM Chip Select 0 to 7 SDCS 8 15 or Programmable I Os by setting bit 11 of the MCCR register O 0 SDRAM Chip Select 8 to 15 EBHSMIDH 1 SDRAM Chip Data Mask 0 to 7 SDRAM Clock Enable RBEREDES 9 height signals with same shape for buffering issues EN Memory Write Enable WED a four signals with same shape for buffering issues ShBAS A SDRAS 0 3 o SORAM RAS Row ddress Strobe 0l four signals with same shape for buffering issues AA DRAM CAS Col A SDCAS 0 3 o S j CAS Co umn Address Strobe 0 four signals with same shape for buffering issues BS 0 1 O SDRAM BS Internal Bank Select Signals to be used with Texas Instruments ALVCH162268 MUX 12 to 24 bit reg
124. abled by PCI CMND Address Parity Error register bit6 Any PCI Bus Transfer Disabled Detected SERR Active PCI Bridge Logic Idle Single Bit Error Access to System Normal Memory Double Bit Error Diagnostic Notes Action Notes Save encoded arb level in CSR register Set Address parity error detected bit in CSR register Set Parity error detected bit 15 in PCI status register Place PCI address in PSEA register Activate SERR signal if enabled by bit 8 PCI CMND register Set Signalled SERR bit in PCI Status register if enabled Target abort PCI transfer if address matches Set Signaled target abort bit in PCI status register Signal Machine Check with SYS_MACHK Set Parity error detected bit 15 in PCI status register Complete PCI transfer normally if address matches Set Detected SERR active bit in CSR register Save encoded ARB level in CSR register Signal Machine Check with SYS_MACHK Set single bit error and syndrome in MESR Set error address in MEAR Return corrected data to PCI device Proceed normally with PCI transaction Set double bit error in MESR Set error address in MEAR Set memory error bit in CSR register Loads Target abort PCI transfer Set signaled target abort bit in PCI status register Signal Machine Check with SYS_MACHK Stores Signal Machine Check with SYS_MACHK Set double bit error in MESR Set error address in MEAR Return uncorrected data to PCI device Proceed normally with PCI transaction 1
125. achine Check with 1 SYS TEA Stores Signal Machine Check with SYS MACHK If PGCHP 26 1 Signal Machine Check with SYS MACHK Terminate CPU transaction normally Page 165 of 209 IBM Dual Bridge and Memory Controller Error Handling for CPU Initiated Transactions Page 3 of Operation Error Mode Enabled by bit 6 in PCI CMND register Detected PCI bus data parity error on load Disabled by bit 6 in PCI CMND register Access to PCI bus cont d Enabled by bit 6 in PCI CMND register Detected PERR on store Disabled by bit 6 in PCI CMND register Detected target abort 1 A dummy 0 is returned for read operation For write data is ignored Page 166 of 209 4 Action Notes Continue transfer on PCI bus to completion Activate the PERR signal Set data parity error bit 8 in PCI Status register Set data parity error bit 15 in PCI Status register Set PCI error bit in SESR Set error address in SEAR register If PGCHP 26 0 4 Loads Signal Machine Check with SYS TEA Stores Signal Machine Check with SYS MACHK If PGCHP 26 1 Signal Machine Check with SYS MACHK Terminate CPU transaction normally Set parity error bit 15 in PCI Status register Proceed normally with PCI transaction Proceed normally with CPU transaction Continue transfer on PCI bus to completion Set data parity error bit 8 in PCI Status register Set data parity error bit 15 in PCI Status register Set PCI error bit in SESR
126. activated 10 Reserved Must be left to 0 Local Reset Enable 11 0 PCI 64 Signal G RESETOUT is not driven di If external arbiter then G RESETOUT is driven 12 15 Reserved 6 26 2000 Page 111 of 209 CPC710 133 IBM Dual Bridge and Memory Controller Bit s 16 17 18 19 20 23 24 25 26 27 81 Description Reserved R W Must be left to 0 Machine Check Detected Signal When Single Bit Error 0 SYS MACHK signal not driven 1 SYS MACHK signal is driven TRASA Active for SDRAM access only 0 tRASmin 5 clock ae tRASmin 4 clock Reserved Reserved R W Auto Retry Enable 0 SYS_ARTRY is not driven 1 SYS ARTRY is driven when the access is in Peripheral Memory or I O space with potential deadlock PowerPC Processor Type see Adaress Transfer Attribute for Snoop Register ATAS on page 118 0 604 T 750 or later version TEA Control Disable 0 SYS TEA is driven 1 SYS TEA is not driven but Machine Check Signal is Reserved Page 112 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Free Register 1 RGBAN1 This register contains Data coming from the CPU Reset Value x 0000 0000 Address x FF00 1110 Access Type Read Write Data from CPU v Y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 31 Data from CPU 6 26 2000 Page 113 of 209 CPC710 133 IBM Dual Bridge and Memory Controller Free
127. ain Open Drain Description 32 bit Multiplexed Address Data Higher Part In the address phase when G_REQ64 is asserted these bits are the upper part of 64 bit address AD 63 32 During data phase an additional 32 bits of data are transferred when G_REQ64 and G_ACK64 are both asserted High Z when unused 32 bit Multiplexed Address Data Lower Part A write operation is defined as the transfer of data from the PCI bus master to a PCI slave device on the PCI Bus Acknowledge 64 Bit Transfer Request 64 Bit Transfer External Pull up required Parity Upper Double Word Bus Command Byte Enable Device Select Initialization Device Select Used as chip select during configuration Cycle Frame Initiator Ready Reserved for future usage It is recommended to tie up this signal Parity Bit PCI 64 Configuration Reflects PCI 64 Configuration bits 13 11 in the CONFIG ADDR reg ister Set to Zero when bit 15 or 14 are on PCI 64 Bus Grant PCI 64 Bus Requests G REQ 2 is sampled at Reset to select arbitration on the PCI 64 bus The arbitration can be made by the device G_REQ 2 1 or by external circuit 20 In case of external arbitration the request is send to PCI from G_GNT 1 and the grant from the external arbiter is received on pin G REQ 1 Reset PCI 64 Bus External pull up required Input Replicated on G RESETOUT when programmed Output Activated by the CPC710 at Powerup or by programming PCI 64 Data Parity E
128. al hexadecimal and binary numbers are used throughout this document and are labeled as follows Decimal 1234 56 Hexadecimal X ABCD Binary b 0101 In Little Endian mode bits and bytes are numbered in descending order from left to right The most significant bit MSB has the highest number and the least significant bit LSB has the lowest number tn en op z 4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 171 16 5 1413121 1 0 In Big Endian mode bits and bytes are numbered in ascending order from left to right The most significant bit MSB has the lowest number and the least significant bit LSB has the highest number o lt MSB 9 LSB 1 2 13 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Page 8 of 209 6 26 2000 IBM Dual Bridge and Memory Controller L2 Cache L2 Cache Optional PowerPC PowerPC 2nd CPU gt 604 750 604 750 i 64 gt 60x System Bus CPC710 0 2 4 6 k PCI 64 Bus 66 MHz z z z z DMA z 2 2 2 72 Memory Controller a a a a PCI Bridges L 72 Sys
129. alue x1014 Address x 00 Access Type Read Only VID Y Y 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit s Description Vendor Identification Number 13 0 Value x 1014 x14 for address 00 and x 10 for address 01 Device ID DEVID This register identifies a particular device Reset Value PCI 32 x 0105 PCI 64 x 00FC Address x 02 Access Type Read Only DEVID Y Y 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit s Description Device Identification Number 15 0 Value x 0105 for PCI 32 x 05 for address 02 and x 01 for address 03 Value x 00FC for PCI 64 x FC for address 02 and x 00 for address 03 6 26 2000 Page 41 of 209 CPC710 133 IBM Dual Bridge and Memory Controller PCI Command CMND This register provides control over the bridge s PCI behavior Reset Value PCI 32 x 0000 PCI 64 x 0000 programming PCI 32 X 0156 example PCI 64 x 0356 Address x 04 Access Type Read Write 2 a s c Lu E c oO E E 8 E 2 2 o gt E o 2 2 amp es i 5 o w S o2 5 So x 2 Soto 53 o 2 uw o c Q ts Gc 8 j amp DoG Q C 9 o0 o C 5 amp or 8 852 9 t29 yE i 3 Se 5 BO Sif Bowel Bee alo Sega 8 m lt x 9 Qa 2 Qo 0D S o 9 o o o s s Reserved Sle o4 2 20 m iu Y yyy i i i KM 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 o Bit s Description 15 10 Reserved Fast Back to back
130. ange allowed 1 Accesses to DMA Address Range inhibited 6 Reserved R W Must be left to 0 7 Reserved 8 11 Resource ID This 4 bit field contains the Resource ID that device uses to determine whether or not it is the target of a DMA transfer operation Time Base Enable 12 0 The Time Base Enable signal to the CPU is deactivated CPU real time clocks halted 1 The Time Base Enable signal SYS TBE to the CPU is activated CPU real time clocks enabled 13 14 Reserved 15 Reserved R W Page 100 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Bit s Description Kill Snoop Operation Must set to 0 for the PowerPC 750 16 0 Device issues Kill address only transaction types for full cache line invalidates 1 Device issues Flush address only transaction type for full cache line invalidates Workaround of the 604 errata Kill snoop bug 17 23 Reserved CPC710 EC LEVEL Read only Bit 24 always at one Bits 25 to 27 main Engineering changes Bits 28 to 31 for sub Engineering changes 1000 0000 for CPC710 100 24 31 6 26 2000 Page 101 of 209 CPC710 133 IBM Dual Bridge and Memory Controller Multi Processor Semaphore MPSR This register is used by the IPL boot code to facilitate bring up of processors in an MP environment It pro vides a first access bit BIT 31 that allows a method for processors to determine which processor is the mas ter since both processors are active after power on BIT 31 contains a value of 0 af
131. ase Address IBM Dual Bridge and Memory Controller Reserved Y vov Y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s 0 11 12 31 Reserved 6 26 2000 Description PCI Base Address Contains the upper bits of the PCI base address that PCI Memory is mapped to Note Address must be aligned on boundary equal to size specified in PCI Memory Size register Page 69 of 209 CPC710 133 IBM Dual Bridge and Memory Controller Component Reset Register CRR This register provides software with a means to disable all devices on the PCI bus by writing a zero in bit O Reset Value x 0000 0000 Address BAR x 000F 7EFO Access Type Read Write 5 o tc e 8 Reserved Reserved 1 vox v 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description Device 0 Reset 0 0 Reset signal P RST or G RST is active 1 Reset signal inactive 1 5 Reserved Must be left to 1 6 31 Reserved Page 70 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Personalization Register PR This register provides additional programmability of the PCI Bridge logic Reset Value x 0000 0000 Address BAR x 000F 7F20 Access Type Read Write PCI ISA Bridge Deadlock Avoidance Disable Issue Flush Snoops not Kill Snoops m Deadlock Avoidance Signal Selection lt
132. atch and if translation is enabled by software the PCI address is translated to a system address bit 4 Personalization Register PR on page 71 A series of checks is performed to determine whether the access is back to the same bridge If it is the PCI bridge will not respond to the PCI master The PCI bridge logic also forwards the access to system memory If this address does not match a memory configuration extent the memory controller logic returns an invalid address error thus ensuring that PCI mas ters do not access system facilities Page 146 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Translation Enabled If translation is enabled the PCI bridge logic translates addresses before presenting them to system memory as shown in the following figure However not all addresses are presented System Memory Space Translation PCI Memory Space mE sg 7 4GB Complement Upper Address bit 0 2GB Complement Upper 12 4 Address Bits No Translation ETC Not Forwarded PCI Memory lt PMBAR Complement Upper 12 Address Bits Translation Disabled If translation is disabled the PCI bridge does not translate addresses before presenting them to the system as shown in the following figure System Memory Space PCI Memory Space m 4GB No Translation MSIZE PCI Memory E r
133. ccesses on the PCI bus 1 PCI Bridge will respond to IO accesses on the PCI bus except for PREP mode see note below Note O cycles for Slave as defined in bit O are not decoded by the CPC710 when the address mapping is in PREP mode See PREP mode definition 6 26 2000 Page 43 of 209 CPC710 133 IBM Dual Bridge and Memory Controller PCI Status STAT This register records status and error information from PCI bus transfers Reads from this register behave normally Writes to this register are restricted in that software cannot set any bit in this register only reset Additionally to reset a bit software must write a 1 to the corresponding bit location For example to reset only bit 14 software must write 0100 0000 0000 0000 b to this register Reset Value x 0280 Address x 06 Access Type Read Write o a oO v E S g eae T 33833 rar TOW 9x 9 o tg 2 g 855 g9 4a 5g zr PF E 2B 8 8g E L 205595 bT Elo E 8 E 9 gp 025 B5 Reserved t e s s 4 15 14 13 12 11 10 918 76 5 4 3 2 1 0 Bit s Description Parity Error 15 0 No Error ie PCI Bridge has detected a parity error bit set even if parity checking is disabled Signaled System Error P G_SERR 14 0 No Error f PCI Bridge has asserted SERR due to an address parity error Signaled Master Abort 13 0 No Error PCI Bridge has issued a master abort Received Target Abort Master 12 0 No Error
134. d 0T17 P GNT3 ovo6 MDATA30 ON15 P CFGl ORO4 MDATA12 O0T18 P GNTA4 0V07 MDATA1 ON16 Vpp ORO5 MDATA22 0T19 P GNT O 0V08 SYS_TT3 ON17 P_ADL26 ORO6 MDATA35 0T20 P MEMREQ 0VO9 SYS DATAP2 ON18 P_ADL8 ORO7 Ground 0T21 P GNT1 0V10 SYS DATAPO ON19 P ADL10 ORO8 MDATA29 0T22 P MEMACK 0V11 SYS DATA29 ON20 Vpp ORO9 MDATA33 0T23 G REQ7 0V12 SYS DATA37 ON21 G GNT7 OR10 BSO 0T24 P ADLO 0V13 SYS DATA60 ON22 Ground OR11 Ground 0T25 P CBE2 0V14 SYS_DATA4 ON23 P ADL31 OR12 Vpp 0U01 MDATA31 0V15 SYS_DATA53 ON24 Vpp OR13 RESERVED4 0U02 Vpp 0V16 SYS ADDR2 ON25 P ADL11 OR14 Ground 0U03 MDATA32 0V17 SYS_ADDRO OPO1 MDATA13 OR15 Ground 0U04 MDATA8 0V18 SYS ADDR26 0PO2 PCI CLK OR16 PLL TUNEO 0U05 Vpp 0V19 SYS_ADDR25 OPO3 MDATA14 OR17 P CBE3 0UO6 MDATA18 0V20 P DEVSEL OPO4 TDI OR18 P LOCK 0UO7 MDATAO 0V21 G RESETOUT OPO5 MDATA15 OR19 Ground 0UO8 MDATA2 0V22 P PERR OPO6 TCK OR20 P ADL4 0U09 Vpp 0V23 SYS_ADDR31 OPO7 SYS_HRESET1 OR21 P_GNT2 0U10 SYS DATA16 0V24 SYS ADDR16 OPO8 TRST OR22 P ADL3 0U11 SYS DATA28 0V25 SYS ADDR22 0PO9 SDCS4 OR23 Ground 0U12 O_GPIO1 owo1 SYS_DBG1 OP10 BS1 OR24 P ADL7 0U13 O GPIOO owo2 SYS AACK 0P11 SDRAS3 OR25 P PAR 0U14 Vpop 0WO3 Ground 0P12 Vpp OTO1 MDATA16 0U15 SYS DATA48 0W04 MDATA6 0P13 RESERVED6 0T02 POWERGOOD 0U16 RESERVED1 0WO05 SYS TSIZ1 0P14 Vpp OTO3 MDA
135. ddress error Page 184 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Double Bit ECC Error General Case The hardware procedure for this error is 1 Set the Double Bit error bit in MESR if no hard errors are present 2 Store the syndrome in MESR and the address in MEAR if no hard errors are present Co In normal mode indicate the error to the requesting logic with DAT ERR for the appropriate double word that failed in memory In diagnostic mode do not indicate Double Bit errors with DAT ERR Software must write zeros to the MESR to clear errors If more than one Double Bit error occurs before the MESR clears only the first error is recorded A Single Bit error is not logged into MESR and MEAR when it occurs after a Double Bit error oOo N OO A If an Address error occurs after a Double Bit error it is not be logged into MESR and MEAR Double Bit ECC Error Special Case For non burst write transactions that do not span an entire aligned double word the Memory Controller per forms a read modify write sequence to memory If the read portion of this sequence results in a Double Bit error the controller indicates the error to the requesting logic through the response bus instead of using DAT ERR If this occurs in diagnostic mode the error is logged into MESR and MEAR but not reported through the response bus Overlapping Memory Extents Overlapping Memory Extents are not detected until an access occurs
136. dge Indicates device has flushed all CPU to PCI 32 bus buffers and any CPU access to PCI is being SYS ARTRYed Memory Request Indicates a PCI device accessing system memory has a potential P MEMREQ l Pull up deadlock and requests device flush all posted CPU to PCI buffers and ARTRY all PCI 32 bus transfers from the 60x bus P_PAR VO Parity Bit P_GNT 0 6 O PCI 32 Bus Grants P REQ 0 6 l Pull up PCI 32 Bus Requests P_RST O PCI 32 Bus Reset P_PERR 1 0 PCI 32 Data Parity Error P SERA UO PCI 32 System Parity Error Reports parity errors on address special cycle data or systems P STOP 1 0 Stop Asserted by the target to request the master to stop current transaction P_TRDY 1 0 Target Ready Asserted by the target when ready to receive data P_CFG 0 2 Oo Configuration Bit Reflect Reflects PCI 32 configuration bits 13 11 in the CONFIG ADDR register Set to zero when bits 14 or 15 are on Page 28 of 209 6 26 2000 IBM Dual Bridge and Memory Controller PCI 64 Bus Interface Signals 3 3V compliant 5V Signal Name G ADH 0 31 G ADL 0 31 G ACK64 G_REQ64 G_PAR64 G_CBE 0 7 G_DEVSEL G_IDSEL G_FRAME G_IRDY G_LOCK G_PAR G CFG 0 2 G GNT 0 7 G REQ 0 7 G PERR G SERR G STOP G TRDY G INTA G INTB G INTC G INTD G ARB G RESETOUT 6 26 2000 VO 1 0 VO VO VO VO VO VO VO VO VO VO VO VO VO Oo 0 0 0 0 0 Type Pull up Pull up Open Drain Open Drain Open Dr
137. dress x 42 Access Type Read Write Disconnect Counter v Y 7 6 5 4 3 2 1 0 Bit s IBM Dual Bridge and Memory Controller Description Device uses this register when acting as a target device as a time out mechanism in burst operations The value written to this register is multiplied by four and used to determine when the bridge should assert STOP AVDG on page 120 After reset this register contains x 00 which disables the timer This counter is enabled only if bit O for PCI 32 or bit 8 for PCI 64 of AVDG Register is set see Diagnostic Register When time out occurs the bit 9 of the CSR Register is set see Channel Status Register CSR on page 91 6 26 2000 Page 59 of 209 CPC710 133 IBM Dual Bridge and Memory Controller Retry Counter RETRY Reset Value x 00 Address x 50 Access Type Read Write RETRY 4 Y T 8 8 4 34 2 0 Bit s Description When the device is a Master on the PCI bus this register is used as a time out mechanism for continuous retries on the PCI bus Whenever a retry occurs for a particular address the PCI bridge logic increments decrements a counter The 8 bit counter is reset whenever data is transferred If the count reaches the value specified in this register the PCI bridge logic will not retry the access and will report the Result by writing bit 5 of the PLSSR Register see Processor Load Store Status Register PLSSR on page 92 After reset the
138. e 0xb0000000 ERRC Ox 001050 write 0x00c00000 SESR Oxff001060 write 0x00000000 SEAR 0x 001070 write 0x00000000 PGCHP 0xff001100 write 0x00000000 Memory Interface registers setup Eyf Ji MESR 0xff001220 write 0x00000000 MEAR 0xff001230 write 0x00000000 MCERO 0xff001300 write 0x800080c0 MCER1 0xff001310 write 0x808080c0 MCCR 0xff001200 write 0x83b06000 PCI64 and PCI32 Interfaces Configuration mode setup JE eee ee Enable configuration mode for PCI64 CNFR Ox f 00000c write 0x80000003 CPU SYNC SYNC OP BAR Oxf 200018 write Oxff400000 PCIENB 0xff201000 write 0x80000000 Enable configuration mode for PCI32 CNFR Ox f00000c write 0x80000002 CPU SYNC SYNC OP BAR 0xff200018 write Oxff500000 PCIENB 0xff201000 write 0x80000000 Disable configuration modes CNFR Ox f 00000c write 0x00000000 CPU SYNC SYNC OP PCI64 Interface registers setup J PIBAR Oxff4f7800 write 0x5c000000 PMBAR write 0x5a000000 Page 208 of 209 6 26 2000 IBM Dual Bridge and Memory Controller PR write 0x00008000 ACR write Oxff000000 MSIZE write Oxfc000000 example with 64 MB IOSIZE write Oxff000000 example with 16 MB SMBAR write 0xe0000000 SIBAR write 0x90000000 CSR write 0x00000000 PLSSK write 0x00000000 PCI64 Command register setup
139. e 2 1 1 33 MHz 1 1 2 3 1 4 72 14 2 M lemory 16 1 Interface 8 4 2 4 4 1 1 2 2 2 Misc 1 1 1 1 1 4 JTAG 1 1 1 1 PLL 6 26 2000 480 Signals 300K Gates IBM Dual Bridge and Memory Controller SYS BG 0 1 SYS AD Ria SYS ADDRP 0 3 SYS TS SYS TIU4 SYS TSIZ 0 2 SYS TBST SYS GBL SYS AACK SYS ARTRY SYS SHD SYS TA SYS TEA SYS DATA 0 63 SYS_DATAP 0 7 SYS_DBG 0 1 FLASH_OE WE XADR_LAT XCVR_RD PRES OE 0 1 G_ADH 0 31 G_ADL 0 31 G_CBE 0 7 G PAR G_PAR64 G_REQ64 G ACK64 G FRAME G IRDY G TRDY G STOP G DEVSEL G PERR G SERR G RST G RESETOUT G INTA B C D P ADL 0 31 P CBE 0 3 P_PAR P_FRAME P_IRDY P_TRDY P_STOP P DEVSEL P PERR P SERR P RST MDATA 0 71 MADDRO ODD MADDRO EVEN MADDR 1 12 SDCS 0 7 8 15 SDDQM 0 7 SDOKEQU ooo WE 0 3 SDRAS 0 3 SDCAS 0 3 SCAN_GATE_ RI CEO_TEST CEO IO CE TRST TESTOUT TDO PLL LOCK VDDA Page 23 of 209 IBM Dual Bridge and Memory Controller Signal Descriptions Tri state driver receivers interface 3 3 V internal functions with 3 3 V LVTTL off chip buses Some receivers interface 3 3 V internal functions with either 3 3 V LVTTL or 5 0 V TTL off chip bidirectional buses All drivers are 50 ohm source terminated In the following table Pull up in the Type column indicates an internal 10K pull up is built into the device driver receiver No additional external dev
140. e Size MSIZE on page 74 System Base Address for PCI Memory SMBAR on page 76 PCI I O Address Space Size IOSIZE on page 75 System Base Address for PCI I O SIBAR on page 77 If the address falls within one of these ranges the 60x interface logic passes the address and command to the appropriate PCI bridge logic for execution using the translation specified by the following PMBAR or PIBAR registers PCI Base Address for I O PIBAR on page 68 PCI Base Address for Memory PMBAR on page 69 Page 144 of 209 6 26 2000 Peripheral I O Address Translation IBM Dual Bridge and Memory Controller The first 8MB of Peripheral I O space requires additional translation To prevent 32 byte granularity accesses to ISA addresses the device supports a noncontiguous I O address mode in which the first 64KB of PCI bus I O space is divided into 32byte segments spaced at 4K intervals within system memory This mode is selected by bit 5 of PHB Configuration Register CTLRW on page 78 Noncontiguous I O Address Mode Enabled Peripheral V O Space 8MB A SIBAR 8MB T Area Wrapped To First 32 Bytes 32 Bytes IOSIZE lt PIBAR 8 MB Ae Va fi IN IOSIZE AN ANV SIBAR 12 KB N 32 Bytes Area Wrapped To First 32 Bytes Not addressable SIBAR 8 KB 32 Bytes Area Wrapped To First 32 Bytes SIBAR 4 KB 32 Bytes Area Wrapped To
141. ed 24 31 Single or Double Bit Error Syndrome Used to determine the failing DIMM Page 124 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Memory Error Address Register MEAR This register contains the address associated with the error logged in the MESR Reset Value x 0000 0000 Address x FF00 1230 Access Type Read Write Address of Memory Error v Y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 31 Address of Memory Error 6 26 2000 Page 125 of 209 CPC710 133 IBM Dual Bridge and Memory Controller Memory Configuration Extent Registers MCER 0 7 Each one of the eight registers MCERO to MCER7 defines one of up to eight banks of memory Bank 0 to 7 supported All registers have the same definition and each defines the size and location for the particular bank of memory Reset Value x 0000 0000 Address MCERO x FF00 1300 MCER1 x FFOO 1310 MCER2 x FF00 1320 MCER3 x FF00 1330 MCER4 x FF00 1340 MCER5 x FFOO 1350 MCER6 x FF00 1360 MCER7 x FF00 1370 Access Type Read Write S E O 2 iz E 96 E amp lt lt ir 2 zz 2 E amp E amp Reserved Start Address For Bank e Extent Size Code For Bank 20 e Ly vov vo 9 vox v8 y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description Bank Enable 0 0 Bank is not present
142. ed on 32 byte cache line reload Three separate dual 32 byte load buffers PCI 32 PCI 64 60x PCI 32 and PCI 64 Bus Bridges Two independent PCI bus bridges with parking PCI revision 2 1 compliant e 3 3V Compliant with 5 0 V PCI signalling e Runs async logic to 60x and memory controller PCI 64 arbitration can be disabled Dual 32 byte buffers in each PCI bus bridge Round robin PCI arbiter Coherency for memory access through DMA controller or through PCI master Noncontiguous byte enable transfer to memory The CPC710 is single load on all PCI signals For system designs requiring high I O bandwidth the device contains two PCI host bus bridges One bridge supports a standard 32 bit 33 MHz PCI bus for standard and native I O The other bridge supports a 64 bit 33 66 MHz PCI bus for high data throughput applications such as graphics and high speed communications A DMA controller provides high speed capability for large data transfers between memory and I O Store gathering enhances CPU to I O performance Page 7 of 209 IBM Dual Bridge and Memory Controller Ordering Information Part Number Operating Speed Junct Temp Power Supply Description IBM25CPC710AB3A100 100 MHz 40 105 C 3 3V 5 IBM Dual Bridge and Memory Controller Conventions and Notation The use of overbars for example RESET designates signals that are active low All signals are active high unless shown with an overbar Decim
143. eer eee ne mee PMBAR Note Translation can be disabled for CPU to PCI transfers if the values stored in the PMBAR and SMBAR registers are the same 6 26 2000 Page 147 of 209 IBM Dual Bridge and Memory Controller Flexible PCI Host Bridge FPHB Mode In FPHB Mode External Masters on the 32 bit and 64 bit PCI buses address system memory using the address translation model shown in the following figure The model uses several programmable registers in the Specific PCI Host Bridge Space Specific PCI Host Bridge Registers on page 64 Note Each PCI bridge contains a set of programmable registers The device monitors addresses on the PCI bus to determine whether a PCI address falls within the range specified by the following PSBAR PSSIZE registers System Base Address Register for PCI 32 PSBAR on page 84 System Address Space SIZE for PCI PSSIZE on page 82 If an address falls within this range the PCI interface logic passes the address to the 60x bridge logic for exe cution using the translation specified by the System Base Address Register BARPS on page 83 PCI64 Configuration by external PCI Agent This flexible FPHB mode allows the configuration by an external PCI agent of some of the CPC710 reg isters of the PCI 64 bus bridge such as the PSBAR PSEM IT ADD SET and INT RESET registers See Standard PCI Configuration Space register number x 00 to x 68 on page 33 PCI to System Memo
144. egisters one for each PCI bridge that can be placed by the user in the upper 16MB of the System Memory One BAR value Base Address has to be defined first for each PCI bridge for example as shown in the following figure BAR_PCI32 FF50 0000 and BAR_PCI64 FF40 0000 The register space for the PCI 32 or PCI 64 bridge can then be accessed by the CPU with the PCI corre sponding base value loaded in the Base Address Register BAR x FF20 0018 The differentiation between the PCI 64 or PCI 32 is made by enabling the corresponding bit in the Connec tivity Configuration Register CNFR x FF00 000C The table Specific PCI Host Bridge Register List on page 64 describes the supported Registers Each of these registers is described in detail on pages 64 through 92 System Register Space x FF00 0000 to x FFFF FFFF The upper 16 MB of the 4 GB address range is reserved for system support functions The table System Reg isters List on page 93 describes the System Space Registers supported These registers are defined as Big Endian unless otherwise noted If the processor is operating in Little Endian mode software must issue Load amp Store reverse instructions to access these registers The device responds to all addresses listed in the table System Registers List on page 93 with a minimum granularity of 4 K blocks Accesses to these registers must be single word accesses on word boundaries or unpredictable results may occur Each of th
145. emory the PCI bus cycle is retried The follow ing figure shows the states the device follows when executing a PCI memory read cycle PCI Memory Read State Diagram Idle PCI Memory Read from system memory Initiate clean cache operation to the processor bus and start SYS ARTRY of CPU access to this cache line Initiate read from system memory and stop SYS ARTRY of CPU accesses to this line Cache line Wait for is modified for operations to complete Cache line not modified in CPU Retry PCI cycle Place memory read data on PCI bus to Y complete PCI transfer FLUSH data in buffers Page 190 of 209 6 26 2000 PCI Master Memory Write Cycles IBM Dual Bridge and Memory Controller When the device receives a memory write bus cycle to system memory it first initiates a FLUSH cache oper ation to the processor bus Processor accesses to this cache line will be SYS ARTRYed until the memory write is finished If the cache line is determined to be stale in memory the PCI bus cycle is retried The follow ing sequence describes the states the device follows when executing a PCI memory write cycle PCI Memory Write State Diagram Idle PCI Memory Write to system memory Initiate FLUSH cache op to the processor bus and start SYS_ARTRY of CPU access to thi is cache line Cache line Wait for is modified cache operation to complete
146. en if another master requests the bus This mode allows the device s memory controller to remain in page mode for these accesses Without this mode another master could insert a memory transaction to take the memory controller out of page mode Address Bus Pipelining Pipelining is controlled by bits 0 and 1 of the 60x Arbitration Control register ABCNTL Bit Description 10 If enabled by software the arbiter maintains up to a two level pipeline per master The arbiter continues to grant the address bus to a specific master until there are as many as three outstanding address tenures wait ing for a data bus tenure to complete or begin Since the device supports two masters on the system bus there can be as many as six address tenures on the 60x system bus that have not completed or begun a data bus tenure The arbiter stops granting the address bus to a particular master after its third address tenure The device can also drive a seventh address only tenure onto the bus to satisfy a DMA snoop operation 01 The arbiter maintains a one level pipeline per master The device stops granting the address bus to a master after it has two outstanding address tenures waiting for a data bus tenure to complete With two masters in the System there could be as many as four outstanding address tenures waiting for a data bus tenure to complete or begin and a fifth device generated address only tenure 0 1 00 Pipelining is completely disabled E
147. enting addresses only 11 Enabled for accesses to incrementing and same addresses NOT RECOMMENDED Page 104 of 209 6 26 2000 10 11 12 13 14 15 16 17 18 31 6 26 2000 IBM Dual Bridge and Memory Controller Description Endian Mode of the PowerPC CPU 0 60x logic interprets data from 60x in Big Endian mode 1 60x logic interprets data from 60x in Little Endian mode Eieio Retry Disable 0 Device will always SYS_ARTRY an EIEIO operation until every command in 60x queues has been dispatched to the logic units inside device 1 Device will not SYS ARTRY an EIEIO operation DBG Park Control 0 DBG signals are not parked when bus is idle 1 DBG signals are parked when bus is idle mode to use for 0 wait state L2 look aside Bit 18 must be set to zero or this bit is ignored Reserved R W Must be left to 0 Activate TA Signal Pre charge 0 The TA signal is precharged by device after a data bus tenure 1 The TA signal is not precharged by device at the completion of a data bus tenure Reserved These bit should be left to zero Reserved R W DBG Control 0 DBGO and DBG1 signals are driven separately 1 DBGO and DBG1 signals are effectively the same they are logically ORed mode to use for L2 lookaside Reserved R W Reserved Page 105 of 209 CPC710 133 IBM Dual Bridge and Memory Controller CPU Soft Reset Register SRST This register provides software with a mechanism to issue soft resets to each of the process
148. envia Pedo sane dee nn 47 eLLIIMeLtcxeneraXd cc 47 Cache EL ISIN CSIZE c 48 Latency Timer ETM e 49 Header Type HDRT swescaceedccvevertteinsusnactetandactnnees aaa eaa a a a aa E Ea E a E aa ANE 50 Built in Self Test BIST p 51 System Base Address Register for PCI 64 PSBAR ssssseseeeeeeneneeen nnne 52 Interrupt Line NTEN pec E O E O 53 Table of Contents 6 26 2000 Page 1 of 209 IBM Dual Bridge and Memory Controller Interrupt Pim INTPIN e 54 Minimum Grant MINGINT sesane inen tense eoe asa ee teu E 55 Maximum Eatency M AXET 12 cese uce cette tenente tenes esee egeat teet AEAEE gea d aree EA 56 Bus Number BUSNO 22 nti E edn RE dE CH dn REESE a RE ERE FR REERE Ru NE RR RAE RNRRuE 57 Subordinate Bus Number SUBNO esses seen ANEAN TEAGRA nete RRNA nnns 58 Disconnect Counte DISGNT eterne trie E eeu RERO EE ER REREF E ER E 59 Retry Counter RE WARY EE 60 Deadlock Retry Counter DLKRETRY for PCI 32 Only sse 61 Set Addressed Interrupt IT ADD SET eessssseseeeseeeesenne ennemi tnmen nenne 62 Reset PGI 64 Interrupt INT RESET net unn Robe d eR RE veas ttk x Fe EROR EORR ER oen ERR EE E 63 Specific PCI Host Bridge Registers eeeeeesesseeeese essen eene nennen nennt r nnn nnmnnn nn nn nnns 64 PCI Slave Error
149. er attribute signals must go to tri state on the next bus cycle Address Retry Output indicates device detects a condition that requires an address tenure to be retried Input When asserted in response to a device cache operation device assumes the cache line is modified and or present in a CPU or L2 cache Device then retries the operation on the PCI bus and address tenure is not rerun until the device on the PCI bus reruns its transfer The pre charge logic is always signaled to initiate the pre charge sequence Shared Output Not applicable Device only pre charges the signal Input Instructs the pre charge logic to initiate a pre charge sequence L2 Hit Indicates an external slave has been addressed by the current master The device arbiter uses this signal to confirm positive selection of an address tenure on the 60x bus Warning This signal is subject to timing constraints Data Bus Grant Indicates the device associated with this signal may with the proper qualification assume mastership of the data bus Data Bus Byte 0 D 0 7 DH 0 7 Byte 1 D 8 15 DH 8 15 Byte 2 D 16 23 DH 16 23 Byte 3 D 24 31 DH 24 31 Byte 4 D 32 39 DL 0 7 Byte 5 D 40 47 DL 8 15 Byte 6 D 48 55 DL 16 23 Byte 7 D 56 63 DL 24 31 Page 25 of 209 IBM Dual Bridge and Memory Controller 60x Bus Interface Signals Page 3 of 3 Signal Name VO Type SYS_DATAP 0 7 y o Data Transfer Termination Signals Ae
150. ese registers is described in detail on pages 93 through 130 Shaded address ranges indicate areas where CPC710 will respond with TEA addressing error is detected and logged in the System Error Status Register SESR x FF00 1060 bit 15 or bit 22 6 26 2000 Page 33 of 209 CPC710 133 IBM Dual Bridge and Memory Controller Register Map XFFFF FFFF System Space Address Map BOOT ROM 2 MB Boot ROM Space Specific PCI 32 Host Bridge Space BAR x 000F 9810 PSEA CRR SMBAR CFGD PSBAR TIODLK PCI 32 PHB PCIDG PR SIBAR PSSIZE CSR INTA ACR CTLRW BPMDLK PLSSR BAN nen GNERTS0 Ig Pe PIBAR MSIZE CTLRO BARPS TPMDLK BAR x 000F 6110 PMBAR IOSIZE CFGA BIODLK Specific PCI 64 Host Bridge Space PSEA CRR SMBAR CFGD BPMDLK INT SET PCIDG PR SIBAR PSSIZE TPMDLK CSR INTA ACR CTLRW BIODLK PLSSR PIBAR MSIZE CTLRO BARPS TIODLK PMBAR IOSIZE CFGA IT AD RESET BAR x 000F 9810 PCI 64 PHB BAR FF40 0000 for example when CNFR 30 31 11 BAR x 000F 6110 16 M5 x FF20 1000 Device Specific Configuration Space PCIENB Standard System Configuration Space DCR DID BAR DMA Space GSCR XSSR XTAR XSCR GSSR XPAR GSCR XSSR XSCR XWAR GSSR XPAR XWAR XTAR Specific System Space UCTL MPSR SIOC 60XC ERRC RGBAN2AVDG SESR GPDIR MCCR SEAR GPIN MESR PGCHP GPOUT MEAR MCER1 MCER6 MCER2 MCER7 MCER3 SIORO MCER4 SIOR1 SRST RGBANIATAS MCERO MCERS5 Standard System Space PID
151. f Boot ROM and System I O Registers PD to Device IBM25CPC710AB3A100 Dir SIO D 15 8 XCVR RD see note PCI 32 F_AD 19 __ BUS 2 ES CE NN F AD 18 0 P ADL 31 0 gt gt B Side A Side WE LVT245 OE XADR LAT FLASH OE gt OE FLASH WE J gt WE Strap for Flash write CE protection BCT245 CC po ee F_AD 18 0 PRES_OE1 gt PDbits 0 0 31 512 K x 8 FLASH REG1 PDbits 1 0 31 PRES OEO gt Presence Detect REGO 8 bits Bank Note There is no output enable control for the LVT245 drivers All control is done by the Direction control bit on signal XCVR_RD For a Read of the Boot Flash the XCVR_RD signal is at the Up level 1 such that the data is transfered through teh 245 buffer from the A side Flash to the B side PCI 32 A D Page 198 of 209 6 26 2000 IBM Dual Bridge and Memory Controller DMA Controller Introduction The data transfers between the system memory and the PCI buses can be performed either by the DMA con troller or by a PCI master on one of the PCI busses which can access in Read or Write the System memory See the PCI section The DMA is initiated either by a PowerPC specific instruction or by writing to the XTAR register The DMA is defined with one channel and with several type of mode of operations To signal the end of the DMA operatio
152. ft Reset Register 106 x FF00 1050 ERRC Error Control Register 107 x FF00 1060 SESR System Error Status Register 108 x FF00 1070 SEAR System Error Address Register 110 x FFOO 1080 Reserved x FF00 1100 PGCHP Chip program Register 111 x FF00 1110 RGBAN1 Free Register 1 113 x FFOO 1120 RGBAN2 Free Register 2 114 x FFOO 1130 GPDIR GPIO Direction Register 115 x FF00 1140 GPIN GPIO Input Register 116 x FF00 1150 GPOUT GPIO Output Register 117 x FFOO 1160 ATAS Address Transfer Attribute for Snoop Reg 118 x FF00 1170 AVDG Device Diagnostic Register 120 X FF00 1174 to x FF00 11FF Reserved x FF00 1200 MCCR Memory Controller Control Register 122 x FF00 1210 Reserved x FF00 1220 MESR Memory Error Status Register 124 x FF00 1230 MEAR Memory Error Address Register 125 x FF00 1300 MCERO Memory Configuration Extent Register 0 126 x FFOO 1310 MCER1 Memory Configuration Extent Register 1 126 x FFO0 1320 MCER2 Memory Configuration Extent Register 2 126 x FF00 1330 MCERS3 Memory Configuration Extent Register 3 126 x FF00 1340 MCER4 Memory Configuration Extent Register 4 126 x FFOO 1350 MCER5 Memory Configuration Extent Register 5 126 x FFOO 1360 MCER6 Memory Configuration Extent Register 6 126 x FF00 1370 MCER7 Memory Configuration Extent Register 7 126 x FF00 1400 SIORO SIO Register 0 DIMM PDs 128 6 26 2000 Page 37 of 209 CPC710 133 IBM Dual Bridge and Memory Controller
153. he CHKSTOP signal CPU Access to Memory Error for CPU 0 0 No Error 4 Error occurred during an access by the CPU to memory Error logged in MESR and MEAR Addressing Error Detected FOR CPU 1 0 No Error 1 Addressing error CPU to PCI Bus Access Error for CPU 1 0 No Error E Error occurred on PCI bus while servicing processor load store request DMA Error for CPU 1 0 No Error 1 Error occurred during DMA transfer CPU Access to Memory Error for CPU 1 0 No Error 1 Error occurred during an access by the CPU to memory Reserved Page 109 of 209 CPC710 133 IBM Dual Bridge and Memory Controller System Error Address Register SEAR This register contains the CPU address associated with the error that is logged in the SESR register described previously This register is only updated for errors that are due to CPU initiated transfers The address for errors that result from transfers initiated by PCI masters or DMA controller are located in error registers contained in the PCI bridge logic or the DMA controller logic In the case of dual processor implementation this register will contain only the address of the first error detected Reset Value x 0000 0000 Address x FF00 1070 Access Type Read Write Address Associated with Error Contained in SESR Y Y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 31 Address Associated with Error
154. he fea ture ROMs that are configured for byte access BUCs must respond to DCR reads at SYS L2 HIT assertion as shown in the following figure Otherwise the device assumes no device is present and SYS TAs the CPU with data indicating no device present 60x Bus Configuration Cycle BUS CLK eii i mmm FUNNY SYS_TA l i l i poA uh l3 l i i Note For in line L2 caches the L2 cache controller only supports configurations from its local processor Software should not configure the controller from a processor on the system bus side of the controller This makes it unnecessary for this kind of L2 cache controller to drive SYS_L2_HIT 6 26 2000 Page 163 of 209 IBM Dual Bridge and Memory Controller Error Handling for CPU Initiated Transactions The devices uses Machine Checks to indicate errors This allows software to log errors before the system is shut down In an MP environment the device activates the Machine Check pin that corresponds to the CPU initiating the transaction Because the PowerPC 601 does not provide this pin the checkstop pin is used Checkstop Errors The device generates a checkstop when the following are detected Address parity error on the 60x system bus if enabled Data parity error on 60x system bus if enabled Internal timeout due to no response from slave on load The 60x logic performs the following when ge
155. his register provides error status information for all transfers initiated by the CPU a PCI master or the other PCI Bridge logic Please see Error Handling for CPU Initiated Transactions on page 164 for additional details on this register Reset Value x 0000 0000 Address BAR x 000F 9810 Access Type Read Write a Ta 3 Eg gli 3 6 e 2 d o ao a e a 2 bago D IG 2 zm A r c Zeke Reserved 14445 Y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s 0 1 Description Reserved SERR Detected 0 No Error pe PCI Bridge detected G P SERR active during master operation No Devsel 0 No Error 1 PCI Bridge did not receive G P DEVSEL during master operation PCI Bus Timeout 0 No Error T PCI Bridge detected bus time out no G P TRDY detected Retry Count Expired 0 No Error T PCI Bridge detected bus time out too many retry s see Retry Counter RETRY on page 60 Reserved Page 92 of 209 6 26 2000 IBM Dual Bridge and Memory Controller System Registers Space System Registers List Page 1 of 3 Address Name Use Page Notes x FF00 0000 to x FF00 0007 Reserved Standard System Registers x FF00 0008 PIDR Physical Identifier Register 96 1 x FF00 000C CNFR Connectivity Configuration Register 97 see p 33 x FF00 0010 RSTR Connectivity Reset Register 98 x FF00 00E8 SPOR Software POR Register 99 7 Specific System Registers x FF00 1000 U
156. iagnostic debug Control vv Vy vov Vv vov 0 1 2 38 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 Reserved R W Boot Flash Size 000 2 0 MB Device initiates FLASH access for addresses x FFEO 0000 to x FFFF FFFF 1 3 001 1 0 MB Device initiates FLASH access for addresses x FFFO 0000 to x FFFF FFFF 011 0 5 MB Device initiates FLASH access for addresses x FFFO 0000 to xx FF7F FFFF 111 Reserved 4 8 Reserved 9 11 Reserved These bit should be left to zero 12 15 Reserved SIO Diagnostic debug Control Must Leave At Zero Do Not Change 16 17 Controls SIO TT1 signal 18 23 Controls PROC ID output 24 27 Controls asynchronous boundary 28 29 Controls SIO TS signal 30 31 Controls SIO TA signal 16 81 6 26 2000 Page 103 of 209 CPC710 133 IBM Dual Bridge and Memory Controller 60x Arbiter Control Register ABCNTL This register provides extensive control over the 60x bus arbiter operation For a detailed description of the 60x bus arbiter see section 60x Bus Arbiter Description on page 154 Reset Value x 0000 0000 Address x FF00 1030 Access Type Read Write PE S en a 1 8 5 2 T 5 2 S RB 5 5 5 2 g S a po g o o gt m S g 54Jx o 8 8 Be 6l t o 5 i 2a 8 Lly z o 3 oO o 3 gt o gt en 2 5
157. ic level Most Positive Down Level The most positive voltage that maintains cell functionality The maximum positive logic Least positive Down Level The least positive voltage that maintains cell functionality The minimum positive logic level Minimum Allowable Down Level The minimum voltage that may be applied without affecting the specified reliability Cell functionality is not implied Minimum Allowable applies to undershoot only LVTTL Driver Minimum DC Currents at Rated Voltage Vpp at 3 0 V temperature at 100 C Driver Type 50 Ohm Driver Outputs Vui V 2 40 Thermal Specifications Power Dissipation Thermal Resistance from junction to air Page 220 of 209 Parameter No Air Flow 100 CFM No Air Flow Cap No Air Flow 4 5mm Heat Sink lui mA 11 0 Typ 2 1 18 1 16 9 12 6 6 0 Vio V 0 40 Max 2 7 ILo mA 7 0 Units Watts C Watt C Watt C Watt C Watt 6 26 2000 IBM Dual Bridge and Memory Controller AC Timing Specifications Voc 3 3 V 5 Tj 40 C to 105 C 6 26 2000 Page 221 of 209 IBM Dual Bridge and Memory Controller 60x Bus Timing Specification 60x Bus Input Timings Signal SYS BR 0 1 SYS TS SYS ARTRY SYS TBST Others 60x Bus Output Timings Signal SYS ADDR 0 31 SYS DATA 0 63 DATAP 0 7 SYS_ARTRY SYS_SHD SYS_AACK SYS_BG 0 1 DBG 0 1 SYS_TA SYS_TEA CHKSTOP SYS GBL SYS HRESET 0 1 S
158. ice is required 60x Bus Interface Signals Page 1 of 3 Signal Name VO Type Description Address Bus Arbitration Signals SYS_BRO 5 0V tolerant Bus Request Indicates the device on the 60x bus associated with this signal is SYS BR1 Int pull up requesting ownership of the address bus SYS BR Int pull up USed for Quad Processor arbitration with external logic SYS_BR3 P P Should be tied to up level 1 if unused SYS BGO o Bus Grant Indicates the master associated with this signal may with proper SYS_BG1 qualification assume mastership of the address bus Address Transfer Start Signals Transfer Start Output Indicates device has started an address tenure and the address bus and transfer attribute signals are valid Only address only operations and snoop operation with programmable TT code are per SYS_TS VO formed Input Indicates a master on the 60x has started an address tenure and the address bus and transfer attribute signals are valid For address tenures that require a data transfer this signal also indicates a request for the data bus Address Bus Signals Address Bus Output Represents the physical address of a cache operation that should be snooped by devices on the 60x bus A 0 is the most signifi cant address bit Input Represents the physical address for the current transaction Internal SYS ADDR 0 31 vO Pull up Address Parity Output Represents one bit of odd parity for each
159. initiated transfers are logged in this register Errors resulting from transfers initiated by a PCI Master or by the DMA controller will result in BITs 17 18 or 19 being set and require software to interrogate additional error registers in the PCI bridge logic and the DMA controller logic BIT 16 CPU to PCI Bus error will also require software to interrogate additional error registers in the PCI bridge logic The bits 22 23 24 25 that are available for read after a CPU1 Machine Check interrupt have the same meaning as errors reported on bits 15 16 19 21 for CPUO Software is responsible for writing zeros to this register in order to clear the bits that are set Reset Value x 0000 0000 Address x FF00 1060 Access Type Read Write 5 wi Q o c o p e e 9 D 2 D 2 o on ao Tr on o o 2 O ODO Oo E n pus u n s lt O Sog 9g o e dx X D ies Pu o Z o eg Q 5 Bu gu iu o e o5 99 L5 So o po z gt oO dE 2 am BD os5e58uuS5S F Gs gE o g e ot a 2 d 5 A 9 o L lt 2 Eu o Teea ygn aana 5 9 98 gd oo0 00 o o o O o 6 aor rio8 9 ogrocxsg u U ss oeWO22egEnu T 2G 2 0 0 FT o a 9 p B28o Oo Fe ge Pao BLS B 9509 2 a 8 9g gud az4 sous g age SESRS5EER ER ER t t Reserved 28 4608 amp 883 80x0805 Reserved Yu yt dud y 444 5499 Y 0 1 213 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
160. ins the upper bits of the SYSTEM address that PCI I O is mapped to Note Address must be aligned on boundary equal to size specified in PCI I O Size register 12 31 Reserved Note Address is decoded only if the Master Enable bit in the PCI Command Register is on 6 26 2000 Page 77 of 209 CPC710 133 IBM Dual Bridge and Memory Controller PHB Configuration Register CTLRW This register is primarily used by software to program device for a particular address translation mode Reset Value x 0200 0000 Address BAR x 000F 7FDO Access Type Read Write 5 ui oO 2 o o D 2 m 2 I o g w a o o o g c c os oe 8 8S gt v g 2 9 S LLI P n g o 2 o olt o gt EB o c or c z oO o o 921 gc E99 za aoge 8 Sze o9 5 m we Oo O09 o0 L Vly 6 ac ac 090 t d djoo o9 o0ccc Reserved 4 i i A A v i 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 Reserved 1 Extensions Enable Read Only 0 Device does not perform extended error recovery 2 64 Bit Mode Enable Read Only 0 Device does not support 64 bit addresses 3 SERR Presentation Read Only 0 PCI Bridge always generates Machine Check if G P SERR driven active 4 Create Interrupt On PHB Detected Error Read Only 0 PCI Bridge always generates Machine Check for PHB detected error ISA Contiguous Mode This bit programs how device translates the first 8 MB of PCI I O space See N
161. ion NY 12533 6351 The IBM home page can be found at http www ibm com The IBM Microelectronics Division home page can be found at http www chips ibm com 6 26 00 p IBM Dual Bridge and Memory Controller Table of Contents eius pee 7 unm 7 sodass a aTa 7 Memory Controller ecce 7 PCI 32 and PCI 64 Bus Bridges ssssesssssessseeeeeneneen nennen nnne nennen sinere nnne n nnne nens 7 rtu ge 7 Conventions and Notation ccceeeeee eee eeeeeeeee cence eee ee ene eeneneaeeeeeeseeeeea sea sn nnn see sni tn nnmnnn nenna nnmnnn nasa nnns nn naa 8 iere nesciun em 8 system Level Block Diagram e M 9 Component Block Diagram eeeeeeeeeeeeeeenee eene nnn enne nnne nennen anne n nnn n RANAS 10 Internal Buffering and Data Flow ueeeeeeeeeeeeeeeeee enne enne nennen nnn nn nnne nennen nnne nnne nnn 11 Pin MORIN AMOI M X 13 aa ECcrHIMeetre 13 Pin SUI ANY soo asia S 13 Signal Pins Sorted by Pin Number c ecccceseeeeeeeeeeeeeeeeeeeneeeeeeeeseeeseeeesneaeseseeseaeseeeeseeaeeeeeeseeeeeeenses 14
162. istered bus exchanger For more information see http www ti com sc MUX_OEA o Output Enable of Data to Device Port A of the external MUX MUX_OEB Output Enable of Data to Memory Port B MUX_CLKEN1B Clock Enable of Data sent to the Memory MUX_CLKEN2B 9 Two signals with same shape for buffering issues MUX_CLKENA1 o Clock Enable of Data sent to Device Clock A1 the first part of the data is stored in the MUX_CLKENA2 external MUX controller and on clock A2 full transfer is made MUX_SEL O Control the MUX circuit of the external MUX controller 6 26 2000 Page 27 of 209 IBM Dual Bridge and Memory Controller PCI 32 Bus Interface Signals 3 3V compliant 5V Signal Name y o Type Description P ADL 0 31 UO 32 bit Multiplexed Address Data A write operation is defined as the transfer of data i from the PCI bus master to a PCI slave device on the PCI Bus P_CBE 0 3 VO Bus Command Byte Enable P_DEVSEL 1 0 Device Select P FRAME lO Cycle Frame Driven by the current master to indicate the beginning and duration of an access P IRDY 0 Initiator Ready ISA Master on the PCI 32 bus P ISA MASTER Pull up Indicates that the CPC710 must automatically P_DEVSEL the current Memory transfer gt and must not translate the PCI address before sending the address to memory Warning To become inactive this signal have to be connected to GND 0 P_LOCK l Reserved for future usage lt is recommended to tie up this signal P MEMACK o Memory Acknowle
163. l assume address only transaction Note SBW Single Beat Write SBR Single Beat Read 6 26 2000 IBM Dual Bridge and Memory Controller Support as Master Yes No No Yes No No No No Yes See ATAS Register Yes No Yes See ATAS Register No No No No No No No Support as Slave NOP NOP Yes NOP Yes treated as 00010 Yes Yes Yes Yes treated as 01010 NOP NOP Yes treated as 01010 Yes Yes treated as 00010 Yes No Yes treated as 01010 Yes Yes treated as 01010 Page 159 of 209 IBM Dual Bridge and Memory Controller Data Gathering The 60x logic gathers data for CPU store transfers to the PCI bus bridges During data gathering single beat stores of up to 32bytes from the CPU are gathered before being sent to the PCI bus bridge unit Data gather ing reduces asynchronous boundary crossings and facilitates data bursting on the PCI bus Data Gathering Algorithm Idle PCI logic went idle Is address gatherable or first Single beat store to PCI Memory Space No Yes Save address for compare lt gt If there are store buffers that have not been transferred to PCI send to PCI logic If there are store buffers that have not been transferred to PCI send to PCI logic Yes Is SYS_TA the data off 60x bus and place in buffer Is
164. ler Page 204 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Initialization Power Up Sequence The power up sequence for the CPC710 is Att 100 mS All PLL inputs are stable and at their final values PLL TUNEO0 0 PLL_TUNE1 1 and TESTIN 0 SYS CLK is stable at or below the target frequency VDDA and Vdd supply are at their final values POWERGOOD input is de asserted Low for Reset PLL RESET input is asserted active Low PCI clocks inputs PCI CLK and PCG CLK are stable at the target frequency Att 0 PLL RESET input is de asserted inactive High PLL LOCK output goes down up to the time that clock are locked to the PLL then is asserted active High indicating the PLL is locked Att 100 uS minimum POWERGOOD input is asserted High HRESET output de asserted by the CPC710 High Bus transactions may begin Boot can begin Note Chip reset is only controlled by the SYS_CLK TESTIN is a manufacturing test input for the PLL PowerUp Sequence SYS CLK J UUUU UU UU UU UU UU UU UU UU UU 100mS PLL RESET In T lock lt 100 uS eH gt 100 uS for PLL Lock PLL_LOCK Out POWERGOOD In SYS_HRESET Out Boot CPU T 0 6 26 2000 Page 205 of 209 IBM Dual Bridge and Memory Controller POWERGOOD Power On Reset Using the system Power On Reset POWERGOOD signal the device resets internally and generates a reset signal to all
165. lly sends a DMA Transfer Read command to the DMA Controller and waits for a dummy read data response The dummy read data is then placed on the processor bus to complete the eciwx transfer on the processor bus The internal flag for special handling of TLBSYNC is set during the eciwx address bus tenure on the pro cessor bus After the DMA Controller receives the DMA Transfer command it issues a Load Pointer command on the internal command bus to the appropriate PCI bus bridge logic unit This transfers the address in XPAR to the PCI bus bridge pointer register The DMA Controller then issues a series of Blit commands or internal Ele mentary Commands from the DMA Controller to the PCI logic to the same PCI bus bridge logic unit that transfers the data The first Blit command contains the memory address stored in the XTAR register The PCI bus bridge logic receives the Blit commands and then executes the transfer For Blit Reads the DMA Controller first determines whether the read from memory requires a snoop transaction If the read is coherent the controller issues a snoop command to the 60x logic If the snoop fails the controller retries the snoop until it passes Once the snoop passes a Blit Read command is transmitted to the PCI bus bridge logic The PCI Bridge logic executes the command and then increments the value in its pointer register by the size of the transfer unless the Address Increment field in the Load Pointer command is set to No I
166. logic will respond with x F000 0000 for a read from x FF20 0000 if SYS L2 HIT signal not driven active 1 No configuration response performed 5 Reserved No SYS L2 HIT Signal Detected Error Disable 6 0 60x logic will generate TEA on the system bus if SYS L2 HIT signal not driven active after AACK 1 No action if SYS L2 HIT detected inactive Disable Data Bus Timeout In the case of timeout the CPC710 activates the CHKSTOP and set bit 20 of the SESR Register see System Error Sta 7 tus Register SESR on page 108 0 Device will signal error if 8ms time out detected from DBG to TA 1 Device will not signal an error for this condition Address Parity Checking Enable 8 0 60x logic will not check address parity on the system bus 1 60x logic will check address parity on the system bus for CPU to the CPC710 access only In case of parity error the CHKSTOP signal is activated Data Parity Checking Enable 9 0 60x logic will not check data parity on the system bus 1 60x logic will check data parity on the system bus for CPU to the CPC710 access only In case of parity error the CHKSTOP signal is activated 10 31 Reserved 6 26 2000 Page 107 of 209 CPC710 133 IBM Dual Bridge and Memory Controller System Error Status Register SESR This register is the primary error status register for device and should be read first after a Machine Check interrupt occurs SYS MACHKO or SYS MACHK1 activated by the CPC710 All errors that result from CPU
167. lows to fit the delay between the Refresh Command and the next Activation This delay has to be at least the tRCmin value specified in the SDRAM datasheet 000 5 bus cycles 001 6 bus cycles 010 7 bus cycles 011 8 bus cycles 100 9 bus cycles 101 10 bus cycles 110 11 bus cycles 111 12 bus cycles Page 180 of 209 6 26 2000 11 12 15 16 17 18 19 20 21 22 23 24 29 30 31 IBM Dual Bridge and Memory Controller Description DRAM Type Must be set to 10 for SDRAM Data Pacing Mode Must be set to 1 for SDRAM Data Mask Mode SDRAM only 0 16 SDCS are available DQM pin of SDRAM devices must be grounded 15 Only eight SDCS are available DQM signal is present on the eight other pins Activate to prevent tRDL violation during Write interrupted by pre charge operations if the device does not guar antee that the data presented in the same time as pre charge is not properly ignored Reserved Must be left to 0 Reserved Must be set to 0 Reserved Must be set to 1 Reserved Must be set to 1 Reserved Must be set to 0 Reserved Must be set to 0 Reserved Must be set to b 00 Reserved Must be set to 0 Reserved Disable Page Mode 0 Memory controller will perform fast page accesses for back to back operations if appropriate 1 Memory controller will perform fast page access only within a burst operation It will NOT perform fast page accesses for back to back bursts even if they occur to the same RAS page
168. m bandwidth 2 31 Reserved Must be set to 0 Page 66 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Interrupt Acknowledge Cycle INTACK A read to the INTACK register generates an Interrupt Acknowledge Cycle on the PCI bus An Interrupt Acknowledge Transaction has no addressing mechanism and is implicitly targeted to the interrupt controller in the system The vector is returned by the interrupt controller when TRDY is asserted Address BAR x 000F 7700 Access Type Read Only INTA v 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 31 This register is a port through to the PCI bus Writes to this register are ignored 6 26 2000 Page 67 of 209 CPC710 133 IBM Dual Bridge and Memory Controller PCI Base Address for I O PIBAR Reset Value x 0000 0000 Address BAR x 000F 7800 Access Type Read Write PCI Base Address Reserved Y vos Y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s 0 11 Description PCI Base Address Contains the upper bits of the PCI base address that PCI I O is mapped to Note Address must be aligned on boundary equal to size specified in PCI I O Size register 12 31 Reserved Page 68 of 209 6 26 2000 PCI Base Address for Memory PMBAR Reset Value x 0000 0000 Address BAR x 000F 7810 Access Type Read Write PCI B
169. mory organizations See Supported SDRAM Organizations on page 177 The SDRAM must comply with the following requirements compatible with the PC100 Specification 1 CAS Latency 2 Burstlength 2 Maximum tRCDmin allowed is 2 Clock cycles Maximum tRPmin allowed is 2 Clock cycles Maximum tRASmin allowed is 5 Clock cycles It is possible to use Extended Data Out Hyper Page DRAM EDO HPM DRAM with IBM Dual Bridge and Memory Controller but this application is not fully supported contact your support for more informations Only one type of RAM can be used in a system it is not possible to mix SDRAM with DRAM devices However different kind of SDRAM organizations can be mixed 60x bus operation is limited to 75 MHz when using EDO DRAM and to 100 MHz when using SDRAM 6 26 2000 Page 169 of 209 IBM Dual Bridge and Memory Controller Memory Performance for Cache Line Operations ECC Active Pipeline Levels Page 170 of 209 Read Burst Write Burst Read Burst Write Burst Operation Initial Sus tained Initial Sus tained Initial Sus tained Initial Sus tained Page Miss Page Hit Page Miss Page Hit Page Miss Page Hit Page Miss Page Hit CAS Latency 2 100 MHz 160 MB s 16 1 2 1 160 MB s 16 1 2 1 160 MB s 16 1 2 1 533 MB s 3 1 1 1 160 MB s 16 1 2 1 228 MB s 10 1 2 1 400 MB s 4 1 2 1 564 MB s 3 1 1 1 2 1 1 1 2 1 1 2 246 MB s
170. n the External interrupt INT2 is raised Mode of operation of the DMA A complete DMA transfer can be done in the following modes that can be programmed in the DMA Global Control Register GSCR Elementary Extended Mode The DMA controller runs with an elementary block of up to 4 KB of data to transfer In the Extended Mode an automatic address increment is performed at the end of each elementary DMA transfers Up to 65 000 iterations or loops of elementary DMA s can be programmed with address incre ments to transfer up to 256 MB of data in a single DMA The end of transfer DMA interrupt INT2 is raised only after completion of the multiple elementary DMAs loops Starting the DMA Write in the XTAR register The write in the XTAR register results in the start of a DMA operation eciwx or ecowx instruction DMAs are initiated by either a eciwx read Data from Memory to PCI or ecowx write PCI to Memory instruction from the processor and ended by an External Interrupt command The controller uses an elemen tary burst of 32 Bytes on the PCI bus to facilitate interleaved PCI bus operations The eciwx and ecowx instructions use the processor s internal address translation logic to present real addresses on the system bus This eliminates the need for external hardware to translate virtual addresses and for software to calcu late real addresses Because the DMA is virtual no software overhead is required for pinning system memory that
171. n errors on pages marked read only Software ensures proper implementation of the DMA operation including address alignments and page boundaries The device aborts a DMA transfer when any of the following conditions are detected TLBSYNC operation detected internal commands are completed before termination Improper DMA transfer setup Second DMA transfer initiated when one is already in progress The transfer crosses a page boundary Page 200 of 209 6 26 2000 IBM Dual Bridge and Memory Controller DMA Transfer Registers Several registers support the DMA transfer process They are mapped to two different address spaces so the software can mark the x FF1C xxxx range as user space and the FF1E xxxx range as privileged space This provides protection needed to allow the eciwx and ecowx instructions to be executed by application level soft ware The registers are listed in the following table and are described in DMA Registers Space on page 130 DMA Transfer Register Summary User Privileged Register Description Address Bits Mode Address Bits Mode GSCR FF1C 0020 0 31 R FF1E 0020 0 31 R W Global Control Register GSSR FF1C 0030 0 31 R FF1E 0030 0 31 R Global Status Register XSCR FF1C 0040 0 31 R W FF1E 0040 0 31 R W DMA Transfer Control Register XSSR FF1C 0050 0 31 R FF1E 0050 0 31 R DMA Transfer Status Register 0 3 R 0 3 R W XPAR FF1C 0070 FF1E 0070 PCI Address Register 4 31 R W 4 31 R XWAR FF1
172. ncrement Blit Write commands are handled in same way except the transfer is from I O to System Memory Note The DMA Controller should wait a minimum of eight cycles before reissuing snoop commands after a snoop fail response After the transfer is complete the controller signals the 60x logic by activating UXI XFER DONE for one cycle The controller then issues a Write with Kill to the address specified in XWAR register to indicate to soft ware that the transfer is complete The controller issues a Kill Cache to the 60x logic and upon receiving a clean response issues a Write command to system memory The write to memory need only be a single beat write to the bytes reserved for DMA transfer status 6 26 2000 Page 203 of 209 IBM Dual Bridge and Memory Controller Special Boundary Conditions Due to queueing in the 60x logic a pulse could be placed on the TLBSYNC line to the DMA Controller before the controller receives an ecowx or eciwx In this case the controller waits until it receives an ecowx or eciwx and then immediately terminates the DMA transfer When two DMA transfers overlap the controller ignores the TLBSYNC pulse if a DMA transfer is nearly complete However because the 60x logic could have an eciwx or ecowx queued the controller would have to remember the TLBSYNC pulse to terminate the second DMA transfer properly To do this the 60x logic indicates the presence of an eciwx or ecowx instruction in its queue to the control
173. nd Memory Controller responds to is programmable o xoosom 6 26 2000 Page 93 of 209 CPC710 133 IBM Dual Bridge and Memory Controller System Registers List Page 2 of 3 Address x FF00 1310 x FF00 1320 x FF00 1330 x FF00 1340 x FF00 1350 x FF00 1360 x FF00 1370 x FF00 1400 x FF00 1410 x FF00 1420 X FF00 1424 to x FF00 1FFF x FF00 2000 to FF17 FFFF DMA Registers User Privilege X FF18 0000 to x FF1C 001F x FF1C 0020 x FF1C 0030 X FF1C 0040 x FF1C 0050 x FF1C 0070 x FF1C 0090 x FF1C 00A0 x FF1E 0020 x FF1E 0030 x FF1E 0040 x FF1E 0050 x FF1E 0070 x FF1E 0090 x FF1E 00A0 x FF1E 00A4 to x FF1F FFFF Name MCER1 MCER2 MCER3 MCER4 MCER5 MCER6 MCER7 SIORO SIOR1 GSCR GSSR XSCR XSSR XPAR XWAR XTAR GSCR GSSR XSCR XSSR XPAR XWAR XTAR System Standard Configuration Registers x FF20 0000 x FF20 0004 X FF20 0008 to x FF20 0014 RO Read Only Register Byte accesses allowed WO Write Only Register o xoos som Page 94 of 209 DCR DID Reserved Use Memory Configuration Extent Register 1 Memory Configuration Extent Register 2 Memory Configuration Extent Register 3 Memory Configuration Extent Register 4 Memory Configuration Extent Register 5 Memory Configuration Extent Register 6 Memory Configuration Extent Register 7 SIO Register 0 DIMM PDs Reserved SIO Register 1 Planar
174. nerating a checkstop 1 Sets appropriate bit s in SESR 2 Drives CHKSTOP active until power on reset The following table describes the error handling performed for CPU initiated transactions The 60x logic drives SYS MACHK signals not the PCI bridge logic or the memory control logic Error Handling for CPU Initiated Transactions Page 1 of 4 Operation Error Mode Action Notes Disabled No action taken i Set No Select error bit in SESR Access not directed Addressing Error Set error address in SEAR SYS L2 HIT not Aem to device driven active Enabled Sos rll 2 0 Signal Machine Check with PGCHP 26 0 Signal Machine Check with SYS MACHK Disabled Inhibit timer no action taken Bus Time out Time expired from Set bus time out error bit in SESR Access to device SYS AACK active to Enabled Set checkstop generated bit in SESR first SYS_TA Set error address in SEAR Signal Checkstop Access to a reserved or non implemented Terminate CPU transaction normally 1 address Alignment or size Access to internal 9 device facilities Store to read only register Load from write only register 1 Adummy 0 is returned for read operation For write data is ignored Page 164 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Error Handling for CPU Initiated Transactions Page 2 of 4 Operation Error Mode Single bit error Don t care Access to system memory Normal Double bit error Diagnostic
175. nne enne nn nnam nnn an nnnm nnns nennen 220 IbiIBIi DM 220 AC Timing Eidem 221 60x Bus TIMING Specification inccr erect enn rete cerni ne ec cx nuno ecc cq uaa onet ek dra na RENE 222 PCI 32 bit Bus Timing Specification eeeeeeeeeeee eene unten nn 223 PCI 64 bit Bus Timing Specification eeeeeeeeeeee eene nennen nennen 224 SDRAM Interface Timing Specification cesses eeeeeen nennen nnne nnmnnn nnns 225 FLASH Interface Timing Specification eeeeeeeeeeeeeeeee enenatis rn 226 Packaging Informati n 5 icoucc nnixid xia xr aida Ebad kd ax da ka wECR exkl law buc FECE vas V x bad idu uU E VR 227 Package Dimensions Emee 227 References rc 228 229 Revision LOO M 229 Page 6 of 209 Table of Contents 6 26 2000 Overview Features Upto 100 MHz PowerPC 60x 64 bit bus Supports 100 MHz SDRAM including PC100 Upto 2 MB flash Boot ROM support 32 bit 33 MHz 64 bit 33 66 MHz async dual bus Reads two external 32 bit registers PreP compliant design One channel DMA controller 3 3 volts 5 5
176. nous DRAM components used The following table describes how to program the MCCR Register Mem ory Controller Control Register MCCR on page 122 Bit s Description Global System Memory Address Space Enable 0 Device will not respond to addresses specified in Memory Configuration Extent Register MCERx 1 System memory address space enabled Diagnostic Mode This bit is used to control presentation of double bit ECC errors to the system This bit is primarily intended for use in mem ory testing at power on time Software can use this bit when testing memory and or ECC logic in order to avoid the hard ware generating a machine check for double bit ECC errors The error however is still logged into the MEAR 0 Normal Mode Multi bit ECC error will generate Machine Check 1 Diagnostic Mode Multi bit ECC does NOT generate Machine Check logged in MEAR amp MESR SDRAM Initialization Status read only 0 SDRAM initialization is not completed 1 SDRAM initialization is completed ECC Mode This field provides software with a means to control ECC generation and checking b 01 is provided to allow software direct read write access to the ECC byte that is associated with every doubleword of data stored in memory and also provide a mechanism to verify the memory controller s ECC generation and checking logic In this mode byte lane 0 data MSB of a double word is written to the ECC byte instead of the normal ECC code byte Data byte
177. nput na ue Vpp 0 6 V Ve Input Max Allowable Overshoot 5 5 V 5 5 0 V receivers Vas Input Max Allowable Undershoot 0 6 V 3 3 V receivers Viau Input Max Allowable Undershoot 0 6 V 5 5 0 V receivers Vouros Output ps a Vp 0 6 V oux Output Max Allowable Overshoot 55 V 5 5 0 V receivers VomAus Output Max Allowable Undershoot 0 6 v 3 3 V receivers Ty Die Junction Temperature 20 105 C 6 26 2000 Page 219 of 209 IBM Dual Bridge and Memory Controller Driver Receiver Specifications DC Voltage Specifications Driver Receiver 3 3V LVTTL Driver 5 0 V tolerant LVTTL Driver 3 3V LVTTL Receiver 5 0 V tolerant LVTTL Receiver 1 Definition of Terms Maximum Allowable Up Level The maximum voltage that may be applied without affecting the specified reliability Cell MAUL Function MAUL V MPUL V Vpp TTL Bo 8 0 V to 3 6 V TTL 5 50 Vos Vpp TIL 0 6 V Vop TTL 5 50 5 50 LPUL V 2 40 2 40 2 00 2 00 MPDL V 0 40 0 40 0 80 0 80 functionality is not implied Maximum Allowable applies to overshoot only MPUL level LPUL MPDL level LPDL MADL LPDL V 0 00 0 00 0 00 0 00 MADL V Notes 0 60 1 0 60 1 0 60 1 0 60 1 Maximum Positive Up Level The most positive voltage that maintains cell functionality The maximum positive logic Least positive Up Level The least positive voltage that maintains cell functionality The minimum positive log
178. nternal SYS DATA 0 63 yo Pull up 6 26 2000 IBM Dual Bridge and Memory Controller Description Transfer Size Output signals and the TBST signal Indicate the data transfer size of the operation Device sets these signals to a value stored in the ATAS register for the operations it initiates Input signals and the TBST signal For normal memory accesses indicate the data transfer size of the operation For the DMA instruc tions eciwx and ecowx they indicate the 4 bit Resource ID RID of the DMA operation TBST TSIZO TSIZ2 Transfer Burst Output signal and the TSIZ signals Indicate the data transfer size of the operation Device sets this signal according to the bit in the ATAS register for operations it initiates Input signal For normal memory accesses indicates a burst transfer is in progress For DMA instructions eciwx and ecowx the input signal and the TSIZ signals indicate the 4 bit Resource ID RID of the DMA operation TBST TSIZO TSIZ2 Global Always asserted by the CPC710 for transactions that it initiates to indi cate that all devices on the 60x bus must snoop the transaction Since the CPC710 asserts this signal only when it is PowerPC bus address master no contention is possible with PowerPC 750 or 7400 Input output GBL signal con nected to SYS GBL Address Acknowledge Indicates the address tenure is complete and the ARTRY sampling window ends on the following bus cycle Address bus and transf
179. oes NOT generate Machine Check logged in MEAR amp MESR SDRAM Initialization Status read only 2 0 SDRAM initialization is not completed 1 SDRAM initialization is completed ECC Mode 00 Normal generation and checking of ECC codes 3 4 01 ECC check disabled Byte lane 0 routed to from ECC check field Data byte 0 forced to all zeros 10 ECC check disabled Normal routing of data and normal ECC code generation 11 Reserved Row Cycle Time for SDRAM Auto refresh tuc 000 5 bus cycles 001 6 bus cycles 010 7 bus cycles 5 7 011 8 bus cycles 100 9 bus cycles 101 10 bus cycles 110 11 bus cycles 111 12 bus cycles 8 9 DRAM Type Must be set to 10 for SDRAM 10 Data Pacing Mode Must be set to 1 for SDRAM Data Mask Mode SDRAM only 0 16 SDCS are available DQM pin of SDRAM devices must be grounded 11 1 Only eight SDCS are available DQM signal is present on the eight other pins Activate to prevent tRDL violation during Write interrupted by pre charge operations if the device does not guar antee that the data presented in the same time as pre charge is not properly ignored 12 15 Reserved Must be left to 0 16 Reserved Must be set to 0 17 Reserved Must be set to 1 18 Reserved Must be set to 1 19 Reserved Must be set to 0 20 Reserved Must be set to 0 Page 122 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Bit s Description 21 22 Reserved Must be set to b 00 23 Reserved Must be set to 0 24 29
180. of 4 Signal Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground INT INT2 Locator MADDRO EVEN MADDR 1 MADDR2 MADDR3 MADDR4 MADDR5 MADDR6 MADDR7 MADDR8 6 26 2000 Pin ORO3 0R07 OR11 OR14 OR15 OR19 OR23 OT11 0T15 OW03 OW07 ow11 0W15 0W19 0W23 AB13 ACO3 ACO7 AC11 AC15 AC19 AC23 AD02 AD24 AE01 AE25 0G23 AC16 0E23 0A01 0G10 0J10 0E08 0D07 0E10 0C10 0B08 0A07 0B07 Signal MADDR9 MADDR10 MADDR11 MADDR12 MADDRO ODD MDATAO MDATA1 MDATA2 MDATA3 MDATA4 MDATAS5 MDATA6 MDATA7 MDATA8 MDATA9 MDATA10 MDATA11 MDATA12 MDATA13 MDATA14 MDATA15 MDATA16 MDATA17 MDATA18 MDATA19 MDATA20 MDATA21 MDATA22 MDATA23 MDATA24 MDATA25 MDATA26 MDATA27 MDATA28 MDATA29 MDATA30 MDATA31 MDATA32 MDATA33 Pin 0A06 0B06 0C04 OF04 0G05 0U07 0V07 0U08 0TO7 0V03 ORO1 ow04 0M07 0U04 ONO8 ONO7 ORO2 ORO4 0P01 OP03 0P05 OTO1 0V04 0U06 OTO9 O0TO8 0Y05 ORO5 0V02 0VO01 0TO5 0T03 0T10 0V05 ORO8 0V06 0U01 0U03 0R09 Signal MDATA34 MDATA35 MDATA36 MDATA37 MDATA38 MDATA39 MDATA40 MDATA41 MDATA42 MDATA43 MDATA44 MDATA45 MDATA46 MDATA47 MDATA48 MDATA49 MDATAS50 MDATA51 MDATA52 MDATAS53 MDATA54 MDATAS55 MDATA56 MDATA57 MDATA58 MDATA59 MDATA60 MDATA61 MDATA62 MDATA63 MDATA64 MDATA65 MDATA66 MDATA67
181. om the PCI 64 or from the CPU in configuration mode The CPU can only execute the SET of INTA INTB INTC INTD when writing in Register INT SET at address BAR x 000F 8310 Reset Value x 0000 0000 Address x 68 Access Type Read Write Reserved Set add it 4 Vv Y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit s Description 31 4 Reserved RESET Interrupts ile Resets the bit corresponding to one PCI 64 interrupt 0 No action 3 0 Bito G_INTA Bit1 G_INTB Bit2 G_INTC Bit3 G_INTD 6 26 2000 Page 63 of 209 CPC710 133 IBM Dual Bridge and Memory Controller Specific PCI Host Bridge Registers Specific PCI Host Bridge Register List Real Address Name Use Page Note BAR x 000F 6110 PSEA PCI Slave Error Address 65 1 BAR x 000F 6120 PCIDG PCI Diagnostic Register 66 BAR x 000F 7700 INTACK Interrupt Acknowledge Cycle 67 1 BAR x 000F 7800 PIBAR PCI Base Address for I O 68 BAR x 000F 7810 PMBAR PCI Base Address for Memory 69 BAR x 000F 7EFO CRR Component Reset Register 70 BAR x 000F 7F20 PR Personalization Register 71 BAR x 000F 7F30 ACR Arbiter Control Register 73 BAR x 000F 7F40 MSIZE PCI Memory Address Space Size 74 BAR x 000F 7F60 IOSIZE PCI I O Address Space Size 75 BAR x 000F 7F80 SMBAR System Base Address for PCI Memory 76 BAR x 000F 7FCO SIBAR System Base Address for PCI I O 77 BAR x 000F
182. oncontiguous I O Address Mode Enabled 5 on page 145 for additional details 0 ISA space is contiguous 1 ISA space is not contiguous 6 ISA Compatibility Mode Read Only Device contains an external pin for this function P ISA MASTER 7 Reserved 8 Reserved 9 31 Reserved Page 78 of 209 6 26 2000 PHB Configuration Register CTLRO IBM Dual Bridge and Memory Controller This register is the primary indicator to software that device contains the PCI extensions specified in the IBM PHB architecture It also provides bridge capability information to software Reset Value PCI 32 x 9006 0000 PCI 64 x 9004 0000 Address BAR x F000 7FEO Access Type Read Only 1 2 9 Q T 3 t S o0 8 2 t E de 2 o o p 77 amp tS E o 2 5 o o Q o g S D z d o 2 o o o o c o o 9 L g 9 22375 o 22088 2 o O 5 9g E m i 9 na Reserved 2 Reserved yy ids vov Yo Y 0 1 2 3456 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 1 PHB Extension Support 10 Device supports error detection extensions but NOT error recovery 2 64 Bit Mode Support 0 NOT supported 3 Lock Support 1 Full support of PCI lock bus cycles 4 Executable PCI Memory Support 0 NOT supported 5 Dual Address Cycle Support 0 NOT supported 6 15 Reserved 16 19 Number Of Interrupts Supported 0000 No interrupts supported 20 31 Reserved 6 26 2000 Page 79 of 209 CPC710 133
183. ontrol of the PLL Default 1 Reset and Bypass mode enable of the PLL Time base enable for refresh DRAM cycles It is recommended to have a Clock in the 7 8125 MHz range 128ns period on input pin PLN_RTC_CLOCK This clock is necessary for the DRAM refresh cycles and other internal timers such as soft reset time software power on reset time bus timeout and SDRAM initialization phase time Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Must be set to 1 Reserved JTAG Clock JTAG Data Input JTAG Test Data Output JTAG Test Mode select Asynchronous JTAG Reset Reserved Must be set to 0 JTAG Compliance Enable Down level 20 Isolate the JTAG from the system reset signal POWERGOOD Up level 21 the POWERGOOD going to 0 Resets the JTAG Reserved Analog Vpp for the PLL Filtering on this 3 3V power supply is necessary to avoid problems with the on chip PLL 6 26 2000 IBM Dual Bridge and Memory Controller SIO Signals Signal Name VO Type Description FLASH_OE O Output Enable FLASH ROM FLASH WE O Write Enable FLASH ROM PRES OEO O Output Enable Presence detect PD buffer 0 PRES OE1 O Output Enable Presence detect PD buffer 1 XADR_LAT O Latch Signal For SIO address register XCVR_RD O Address Direction SIO address bus Reserved Signals Signal Name VO Type Description RESERVED1 External Pull Up recommended RESERVED2 O External Pull Up recommended RESERV
184. or register initialization is not complete T Bank is present and decoded by device 1 3 Reserved R W Start Address For Bank Bits 0 10 Defines the beginning address of this bank Contains bits 0 10 of the 32 bit real address Address restricted to a boundary equal to the size of the bank 15 Reserved R W Page 126 of 209 6 26 2000 Bit s 16 25 26 29 30 31 6 26 2000 Description Extent Size Code For Bank xS3FF x 3FB x 3F3 x 3ES x 3C3 x 383 x 303 x 203 x 003 x 002 x 000 Reserved Reserved 4MB 8 MB 16 MB 32 MB 64 MB 128 MB 256 MB 512 MB 1 GB SDRAM Addressing Organization b 0001 b 0010 b 0011 b 0100 b 0101 b 0110 b 0111 b 1000 b 1001 b 1010 b 1011 b 1100 b 0000 Reserved 11 8 2 Row Col Bank select Address lines 11 9 1 11 10 1 12 8 2 12 10 2 13 8 1 13 8 2 13 9 1 13 10 1 11 8 1 12 8 1 12 9 1 IBM Dual Bridge and Memory Controller All other supported organizations see Supported SDRAM Organizations on page 177 Page 127 of 209 CPC710 133 IBM Dual Bridge and Memory Controller System I O Register 0 SIORO This register is user defined However it has been introduced in the PowerPC chip support to provide the memory DIMM presence detect pins for all four pairs of DIMM sockets Device supports a maximum of four pairs or eight DIMMs The DIMM pairs must be of
185. ors When device detects a write to this register the corresponding SYS SRESET 0 or 1 signal is driven active for a minimum of eight RTC_CLK clocks Reset Value x 0000 0000 Address x FF00 1040 Access Type Write Only o Soft Reset Control for ARB Level 0 lt Soft Reset Control for ARB Level 1 Reserved Y Y 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description Soft Reset Control for ARB Level 0 0 0 Writing O to this bit has no effect 1 Writing 1 to this bit will initiate a pulse on the SYS SRESETO signal Soft Reset Control for ARB Level 1 1 0 Writing O to this bit has no effect T Writing 1 to this bit will initiate a pulse on the SYS SRESETI signal 2 31 Reserved Page 106 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Error Control Register ERRC This register controls how the 60x interface logic responds when detecting an error Reset Value x 0000 0000 Address x FF00 1050 Access Type Read Write o a S a E a o 3 wi E B g o B X odi o5 9 asts oo c c z o u S 5DE 6 DB S ot 2 3 e 50 2 T O0 RC 5 5S O oH Ao amp SSP o Bs ago g 5 s Reserved 29 SEBS Reserved Y Vi 4 vide Y 012 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 3 Reserved 60x Bus Configuration Cycle Timeout Disable 4 0 60x
186. pace Size PCI I O Address Space Size System Base Address for PCI Memory System Base Address for PCI I O Configuration Register R W Configuration Register R O CONFIG ADDR CONFIG DATA PCI to System CPU Address space Size CPU Base Address Register System Base Address Register for PCI 32 Bottom of Peripheral Memory space with potential dead lock Top of Peripheral Memory space with potential deadlock Bottom of Peripheral I O space with potential deadlock Top of Peripheral I O space with potential deadlock PCI 64 Reset Interrupt INT1 Addressed Register Set of G INTA G INTB G INTC G INTD on PCI 64 Channel Status Register Processor Load Store Status Register Page 65 66 67 68 69 70 71 78 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Note 6 26 2000 IBM Dual Bridge and Memory Controller System Registers List Page 1 of 2 Address Name Use Page Notes x FF00 0000 to x FF00 0007 Reserved Standard System Registers x FF00 0008 PIDR Physical Identifier Register 96 x FF00 000C CNFR Connectivity Configuration Register 97 x FF00 0010 RSTR Connectivity Reset Register 98 x FF00 00E8 SPOR Software POR Register 99 Specific System Registers x FF00 1000 UCTL Universal Control Register 100 x FF00 1010 MPSR Multi Processor Semaphore Register 102 x FF00 1020 SIOC System I O Control 103 x FF00 1030 ABCNTL 60x Arbiter Control Register 104 x FFOO 1040 SRST CPU So
187. r is written by software to indicate to the PCI bridge where its register space is located in the 4 GB system addressing space There are no restrictions placed on the value of this register other than it must not overlap other extents defined for the system Reset Value x 0000 0000 Address x FF20 0018 Access Type Read Write Upper Bits of 1MB Address Bridge Register Space Reserved Y vov v 0 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 11 Upper Bits of 1 MB Address for Bridge Register Space 12 31 Reserved Assumed to be X 0 0000 Note The start address is assumed to be on a 1 MB boundary Page 140 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Device Specific Configuration Space The registers listed in this section can only be accessed with configuration cycles on the 60x bus directed to the specific PCI bridge PCI BAR Enable Register PCIENB This register provides a mechanism for software to disable the PCI bridge logic from decoding the address space pointed to by the BAR This register is primarily used at power on time when the BAR has not been ini tialized Reset Value x 0000 0000 Address x FF20 1000 Access Type Read Write Q o o 77 g t o O O A o 9 iG Reserved Reserved Lv vov vov v 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
188. register contains x 00 which disables the retry counter Page 60 of 209 6 26 2000 Deadlock Retry Counter DLKRETRY for PCI 32 Only Reset Value x 00 Address x 51 Access Type Read Write DLKRETRY 4 Y 7 6 5432 1 0 Bit s Description IBM Dual Bridge and Memory Controller Available only for the PCI 32 this 8 bit counter is used to limit the number of Retries in the case of an access in a dead a lock area space defined with the BPMDLK TPMDLK or BIODLK TIODLK registers 6 26 2000 Page 61 of 209 CPC710 133 IBM Dual Bridge and Memory Controller Set Addressed Interrupt IT ADD SET This is a Virtual Register When addressed the interrupt signal INT1 is set goes to 0 The SET can be done from the PCI 64 or from the PowerPC CPU in configuration mode Only the PowerPC CPU can reset the interrupt INT1 by writing a 1 in the IT ADD RESET interrupt reset register Reset Value x 0000 0000 Address x 64 Access Type Write Only Reserved Set add it Y vv Y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 O0 Bit s Description 31 8 Reserved Set add it 7 0 1 Writing a 1 in one of these 8 bits SETS the interrupt signal INT1 0 No action Page 62 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Reset PCI 64 Interrupt INT RESET Resets one of the posted interrupt G INTA G_INTB G INTC G INTD on the PCI 64bit bus Reset can be done fr
189. rror PCI 64 System Parity Error Stop Asserted by the target to request the master to stop the current transaction Target Ready Asserted by the target when ready to receive data PCI 64 Interrupt A PCI 64 Interrupt B PCI 64 Interrupt C PCI 64 Interrupt D PCI 64 Arbiter Asserted 21 when the device is the PCI 64 arbiter Local Reset Asserted by PCI 64 reset and special conditions Page 29 of 209 IBM Dual Bridge and Memory Controller Test and Clock Signals Signal Name SYS CLK PCI CLK PCG CLK PLL LOCK PLL TUNEO PLL TUNE1 PLL RESET PLN RTC CLOCK CE1 A CE1 B CE1 C1 CE1 C2 DI DI2 CEO IO CEO TEST RI SCAN GATE TCK TDI TDO TMS TRST TESTIN CE TRST TESTOUT VDDA Page 30 of 209 yo Internal Type Pull down Pull up Pull up Pull up Pull up Pull up Pull up Pull up Pull up Pull down Pull down Pull down Pull up Pull up Pull up Pull up Pull up Pull up Pull up Description System Reference Clock It is provided to the CPC710 and used as a clock for the 60X bus and thus the Pow erPC processor and for the SDRAM signals that are all synchronous This clock is not synchronized with the PCI 32 and the PCI 64 independent clocks Main Clock Input for the PCI 32 bit bridge up to 33 MHz Main Clock Input for the PCI 64 bit bridge up to 66 MHz Output indicating a locked state for the PLL Loop stability tuning control of the PLL Default 0 Loop stability tuning c
190. ry Addressing Model FPHB Mode System Memory Space 4GB System Memory PCI Space Memory or I O Space is selected by bit 7 of PSSIZE Programmable Registers BARPS Page 148 of 209 PCI Memory or PCI I O PSSIZE PSBAR 6 26 2000 IBM Dual Bridge and Memory Controller 60x Interface Overview The 60x interface ties the CPC710 to the PowerPC 60x system bus It performs the following functions Arbitration Configuration Processor load store address decoding PCI to Memory access Snoop operations Sync EIEIO processing Endian translation Reset logic operations Time base functions 6 26 2000 Page 149 of 209 IBM Dual Bridge and Memory Controller Endian Support The Data in a system built with the CPC710 are in the following mode System Memory Big Endian PCI space Little Endian Bytes are always swapped inside the CPC710 PowerPC Processor Big Endian However the Little Endian mode is also supported for the processor but the CPC710 internally swap bytes and unmundge address before sending it to the memory or the PCI bus CPC710 Endian Logic PowerPC Big and Little Endian CPU A 60x BUS Address Data Y PCI 64 Bridge Logic Unmunge and Byte Swap 64 Little Endian On gt Byte
191. ry Controller SDRAM Input Signal Frequencies Maximum Input Capacitance Signal Name Running Frequency SDRAM Note 1 SDCS BUS CLK 5pF SDCKE BUS_CLK 5pF MDATAO 1 BUS CLK 2 7pF MADDRO 1 BUS CLK 2 5pF BS BUS_CLK 2 5pF SDRAS BUS_CLK 2 5pF SDCAS BUS_CLK 2 5pF WE BUS_CLK 2 5pF SDDQM BUS_CLK 2 5pF 1 These are usual values for a single SDRAM chip V 3 3V T 25C f 1MHz 2 These are usual values for an unbuffered DIMM 8 x 1M x 16 V 3 3V T 25C f 1MHz 3 Signal is critical runs at full speed DIMM Row Address Derivation for SDRAM x72 Width DIMM DIMM Row Address Addressing 42 11 10 9 8 7 6 5 13 11 2 4 7 9 10 11 12 13 14 13 10 2 4 7 9 10 11 12 13 14 13 9 2 4 7 9 10 11 12 13 14 13 10 1 4 7 9 10 11 12 13 14 13 9 1 5 7 9 10 11 12 13 14 13 8 2 6 7 9 10 11 12 13 14 13 8 1 6 7 9 10 11 12 13 14 12 10 2 7 9 10 11 12 13 14 12 9 2 7 9 10 11 12 13 14 12 8 2 z 7 9 10 11 12 13 14 12 91 7 9 10 11 12 13 14 12 8 1 z 7 9 10 11 12 13 14 11 10 1 9 10 11 12 13 14 11 91 i s 9 10 11 12 13 14 11 8 2 z z 9 10 11 12 13 14 11 8 1 9 10 11 12 13 14 Page 178 of 209 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 30pF 50pF 15pF 50pF 50pF 50pF 50pF 50pF 50pF 3 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Unbuffered DIMM Note 2 2 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 Note 19 19 19 1
192. scribe the transaction types supported by the device on the processor bus The device supports the PowerPC 604 critical double word burst transactions Non Burst Transactions SYS TBST 1 SYS TSIZ 0 2 A 29 31 Definition Note 000 000 111 8 byte transfer 001 000 111 1 byte transfer 010 000 111 2 byte transfer 011 000 111 3 byte transfer 100 000 111 4 byte transfer 101 000 111 5 byte transfer 110 000 111 6 byte transfer 111 000 111 7 byte transfer 1 For transfers where the number of bytes to transfer cross a doubleword boundary the device will truncate the transfer size to avoid crossing a doubleword boundary Burst Transactions SYS TBST 0 SYS TSIZ 0 2 A 27 31 Definition Support Notes 000 XXXXX 8 Byte transfer No 2 00xxx 16 byte transfer beginning on 32 byte boundary TBD o ss 16 byte transfer beginning on odd doubleword No boundary 001 10xxx 16 byte transfer beginning on odd 16 byte boundary TBD ddxx 16 byte transfer beginning on odd doubleword No boundary 00xxx 32 byte transfer beginning on 32 byte boundary sx 32 byte transfer beginning on odd doubleword 13 boundary 010 Yes 10xxx 32 byte transfer beginning on odd 16 byte boundary 1 3 TE 3ex x 32 byte transfer beginning on odd doubleword 13 boundary 1 For transfers that cross a 32 byte boundary the device will wrap to the beginning of the 32 byte block to satisfy the data transfer 2 Unpredictable results will occur if this transfer size is attempted on
193. scribed in the PCI 2 1 specification PCI Address Data Bus for TYPE 0 Configuration Cycles 31 30 24 23 16 15 1110 87 210 CONTIG ADDRESS E Reserved Bus Number Device Function Register No 0 0 Decoded in the CPC710 PCI Addr Data Bus Only One 1 Function Register No 00 in configuration phase 31 11 10 0 Device 1 Device 2 Device 3 000000000000000000001 000000000000000000010 000000000000000000100 External IDSEL Signals Logic on PCI 32 and PCI 64 CONFIG_ADDRESS 14 15 00 only In order to decrease loading of the AD lines the CPC710 also indirectly supports up to eight separate IDSEL lines It relies on external 3 8 decoders to provide a unique signal for each device on the bus The CPC710 drives external address bits 13 through 11 Little Endian using the three P G_CFG signals It also drives PCI address data bus bits 31 through 11 as shown in the above table The recommended external connection for the 3 8 decoders is shown below External IDSEL Signal Logic for PCI 32 3 8 CPC710 IDSELO Decoder g IDSELI Not Connected CONFIG_ADDRESS 11 P CFG0 sn 2 IDSEL2 CONFIG_ADDRESs 12 P CFG1 gp SEL cowriG AppRESs 13 P CFG2 c 5 IDSEL5 See Device Table s IDSEL6 7 IDSEL7 Type 1 Configuration Cycles For TYPE 1 configuration cycles the CPC710 directly copies the contents of the CONFIG_ADDRESS regis ter to the Address Data signals on the PCI bus
194. sfer sizes will result from an unaligned 4 byte access to an odd address 2 These transfer sizes are not supported by any of the processors 3 These cells apply only to the PowerPC 604 which performs unaligned LE transfers Because the device cannot determine the processor s Endian state software must write to the Arbiter Control Register bit 9 at the same time the processor HID register bit is updated If the processor is operating in BE mode bit 9 must be set to 0 to prevent the device from unmunging or byte swapping the processor s data If the processor is operating in LE mode bit 9 must be set to 1 to unmunge the address as specified in Little Endian Address Unmunge Equations below and to swap the data bus bytes as specified in Data Bus Byte Swap for Little Endian below Page 152 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Little Endian Address Unmunge Equations Transfer Size Equation to Convert to Address 1 Byte ADDR 29 31 XOR 111 2 Byte ADDR 29 31 XOR 110 and 1 81 1 3 Byte ADDR 29 31 XOR 101 4 Byte ADDR 29 31 XOR 100 8 Byte none Data Bus Byte Swap for Little Endian Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 A B C D E F G H 60x Data Bus LLEEELELEEEEEELEEEEEELELEEELLELES CLLELEELLELEEELLEEEEELLELELLL LT I 0 78 15 16 23 24 31 0 78 15 16 23 24 31 Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 Internal H G F E D C B A Data
195. ss Register priv Reserved Device Characteristics Register Device ID Register Base Address Register PCI BAR Enable Register Reserved FLASH ROM Up to 2 MB Page 129 130 131 132 133 135 136 137 130 131 132 133 135 136 137 138 139 140 141 Notes 6 26 2000 IBM Dual Bridge and Memory Controller Standard PCI Configuration Registers The following registers are defined as Little Endian LE ordering Therefore for software running in Big Endian BE mode any access to these registers that is not a single byte access must utilize the load store byte reversal instructions when accessing these registers Software running in LE mode can use the normal load and store instructions There is one set of registers for the PCI 32 bit and one set for the PCI 64 bit The relative address or register number of these registers is specified in the CFGA Configuration Address PCI Configuration Space Device ID Vendor ID Status Command Subclass Code Prg Intf Rev ID Header Latency Cache Type Timer Line Size PSBAR for PCI 64 only Reserved for Base Address Registers Reserved Reserved for Expansion ROM Base Addr Reserved Maximum Latency Minimum Grant Interrupt Pin Interrupt Line Reserved Disconnect Counter Subordinate Bus Numb Bridge Bus Numb Reserved Dead Lock Retry Retry Counter Reserved
196. ster Set PCI bus time out error in CSR register Save encoded ARB level in CSR register Signal Machine Check with MACHK 2nd PCI bridge logs errors same as CPU initiated 2nd PCI bridge does NOT drive MACHK pin Set PCI PCI error bit in CSR register Save encoded ARB level in CSR register Save PCI address in PSEA register Loads Target abort PCI transfer Set signaled target abort bit in PCI status register Signal Machine Check with MACHK Stores Signal Machine Check with MACHK 1 Normally means that dummy zeros are returned for loads and write data is ignored Page 196 of 209 6 26 2000 IBM Dual Bridge and Memory Controller System I O Interface The device implements a 2 MB ROM space from address 4G 2M to 4 GB Configuration There is no configuration requirement for SIO logic These areas are hard wired in the upper 16 MB of real memory System I O Registers Application Presence Detect Bits The device provides Output Enables signals and read cycles for two external 32 bit registers The read of the SIORO or SIOR1 results in a read of bits 0 to 31 of these register which correspond respectively to the data present on the line 31 and 0 of the PCI 32 bit A D during the read cycle For descriptions of these registers refer to System I O Register 0 SIORO on page 128 controls PRES OEO signal e System I O Register 1 SIOR1 on page 129 controls PRES_OE1 signal MCCR Register Settings on page 181
197. sters soft ware must read the PD bits and the ID bits for each DIMM These bits are located in the System I O registers see System I O Register 0 SIORO on page 128 The following table describes how to initialize these regis ters MCER Register Initialization see notes 1 4 Device DIMM Description Bank Size MB MCER x MCER x 1 DIMM Size MB EM Bank x Bank x1 RUD ed 2 1 4 Not equipped xX 3F3 Off 4 2 4 4 x 3F3 X 3F3 4 1 8 Not equipped X 3E3 Off 8 2 8 8 x 3E3 x 3E3 8 1 16 Not equipped x3C3 Off 16 2 16 16 x3C3 x 3C3 16 1 32 Not equipped x 383 Off 32 2 32 32 x 383 x 383 DIMM size is the size in MB of one DIMM including Bank A and Bank B if dual bank DIMM 2 Number of banks per DIMM One for single bank DIMM i e DIMM equipped with Bank A only two for dual bank DIMM i e DIMM equipped with Bank A and Bank B 3 xin MCER x 0 2 4 or 6 4 a setting of off indicates that the bank must be disabled by setting MCER x Bit 0 0 Page 182 of 209 6 26 2000 IBM Dual Bridge and Memory Controller MCER Register Initialization see notes 1 4 a Device DIMM Description Bank Size MB MCER 9 MCERGH DIMM Size MB A eM Bank x Bank x 1 a Ei 32 1 64 Not equipped x 303 Off 64 2 64 64 x 303 x 303 64 1 128 Not equipped x 203 Off 128 2 128 128 x 203 x 203 128 1 256 Not equipped x 003 Off 256 2 256 256 x 003 x 003 256 1 512 Not equipped x 002 Off 512
198. ted 1 2 1 22 30 x x TYPE 0 configuration cycle with no IDSELs on Returns 1s on loads and ignores store data 34 7 0 Special cycle command Special cycle command issued to PCI Bus BUS gt BUSNO X X x Configuration access to bridge on PCI Bus BUS SUBNO TYPE 1 configuration cycle on PCI Bus r Bie Invalid bust CONFIG ADDR 1 2 3 US gt BUSNO x x x Returns 1s on loads and ignores store data BUS gt SUBNO No access made to PCI Bus 1 Firmware must insure the SUBNO register in the PCI header is greater than or equal to the BUSNO register in the PCI header Unpredictable results can occur if this is not true 2 The PCI Bridge performs a compare of the BUS NUMBER field in the CONFIG_ADDRESS register and the BUS NUMBER field in the bridge s 256 byte PCI header 3 The PCI Bridge performs a compare of the BUS NUMBER field in the CONFIG_ADDRESS register and the SUBORDINATE BUS NUMBER field in the bridge s 256 byte PCI header If there is no response to a configuration cycle no DEVSEL detected the device Master Aborts the cycle sets the Master Abort bit in the PCI Status register and completes the processor cycle normally by returning all ones on reads and ignoring data on writes Page 192 of 209 6 26 2000 IBM Dual Bridge and Memory Controller TYPE 0 Configuration Cycles During a TYPE 0 configuration cycles the CPC710 provides on the AD 11 31 lines the IDSEL of the device to be configured on the PCI 32 or PCI 64 bus as de
199. tem I O Pair 0 d i 3 5 7 CC PCI 32 Bus 33 MHz gt 72 a a a a XCVr SDRAMs up to 2GB y Flash __ PD Regs The CPC710 is designed to interface with 60x system bus definition It can also directly interface to one or two PowerPC 604 750 7400 processors 6 26 2000 Page 9 of 209 IBM Dual Bridge and Memory Controller Component Block Diagram 60x Bus Interface Logic JTAG Controller 60x Address Address Endian MD minc e ioe Queueing Arbiter Decodes Translation Configuration Posted Internal Device Interface Clock Logic Store Buffers Memory DMA PCI 32 PCI 64 CACHE OP INTF SDRAM Memory Controller s SDRAM i omman 60X DMA Controller Logic MEM ueues z INTF 8 Internal Device Interface S a Control Logic x 60x MEMORY PCI 32 PCI 64 ECC Correction E PCI 64 S DMA Data Buffers System I O Control PCI 64 Bus Interface PCI 32 Bus Interface 0 g oO 8 DMA oss DMA E External Registers 9 5 PCI Bus Sla PCI Bus Interface G Master Slave Master Slave 8 60x 8 E Logic 60x 8 E Logic 3 B 3 8 PCI 32 a PCI 64 A T T t T E interlace 5 Data 5 2 Data z Memory Buffers Memory 2 Buffers IBM25CPC710AB3A100 Clocked at System Bus Speed Clocked at PCI 32 Bus Speed 33 MHz Clocked at PCI 64 Bus Speed 33 6
200. ter power on reset When the first processor read occurs to this register BIT 31 returns a value of 0 All subsequent reads of this regis ter return a value of 1 for BIT 31 In addition to the First Access Bit bits 0 and 1 provide semaphores for use by the firmware during boot time and are utilized until system memory has been initialized and tested Reset Value x 0000 0000 Address x FF00 1010 Access Type Read Write Reserved Y Y 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Multi processor Synchronization Bit 0 Multi processor Synchronization Bit 1r 4 Multi processor First Access Bit Bit s Description 0 Multi processor Synchronization Bit 0 Used for communication between processors at IPL time 1 Multi processor Synchronization Bit 1 used for communication between processors at IPL time 2 30 Reserved Multi processor First Access Bit Read Only Set after read 31 0 Initial power on value Indicates first read of this register 1 Indicates that this register has been read at least once previously Page 102 of 209 6 26 2000 IBM Dual Bridge and Memory Controller System I O Control SIOC This register provides initialization and control of the Boot FLASH devices to which device interfaces Reset Value x 0000 0000 Address x FF00 1020 Access Type Read Write oO N a v Ez o oO c iL 2 3 8 Reserved Reserved Reserved SIO D
201. the reset when the bit 2 is deasserted Returns to high level 1 it takes 250ns before the PCI 32 bus can be used for normal accesses Page 206 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Reset in Multiprocessor mode The sequence of Power On Reset in Multiprocessor is the same as for a Single CPU on the 60X bus Simultaneously the HRESETO and HRESET1 signal goes up after the POWERGOOD signal goes up One of the two CPU get the PowerPC bus through SYS_BRO or SYS BR1 and get granted to access the Boot ROM at address FFFF 0100 It can be decided for example that the CPU 0 is the Master and the CPU 1 the slave with the CPU O0 in charge of running the code to configure the CPC710 bridge The Master slave configuration is defined with the help of registers PIDR amp RSTR PIDR Physical Identifier Register When BRO BGO signal pair is set bit 31 is set to 0 BR1 BG1 signal pair is set bit 31 is set to 1 RSTR Connectivity Reset Register permit to reset CPUO or CPU1 The first action of the boot code is to permit to the connected CPU to read the PIDR register such that this CPU identifies if he is a Master or a slave In the case the CPU 1 slave get access first the boot code can put him in a pooling mode until the Master complete the I O and Memory initialization One way is to write in the Register RSTR 4 Way Multiprocessor The CPC710 has four 4 PowerPC Bus Requests but internally the arbitration is done on 2 reques
202. tive other REQs internally gated 17 2 not activate P GNT 5 until 60x bus has flushed all posted PCI 32 bit bus transfers 1 PCI ISA Bridge is NOT present in system so device treats the P REQ 5 signal like any other PCI bus REQ sig nal Grant Active To Frame Active Time out Disable 0 If device grants the PCI bus to a PCI master and other REQs are outstanding the PCI master must activate the FRAME signal within 20 cycles or device will deactivate its GNT signal 18 1 Once device has granted the bus to a PCI device Device waits until it sees FRAME active from that device before deactivating its grant signal Note The 20 cycle count is not guaranteed The timer runs continuously and therefore device could remove the grant at any time Issue Flush Snoops Instead Of Kill Snoops 19 0 PCI bridge requests the 60x logic to perform Kill snoops on 60x bus for DMAs as normal 1 PCI bridge substitutes Flush snoops instead of Kill snoops to the 60x logic This is to avoid a 604 coherency problem that exists for Kill snoop operations 20 31 Reserved Page 72 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Arbiter Control Register ACR This register provides software with a means to disable individual devices on the PCI bus from generating master bus operations Reset Value x 0000 0000 Address BAR x 000F 7F30 Access Type Read Write 200250052590 0 Q Q Q Q Q Q Q Q oO oO oO oO oO oO oO oO pn E c c E c
203. to an address mapped to two different configuration extents When an overlap condition is detected the hardware follows the following procedure 1 Set the Overlapping Memory Extent error bit in MESR if no hard errors exist 2 Store the address in MEAR if no hard errors exist 3 The Memory Controller responds with dummy data for reads ignores write data and indicates an Invalid Address error to the requesting logic To enable further error logging the software writes zeros into the MESR When a Single bit or a hard error occurs after an Overlapping Memory Extent the error is not logged into MESR and MEAR 6 26 2000 Page 185 of 209 IBM Dual Bridge and Memory Controller Page 186 of 209 6 26 2000 IBM Dual Bridge and Memory Controller m PCI Bridges Overview The device s PCI Bridge function executes load and store operations from the CPU to the PCI buses It also provides an interface for PCI devices to access system memory The PCI Bridge logic fully supports the PCI Local Bus Specification 2 The following table describes the physical connections for PCI devices on the PCI 32 bus in a desktop system PCI 32 Bus Device Physical Connection Example Device ARB Level RESET Signal IDSEL Signal PCI SLOT 0 P_REQO P_GNTO P_RST IDSEL1 PCI SLOT 1 P_REQ1 P_GNT1 P_RST IDSEL2 PCI SLOT 2 P_REQ2 P_GNT2 P_RST IDSEL3 ETHERNET CHIP P_REQ3 P_GNT3 P_RST IDSEL4 SCSI CHIP P_REQ4 P_GNT4 P_RST IDSEL5 ISA BRIDGE CHIP P REQ5 P GNT5 P RST IDSEL6
204. to x FFFF FFFF IPLROM FLASH ROM Up to 2 MB 4 6 8 RO Read Only Register All bits can be read Only bits 4 31 can be written All bits can be read Only bits 0 3 can be written Four beat burst read operations allowed to this address space Single byte writes only Not decoded by system logic Byte accesses allowed WO Write Only Register Range that IBM Dual Bridge and Memory Controller responds to is programmable ONOaORWOND 6 26 2000 Page 95 of 209 CPC710 133 IBM Dual Bridge and Memory Controller Physical Identifier Register PIDR This register provides a unique number for each processor or any 60x bus master reading this location It is primarily used by processors to differentiate themselves in multiprocessor configurations When this register is read device latches the current processors SYS BR SYS BO pair into this register which physically iden tifies the processor Each processor has a unique SYS BR SYS BG pair connected to it Reset Value x 0000 0000 Address x FF00 0008 Access Type Read Write Reserved Physical Identifier v vv Y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 23 Reserved Physical Identifier Device responds with two values for this field 24 31 X 00 Indicates processor associated with BRO and BGO pins X 01 Indicates processor associated with BR1 and BG1 pins Page 96 of 209 6 26 2000 IBM
205. transaction on the processor bus If the RID bits in the IBM25CPC710AB3A100 and System Control register match the RID bits on the SYS TBST and SYS TSIZ 0 2 lines the 60x logic accepts the transfer If the instruction is an ecowx the 60x logic SYS TAs the bus for dummy write data and sends a DMA Transfer Write command to the DMA Controller The internal address bus associated with the Transfer Write command contains the address from the proces sor bus This address is placed in the XTAR register by the DMA Controller During the processor address tenure the 60x logic sets an internal flag to indicate special handling of TLBSYNC operations on the proces Sor bus If the flag is not set the 60x logic ignores all TLBSYNC operations on the processor bus If the flag is set a TLBSYNC operation on the bus causes the 60x logic to place a one cycle pulse on the UX6 TLB SYNC line to the DMA Controller The 60x logic continuously SYS ARTRYs the TLBSYNC bus operation until it receives a one cycle pulse on the internal UXI XFER DONE line from the DMA Controller This pulse also resets the 60x logic s internal flag to perform special handling of the TLBSYNC operations Note Since the PowerPC601 processor does not issue TLBSYNC operations the 60x logic must treat any SYNCs following a TLBI as a TLBSYNC operation when operating with a PowerPC601 processor When the eciwx instruction is used the 60x logic performs the same steps except that the 60x logic interna
206. ts In the case of 4 Way multiprocessing support it is necessary to add an external logic to handle the additional 2 pro cessors See scheme below 6 26 2000 PowerPC750 PowerPC750 PowerPC750 PowerPC750 CPUO CPU 1 CPU 2 CPU 3 BRO BGO BR1 BG1 BR2 BG2 BR3 BG3 4 way SMP A arbitration i t external circuit CPLD A A BROW BR1Y BR2Y BR3Y BGO BGI g g CPC710 60X Bus Arbitration Figure 10 Abitration to su ort of 4 Way Multiprocessing with the CPC710 Page 207 of 209 IBM Dual Bridge and Memory Controller Typical Register setup sequence Many deviations from the proposed following example of set up are possible However it is important to keep the basic operations in the same sequence order as described below RR KKK kk Ck kk Ck KC kk ko kk Ck Kk Ck ck Kk Ck kk kk kk Ck ke kk Ck ko kk ke kk kk kk ke kk I I ke ke ke ke ek Typical CPC710 100 registers setup sequence from model simulation y 11 17 99 IBM France ROR KK KR kk kk kk Ck I KR kk kk kk Ck ck Kk Ck kk Ck Ck kk Ck ko kk Ck kk IKARIA ke ke ke ke ke ke ke ek Begin CPC710 100 registers setup sequence 22222 222 222 2 22 2 2 222 2 222 2 2 2 2 2 2 4J 60X Interface registers setup m D mec P CRM RSTR 0xf 000010 write 0xf0000000 UCTL 0xff001000 write 0x32f80000 ABCNTL 0xff001030 writ
207. ven with two masters in the system there will only be one address tenure waiting for a data tenure to complete 41 Implemented to accommodate slave devices like an L2 lookaside that can only support one level pipeline regardless of the number of masters on the 60x bus Page 154 of 209 6 26 2000 IBM Dual Bridge and Memory Controller Arbiter Requirements Internal ABB All devices on the 60x bus must generate an internal ABB Because the arbiter may grant the address bus to a requesting device while another master is active the requesting master must generate an ABB based on SYS TS and SYS AACK The current master does not provide an ABB Qualified SYS BG Equation Use the following equation to detect a qualified bus grant using positive logic QBG SYS BG ABB SYS ARTRY where ABB represents the interval between SYS TS and SYS AACK active Note Bus Request SYS BR need not be active to detect a qualified bus grant parked case SYS TS Assertion All master devices must drive SYS TS active in the cycle immediately following a qualified address bus Oth erwise the address tenure is aborted and another master is free to drive the address bus SYS BR Negation All master devices must negate SYS BR for at least one bus cycle immediately after receiving a qualified bus grant Qualified SYS DBG Equation The equation for qualified SYS_DBG using positive logic is QDBG SYS DBG ARTRY DBB is unused because the arbiter does not issue a
208. volt compliant I O 40 to 105 C junction temperature Industrial Power dissipation 2 1 watts typical at 3 3 volts 100 MHz CBGA package 625 pins 32x32mm CMOS 5S6 0 35um technology 9 0x9 05mm PLL to reduce on chip system clock skew JTAG controller LSSD design 60x Bus Interface Supports 750 or 7400 or 604e PowerPC 100 MHz external bus operation Supports two processor or L2 lookaside cache Dual 32 byte store back buffers High bandwidth 2 way arbiter Little Endian mode PowerPC Supports SYNC EIEIO ordering operations Supports 60x bus configuration cycles Description The CPC710 is a highly integrated host bridge device that interfaces a PowerPC 60x bus with SDRAM based system memory and two PCI ports It provides arbitration for one or two processors and supports two levels of pipelining per processor along with 64 byte buffers The device s memory controller supports SDRAM allowing the memory to burst data on almost every bus cycle at 100 MHz 1 2 1 1 after initial latency on Read and 1 1 1 1 on write 6 26 2000 IBM Dual Bridge and Memory Controller Memory Controller Supports 100 MHz SDRAM including PC100 Upto 2GB 2 way interleaved SDRAM with ECC external MUX to reduce pin count Supports 16 64 128 and 256 Mb SDRAMs Programmable timing parameters Upto 8 dual bank DIMM SDRAM Access command queue with look ahead override option for CPU PCl s and DMA Access bas
209. x 2075705t o o 9 o Es 2g 2o Lg L g e g oO oO gst amp avg 2 2 0 2 8 5 98 gS g o293825232929 2 d d amp uodzigscscosc Reserved Y 4 4 4 i i x v Y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description Pipeline Control 00 Pipelining Disabled 0 1 01 One level pipelining per arbitration level is enabled two outstanding addresses allowed 10 Two level pipelining per arbitration level is enabled three outstanding addresses allowed 11 One level pipeline enabled across both arbitration levels Selected this mode for operation with an L2 look aside controller Address Bus Parking Control 00 Parking Disabled 2 3 01 Parking enabled for Arbitration level 0 only 10 Parking enabled for Arbitration level 1 only 11 MRU parking enabled Last arbitration level active is parked 64 Byte Cache Line 0 Arbiter will grant the address bus as normal 4 ds Arbiter will grant a second address bus tenure to the current arbitration level if the current arbitration level is again requesting the address bus and if first access is a burst transaction Normal round robin grant sequence will resume after each pair of grants Data Gather Control for PCI 32 bus 5 6 Ox Not enabled 10 Enabled for accesses to incrementing addresses only 11 Enabled for accesses to incrementing and same addresses NOT RECOMMENDED Data Gather Control for PCI 64 bus 7 8 Ox Not enabled 10 Enabled for accesses to increm
210. yte MSB the next sequential address contains the second MSB and so on In LE mode the specified address contains the scalar s least significant byte LSB the next sequential address contains the second LSB and so on Processor Behavior in LE Mode PowerPC 604 and 750 processors normally operate in BE mode To operate in LE mode the processors generate an LE address internally and then modify or munge the three low order address bits to create a BE address equivalent The processors do not issue unaligned LE transfers on the bus Instead they take an alignment interrupt However the PowerPC 604 processor does issue unaligned LE transfers as long as they do not cross word boundaries The following table describes the addresses generated by the processor for LE transfers Endian Behavior PREP architecture requires data to be stored in the same Endian mode as the processor Therefore the device implements logic to unmunge the address and byte swap the data bus as it comes from the proces Sor before sending it to memory or to the PCI bridges See Device Endian Logic below Processor Little Endian Address Modification Transfer Size bytes Processor s Internally Generated LE Effective Address 1 2 3 4 5 6 7 8 29 31 Resulting Processor Big endian Address 29 31 0 7 6 53 4 0 1 6 53 48 2 5 4 3 4 4 3 2 13 0 5 2 13 0 6 1 0 7 0 1 The PowerPC 604 does not support 3 byte transfers in LE mode however these tran

IBM Dual Bridge and Memory Controller CPC710

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