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UM10601 LPC81x User manual

1. 206 Has iid d ati assi 223 16 3 1 I2C transmit receive in master mode 207 166 10 ded Ba jist eta 16 3 2 Configure the I2C for wake up 209 16611 Pn c ha ree QUON MM MC 225 16 3 2 1 Wake up from Sleep mode 209 16 6 12 mah a n dia 226 16 3 2 2 Wake up from Deep sleep and Power down 16 6 13 Slave Address 227 chest hace eG Rk ee a a e 209 i 164 Pin description 210 16 6 14 Slave address Qualifier 0 register 227 ud SUE 16 6 15 Monitor data register 228 16 5 General description 210 16 7 Functional description 229 16 6 Register description 212 1674 Busrates and timing considerations 229 bos iSc ell aid register 213 16 7 1 1 229 6 tatus register 215 qd679 229 16 6 3 Interrupt Enable Set and read register 219 16 73 Ten bit 230 16 6 4 Interrupt Enable Clear register EDI 220 16 7 4 Clocking and power considerations 230 16 6 5 Time out value register 221 1675 231 Chapter 17 LPC81x SPIO 1 17 1 How to read this chapter 232 17 6 7 SPI Transmitter Data
2. 98 8 6 8 Pin interrupt rising edge register 105 8 5 2 Pattern match engine 98 8 6 9 Pin interrupt falling edge register 106 8 5 2 1 Inputs and outputs of the pattern match 8 6 10 Pin interrupt status register 106 engine isses ene 100 8 6 11 Pattern Match Interrupt Control Register 106 8 5 2 2 Boolean expressions 101 8 6 12 Pattern Match Interrupt Bit Slice Source 8 6 Register description 102 5 107 8 6 1 Pin interrupt mode register 102 8 6 13 Pattern Match Interrupt Bit Slice Configuration 8 6 2 Pin interrupt level or rising edge interrupt enable register 6 nn nn nnn 111 GglSlOl RE 103 8 7 Functional description 117 8 6 3 Pin interrupt level or rising edge interrupt set 8 7 1 Pin interrupts 117 FEGISIE 35 Phe ae es ee ke 103 8 7 2 Pattern Match engine example 117 8 7 3 Pattern match engine edge detect examples 119 Chapter 9 LPC81x Switch matrix 9 1 How to read this chapter 121 9 5 1 Pin assign register O 127 9 2 Features 121 9 5 2 Pin assign register 1 128 9 3 Basic 121 953 Pin assign register 2 128 9 3 1
3. lt 263 icr 19 7 1 CRC CCITT set up 263 19 5 General description E E EN 260 1972 E 263 19 6 Register description 262 19 7 3 CRC 32 264 19 6 1 CRC mode register 262 Chapter 20 LPC81x Flash controller 20 1 How to read this chapter 265 20 4 4 Flash signature generation result register 266 20 2 Features casi cosus eas na rer ra Res 265 20 5 Functional description 266 20 3 General 265 20 5 1 Flash signature generation 266 20 4 Register description 265 20 5 1 1 Signature generation address and control 20 4 1 Flash configuration register 265 registers Be gs Ae ee d 20 4 2 Flash signature start address register 266 20 5 1 2 Signature HR pepe ps cp mae 20 4 3 Flash signature stop address register 266 20 5 1 3 Content verification Chapter 21 LPC81x Boot ROM 21 1 How to read this chapter 269 21 5 1 Boot loader 271 212 PF dlul S iiacevcseesenernerenicucaees 269 21 5 2 272 21 3 Basic configuration 269 21 6 Functional description 273 21 3 1 Bootloader versions 269 21 6 1 Memory map after any reset
4. UM10601 LPC81x User manual Rev 1 6 2 April 2014 User manual Document information Info Content Keywords ARM Cortex M0 LPC800 LPC800 UM LPC81x LPC81x UM USART I2C LPC811M001JDH16 LPC812M101JDH16 LPC812M101JD20 LPC812M101JDH20 LPC810M021FN8 LPC812M101JTB16 Absiract LPC81x user manual NXP Semiconductors U M1 0601 Revision history LPC81x User manual Rev Date Description 1 6 20140402 LPC81x user manual PDF output size corrected 1 5 20140306 LPC81x user manual Modifications Table 147 SCT configuration example corrected Figure 43 Boot ROM structure corrected 1 4 20140207 LPC81x user manual Modifications UM10601 Editorial updates in the SPI chapter Bit FLEN renamed to LEN in the TXDATCTL and TXCTL registers Bit description of the FRAME_DELAY bit in the SPI DELAY register updated See Table 205 Chapter 29 LPC81x Code examples added SCT behavior in undefined state described in Section 10 7 5 Clarify write access to the following registers in the SCT COUNT STATE MATCH FRACMAT and OUTPUT Writes are only allowed when the counter is halted Clarify repeated access to SCT CTRL register Reset value of the SYSAHBCLKCTRL register corrected See Table 30 Part LPC812M101JTB16 added Code examples corrected in Chapter 23 LPC81x Power profile API ROM driver Chapter 25 LPC81x USART ROM driver routines and C
5. 180 13 6 1 Control register 181 13 6 2 Count register 182 Chapter 14 LPC81x ARM Cortex SysTick Timer SysTick 14 1 How to read this chapter 183 14 6 1 System Timer Control and status register 184 14 2 183 1462 System Timer Reload value register 185 14 3 Basic 183 a Pd d NS es 144 F Md ls VRUG TAISTO n 14 5 General description 183 Aner ee bb RU emcee d n 14 7 1 Example timer calculation 186 14 6 Register description 184 Example system clock 20 MHz 186 Chapter 15 LPC81x USARTO 1 2 15 1 How to read this chapter 187 15 3 Basic configuration 187 152 187 15 3 1 Configure the USART clock and baud rate 188 15 3 2 Configure the USART for wake up 189 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 365 of 370 NXP Semiconductors UM10601 Chapter 30 Supplementary information 15 3 2 1 Wake up from Sleep mode 189 15 6 7 USART Receiver Data with Status register 200 15 3 2 2 Wak
6. 244 Table 212 SPI Transmitter Control register TXCTL Chapter 30 Supplementary information Table 233 LPC81x flash and ISP configurations 276 Table 234 LPC81x flash configuration 277 Table 235 Code Read Protection options 278 Table 236 Code Read Protection hardware software interaction 279 Table 237 ISP commands allowed for different CRP 279 Table 238 UART ISP command summary 280 Table 239 UART ISP Unlock command 280 Table 240 UART ISP Set Baud Rate command 281 Table 241 UART ISP Echo command 281 Table 242 UART ISP Write to RAM command 281 Table 243 UART ISP Read Memory command 282 Table 244 UART ISP Prepare sector s for write operation COMMANG oid ives ees Pa oe Y wee 282 Table 245 UART ISP Copy RAM to flash command 283 Table 246 UART ISP Go command 284 Table 247 UART ISP Erase sector command 284 Table 248 UART ISP Blank check sector command 285 Table 249 UART ISP Read Part Identification command285 addresses 0x4005 8020 SPIO 0x4005 C020 Table 250 Part identification numbers 285 SPI1 bit 245 Table 251 UART ISP Read Boot Code version number Table 213 SPI Divider register DIV addresses 0x4005 8024
7. 73 Table 92 Register overview Pin interrupts and pattern Table 64 PIOO 12 register PIOO 12 address 0x4004 match engine base address OxA000 4000 102 4008 bit description 74 Table 93 Pin interrupt mode register ISEL address Table 65 PIOO 5 register PIOO 5 address 0x4004 400C 0xA000 4000 bit description 102 bit description 75 Table 94 Pin interrupt level or rising edge interrupt enable Table 66 PIOO 4 register PIOO 4 address 0x4004 4010 register IENR address 0xA000 4004 bit bit description 76 description 1038 Table 67 PIOO 3 register PIOO 3 address 0x4004 4014 Table 95 Pin interrupt level or rising edge interrupt set bit description 77 register SIENR address 0xA000 4008 bit Table 68 PIOO 2 register PIOO 2 address 0x4004 4018 desctiption ssl t 103 bit description 78 Table 96 Pin interrupt level or rising edge interrupt clear Table 69 PIOO 11 register PIOO 11 address 0x4004 register CIENR address 0xA000 400C bit 401C bit 79 description 104 Table 70 PIOO 10 register PIOO_10 address 0x4004 Table 97 Pin interrupt active level or falling edge interrupt 4020 bit description 80 enable register IENF address 0xA000 4010 bit Table 71
8. 323 Table 294 uart get mem _ 323 Table 295 uart_setup 324 Table 296 _ 324 Table 297 uart get 324 Table 298 uart put 324 Table 299 uart get 325 Table 300 uart put 325 Table 301 325 Table 302 Errorcodes 325 Table 303 SWD pin description 328 Table 304 JTAG boundary scan pin description 329 Table 305 Pin description table fixed pins 334 Table 306 Cortex MO instruction summary 337 Table 307 126 Code 340 Table 308 126 Code 341 Table 309 126 Code 341 Table 310 126 Code 342 Table 311 l2C Code 342 Table 312 Il2C Code 343 Table 313 Il2C Code 343 Table 314 Il2C Code 344 Table 315 126 Code 344 Table 316 I2C Code 345 Table 317 12C Code 345 Table 318 I2C Code
9. gt SDA Pc aus 1 XTALOUT XTALIN USART2 ALWAYS ON POWER DOMAIN EEGET CLOCK RESET CEKIN GENERATION CLKOUT POWER CONTROL SYSTEM FUNCTIONS _11 2 r VDDCMP ACMP_O clocks and controls aaa 005746 Fig 1 LPC81x block diagram UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 8 of 370 NXP Semiconductors U M1 0601 Chapter 1 LPC81x Introductory information 1 5 General description 1 5 1 ARM Cortex M0 core configuration The ARM Cortex MO core runs at an operating frequency of up to 30 MHz Integrated in the core are the NVIC and Serial Wire Debug with four breakpoints and two watch points The ARM Cortex MO core supports a single cycle I O enabled port IOP for fast GPIO access at address 0xA000 0000 The ARM Cortex MO core revision is rOpO The core includes a single cycle multiplier and a system tick timer SysTick UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 9 of 370 UM10601 Chapter 2 LPC81x Memory mapping Rev 1 6 2 April 2014 User manual 2 1 How to read this chapter The memory mapping is identical for all LPC81x parts Different LPC81x parts support different flash and SRAM memory size
10. 273 inti 21 6 2 Boot process 273 21 4 Pin 271 6 flowchart 27 21 5 Generaldescription 271 iid Boot process Chapter 22 LPC81x Flash ISP and IAP programming 22 1 How to read this chapter 276 22 2 Features RR RR 276 22 3 Pin 276 224 Generaldescription 276 22 4 1 Flash 276 22 4 2 Flash content protection mechanism 277 22 4 3 Code Read Protection CRP 278 22 4 3 1 ISP entry protection 279 22 5 description 280 22 5 1 UART ISP commands 280 22 5 1 4 Unlock Unlock gt 280 22 5 1 2 Set Baud Rate Baud Rate stop bit 281 22 5 1 3 Echo lt gt 281 22 51 4 Write to RAM start address gt number of gt 281 22 5 1 5 Read Memory address number of gt 282 22 5 1 6 Prepare sector s for write operation start sector number end sector number 282 UM10601 All information provided in this document is subject to legal disclaimers 22 5 1 7 RAM to flash Flash address RAM address gt no of bytes gt
11. NS Mode 2 CPOL 1 SCK SSEL 1 i i i i 1 i i i i MISO owe X MSB LSB gt lt gt Pre_delay Data frame Post_delay Pre and post delay CPHA 1 Pre_delay 2 Post_delay 1 Mode 1 CPOL 0 SCK Mode 1 SCK SSEL gt gt Pre_delay Data frame Post_delay Fig 37 Pre delay and Post delay timing UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 248 of 370 NXP Semiconductors U M1 0601 Chapter 17 LPC81x SPIO 1 17 7 2 2 Frame delay The Frame delay value controls the amount of time at the end of each frame This delay is inserted when the EOF bit 1 Frame delay is illustrated by the examples in Figure 38 Note that frame boundaries occur only where specified This is because frame lengths can be any size involving multiple data writes See Section 17 7 5 for more information Frame delay 0 Frame delay 2 Pre delay 0 Post delay 0 SSEL lt First data frame Frame_delay Second data frame Frame delay 1 Frame delay 2 Pre delay 0 Post delay 0 sk 5 Pe Ly Le i i Mode3 CPOL 1 A f UP Lf VJ M ME iii
12. Routine uart get mem size Prototype uint32 t ramsize in bytes get mem size void Input parameter None Return Memory size in bytes Description Get the memory size needed by one UART instance UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 323 of 370 NXP Semiconductors UM10601 UM10601 25 4 2 25 4 3 25 4 4 25 4 5 UART setup Chapter 25 LPC81x USART API ROM driver routines Table 295 uart_setup Routine Prototype Input parameter uart_setup UART_HANDLE_T uart_setup uint82_t base addr uint8_t base_addr Base address of register for this uart block ram Pointer to the memory space for uart instance The size of the memory space can be obtained by the uart_get_mem_size function Return The handle to corresponding uart instance Description Setup UART instance with provided memory and return the handle to this instance UART init Table 296 uart_init Routine uart_init Prototype uint32_t uart init UART HANDLE T handle UART_CONFIG set Input parameter Return Description handle The handle to the uart instance set configuration for uart operation Fractional divider value if System clock is not integer multiples of baud rate Setup baud rate and operation mode for uart then enable uart UART get character Table 297 uart_get_char
13. 10 6 1 SCT configuration register This register configures the overall operation of the SCT Write to this register before any other registers Table 121 SCT configuration register CONFIG address 0x5000 4000 bit description Bit Symbol Value Description Reset value 0 UNIFY SCT operation 0 0 16 bit The SCT operates as two 16 bit counters named L and H 1 32 bit The SCT operates as a unified 32 bit counter 2 1 CLKMODE SCT clock mode 0 0x0 Bus clock The bus clock clocks the SCT and prescalers 0 1 Prescaled bus clock The SCT clock is the bus clock but the prescalers are enabled to count only when sampling of the input selected by the CKSEL field finds the selected edge The minimum pulse width on the clock input is 1 bus clock period This mode is the high performance sampled clock mode 0 2 Input The input selected by CKSEL clocks the SCT and prescalers The input is synchronized to the bus clock and possibly inverted The minimum pulse width on the clock input is 1 bus clock period This mode is the low power sampled clock mode 0x3 Reserved 6 3 CKSEL SCT clock select All other values are reserved 0 0x0 Input 0 rising edges 0 1 Input 0 falling edges 0 2 Input 1 rising edges 0x3 Input 1 falling edges 0 4 Input 2 rising edges 0 5 Input 2 falling edges 0 6 Input 3 rising edges 0 7 Input 3 falling edges 7 NORELAOD L A 1 in this bit prevents the lower match registers from being reloaded from their 0 res
14. 16 register PIOO 16 address 0x4004 desctiptioni 2 sce dees ee rq e 104 4024 bit description 81 Table 98 Pin interrupt active level or falling edge interrupt Table 72 PIOO 15 register 15 address 0x4004 set register SIENF address 0 000 4014 bit 4028 bit description 82 description 105 Table 73 PIOO 1 register PIOO 1 address 0x4004 402C Table 99 Pin interrupt active level or falling edge interrupt bit description 83 clear register CIENF address 0xA000 4018 bit Table 74 PIOO 9 register PIOO 9 address 0x4004 4034 desctiption eile EDIT 105 bit description 84 Table 100 Pin interrupt rising edge register RISE address Table 75 PIOO 8 register PIOO 8 address 0x4004 4038 0xA000 401C bit description 105 bit description 85 Table 101 Pin interrupt falling edge register FALL address Table 76 PIOO 7 register PIOO 7 address 0x4004 403C 0xA000 4020 bit description 106 bit description 86 Table 102 Pin interrupt status register IST address OxA000 Table 77 6 register PIOO 6 address 0x4004 4040 4024 bit description 106 bit description 87 Table 103 Pattern match interrupt control register Table 78 PIOO 0 register PIOO 0 address 0x4004 4044 PMCTRL addre
15. 2C STAT g ST NACK TX 0x8 2C STAT SLVPENDING 0x100 2C STAT SLVSTATE x lt a c 2C STAT SLVST ADDR 0x000 2C STAT SLVST RX 0x20 2C STAT SLVST TX 0x40 2C MSTCTL MSTCONTINUE 0 1 2C MSTCTL MSTSTART 0x2 2C MSTCTL MSTSTOP 0x4 2C SLVCTL SLVCONTINUE 0 1 2C SLVCTL SLVNACK 0x2 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 340 of 370 NXP Semiconductors UM1 0601 Chapter 29 LPC81x Code examples 29 2 2 Interrupt handler Table 308 12C Code example Interrupt handler void I2c IRQHandler uint32 t intstat LPC_I2C gt INTSTAT uint32 t stat LPC_I2C gt STAT if intstat amp I2C STAT MSTPENDING uint32 t mst state stat amp I2C STAT MSTSTATE if mst state I2C STAT MSTST IDLE LPC I2C MSTDAT 0x23 lt lt 1 1 address and 1 for Rin bit in order to read data LPC_I2C gt MSTCTL I2C MSTCTL MSTSTART send start if mst state I2C STAT MSTST RX uint8 t data data LPC I2C MSTDAT receive data if data 0 abort LPC I2C MSTDAT 0x23 lt lt 1 0 address and 1 for RWn bit in order to read data LPC I2C MSTCTL I2C MSTCTL MSTSTART repeated start nack implied if mst state I2C STAT MSTSTX LPC I2C MSTCTL I2C MSTCTL MSTSTOP stop
16. I2C_HANDLE_T Handle to the allocated SRAM area I2C Pointer to the I2C PARAM struct I2C RESULT Pointer to the 12C RESULT struct ErrorCode Receives bytes from slave and put into receive buffer After the task is finished the slave address with the R W bit 1 is in the first byte of the receive buffer STOP condition is sent at end unless stop flag 0 Program control will be returned immediately and task will be completed on an interrupt driven basis When task is completed the callback function is called I2C Master Transmit Receive Interrupt Table 279 12C Master Transmit Receive Interrupt Routine Prototype Input parameter Return Description I2C Master Transmit Receive Interrupt ErrorCode t i2c master tx rx intr 2C HANDLE T I2C I2C RESULT I2C HANDLE T Handle to the allocated SRAM area I2C Pointer to the I2C PARAM struct I2C RESULT Pointer to the 12C RESULT struct ErrorCode First transmits bytes in the send buffer to a slave and secondly receives bytes from slave and store it in the receive buffer The slave address with the R W bit 0 is expected in the first byte of the send buffer After the task is finished the slave address with the R W bit 1 is in the first byte of the receive buffer STOP condition is sent at end unless stop flag 0 Program control will be returned immediately and task will be completed on an interrupt driven
17. MoD 1 MOD o chip reset _ watchdog interrupt gt Fig 24 Windowed Watchdog timer block diagram 12 5 2 Clocking and power control The watchdog timer block uses two clocks PCLK and WDCLK PCLK is used for the APB accesses to the watchdog registers and is derived from the system clock see Figure 3 The WDCLK is used for the watchdog timer counting and is derived from the watchdog oscillator The synchronization logic between the two clock domains works as follows When the MOD and TC registers are updated by APB operations the new value will take effect in 3 WDCLK cycles on the logic in the WDCLK clock domain When the watchdog timer is counting on WDCLK the synchronization logic will first lock the value of the counter on WDCLK and then synchronize it with PCLK so that the CPU can read the WDTV register Remark Because of the synchronization step software must add a delay of three WDCLK clock cycles between the feed sequence and the time the WOPROTECT bit is enabled in the MOD register The length of the delay depends on the selected watchdog clock WDCLK UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 173 of 370 NXP Semiconductors U M1 0601 UM10601 12 5 3 12 5 3 1 12 5 3 2 Chapter 12 LPC81x Windowed Watchdog Timer WWDT Using the WWDT lock features The WWDT supports
18. Routine Prototype Input parameter uart_get_char uint8 t uart get char UART HANDLE T handle handle The handle to the uart instance Return Received data Description Receive one Char from uart This functions is only returned after Char is received In case Echo is enabled the received data is sent out immediately UART put character Table 298 uart put char Routine uart put char Prototype void uart put char UART HANDLE T handle uint8 t data Input parameter Return Description handle The handle to the uart instance data data to be sent out None Send one Char through uart This function is only returned after data is sent All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 324 of 370 UM10601 Chapter 25 LPC81x USART API ROM driver routines NXP Semiconductors 25 4 6 UART get line Table 299 uart_get_line Routine uart_get_line Prototype uint32 t uart get line UART HANDLE T handle UART T param Input parameter handle The handle to the uart instance param Refer to definition Return Error code ERR UART RECEIVE ON UART receive is ongoing Description Receive multiple bytes from UART 25 4 7 UART put line Table 300 uart put line Routine uart put line Prototype uint32 t uart put line UART HANDLE T handle UART PARAM T p
19. STS 1 STS STS1 STS1 STS1 ATE STAT MSTPENDING I2C STAT MSTST IDLE abort address and 1 for RWn bit in order to read data ART ATE send start TAT MSTPENDING I2C STAT MSTST RX abort ceive data OP stop transaction nack implied ATE TAT MSTPENDING I2C STAT MSTST IDLE abort All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 344 of 370 NXP Semiconductors UM1 0601 Chapter 29 LPC81x Code examples 29 2 10 Master sending nack and repeated start on data Table 316 12C Code example Master sending nack and repeated start on data Address 0x23 Polling mode No error checking LPC I2C CFG I2C MSTEN while LPC_I2C gt STAT amp I2C STAT MSTPENDING if LPC_I2C gt STAT amp I2C STAT MSTSTATE I2C STAT MSTST IDLE abort LPC I2C MSTDAT 0x23 lt lt 1 1 address and 1 for RWn bit in order to read data LPC_I2C gt MSTCTL I2C MSTCTL MSTSTART send start while LPC_I2C gt STAT amp I2C STAT MSTPENDING if LPC_I2C gt STAT amp I2C STAT MSTSTATE I2C STAT MSTST RX abort data LPC_I2C gt MSTDAT receive data if data Oxdd abort LPC I2C MSTDAT 0x23 lt lt 1 0 address and 1 for RWn bit in order to read data LPC I2C MSTCTL I2C MSTCTL MSTSTART
20. 16 3 2 Configure the I2C for wake up In sleep mode any activity on the I2C bus that triggers an 12 interrupt can wake up the part provided that the interrupt is enabled in the INTENSET register and the NVIC As long as the 12 clock I2C PCLK remains active in sleep mode the I2C can wake up the part independently of whether the I2C block is configured in master or slave mode In Deep sleep or Power down mode the 12C clock is turned off as are all peripheral clocks However if the I2C is configured in slave mode and an external master on the I2C bus provides the clock signal the 12C block can create an interrupt asynchronously This interrupt if enabled in the NVIC the STARTERP1 register and in the I2C block s INTENCLR register can then wake up the core 16 3 2 1 Wake up from Sleep mode e Enable the I2C interrupt in the NVIC e Enable the I2C wake up event in the 12 INTENSET register Wake up on any enabled interrupts is supported see the INTENSET register Examples are the following events Master pending Change to idle state Start stop error Slave pending Address match in slave mode Data available ready 16 3 2 2 Wake up from Deep sleep and Power down modes e Enable the 12C interrupt in the NVIC e Enable the I2C interrupt in the STARTERP1 register in the SYSCON block to create the interrupt signal asynchronously while the core and the peripheral are not clocked See Table 46 Start
21. 31 0x4004 8170 bit description 43 Table 22 System oscillator control register SYSOSCCTRL Table 43 NMI source selection register NMISRC address address 0x4004 8020 bit description 32 0x4004 8174 bit description 43 Table 23 Watchdog oscillator control register Table 44 Pin interrupt select registers PINTSEL 0 7 WDTOSCCTRL address 0x4004 8024 bit address 0x4004 8178 PINTSELO to 0x4004 32 8194 PINTSEL7 bit description 44 Table 24 System reset status register SYSRSTSTAT Table 45 Start logic 0 pin wake up enable register 0 address 0x4004 8030 bit description 34 STARTERPO address 0x4004 8204 bit Table 25 System PLL clock source select register description 44 SYSPLLCLKSEL address 0x4004 8040 bit Table 46 Start logic 1 interrupt wake up enable register description 34 STARTERP1 address 0 4004 8214 bit Table 26 System PLL clock source update enable register description 45 SYSPLLCLKUEN address 0x4004 8044 bit Table 47 Deep sleep configuration register description 35 PDSLEEPCFG address 0x4004 8230 bit Table 27 Main clock source select register MAINCLKSEL description 46 address 0x4004 8070 bit description 35 Table 48 Wake up configuration register PDAWAKECFG Table 28 Ma
22. 345 Table 319 I2C Code 346 Table 320 126 Code 346 Table 321 12C Code 347 Table 322 126 Code 347 Table 323 l2C Code 347 Table 324 SPI Code 348 Table 325 SPI Code 348 Table 326 SPI Code 349 Table 327 SPI Code 349 Table 328 SPI Code 349 Table 329 SPI Code 350 Table 330 SPI Code 350 Table 331 SPI Code 350 Table 332 SPI Code 350 Table 333 SPI Code 351 Table 334 UART Code 351 Table 335 UART Code 351 Table 336 UART Code 352 Table 337 UART Code 352 Table 338 UART Code 352 Table 339 UART Code 352 Table 340 UART Code 352 Table 341 Abbreviations 353 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 A
23. 55 ps user code boot code execution finishes user code starts UM10601 4 4 7 3 Brown out detection The brown out detection circuit includes up to three levels for monitoring the voltage on the Vpp pin If this voltage falls below one of the selected levels the BOD asserts an interrupt signal to the NVIC or issues a reset depending on the value of the BODRSTENA bit in the BOD control register Table 40 The interrupt signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC see Table 4 in order to cause a CPU interrupt if not software can monitor the signal by reading a dedicated status register If the BOD interrupt is enabled in the STARTERP1 register see Table 46 and in the NVIC the BOD interrupt can wake up the chip from Deep sleep and power down mode If the BOD reset is enabled the forced BOD reset can wake up the chip from Deep sleep or Power down mode 7 4 System PLL functional description The LPC81x uses the system PLL to create the clocks for the core and peripherals All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 50 of 370 NXP Semiconductors U M1 0601 Chapter 4 LPC81x System configuration SYSCON irc_osc_clk Sys osc clk FCLKIN 3 y t L L p FCCO pd PSEL lt 1
24. Ensure that bit 3 in the PCON register Table 56 is cleared Write Ox3 to the PM bits in the PCON register see Table 56 Store data to be retained in the general purpose registers Section 5 6 2 Write one to the SLEEPDEEP bit in the ARM Cortex M0 SCR register Start the self wake up timer by writing a value to the WKT COUNT register Table 165 Use the ARM WFI instruction 5 7 7 5 Wake up from Deep power down mode using the self wake up timer The part goes through the entire reset process when the self wake up timer times out 1 When the WKT count reaches 0 the following happens The PMU will turn on the on chip voltage regulator When the core voltage reaches the power on reset POR trip point a system reset will be triggered and the chip re boots All registers except the DPDCTRL and GPREGO to GPREGS registers will be in their reset state Once the chip has booted read the deep power down flag in the PCON register Table 56 to verify that the reset was caused by a wake up event from Deep power down and was not a cold reset 3 Clear the deep power down flag in the PCON register Table 56 4 Optional Read the stored data in the general purpose registers Section 5 6 2 5 Set up the PMU for the next Deep power down cycle Remark The RESET pin has no functionality in Deep power down mode UM10601 All information provided in this document is subject to legal disclaimers
25. SRC ADDR NOT MAPPED DST ADDR NOT MAPPED COUNT ERROR Byte count is not 256 512 1024 4096 SECTOR NOT PREPARED FOR WRITE OPERATION BUSY None This command is used to program the flash memory The affected sectors should be prepared first by calling Prepare Sector for Write Operation command The affected sectors are automatically protected again once the copy command is successfully executed The boot sector can not be written by this command 22 5 2 3 Erase Sector s IAP Table 259 IAP Erase Sector s command Command Input Status code Result Description Erase Sector s Command code 52 decimal Param0 Start Sector Number Param1 End Sector Number should be greater than or equal to start sector number Param2 System Clock Frequency CCLK in kHz CMD SUCCESS BUSY SECTOR NOT PREPARED FOR WRITE OPERATION INVALID SECTOR None This command is used to erase a sector or multiple sectors of on chip flash memory The boot sector can not be erased by this command To erase a single sector use the same Start and End sector numbers UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 291 of 370 NXP Semiconductors UM10601 Chapter 22 LPC81x Flash ISP and IAP programming 22 5 2 4 Blank check sector s IAP Table 260 IAP Blank check sector s comman
26. UM10601 Chapter 4 LPC81x System config uration SYSCON Table 30 System clock control register SYSAHBCLKCTRL address 0x4004 8080 bit description continued Bit 10 11 12 13 14 15 16 17 18 Symbol GPIO SWM SCT WKT MRT SPIO 5 1 UARTO UART1 UART2 WWDT Value Description 0 1 Reset value Enables clock for GPIO port registers and GPIO pin 1 interrupt registers Disable Enable Enables clock for switch matrix Disable Enable Enables clock for state configurable timer Disable Enable Enables clock for self wake up timer Disable Enable Enables clock for multi rate timer Disable Enable Enables clock for SPIO Disable Enable Enables clock for SPI1 Disable Enable Enables clock for CRC Disable Enable Enables clock for USARTO Disable Enable Enables clock for USART1 Disable Enable Enables clock for USART2 Disable Enable Enables clock for WWDT Disable Enable Enables clock for IOCON block Disable Enable All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 37 of 370 NXP Semiconductors U M1 0601 Chapter 4 LPC81x System configuration SYSCON Table 30 System clock control register SYSAHBCLKCTRL address 0x4004 8080 bit description continued Bit Symbol
27. 252 17 6 6 SPI Receiver Data register 242 Chapter 18 LPC81x Analog comparator 18 1 How to read this chapter 254 18 3 Basic configuration 254 18 2 Features 254 18 3 1 Connect the comparator output to the SCT 254 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 366 of 370 NXP Semiconductors UM10601 18 4 Pin 255 18 5 Generaldescription 255 18 5 1 Reference voltages 256 18 5 2 Settling times 256 18 5 3 Interrupts csse rere ERG 256 Chapter 30 Supplementary information 18 5 4 Comparator 257 18 6 Register description 257 18 6 1 Comparator control register 257 18 6 2 Voltage ladder register 259 Chapter 19 LPC81x Cyclic Redundancy Check CRC engine 19 1 How to read this chapter 260 19 6 2 CRC seed 262 19 2 260 1963 checksum 262 19 3 Basic configuration 260 1964 data 263 194 260 197
28. 812 101 16 333 non sticky edge detect evaluates as false 120 Fig 13 Example Connect function UO_RXD and UO TXD to pins 10 and 14 on the SO20 package 122 Fig 14 Functional diagram of the switch matrix 124 Fig 15 SCTimer PWM block diagram 135 Fig 16 SCTimer PWM counter and select logic 136 Fig 17 Match logics irre fedet 154 Fig 18 Capture logic 154 Fig 19 Event selection 155 Fig 20 lt 1 155 Fig 21 SCT interrupt 156 Fig 22 SCT configuration example 162 Fig 23 MRT block diagram 165 Fig 24 Windowed Watchdog timer block diagram 173 Fig 25 Early watchdog feed with windowed mode enabled Wee al eee ek 179 Fig 26 Correct watchdog feed with windowed mode enabled 179 Fig 27 Watchdog warning interrupt 179 Fig 28 System tick timer block diagram 183 Fig 29 USART clocking 189 Fig 30 USART block 192 Fig 31 Hardware flow control using RTS and CTS 205 Fig 32 l2C 207 Fig 33 12C block diagram 211 Fig 34 SPI 232 Fig 35 SPI bloc
29. Chapter 9 LPC81x Switch matrix 9 5 Register description Table 108 Register overview Switch matrix base address 0x4000 C000 Name PINASSIGNO PINASSIGN1 PINASSIGN2 PINASSIGN3 PINASSIGN4 PINASSIGN5 PINASSIGN6 PINASSIGN7 PINASSIGN8 PINENABLEO Offset 0x000 Reference Table 109 Reset value OxFFFF FFFF Access R W Description Pin assign register 0 Assign movable functions UO TXD UO RXD UO RTS UO CTS Pin assign register 1 Assign movable functions UO SCLK U1 TXD U1 RXD U1 RTS Pin assign register 2 Assign movable functions UT CTS U1 SCLK U2 TXD U2 RXD Pin assign register 3 Assign movable function U2 RTS U2 CTS U2 SCLK SPIO SCK Pin assign register 4 Assign movable functions SPIO MOSI SPIO MISO SPIO SSEL SPI1_SCK Pin assign register 5 Assign movable functions 1 MOSI SPI1 MISO SPI SSEL CTIN 0 Pin assign register 6 Assign movable functions CTIN 1 CTIN 2 CTIN 3 CTOUT 0 Pin assign register 7 Assign movable functions CTOUT 1 CTOUT 2 CTOUT 3 I2C SDA Pin assign register 8 Assign movable functions 12C_SCL ACMP CLKOUT GPIO INT BMAT Reserved R W 0x004 OxFFFF FFFF Table 110 R W 0x008 OxFFFF FFFF Table 111 R W 0x00C OxFFFF FFFF 112 R W 0x010 OxFFFF FFFF Table 113 R W 0x014 OxFFFF FFFF Table 114 R W 0x018 FFFF Table 115 R W 0 01 OxFFFF FFFF X Table 116 R W 0x020 FFFF T
30. NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 332 of 370 NXP Semiconductors U M1 0601 Chapter 27 LPC81x Packages and pin description PIOO 17 PIOO 14 PIOO 13 PIOO O ACMP I1 TDO PIOO 12 PIO0_6 VDDCMP RESET PIOO 5 PIOO 7 PIOO_4 WAKEUP TRST TSSOP20 Vss SWCLK PIOO_3 TCK Vpp SWDIO PIOO 2 TMS PIOO 8 XTALIN PIOO 11 PIOO_9 XTALOUT PIOO 10 PIOO 1 ACMP I2 CLKIN TDI 16 15 aaa 003775 Fig 56 Pin configuration TSSOP20 package LPC812M101JDH20 terminal 1 XSON16 index area PIOO 13 PIOO_0 ACMP_I1 TDO PIOO_12 PIOO_6 VDDCMP RESET PIOO 5 PIOO 7 PIOO_4 WAKEUP TRST Vss SWCLK PIOO_3 TCK VDD SWDIO PIOO 2 TMS PIOO 8 XTALIN PIOO 11 PIOO 9 XTALOUT PIOO 10 PIOO 1 ACMP I2 CLKIN TDI aaa 009570 Transparent top view Fig 57 Pin configuration XSON16 package LPC812M101JTB16 27 2 Pin description The pin description table Table 305 shows the pin functions that are fixed to specific pins on each package These fixed pin functions are selectable between the GPIO and the RESET comparator SWD and XTAL pins By default the GPIO function is selected except on pins PIOO 2 PIOO 3 and PIOO 5 JTAG functions are available in boundary scan mode only Movable function for the I2C USART SPI and SCT pin functions can be assigned through the switch matrix to any pin that is not power or ground in place of the pin s fixed functi
31. Routine Prototype Input parameter 12C Set Slave Address ErrorCode ti2c set slave addr I2C HANDLE T slave 0 3 slave mask 0 3 I2C HANDLE T Handle to the allocated SRAM area Slave addr 0 3 unint32 variable 7 bit slave address Slave mask 0 3 unint32 variable Slave address mask Return ErrorCode Description Sets the slave address and associated mask The set slave addr function supports four 7 bit slave addresses and masks I2C Get Memory Size Table 285 12C Get Memory Size Routine I2C Get Memory Size Prototype uint32 ti2c get mem size void Input parameter None Return uint32 Description Returns the number of bytes in SRAM needed by the 12 driver I2C Setup Table 286 12 Setup Routine I2C Setup Prototype I2C HANDLE T i2c setup i2c base addr start of ram Input parameter Return Description I2C base addr unint32 variable Base address for I2C peripherals Start of ram unint32 pointer Pointer to allocated SRAM I2C Handle Returns a handle to the allocated SRAM area 12C Set Bit Rate Table 287 12 Set Bit Rate Routine Prototype Input parameter Return Description 12C Set Bit Rate ErrorCode t i2c set bitrate Il2C HANDLE P clk in hz bitrate in bps I2C HANDLE T Handle to the allocated SRAM area P clk in hz unint32 variable The Peripheral Clock in Hz Bitrate in bps unint32 variable Requested 12 operating frequency in Hz
32. UM10601 3 4 3 Chapter 3 LPC81x Nested Vectored Interrupt Controller NVIC Table 6 Interrupt clear enable register 0 ICERO address 0xE000 E180 Bit Symbol Description Reset value 0 ICE_SPIO Interrupt disable 0 1 ICE_SPI1 Interrupt disable 0 2 Reserved 3 ICE_UARTO Interrupt disable 0 4 ICE_UART1 Interrupt disable 0 5 ICE_UART2 Interrupt disable 0 6 Reserved 7 Reserved 8 ICE I2C Interrupt disable 0 9 ICE SCT Interrupt disable 0 10 ICE MRT Interrupt disable 0 11 ICE CMP Interrupt disable 0 12 ICE WDT Interrupt disable 0 13 ICE BOD Interrupt disable 0 14 ICE FLASH Interrupt disable 0 15 ICE WKT Interrupt disable 0 23 16 Reserved 24 ICE_PININTO Interrupt disable 0 25 ICE_PININT1 Interrupt disable 0 26 ICE_PININT2 Interrupt disable 0 27 ICE_PININT3 Interrupt disable 0 28 ICE_PININT4 Interrupt disable 0 29 ICE_PININT5 Interrupt disable 0 30 ICE_PININT6 Interrupt disable 0 31 ICE_PININT7 Interrupt disable 0 Interrupt Set Pending Register 0 register The ISPRO register allows setting the pending state of the peripheral interrupts or for reading the pending state of those interrupts Clear the pending state of interrupts through the ICPRO registers Section 3 4 4 The bit description is as follows for all bits in this register Write Writing 0 has no effect writing 1 changes the interrupt state to pending Read 0 indicates that the interrupt is not pending 1 indicates
33. eee use Ys lt gt lt gt lt gt First data frame Frame_delay Second data frame Fig 38 Frame_delay timing UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 249 of 370 NXP Semiconductors U M1 0601 Chapter 17 LPC81x SPIO 1 17 7 2 3 Transfer delay The Transfer delay value controls the minimum amount of time that SSEL is deasserted between transfers because the EOT bit 1 When Transfer delay 0 SSEL may be deasserted for a minimum of one SPI clock time Transfer delay is illustrated by the examples in Figure 39 Transfer delay Transfer delay 1 Pre delay 0 Post delay 0 skcraueo of VL PVP VL O _ Dm SSEL de ee Jo X to ox 0M J vosi X e y X we X Xue X miso wee X use Ces X o9 X 1 gt lt gt First data frame Transfer delay Second data frame Transfer delay Transfer delay 1 Pre delay 0 Post delay 0 exe 1 AUE sekcru n i VE LP VS PP WAWA SSEL Pc ee eh MEME J MSB y LBs Y Y LSB Y CES miso X X088 C 58 1 gt lt gt First data frame Transfer _delay Second data frame Fig 39 Tra
34. reset level 0 changed to reserved in Table 41 control register BODCTRL address 0x4004 8150 bit description All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 3 of 370 NXP Semiconductors U M1 0601 LPC81x User manual Revision history continued Rev Date Description 1 1 20130124 LPC800 user manual Modifications Flash signature creation algorithm corrected See Section 19 5 1 Flash signature generation System PLL output frequency restricted to lt 100 MHz MTB register memory space changed to 1 kB in Figure 2 LPC800 Memory mapping Description of the External trace buffer command register updated See Section 4 6 20 External trace buffer command register Flash interrupt removed in Table 3 Chapter 27 summarizing the ARM Cortex MO instruction set added ISP Read CRC checksum command added See Section 21 5 1 15 Read CRC checksum address no of bytes gt Section 20 3 1 Boot loader versions added MRT implementation changed to 31 bit timer See Chapter 11 Bit description of Table 140 Idle channel register IDLE CH address 0x4000 40F4 bit description corrected Updates for clarification in Chapter 17 LPC800 SPIO 1 Updates for clarification in Chapter 16 LPC800 I2C bus interface Updates for clarification in Chapter 15 LPC800 USARTO 1 2 Updat
35. 0 7 Input 7 Selects the pin selected in the PINTSEL7 register as the source to bit slice 3 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 109 of 370 NXP Semiconductors UM10601 Chapter 8 LPC81x Pin interrupts pattern match engine Table 104 Pattern match bit slice source register PMSRC address 0xA000 402C bit description Bit Symbol Value Description Reset value 22 20 SRC4 Selects the input source for bit slice 4 0 0x0 Input 0 Selects the pin selected in the PINTSELO register as the source to bit slice 4 0 1 Input 1 Selects the pin selected the PINTSEL1 register as the source to bit slice 4 0x2 Input 2 Selects the pin selected in the PINTSEL2 register as the source to bit slice 4 0x3 Input 3 Selects the pin selected in the PINTSELS register as the source to bit slice 4 0 4 Input 4 Selects the pin selected in the PINTSEL4 register as the source to bit slice 4 0 5 Input 5 Selects the pin selected the PINTSEL5 register as the source to bit slice 4 0x6 Input 6 Selects the pin selected in the PINTSEL6 register as the source to bit slice 4 0 7 Input 7 Selects the pin selected in the PINTSEL7 register as the source to bit slice 4 25 23 SRC5 Selects the input source for bit slice 5 0 0x0 Input 0 Selects the pin selected in the PINTSELO register as the source to bit slice 5 0 1 Input 1
36. 111 0x0000 1800 0x0000 1BFF yes yes 7 1 112 127 0x0000 1C00 0x0000 1FFF yes yes 8 1 128 143 0 0000 2000 0x0000 23FF yes 9 1 144 159 0x0000 2400 0x0000 27FF yes 10 1 160 175 0 0000 2800 0x0000 2BFF yes 11 1 176 191 0x0000 2 00 0x0000 2FFF yes 12 1 192 207 0 0000 3000 0x0000 33FF yes 13 1 208 223 0 0000 3400 0x0000 37FF yes 14 1 224 239 0x0000 3800 0x0000 3BFF yes 15 1 240 255 0 0000 3C00 0x0000 3FFF yes Flash content protection mechanism The part is equipped with the Error Correction Code ECC capable Flash memory The purpose of an error correction module is twofold The ECC first decodes data words read from the memory into output data words Then the ECC encodes data words to be written to the memory The error correction capability consists of single bit error correction with Hamming code The operation of the ECC is transparent to the running application The ECC content itself is stored in a flash memory not accessible by the user s code to either read from it or write into it on its own 6 bit of ECC corresponds to every consecutive 32 bit of the user accessible Flash Consequently Flash bytes from 0x0000 0000 to 0x0000 0003 are protected by the first 6 bit ECC Flash bytes from 0x0000 0004 to 0x0000 0007 are protected by the second 6 bit ECC byte etc Whenever the CPU requests a read from the user accessible Flash both 32 bits of raw data containing the specified memory l
37. 272 of 370 NXP Semiconductors U M1 0601 Chapter 21 LPC81x Boot ROM The boot rom structure should be included as follows typedef struct ROM API const uint32 t unused 3 const PWRD API T pPWRD const uint32 t p devil const I2CD API T pI2CD const uint32 t p dev3 const uint32 t p dev4 const uint32 t p dev5 const UARTD API T pUARTD ROM API define ROM DRIVER BASE OxlFFF1FF8UL Table 232 API calls API Description Reference Flash IAP Flash In Application programming Table 256 Power profiles Configure system clock and power consumption Table 269 I2C driver 12C ROM Driver Table 272 UART driver USART ROM Driver Table 293 21 6 Functional description UM10601 21 6 1 21 6 2 Memory map after any reset The boot block is 8 kB in size The boot block is located in the memory region starting from the address 0x1FFF 0000 The bootloader is designed to run from this memory area but both the ISP and IAP software use parts of the on chip RAM The RAM usage is described in Section 22 6 2 Memory and interrupt use for ISP and IAP The interrupt vectors residing in the boot block of the on chip flash memory also become active after reset i e the bottom 512 bytes of the boot block are also visible in the memory region starting from the address 0x0000 0000 Boot process During the boot process the boot loader checks if there is valid user code in flash The criterion for va
38. 282 22 5 1 8 Go address mode 284 22 5 1 9 Erase sector s start sector number end sector number 284 22 5 1 10 Blank check sector s sector number end sector number 285 22 5 1 11 Read Part Identification number 285 22 5 1 12 Read Boot code version number 286 22 5 1 13 Compare lt address1 gt lt address2 gt no of bytes 286 22 5 1 14 ReadUID 286 22 5 1 15 Read CRC checksum address no of bytes 286 22 5 1 16 UART ISP Return Codes 287 22 5 2 IAP 5 288 22 5 2 1 Prepare sector s for write operation IAP 290 22 5 2 2 RAM to flash IAP 290 22 5 2 3 Erase Sector s 291 22 5 2 4 Blank check sector s 292 NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 367 of 370 NXP Semiconductors UM10601 22 5 2 5 Read Part Identification number IAP 292 22 5 2 6 Read Boot code version number 292 22 5 2 7 Compare lt address1 gt lt address2 gt no of bytes IAP oi beth x REIR 293 22 5 2 8 Reinvoke ISP 294 225 2 9 ReadUlD IAP 294 22 5 2 10 Erase 294 22 5 2 11 IAP
39. 38 OxE000 E180 essere mes 17 Table 32 CLKOUT clock source select register Table 7 Interrupt set pending register register ISPRO CLKOUTSEL address 0x4004 80E0 bit address 0xE000 E200 bit description 17 description 38 Table 8 Interrupt clear pending register 0 register ICPRO Table 33 CLKOUT clock source update enable register address 0xE000 E280 bit description 18 CLKOUTUEN address 0x4004 80E4 bit Table 9 Interrupt Active Bit Register 0 IABRO address lt 39 OxE000 E300 bit description 19 Table 34 CLKOUT clock divider registers CLKOUTDIV Table 10 Interrupt Priority Register 0 IPRO address address 0x4004 80E8 bit description 39 OxE000 E400 bit description 20 Table 35 USART fractional generator divider value register Table 11 Interrupt Priority Register 1 IPR1 address UARTFRGDIV address 0x4004 80F0 bit OxE000 E404 bit description 20 description 40 Table 12 Interrupt Priority Register 2 IPR2 address Table 36 USART fractional generator multiplier value OxE000 E408 bit description 21 register UARTFRGMULT address 0x4004 80F4 Table 13 Interrupt Priority Register 3 IPR3 address bit 40 OxE000 E40C bit description 21 Table 37 External trace buffer command register T
40. Chapter 27 LPC81x Packages and pin description Table 305 Pin description table fixed pins Symbol Type Reset Description z state o eo X do N T amp a 899g ooo Or F A RESET PIOO 5 4 3 1 41 PU RESET External reset input A LOW going pulse as short as 50 ns on this pin resets the device causing I O ports and peripherals to take on their default states and processor execution to begin at address 0 PIOO 5 General purpose digital input output pin PIOO0 6 VDDCMP 18 15 VO i PU PIOO 6 General purpose digital input output pin Al VDDCMP Alternate reference voltage for the analog comparator PIOO 7 17 14 2 1 PU PIOO 7 General purpose digital input output pin PIOO 8 XTALIN 14 11 B O 8 General purpose digital input output pin XTALIN Input to the oscillator circuit and internal clock generator circuits Input voltage must not exceed 1 95 V PIOO 9 XTALOUT 13 10 B VO PIOO 9 General purpose digital input output pin O XTALOUT Output from the oscillator circuit PIOO 10 9 8 8 IA PIOO 10 General purpose digital input output pin Assign 12C functions to this pin when true open drain pins are needed for a signal compliant with the full I2C specification PIOO 11 8 8 IA PIOO 11 General purpose digital input output pin Assign I2C functions to this pin when true open drain pins are needed for a signal co
41. Digital peripherals software configurable off off off WKT low power software configurable software software software oscillator configurable configurable configurable All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 61 of 370 NXP Semiconductors U M1 0601 UM10601 5 7 2 5 7 3 5 7 3 1 5 7 4 5 7 4 1 Chapter 5 LPC81x Reduced power modes and Power Management Remark The Debug mode is not supported in Sleep Deep sleep Power down or Deep power down modes Reduced power modes and WWDT lock features The WWDT lock feature influences the power consumption in any of the power modes because locking the WWDT clock source forces the watchdog oscillator to be on independently of the Deep sleep and Power down mode software configuration through the PDSLEEPCFG register For details see Section 12 5 3 Using the WWDT lock features Active mode In Active mode the ARM Cortex MO core memories and peripherals are clocked by the system clock or main clock The chip is in Active mode after reset and the default power configuration is determined by the reset values of the PDRUNCFG and SYSAHBCLKCTRL registers The power configuration can be changed during run time Power configuration in Active mode Power consumption in Active mode is determined by the following configuration choices
42. ISP entry pin on chip versions 1A and 2A and on the DIP8 package see Table 231 For these chip versions and packages a LOW level on this pin during reset starts the ISP command handler See PIOO 12 for all other packages Al 12 Analog comparator input 2 CLKIN External clock input SWDIO PIOO 2 TMS 7 6 4 BIO 1 PU SWDIO Serial Wire Debug I O SWDIO is enabled by default on this pin In boundary scan mode TMS Test Mode Select PIOO 2 General purpose digital input output pin SWCLK PIOO 3 6 5 BIO SWCLK Serial Wire Clock SWCLK is enabled by default on TCK this pin In boundary scan mode TCK Test Clock lO PIOO 3 General purpose digital input output pin 4 WAKEUP 5 4 2 E VO 1 PIO0_4 General purpose digital input output pin TRST In ISP mode this is the USARTO transmit pin UO TXD In boundary scan mode TRST Test Reset This pin triggers a wake up from Deep power down mode If you need to wake up from Deep power down mode via an external pin do not assign any movable function to this pin Pull this pin HIGH externally to enter Deep power down mode Pull this pin LOW to exit Deep power down mode A LOW going pulse as short as 50 ns wakes up the part UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 334 of 370 NXP Semiconductors U M1 0601
43. If the delay of the input signal must be minimized select a faster PCLK and a higher sample mode S MODE to minimize the effect of the potential extra clock cycle All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 70 of 370 NXP Semiconductors UM10601 Chapter 6 LPC81x I O configuration IOCON If the sensitivity to noise spikes must be minimized select a slower PCLK and lower sample mode Related registers and links Table 39 IOCON glitch filter clock divider registers 6 to 0 IDOCONCLKDIV 6 0 address 0x4004 8134 IOCONCLKDIV6 to 0x004 814C IOCONFILTCLKDIVO bit description 6 5 Register description Each port pin PlOn m has one IOCON register assigned to control the pin s function and electrical characteristics Table 61 Register overview I O configuration base address 0x4004 4000 Name Access Address Description Reset value Reference offset PIOO 17 R W 0x000 I O configuration for pin PIOO 17 0x0000 0090 Table 62 PIOO 13 R W 0x004 I O configuration for pin PIOO 13 0x0000 0090 Table 63 PIOO 12 R W 0x008 I O configuration for 12 0x0000 0090 Table 64 PIOO 5 R W 0x00C I O configuration for pin PIOO 5 RESET 0 0000 0090 Table 65 PIOO 4 R W 0x010 I O configuration for PIOO 4 0x0000 0090 Table 66 PIOO 3 R W 0x014 configuration for pin 0x0000 0090 Table 67 PIOO
44. Interrupt active Reset value NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 19 of 370 NXP Semiconductors UM10601 UM10601 3 4 6 3 4 7 Chapter 3 LPC81x Nested Vectored Interrupt Controller NVIC Table 9 Interrupt Active Bit Register 0 IABRO address 0xE000 E300 bit description Bit Symbol Function Reset value 9 IAB_SCT Interrupt active 0 10 IAB Interrupt active 0 11 IAB Interrupt active 0 12 IAB WDT Interrupt active 0 13 IAB Interrupt active 0 14 FLASH Interrupt active 0 15 IAB Interrupt active 0 23 16 Reserved 24 IAB_PININTO Interrupt active 0 25 IAB_PININT1 Interrupt active 0 26 IAB_PININT2 Interrupt active 0 27 IAB_PININT3 Interrupt active 0 28 IAB_PININT4 Interrupt active 0 29 IAB_PININT5 Interrupt active 0 30 IAB_PININT6 Interrupt active 0 31 IAB_PININT7 Interrupt active 0 Interrupt Priority Register 0 The IPRO register controls the priority of four peripheral interrupts Each interrupt can have one of 4 priorities where 0 is the highest priority Table 10 Interrupt Priority Register 0 IPRO address 0xE000 E400 bit description Bit Symbol Description 5 0 These bits ignore writes and read as 0 7 6 IP_SPIO Interrupt Priority 0 highest priority 3 lowest priority 13 8 These bits ignore writes and read as O 15 14 IP_SPI1 Interrupt Priority 0 highest priority 3 lo
45. MSTPENDING MSTARBLOSS MSTSTSTPERR SLVPENDING SLVNOTSTR SLVDESEL MONRDY MONOV MONIDLE EVENTTIMEOUT SCLTIMEOUT Description Reset value Master Pending 1 Reserved Master Arbitration Loss flag 0 Reserved Read value is undefined only zero should be NA written Master Start Stop Error flag 0 Reserved Read value is undefined only zero should be NA written Slave Pending 0 Reserved Read value is undefined only zero should be NA written Slave Not Stretching status 1 Reserved Read value is undefined only zero should be NA written Slave Deselected flag Monitor Ready Monitor Overflow flag Reserved Read value is undefined only zero should be NA written Monitor Idle flag 0 Reserved Read value is undefined only zero should be NA written Event time out Interrupt flag SCL time out Interrupt flag 0 Reserved Read value is undefined only zero should be NA written Master Control register The MSTCTL register contains bits that control various functions of the I2C Master interface Only write to this register when the master is pending MSTPENDING 1 in the STAT register Table 186 Table 194 Master Control register MSTCTL address 0x4005 0020 bit description Bit Symbol Value Description Reset value 0 MSTCONTINUE Master Continue This bit is write only 0 0 No effect Continue Informs the Master function to continue to the next operation This must be done a
46. NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 75 of 370 NXP Semiconductors UM10601 6 5 5 PIOO 4 register Table 66 PIOO 4 register PIOO 4 address 0x4004 4010 bit description Chapter 6 LPC81x I O configuration IOCON Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor 0b10 control 0x0 Inactive no pull down pull up resistor enabled 0 1 Pull down resistor enabled 0 2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled Remark This is not a true open drain mode 12 11 5 MODE Digital filter sample mode 0 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than one filter clock are rejected 0 2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 15 13 CLK_DIV Select peripheral clock divider for input filter sampling clock 0 Value 0x7 is reserved 0x0 IOCONCLKDIVO 0 1 IOCONCLKDIV1 0 2 IOCONCLKDIV2 0x3 IOCONCLKDIVS 0x4 IOCONCLKDIVA 0x5 IOCONCLKDIV5 0 6 IOCONCLKDIVE 31 16 E Reserved 0 UM1060
47. PINTSEL4 R W 0x188 GPIO Pin Interrupt Select register 4 0 Table 44 PINTSEL5 R W 0x18C GPIO Pin Interrupt Select register 5 0 Table 44 PINTSEL6 R W 0x190 GPIO Pin Interrupt Select register 6 0 Table 44 PINTSEL7 R W 0x194 GPIO Pin Interrupt Select register 7 0 Table 44 STARTERPO R W 0x204 Start logic 0 pin wake up enable register 0 Table 45 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 28 of 370 NXP Semiconductors U M1 0601 Chapter 4 LPC81x System configuration SYSCON Table 17 Register overview System configuration base address 0x4004 8000 continued Name Access Offset Description Reset value Reference STARTERP1 R W 0x214 Start logic 1 interrupt wake up enable 0 Table 46 register PDSLEEPCFG R W 0x230 Power down states in deep sleep mode OxFFFF Table 47 PDAWAKECFG R W 0x234 Power down states for wake up from OxEDFO Table 48 deep sleep PDRUNCFG R W 0x238 Power configuration register OxEDFO Table 49 DEVICE ID R Ox3F8 Device ID part dependent Table 50 4 6 1 System memory remap register The system memory remap register selects whether the exception vectors are read from boot ROM flash or SRAM By default the flash memory is mapped to address 0x0000 0000 When the MAP bits in the SYSMEMREMAP register are set to 0 0 or 0 1 the boot ROM or RAM respectively are mapped to the bottom 512 bytes of the mem
48. Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor 0b10 control 0x0 Inactive no pull down pull up resistor enabled 0 1 Pull down resistor enabled 0 2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 5 Reserved 0b001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled Remark This is not a true open drain mode 12 11 5 MODE Digital filter sample mode 0 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than one filter clock are rejected 0 2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 1543 CLK_DIV Select peripheral clock divider for input filter sampling clock 0 Value 0 7 is reserved 0 0 IOCONCLKDIVO 0 1 IOCONCLKDIV1 0 2 IOCONCLKDIV2 0x3 IOCONCLKDIV3 0x4 IOCONCLKDIVA 0x5 IOCONCLKDIV5 0 6 IOCONCLKDIVE6 31 16 Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 72 of 370 NXP Semiconductors UM10601 6 5 2 PIOO 13 register Chapter 6 LPC81x I O configuration IOCON Table 63 PIOO_13 register PIOO 13 address
49. See bit slice drawing Figure 9 The pattern match capability can be used to create complex software state machines Each minterm and its corresponding individual interrupt represents a different transition event to a new state Software can then establish the new set of conditions that is a new boolean expression that will cause a transition out of the current state Example Assume the expression INO IN1 IN3 IN1 IN2 INO IN3 IN4 is specified through the registers PMSRC Table 104 and PMCFG Table 105 Each term in the boolean expression INO IN1 IN3 etc represents one bit slice of the pattern match engine Inthe first minterm INO IN1 IN3 bit slice 0 monitors for a high level on input INO bit slice 1 monitors for a low level on input IN1 and bit slice 2 monitors for a rising edge on input IN3 If this combination is detected that is if all three terms are true the interrupt associated with bit slice 2 PININT2 IRQ will be asserted Inthe second minterm IN1 IN2 bit slice 3 monitors input IN1 for a high level bit slice 4 monitors input IN2 for a high level If this combination is detected the interrupt associated with bit slice 4 PININT4 IRQ will be asserted n the third minterm INO IN3 IN4 bit slice 5 monitors input INO for a high level bit slice 6 monitors input INS for a low level and bit slice 7 monitors input INA for a low level If this combinat
50. cortex mOp rOpO trm ARM Cortex MO Technical Reference Manual 4 0010486 ARM technical reference manual 5 ARMv6 M Architecture Reference Manual UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 353 of 370 NXP Semiconductors UM10601 30 3 Legal information Chapter 30 Supplementary information 30 3 1 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information 30 3 2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damag
51. or the watchdog oscillator or the IRC oscillator The main system clock clocks the core the peripherals and the memories Bit 0 of the MAINCLKUEN register see Section 4 6 11 must be toggled from 0 to 1 for the update to take effect Table 27 Main clock source select register MAINCLKSEL address 0x4004 8070 bit description Bit Symbol Value Description Reset value 1 0 SEL Clock source for main clock 0 0x0 IRC Oscillator 0 1 PLL input 0 2 Watchdog oscillator 0x3 PLL output 31 22 Reserved Main clock source update enable register This register updates the clock source of the main clock with the new input clock after the MAINCLKSEL register has been written to In order for the update to take effect first write a zero to bit O of this register then write a one Table 28 Main clock source update enable register MAINCLKUEN address 0x4004 8074 bit description Bit Symbol Value Description Reset value 0 ENA Enable main clock source update 0 0 No change 1 Update clock source 31 1 Reserved UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 35 of 370 NXP Semiconductors U M1 0601 UM10601 4 6 12 4 6 13 Chapter 4 LPC81x System configuration SYSCON System clock divider register This register controls how the main clock is divided to provide the system clock to the cor
52. rCode t i2c slave receive intr I2C HANDLE T h i2c I2C PARAM ptp I2C RESULT i2c slave transmit intr I2C HANDLE T h i2c I2C PARAM ptp uint32 t slave addr 0 3 uint32 t slave mask 0 3 void i2c handler MASTER functions ErrorCode t i2c ErrorCode t i2c master ErrorCode t i2c master ErrorCode t i2c master 12C RESULT ptr ErrorCode t i2c master 12C RESULT ptr ErrorCode t i2c ptr SLAVE functions ErrorCode t i ErrorCode_t i 12C RESULT ptr Erro ErrorCode_t 12C RESULT ptr ErrorCode t i2c set slave addr I2C HANDLE T h i2c OTHER functions uint32 t i2c get mem size void ramsize in bytes memory needed by I2C drivers UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 308 of 370 NXP Semiconductors U M1 0601 Chapter 24 LPC81x I2C bus ROM API I2C HANDLE T i2c setup uint32 t i2c base addr uint32 t start of ram ErrorCode t i2c set bitrate I2C HANDLE T h i2c uint32 t P clk in hz uint32 t bitrate in bps uint32 t i2c get firmware version 2 MODE T i2c get status I2C HANDLE T h i2c I2CD API T define ROM DRIVER BASE OxlFFFlFF8UL define LPC I2CD I2CD T ROM T ROM DRIVER BASE pI2CD See Section
53. 0 3 TXUR Transmitter Underrun interrupt flag 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 245 of 370 NXP Semiconductors U M1 0601 Chapter 17 LPC81x SPIO 1 Table 214 SPI Interrupt Status register INTSTAT addresses 0x4005 8028 SPIO 0x4005 C028 SPI1 bit description Bit Symbol Description Reset value 4 SSA Slave Select Assert 0 5 SSD Slave Select Deassert 0 31 6 Reserved Read value is undefined only zero should be written NA UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 246 of 370 NXP Semiconductors U M1 0601 Chapter 17 LPC81x SPIO 1 17 7 Functional description 17 7 1 Operating modes clock and phase selection SPI interfaces typically allow configuration of clock phase and polarity These are sometimes referred to as numbered SPI modes as described in Table 215 and shown in Figure 36 CPOL and CPHA are configured by bits in the CFG register Section 17 6 1 Table 215 SPI mode summary SPI SCKrest data SCK data moe Mode Description state change edge sample edge The SPI captures serial data on the first clock transition of 0 0 the transfer when the clock changes away from the rest low falling rising state Data is changed on the
54. 0 RO 1 RO 0 W1 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 239 of 370 NXP Semiconductors U M1 0601 Chapter 17 LPC81x SPIO 1 Table 206 SPI Status register STAT addresses 0x4005 8008 SPIO 0x4005 C008 SPI1 bit description Bit Symbol Description Reset Access value 11 7 ENDTRANSFER Transfer control bit Software can set this bit to force an end to the current 0 RO W1 transfer when the transmitter finishes any activity already in progress as if the EOT flag had been set prior to the last transmission This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer The bit is cleared when the transmitter becomes Idle as the transfer comes to an end Forcing an end of transfer in this manner causes any specified FrameDelay and TransferDelay to be inserted 8 MSTIDLE Master idle status flag This bit is 1 whenever the SPI master function is fully 1 RO idle This means that the transmit holding register is empty and the transmitter is not in the process of sending data 31 9 Reserved Read value is undefined only zero should be written NA NA 1 RO Read only W1 write 1 to clear 17 6 4 SPI Interrupt Enable read and Set register The INTENSET register is used to enable various SPI interrupt sources Enable b
55. 0 SPIO SPIO interrupt wake up 0 0 Disabled 1 Enabled 1 SPI1 SPI interrupt wake up 0 0 Disabled 1 Enabled Reserved USARTO USARTO interrupt wake up Configure USART 0 in synchronous slave mode 0 Disabled 1 Enabled 4 USART1 USART1 interrupt wake up Configure USART 0 in synchronous slave mode 0 Disabled 1 Enabled 5 USART2 USART2 interrupt wake up Configure USART 0 in synchronous slave mode 0 Disabled 1 Enabled 7 6 Reserved 12 12 interrupt wake up 0 0 Disabled 1 Enabled 11 9 Reserved 12 WWDT WWDT interrupt wake up 0 0 Disabled 1 Enabled 13 BOD BOD interrupt wake up 0 0 Disabled 1 Enabled 14 Reserved UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 45 of 370 NXP Semiconductors U M1 0601 UM10601 4 6 30 4 6 31 Chapter 4 LPC81x System configuration SYSCON Table 46 Start logic 1 interrupt wake up enable register STARTERP1 address 0x4004 8214 bit description continued Bit Symbol Value Description Reset value 15 WKT Self wake up timer interrupt wake up 0 0 Disabled 1 Enabled 31 16 Reserved Deep sleep mode configuration register The bits in this register BOD_PD and WDTOSC_OD can be programmed to control aspects of Deep sleep and Power down modes The bits are loaded into corresponding bits of the PDRUNCFG register when Deep sleep mode or Power down mode is
56. 1 The following conditions must be fulfilled to use the I2C driver routines in master mode For 7 bit addressing the first byte of the send buffer must have the slave address in the most significant 7 bits and the least significant R W bit 2 0 Example Slave address 0x53 first byte is OxA6 For 7 bit addressing the first byte of the receive buffer must have the slave address in the most significant 7 bits and the least significant R W bit 1 Example Slave 0x53 first byte OxA7 For 10 bit address the first byte of the transmit buffer must have the slave address most significant 2 bits with the R W bit 0 The second byte must contain the remaining 8 bit of the slave address For 10 bit address the first byte of the receive buffer must have the slave address most significant 2 bits with the R W bit 21 The second byte must contain the remaining 8 bit of the slave address The number of bytes to be transmitted should include the first byte of the buffer which is the slave address byte Example 2 data bytes 7 bit slave addr 3 e The application program must enable 12C interrupts When I2C interrupt occurs the i2c isr handler function must be called from the application program When using the interrupt function calls the callback functions must be define Upon the completion of a read write as specified by the PARAM structure the callback functions will be invoked UM10601 All information provide
57. 16 3 1 Chapter 16 LPC81x I2C bus interface SYSCON 12C function clock system clock I2C PCLK sampling Clock divider time out Clock logic SYSAHBCLKCTRL 5 METHME I2C clock enable MSTSCLHIGH MSTSCLLOW Fig 32 12 clocking 12C transmit receive in master mode In this example the LPC81x I2C is configured as the master The master sends 8 bits to the slave and then receives 8 bits from the slave The system clock is set to 30 MHz and the bit rate is about 400 KHz Therefore you can select any pin for the I2CO_SCL and I2CO0 SDA functions Special open drain I2C pads are optional The transmission of the address and data bits is controlled by the state of the MSTPENDING status bit Whenever the status is Master pending the master can read or write to the MSTDAT register and go to the next step of the transmission protocol by writing to the MSTCTRL register Configure the pins e Select two pins for I2CO SCL and I2CO SDA through the switch matrix See Table 183 Inthe IOCON register for the selected pins disable the internal pull up if using a standard digital I O pin Configure the 12C bit rate Divide the system clock I2C PCLK by a factor of 2 See Table 192 12C Clock Divider register CLKDIV address 0x4005 0014 bit description Set the SCL high and low times to 2 clock cycles each This is the default See Table 195 Master Time register MSTTIME address 0x4005 0024 bit
58. 234 of 370 NXP Semiconductors U M1 0601 Chapter 17 LPC81x SPIO 1 17 5 General description Tx Shift Register amp State Machine 5 interrupts Inte rrupt control Rx interrupts Rx Shift Register SPIn RXDAT amp State Machine SSEL pin RxSSEL SSA SSD levels RxRdy RxOv SSEL SPIn TXDAT SPI interrupt General controls amp format configurations 1 ped SPOL DivVal SSEL field internal SPI_PCLK clock s Clock divider 1 Includes CPOL CPHA LSBF FLEN master enable transfer delay frame delay pre delay post delay SOT EOT EOF RXIgnore individual interrupt enables Fig 35 SPI block diagram 17 6 Register description The Reset Value reflects the data stored in used bits only It does not include reserved bits content See Section 29 3 Code examples SPI for code examples that explain how to program the register interface UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 235 of 370 NXP Semiconductors UM10601 UM10601 Chapter 17 LPC81x SPIO 1 Table 203 Register overview SPI base address 0x4005 8000 SPIO and 0x4008 C000 SPI1 Name Access Offset Description Reset Reference value CFG R W 0x000 Configuration register 0 Table 204 DLY R W 0x00
59. Both the BOD interrupt and the BOD reset depending on the value of bit BODRSTENA in this register can wake up the chip from Sleep Deep sleep and Power down modes See the LPC81x data sheet for the BOD reset and interrupt levels All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 41 of 370 NXP Semiconductors U M1 0601 UM10601 4 6 24 4 6 25 Chapter 4 LPC81x System configuration SYSCON Table 40 BOD control register BODCTRL address 0x4004 8150 bit description Bit Symbol Value Description Reset value 1 0 BODRSTLEV BOD reset level 0 0x0 Reserved 0 1 Level 1 0 2 Level 2 0x3 Level 3 3 2 BODINTVAL BOD interrupt level 0 0x0 Reserved 0 1 Level 1 0 2 Level 2 0x3 Level 3 4 BODRSTENA BOD reset enable 0 0 Disable reset function 1 Enable reset function 31 5 Reserved 0x00 System tick counter calibration register This register determines the value of the SYST_CALIB register Table 41 System tick timer calibration register SYSTCKCAL address 0x4004 8154 bit description Bit Symbol Description Reset value 25 0 CAL System tick timer calibration value 0 31 26 Reserved IRQ latency register The IRQLATENCY register is an eight bit register which specifies the minimum number of cycles 0 255 permitted for the system to respond to an interrupt request The intent of this reg
60. Enable rising edge or level interrupt 31 8 Reserved Pin interrupt level or rising edge interrupt clear register For each of the 8 pin interrupts selected in the PINTSELn registers see Section 4 6 27 one bit in the CIENR register clears the corresponding bit in the IENR register depending on the pin interrupt mode configured in the ISEL register e f the pin interrupt mode is edge sensitive PMODE 0 the rising edge interrupt is cleared e If the pin interrupt mode is level sensitive PMODE 1 the level interrupt is cleared All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 103 of 370 NXP Semiconductors U M1 0601 Chapter 8 LPC81x Pin interrupts pattern match engine Table 96 Pin interrupt level or rising edge interrupt clear register CIENR address 0xA000 400C bit description Bit Symbol Description Reset Access value 7 0 CENRL Ones written to this address clear bits in the IENR thus NA WO disabling the interrupts Bit n clears bit n in the IENR register 0 No operation 1 Disable rising edge or level interrupt 31 8 Reserved 8 6 5 Pin interrupt active level or falling edge interrupt enable register For each of the 8 pin interrupts selected in the PINTSELn registers see Section 4 6 27 one bit in the IENF register enables the falling edge interrupt or the configur
61. ErrorCode Configures the I2C duty cycle registers SCLH and SCLL All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 313 of 370 NXP Semiconductors UM10601 Chapter 24 LPC81x I2C bus ROM API 24 4 16 12 Get Firmware Version Table 288 12 Get Firmware Version Routine Prototype Input parameter Return Description I2C Get Firmware Version uint32 ti2c get firmware version void None I2C ROM Driver version number Returns the version number The firmware version is an unsigned 32 bit number 24 4 17 12 Get Status Table 289 12 Get Status Routine Prototype Input parameter Return Description I2C Get Status I2C MODE T i2c get status I2C HANDLE I2C HANDLE T Handle to the allocated SRAM area Status code Returns status code The status code indicates the state of the 12C bus Refer to I2C Status Code Table 24 4 48 12C time out value Table 290 12 time out value Routine Prototype Input parameter Return Description I2C time out value ErrorCode ti2c set timeout I2C HANDLE h i2c uint32 t timeout I2C HANDLE T Handle to the allocated SRAM area uint32 t timeout time value is timeout 16 i2c function clock If timeout 0 timeout feature is disabled Status code Returns status code The status code indicates the state of the
62. I2C gt STAT amp CTL 12C_MS1 _12C gt STAT amp CTL 12C_MS1 le LPC_I2C gt STAT amp 12C CFG MSTEN AT amp I2C STAT 0x23 1 2C_S AT amp I2C STAT 0xaa se I2C MSTCTL 2C S AT amp I2C STAT 0xdd se 2C_S 2C STAT 2C_S AT amp if LPC I2C 5 1 AT amp I2C STAT STSTAT STSTAR MS STSTA nd suba STCON MS STSTA nd data STCONT TAT_MST STSTAT STSTOP TAT_MST STSTAT E IPE TE dd TIN IPR while LPC_I2C gt STAT amp I2C STAT MSTPENDING l I2C STAT MSTST IDLE 0 address and 0 for RWn bit in order to write send start DINC l 2 STA ress UE cont DING l 2 STA UE cont DING I2C STA send stop DING I2C STA inue t I MSTS inue t I MSTS abort MSTSTX abort ransaction IX abort ransaction IX abort MSTST _IDLE abort UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 342 of 370 NXP Semiconductors UM10601 UM10601 29 2 6 29 2 7 Chapter 29 LPC81x Code examples Master read one byte from subaddress on slave Table 312 12C Code example Master read one byte from subaddress on slave Address 0x23
63. Idle The Master function is available to be used for a new transaction Receive ready Received data available Master Receiver mode Address plus Read was previously sent and Acknowledged by slave Transmit ready Data can be transmitted Master Transmitter mode Address plus Write was previously sent and Acknowledged by slave NACK Address Slave NACKed address NACK Data Slave NACKed transmitted data Master Arbitration Loss flag This flag can be cleared by software 0 W1 writing a 1 to this bit It is also cleared automatically a 1 is written to MSTCONTINUE No loss No Arbitration Loss has occurred Arbitration loss The Master function has experienced an Arbitration Loss At this point the Master function has already stopped driving the bus and gone to an idle state Software can respond by doing nothing or by sending a Start in order to attempt to gain control of the bus when it next becomes idle 5 Reserved Read value is undefined only zero should be written NA NA UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 215 of 370 NXP Semiconductors UM10601 Chapter 16 LPC81x I2C bus interface Table 186 I2C Status register STAT address 0x4005 0004 bit description continued Bit Symbol 6 MSTSTSTPERR SLVPENDING 10 9 SLVSTATE 11 SLVNOTSTR 13 12 SLVIDX UM10601 Value Descrip
64. LOGIC PMSCR bits SCRn all pins PlOO_m PINTSEL7 slice n 1 endpoint configured PMCFG bit n 1 1 PROD_ENDPTS tied HIGH for slice 7 DETECT NVIC pin interrupt n 1 LOGIC c ra 7 v a ao e gt a to IN7 Slice 2 to slice 2 to INO Slice n 2 See Figure 9 for the detect logic block Fig 8 Pattern match engine connections UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 99 of 370 NXP Semiconductors U M1 0601 Chapter 8 LPC81x Pin interrupts pattern match engine The detect logic of each slice can detect the following events on the selected input Edge with memory sticky A rising edge a falling edge or a rising or falling edge that is detected at any time after the edge detection mechanism has been cleared The input qualifies as detected the detect logic output remains HIGH until the pattern match engine detect logic is cleared again Event non sticky Every time an edge rising or falling is detected the detect logic output for this pin goes HIGH This bit is cleared after one clock cycle and the detect logic can detect another edge Level A HIGH or LOW level on the selected input Figure 9 shows the details of the edge detection logic for each slice You can combine a sticky event with non sticky events to create a pin interrupt
65. On the assertion of any reset source ARM core software reset POR BOD reset External reset and Watchdog reset the following processes are initiated 1 The IRC starts up After the IRC start up time maximum of 6 us on power up the IRC provides a stable clock output 2 The flash is powered up This takes approximately 100 us Then the flash initialization sequence is started which takes about 250 cycles 3 The boot code in the ROM starts The boot code performs the boot tasks and may jump to the flash When the internal Reset is removed the processor begins executing at address 0 which is initially the Reset vector mapped from the boot block At that point all of the processor and peripheral registers have been initialized to predetermined values Start up behavior See Figure 4 for the start up timing after reset The IRC is the default clock at Reset and provides a clean system clock shortly after the supply voltage reaches the threshold value of 1 8 V All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 49 of 370 NXP Semiconductors U M1 0601 Chapter 4 LPC81x System configuration SYSCON Fig 4 IRC status internal reset VDD valid threshold 1 8V GND processor status Start up timing IRC starts 80 us 101 us supply ramp up boot time gt time
66. PWR_CMD_SUCCESS 0 PWR_INVALID_FREQ 1 PWR_INVALID_MODE 2 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 302 of 370 NXP Semiconductors U M1 0601 23 4 2 1 23 4 2 2 23 4 2 3 Chapter 23 LPC81x Power profile ROM driver For a simplified clock configuration scheme see Figure 47 For more details see Figure 3 ParamO0 main clock The main clock is the clock rate the microcontroller uses to source the system s and the peripherals clock It is configured by either a successful execution of the clocking routine call or a similar code provided by the user This operand must be an integer between 1 to 30 MHz inclusive If a value out of this range is supplied set power returns PWR INVALID FREQ and does not change the power control system Param1 mode The input parameter mode Param7 specifies one of four available power settings If an illegal selection is provided set power returns PWR INVALID MODE and does not change the power control system PWR DEFAULT keeps the device in a baseline power setting similar to its reset state PWR CPU PERFORMANCE configures the microcontroller so that it can provide more processing capability to the application CPU performance is 30 better than the default option PWR EFFICIENCY setting was designed to find a balance between active current and the CPU s ability to
67. Receiver Overrun interrupt flag This flag applies only to slave mode Master 0 This flag is set when the beginning of a received character is detected while the receiver buffer is still in use If this occurs the receiver buffer contents are preserved and the incoming data is lost Data received by the SPI should be considered undefined if RxOv is set Transmitter Underrun interrupt flag This flag applies only to slave mode Master 0 In this case the transmitter must begin sending new data on the next input clock if the transmitter is idle If that data is not available in the transmitter holding register at that point there is no data to transmit and the TXUR flag is set Data transmitted by the SPI should be considered undefined if TXUR is set Slave Select Assert This flag is set whenever any slave select transitions from deasserted to asserted in both master and slave modes This allows determining when the SPI transmit receive functions become busy and allows waking up the device from reduced power modes when a slave mode access begins This flag is cleared by software Slave Select Deassert This flag is set whenever any asserted slave selects transition to deasserted in both master and slave modes This allows determining when the SPI transmit receive functions become idle This flag is cleared by software Stalled status flag This indicates whether the SPI is currently in a stall condition Reset Access value
68. Section 4 6 9 System PLL clock source update register Configure the PLL M and N dividers Section 4 6 3 System PLL control register Wait for the PLL to lock by monitoring the PLL lock status Section 4 6 4 System PLL status register 4 3 2 Configure the main clock and system clock The clock source for the registers and memories is derived from main clock The main clock can be sourced from the IRC at a fixed clock frequency of 12 MHz or from the PLL The divided main clock is called the system clock and clocks the core the memories and the peripherals register interfaces and peripheral clocks 1 Select the main clock You have the following options IRC 12 MHz internal oscillator default PLL output You must configure the PLL to use the PLL output Section 4 6 10 Main clock source select register Update the main clock source Section 4 6 11 Main clock source update enable register Select the divider value for the system clock A divider value of 0 disables the system clock Section 4 6 12 System clock divider register Select the memories and peripherals that are operating in your application and therefore must have an active clock The core is always clocked Section 4 6 13 System clock control register 4 3 3 Set up the system oscillator using XTALIN and XTALOUT If you want to use the system oscillator with the LPC81x you need to assign the XTALIN and X
69. description 5 Disable any special functions on pin PIOO n in the PINENABLEO register 6 Program the pin number n into the bits assigned to FUNC FUNC is now connected to pin x on the package 9 3 2 Enable an analog input or other special function The switch matrix enables functions that can only be assigned to one pin Examples are analog inputs all GPIO pins and the debug SWD pins UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 122 of 370 NXP Semiconductors U M1 0601 Chapter 9 LPC81x Switch matrix f you want to assign a GPIO pin to a pin on any LPC81x package disable any special function available on this pin in the PINENABLEO register and do not assign any movable function to it By default all pins except pins PIOO 2 PIOO 3 and PIOO 5 are assigned to GPIO For all other functions that are not in the table of movable functions do the following a Locate the function in the pin description table in the data sheet This shows the package pin for this function b Enable the function in the PINENABLEO register All other possible functions on this pins are now disabled 9 4 General description The switch matrix connects internal signals functions to external pins Functions are signals coming from or going to a single pin on the package and coming from or going to an on chip peripheral bl
70. event 4 is enabled Configure states in which event 5 is enabled Registers EV2_CTRL EV2 CTRL EV3_CTRL EV4 CTRL EV5 CTRL EV5 CTRL OUTO SET OUTO CLR EVO STATE EV1 STATE EV2 STATE EV3 STATE EVA STATE EV5 STATE Setting Set COMBMODE 0x3 Event 2 uses match condition and I O condition Set IOSEL 0 Select input 0 Set IOCOND 0x0 Input 0 is LOW Set MATCHSEL 0 Chooses match register 0 to qualify the event Set STATEV bits to 1 and the STATED bit to 1 Event 2 changes the state to state 1 Set COMBMODE 0x1 Event uses match condition only e Set MATCHSEL 0x3 Select match value of match register 3 The match value of MATS is associated with event 3 Set COMBMODE 0x1 Event 4 uses match condition only Set MATCHSEL 0x4 Select match value of match register 4 The match value of MAT4 is associated with event 4 e Set COMBMODE 0x3 Event 5 uses match condition and I O condition Set IOSEL 0 Select input 0 Set IOCOND 0x3 Input 0 is HIGH e Set MATCHSEL 0 Chooses match register 0 to qualify the event Set STATEV bits to 0 and the STATED bit to 1 Event 5 changes the state to state 0 Set SETO bits 0 for event 0 and 3 for event 3 to one to set the output when these events 0 and 3 occur Set CLRO bits 1 for events 1 and 4 for event 4 to one to clear the output when events 1 and 4 occur Set STATEMSKO bit 0 to 1 Set all other bits to 0 E
71. f FX MISO _ LSB uss Y ise Y lt gt lt gt First data frame Second data frame Receiver stall 0 Frame delay 0 Pre delay 0 Post delay 0 2 clock stall MdeocPo 9 sk N NV NI NV NN 2 1 SCK V ff WIWU UU MISO _ LSB uss Y ise Y lt gt lt gt First data frame Second data frame Receiver stall 1 Frame delay 0 Pre delay 0 Post delay 0 2 clock stall miso Ymse LSB MSB Y lt gt lt gt First data frame Second data frame Fig 40 Examples of data stalls UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 253 of 370 UM10601 Chapter 18 LPC81x Analog comparator Rev 1 6 2 April 2014 User manual 18 1 How to read this chapter The analog comparator is available on all LPC81x parts 18 2 Features Selectable external inputs can be used as either the positive or negative input of the comparator The Internal voltage reference 0 9 V bandgap reference can be used as either the positive or negative input of the comparator 32 stage voltage ladder can be used as either the positive or negative input of the comparator Voltage ladder source selectable between the supply pin Vpp or VDDCMP pin Voltage ladder can be separately powered down when not re
72. gt INTENSET UART_STAT_TXRDY tx_countertt if intstat amp UART_STAT_TXRDY if tx rdy flag abort tx rdy flag 1 LPC_USART gt INTENCLR UART STAT TXRDY UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 351 of 370 NXP Semiconductors U M1 0601 UM10601 29 4 3 29 4 4 29 4 5 29 4 6 29 4 7 Chapter 29 LPC81x Code examples Transmit one byte of data Table 336 UART Code example Transmit one byte of data LPC_USART gt CFG UART_CFG_DATALEN 8 UART_CFG_ENABLE while LPC_USART gt STAT amp UART STAT TXRDY LPC_USART gt TXDAT 0 4 while LPC USART STAT amp UART_STAT_TXIDLE Receive one byte of data Table 337 UART Code example Receive one byte of data LPC_USART gt CFG UART CFG DATALEN 8 UART CFG ENABLE while LPC USART STAT amp UART STAT RXRDY data LPC_USART gt RXDAT if data Oxdd abort Transmit and receive one byte of data Table 338 UART Code example Transmit and receive one byte of data LPC_USART gt CFG UART_CFG_DATALEN 8 UART_CFG_ENABLE while LPC_USART gt STAT amp UART_STAT_TXRDY LPC_USART gt TXDAT 0xdd while LPC_USART gt STAT amp UART_STAT_RXRDY data LPC_USART gt RXDAT if data Oxdd abort Loop back 10 bytes of data Table 339 UART Code example Loop back 1
73. repeated start nack implied while LPC_I2C gt STAT amp I2C STAT MSTPENDING LPC I2C MSTCTL I2C MSTCTL MSTSTOP stop transaction while LPC_I2C gt STAT amp I2C STAT MSTPENDING if LPC_I2C gt STAT amp I2C STAT MSTSTATE I2C STAT MSTST IDLE abort ra 29 2 11 Master sending nack and repeated start on data Interrupt mode Table 317 12C Code example Master sending nack and repeated start on data Address 0x23 No error checking Interrupt mode LPC_I2C gt CFG I2C CFG MSTEN LPC_I2C gt INTENSET I2C STAT MSTPENDING NVIC_EnableIRQ I2c_IRQn while LPC_I2C gt INTENSET amp I2C_STAT_MSTPENDING if LPC_I2C gt STAT amp I2C STAT MSTSTATE I2C STAT MSTST IDLE abort NVIC DisableIRQ I2c IRQn 29 2 12 Slave read one byte from master Table 318 12C Code example Slave read one byte from master Address 0x23 Polling mode LPC_I2C gt SLVADRO 0x23 lt lt 1 put address in address 0 register LPC I2C CFG I2C SLVEN while LPC_I2C gt STAT amp I2C STAT SLVPENDING if LPC_I2C gt STAT amp I2C STAT SLVSTATE I2C STAT SLVST ADDR abort LPC_I2C gt SLVCTL I2C SLVCTL SLVCONTINUE ack address while LPC_I2C gt STAT amp I2C STAT SLVPENDING if LPC_I2C gt STAT amp I2C STAT SLVSTATE I2C STAT SLVST RX abort data LPC I2C SLVDAT read data if data Oxdd abort LPC_I2C gt SLVCTL I2C SLVCTL
74. to bit slice 6 Input Selects the pin selected in the PINTSEL3 register as the source to bit slice 6 Input 4 Selects the pin selected in the PINTSEL4 register as the source to bit slice 6 Input 5 Selects the pin selected in the PINTSELS register as the source to bit slice 6 Input 6 Selects the pin selected in the PINTSEL6 register as the source to bit slice 6 Input 7 Selects the pin selected in the PINTSEL7 register as the source to bit slice 6 Selects the input source for bit slice 7 Input 0 Selects the pin selected in the PINTSELO register as the source to bit slice 7 Input 1 Selects the pin selected in the PINTSEL1 register as the source to bit slice 7 Input 2 Selects the pin selected in the PINTSEL2 register as the source to bit slice 7 Input 3 Selects the pin selected in the PINTSEL3 register as the source to bit slice 7 Input 4 Selects the pin selected in the PINTSEL4 register as the source to bit slice 7 Input 5 Selects the pin selected in the PINTSELS register as the source to bit slice 7 Input 6 Selects the pin selected in the PINTSEL6 register as the source to bit slice 7 Input 7 Selects the pin selected in the PINTSEL7 register as the source to bit slice 7 Reset value 0 UM10601 8 6 13 Pattern Match Interrupt Bit Slice Configuration register The bit slice configuration register configures the detect logic and contains bits to select from among eight alternative c
75. 0 gt PFD A 2 SYSPLLCLKSEL pd cd LOCK 2P gt DETECT LOCK gt FCLKOUT l analog section pd d cd Fig 5 System PLL block diagram M s MSEL lt 4 0 gt UM10601 4 7 4 1 4 7 4 2 The block diagram of this PLL is shown in Figure 5 The input frequency range is 10 MHz to 25 MHz The input clock is fed directly to the Phase Frequency Detector PFD This block compares the phase and frequency of its inputs and generates a control signal when phase and or frequency do not match The loop filter filters these control signals and drives the current controlled oscillator which generates the main clock and optionally two additional phases The CCO frequency range is 156 MHz to 320 MHz These clocks are either divided by 2xP by the programmable post divider to create the output clocks or are sent directly to the outputs The main output clock is then divided by M by the programmable feedback divider to generate the feedback clock The output signal of the phase frequency detector is also monitored by the lock detector to signal when the PLL has locked on to the input clock Remark The divider values for P and M must be selected so that the PLL output clock frequency FCLKOUT is lower than 100 MHz because the main clock is limited to a maximum frequency of 100 MHz Lock detector The lock detector measures the phase difference between the ri
76. 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 15 13 CLK_DIV Select peripheral clock divider for input filter sampling clock 0 Value 0x7 is reserved 0 0 IOCONCLKDIVO 0 1 IOCONCLKDIV1 0 2 IOCONCLKDIV2 0x3 IOCONCLKDIV3 0 4 IOCONCLKDIVA 0x5 IOCONCLKDIV5 0x6 IOCONCLKDIV6 31 16 Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 82 of 370 NXP Semiconductors UM10601 6 5 12 PIOO 1 register Chapter 6 LPC81x I O configuration IOCON Table 73 1 register PIOO 1 address 0 4004 402C bit description Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor 0b10 control 0x0 Inactive no pull down pull up resistor enabled 0 1 Pull down resistor enabled 0 2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 5 Reserved 0b001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled Remark This is not a true open drain mode 12 11 5 MODE Digital filter sample mode 0 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than one filter clock are rej
77. 11 IPR3 RW 0x40C Interrupt Priority Registers 3 This register allows assigning a priority 0 Table 13 to each interrupt This register contains the 2 bit priority fields for interrupts 12 to 15 0 410 Reserved 0 0x414 Reserved 0 IPR6 RW 0x418 Interrupt Priority Registers 6 This register allows assigning a priority 0 Table 14 to each interrupt This register contains the 2 bit priority fields for interrupts 24 to 27 IPR7 RW 0x41C Interrupt Priority Registers 7 This register allows assigning a priority 0 Table 15 to each interrupt This register contains the 2 bit priority fields for interrupts 28 to 31 3 4 1 Interrupt Set Enable Register 0 register The ISERO register allows to enable peripheral interrupts or to read the enabled state of those interrupts Disable interrupts through the ICERO Section 3 4 2 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 15 of 370 NXP Semiconductors UM10601 UM10601 3 4 2 The bit description is as follows for all bits in this register Write Writing 0 has no effect writing 1 enables the interrupt Chapter 3 LPC81x Nested Vectored Interrupt Controller NVIC Read 0 indicates that the interrupt is disabled 1 indicates that the interrupt is enabled Table 5 Interrupt Set Enable Register 0 register ISERO address 0xE000 E100 bit descr
78. 114 Pin assign register 5 PINASSIGNS address 0x4000 C014 bit description 129 Table 115 Pin assign register 6 PINASSIGN6 address 0x4000 C018 bit description 130 Table 116 Pin assign register 7 PINASSIGN7 address 0x4000 1 bit description 130 Table 117 Pin assign register 8 PINASSIGNS address 0x4000 C020 bit description 131 Table 118 Pin enable register 0 PINENABLEO address 0x4000 C1C0 bit description 131 Table 119 SCT pin description 134 Table 120 Register overview State Configurable Timer base address 0x5000 4000 Table 121 SCT configuration register CONFIG address 0x5000 4000 bit description Table 122 SCT control register CTRL address 0x5000 4004 bit 141 Table 123 SCT limit register LIMIT address 0x5000 4008 bit 142 Table 124 SCT halt condition register HALT address 0x5004 400C bit description 142 Table 125 SCT stop condition register STOP address 0x5000 4010 bit description 143 Table 126 SCT start condition register START address 0x5000 4014 bit description Table 127 SCT counter register COUNT address 0x5000 4040 bit description 144 Table 128 SCT state register STATE address 0x5000 4044 bit description 144 Table 129 SCT input registe
79. 16 81 MEL LL 69 6511 15 82 6 4 4 Open drain 70 6512 1 83 ASAD MOUS 70 6 5 13 PIOO 84 046 70 6544 PIOO 85 6 4 7 Programmable glitch filter 70 6 5 15 7 86 6 5 Register description 71 6 5 16 87 6 5 1 PIOU 17 register 72 6 5 17 88 6 5 2 1 0 _13 73 6 5 18 1 0_14 89 6 5 3 PIOO 12 register 74 Chapter 7 LPC81x GPIO port 7 1 How to read this chapter 90 7 6 3 GPIO port direction registers 92 72 90 7 6 4 GPIO port mask registers 92 7 6 5 GPIO port pin registers 92 7 Basic configuration 90 2 Pi 90 7 6 6 GPIO masked port registers 93 ep On E 7 6 7 GPIO port set registers 93 7 5 General 90 7 68 GPIO port clear registe
80. 186 I2C Status register STAT address 0x4005 0004 bit description continued Bit Symbol Value Description Reset Access value 14 SLVSEL Slave selected flag SL VSEL is set after an address match when 0 RO software tells the Slave function to acknowledge the address It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function when slave software decides to NACK a matched address or when there is a Stop detected on the bus SLVSEL is not cleared if software NACKs data 0 Not selected The Slave function is not currently selected Selected The Slave function is currently selected 15 SLVDESEL Slave Deselected flag This flag will cause an interrupt when set if 0 W1 enabled via INTENSET This flag can be cleared by writing a 1 to this bit 0 Not deselected The Slave function has not become deselected This does not mean that it is currently selected That information can be found in the SLVSEL flag 1 Deselected The Slave function has become deselected This is specifically caused by the SL VSEL flag changing from 1 to 0 See the description of SLVSEL for details on when that event occurs 16 MONRDY Monitor Ready This flag is cleared when the MONRXDAT register is 0 RO read 0 No data The Monitor function does not currently have data available Data waiting The Monitor function has data waiting to be read 17 MONOV Monitor Overflow flag 0 W1 0 No overrun Mo
81. 2 4 2 0 7 2 7 2 0 8 3 0 MHz 0 9 3 25 MHz OxA 3 5 MHz 0xB 3 75 MHz OxC 4 0 MHz OxD 4 2 MHz OxE 4 4 MHz OxF 4 6 MHz 31 9 Reserved 0x00 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 33 of 370 NXP Semiconductors U M1 0601 Chapter 4 LPC81x System configuration SYSCON 4 6 7 System reset status register If another reset signal for example the external RESET pin remains asserted after the POR signal is negated then its bit is set to detected Write a one to clear the reset The reset value given in Table 24 applies to the POR reset Table 24 System reset status register SYSRSTSTAT address 0x4004 8030 bit description Bit Symbol Value Description Reset value 0 POR POR reset status 0 0 No POR detected 1 POR detected Writing a one clears this reset 1 EXTRST External reset status 0 0 No reset event detected 1 Reset detected Writing a one clears this reset 2 WDT Status of the Watchdog reset 0 0 No WDT reset detected 1 WDT reset detected Writing a one clears this reset 3 BOD Status of the Brown out detect reset 0 0 No BOD reset detected 1 BOD reset detected Writing a one clears this reset 4 SYSRST Status of the software system reset 0 0 No System reset detected 1 System reset detected Writing a one clears this reset 31 5 Reserved 5 4 6 8 System PLL cloc
82. 21 5 2 for how to include the ROM driver structure 24 4 4 ISR handler Table 273 ISR handler Routine ISR handler Prototype void i2c isr handler I2C HANDLE T Input parameter 126 HANDLE T Handle to the allocated SRAM area Return None Description 12C ROM Driver interrupt service routine This function must be called from the 12 ISR when using 12C Rom Driver interrupt mode 24 4 2 12 Master Transmit Polling Table 274 12C Master Transmit Polling Routine I2C Master Transmit Polling Prototype ErrorCode_t i2c_master_transmit_poll I2C_HANDLE_T I2C Il2C RESULT Input parameter 12C HANDLE T Handle to the allocated SRAM area I2C Pointer to the I2C PARAM struct I2C RESULT Pointer to the 12C RESULT struct Return ErrorCode Description Transmits bytes in the send buffer to a slave The slave address with the R W bit 0 is expected in the first byte of the send buffer STOP condition is sent at end unless stop flag 20 When the task is completed the function returns to the line after the call UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 309 of 370 NXP Semiconductors UM10601 UM10601 24 4 3 24 4 4 24 4 5 Chapter 24 LPC81x I2C bus ROM API I2C Master Receive Polling Table 275 12C Master Receive Polling Routine Proto
83. 215 Table 187 Master function state codes MSTSTATE 218 Table 188 Slave function state codes SLVSTATE 218 Table 189 Interrupt Enable Set and read register INTENSET address 0x4005 0008 bit description 219 Table 190 Interrupt Enable Clear register INTENCLR address 0x4005 000C bit description 220 Table 191 time out register TIMEOUT address 0x4005 0010 bit description 222 Table 192 I C Clock Divider register CLKDIV address 0x4005 0014 bit description 222 Table 193 12C Interrupt Status register INTSTAT address 0x4005 0018 bit description 223 Table 194 Master Control register MSTCTL address 0x4005 0020 bit description 223 Table 195 Master Time register MSTTIME address 0x4005 0024 bit description 224 Table 196 Master Data register MSTDAT address 0x4005 0028 bit description 225 Table 197 Slave Control register SLVCTL address 0x4005 0040 bit description 226 Table 198 Slave Data register SLVDAT address 0x4005 0044 bit description 226 Table 199 Slave Address registers SLVADR 0 3 address 0x4005 0048 SLVADRO to 0x4005 0054 SLVADR3 bit description 227 Table 200 Slave address Qualifier 0 register SLVQUALO address 0x4005 0058 bit description 228 Table 201 Monitor data reg
84. 22 24 DIRECTION Direction qualifier for event generation This field only applies when the counters are operating in BIDIR mode If BIDIR 0 the SCT ignores this field Value 0x3 is reserved 0x0 Direction independent This event is triggered regardless of the count direction 0 1 Counting up This event is triggered only during up counting when BIDIR 1 0 2 Counting down This event is triggered only during down counting when BIDIR 1 31 23 Reserved 10 6 24 SCT output set registers 0 to 3 Each output n has one set register that controls how events affect each output Whether outputs are set or cleared depends on the setting of the SETCLRn field in the SCT OUTPUTDIRCTRL register Table 144 SCT output set register OUT 0 3 SET address 0x5000 4500 OUTO_SET to 0x5000 4518 OUT3_SET bit description Bit Symbol Description Reset value 5 0 SET A 1 in bit m selects event m to set output n or clear itif SETCLRn 0 0 1 or 0x2 event 0 bit 0 event 1 bit 1 event 5 bit 5 31 6 Reserved 10 6 25 SCT output clear registers 0 Each output n has one clear register that controls how events affect each output Whether outputs are set or cleared depends on the setting of the SETCLRn field in the OUTPUTDIRCTRL register UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 153 of 370 NXP Semiconductors U M1 0601 Chapter 10
85. 32 bit signature from a range of flash memory A typical usage is to verify the flashed contents against a calculated signature e g during programming The address range for generating a signature must be aligned on flash word boundaries i e 32 bit boundaries Once started signature generation completes independently While signature generation is in progress the flash memory cannot be accessed for other purposes and an attempted read will cause a wait state to be asserted until signature All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 266 of 370 NXP Semiconductors U M1 0601 UM10601 20 5 1 1 20 5 1 2 20 5 1 3 Chapter 20 LPC81x Flash controller generation is complete Code outside of the flash e g internal RAM can be executed during signature generation This can include interrupt services if the interrupt vector table is re mapped to memory other than the flash memory The code that initiates signature generation should also be placed outside of the flash memory Signature generation address and control registers These registers control automatic signature generation A signature can be generated for any part of the flash memory contents The address range to be used for generation is defined by writing the start address to the signature start address register FMSSTART and the stop address to the signatu
86. 4 address 0x5000 4200 MATCHRELO to 0x5000 4210 MATCHRELA bit description REGMODEn bit 0 150 Table 141 SCT capture control registers 0 to 4 CAPCTRL 0 4 address 0x5000 4200 CAPCTRLO to 0x5000 4210 CAPCTRLA bit description REGMODEn bit 1 151 Table 142 SCT event state mask registers 0 to 5 EV 0 5 STATE addresses 0x5000 4300 EVO STATE to 0x5000 4328 EV5_STATE bit description sss ilr dene be End 151 Table 143 SCT event control register 0 to 5 EV 0 5 CTRL address 0x5000 4304 EVO CTRL to 0x5000 432C EV5 CTRL bit description 152 Table 144 SCT output set register OUT 0 3 SET address 0x5000 4500 OUTO SET to 0x5000 4518 OUT3_SET bit description 153 Table 145 SCT output clear register OUT 0 3 CLR address 0x5000 0504 OUTO CLR to 0x5000 051C OUT3 CLR bit description 154 Table 146 Event conditions 157 Table 147 SCT configuration example 162 Table 148 Register overview MRT base address 0x4000 4000 hxc reote 167 Table 149 Time interval register INTVAL 0 3 address 0x4000 4000 INTVALO to 0x4000 4030 INTVAL3 bit description 168 Table 150 Timer register TIMER 0 3 address 0x4000 4004 TIMERO to 0x4000 4034 TIMER3 bit description 168 Table 151 Control register CTRL 0 3 address 0x4000 4008 CTRLO to 0x4000 4038 CTRL3 bit description e
87. 4 0 REGMOD L q Each bit controls one pair of match capture registers register 0 0 bit 0 register 1 bit 1 register 4 bit 4 0 registers operate as match registers 1 registers operate as capture registers 15 5 Reserved 20 16 REGMOD Each bit controls one pair of match capture registers register 0 0 bit 16 register 1 bit 17 register 4 bit 20 0 registers operate as match registers 1 registers operate as capture registers 31 21 Reserved SCT output register The SCT supports 4 outputs each of which has a corresponding bit in this register Software can write to any of the output registers when both counters are halted to control the outputs directly Writing to the OUT register is only allowed when all counters L counter H counter and unified counter are halted HALT bits are set to 1 in the CTRL register Software can read this register at any time to sense the state of the outputs Table 131 SCT output register OUTPUT address 0x5000 4050 bit description Bit Symbol Description Reset value 3 0 OUT Writing a 1 to bit n makes the corresponding output HIGH 0 makes 0 the corresponding output LOW output 0 bit 0 output 1 bit 1 output 3 bit 3 31 4 Reserved SCT bidirectional output control register This register specifies for each output the impact of the counting direction on the meaning of set and clear operations on the output see Section 10 6
88. 5 7 9 5 8 Chapter 9 LPC81x Switch matrix Table 114 Pin assign register 5 PINASSIGN5 address 0x4000 C014 bit description Bit Symbol 15 8 SPI1 MISO IO 23 16 SPI1 SSEL IO 31 24 CTIN O I Description Reset value SPI1_MISIO function assignment The value is the pin number OxFF to be assigned to this function The following pins are available PIOO 0 2 0 to PIOO 17 Ox11 SPI1_SSEL function assignment The value is the pin number to OxFF be assigned to this function The following pins are available PIOO 0 0 to PIOO 17 0x11 CTIN 0 function assignment The value is the pin number to be OxFF assigned to this function The following pins are available PIOO 0 0 to PIOO 17 0x11 Pin assign register 6 Table 115 Pin assign register 6 PINASSIGN6 address 0x4000 C018 bit description Bit Symbol 7 0 CTIN 1 I 158 CTIN 2 I 23 16 CTIN 3 31 24 CTOUT 0 O Description Reset value CTIN 1 function assignment The value is the pin number tobe OxFF assigned to this function The following pins are available PIOO 0 2 0 to PIOO 17 Ox11 CTIN 2function assignment The value is the pin number to be OxFF assigned to this function The following pins are available PIOO 0 2 0 to PIOO 17 Ox11 CTIN 3 function assignment The value is the pin number tobe OxFF assigned to this function The following pins are available PIOO 0 2 0 to PIOO 17 Ox11 CTOUT function assign
89. 5 7 7 Deep power down mode 66 5 6 1 Power control register 59 5 7 7 1 Power configuration in Deep power down m 5 6 2 General purpose registers 0 to 3 60 mode Sept Ea D 5 6 3 Deep power down control register 60 5 7 7 2 AREE Deep power down mode using n 7 Functional description 61 2 Ip 5 7 7 3 Wake up from Deep power down mode using the 5 7 1 Power 61 WAKEUP pin 66 ara power modes and WWET HOO 62 5 7 7 4 Programming Deep power down mode using the 5 73 Active mode R A 62 self wake up 67 5 7 3 1 Power configuration in Active mode 62 ps 57 4 mode 62 BHO es 5 7 4 1 Power configuration in Sleep mode 62 Chapter 6 LPC81x I O configuration IOCON 6 1 How to read this chapter 68 6 5 4 5 register 75 6 2 PR PPP 68 655 1 0_4 76 6 3 Basic 68 aes es 69 amp 58 11 79 6 4 1 configuration Sie fy aha a a iE 69 6 5 9 10 80 6 4 2 69 6 5 10 PIOO
90. Data available to be received Receiver overrun 17 4 Pin description The SPI signals are movable functions and are assigned to external pins through the switch matrix See Section 9 3 1 Connect an internal signal to a package pin to assign the SPI functions to pins on the LPC81x package UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 233 of 370 NXP Semiconductors UM10601 Table 202 SPI Pin Description Chapter 17 LPC81x SPIO 1 Function SPIO_SCK SPIO_MOSI SPIO_MISO SPIO_SSEL SPI1_SCK SPI1_MOSI SPI1_MISO SPI1_SSEL Direct Pin Description ion Serial Clock SCK is a clock signal used to synchronize the transfer of data It is driven by the master and received by the slave When the SPI interface is used the clock is programmable to be active high or active low SCK only switches during a data transfer It is driven whenever the Master bit in the CFG register equals 1 regardless of the state of the Enable bit Master Out Slave In The MOSI signal transfers serial data from the master to the slave When the SPI is a master it outputs serial data on this signal When the SPI is a slave it clocks in serial data from this signal MOSI is dri
91. End of Frame 0 22 RXIGNORE Receive Ignore 0 23 Reserved Read value is undefined only zero should be written NA 27 24 LEN Data transfer length 0 0 31 28 Reserved Read value is undefined only zero should be written NA 17 6 10 SPI Divider register The DIV register determines the clock used by the SPI in master mode For details on clocking see Section 17 7 3 Clocking and data rates Table 213 SPI Divider register DIV addresses 0x4005 8024 SPIO 0x4005 C024 SPI1 bit description Bit Symbol Description Reset Value 15 0 DIVVAL Rate divider value Specifies how the PCLK for the SPI is dividedto 0 produce the SPI clock rate in master mode DIVVAL is 1 encoded such that the value 0 results in PCLK 1 the value 1 results in PCLK 2 up to the maximum possible divide value of OxFFFF which results in PCLK 65536 31 16 Reserved Read value is undefined only zero should be written NA 17 6 11 SPI Interrupt Status register The read only INTSTAT register provides a view of those interrupt flags that are currently enabled This can simplify software handling of interrupts See Table 206 for detailed descriptions of the interrupt flags Table 214 SPI Interrupt Status register INTSTAT addresses 0x4005 8028 SPIO 0x4005 C028 SPI1 bit description Bit Symbol Description Reset value 0 RXRDY Receiver Reagy flag 0 1 TXRDY Transmitter Ready flag 1 2 RXOV Receiver Overrun interrupt flag
92. Fig 46 Power profiles pointer structure ARM CORTEX MO main clock system clock irc osc clk SYSAHBCLKDIV SYSAHBCLKCTRL 1 ROM enable wdt osc clk SYSAHBCLKCTRL n MAINCLKSEL n enable Sys pllcikout 7 CLOCK Peripherals Ik DIVIDER T SYS PLL CLKIN sys_pllclkin SYSPLLCLKSEL Fig 47 LPC81x clock configuration for power API use 23 4 API description The power profile API provides functions to configure the system clock and optimize the system setting for lowest power consumption UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 298 of 370 NXP Semiconductors U M1 0601 UM10601 23 4 1 Chapter 23 LPC81x Power profile ROM driver Table 269 Power profile API calls API call Description Reference set_pll command result Power API set pll routine Table 270 set power command result Power API set power routine Table 271 The following elements have to be defined in an application that uses the power profiles typedef struct _PWRD void set_pll unsigned int cmd unsigned int resp void set_power unsigned int cmd unsigned int resp PWRD define ROM DRIVER BASE OxlFFFlFF8UL define LPC PWRD API PWRD API T ROM T ROM DRIVER BASE pPWRD See Section 21 5 2 for how to inc
93. I2C STAT MSTSTATE LPC_I2C gt MSTDAT 0x23 lt lt 1 0 LPC_I2C gt MSTCTL I2C while LPC_I2C gt STAT amp I2C STAT MSTPE if LPC_I2C gt STAT amp I2C STAT MSTSTATE LPC I2C MSTDAT 0 send data LPC I2C MSTCTL I2C MSTCTL MSTCONTIN while LPC_I2C gt STAT amp I2C STAT MSTPE if LPC_I2C gt STAT amp 12 STAT MSTSTATE LPC_I2C gt MSTCTL I2C MSTCTL MSTSTOP while LPC_I2C gt STAT amp I2C STAT MSTPE if LPC_I2C gt STAT amp I2C STAT MSTSTATE NDING l I2C STAT MSTST IDLE address and 0 for RWn bit in order to write data STSTART send start DINC l 126 STAT MSTS UE cont DINC l I2C STA inue t I MSTS DING l I2C STA stop transaction MSTST abort IX abort ransaction I NACKX abort _IDLE abort Table 315 12C Code example Master sending nack and stop on data Master sending nack and stop on data Address 0x23 Polling mode No error checking LPC_I2C gt CFG I2C CFG MSTEN while LPC I2C STAT amp I2C if LPC I2C STAT amp I2C STAT LPC_I2C gt MSTDAT 0x23 lt lt 1 LPC_I2C gt MSTCTL 12C_MSTCTL_ while LPC I2C STAT amp I2C_S if LPC_I2C gt STAT amp I2C STAT data LPC_I2C gt MSTDAT re if data Oxdd abort LPC_I2C gt MSTCTL 12C_MSTCTL_ while LPC I2C STAT amp I2C_S if LPC I2C STAT amp I2C STAT
94. I2C for code examples that explain how to program the register interface UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 212 of 370 NXP Semiconductors U M1 0601 Chapter 16 LPC81x I2C bus interface Table 184 Register overview I2C base address 0x4005 0000 Name Access Offset Description Reset Reference value CFG R W 0x00 Configuration for shared functions 0 Table 185 STAT R W 0x04 Status register for Master Slave and Monitor functions 0x00080 Table 186 1 INTENSET R W 0x08 Interrupt Enable Set and read register 0 Table 189 W 0x0C Interrupt Enable Clear register NA Table 190 TIMEOUT R W 0x10 Time out value register OxFFFF Table 191 CLKDIV R W 0x14 Clock pre divider for the entire I2C block This determines what 0 Table 192 time increments are used for the MSTTIME and SLVTIME registers INTSTAT R 0x18 Interrupt Status register for Master Slave and Monitor 0 Table 193 functions MSTCTL R W 0x20 Master control register 0 Table 194 MSTTIME R W 0x24 Master timing configuration 0x77 Table 195 MSTDAT R W 0x28 Combined Master receiver and transmitter data register NA Table 196 SLVCTL R W 0x40 Slave control register 0 Table 197 SLVDAT R W 0x44 Combined Slave receiver and transmitter data register NA Table 198 SLVADRO R W 0x48 Slave address 0 0x01 Table 199 SLVADR1 R W 0x4C Slave add
95. IN5 IN7ev with IN6fe sticky falling edge on input 6 IN7ev non sticky event rising or falling edge on input 7 Each individual term in the expression shown above is controlled by one bit slice To specify this expression program the pattern match bit slice source and configuration register fields as follows e PMSRC register Table 104 Since bit slice 5 will be used to detect a sticky event on input 6 you can write a 1 to the SRC5 bits to clear any pre existing edge detects on bit slice 5 SRCO 001 select input 1 for bit slice 0 SRC1 001 select input 1 for bit slice 1 SRC2 010 select input 2 for bit slice 2 SRC3 010 select input 2 for bit slice SRC4 011 select input 3 for bit slice 4 SRC5 110 select input 6 for bit slice 5 SRC6 101 select input 5 for bit slice 6 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 117 of 370 NXP Semiconductors UM10601 Chapter 8 LPC81x Pin interrupts pattern match engine SRC7 111 select input 7 for bit slice 7 PMCFG register Table 105 PROD ENDPTSO 1 PROD_ENDPTS02 1 PROD_ENDPTS5 1 All other slices are not product term endpoints and their PROD_ENDPTS bits are 0 Slice 7 is always a product term endpoint and does not have a register bit associated with it 0100101 bit slices 0 2 5 and 7 ar
96. IRC to provide a clock signal that can be shut down cleanly a In Deep sleep mode the peripherals receive no internal clocks The flash is in stand by mode The SRAM memory and all peripheral registers as well as the processor maintain their internal states The WWDT WKT and BOD can remain active to wake up the system on an interrupt b In Power down mode the peripherals receive no internal clocks The internal SRAM memory and all peripheral registers as well as the processor maintain their internal states The flash memory is powered down The WWDT WKT and BOD can remain active to wake up the system on an interrupt 3 Deep power down mode For maximal power savings the entire system is shut down except for the general purpose registers in the PMU and the self wake up timer Only the general purpose registers in the PMU maintain their internal states The part can wake up on a pulse on the WAKEUP pin or when the self wake up timer times out On wake up the part reboots Remark The LPC81x is in active mode when it is fully powered and operational after booting Wake up process If the part receives a wake up signal in any of the reduced power modes it wakes up to the active mode See these links for related registers and wake up instructions To configure the system after wake up Table 48 Wake up configuration register PDAWAKECFG address 0 4004 8234 bit description To use external interrupts for wake up Tabl
97. L counting down Set and clear are reversed when counter L or the unified counter is counting down 0 2 counting down Set and clear are reversed when counter is counting down Do not use if UNIFY 1 7 6 SETCLR3 Set clear operation on output 3 Value 0x3 is reserved Do not program this value 0 0x0 Any Set and clear do not depend on any counter 0 1 L counting down Set and clear are reversed when counter L or the unified counter is counting down 0 2 counting down Set and clear are reversed when counter is counting down Do not use if UNIFY 1 31 8 Reserved 10 6 13 SCT conflict resolution register The registers OUTn SETn Section 10 6 24 and OUTnCLRn Section 10 6 25 allow both setting and clearing to be indicated for an output in the same clock cycle even for the same event This SCT conflict resolution register resolves this conflict To enable an event to toggle an output set the OnRES value to 0x3 in this register and set the event bits in both the Set and Clear registers Table 133 SCT conflict resolution register RES address 0x5000 4058 bit description Bit Symbol Value Description Reset value 1 0 OORES Effect of simultaneous set and clear on output 0 0 0x0 No change 0 1 Set output or clear based on the SETCLRO field 0 2 Clear output or set based the SETCLRO field 0x3 Toggle output 3 2 O1RES Effect of simultaneous set and clear on output 1 0 0x0 No change 0 1 Set output or clear based on
98. LPC81x SCTimer PWM SCT Table 145 SCT output clear register OUT 0 3 _CLR address 0x5000 0504 OUTO_CLR to 0x5000 051C OUT3_CLR bit description Bit Symbol Description Reset value 5 0 CLR A 1 in bit m selects event m to clear output or set itif SETCLRn 0 Ox1 or 0x2 event 0 bit 0 event 1 bit 1 event 5 bit 5 31 6 Reserved 10 7 Functional description 10 7 1 Match logic Counter H gt Match Reload 9 Match RegiH iH UNIFY Match Match Reload 9 m MatchiL RegiL iL Counter L gt Fig 17 Match logic 10 7 2 Capture logic Counter H capture capture control select regi H iH Events UNIFY SCT clock e capture Sus Ed select regiL Counter L l p Fig 18 Capture logic UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 154 of 370 NXP Semiconductors UM10601 10 7 3 Event selection State variables allow control of the SCT across more than one cycle of the counter Counter matches input output edges and state values are combined into a set of general purpose events that can switch outputs request interrupts and c
99. Only one register is used for operation as one 32 bit counter timer UNIFY 0 Access the L and registers by a 32 bit read or write operation or can be read or written to individually for operation as two 16 bit counter timers Typically the UNIFY bit is configured by writing to the CONFIG register before any other registers are accessed 2 The REGMODEn bits in the REGMODE register determine whether each set of Match Capture registers uses the match or capture functionality REGMODEn 1 Registers operate as match and reload registers REGMODEn 0 Registers operate as capture and capture control registers UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 136 of 370 NXP Semiconductors UM10601 Chapter 10 LPC81x SCTimer PWM SCT Table 120 Register overview State Configurable Timer base address 0x5000 4000 Name Access Address Description Reset value Reference offset CONFIG R W 0x000 SCT configuration register 0x0000 7 00 Table 121 CTRL R W 0x004 SCT control register 0x0004 0004 Table 122 CTRL_L R W 0x004 SCT control register low counter 16 bit Table 122 CTRL_H R W 0x006 SCT control register high counter 16 bit Table 122 LIMIT R W 0x008 SCT limit register 0x0000 0000 Table 123 LIMIT_L R W 0x008 SCT limit register low counter 16 bit Table 123 LIMIT_H R W 0x00A SCT limit registe
100. PIOO 17 0x11 Pin assign register 4 Table 113 Pin assign register 4 PINASSIGN4 address 0x4000 C010 bit description Bit Symbol Description Reset value 7 0 SPIO_MOSI_IO MOSI function assignment The value is the pin numberto OXFF be assigned to this function The following pins are available PIOO 0 0 to PIOO 17 0x11 15 8 MISO IO SPIO_MISIO function assignment The value is the pin number OxFF to be assigned to this function The following pins are available PIOO 0 2 0 to PIOO 17 Ox11 23 16 SPIO SSEL IO SPIO SSEL function assignment The value is the pin numberto OxFF be assigned to this function The following pins are available PIOO 0 0 to PIOO 17 0x11 31 24 SPM SCK IO SPI SCK function assignment The value is the pin number to OxFF be assigned to this function The following pins are available PIOO 0 0 to PIOO 17 0x11 Pin assign register 5 Table 114 Pin assign register 5 PINASSIGNS5 address 0x4000 C014 bit description Bit Symbol Description Reset value 7 0 SPI1 MOSI IO SPI1_MOSI function assignment The value is the pin number to OxFF be assigned to this function The following pins are available PIOO 0 0 to PIOO 17 0x11 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 129 of 370 NXP Semiconductors UM10601 UM10601 9
101. SP Form address from SP Form address from PC Subtract Lo and Lo 3 bit immediate 8 bit immediate With carry Immediate from SP Negate Multiply Compare Multiply Compare Negative Immediate UM10601 Assembler MOVS Rd lt imm gt MOVS Rd Rm MOV Rd Rm MOV PC Rm ADDS Rd Rn imm ADDS Rd Rn Rm ADD Rd Rd Rm ADD PC PC Rm ADDS Rd Rd lt imm gt ADCS Rd Rd Rm ADD SP SP lt imm gt ADD Rd SP lt imm gt ADR Rd label SUBS Rd Rn Rm SUBS Rd Rn lt imm gt SUBS Rd Rd lt imm gt SBCS Rd Rd Rm SUB SP SP lt imm gt RSBS Rd Rn 0 MULS Rd Rm Rd CMP Rn Rm CMN Rn Rm CMP Rn lt imm gt All information provided in this document is subject to legal disclaimers Cycles 1 1 1 2 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 337 of 370 NXP Semiconductors UM10601 Table 306 Cortex MO instruction summary Chapter 28 LPC81x Appendix Operation Logical Shift Rotate Load Store Push Pop UM10601 Description AND Exclusive OR OR Bit clear Move NOT AND test Logical shift left by immediate Logical shift left by register Logical shift right by immediate Logical shift right by register Arithmetic shift right Arithmetic shift right by register Rotate right by register Word immediate offset Halfword immediate offse
102. SPI TXDATCTL FLEN 7 SPI TXDATCTL EOT SPI TXDATCTL SSEL N 0xe while LPC_SPI gt STAT amp SPI STAT RXRDY data LPC_SPI gt RXDAT if data Oxdd abort while LPC_SPI gt STAT amp SPI STAT MSTIDLE Transmit and receive a byte to from slave 0 Table 328 SPI Code example Transmit and receive a byte to from slave 0 LPC_SPI gt CFG SPI CFG MASTER SPI CFG ENABLE while LPC_SPI gt STAT amp SPI STAT TXRDY LPC_SPI gt TXDATCTL SPI TXDATCTL FLEN 7 SPI TXDATCTL EOT SPI TXDATCTL SSEL 0 0xdd while LPC_SPI gt STAT amp SPI STAT RXRDY data LPC_SPI gt RXDAT if data Oxdd abort while LPC_SPI gt STAT amp SPI STAT MSTIDLE All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 349 of 370 NXP Semiconductors UM1 0601 UM10601 29 3 6 29 3 7 29 3 8 29 3 9 Chapter 29 LPC81x Code examples Transmit and receive 24 bits to from slave 0 Table 329 SPI Code example Transmit and receive 24 bits to from slave 0 LPC SPI CFG SPI CFG MASTER SPI CFG ENABLE while LPC_SPI gt STAT amp SPI STAT TXRDY LPC_SPI gt TXDATCTL SPI TXDATCTL FLEN 15 SPI TXDATCTL SSEL N 0xe Oxdddd while LPC_SPI gt STAT amp SPI STAT RXRDY data LPC_SPI gt RXDAT if data Oxdddd abort while LPC_
103. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5 0x2 Input 2 Selects the pin selected in the PINTSEL2 register as the source to bit slice 5 0x3 Input Selects the pin selected in the PINTSELS register as the source to bit slice 5 0 4 Input 4 Selects the pin selected in the PINTSEL4 register as the source to bit slice 5 0 5 Input 5 Selects the pin selected in the PINTSEL5 register as the source to bit slice 5 0x6 Input 6 Selects the pin selected in the PINTSEL6 register as the source to bit slice 5 0 7 Input 7 Selects the pin selected in the PINTSEL7 register as the source to bit slice 5 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 110 of 370 NXP Semiconductors UM10601 Chapter 8 LPC81x Pin interrupts pattern match engine Table 104 Pattern match bit slice source register PMSRC address 0xA000 402C bit description Bit Symbol Value 28 26 SRC6 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 31 29 SRC7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Description Selects the input source for bit slice 6 Input 0 Selects the pin selected in the PINTSELO register as the source to bit slice 6 Input 1 Selects the pin selected in the PINTSEL1 register as the source to bit slice 6 Input 2 Selects the pin selected in the PINTSEL2 register as the source
104. Status codes 294 22 6 Functional description 295 22 6 1 UART Communication protocol 295 22 6 1 1 UART ISP command format 295 22 6 1 2 22 6 1 3 22 6 2 22 6 2 1 22 6 2 2 22 6 2 3 22 6 2 4 22 6 3 22 6 3 1 22 6 3 2 Chapter 23 LPC81x Power profile ROM driver Chapter 30 Supplementary information UART ISP response format UART ISP data format Memory and interrupt use for ISP and IAP 295 Interrupts during UART ISP 295 Interrupts during IAP 296 RAM used by ISP command handler 296 RAM used by IAP command handler 296 Debugging 296 Comparing flash images 296 Serial Wire Debug SWD flash programming interface icis 23 1 How to read this chapter 297 23 5 1 1 Invalid frequency device maximum clock rate 29 2 Features mE 297 exceeded 303 23 3 zu sed 2 1 can NUS CHO D 298 2354 3 Exact solution cannot be found PLL 304 2341 setpl ae 299 235 14 System clock less than or equal to the expected 23 41 1 Param0 system PLL input frequency and WANS RM 304 Param1 expected system 300 2354 5 System clock greater than
105. TXDAT Table 211 SPI Transmitter Data Register TXDAT addresses 0x4005 801C SPIO 0x4005 C01C SPI1 bit description Bit Symbol Description Reset value 15 0 DATA Transmit Data This field provides from 4 to 16 bits of data to be 0 transmitted 31 16 Reserved Only zero should be written NA 17 6 9 SPI Transmitter Control register The TXCTL register provides a way to separately access control information for the SPI These bits are another view of the same named bits in the TXDATCTL register see Section 17 6 7 Changing bits in TXCTL has no effect unless data is later written to the TXDAT register Data written to TXDATCTL overwrites the TXCTL register When control information needs to be changed during transmission the TXDATCTL register should be used see Section 17 6 7 instead of TXDAT Control information can then be written along with data UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 244 of 370 NXP Semiconductors U M1 0601 Chapter 17 LPC81x SPIO 1 Table 212 SPI Transmitter Control register TXCTL addresses 0x4005 8020 SPIO 0x4005 C020 SPI1 bit description Bit Symbol Description Reset value 15 0 Reserved Read value is undefined only zero should be written 16 TXSSEL N Transmit Slave Select 0x0 19 17 Reserved 0x0 20 EOT End of Transfer 0 21 EOF
106. Table 189 Interrupt Enable Set and read register INTENSET address 0x4005 0008 bit description Bit 3 1 10 9 Symbol MSTPENDINGEN MSTARBLOSSEN MSTSTSTPERREN SLVPENDINGEN SLVNOTSTREN SLVDESELEN MONRDYEN MONOVEN All information provided in this document is subject to legal disclaimers Value Description Master Pending interrupt Enable The MstPending interrupt is disabled The MstPending interrupt is enabled Reserved Read value is undefined only zero should be written Master Arbitration Loss interrupt Enable The MstArbLoss interrupt is disabled The MstArbLoss interrupt is enabled Reserved Read value is undefined only zero should be written Master Start Stop Error interrupt Enable The MstStStpErr interrupt is disabled The MstStStpErr interrupt is enabled Reserved Read value is undefined only zero should be written Slave Pending interrupt Enable The SlvPending interrupt is disabled The SlvPending interrupt is enabled Reserved Read value is undefined only zero should be written Slave Not Stretching interrupt Enable The SlvNotStr interrupt is disabled The SlvNotStr interrupt is enabled Reserved Read value is undefined only zero should be written Slave Deselect interrupt Enable The SlvDeSel interrupt is disabled The SlvDeSel interrupt is enabled Monitor data Ready interrupt Enable The MonRqy interrupt is disabled The MonRgy interrupt is enabled Mo
107. Table 219 Comparator control register This register enables the comparator configures the interrupts and controls the input multiplexers on both sides of the comparator All bits not shown in Table 218 are reserved and should be written as 0 Table 218 Comparator control register CTRL address 0x4002 4000 bit description Bit Symbol Value Description Reset value 2 0 Reserved Write as 0 0 4 3 EDGESEL This field controls which edges on the comparator 0 output set the COMPEDGE bit bit 23 below 0 0 Falling edges 0 1 Rising edges 0 2 Both edges 0x3 Both edges Reserved Write as 0 6 COMPSA Comparator output control 0 Comparator output is used directly 1 Comparator output is synchronized to the bus clock for output to other modules 7 Reserved Write as 0 0 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 257 of 370 NXP Semiconductors UM10601 Chapter 18 LPC81x Analog comparator Table 218 Comparator control register CTRL address 0x4002 4000 bit description Bit Symbol Value Description Reset value 10 8 COMP VP SEL Selects positive voltage input 0 0x0 Voltage ladder output 0 1 ACMP 11 0x2 ACMP 12 0x3 Reserved 0x4 Reserved 0x5 Reserved 0x6 Internal reference voltage bandgap 0 7 Reserved 13 11 COMP VM SEL Selects negative voltage input 0 0x0 Voltage ladder outpu
108. The data are read from this address for CRC checksum calculation This address must be on a word boundary Number of Bytes Number of bytes to be calculated for the CRC checksum must be a multiple of 4 Return Code CMD SUCCESS followed by data in plain binary format ADDR ERROR address not on word boundary ADDR NOT MAPPED COUNT ERROR byte count is not a multiple of 4 PARAM ERROR CODE READ PROTECTION ENABLED Description This command is used to read the CRC checksum of a block of RAM or flash memory This command is blocked when code read protection is enabled Example S 268436736 4 lt CR gt lt LF gt reads the CRC checksum for 4 bytes of data from address 0x1000 0500 If checksum value is OXCBF43926 then the host will receive 8421780262 lt CR gt lt LF gt 22 5 1 16 UART ISP Return Codes Table 255 UART ISP Return Codes Summary Return Mnemonic Description Code 0 CMD SUCCESS Command is executed successfully Sent by ISP handler only when command given by the host has been completely and successfully executed 1 INVALID COMMAND Invalid command 2 SRC ADDR ERROR Source address is not on word boundary 3 DST ADDR ERROR Destination address is not on a correct boundary 4 ADDR NOT MAPPED Source address is not mapped in the memory map Count value is taken in to consideration where applicable 5 DST ADDR NOT MAPPED Destination address is not mapped in the memory map Count value is taken in to conside
109. This bit is only cleared when the PMCFG or the PMSRC registers are written to 0 2 Sticky falling edge Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0x3 Sticky rising or falling edge Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0 4 High level Match for this bit slice occurs when there is a high level on the input specified for this bit slice in the PMSRC register 0 5 Low level Match occurs when there is a low level on the specified input Ox6 Constant 0 This bit slice never contributes to a match should be used to disable any unused bit slices 0 7 Event Non sticky rising or falling edge Match occurs on an event i e when either a rising or falling edge is first detected on the specified input this is a non sticky version of value 0x3 This bit is cleared after one clock cycle 31 29 CFG7 Specifies the match contribution condition for bit slice 7 0b000 0x0 Constant HIGH This bit slice always contributes to a product term match 0 1 Sticky rising edge Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cl
110. Value Description Reset value 19 ACMP Enables clock to analog comparator 0 0 Disable 1 Enable 31 220 Reserved 4 6 14 USART clock divider register This register configures the clock for the fractional baud rate generator and all USARTSs The UART clock can be disabled by setting the DIV field to zero this is the default setting Table 31 USART clock divider register UARTCLKDIV address 0x4004 8094 bit description Bit Symbol Description Reset value 7 0 DIV USART fractional baud rate generator clock divider values 0 0 Clock disabled 1 Divide by 1 to 255 Divide by 255 31 8 Reserved 4 6 15 CLKOUT clock source select register This register selects the signal visible on the CLKOUT pin Any oscillator or the main clock can be selected Bit 0 of the CLKOUTUEN register see Section 4 6 16 must be toggled from 0 to 1 for the update to take effect Table 32 CLKOUT clock source select register CLKOUTSEL address 0x4004 80E0 bit description Bit Symbol Value Description Reset value 1 0 SEL CLKOUT clock source 0 0x0 IRC oscillator 0 1 Crystal oscillator SYSOSC 0x2 Watchdog oscillator 0x3 Main clock 312 Reserved 0 4 6 16 CLKOUT clock source update enable register This register updates the clock source of the CLKOUT pin with the new clock after the CLKOUTSEL register has been written to In order for the update to take effect at the input of the CLKOUT pin first write a zero t
111. W 0x000 Power control register 0x0 Table 56 R W 0x004 General purpose register 0 0x0 Table 57 R W 0x008 General purpose register 1 0x0 Table 57 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 58 of 370 NXP Semiconductors U M1 0601 UM10601 5 6 1 Chapter 5 LPC81x Reduced power modes and Power Management Table 55 Register overview PMU base address 0x4002 0000 continued Name Access Address Description Reset Reference offset value GPREG2 R W 0x00C General purpose register 2 0x0 Table 57 GPREG3 R W 0x010 General purpose register 3 0x0 Table 57 DPDCTRL RAN 0x014 Deep power down control 0x0 Table 58 register Also includes bits for general purpose storage Power control register The power control register selects whether one of the ARM Cortex MO controlled power down modes Sleep mode or Deep sleep Power down mode or the Deep power down mode is entered and provides the flags for Sleep or Deep sleep Power down modes and Deep power down modes respectively Table 56 Power control register PCON address 0x4002 0000 bit description Bit Symbol Value Description Reset value 2 0 PM Power mode 000 0x0 Default The part is in active or sleep mode 0 1 Deep sleep mode ARM WFI will enter Deep sleep mode 0 2 Power down mode ARM WFI will enter Power down mode 0x3 Deep power down mode ARM WFI
112. WRITE_OPERATION BUSY CMD_LOCKED PARAM_ERROR CODE_READ_PROTECTION_ENABLED This command is used to program the flash memory The Prepare Sector s for Write Operation command should precede this command The affected sectors are automatically protected again once the copy command is successfully executed The boot block cannot be written by this command This command is blocked when code read protection is enabled C 0 268437504 512 lt CR gt lt LF gt copies 512 bytes from the RAM address 0x1000 0800 to the flash address 0 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 283 of 370 NXP Semiconductors U M1 0601 Chapter 22 LPC81x Flash ISP and IAP programming 22 5 1 8 Go lt address gt lt mode gt Table 246 UART ISP Go command Command G Input Address Flash or RAM address from which the code execution is to be started This address should be on a word boundary Mode T Execute program in Thumb Mode Return Code CMD_SUCCESS ADDR_ERROR ADDR_NOT_MAPPED CMD_LOCKED PARAM_ERROR CODE_READ_PROTECTION_ENABLED Description This command is used to execute a program residing in RAM or flash memory It may not be possible to return to the ISP command handler once this command is successfully executed This command is blocked when code read protection is enabled The command must be used w
113. a tightly controlled environment like a software state machine consider using the NOT register This can require less write operations than SET and CLR To read the state of one pin read a Byte Pin or Word Pin register To make a decision based on multiple pins read and mask a PORT register All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 95 of 370 UM10601 Chapter 8 LPC81x Pin interrupts pattern match engine Rev 1 6 2 April 2014 User manual 8 1 How to read this chapter The pin interrupt generator and the pattern match engine are available on all LPC81x parts 8 2 Features Pin interrupts Up to eight pins can be selected from all GPIO pins as edge or level sensitive interrupt requests Each request creates a separate interrupt in the NVIC Edge sensitive interrupt pins can interrupt on rising or falling edges or both Level sensitive interrupt pins can be HIGH or LOW active e Pattern match engine Upto eight pins can be selected from all GPIO pins to contribute to a boolean expression The boolean expression consists of specified levels and or transitions on various combinations of these pins Each bit slice minterm product term comprising the specified boolean expression can generate its own dedicated interrupt request Any occurrence of a pattern match can be pro
114. amp parity generation amp detection Receiver Receiver Receiver Buffer Shift Register Register USARTO block USART1 block USART2 block U_PCLK UARTCLKDIV 1 MULT DIV Fig 30 USART block diagram UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 192 of 370 NXP Semiconductors UM10601 Chapter 15 LPC81x USARTO 1 2 15 6 Register description The reset value reflects the data stored in used bits only It does not include the content of reserved bits See Section 29 4 Code examples UART for code examples that explain how to program the register interface Table 172 Register overview USART base address 0x4006 4000 USARTO 0x4006 8000 USART1 0 4006 C000 USART2 Name Access Offset Description Reset Reference value CFG R W 0x000 USART Configuration register Basic USART configuration 0 Table 173 settings that typically are not changed during operation CTL R W 0x004 USART Control register USART control settings that are more 0 Table 174 likely to change during operation STAT R W 0x008 USART Status register The complete status value can be read 0x000E Table 175 here Writing 1s clears some bits in the register Some bits can be cleared by writing a 1 to them INTENSET R W OxOOC Interrupt Enable read and Set register Contains an individual 0 Table 176
115. and Control register 243 17 2 232 17 68 Transmitter Data Register 244 17 3 232 iu i Control register 244 17 3 1 Configure the SPls for wake up 233 9 19 NIGER TER RUE ae 17 3 1 1 Wake up from Sleep mode 233 17 6 11 Interrupt Status register 245 17 3 1 2 Wake up from Deep sleep or Power down 17 7 Functional description 247 233 17 7 1 Operating modes clock and phase selection 247 17 4 233 is ie MM MCN ME NS 7 2 re_delay Post_delay 17 General description 235 17722 Frame 249 17 6 X Register description 235 17723 Transfer 250 17 6 1 2a Configuration register 237 17 73 Clocking and data 251 17 6 2 PI Delay register 238 17 73 41 Datarate calculations 251 17 6 3 SPI Status 239 1774 5 251 17 6 4 Interrupt Enable read and Set register 240 1775 Data lengths greater than 16 bits 251 17 6 5 SPI Interrupt Enable Clear register 242 1776
116. and no events can occur Configure the SCT without using states The SCT can be used as standard counter timer with external capture inputs and match outputs without using the state logic To operate the SCT without states configure the SCT as follows Write zero to the STATE register zero is the default Write zero to the STATELD and STATEV fields in the EVCTRL registers for each event Write Ox1 to the EVn STATE register of each event Writing Ox1 enables the event In effect the event is allowed to occur in a single state which never changes while the counter is running SCT PWM Example Figure 22 shows a simple application of the SCT using two sets of match events EVO 1 and EV3 4 to set clear SCT output 0 The timer is automatically reset whenever it reaches the MATO match value In the initial state 0 match event EVO sets output 0 to HIGH and match event EV1 clears output 0 The SCT input 0 is monitored If inputO is found LOW by the next time the timer is reset EV2 the state is changed to state 1 and EV3 4 are enabled which create the same output but triggered by different match values If input 0 is found HIGH by the next time the timer is reset the associated event EV5 causes the state to change back to state Owhere the events EVO and EV1 are enabled The example uses the following SCT configuration e 1 input 1 output 5 match registers 6 events and match 0 used with autolimit function e 2 state
117. and the capability of powering down the device without affecting the bus See Section 9 3 1 Connect an internal signal to a package pin to assign the I2C pins to any pin on the LPC81x package Table 183 I2C bus pin description Function Type Pin Description SWM register Reference l2CO SCL I O any use pin PIOO 10 or PIOO 11 for I2CO serial clock PINASSIGN8 Table 117 compatibility with the full IC bus specification 1260 SDA any use pin PIOO 10 or PIOO 11 for I2CO serial data PINASSIGN7 Table 116 compatibility with the full IC bus specification 16 5 General description The architecture of the I2C bus interface is shown in Figure 33 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 210 of 370 NXP Semiconductors U M1 0601 Chapter 16 LPC81x I2C bus interface Monitor function Timing generation function function Bq 12C0_SDA xX 12C0_SCL Fig 33 12C block diagram UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 211 of 370 NXP Semiconductors UM10601 Chapter 16 LPC81x I2C bus interface 16 6 Register description The register functions can be grouped as follows Common registers Table 185 I2C Configuration register
118. any any 7 77 any Description SCT input 0 SCT input 1 SCT input 2 SCT input 3 SCT output 0 SCT output 1 SCT output 2 SCT output 3 SWM register PINASSIGN5 PINASSIGN6 PINASSIGN6 PINASSIGN6 PINASSIGN6 PINASSIGN7 PINASSIGN7 PINASSIGN7 Reference Table 114 Table 115 Table 115 Table 115 Table 115 Table 116 Table 116 Table 116 10 5 General description The State Configurable Timer SCT allows a wide variety of timing counting output modulation and input capture operations UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 134 of 370 NXP Semiconductors U M1 0601 Chapter 10 LPC81x SCTimer PWM SCT The most basic user programmable option is whether a SCT operates as two 16 bit counters or a unified 32 bit counter In the two counter case in addition to the counter value the following operational elements are independent for each half e State variable Limit halt stop and start conditions Values of Match Capture registers plus reload or capture control values In the two counter case the following operational elements are global to the SCT Clock selection Inputs Events Outputs Interrupts Events outputs and interrupts can use match conditions from either counter Remark In this chapter the term bus error indicates an SCT response th
119. assigned to pin PIOO 11 and if I C Fast mode Plus is selected in the I O configuration register UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 125 of 370 NXP Semiconductors U M1 0601 Chapter 9 LPC81x Switch matrix Table 107 Movable functions assign to pins PIOO 0 to PIOO 17 through switch matrix Function name Description SWM Pin assign Reference register l2C0 SCL I2C bus clock input output open drain if assigned to PINASSIGN8 Table 117 PIOO 10 High current sink only if assigned to 10 and if lC Fast mode Plus is selected in the I O configuration register ACMP O O Analog comparator output PINASSIGN8 Table 117 CLKOUT Clock output PINASSIGN8 Table 117 GPIO_INT_BMAT O Output of the pattern match engine PINASSIGN8 Table 117 9 4 2 Switch matrix register interface The switch matrix consists of two blocks of pin assignment registers PINASSIGN and PINENABLE Every function has an assigned field 1 bit or 8 bit wide within this bank of registers where you can program the external pin identified by its GPIO function you want the function to connect to GPIOs range from PIOO 0 to PIOO 17 and for assignment through the pin assignment registers are numbered 0 to 17 There are two types of functions which must be assigned to port pins in different ways 1 Movable functio
120. be enabled based on the count direction Match events can be held until another qualifying event occurs Selected events can limit halt start or stop a counter Supports 4inputs 4outputs 5 match capture registers 6 events 2states 10 3 Basic configuration UM10601 Configure the SCTimer PWM as follows Use the SYSAHBCLKCTRL register Table 30 to enable the clock to the SCT register interface and peripheral clock The LPC81x system clock is the input clock to the SCT clock processing and is the source of the SCT clock Clear the SCT peripheral reset using the PRESETCTRL register Table 19 The SCT combined interrupt is connected to slot 8 in the NVIC Use the switch matrix to connect the SCT inputs and outputs to pins see Section 10 4 and internally see Section 10 5 10 3 1 Use the SCTimer PWM as a simple timer To configure the SCT as a simple timer with match or capture functionality follow these steps All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 133 of 370 NXP Semiconductors UM10601 Chapter 10 LPC81x SCTimer PWM SCT 1 Set up the SCT as one 32 bit timer or one or two 16 bit timers See Table 121 2 Preload the 32 bit timer or the 16 bit timers with a count value See Table 127 3 If you need to create a match event when the timer reaches a match valu
121. be useful while setting up an SPI memory Control information can optionally be written along with data This allows very versatile operation including frames of any length One Slave Select input output with selectable polarity and flexible usage Remark Texas Instruments SSI and Microwire modes are not supported 17 3 Basic configuration Configure SPIO 1 using the following registers n the SYSAHBCLKCTRL register set bit 11 and 12 Table 30 to enable the clock to the register interface Clear the SPIO 1 peripheral resets using the PRESETCTRL register Table 19 Enable disable the SPIO 1 interrupts in interrupt slots 40 and 1 in the NVIC Configure the SPIO 1 pin functions through the switch matrix See Section 17 4 The peripheral clock for both SPls is the system clock see Figure 3 LPC81x clock generation SPI0 1 SYSCON SPIO 1 PCLK system clock Clock divider SYSAHBCLKCTRL 11 12 SPIO 1 clock enable Fig 34 SPI clocking UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 232 of 370 NXP Semiconductors U M1 0601 Chapter 17 LPC81x SPIO 1 17 3 1 Configure the SPIs for wake up In sleep mode any signal that triggers an SPI interrupt can wake up the part provided that the interrupt is enabled in the INTENSET register and the NVIC As long as the SPI cloc
122. boot loader code is executed every time the part is powered on or reset The boot loader can execute the ISP command handler or the user application code A LOW level after reset at the ISP entry pin is considered as an external hardware request to start the ISP command handler via USART For details on the boot process see Section 21 6 2 Boot process Remark SRAM location 0x1000 0000 to 0x1000 0050 is not used by the bootloader and the memory content in this area is retained during reset SRAM memory is not retained when the part powers down or enters Deep power down mode Assuming that power supply pins are at their nominal levels when the rising edge on RESET pin is generated it may take up to 3 ms before the ISP entry pin is sampled and the decision whether to continue with user code or ISP handler is made The boot loader performs the following steps see Figure 44 1 If the watchdog overflow flag is set the boot loader checks whether a valid user code is present If the watchdog overflow flag is not set the ISP entry pin is checked 2 If there is no request for the ISP command handler execution ISP entry pin is sampled HIGH after reset a search is made for a valid user program All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 271 of 370 NXP Semiconductors UM10601 UM10601 21 5 2 Chapter 21 LPC8
123. by software Table 169 System Timer Current value register SYST CVR 0xE000 E018 bit description Bit Symbol Description Reset value 23 0 CURRENT Reading this register returns the current value of the System Tick 0 counter Writing any value clears the System Tick counter and the COUNTFLAG bit in STCTRL 31 24 Reserved user software should not write ones to reserved bits The NA value read from a reserved bit is not defined All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 185 of 370 NXP Semiconductors U M1 0601 Chapter 14 LPC81x ARM Cortex SysTick Timer SysTick 14 6 4 System Timer Calibration value register The value of the SYST CALIB register is driven by the value of the SYSTCKCAL register in the system configuration block SYSCON see Table 41 Table 170 System Timer Calibration value register SYST CALIB 0xE000 E01C bit description Bit Symbol Value Description Reset value 23 0 TENMS See Ref 5 0 4 29 24 Reserved user software should write ones to NA reserved bits The value read from a reserved bit is not defined 30 SKEW See Ref 5 0 31 NOREF See Ref 5 0 14 7 Functional description UM10601 14 7 1 The SysTick timer is a 24 bit timer that counts down to zero and generates an interrupt The intent is to provide a fixed 10 millisecond time interval between inte
124. byte of the receive buffer STOP condition is sent at end unless stop flag 0 When the task is completed the function returns to the line after the call I2C Master Transmit Interrupt Table 277 12C Master Transmit Interrupt Routine Prototype Input parameter Return Description I2C Master Transmit Interrupt ErrorCode ti2c master transmit intrl2C HANDLE T I2C I2C RESULT I2C HANDLE T Handle to the allocated SRAM area I2C Pointer to the I2C PARAM struct I2C RESULT Pointer to the 12C RESULT struct ErrorCode Transmits bytes in the send buffer to a slave The slave address with the R W bit 0 is expected in the first byte of the send buffer STOP condition is sent at end unless stop flag 20 Program control will be returned immediately and task will be completed on an interrupt driven basis When task is completed the callback function is called All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 310 of 370 NXP Semiconductors UM10601 UM10601 Chapter 24 LPC81x I2C bus ROM API 24 4 6 12C Master Receive Interrupt 24 4 7 24 4 8 Table 278 12C Master Receive Interrupt Routine Prototype Input parameter Return Description I2C Master Receive Interrupt ErrorCode_t i2c_master_receive_intr I2C_HANDLE_T 126 12C_RESULT
125. count down sequence A read reflects the current value of the timer UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 182 of 370 UM10601 Chapter 14 LPC81x ARM Cortex SysTick Timer SysTick Rev 1 6 2 April 2014 User manual 14 1 How to read this chapter The SysTick timer is available on all LPC81x parts 14 2 Features Simple 24 bit timer Uses dedicated exception vector Clocked internally by the system clock or the system clock 2 14 3 Basic configuration The system tick timer is configured using the following registers 1 The system tick timer is enabled through the SysTick control register Table 167 The System tick timer clock is fixed to half the frequency of the system clock 2 Enable the clock source for the SysTick timer in the SYST CSR register Table 167 14 4 Pin description TheSysTick has no configurable pins 14 5 General description The block diagram of the SysTick timer is shown below in the Figure 28 SYST CALIB SYST RVR load data SYST CVR private 24 bit down counter peripheral system clock us clock reference clock under count 7 system clock 2 load flow enable SYST CSR bit CLKSOURCE SYST CSR COUNTFLAG System Tick interrupt Fig 28 System tick timer block diagram UM10601 All informat
126. description The result is an SCL clock of 375 kHz Configure the LPC81x I2C as master Set the MSTEN bit to 1 in the CFG register See Table 185 Write data to the slave 1 Write the slave address with the RW bit set to 0 to the Master data register MSTDAT See Table 196 2 Start the transmission by setting the MSTSTART bit to 1 in the Master control register See Table 194 The following happens The pending status is cleared and the I2C bus is busy The I2C master sends the start bit and address with the RW bit to the slave 3 Wait for the pending status to be set MSTPENDING 1 by polling the STAT register 4 Write 8 bits of data to the MSTDAT register All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 207 of 370 NXP Semiconductors U M1 0601 UM10601 Chapter 16 LPC81x I2C bus interface Continue with the transmission of the data by setting the MSTCONT bit to 1 in the Master control register See Table 194 The following happens The pending status is cleared and the I2C bus is busy The l2C master sends the data bits to the slave address Wait for the pending status to be set MSTPENDING 1 by polling the STAT register Stop the transmission by setting the MSTSTOP bit to 1 in the Master control register See Table 194 Read data from the slave 1 o Ww
127. enable the pattern match functionality This eliminates the possibility of spurious interrupts as the feature is being enabled Table 103 Pattern match interrupt control register PMCTRL address 0xA000 4028 bit description Bit Symbol Value Description Reset value 0 SEL PMATCH Specifies whether the 8 pin interrupts are controlled by 0 the pin interrupt function or by the pattern match function 0 Pin interrupt Interrupts are driven in response to the standard pin interrupt function 1 Pattern match Interrupts are driven in response to pattern matches 1 ENA RXEV Enables the RXEV output to the ARM cpu and ortoa 0 GPIO output when the specified boolean expression evaluates to true 0 Disabled RXEV output to the cpu is disabled 1 Enabled RXEV output to the cpu is enabled 23 2 Reserved Do not write 1s to unused bits 0 31 24 This field displays the current state of pattern matches 0 0 A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs Pattern Match Interrupt Bit Slice Source register The bit slice source register specifies the input source for each of the eight pattern match bit slices Each of the possible eight inputs is selected in the pin interrupt select registers in the SYSCON block See Section 4 6 27 Input O corresponds to the pin selected in the PINTSELO register input 1 corresponds to the pin selected in the PIN
128. from internally floating as follows Set bits 10 and 11 in the GPIO DIRO register to 1 to enable the output driver and write 1 to bits 10 and 11 in the GPIO CLRO register to drive the outputs LOW internally UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 335 of 370 NXP Semiconductors UM1 0601 4 Chapter 27 LPC81x Packages and pin description RESET functionality is not available in Deep power down mode Use the WAKEUP pin to reset the chip and wake up from Deep power down mode An external pull up resistor is required on this pin for the Deep power down mode 5 5 V tolerant pin providing standard digital I O functions with configurable modes configurable hysteresis and analog input When configured as an analog input the digital section of the pin is disabled and the pin is not 5 V tolerant 6 5 V tolerant pad providing digital I O functions with configurable pull up pull down resistors and configurable hysteresis In Deep power down mode pulling this pin LOW wakes up the chip 7 5 V tolerant pad providing digital I O functions with configurable pull up pull down resistors and configurable hysteresis 8 5 V tolerant pin providing standard digital I O functions with configurable modes configurable hysteresis and analog I O for the system oscillator When configured as an analog I O the digital section of the
129. function can operate without any internal clocking when the slave is not currently addressed This means that reduced power modes up to Power down mode can be entered and the device will wake up when the I C Slave function recognizes an address Monitor mode can similarly wake up the device from a reduced power mode when information becomes available All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 230 of 370 NXP Semiconductors U M1 0601 Chapter 16 LPC81x I2C bus interface 16 7 5 Interrupts The 12 provides a single interrupt output that handles all interrupts for Master Slave and Monitor functions UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 231 of 370 UM10601 Chapter 17 LPC81x SPIO 1 Rev 1 6 2 April 2014 User manual 17 1 How to read this chapter SPIO is available on all parts SPI1 is available on parts LPC812M101JDH16 and LPC812M101JDH20 only See Section 29 3 Code examples SPI for code examples that explain how to program the register interface 17 2 Features Data transmits of 1 to 16 bits supported directly Larger frames supported by software Master and slave operation Data can be transmitted to a slave without the need to read incoming data This can
130. gt SLVADRO 0x23 lt lt 1 put address in address 0 register LPC I2C CFG I2C SLVEN while LPC_I2C gt STAT amp I2C STAT SLVPENDING if LPC_I2C gt STAT amp I2C STAT SLVSTATE I2C STAT SLVST ADDR abort LPC_I2C gt SLVCTL I2C SLVCTL SLVCONTINUE ack address while LPC_I2C gt STAT amp I2C STAT SLVPENDING if LPC_I2C gt STAT amp I2C STAT SLVSTATE I2C STAT SLVST RX abort data LPC I2C SLVDAT read data if data Oxdd abort LPC_I2C gt SLVCTL I2C SLVCTL SLVNACK nack data UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 347 of 370 NXP Semiconductors UM1 0601 Chapter 29 LPC81x Code examples 29 3 Code examples SPI 29 3 1 Definitions Table 324 SPI Code example SPI defines define SPI_CFG_ENABLE define SPI_CFG_MASTER define SPI_STAT_RXRDY define SPI_STAT_TXRDY define SPI_STAT_SSD 0x20 define SPI_STAT_MSTIDLE 0x100 define SPI_TXDATCTL_SSEL_N s s lt lt 16 define SPI_TXDATCTL_EOT lt lt 20 define SPI_TXDATCTL_EOF lt lt 21 define SPI_TXDATCTL_RXIGNORE 1 lt lt 22 define SPI_TXDATCTL_FLE 1 lt lt 24 0x 29 3 2 Interrupt handler Table 325 SPI Code example Interrupt handler void Spi IRQHandler uinti16 t data u
131. identification numbers Device Hex coding LPC810M021FN8 0x0000 8100 LPC811M001JDH16 0x0000 8110 LPC812M101JDH16 0x0000 8120 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 285 of 370 NXP Semiconductors U M1 0601 22 5 1 12 22 5 1 13 22 5 1 14 22 5 1 15 UM10601 Chapter 22 LPC81x Flash ISP and IAP programming Table 250 Part identification numbers Device Hex coding LPC812M101JD20 0x0000 8121 LPC812M101JDH20 0x0000 8122 LPC812M101JTB16 0x0000 8122 Read Boot code version number Table 251 UART ISP Read Boot Code version number command Command K Input None Return Code CMD_SUCCESS followed by 2 bytes of boot code version number in ASCII format It is to be interpreted as lt byte1 Major gt lt byteO Minor gt Description This command is used to read the boot code version number Compare lt address1 gt lt address2 gt no of bytes gt Table 252 UART ISP Compare command Command M Input Address1 DST Starting flash or RAM address of data bytes to be compared This address should be a word boundary Address2 SRC Starting flash or RAM address of data bytes to be compared This address should be a word boundary Number of Bytes Number of bytes to be compared should be a multiple of 4 Return Code CMD_SUCCESS Source and destination data are equal COMPARE_ERROR F
132. is deselected and GPIO is assigned to this pin Functions CLKIN and ACMP 12 are connected to the same pin PIOO 1 To use ACMP 12 disable the CLKIN function in bit 7 of this register and enable ACMP 12 0 Enable 12 This function is enabled on pin PIOO 1 1 Disable ACMP 12 GPIO function PIOO 1 default or any other movable function can be assigned to pin PIOO 1 Enables fixed pin function Writing a 1 deselects the function and any movable function can be assigned to this pin This function is selected by default 0 Enable SWCLK This function is enabled on pin PIOO 3 Disable SWCLK GPIO function PIOO 3 is selected on this pin Any other movable function can be assigned to pin PIOO 3 Enables fixed pin function Writing a 1 deselects the function and any movable function can be assigned to this pin This function is selected by default 0 Enable SWDIO This function is enabled on pin PIOO 2 Disable SWDIO GPIO function PIOO 2 is selected on this pin Any other movable function can be assigned to pin PIOO 2 1 1 0 0 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 131 of 370 NXP Semiconductors U M1 0601 Chapter 9 LPC81x Switch matrix Table 118 Pin enable register 0 PINENABLEO address 0x4000 C1C0 bit description Bit Symbol Value Description Reset value 4 XTALIN EN Enables fixed pin
133. logic 1 interrupt wake up enable register STARTERP1 address 0x4004 8214 bit description Inthe PDAWAKE register configure all peripherals that need to be running when the part wakes up Configure the I2C in slave mode UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 209 of 370 NXP Semiconductors U M1 0601 Chapter 16 LPC81x I2C bus interface Enable the 12C the interrupt in the I2C INTENCLR register which configures the interrupt as wake up event Examples are the following events Slave deselect Slave pending wait for read write or ACK Address match Data available ready for the monitor 16 4 Pin description The I2C pins are movable pin functions and are assigned to pins on the LPC81x packages through the switch matrix You have two choices to connect the 12C pins 1 Connect to special 12C open drain pins PIOO 10 and PIOO 11 2 Connect to any other pin that can host a movable function When the I C function is connected to specialized I C pins it supports the full I2 C bus specification up to Fast Mode Plus up to 1 MHz I C When the I C function is connected to standard pins that are set to open drain mode a functional I2C bus can be used in this way but some aspects of the 1 C bus specification may not be met This can have an impact on the bus speed noise filtering
134. master that provides the shortest SCL high time will cause that time to appear on SCL as long as that master is participating in I2C traffic i e when it is the only master on the bus or during arbitration between masters Rate calculations give a base frequency that represents the fastest that the IC bus could operate if nothing slows it down Rate calculations SCL high time in 12 function clocks CLKDIV 1 MSTSCLHIGH 2 SCL low time in 12 function clocks CLKDIV 1 MSTSCLLOW 2 Nominal SCL rate 12C function clock rate SCL high time SCL low time Time out A time out feature on an I C interface can be used to detect a stuck bus and potentially do something to alleviate the condition Two different types of time out are supported Both types apply whenever the 12C block and the time out function are both enabled Master Slave or Monitor functions do not need to be enabled In the first type of time out reflected by the EVENTTIMEOUT flag in the STAT register the time between bus events governs the time out check These events include Start Stop and all changes on the I C clock SCL This time out is asserted when the time between All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 229 of 370 NXP Semiconductors U M1 0601 UM10601 16 7 3 16 7 4 Chapter 16 LPC81x I2C bus in
135. more minterms product terms of the specified boolean expression is matched A separate interrupt request is generated for each individual minterm In addition the pattern match module can be enabled to generate a Receive Event RXEV output to the ARM core when a boolean expression is true i e when any minterm is matched The RXEV output is also be routed to GPIO_INT_BMAT pin This allows the GPIO module to provide a rudimentary programmable logic capability employing up to eight inputs and one output The pattern match function utilizes the same eight interrupt request lines as the pin interrupts so these two features are mutually exclusive as far as interrupt generation is concerned A control bit is provided to select whether interrupt requests are generated in response to the standard pin interrupts or to pattern matches Note that if the pin interrupts are selected the RXEV request to the CPU can still be enabled for pattern matches Remark Pattern matching cannot be used to wake the part up from Deep sleep or power down mode Pin interrupts must be selected in order to use the pins for wake up Boolean expressions The pattern match module is constructed of eight bit slice elements Each bit slice is programmed to represent one component of one minterm product term within the boolean expression The interrupt request associated with the last bit slice for a particular minterm will be asserted whenever that minterm is matched
136. must also occur after the watchdog counter passes that value When the Watchdog Timer is configured so that a watchdog event will cause a reset and the counter reaches zero the CPU will be reset loading the stack pointer and program counter from the vector table as for an external reset The Watchdog time out flag WDTOF can be examined to determine if the Watchdog has caused the reset condition The WDTOF flag must be cleared by software When the Watchdog Timer is configured to generate a warning interrupt the interrupt will occur when the counter matches the value defined by the WARNINT register 12 5 1 Block diagram The block diagram of the Watchdog is shown below in the Figure 24 The synchronization logic PCLK WDCLK is not shown in the block diagram UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 172 of 370 NXP Semiconductors U M1 0601 Chapter 12 LPC81x Windowed Watchdog Timer WWDT feed ok 4 24 bit down counter enable count FEED WINDOW a el WDTV feed sequence ange re detect and WDINTVAL protection 0 ORAL g compare compare 1 5 shadow bit feed ok MOD WDPROTECT WDTOF WDINT WDRESET WDEN register 4 2 MOD 3
137. must be set in the WWDT MOD register and the WWDT must be enabled in the SYSAHBCLKCTRL register Reset from the watchdog timer WWDT reset must be set in the WWDT MOD register In this case the watchdog oscillator must be running in Deep sleep mode see PDSLEEPCFG register and the WDT must be enabled in the SYSAHBCLKCTRL register Via any of the USART blocks if the USART is configured in synchronous mode See Section 15 3 2 Configure the USART for wake up e Via the I2C See Section 16 3 2 Via any of the SPI blocks See Section 17 3 1 5 7 6 Power down mode In Power down mode the system clock to the processor is disabled as in Sleep mode All analog blocks are powered down except for the BOD circuit and the watchdog oscillator which must be selected or deselected during Power down mode in the PDSLEEPCFG register The main clock and therefore all peripheral clocks are disabled except for the clock to the watchdog timer if the watchdog oscillator is selected The IRC itself and the flash are powered down decreasing power consumption compared to Deep sleep mode Power down mode eliminates all power used by analog peripherals and all dynamic power used by the processor itself memory systems and related controllers and internal buses The processor state and registers peripheral registers and internal SRAM values are maintained and the logic levels of the pins remain static Wake up times are longer compared to t
138. new system clock is 24 MHz System clock greater than or equal to the expected value command 0 12000 command 1 20000 command 2 FREQ command 3 0 LPC_PWRD_API gt set_pll command result The above code specifies a 12 MHz PLL input clock a system clock of at least 20 MHz and no locking time out set_p returns PLL CMD SUCCESS in result 0 and 24000 in result 1 The new system clock is 24 MHz All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 304 of 370 NXP Semiconductors U M1 0601 23 5 1 6 23 5 2 23 5 2 1 23 5 2 2 UM10601 Chapter 23 LPC81x Power profile ROM driver System clock approximately equal to the expected value command 0 12000 command 1 16500 command 2 CPU FREQ APPROX command 3 0 LPC PWRD API set pll command result The above code specifies a 12 MHz PLL input clock a system clock of approximately 16 5 MHz and no locking time out set pll returns PLL CMD SUCCESS in result 0 and 16000 in result 1 The new system clock is 16 MHz Power control See Section 23 5 1 1 and Section 23 5 2 2 for examples of the power control API Invalid frequency device maximum clock rate exceeded command 0 30 command 1 CPU PERFORMANCE command 2 40 LPC PWRD API set power command result The above setup would b
139. number of 1s in a received character is expected to be even 0x3 Odd parity Adds a bit to each character such that the number of 1s in a transmitted character is odd and the number of 1s in a received character is expected to be odd 6 STOPLEN Number of stop bits appended to transmitted data Only a 0 single stop bit is required for received data 0 1 stop bit 1 2 stop bits This setting should only be used for asynchronous communication Reserved Only write 0 to this bit Reserved Read value is undefined only zero should be NA written UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 194 of 370 NXP Semiconductors U M1 0601 Chapter 15 LPC81x USARTO 1 2 Table 173 USART Configuration register CFG address 0x4006 4000 USARTO 0x4006 8000 USART1 0x4006 C000 USART2 bit description continued Bit Symbol Value Description Reset Value 9 CTSEN CTS Enable Determines whether CTS is used for flow 0 control CTS can be from the input pin or from the USART s own RTS if loopback mode is enabled See Section 15 7 3 for more information 0 No flow control The transmitter does not receive any automatic flow control signal 1 Flow control enabled The transmitter uses the CTS input or RTS output in loopback mode for flow control purposes 10 Reserved Read value is undefined only zero sh
140. of the Current Controlled Oscillator 156 to 320 MHz FCLKOUT Frequency of sys pllclkout This is the PLL output frequency and must be 100 MHz P System PLL post divider ratio PSEL bits in SYSPLLCTRL see Section 4 6 3 M System PLL feedback divider register MSEL bits in SYSPLLCTRL see Section 4 6 3 4 7 4 4 4 Normal mode In this mode the post divider is enabled giving a 50 duty cycle clock with the following frequency relations 1 Fclkout 2 M x Fclkin 2 FCCO 2 x P UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 52 of 370 NXP Semiconductors U M1 0601 Chapter 4 LPC81x System configuration SYSCON To select the appropriate values for M and P it is recommended to follow these steps Specify the input clock frequency Fclkin Calculate M to obtain the desired output frequency Fclkout with M Foout Felkin Find a value so that FCCO 2 x P x Fetkout N Verify that all frequencies and divider values conform to the limits specified in Table 20 Remark The divider values for P and M must be selected so that the PLL output clock frequency FCLKOUT is lower than 100 MHz Table 52 shows how to configure the PLL for a 12 MHz crystal oscillator using the SYSPLLCTRL register Table 20 The main clock is equivalent to the system clock if the system clock divider SYS
141. peripherals la eee tn eene eres flash controller 0x4004 0000 1GB 0x4000 0000 reserved 0x4003 C000 reserved 0x4003 8000 Te reserved SES reserved 0 5 GB 0x2000 0000 0x4003 4000 ES reserved uM reserved 0x4003 0000 Ox1FFF 2000 8 kB boot ROM dieu 0 4002 000 EU reserved 0x4002 8000 Sd reserve analog comparator 0x1400 0400 0 4002 4000 1 kB MTB registers 0x4002 0000 0x1400 0000 reserved 0x4001 C000 reserved reserved 0x4001 8000 reserved 0x4001 4000 reserved 0x4001 0000 Switch matrix 0x4000 C000 self wake up timer 0x4000 8000 MRT 0x4000 4000 WWDT 0x4000 0000 0x1000 1000 4kB SRAM LPC812 0x1000 0800 2kB SRAM LPC811 0x1000 0400 1 SRAM LPC810 0x1000 0000 BN reserved m Jo JF o IN Jo v 0x0000 4000 16 kB on chip flash LPC812 0x0000 2000 0x0000 00CO 8 kB on chip flash LPC811 0x0000 1000 active interrupt vectors 0 0000 0000 4 kB on chip flash LPC810 dd 0x0000 0000 aaa 005748 The private peripheral bus includes the ARM Cortex M0 peripherals such as the NVIC SysTick and the core control registers Fig 2 LPC81x Memory mapping 2 2 2 Micro Trace Buffer MTB The LPC81x supports the ARM Cortex MO Micro Trace Buffer See Section 26 5 4 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 11 of 370 UM
142. pin is disabled and the pin is not 5 V tolerant 9 The digital part of this pin is V tolerant pin due to special analog functionality Pin provides standard digital I O functions with configurable modes configurable hysteresis and an analog input When configured as an analog input the digital section of the pin is disabled UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 336 of 370 UM10601 Chapter 28 LPC81x Appendix Rev 1 6 2 April 2014 28 1 How to read this chapter User manual This chapter summarizes the ARM Cortex MO instructions The instruction set is identical for all LPC81x parts 28 2 General description The processor implements the ARMv6 M Thumb instruction set including a number of 32 bit instructions that use Thumb 2 technology The ARMv6 M instruction set contains all of the 16 bit Thumb instructions from ARMv7 M excluding CBZ CBNZ and IT the 32 bit Thumb instructions BL DMB DSB ISB MRS and MSR Table 306 shows the Cortex M0 instructions and their cycle counts The cycle counts are based on a system with zero wait states Table 306 Cortex MO instruction summary Operation Move Description 8 bit immediate Lo to Lo Any to Any Any to PC Add 3 bit immediate All registers Lo Any to Any Any to PC 8 bit immediate With carry Immediate to
143. register Remark The MTB BASE register is not implemented Reading the BASE register returns 0 0 independently of the SRAM memory area configured for trace UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 331 of 370 UM10601 Chapter 27 LPC81x Packages and pin description Rev 1 6 2 April 2014 User manual 27 1 Packages RESET PIOO_5 8 PIOO_O ACMP_I1 TDO 4 WAKEUP TRST SWCLK PIOO 3 TCK 6 Vpp SWDIO PIOO 2 TMS 4 PIOO_1 ACMP_I2 CLKIN TDI aaa 005747 Fig 53 Pin configuration DIP8 package LPC810M021JN8 PIO0_13 PIO0 0 ACMP I1 TDO PIOO 12 C PIO0 6 VDDCMP RESET PIO0 5 PIOO 7 PIO0 4 WAKEUP TRST TSSOP46 Vss SWCLK PIOO 3 TCK Vpp SWDIO PIO0_2 TMS PIOO_8 XTALIN PIOO_11 PIO0_9 XTALOUT PIOO 10 PIOO 1 ACMP IZ CLKIN TDI aaa 003707 Fig 54 Pin configuration TSSOP16 package LPC811M001JDH16 and LPC812M101JDH16 PIOO 17 PIOO 14 PIOO 13 0 ACMP H TDO PIOO 12 6 VDDCMP 5 7 4 WAKEUP TRST Vss SWCLK PIOO 3 TCK SWDIO PIOO 2 TMS PIOO 8 XTALIN PIOO 11 PIOO 9 XTALOUT PIOO 10 PIOO_1 ACMP_2 CLKIN TDI PIOO 16 15 aaa 003756 Fig 55 Pin configuration SO20 package LPC812M101JD20 UM10601 All information provided in this document is subject to legal disclaimers
144. sent to the host The host should respond by sending the crystal frequency in kHz at which the part is running The response is required for backward compatibility of the boot loader code and on the LPC81x is ignored The boot loader configures the part to run at the 12 MHz IRC frequency Once the crystal frequency response is received the part is initialized and the ISP command handler is invoked For safety reasons an Unlock command is required before executing the commands resulting in flash erase write operations and the Go command The rest of the commands can be executed without the unlock command The Unlock command is required to be executed once per ISP session The Unlock command is explained in Table 239 UART ISP Unlock command All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 274 of 370 NXP Semiconductors U M1 0601 Chapter 21 LPC81x Boot ROM 21 6 3 Boot process flowchart RESET INITIALIZE no CRP1 2 3 ENABLED ENABLE DEBUG id USER CODE VALID WATCHDOG FLAG SET CRP3 NO ISP no ENABLED bd pe EXECUTE INTERNAL 3 USER CODE ISP ENTRY PIN LOW yes yes 4 USER CODE VALID boot from UART AA RUN AUTO BAUD 1 v AUTO BAUD SUCCESSFUL RECEIVE CRYSTAL FREQUENCY 2 RUN UART ISP COMMA
145. several lock features which can be enabled to ensure that the WWDT is running at all times Disabling the WWDT clock source Changing the WWDT reload value Disabling the WWDT clock source If bit 5 in the WWDT MOD register is set the WWDT clock source is locked and can not be disabled either by software or by hardware when Sleep Deep sleep or Power down modes are entered Therefore the user must ensure that the watchdog oscillator for each power mode is enabled before setting bit 5 in the MOD register In Deep power down mode no clock locking mechanism is in effect because no clocks are running However an additional lock bit in the PMU can be set to prevent the part from even entering Deep power down mode see Table 55 Changing the WWDT reload value If bit 4 is set in the WWDT MOD register the watchdog time out value TC can be changed only after the counter is below the value of WDWARNINT and WDWINDOW The reload overwrite lock mechanism can only be disabled by a reset of any type All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 174 of 370 NXP Semiconductors UM10601 12 6 Register description Chapter 12 LPC81x Windowed Watchdog Timer WWDT UM10601 12 6 1 The Watchdog Timer contains the registers shown in Table 155 The reset value reflects the data stored in used bits only It does not in
146. slice 2 0 0x0 Input 0 Selects the pin selected in the PINTSELO register as the source to bit slice 2 0 1 Input 1 Selects the pin selected in the PINTSEL1 register as the source to bit slice 2 0x2 Input 2 Selects the pin selected in the PINTSEL2 register as the source to bit slice 2 0x3 Input Selects the pin selected the PINTSELS register as the source to bit slice 2 0 4 Input 4 Selects the pin selected in the PINTSEL4 register as the source to bit slice 2 0 5 Input 5 Selects the pin selected in the PINTSEL5 register as the source to bit slice 2 0x6 Input 6 Selects the pin selected in the PINTSEL6 register as the source to bit slice 2 0 7 Input 7 Selects the pin selected in the PINTSEL7 register as the source to bit slice 2 19 17 SRC3 Selects the input source for bit slice 3 0 0x0 Input 0 Selects the pin selected in the PINTSELO register as the source to bit slice 3 0 1 Input 1 Selects the pin selected in the PINTSEL1 register as the source to bit slice 3 0 2 Input 2 Selects the pin selected in the PINTSEL2 register as the source to bit slice 3 0x3 Input 3 Selects the pin selected in the PINTSELS register as the source to bit slice 3 0 4 Input 4 Selects the pin selected in the PINTSEL4 register as the source to bit slice 3 0 5 Input 5 Selects the pin selected in the PINTSEL5 register as the source to bit slice 3 0x6 Input 6 Selects the pin selected in the PINTSEL6 register as the source to bit slice 3
147. small outline package 20 leads body width 7 5 mm SOT163 1 LPC812M101JDH20 TSSOP20 plastic thin shrink small outline package 20 leads body width 4 4 mm SOT360 1 LPC812M101JTB16 XSON16 plastic extremely thin small outline package no leads 16 terminals body SOT1341 2 5 x 3 2 x 0 5 mm 1 Table 2 Ordering options Type number Flash kB SRAM kB USART 2 SPI Comparator GPIO Package LPC810M021FN8 4 1 2 1 1 1 6 DIP8 LPC811M001JDH16 8 2 2 1 1 1 14 TSSOP16 LPC812M101JDH16 16 4 3 1 2 1 14 TSSOP16 LPC812M101JD20 16 4 2 1 1 1 18 5020 LPC812M101JDH20 16 4 3 1 2 1 18 TSSOP20 LPC812M101JTB16 16 4 3 1 2 1 14 XSON16 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 7 of 370 NXP Semiconductors U M1 0601 Chapter 1 LPC81x Introductory information 1 4 Block diagram LPC81xM SWCLK SWD gt TEST DEBUG Tex INTERFACE PIOO HIGH SPEED lt GPIO ARM CORTEX MO FLASH SRAM PIN INTERRUPTS 4 8 16 kB 1 2 4 kB PATTERN MATCH save save CTOUT 0 SCTIMER CTIN 3 0 PWM AHB LITE BUS ii slave slave AHB TO APB BRIDGE XT WWDT gt USARTO IOCON SWITCH MULT RATE TIMER MATRIX scg seme wen 4 RXD CTS SCLK SCK SSEL MISO MOSI se SCK SSEL ee MISO MOSI WAKE UP TIMER SCL
148. subaddress 0xaa Polling mode No error checking if LPC_I LPC_I2C gt subadd LPC_I2C gt while L if LPC_I LPC_I2C gt LPC_I2C gt while L if LPC_I LPC_I2C gt subadd LPC_I2C gt 1 data LP d LPC_I2C gt if LPC I 2C gt 1 STDAT DAI PC I2C MSTCTL I2C MSTCTL 2C gt 1 _I2C gt STAT amp I2C TAT amp I2C STAT T 0x23 lt lt gt STAT TAT amp C_I2C gt MSTDAT ata Qxdd abo while LPC_I2C gt STAT AT amp amp 12C_ 2C STAT t amp 12C_ 2C STAT LPC I2C CFG I2C MSTEN while LPC_I2C gt STAT amp I2C STAT MSTPENDINGC AT amp I2C STAT 0x23 STCTL I2C C_I2C gt STAT amp I2C_ amp I2C STAT S se STCTL I2C MSTCTL C C S e S S S CTL I2C MSTCTL S re S STSTATE I2C STAT MSTST IDLE abort 0 address and 0 for RWn bit in order to write STSTART send start TAT_MSTPENDING STSTATE I2C STAT MSTSTX abort nd subaddress STCONTINUE continue transaction TAT_MSTPENDING STSTATE I2C STAT MSTSTX abort 1 address and 1 for RWn bit in order to write STSTART send repeated start TAT_MSTPENDING STSTATE I2C STAT MSTST RX abort ad data STSTOP send stop TAT_MSTPENDING STSTATE I2C STAT MSTST IDLE abort Master
149. the MASK register is 1 write clear output bit if the corresponding bit in the MASK register is 0 1 Read pin is HIGH and the corresponding bit in the MASK register is 0 write set output bit if the corresponding bit in the MASK register is 0 31 18 Reserved 0 GPIO port set registers Output bits can be set by writing ones to these registers regardless of MASK registers Reading from these register returns the port s output bits regardless of pin directions Table 88 GPIO set port 0 register SETO address 0xA000 2200 bit description Bit Symbol Description Reset Access value 17 0 SETPO Read or set output bits 0 R W 0 Read output bit write no operation 1 Read output bit write set output bit 31 18 Reserved 0 GPIO port clear registers Output bits can be cleared by writing ones to these write only registers regardless of MASK registers All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 93 of 370 NXP Semiconductors UM10601 7 6 9 7 7 Functional Chapter 7 LPC81x GPIO port Table 89 GPIO clear port 0 register CLRO address 0xA000 2280 bit description Bit Symbol Description Reset Access value 17 0 CLRPO Clear output bits NA WO 0 No operation 1 Clear output bit 31 18 Reserved 0 GPIO port toggle registers Output bits can be toggled inver
150. the host Exceptions from this rule are Set Baud Rate Write to RAM Read Memory and Go commands Table 238 UART ISP command summary ISP Command Usage Described in Unlock U Unlock Code Table 239 Set Baud Rate B Baud Rate stop bit Table 240 Echo A setting Table 241 Write to RAM W start address gt number of bytes Table 242 Read Memory R address number of bytes Table 243 Prepare sector s for P start sector number end sector number gt Table 244 write operation Copy RAM to flash C Flash address RAM address number of bytes Table 245 Go G address Mode Table 246 Erase sector s E start sector number end sector number Table 247 Blank check sector s start sector number end sector number Table 248 Read Part ID J Table 249 Read Boot code version Table 251 Compare M address lt address2 gt number of bytes Table 252 ReadUID N Table 253 Read CRC checksum S address number of bytes Table 254 22 5 1 4 Unlock Unlock code Table 239 UART ISP Unlock command Command U Input Unlock code 23130 decimal Return Code CMD SUCCESS INVALID CODE PARAM ERROR Description This command is used to unlock Flash Write Erase and Go commands Example U 23130 lt CR gt lt LF gt unlocks the Flash Write Erase amp Go commands UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights rese
151. the user allocated stack space is 148 bytes and grows downwards Debugging Comparing flash images Depending on the debugger used and the IDE debug settings the memory that is visible when the debugger connects might be the boot ROM the internal SRAM or the flash To help determine which memory is present in the current debug environment check the value contained at flash address 0x0000 0004 This address contains the entry point to the code in the ARM Cortex MO vector table which is the bottom of the boot ROM the internal SRAM or the flash memory respectively Table 268 Memory mapping in debug mode Memory mapping mode Memory start address visible at 0x0000 0004 Bootloader mode 0x1FFF 0000 User flash mode 0x0000 0000 User SRAM mode 0x1000 0000 Serial Wire Debug SWD flash programming interface Debug tools can write parts of the flash image to RAM and then execute the IAP call Copy RAM to flash repeatedly with proper offset All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 296 of 370 UM10601 Chapter 23 LPC81x Power profile ROM driver Rev 1 6 2 April 2014 User manual 23 1 How to read this chapter The power profiles are available for all LPC81x parts 23 2 Features Includes ROM based application services Power Management services Clocking services 23 3 General descr
152. to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 221 of 370 NXP Semiconductors U M1 0601 UM10601 16 6 6 16 6 7 Chapter 16 LPC81x I2C bus interface Table 191 time out register TIMEOUT address 0x4005 0010 bit description Bit Symbol Description Reset value 3 0 TOMIN Time out time value bottom four bits These are hard wired to OxF OxF This gives a minimum time out of 16 12 function clocks and also a time out resolution of 16 12C function clocks 15 4 TO Time out time value Specifies the time out interval value in increments OxFFF of 16 12C function clocks as defined by the CLKDIV register To change this value while 12C is in operation disable all time outs write new value to TIMEOUT then re enable time outs 0x000 A time out will occur after 16 counts of the I C function clock 0x001 A time out will occur after 32 counts of the 12C function clock OxFFF A time out will occur after 65 536 counts of the 12C function clock 31 16 Reserved Read value is undefined only zero should be written NA 12C Clock Divider register The CLKDIV register divides down the Peripheral Clock PCLK to produce the 12 function clock that is used to time various aspects of the 12C interface The I C function clock is used for some internal operations in the 12C block and to generate the timing required by the I2C bus specification some of which a
153. transaction LPC_I2C gt INTENCLR I2C STAT MSTPENDING 29 2 3 Master write one byte to slave Table 309 12C Code example Master write one byte to slave Address 0x23 Data Oxdd Polling mode LPC_I2C gt CFG I2C_CFG_MSTEN while LPC_I2C gt STAT amp I2C STAT MSTPENDING if LPC_I2C gt STAT amp I2C STAT MSTSTATE I2C STAT MSTST IDLE abort LPC I2C MSTDAT 0x23 lt lt 1 0 address and 0 for RWn bit LPC I2C MSTCTL I2C MSTCTL MSTSTART send start while LPC_I2C gt STAT amp I2C STAT MSTPENDING if LPC_I2C gt STAT amp I2C STAT MSTSTATE I2C STAT MSTSTX abort LPC_I2C gt MSTDAT 0 send data 5 C LPC_I2C gt MSTCTL I2C MSTCTL MSTCONTINUE continue transaction while LPC_I2C gt STAT amp I2C STAT MSTPENDING if LPC_I2C gt STAT amp I2C STAT MSTSTATE I2C STAT MSTSTX abort LPC I2C MSTCTL I2C MSTCTL MSTSTOP send stop while LPC_I2C gt STAT amp I2C STAT MSTPENDING if LPC_I2C gt STAT amp I2C STAT MSTSTATE I2C STAT MSTST IDLE abort UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 341 of 370 NXP Semiconductors UM10601 29 2 4 Table 310 12C Code example Chapter 29 LPC81x Code examples Master read one byte from slave Master rea
154. up to 18 general purpose l O pins For additional documentation related to this part see Section 30 2 References UM10601 System ARM Cortex M0 processor running at frequencies of up to 30 MHz with single cycle multiplier and fast single cycle I O port ARM Cortex M0 built in Nested Vectored Interrupt Controller NVIC System tick timer Serial Wire Debug SWD and JTAG boundary scan modes BSDL supported Micro Trace Buffer MTB supported e Memory Up to 16 kB on chip flash programming memory with 64 Byte page write and erase 4 kB SRAM ROM API support Boot loader USART drivers 12 drivers Power profiles Flash In Application Programming IAP and In System Programming ISP Digital peripherals High speed GPIO interface connected to the ARM Cortex MO IO bus with up to 18 General Purpose I O GPIO pins with configurable pull up pull down resistors programmable open drain mode input inverter and glitch filter High current source output driver 20 mA on four pins High current sink driver 20 mA on two true open drain pins GPIO interrupt generation capability with boolean pattern matching feature on eight GPIO inputs Switch matrix for flexible configuration of each I O pin function All information provided in this document is subject to legal disclaimers NXP B V 2014 AII rights reserved User manual Rev 1 6 2 April 2014 5 of 370 NXP Semiconductor
155. value is undefined only zero should be written NA Slave Control register The SLVCTL register contains bits that control various functions of the 1 C Slave interface Only write to this register when the slave is pending SLVPENDING 1 in the STAT register Table 186 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 225 of 370 NXP Semiconductors U M1 0601 UM10601 16 6 12 Chapter 16 LPC81x I2C bus interface Table 197 Slave Control register SLVCTL address 0x4005 0040 bit description Bit Symbol Value Description Reset Value 0 SLVCONTINUE Slave Continue 0 0 No effect Continue Informs the Slave function to continue to the next operation This must done after writing transmit data reading received data or any other housekeeping related to the next bus operation 1 SLVNACK Slave NACK 0 0 No effect NACK Causes the Slave function to NACK the master when the slave is receiving data from the master Slave Receiver mode 31 2 Reserved Read value is undefined only zero should be written Slave Data register The SLVDAT register provides the means to read the most recently received data for the Slave function and to transmit data using the Slave function Table 198 Slave Data register SLVDAT address 0x4005 0044 bit description Bit Symbol Description Reset Value 7 0 DA
156. whenever a rising or falling edge occurs after a qualifying edge event You can create a time window during which rising or falling edges can create a pin interrupt by combining a level detect with an event detect See Section 8 7 3 for details INO IN1 IN2 IN3 IN4 IN5 ING IN7 0 MUX From Previous Rise Detect 1 Slice sticky with synch clear PMCFG Fall Detect Prod_Endpts i sticky with synch 2 PMSRC SRC i 3 Pattern_Match i Intr_Req i 4 oe oe gt 6 Rise Detect non sticky gt Fall Detect non sticky To Next Slice Fig 9 Pattern match bit slice with detect logic PMCFG CFG i UM10601 8 5 2 1 Inputs and outputs of the pattern match engine The connections between the pins and the pattern match engine are shown in Figure 8 All inputs to the pattern match engine are selected in the SYSCON block and can be GPIO port pins or another pin function depending on the switch matrix configuration All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 100 of 370 NXP Semiconductors U M1 0601 UM10601 8 5 2 2 Chapter 8 LPC81x Pin interrupts pattern match engine The pattern match logic continuously monitors the eight inputs and generates interrupts when any one or
157. will enter Deep power down mode ARM Cortex MO core powered down 3 NODPD A 1 in this bit prevents entry to Deep power down mode 0 when 0x3 is written to the PM field above the SLEEPDEEP bit is set and a WFI is executed This bit is cleared only by power on reset so writing a one to this bit locks the part in a mode in which Deep power down mode is blocked 7 4 Reserved Do not write ones to this bit SLEEPFLAG Sleep mode flag 0 Active mode Read No power down mode entered Part is in Active mode Write No effect 1 Low power mode Read Sleep Deep sleep or Power down mode entered Write Writing a 1 clears the SLEEPFLAG bit to 0 10 9 Reserved Do not write ones to this bit 11 DPDFLAG Deep power down flag 0 Not Deep power down Read Deep power down mode 0 not entered Write No effect 1 Deep power down Read Deep power down mode entered Write Clear the Deep power down flag 31 112 Reserved Do not write ones to this bit 0 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 59 of 370 NXP Semiconductors U M1 0601 5 6 2 5 6 3 Chapter 5 LPC81x Reduced power modes and Power Management General purpose registers 0 to 3 The general purpose registers retain data through the Deep power down mode when power is still applied to the Vpp pin but the chip has entered Deep power down mode
158. yes yes no yes CRP2 yes yes yes no no yes no no yes all sectors only no yes yes no yes CRP3 no entry in ISP mode allowed n a n a n a n a n a n a n a n a n a n a n a n a n a n a In case a CRP mode is enabled and access to the chip is allowed via the ISP an unsupported or restricted ISP command will be terminated with return code CODE READ PROTECTION ENABLED ISP entry protection In addition to the three CRP modes the user can prevent the sampling of the ISP entry pin for entering ISP mode and thereby release the ISP entry pin for other uses This is called the ISP mode The NO ISP mode can be entered by programming the pattern Ox4E69 7370 at location 0x0000 02FC All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 279 of 370 NXP Semiconductors U M1 0601 Chapter 22 LPC81x Flash ISP and IAP programming 22 5 API description 22 5 1 UART ISP commands The following commands are accepted by the ISP command handler Detailed status codes are supported for each command The command handler sends the return code INVALID COMMAND when an undefined command is received Commands and return codes are in ASCII format CMD SUCCESS is sent by ISP command handler only when received ISP command has been completely executed and the new ISP command can be given by
159. 0 to 17 0x11 Pin assign register 1 Table 110 Pin assign register 1 PINASSIGN1 address 0x4000 C004 bit description Bit Symbol 7 0 UO SCLK IO 15 8 U1 TXD O 23 16 U1 I 31 24 U1 RTS O Description Reset value UO SCLK function assignment The value is the pin number to be OxFF assigned to this function The following pins are available PIOO 0 0 to PIOO 17 Ox11 U1 TXD function assignment The value is the pin number to be assigned to this function The following pins are available PIOO 0 0 to PIOO 17 Ox11 U1 RXD function assignment The value is the pin number to be assigned to this function The following pins are available PIOO 0 0 to PIOO 17 Ox11 U1 RTS function assignment The value is the pin number tobe OxFF assigned to this function The following pins are available PIOO 0 0 to PIOO 17 Ox11 Pin assign register 2 Table 111 Pin assign register 2 PINASSIGN2 address 0x4000 C008 bit description Bit Symbol 7 0 U1 CTS I 15 8 U1 SCLK IO 23 16 U2 TXD O 31 24 U2 RXD I Description Reset value U1 CTS function assignment The value is the pin number to be OxFF assigned to this function The following pins are available PIOO 0 0 to PIOO 17 Ox11 U1 SCLK function assignment The value is the pin number to OxFF assigned to this function The following pins are available PIOO 0 0 to PIOO
160. 0 0000 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 263 of 370 NXP Semiconductors U M1 0601 Chapter 19 LPC81x Cyclic Redundancy Check CRC engine 19 7 3 CRC 32 set up Polynomial x924 x26 x23 x22 x16 x12 x11 4 x10 X8 x7 4 x94 x44 x24 x 4 1 Seed Value OxFFFF FFFF Bit order reverse for data input YES 1 s complement for data input NO Bit order reverse for CRC sum YES 1 s complement for CRC sum YES MODE 0x0000 0036 SEED OxFFFF FFFF UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 264 of 370 UM10601 Chapter 20 LPC81x Flash controller Rev 1 6 2 April 2014 User manual 20 1 How to read this chapter 20 2 Features The flash controller is identical on all LPC81x parts Controls flash access time Provides registers for flash signature generation 20 3 General description The flash controller is accessible for programming flash wait states and for generating the flash signature 20 4 Register description 20 4 1 Table 225 Register overview FMC base address 0x4004 0000 Name Access Address Description Reset Reference offset value FLASHCFG R W 0x010 Flash configuration register Table 226 FMSSTART R W 0x020 Signatu
161. 0 2000 bit description 92 0000 bit description 59 Table 85 GPIO mask port 0 register MASKO address Table 57 General purpose registers 0 to GPREGI O0 3 0xA000 2080 bit description 92 address 0x4002 0004 GPREGO to 0x4002 0010 Table 86 GPIO port 0 pin register PINO address OxA000 GPREG3 bit description 60 2100 bit description 93 Table 58 Deep power down control register DPDCTRL Table 87 GPIO masked port 0 pin register MPINO address address 0x4002 0014 bit description 60 0xA000 2180 bit description 93 Table 59 Peripheral configuration in reduced power Table 88 GPIO set port 0 register SETO address OxA000 MOES isa eee eee are a ai eee 61 2200 bit description 93 Table 60 Pinout summary 68 Table 89 GPIO clear port 0 register CLRO address 0xA000 Table 61 Register overview I O configuration base 2280 bit description 94 address 0x4004 4000 71 Table 90 GPIO toggle port 0 register NOTO address Table 62 17 register PIOO 17 address 0x4004 0xAO000 2300 bit description 94 4000 bit lt 72 Table 91 Pin interrupt pattern match engine pin Table 63 PIOO 13 register 13 address 0x4004 97 4004 bit description
162. 0 7 10 1 Configure the counter 158 10 7 1 Match 154 10 7 10 2 Configure the match and capture registers 158 10 7 2 154 10 7 10 3 Configure events and event responses 159 10 7 3 Event 155 10 7 10 4 Configure multiple 160 10 7 4 Output 155 10 7 10 5 Miscellaneous options 160 10 7 5 jos 10711 RUNING SOT 160 10 76 Interrupt generation 156 10 7 12 Configure the SCT without using states 161 10 7 7 Clearing the prescaler 156 10 7 13 SCT PWM 161 Chapter 11 LPC81x Multi Rate Timer MRT 11 1 How to read this chapter 164 11 6 Register description 166 11 2 164 11 6 1 Time interval register 168 11 3 164 p bd s 11 4 Pi CEN 6 ontrol register GESEHDEBH 163 11 6 4 Status register 169 11 5 General description sess 164 4165 1 169 11 5 1 Repeat interrupt 165 11 6 6 Global interrupt flag regist
163. 0 OD Open drain mode 0 0 Disable 1 Open drain mode enabled Remark This is not a true open drain mode 12 11 5 MODE Digital filter sample mode 0 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than one filter clock are rejected 0 2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 1543 CLK_DIV Select peripheral clock divider for input filter sampling clock 0 Value 0 7 is reserved 0 0 IOCONCLKDIVO 0 1 IOCONCLKDIV1 0 2 IOCONCLKDIV2 0x3 IOCONCLKDIV3 0x4 IOCONCLKDIVA 0x5 IOCONCLKDIV5 0 6 IOCONCLKDIVE6 31 16 Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 86 of 370 NXP Semiconductors UM10601 6 5 16 PIOO 6 register Chapter 6 LPC81x I O configuration IOCON Table 77 PIOO_6 register PIOO 6 address 0x4004 4040 bit description Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 0x0 Inactive no pull down pull up resistor enabled 0 1 Pull down resistor enabled 0 2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input invert
164. 0 Parameter 1 Parameter n CR LF Data Data only for Write commands UART ISP response format Return_Code lt CR gt lt LF gt Response_0 lt CR gt lt LF gt Response_1 lt CR gt lt LF gt Response n CR LF Data Data only for Read commands UART ISP data format The data stream is in plain binary format Memory and interrupt use for ISP and IAP Interrupts during UART ISP The boot block interrupt vectors located in the boot block of the flash are active after any reset All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 295 of 370 NXP Semiconductors U M1 0601 22 6 2 2 22 6 2 3 22 6 2 4 22 6 3 22 6 3 1 22 6 3 2 UM10601 Chapter 22 LPC81x Flash ISP and IAP programming Interrupts during IAP The on chip flash memory is not accessible during erase write operations When the user application code starts executing the interrupt vectors from the user flash area are active Before making any IAP call either disable the interrupts or ensure that the user interrupt vectors are active in RAM and that the interrupt handlers reside in RAM The IAP code does not use or disable interrupts RAM used by ISP command handler The stack of ISP commands is located at 0x1000 0270 The maximum stack usage is 540 byte and grows downwards RAM used by IAP command handler The maximum stack usage in
165. 0 bytes of data LPC_USART gt CFG UART CFG DATALEN 8 UART CFG ENABLE for i 0 i 10 itt while LPC_USART gt STAT amp UART_STAT_TXRDY UART_STAT_RXRDY LPC_USART gt TXDAT LPC_USART gt RXDAT while LPC_USART gt STAT amp UART STAT TXIDLE Loop back 10 bytes of data using interrupts Table 340 UART Code example Loop back 10 bytes of data using interrupts LPC USART CFG UART DATALEN 8 UART ENABLE LPC_USART gt INTENSET UART STAT TXRDY UART STAT RXRDY while tx counter 10 LPC_USART gt INTENCLR UART STAT TXRDY UART STAT RXRDY while LPC_USART gt STAT amp UART STAT TXIDLE NVIC DisableIRQ Usart IROn All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 352 of 370 UM10601 Chapter 30 Supplementary information Rev 1 6 2 April 2014 User manual 30 1 Abbreviations Table 341 Abbreviations Acronym Description AHB Advanced High performance Bus APB Advanced Peripheral Bus BOD BrownOut Detection GPIO General Purpose Input Output PLL Phase Locked Loop RC Resistor Capacitor SPI Serial Peripheral Interface SMBus System Management Bus TEM Transverse ElectroMagnetic UART Universal Asynchronous Receiver Transmitter 30 2 References 1 LPC81XM LPC81X Data sheet 2 ES LPC81XM LPC81X Errata sheet 3 0010484
166. 014 113 of 370 NXP Semiconductors U M1 0601 Chapter 8 LPC81x Pin interrupts pattern match engine Table 105 Pattern match bit slice configuration register PMCFG address 0xA000 4030 bit description continued Bit Symbol Value Description Reset value 16 14 CFG2 Specifies the match contribution condition for bit slice 2 0b000 0x0 Constant HIGH This bit slice always contributes to a product term match 0 1 Sticky rising edge Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0 2 Sticky falling edge Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0x3 Sticky rising or falling edge Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0 4 High level Match for this bit slice occurs when there is a high level on the input specified for this bit slice in the PMSRC register 0 5 Low level Match occurs when there is a low level on the specified input Ox6 Constant 0 This bit slice never contributes to a match should be used t
167. 06 401C USARTO 0x4006 801C USART1 0x4006 C01C USART2 bit description Bit Symbol Description Reset Value 80 TXDATA Writing to the USART Transmit Data Register causes the data to be 0 transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met CTS low if CTSEN bit 1 TXDIS bit 0 31 9 Reserved Only zero should be written NA UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 201 of 370 NXP Semiconductors U M1 0601 Chapter 15 LPC81x USARTO 1 2 15 6 9 USART Baud Rate Generator register The Baud Rate Generator is a simple 16 bit integer divider controlled by the BRG register The BRG register contains the value used to divide the base clock in order to produce the clock used for USART internal operations A 16 bit value allows producing standard baud rates from 300 baud and lower at the highest frequency of the device up to 921 600 baud from a base clock as low as 14 7456 MHz Typically the baud rate clock is 16 times the actual baud rate This overclocking allows for centering the data sampling time within a bit cell and for noise reduction and detection by taking three samples of incoming data Details on how to select the right values for BRG can be found later in this chapter see Section 15 7 1 Remark If software needs to change t
168. 06 C004 USART2 bit description 0 disabled 1 enabled Remove clock frequency parameter from IAP commands Copy RAM to flash Erase page and Erase sector See Section 22 5 2 IAP commands IDLE bit renamed to MSTIDLE in Section 17 6 3 SPI Status register Update IAP description See Section 22 5 2 IAP commands Editorial updates Some register and bit names corrected 1 2 20130314 LPC800 user manual Modifications UM10601 Editorial updates Table 53 PLL configuration examples updated Register bit description of Table 105 Pattern match bit slice source register PMSRC address 0xA000 402C bit description updated Chapter 5 LPC800 Reduced power modes and Power Management Unit PMU updated Section 5 3 1 Low power modes the ARM Cortex MO core added Removed dependency on system frequency for flash access times in Table 227 Flash configuration register FLASHCFG address 0x4004 0010 bit description Instructions on how to prevent floating internal pins added See Section 6 3 Figure 31 I2C clocking updated Description of the NMISRC register updated See Section 4 6 26 NMI source selection register Section 16 3 1 I2C transmit receive in master mode added Chapter 14 LPC800 ARM Cortex SysTick Timer SysTick added Address offset of the DEVICE ID register corrected See Table 51 Device ID register DEVICE ID address 0x4004 83F8 bit description
169. 0601 8 7 1 8 7 2 Pin interrupts In this interrupt facility up to 8 pins are identified as interrupt sources by the Pin Interrupt Select registers PINTSELO 7 All registers in the pin interrupt block contain 8 bits corresponding to the pins called out by the PINTSELO 7 registers The ISEL register defines whether each interrupt pin is edge or level sensitive The RISE and FALL registers detect edges on each interrupt pin and can be written to clear and set edge detection The IST register indicates whether each interrupt pin is currently requesting an interrupt and this register can also be written to clear interrupts The other pin interrupt registers play different roles for edge sensitive and level sensitive pins as described in Table 106 Table 106 Pin interrupt registers for edge and level sensitive pins Name Edge sensitive function Level sensitive function IENR Enables rising edge interrupts Enables level interrupts SIENR Write to enable rising edge interrupts Write to enable level interrupts CIENR Write to disable rising edge interrupts Write to disable level interrupts IENF Enables falling edge interrupts Selects active level SIENF Write to enable falling edge interrupts Write to select high active CIENF Write to disable falling edge interrupts Write to select low active Pattern Match engine example Suppose the desired boolean pattern to be matched is IN1 1 IN2 IN2 IN3 IN6fe
170. 0x4 IOCONCLKDIV4 0 5 IOCONCLKDIV5 0x6 IOCONCLKDIV6 31 16 Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 77 of 370 NXP Semiconductors UM10601 6 5 7 2 register Chapter 6 LPC81x I O configuration IOCON Table 68 PIOO 2 register PIOO 2 address 0x4004 4018 bit description Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor 0b10 control 0x0 Inactive no pull down pull up resistor enabled 0 1 Pull down resistor enabled 0 2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 5 Reserved 0b001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled Remark This is not a true open drain mode 12 11 5 MODE Digital filter sample mode 0 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than one filter clock are rejected 0 2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 1543 CLK_DIV Select peripheral clock divider for input filter sampling clock 0 Value 0 7 is reser
171. 0x4004 4004 bit description Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor 0b10 control 0x0 Inactive no pull down pull up resistor enabled 0 1 Pull down resistor enabled 0 2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 5 Reserved 0b001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled Remark This is not a true open drain mode 12 11 5 MODE Digital filter sample mode 0 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than one filter clock are rejected 0 2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 1543 CLK_DIV Select peripheral clock divider for input filter sampling clock 0 Value 0 7 is reserved 0 0 IOCONCLKDIVO 0 1 IOCONCLKDIV1 0 2 IOCONCLKDIV2 0x3 IOCONCLKDIV3 0x4 IOCONCLKDIVA 0x5 IOCONCLKDIV5 0 6 IOCONCLKDIVE6 31 16 Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 73 of 370 NXP Semiconductors UM10601 6 5 3 PIOO 12 register Chapter
172. 1 lt received address lt SLVQUALO 7 1 31 8 Reserved Read value is undefined only zero should be written Monitor data register The read only MONRXDAT register provides information about events on the I C bus primarily to facilitate debugging of the 12C during application development All data addresses and data passing on the bus and whether these were acknowledged as well as Start and Stop events are reported The Monitor function must be enabled by the MONEN bit in the CFG register Monitor mode can be configured to stretch the 12C clock if data is not read from the MONRXDAT register in time to prevent it via the MONCLKSTR bit in the CFG register This can help ensure that nothing is missed but can cause the monitor function to be somewhat intrusive by potentially adding clock delays depending on software response time In order to improve the chance of collecting all Monitor information if clock stretching is not enabled Monitor data is buffered such that it is available until the end of the next piece of information from the 2C bus Table 201 Monitor data register MONRXDAT address 0x4005 0080 bit description Bit Symbol Value Description Reset value 7 0 MONRXDAT Monitor function Receiver Data This reflects every data 0 byte that passes on the 12C pins and adds indication of Start Repeated Start and data NACK 8 MONSTART Monitor Received Start 0 0 No detect The monitor function has not detec
173. 1 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 76 of 370 NXP Semiconductors U M1 0601 Chapter 6 LPC81x I O configuration IOCON 6 5 6 PIOO 3 register Table 67 PIOO_3 register PIOO 3 address 0x4004 4014 bit description Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor 0b10 control 0x0 Inactive no pull down pull up resistor enabled 0 1 Pull down resistor enabled 0 2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled Remark This is not a true open drain mode 12 11 5 MODE Digital filter sample mode 0 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than one filter clock are rejected 0 2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 1543 CLK_DIV Select peripheral clock divider for input filter sampling clock 0 Value 0x7 is reserved 0x0 IOCONCLKDIVO 0 1 IOCONCLKDIV1 0 2 IOCONCLKDIV2 0x3 IOCONCLKDIVS3
174. 1 in the corresponding PROD ENPTSn bit Setting a term as the final component has two effects 1 The interrupt request associated with this bit slice will be asserted whenever a match to that product term is detected 2 The next bit slice will start a new independent product term in the boolean expression i e an OR will be inserted in the boolean expression following the element controlled by this bit slice Table 105 Pattern match bit slice configuration register PMCFG address 0xA000 4030 bit description Bit Symbol Value Description Reset value 0 PROD EN Determines whether slice 0 is an endpoint 0 DPTSO 0 No effect Slice 0 is not an endpoint endpoint Slice 0 is the endpoint of a product term minterm Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true 1 PROD_EN Determines whether slice 1 is an endpoint 0 DPTS1 0 No effect Slice 1 is not an endpoint endpoint Slice 1 is the endpoint of a product term minterm Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true 2 PROD EN Determines whether slice 2 is an endpoint 0 DPTS2 0 No effect Slice 2 is not an endpoint endpoint Slice 2 is the endpoint of a product term minterm Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true 3 PROD_EN Determines whether slice 3 is an endpoint 0 DPTS3 0 No effect Slice 3 is not an endpoint endpoint Slice 3 is the endpoint of a product term minterm Pin inter
175. 10601 Chapter 3 LPC81x Nested Vectored Interrupt Controller NVIC Rev 1 6 2 April 2014 User manual 3 1 How to read this chapter The NVIC is identical on all LPC81x parts The SPI1 and USART2 interrupts are implemented on parts LPC812M101FDH20 and LPC812M101FDH16 only 3 2 Features e Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex M0 Tightly coupled interrupt controller provides low interrupt latency Controls system exceptions and peripheral interrupts The NVIC supports 32 vectored interrupts Four programmable interrupt priority levels with hardware priority level masking Software interrupt generation using the ARM exceptions SVCall and PendSV see Ref 3 Support for NMI e ARM Cortex MO Vector table offset register VTOR implemented 3 3 General description The Nested Vectored Interrupt Controller NVIC is an integral part of the Cortex M0 The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts 3 3 1 Interrupt sources Table 3 lists the interrupt sources for each peripheral function Each peripheral device may have one or more interrupt lines to the Vectored Interrupt Controller Each line may represent more than one interrupt source Interrupts with the same priority level are serviced in the order of their interrupt number See Ref 3 for a detailed description of the NVIC and the NVI
176. 17 Ox11 U2 TXD function assignment The value is the pin number to OXFF assigned to this function The following pins are available PIOO 0 0 to PIOO 17 Ox11 U2 RXD function assignment The value is the pin number to be OxFF assigned to this function The following pins are available PIOO 0 0 to PIOO 17 Ox11 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 128 of 370 NXP Semiconductors U M1 0601 9 5 4 9 5 5 9 5 6 UM10601 Chapter 9 LPC81x Switch matrix Pin assign register 3 Table 112 Pin assign register 3 PINASSIGN3 address 0x4000 COOC bit description Bit Symbol Description Reset value 7 0 U2 RTS O U2 RTS function assignment The value is the pin number to be OxFF assigned to this function The following pins are available PIOO 0 0 to PIOO 17 Ox11 15 8 U2 CTS I U2 CTS function assignment The value is the pin number to be OxFF assigned to this function The following pins are available PIOO 0 0 to PIOO 17 2 Ox11 23 16 U2 SCLK IO U2_SCLK function assignment The value is the pin number to be OXxFF assigned to this function The following pins are available PIOO 0 0 to PIOO 17 Ox11 31 24 SPIO SCK IO SPIO SCK function assignment The value is the pin number to OxFF be assigned to this function The following pins are available PIOO 0 0 to
177. 1x Boot ROM 3 If a valid user program is found then the execution control is transferred to it If a valid user program is not found the boot loader attempts to load a valid user program via the USART interface Remark The sampling of pin the ISP entry pin can be disabled through programming flash location 0x0000 02FC see Section 22 4 3 Code Read Protection CRP ROM based APIs Once the part has booted the user can access several APIs located in the boot ROM to access the flash memory optimize power consumption and operate the USART 12C peripherals The structure of the boot ROM APIs is shown in Figure 43 Ptr to ROM Flash IAP Ox1FFF 1FFO Ptr to ROM Driver table Ox1FFF 1FF8 0x0 0x4 0x8 0xC 0x10 0x14 0x24 ROM Driver Table Ptr to Device Table 0 Reserved Ptr to Device Table 1 Reserved Ptr to Device Table 2 Reserved Ptr to Power profiles function table Ptr to Device Table 4 Reserved Device 3 Power profiles API function table Device 5 Ptr to I2C driver routine function table Ptr to UART driver routine function table Fig 43 Boot ROM structure 2C driver routines function table Device 9 UART driver routines function table All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014
178. 2014 74 of 370 NXP Semiconductors UM10601 6 5 4 PIOO 5 register Chapter 6 LPC81x I O configuration IOCON Table 65 PIOO_5 register PIOO 5 address 0x4004 400C bit description Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor 0b10 control 0x0 Inactive no pull down pull up resistor enabled 0 1 Pull down resistor enabled 0 2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 5 Reserved 0b001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled Remark This is not a true open drain mode 12 11 5 MODE Digital filter sample mode 0 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than one filter clock are rejected 0 2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 1543 CLK_DIV Select peripheral clock divider for input filter sampling clock 0 Value 0 7 is reserved 0 0 IOCONCLKDIVO 0 1 IOCONCLKDIV1 0 2 IOCONCLKDIV2 0x3 IOCONCLKDIV3 0x4 IOCONCLKDIVA 0x5 IOCONCLKDIV5 0 6 IOCONCLKDIVE6 31 16 Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers
179. 24 LPC81x I2C bus ROM API 2 Enable the two pins required for the SCL and SDA outputs of the I2C peripheral 3 Allocate RAM area for dedicated use of the I2C ROM Driver After the I2C block is configured the I2C ROM driver variables have to be set up Initialize pointer to the I2C API function table Declare the PARAM and RESULT struct Declare Error Code struct Declare the transmit and receive buffer If interrupts are used then additional driver variables have to be set up Declare the l2C_CALLBK_T type Declare callback functions Declare I2C ROM Driver ISR within the 12C ISR Enable 12C interrupt U gt I2C Master mode set up The I2C ROM Driver support polling and interrupts In the master mode 7 bit and 10 bit addressing are supported The setup is as follows 1 Allocate SRAM for the I2C ROM Driver by making a call to the i2C get mem size function 2 Create the I2C handle by making a call to the i2c_setup function 3 Set the 12 operating frequency by making a call to the i2c set bitrate function size in bytes LPC I2CD API i2c get mem size i2c handle LPC I2CD API i2c setup LPC I2C BASE uint32 t amp I2C Handle 0 error code LPC I2CD API i2c set bitrate I2C HANDLE T i2c handle PCLK in Hz bps in hz I2C Slave mode set up The I2C ROM Driver support polling and interrupts in the slave mode In the slave mode only 7 bit addressing is suppo
180. 24 and Section 10 6 25 Table 132 SCT bidirectional output control register OUTPUTDIRCTRL address 0x5000 4054 bit description Bit Symbol Value Description Reset value 1 0 SETCLRO Set clear operation on output 0 Value 0x3 is reserved Do not program this value 0 0x0 Any Set and clear do not depend on any counter 0 1 L counting down Set and clear are reversed when counter L or the unified counter is counting down 0 2 counting down Set and clear are reversed when counter is counting down Do not use if UNIFY 1 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 146 of 370 NXP Semiconductors U M1 0601 Chapter 10 LPC81x SCTimer PWM SCT Table 132 SCT bidirectional output control register OUTPUTDIRCTRL address 0x5000 4054 bit description Bit Symbol Value Description Reset value 3 2 SETCLR1 Set clear operation on output 1 Value 0x3 is reserved Do not program this value 0 0x0 Any Set and clear do not depend on any counter 0 1 L counting down Set and clear are reversed when counter L or the unified counter is counting down 0 2 counting down Set and clear are reversed when counter is counting down Do not use if UNIFY 1 5 4 SETCLR2 Set clear operation on output 2 Value 0x3 is reserved Do not program this value 0 0x0 Any Set and clear do not depend on any counter 0 1
181. 286 SPIO 0x4005 C024 SPI1 bit description 245 Table 252 UART ISP Compare command 286 Table 214 SPI Interrupt Status register INTSTAT addresses Table 253 UART ISP ReadUID command 286 0x4005 8028 SPIO 0x4005 C028 SPI1 bit Table 254 UART ISP Read CRC checksum command 287 descriptiori 22e suu i Rea ERE RE 245 Table 255 UART ISP Return Codes Summary 287 Table 215 SPI mode 5 247 Table 256 IAP Command Summary 289 Table 216 Analog comparator pin description 255 Table 257 IAP Prepare sector s for write operation Table 217 Register overview Analog comparator base command ike ex ede Ideen 290 address 0x4002 4000 257 Table 258 IAP Copy RAM to flash command 291 Table 218 Comparator control register CTRL address Table 259 IAP Erase Sector s command 291 0x4002 4000 bit description 257 Table 260 IAP Blank check sector s command 292 Table 219 Voltage ladder register LAD address 0x4002 Table 261 IAP Read Part Identification command 292 4004 bit description 259 Table 262 IAP Read Boot Code version number Table 220 Register overview CRC engine base address 292 0 5000 0000 262 Table 263 IAP Compare command 293 Table 221 CRC mode register MODE address 0x5000 Tab
182. 2C function assignment The value is the pin OxFF number to be assigned to this function The following pins are available PIOO 0 0 to PIOO 17 0x11 15 8 ACMP ACMP function assignment The value is the pin OxFF number to be assigned to this function The following pins are available PIOO 0 0 to PIOO 17 0x11 23 16 CLKOUT O CLKOUT function assignment The value is the pin OxFF number to be assigned to this function The following pins are available 0 0 to PIOO 17 0x11 31 24 GPIO INT BMAT GPIO INT BMAT function assignment The value is the OxFF pin number to be assigned to this function The following pins are available PIOO 0 2 0 to PIOO 17 2 Ox11 9 5 10 Pin enable register 0 Table 118 Pin enable register 0 PINENABLEO address 0x4000 C1C0 bit description Bit Symbol Value Description Reset value 0 ACMP l1 EN 1 ACMP 12 EN 2 SWCLK EN 3 SWDIO EN UM10601 Enables fixed pin function Writing a 1 deselects the function and any movable function can be assigned to this pin By default the fixed pin function is deselected and GPIO is assigned to this pin 0 Enable ACMP 11 This function is enabled on pin 0 Disable ACMP 11 GPIO function PIOO 0 default or any other movable function be assigned to pin PIOO 0 Enables fixed pin function Writing a 1 deselects the function and any movable function can be assigned to this pin By default the fixed pin function
183. 2M101JDH16 and the corresponding switch matrix select bits are reserved for all other parts Flexible assignment of digital peripheral functions to pins Enable disable of analog functions 9 3 Basic configuration UM10601 Once configured no clocks are needed for the switch matrix to function The system clock is needed only to write to or read from the pin assignment registers After the switch matrix is configured disable the clock to the switch matrix block in the SYSAHBCLKCTRL register Before activating a peripheral or enabling its interrupt use the switch matrix to connect the peripheral to external pins The boot loader assigns the SWD functions to pins PIOO 2 and PIOO 3 If the user code disables the SWD functions through the switch matrix to use the pins for other functions the SWD port is disabled Remark For the purpose of programming the pin functions through the switch matrix every pin except the power and ground pins is identified in a package independent way by its GPIO port pin number All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 121 of 370 NXP Semiconductors U M1 0601 Chapter 9 LPC81x Switch matrix 9 3 1 Connect an internal signal to a package pin 16 gt PIOO 17 PIOO 14 PIOO 13 PIOO I1 TDO F g M disable XTALIN PIOO 12 PIOO_6 VDDCMP PINENABLEO bi
184. 3 4 to 0 This is the default Set a match value 1 2 4 5 L in each register The match 0 register serves as an automatic limit event that resets the counter without using an event To enable the automatic limit set the AUTOLIMIT bit in the CONFIG register Set a match reload value RELOADO 1 2 3 4 L in each register same as the match value in this example Set COMBMODE 0x1 Event 0 uses match condition only Set MATCHSEL 1 Select match value of match register 1 The match value of MAT1 is associated with event 0 Set COMBMODE 0x1 Event 1 uses match condition only Set MATCHSEL 2 Select match value of match register 2 The match value of MAT2 is associated with event 1 NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 162 of 370 NXP Semiconductors UM10601 Table 147 SCT configuration example Chapter 10 LPC81x SCTimer PWM SCT Configuration Define when event 2 occurs Define how event 2 changes the state Define when event 3 occurs Define when event 4 occurs Define when event 5 occurs Define how event 5 changes the state Define by which events output 0 is set Define by which events output 0 is cleared Configure states in which event 0 is enabled Configure states in which event 1 is enabled Configure states in which event 2 is enabled Configure states in which event 3 is enabled Configure states in which
185. 39 0x110 REGMODO to REGMODE4 1 CAP_LO to CAP_L4 0x100to SCT capture register of capture channel 0 to 4 Table 139 0x110 low counter 16 bit REGMODO L to REGMODE4 L 1 CAP to CAP H4 0x102to SCT capture register of capture channel 0 to 4 Table 139 0x13E high counter 16 bit REGMODO H to REGMODE4_H 1 MATCHRELO to R W 0x200 to SCT match reload value register 0 to 4 0x0000 0000 Table 140 MATCHREL4 0x210 REGMODO 0 to REGMODE4 0 MATCHREL_LO to R W 0x200 to SCT match reload value register 0 to 4 low Table 140 MATCHREL L4 0x210 counter 16 bit REGMODO L 0 to REGMODE4 L 0 MATCHREL to R W 0x202 to SCT match reload value register 0 to 4 high Table 140 MATCHREL_H4 0x212 counter 16 bit REGMODO 0 to REGMODE4 0 CAPCTRLO to 0x200 to SCT capture control register 0 to 4 REGMODO 0x0000 0000 Table 141 CAPCTRL4 0x210 1 to REGMODE4 1 CAPCTRL_LO to 0 200 to SCT capture control register 0 to 4 low counter Table 141 CAPCTRL_L4 0x210 16 bit REGMODO L 1 to REGMODE4 L 1 CAPCTRL_HO to 0x202 to SCT capture control register O to 4 high counter Table 141 CAPCTRL_H4 0x212 16 bit REGMODO 1 to REGMODE4 1 EVO STATE R W 0x300 SCT event 0 state register 0x0000 0000 Table 142 EVO CTRL R W 0x304 SCT event 0 control register 0x0000 0000 Table 143 EV1_STATE R W 0x308 SCT event 1 state register 0x0000 0000 Table 142 EV1_CTRL R W 0x30C SCT event 1 control register 0x0000 0000 Table 143 EV2_STATE R W 0x310 SCT event 2 state registe
186. 4 All rights reserved User manual Rev 1 6 2 April 2014 292 of 370 NXP Semiconductors UM10601 UM10601 Chapter 22 LPC81x Flash ISP and IAP programming 22 5 2 7 Compare lt address1 gt lt address2 gt no of bytes gt IAP Table 263 IAP Compare command Command Input Status code Result Description Compare Command code 56 decimal ParamO DST Starting flash or RAM address of data bytes to be compared This address should be a word boundary Param1 SRC Starting flash or RAM address of data bytes to be compared This address should be a word boundary Param2 Number of bytes to be compared should be a multiple of 4 CMD_SUCCESS COMPARE_ERROR COUNT_ERROR Byte count is not a multiple of 4 ADDR_ERROR ADDR_NOT_MAPPED Result0 Offset of the first mismatch if the Status Code is COMPARE ERROR This command is used to compare the memory contents at two locations All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 293 of 370 NXP Semiconductors UM10601 Chapter 22 LPC81x Flash ISP and IAP programming 22 5 2 8 Reinvoke ISP IAP Table 264 IAP Reinvoke ISP Command Input Status code Result Description Compare Command code 57 decimal None None This command is used to invoke the bootloader in ISP mode It maps boot vectors sets PCLK CCL
187. 4 SPI Delay register 0 Table 205 STAT R W 0x008 SPI Status Some status flags canbe 0 0102 Table 206 cleared by writing a 1 to that bit position INTENSET R W Ox00C Interrupt Enable read and Set 0 Table 207 complete value may be read from this register Writing a 1 to any implemented bit position causes that bit to be set INTENCLR W 0x010 SPI Interrupt Enable Clear Writing a 1 NA Table 208 to any implemented bit position causes the corresponding bit in INTENSET to be cleared RXDAT R 0x014 SPI Receive Data NA Table 209 TXDATCTL R W 0x018 SPI Transmit Data with Control 0 Table 210 TXDAT R W 0x01C SPI Transmit Data 0 Table 211 TXCTL R W 0x020 Transmit Control 0 Table 212 DIV R W 0x024 clock Divider 0 Table 213 INTSTAT R 0x028 Interrupt Status 0x02 Table 214 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 236 of 370 NXP Semiconductors U M1 0601 Chapter 17 LPC81x SPIO 1 17 6 1 SPI Configuration register The CFG register contains information for the general configuration of the SPI Typically this information is not changed during operation Some configurations such as CPOL CPHA and LSBF should not be made while the SPI is not fully idle See the description of the Master idle status bit MSTIDLE in Table 206 for more information Remark If the interface is re configured from Maste
188. 5 bit 5 15 6 Reserved 21 16 STOPMSK H If bit n is one event n sets the STOP H bit in the CTRL register 0 event 0 bit 16 event 1 bit 17 event 5 bit 21 31 22 Reserved SCT start condition register If UNIFY 1 in the CONFIG register only the _L bits are used If UNIFY 0 in the CONFIG register this register can be written to as two registers START L and START Both the L and registers can be read or written individually or in a single 32 bit read or write operation The bits in this register select which events if any clear the STOP bit in the Control register Since no events can occur when HALT is 1 only software can clear the HALT bit by writing the Control register Table 126 SCT start condition register START address 0x5000 4014 bit description Bit Symbol Description Reset value 5 0 STARTMSK L If bit n is one event n clears the STOP L bit in the CTRL 0 register event 0 bit 0 event 1 bit 1 event 5 bit 5 15 6 Reserved 21 16 STARTMSK H If bit n is one event n clears the STOP H bit in the CTRL 0 register event 0 bit 16 event 1 bit 17 event 5 bit 21 31 22 Reserved SCT counter register If UNIFY 1 in the CONFIG register the counter is a unified 32 bit register and both the Land H bits are used If UNIFY 0 in the CONFIG register this register can be written to as two registers COUNT L and COUNT H Both the L and H registers can be read
189. 5 ICP_PININT6 ICP_PININT7 Function Interrupt pending clear Reserved Reserved Interrupt pending clear Interrupt pending clear Interrupt pending clear Interrupt pending clear Interrupt pending clear Interrupt pending clear Interrupt pending clear Interrupt pending clear Reserved Interrupt pending clear Interrupt pending clear Interrupt pending clear Interrupt pending clear Interrupt pending clear Interrupt pending clear Interrupt pending clear Interrupt pending clear Reset value 0 0 3 4 5 Interrupt Active Bit Register 0 The IABRO register is a read only register that allows reading the active state of the peripheral interrupts Use this register to determine which peripherals are asserting an interrupt to the NVIC and may also be pending if there are enabled The bit description is as follows for all bits in this register Write n a Read 0 indicates that the interrupt is not active 1 indicates that the interrupt is active Table 9 Interrupt Active Bit Register 0 IABRO address 0xE000 E300 bit description Bit ON Oa fF WN O UM10601 Symbol IAB_SPIO IAB_SPI1 IAB UARTO IAB UART1 IAB UART2 IAB I2C All information provided in this document is subject to legal disclaimers Function Interrupt active Interrupt active Reserved Interrupt active Interrupt active Interrupt active Reserved Reserved
190. 6 IAP Command Summary IAP Command Command Code Described in Prepare sector s for write operation 50 decimal Table 257 Copy RAM to flash 51 decimal Table 258 Erase sector s 52 decimal Table 259 Blank check sector s 53 decimal Table 260 Read Part ID 54 decimal Table 261 Read Boot code version 55 decimal Table 262 Compare 56 decimal Table 263 Reinvoke ISP 57 decimal Table 264 Read UID 58 decimal Table 265 Erase page 59 decimal Table 266 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 289 of 370 NXP Semiconductors U M1 0601 Chapter 22 LPC81x Flash ISP and IAP programming Command Parameter Array command param O0 command param 1 command param 2 command param n Status Result Array status result 0 status result 1 status result 2 status result n Command code Param 0 Param 1 ARM REGISTER ARM REGISTER r1 Param n Status code Result 0 Result 1 Result n Fig 45 IAP parameter passing 22 5 2 1 Prepare sector s for write operation IAP This command makes flash write erase operation a two step process Table 257 IAP Prepare sector s for write operation command Command Prepare sector s for write operation Input Command code 50 decimal Param0 Start Sector Number Param1 End Sector Number sh
191. 6 LPC81x I O configuration IOCON Table 64 12 register PIOO 12 address 0x4004 4008 bit description Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor 0b10 control 0x0 Inactive no pull down pull up resistor enabled 0 1 Pull down resistor enabled 0 2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 5 Reserved 0b001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled Remark This is not a true open drain mode 12 11 5 MODE Digital filter sample mode 0 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than one filter clock are rejected 0 2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 1543 CLK_DIV Select peripheral clock divider for input filter sampling clock 0 Value 0 7 is reserved 0 0 IOCONCLKDIVO 0 1 IOCONCLKDIV1 0 2 IOCONCLKDIV2 0x3 IOCONCLKDIV3 0x4 IOCONCLKDIVA 0x5 IOCONCLKDIV5 0 6 IOCONCLKDIVE6 31 16 Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April
192. 7 1 5 1 ARM Cortex M0 core configuration 9 Chapter 2 LPC81x Memory mapping 2 1 How to read this chapter 10 2 2 1 Memory 11 2 2 General 10 222 Micro Trace Buffer 11 Chapter 3 LPC81x Nested Vectored Interrupt Controller NVIC 3 1 3 2 3 3 3 3 1 3 3 2 3 3 3 3 4 3 4 1 3 4 2 How to read this chapter 12 Features sisi sins ser RR RR Rs 12 General description 12 Interrupt 12 Non Maskable Interrupt NMI 14 Vector table offset 14 Register description 15 Interrupt Set Enable Register 0 register 15 Interrupt clear enable register 0 16 3 4 3 3 4 4 3 4 5 3 4 6 3 4 7 3 4 8 3 4 9 3 4 10 3 4 11 Chapter 4 LPC81x System configuration SYSCON Interrupt Set Pending Register 0 register 17 Interrupt Clear Pending Register 0 register 18 Interrupt Active Bit Register 0 19 Interrupt Priority Register O 20 Interrupt Priority Register1 20 Interrupt Priority Register 2 21 Interrupt Priority Register 3 21 Interrupt Priority Register 6 22 Interrupt Priority Register 7 22 4 1 How to read this chapter 23 4 6 16 CLKOUT clock sourc
193. 70 NXP Semiconductors U M1 0601 UM10601 Chapter 17 LPC81x SPIO 1 17 7 6 Data stalls A stall for Master transmit data can happen in modes 0 and 2 when SCK cannot be returned to the rest state until the MSB of the next data frame can be driven on MOSI In this case the stall happens just before the final clock edge of data if the next piece of data is not yet available A stall for Master receive can happen when a receiver overrun would otherwise occur if the transmitter was not stalled In modes 0 and 2 this occurs if the previously received data is not read before the end of the next piece of is received This stall happens one clock edge earlier than the transmitter stall In modes 1 and 3 the same kind of receiver stall can occur but just before the final clock edge of the received data Also a transmitter stall will not happen in modes 1 and 3 because the transmitted data is complete at the point where a stall would otherwise occur so it is not needed Stalls are reflected in the STAT register by the Stalled status flag which indicates the current SPI status All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 252 of 370 NXP Semiconductors U M1 0601 Chapter 17 LPC81x SPIO 1 Transmitter stall 0 Frame delay 0 Pre delay 0 Post delay 0 2 clock stall Mode 0 CPOL 0 SCK fo
194. 86 I2C Status register STAT address 0x4005 0004 bit description continued Bit Symbol Value Description Reset Access value 24 EVENTTIMEOUT Event Time out Interrupt flag Indicates when the time between 0 W1 events has been longer than the time specified by the TIMEOUT register Events include Start Stop and clock edges The flag is cleared by writing a 1 to this bit No time out is created when the 12C bus is idle 0 No time out 12C bus events have not caused a time out Event time out The time between I C bus events has been longer than the time specified by the 12C TIMEOUT register 25 SCLTIMEOUT SCL Time out Interrupt flag Indicates when SCL has remained low 0 W1 longer than the time specific by the TIMEOUT register The flag is cleared by writing a 1 to this bit 0 No time out SCL low time has not caused a time out Time out SCL low time has caused a time out 31 26 Reserved Read value is undefined only zero should be written NA NA Table 187 Master function state codes MSTSTATE MstState Description Actions 0 Idle The Master function is available to be used for a new Send a Start or disable MSTPENDING transaction interrupt if the Master function is not needed currently 1 Received data is available Master Receiver mode Address Read data and either continue send a Stop or plus Read was previously sent and Acknowledged by slave send a Repeated Start 2 Data can be transmitted Master Transmitte
195. AHBCLKDIV is set to one see Table 29 Table 52 PLL configuration examples PLL input Main clock bits M PSEL bits FCCO SYSAHBCLKDIV System clock Fclkout Table 20 divider Table 20 divider frequency clock sys plicikin value value Fclkin 12 MHz 60 MHz 00100 binary 5 01 binary 2 240MHz 2 30 MHz 12 MHz 24 MHz 00001 binary 2 10 binary 4 192MHz 1 24 MHz UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 53 of 370 NXP Semiconductors U M1 0601 Chapter 4 LPC81x System configuration SYSCON 4 7 4 4 2 PLL Power down mode In this mode the internal current reference will be turned off the oscillator and the phase frequency detector will be stopped and the dividers will enter a reset state While in PLL Power down mode the lock output will be low to indicate that the PLL is not in lock When the PLL Power down mode is terminated by SYSPLL_PD bit to zero in the Power down configuration register Table 49 the PLL will resume its normal operation and will make the lock signal high once it has regained lock on the input clock UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 54 of 370 UM10601 Chapter 5 LPC81x Reduced power modes and Power Management Unit PMU Rev 1 6 2 April 2014 User
196. ALUE 1 and the timer starts to count down When the timer reaches 0 an interrupt is generated and the timer stops and enters the idle state While the timer is running in the one shot interrupt mode you can perform the following actions e Update the INTVALn register with a new time interval value gt 0 and set the LOAD bit to 1 The timer immediately reloads the new time interval and starts counting down from the new value No interrupt is generated when the TIME_INTVALn register is updated e Write a 0 to the INTVALn register and set the LOAD bit to 1 The timer immediately stops counting and moves to the idle state No interrupt is generated when the INTVALn register is updated One shot bus stall mode The one shot bus stall mode stalls the bus interface for IVALUE 3 cycles of the system clock For the Cortex M0 this mode effectively stops all CPU activity until the MRT has finished counting down to zero At the end of the count down no interrupt is generated instead the bus resumes its transactions The bus stall mode allows to halt an application for a predefined amount of time and then resume as opposed to creating a software loop or polling a timer Since in bus stall mode there are no bus transactions while the MRT is counting down the CPU consumes a minimum amount of power during that time Typically this mode can be used when an application must be idle for a short time in the order of us or 10 to 50 clock cycles f
197. April 2014 195 of 370 NXP Semiconductors UM10601 Chapter 15 LPC81x USARTO 1 2 Table 174 USART Control register CTL address 0x4006 4004 USARTO 0x4006 8004 USART1 0x4006 C004 USART2 bit description Bit Symbol 1 TXBRKEN 2 ADDRDET 5 3 6 TXDIS 9 CLRCC 31 10 Value Description Reset Value Reserved Read value is undefined only zero should be NA written Break Enable 0 Normal operation Continuous break is sent immediately when this bit is set and remains until this bit is cleared A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled TXDIS in CTL is set and then waiting for the transmitter to be disabled TXDISINT in STAT 1 before writing 1 to TXBRKEN Enable address detect mode 0 Disabled The USART presents all incoming data Enabled The USART receiver ignores incoming data that does not have the most significant bit of the data typically the 9th bit 1 When the data MSB bit 1 the receiver treats the incoming data normally generating a received data interrupt Software can then check the data to see if this is an address that should be handled If it is the ADDRDET bit is cleared by software and further incoming data is handled normally Reserved Read value is undefined only zero should be NA written Transmit Disable 0 Not disabled USART transmitter is not disabled Disabled USART trans
198. April 2014 300 of 370 NXP Semiconductors U M1 0601 UM10601 23 4 1 3 23 4 2 Chapter 23 LPC81x Power profile ROM driver Param3 system PLL lock time out It should take no more than 100 us for the system PLL to lock if a valid configuration is selected If Param3 is zero set pll will wait indefinitely for the PLL to lock A non zero value indicates how many times the code will check for a successful PLL lock event before it returns PLL NOT LOCKED In this case the PLL settings are unchanged and is returned as Result1 Remark The time it takes the PLL to lock depends on the selected PLL input clock source IRC system oscillator and its characteristics The selected source can experience more or less jitter depending on the operating conditions such as power supply and or ambient temperature This is why it is suggested that when a good known clock source is used and a PLL NOT LOCKED response is received the set pll routine should be invoked several times before declaring the selected PLL clock source invalid Hint setting Param3 equal to the system PLL frequency Hz divided by 10000 will provide more than enough PLL lock polling cycles set power This routine configures the device s internal power control settings according to the calling arguments The goal is to reduce active power consumption while maintaining the feature of interest to the application close to its optimum Remark Use the set powe
199. BLED Description This command is used to read data from RAM or flash memory This command is blocked when code read protection is enabled Example R 268435456 4 lt CR gt lt LF gt reads 4 bytes of data from address 0x1000 0000 Prepare sector s for write operation start sector number end sector number This command makes flash write erase operation a two step process Table 244 UART ISP Prepare sector s for write operation command Command P Input Start Sector Number End Sector Number Should be greater than or equal to start sector number Return Code CMD SUCCESS BUSY INVALID SECTOR PARAM ERROR Description This command must be executed before executing Copy RAM to flash or Erase Sector s command Successful execution of the Copy RAM to flash or Erase Sector s command causes relevant sectors to be protected again The boot block can not be prepared by this command To prepare a single sector use the same Start and End sector numbers Example P 0 0 lt CR gt lt LF gt prepares the flash sector 0 Copy RAM to flash Flash address gt RAM address gt no of bytes gt When writing to the flash the following limitations apply 1 The smallest amount of data that can be written to flash by the copy RAM to flash command is 64 byte equal to one page 2 One page consists of 16 flash words lines and the smallest amount that can be modified per flash write is one flash word one line T
200. C interface as a Master or a Slave The software routines do not implement arbitration to make a Master switch to a Slave mode in the midst of a transmission Although multi master arbitration is not implemented in these 12C drivers it is possible to use them in a system design with more than one master If the flag returned from the driver indicates that the message was not successful due to loss of arbitration the application just resends the message UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 306 of 370 NXP Semiconductors U M1 0601 Chapter 24 LPC81x I2C bus ROM API 12 driver routines function table i2c_isr_handler Ptr to ROM Driver table i2c_master_transmit_poll Ox1FFF 1FF8 5 i2c_get_status ROM Driver Table 0x00 0x04 0x08 0x0C Ptr to Device Table 3 0x10 Ptr to Device Table 4 0x14 Ptr to I2C driver routines Ptrto Device Tablen Fig 49 I2C bus driver routines pointer structure 24 4 API description The 12C API contains functions to configure the I2C and send and receive data in master and slave modes Table 272 12 API calls API call Description Reference void i2c isr handler IBC HANDLE T I2C ROM Driver interrupt service Table 273 routine ErrorCode t i2c master transmit poll l2C HANDLE I2C PARAM 12C Master Trans
201. C register description Table 3 Connection of interrupt sources to the NVIC Interrupt Description Flags number 0 SPIO_IRQ SPIO interrupt See Table 207 SPI Interrupt Enable read and Set register INTENSET addresses 0x4005 800C SP10 0x4005 SPI1 bit description 1 SPI1_IRQ SPI1 interrupt Same as SPIO_IRQ 2 Reserved UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 12 of 370 NXP Semiconductors U M1 0601 Chapter 3 LPC81x Nested Vectored Interrupt Controller NVIC Table 3 Connection of interrupt sources to the NVIC Interrupt Name Description Flags number 3 UARTO IRQ USARTO interrupt See Table 176 USART Interrupt Enable read and set register INTENSET address 0x4006 400C USARTO 0x4006 800C USART1 0x4006 C00C USART2 bit description 4 UART1 IRQ USART1 interrupt Same as UARTO IRQ 5 UART2 IRQ USART2 interrupt Same as UARTO IRQ 6 Reserved 7 Reserved 8 laco IRQ 12 0 interrupt See Table 190 Interrupt Enable Clear register INTENCLR address 0x4005 000C bit description 9 SCT IRQ State configurable timer EVFLAG SCT event interrupt 10 MRT IRQ Multi rate timer interrupt Global MRT interrupt GFLAGO GFLAG1 GFLAG2 GFLAG3 11 CMP_IRQ Analog comparator interrupt COMPEDGE rising falling or both edges can set the bit 12 WDT_IRQ Win
202. CFG address 0x4005 0000 bit description Table 186 I2C Status register STAT address 0x4005 0004 bit description Table 193 12C Interrupt Status register INTSTAT address 0x4005 0018 bit description Table 189 Interrupt Enable Set and read register INTENSET address 0x4005 0008 bit description Table 190 Interrupt Enable Clear register INTENCLR address 0x4005 000C bit description Table 191 time out register TIMEOUT address 0x4005 0010 bit description Table 192 12C Clock Divider register CLKDIV address 0x4005 0014 bit description Master function registers Table 194 Master Control register MSTCTL address 0x4005 0020 bit description Table 195 Master Time register MSTTIME address 0x4005 0024 bit description Table 196 Master Data register MSTDAT address 0x4005 0028 bit description Slave function registers Table 197 Slave Control register SLVCTL address 0x4005 0040 bit description Table 197 Slave Control register SLVCTL address 0x4005 0040 bit description Table 199 Slave Address registers SLVADR 0 3 address 0x4005 0048 SLVADRO to 0x4005 0054 SLVADR3 bit description Table 200 Slave address Qualifier 0 register SLVQUALO address 0x4005 0058 bit description Monitor function register Table 201 Monitor data register MONRXDAT address 0x4005 0080 bit description See Section 29 2 Code examples
203. Connect an internal signal to a package pin 122 a Es assign e ca 9 3 2 Enable an analog input or other special massign register CEP MN 3 T MM 122 9 5 6 Pin assign register5 129 pa 9 5 7 Pin assign register6 130 9 4 General description 123 958 Pin assign register 7 130 9 4 1 Movable functions 125 9 5 9 Pin assign register 8 131 9 4 2 Switch matrix register interface 126 9 5 10 Pin enable register O 131 9 5 Register description 127 Chapter 10 LPC81x SCTimer PWM SCT 10 1 How to read this chapter 133 10 6 10 SCT match capture registers mode register 145 10 2 133 10 6 11 SCT output 146 10 3 Basic 133 10 6 12 SCT bidirectional output control register 146 10 3 1 Use the SCTimer PWM as a simple timer 133 10 6 13 SCT conflict resolution register 147 d 10 6 14 SCT flag enable register 148 10 4 Pin 134 10 6 15 event flag register 148 10 5 General description 134 10 6 16 SCT conflict enable register 148 10 6 Register description 136 10 6 17 SCT conflict flag register 149 10 6 1 SCT configuratio
204. Control register This register controls the 0 Table 151 MRT1 modes STAT1 R W 0x1C MRT1 Status register 0 Table 152 INTVAL2 R W 0x20 MRT2 Time interval value register This value is 0 Table 149 loaded into the TIMER register TIMER2 R W 0x24 MRT2 Timer register This register reads the value Ox7FFF FFFF Table 150 of the down counter CTRL2 R W 0x28 MRT2 Control register This register controls the 0 Table 151 MRT2 modes STAT2 R W 0x2C MRT2 Status register 0 Table 152 INTVAL3 R W 0x30 MRT3 Time interval value register This value is 0 Table 149 loaded into the TIMERS register TIMER3 R W 0x34 MRTS3 Timer register This register reads the value Ox7FFF FFFF Table 150 of the down counter CTRL3 R W 0x38 Control register This register controls the 0 Table 151 MRT modes STAT3 R W Ox3C MRTS Status register 0 Table 152 IDLE CH R OxF4 Idle channel register This register returns the 0 Table 153 number of the first idle channel IRQ_FLAG R W OxF8 Global interrupt flag register 0 Table 154 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 167 of 370 NXP Semiconductors U M1 0601 Chapter 11 LPC81x Multi Rate Timer MRT 11 6 1 Time interval register This register contains the MRT load value and controls how the timer is reloaded The load value is IVALUE 1 Table 149 Time interval register INTVAL 0 3 a
205. DIP8 PIOO 0 to PIOO 5 TSSOP16 XSON16 PIOO 0 to PIOO 13 TSSOP20 PIOO 0 to PIOO 17 SOP20 PIOO 0 to PIOO 17 e GPIO port registers are located on the ARM Cortex MO I O port for fast access The ARM Cortex MO I O port supports single cycle access GPIO ports GPIO pins can be configured as input or output by software All GPIO pins default to inputs at reset Pininterrupt registers allow pins to be sensed and set individually 7 3 Basic configuration For the GPIO port registers enable the clock to the GPIO port registers in the SYSAHBCLKCTRL register Table 30 bit 6 7 4 Pin description All GPIO functions are fixed pin functions The switch matrix assigns every GPIO port pin to one and only one pin on the LPC81x package By default the switch matrix connects all package pins except supply and ground pins to their GPIO port pins The pin description table see Table 305 shows how the GPIO port pins are assigned to LPC81x package pins 7 5 General description UM10601 The GPIO port registers can be used to configure each GPIO pin as input or output and read the state of each pin if the pin is configured as input or set the state of each pin if the pin is configured as output All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 90 of 370 NXP Semiconductors UM10601 Chapter 7 LPC81x G
206. DIV Select peripheral clock divider for input filter sampling clock 0 Value 0 7 is reserved 0 0 IOCONCLKDIVO 0 1 IOCONCLKDIV1 0 2 IOCONCLKDIV2 0x3 IOCONCLKDIV3 0x4 IOCONCLKDIVA 0x5 IOCONCLKDIV5 0 6 IOCONCLKDIVE6 31 16 Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 81 of 370 NXP Semiconductors U M1 0601 Chapter 6 LPC81x I O configuration IOCON 6 5 11 15 register Table 72 PIOO_15 register PIOO 15 address 0x4004 4028 bit description Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor 0b10 control 0x0 Inactive no pull down pull up resistor enabled 0 1 Pull down resistor enabled 0 2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0b001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled Remark This is not a true open drain mode 12 11 S MODE Digital filter sample mode 0 0x0 Bypass input filter 0x1 1 clock cycle Input pulses shorter than one filter clock are rejected 0x2 2 clock cycles Input pulses shorter than two filter clocks are rejected
207. DRUNCFG register See Table 49 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 31 of 370 NXP Semiconductors U M1 0601 4 6 6 Chapter 4 LPC81x System configuration SYSCON Table 22 System oscillator control register SYSOSCCTRL address 0x4004 8020 bit description Bit Symbol Value Description Reset value 0 BYPASS Bypass system oscillator 0x0 0 Disabled Oscillator is not bypassed 1 Enabled PLL input sys_osc_clk is fed directly from the XTALIN pin bypassing the oscillator Use this mode when using an external clock source instead of the crystal oscillator 1 FREQRANGE Determines oscillator frequency range 0x0 0 1 20 MHz frequency range 1 15 25 MHz frequency range 31 2 Reserved 0x00 Watchdog oscillator control register This register configures the watchdog oscillator The oscillator consists of an analog and a digital part The analog part contains the oscillator function and generates an analog clock Fclkana With the digital part the analog output clock Fclkana can be divided to the required output clock frequency wdt osc clk The analog output frequency Fclkana can be adjusted with the FREQSEL bits between 600 kHz and 4 6 MHz With the digital part Fclkana will be divided divider ratios 2 4 64 to wdt osc using the DIVSEL bits The output clock frequency of the watchdog osc
208. Definitions 351 Interrupt mode 345 2942 Interrupt 351 29 2 12 Slave read one byte from master 345 29 4 3 Transmit one byte of data 352 29 2 13 Slave write one byte to master 346 29 4 4 Receive one byte of data 352 29 2 14 Slave read one byte from master into 29 4 5 Transmit and receive one byte of data 352 5 346 2946 Loop back 10 bytes of data 352 29 2 15 Slave write one byte to master from 2947 Loop back 10 bytes of data using interrupts 352 347 Chapter 30 Supplementary information 30 1 lt 353 30 3 1 Definitions 354 30 2 1 lt 353 30 3 2 Disclaimers 354 30 3 Legal 354 3033 354 continued gt gt UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 369 of 370 NXP Semiconductors UM10601 30 4 30 5 Tables Figures Chapter 30 Supplementary information 30 6 Contes aca mcm ia do 362 Please be aware that important not
209. Determine how the event affects the system state In the EVn_CTRL registers up to 6 events one register per event set the new state value in the STATEV field for this event If the event is the highest numbered in the current state this value is either added to the existing state value or replaces the existing state value depending on the field STATELD Remark If there are higher numbered events in the current state this event cannot change the state If the STATEV and STATELD values are set to zero the state does not change 10 7 10 5 Miscellaneous options UM10601 e There are a certain selectable number of capture registers Each capture register can be programmed to capture the counter contents when one or more events occur Ifthe counter is in bidirectional mode the effect of set and clear of an output can be made to depend on whether the counter is counting up or down by writing to the OUTPUTDIRCTRL register 10 7 11 Run the SCT Configure the SCT see Section 10 7 10 Configure the SCT Write to the STATE register to define the initial state By default the initial state is state 0 To start the SCT write to the CTRL register Clear the counters Clear or set the STOP L and or STOP H bits Remark The counter starts counting once the STOP bit is cleared as well If the STOP bit is set the SCT waits instead for an event to occur that is configured to start the counter For e
210. E typedef void I2C HANDLE T After the definition of the handle the handle must be initialized with I2C base address and RAM reserved for the I2C ROM driver by making a call to the i2c_setup function The callback function type must be defined if interrupts for the I2C ROM driver are used typedef void I2C CALLBK T uint32 t err code uint32 t n The callback function will be called by the I2C ROM driver upon completion of a task when interrupts are used 24 4 22 PARAM and RESULT structure The I2C ROM driver input parameters consist of two structures a PARAM structure and RESULT structure The PARAM structure contains the parameters passed to the I2C ROM driver and the RESULT structure contains the results after the 12C ROM driver is called The PARAM structure is as follows typedef struct i2c parameters passed to ROM function uint32 t num bytes send uint32 t num bytes rec uint8 t buffer ptr send uint8 t buffer ptr rec UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 315 of 370 NXP Semiconductors UM1 0601 24 4 23 24 4 24 Chapter 24 LPC81x I2C bus ROM API I2C CALLBK T func pt callback function pointer uint8 t stop flag uint8 t dummy 3 required for word alignment I2C PARAM The RESULT structure is as follows typedef struct i2c R RESULTs struct resu
211. ECT LOGIC PINTSEL7 n 6 for the DIP8 package n 14 for the TSSOP16 XSON16 package n 18 for the TSSOP SOP20 packages Fig 7 Pin interrupt connections 8 5 2 Pattern match engine The pattern match feature allows complex boolean expressions to be constructed from the same set of eight GPIO pins that were selected for the GPIO pin interrupts Each term in the boolean expression is implemented as one slice of the pattern match engine A slice consists of an input selector and a detect logic The slice input selector selects one input from the available eight inputs with each input connected to a pin by the input s PINTSEL register The detect logic monitors the selected input continuously and creates a HIGH output if the input qualifies as detected Several terms can be combined to a minterm by designating a slice as an endpoint of the expression A pin interrupt for this slice is asserted when the minterm evaluates as true UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 98 of 370 NXP Semiconductors U M1 0601 Chapter 8 LPC81x Pin interrupts pattern match engine to IN7 from slice n 1 to INO tied HIGH for slice 0 slice n 1 A SYSCON slice endpoint configured PMCFG bit 1 PROD_ENDPTS all pins m PINTSELO DETECT NVIC pin interrupt n
212. FG address 0x4004 8234 bit description Bit Symbol Value Description Reset value 0 IRCOUT_PD IRC oscillator output wake up configuration 0 0 Powered 1 Powered down 1 IRC_PD IRC oscillator power down wake up configuration 0 0 Powered 1 Powered down 2 FLASH_PD Flash wake up configuration 0 0 Powered 1 Powered down 3 BOD_PD BOD wake up configuration 0 0 Powered 1 Powered down 4 Reserved 1 5 SYSOSC_PD Crystal oscillator wake up configuration 1 0 Powered 1 Powered down 6 WDTOSC_PD Watchdog oscillator wake up configuration 1 Changing this bit to powered down has no effect when the LOCK bit in the WWDT MOD register is set In this case the watchdog oscillator is always running 0 Powered 1 Powered down 7 SYSPLL_PD System PLL wake up configuration 1 0 Powered 1 Powered down 11 8 Reserved Always write these bits as 061101 0b1101 14 12 Reserved Always write these bits as 0b110 0b110 15 ACMP Analog comparator wake up configuration 1 0 Powered 1 Powered down 31 16 Reserved 0 Power configuration register The PDRUNCFG register controls the power to the various analog blocks This register can be written to at any time while the chip is running and a write will take effect immediately with the exception of the power down signal to the IRC To avoid glitches when powering down the IRC the IRC clock is automatically switched off at a clean point Therefore for the IRC a delay is possible before the power down state take
213. HSEL 4 HEVENT 5 OUTSEL 9 6 IOSEL 11 10 IOCOND 13 12 COMBMODE UM10601 Value Description Reset value Selects the Match register associated with this event if any A match can occur only 0 when the counter selected by the HEVENT bit is running Select L H counter Do not set this bit if UNIFY 1 0 L state Selects the L state and the L match register selected by MATCHSEL H state Selects the H state and the H match register selected by MATCHSEL Input output select 0 Input Selects the inputs elected by IOSEL Output Selects the outputs selected by IOSEL Selects the input or output signal associated with this event if any Do not select 0 input in this register if CLKMODE is 1x In this case the clock input is an implicit ingredient of every event IOSEL 0 selects pins CTIN 0 or CTOUT_O IOSEL selects pins CTIN or CTOUT_3 Selects the I O condition for event n The detection of edges on outputs lag the 0 conditions that switch the outputs by one SCT clock In order to guarantee proper edge state detection an input must have a minimum pulse width of at least one SCT clock period 0x0 LOW 0x1 Rise 0x2 Fall 0x3 Selects how the specified match and I O condition are used and combined Ox0 The event occurs when either the specified match or I O condition occurs 0 1 MATCH Uses the specified match only 0 2 Uses the specified I O condition only 0 3 AND The event o
214. I2C bus Refer to I2C Status Code Table 24 4 49 Error codes Table 291 Error codes Error Code Description Comment 0 Successful completion Function was completed successfully 1 General error 0x0006 0001 ERR I2C 0x0006 0002 ERR l2C BUFFER OVERFLOW 0x0006 0003 ERR I2C BYTE COUNT ERR 0x0006 0004 ERR I2C LOSS OF ARBRITRATION 0x0006 0005 ERR 126 SLAVE NOT ADDRESSED UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 314 of 370 NXP Semiconductors U M1 0601 Chapter 24 LPC81x I2C bus ROM API Table 291 Error codes Error Code Description Comment 0x0006 0006 ERR I2C LOSS OF ARBRITRATION NAK BIT 0x0006 0007 ERR 126 GENERAL FAILURE Failure detected on I2C bus 0x0006 0008 ERR l2C REGS SET TO DEFAULT 12C clock frequency could not be set Default value of 0x04 is loaded into SCLH and SCLL 24 4 20 12 Status code Table 292 12 Status code Status code Description 0 IDLE 1 MASTER SEND 2 MASTER RECEIVE 3 SLAVE SEND 4 SLAVE RECEIVE 24 4 21 12 ROM driver variables The I2C ROM driver requires specific variables to be declared and initialized for proper usage Depending on the operating mode some variables can be omitted 24 4 21 1 12C Handle The I2C handle is a pointer allocated for the 12C ROM driver The handle needs to be defined as an I2C handle TYP
215. K and configures USARTO pins UO RXD and UO TXD This command may be used when a valid user program is present in the internal flash memory and the ISP entry pin is not accessible to force the ISP mode 22 5 2 9 ReadUID IAP Table 265 IAP ReadUID command Command Compare Input Command code 58 decimal Status code CMD_SUCCESS Result Result0 The first 32 bit word at the lowest address Result1 The second 32 bit word Result2 The third 32 bit word Result3 The fourth 32 bit word Description This command is used to read the unique ID 22 5 2 10 Erase page Table 266 IAP Erase page command Command Erase page Input Command code 59 decimal Start page number Param1 End page number should be greater than or equal to start page Param2 System Clock Frequency CCLK in kHz Status code CMD SUCCESS BUSY SECTOR NOT PREPARED FOR WRITE OPERATION INVALID SECTOR Result None Description This command is used to erase a page or multiple pages of on chip flash memory To erase a single page use the same start and end page numbers 22 5 2 11 1 Status codes Table 267 IAP Status codes Summary Status Mnemonic Description Code 0 CMD SUCCESS Command is executed successfully 1 INVALID COMMAND Invalid command 2 SRC ADDR ERROR Source address is not on a word boundary UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights res
216. L lock time out Result Result PLL SUCCESS PLL INVALID FREQ PLL INVALID MODE PLL FREQ NOT FOUND PLL NOT LOCKED Result1 system clock in kHz The following definitions are needed when making set_pll power routine calls set_pll mode options All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 299 of 370 NXP Semiconductors U M1 0601 UM10601 23 4 1 1 23 4 1 2 Chapter 23 LPC81x Power profile API ROM driver define CPU_FREQ_EQU define CPU_FREQ_LTE define CPU_FREQ_GTE define CPU_FREQ_APPROX set_pll result options define PLL CMD SUCCESS 0 define PLL_INVALID_FREQ 1 define PLL_INVALID_MODE 2 3 4 Ww c define PLL_FREQ_NOT_FOUND define PLL_NOT_LOCKED For a simplified clock configuration scheme see Figure 47 For more details see Figure 3 ParamO0 system PLL input frequency and Param1 expected system clock set pll configures a setup in which the main clock does not exceed 30 MHz see Figure 47 It easily finds a solution when the ratio between the expected system clock and the system PLL input frequency is an integer value but it can also find solutions in other cases The system PLL input frequency must be between 10000 to 25000 kHz 10 MHz to 25 MHz inclusive The expected system clock Param1 must be between 1 and 30000 kHz inclusive If e
217. NASSIGN1 Table 110 U1 CTS Clear To Send input for USART1 PINASSIGN2 Table 111 U1_SCLK Serial clock input output for USART1 in synchronous PINASSIGN2 Table 111 mode U2_TXD Transmitter output for USART2 PINASSIGN2 Table 111 U2_RXD Receiver input for USART2 PINASSIGN2 Table 111 U2 RTS Request To Send output for USART1 PINASSIGN3 Table 112 U2 CTS Clear To Send input for USART1 PINASSIGN3 Table 112 U2_SCLK Serial clock input output for USART1 in synchronous PINASSIGN3 Table 112 mode SPIO_SCK Serial clock for SPIO PINASSIGN3 Table 112 SPIO MOSI VO Master Out Slave In for SPIO PINASSIGN4 Table 113 SPIO_MISO VO Master In Slave Out for SPIO PINASSIGN4 Table 113 SPIO_SSEL Slave select for SPIO PINASSIGN4 Table 113 SPH SCK Serial clock for SPI1 PINASSIGN4 Table 113 SPI1 MOSI VO Master Out Slave In for SPI PINASSIGN5 Table 114 SPI1_MISO VO Master In Slave Out for SPI1 PINASSIGN5 Table 114 SPI1 SSEL O Slave select for SPI1 PINASSIGN5 Table 114 CTIN 0 SCT input 0 PINASSIGN5 Table 114 CTIN_1 SCT input 1 PINASSIGN6 Table 115 CTIN 2 SCT input 2 PINASSIGN6 Table 115 CTIN_3 SCT input 3 PINASSIGN6 Table 115 CTOUT 0 SCT output 0 PINASSIGN6 Table 115 CTOUT_1 SCT output 1 PINASSIGN7 Table 116 CTOUT 2 O SCT output 2 PINASSIGN7 Table 116 CTOUT_3 SCT output 3 PINASSIGN7 Table 116 Il2C0 SDA y o I2C bus data input output open drain if assigned to pin PINASSIGN7 Table 116 PIOO 11 High current sink only if
218. NCLR register see Table 177 The error flags for received noise parity error framing error and overrun are set immediately upon detection and remain set until cleared by software action in STAT Table 175 USART Status register STAT address 0x4006 4008 USARTO 0x4006 8008 USART1 0x4006 C008 USART2 bit description Bit 11 12 13 UM10601 Symbol RXRDY RXIDLE TXRDY TXIDLE CTS DELTACTS TXDISINT OVERRUNINT RXBRK DELTARXBRK START FRAMERRINT Description Receiver Ready flag When 1 indicates that data is available to be read from 0 the receiver buffer Cleared after a read of the RXDAT or RXDATSTAT registers Receiver Idle When 0 indicates that the receiver is currently in the process of 1 receiving data When 1 indicates that the receiver is not currently in the process of receiving data Transmitter Ready flag When 1 this bit indicates that data may be written to 1 the transmit buffer Previous data may still be in the process of being transmitted Cleared when data is written to TXDAT Set when the data is moved from the transmit buffer to the transmit shift register Transmitter Idle When 0 indicates that the transmitter is currently in the 1 process of sending data When 1 indicate that the transmitter is not currently in the process of sending data This bit reflects the current state of the CTS signal regardless of the setting of NA the CTSEN bit in the CFG regist
219. ND HANDLER 1 The boot code is implementing auto baud in software 2 This step is included for backward compatibility and the response is ignored by the boot loader Fig 44 Boot process flowchart UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 275 of 370 UM10601 Chapter 22 LPC81x Flash ISP and IAP programming Rev 1 6 2 April 2014 User manual 22 1 How to read this chapter See Table 233 for different flash configurations Remark The ISP entry pin location also depends on the chip version See Table 231 Table 233 LPC81x flash and ISP configurations Type number Flash ISP entry pin location Package LPC810M021FN8 4kB PIOO_1 DIP8 LPC811M001JDH16 8 kB PIOO 12 TSSOP16 LPC812M101JDH16 16 kB PIOO 12 TSSOP16 LPC812M101JD20 16 kB PIOO 12 SOP20 LPC812M101JDH20 16 kB PIOO 12 TSSOP20 LPC812M101JTB16 16 kB PIOO 12 XSON16 22 2 Features e In System Programming In System programming ISP is programming or reprogramming the on chip flash memory using the bootloader software and UART serial port e In Application Programming In Application IAP programming is performing erase and write operation on the on chip flash memory as directed by the end user application code You can use ISP and IAP when the part resides in the end user board Flash page write and erase supported 22 3 Pi
220. NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 67 of 370 UM10601 Chapter 6 LPC81x I O configuration IOCON Rev 1 6 2 April 2014 User manual 6 1 How to read this chapter The IOCON block is identical for all LPC81x parts Registers for pins that are not available on a specific package are reserved Table 60 Pinout summary Package Pins configuration registers available DIP8 PIOO 0 to PIOO 5 TSSOP16 XSON16 PIOO 0 to PIOO 13 TSSOP20 PIOO 0 to PIOO 17 SOP20 PIOO 0 to PIOO 17 6 2 Features The following electrical properties are configurable for each pin Pull up pull down resistor Open drain mode Hysteresis Digital glitch filter with programmable time constant Analog mode for a subset of pins see the LPC81xM data sheet The true open drain pins PIOO 10 and PIOO 11 can be configured for different I2C bus speeds 6 3 Basic configuration Enable the clock to the IOCON in the SYSAHBCLKCTRL register Table 30 bit 18 Once the pins are configured you can disable the IOCON clock to conserve power Remark If the open drain pins PIOO 10 and PIOO 11 are not available on the package prevent the pins from internally floating as follows Set bits 10 and 11 in the GPIO DIRO register to 1 to enable the output driver and write 1 to bits 10 and 11 in the GPIO CLRO register to drive the outputs LOW internally UM10601 All information provided in this document i
221. O port pin number as 0 to 17 for pins PIOO 0 to PIOO 17 to the INTPIN bits For example setting INTPIN to 0x5 in PINTSELO selects pin PIOO 5 for pin interrupt 0 To determine the GPIO port pin number on a given LPC81x package see the pin description table in the data sheet Remark The GPIO port pin number serves to identify the pin to the PINTSEL register Any digital input function including GPIO can be assigned to this pin through the switch matrix Each of the 8 pin interrupts must be enabled in the NVIC using interrupt slots 24 to 31 see Table 3 To use the selected pins for pin interrupts or the pattern match engine see Section 8 5 2 Pattern match engine All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 43 of 370 NXP Semiconductors U M1 0601 Chapter 4 LPC81x System configuration SYSCON Table 44 Pin interrupt select registers PINTSEL 0 7 address 0x4004 8178 PINTSELO to 0 4004 8194 PINTSEL7 bit description Bit Symbol Description Reset value 5 0 INTPIN Pin number select for pin interrupt or pattern match engine input 0 PIOO 0 to PIOO 17 correspond to numbers 0 to 17 31 6 Reserved z 4 6 28 Start logic 0 pin wake up enable register The STARTERPO register enables the selected pin interrupts for wake up from deep sleep mode and power down modes Remark Also enable the corresp
222. OLY CRC polynom 00 1X CRC 32 polynomial 01 CRC 16 polynomial 00 CRC CCITT polynomial 2 BIT_RVS_WR Data bit order 0 1 Bit order reverse for CRC_WR_DATA per byte 0 No bit order reverse for CRC_WR_DATA per byte 3 CMPL_WR Data complement 0 1 1 s complement for CRC_WR_DATA 0 No 1 s complement for CRC_WR_DATA 4 BIT_RVS_SUM CRC sum bit order 0 1 Bit order reverse for CRC_SUM 0 No bit order reverse for CRC_SUM 5 CMPL_SUM CRC sum complement 0 1 1 s complement for CRC_SUM OzNo 1 s complement for CRC_SUM 31 6 Reserved Always 0 when read 0x0000000 CRC seed register Table 222 CRC seed register SEED address 0x5000 0004 bit description Bit Symbol Description Reset value 31 0 CRC_SEED A write access to this register will load CRC seed value to 0x0000 FFFF CRC_SUM register with selected bit order and 1 s complement pre processes Remark A write access to this register will overrule the CRC calculation in progresses CRC checksum register This register is a Read only register containing the most recent checksum The read request to this register is automatically delayed by a finite number of wait states until the results are valid and the checksum computation is complete All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 262 of 370 NXP Semiconductors UM10601 Chapter 19 LPC81x Cyclic R
223. Only a cold boot when all power has been completely removed from the chip will reset the general purpose registers Table 57 General purpose registers 0 to 3 GPREG 0 3 address 0x4002 0004 GPREGO to 0x4002 0010 GPREG3 bit description Bit Symbol Description Reset value 31 0 GPDATA Data retained during Deep power down mode 0x0 Deep power down control register The Deep power down control register controls the low power oscillator that can be used by the self wake up timer to wake up from Deep power down mode In addition this register configures the functionality of the WAKEUP pin pin PIOO 4 The bits in the register not used for deep power down control bits 31 4 can be used for storing additional data which are retained in Deep power down mode in the same way as registers GPREGO to GPREGS Remark If there is a possibility that the external voltage applied on pin Vpp drops below 2 2 V during Deep power down the hysteresis of the WAKEUP input pin has to be disabled in this register before entering Deep power down mode in order for the chip to wake up Remark Enabling the low power oscillator in Deep power down mode increases the power consumption Only enable this oscillator if you need the self wake up timer to wake up the part from Deep power down mode You may need the self wake up timer if the wake up pin is used for other purposes and the wake up function is not available Table 58 Deep power down control regi
224. PIO port 7 6 Register description The GPIO port registers and the GPIO pin interrupt registers are located on the ARM I O port The I O port supports single cycle access GPIO port addresses can be read and written as bytes halfwords or words ext indicates that the data read after reset depends on the state of the pin which in turn may depend on an external source Remark You can program reserved bits in the GPIO registers to prevent the open drain I2C pins from internally floating when not pinned out See Section 6 3 Table 81 Register overview GPIO port base address 0xA000 0000 Name Access Address Description Reset Width Reference offset value BO to B17 R W 0x0000 to 0x0012 Byte pin registers 0 pins ext byte 8 bit Table 82 PIOO 0 to PIOO 17 Wo to W17 R W 0x1000 to 0x1048 Word pin registers port 0 ext word 32 bit Table 83 DIRO R W 0x2000 Direction registers port 0 0 word 32 bit Table 84 MASKO R W 0x2080 Mask register port 0 0 word 82 bit Table 85 PINO R W 0x2100 Port pin register port 0 ext word 82 bit Table 86 MPINO R W 0x2180 Masked port register port 0 ext word 82 bit Table 87 SETO R W 0x2200 Write Set register for port 0 0 word 82 bit Table 88 Read output bits for port 0 CLRO WO 0x2280 Clear port 0 NA word 32 bit Table 89 NOTO WO 0x2300 Toggle port 0 NA word 82 bit Table 90 7 6 1 GPIO port byte pin registers Each GPIO pin has a byte register in this address range Softw
225. RT receive transmit and control signals are movable functions and are assigned to external pins through the switch matrix See Section 9 3 1 Connect an internal signal to a package pin to assign the USART functions to pins on the LPC81x package Table 171 USART pin description Function Direction Pin UO UO RXD I 00 RIS any any any UO CTS any UM10601 Reference Table 109 Table 109 Table 109 Description SWM register PINASSIGNO PINASSIGNO PINASSIGNO Transmitter output for USARTO Serial transmit data Receiver input for USARTO Serial receive data Request To Send output for USARTO Active low signal indicates that the USARTO is ready to receive data This signal supports inter processor communication through the use of hardware flow control This feature is active when the USART RTS signal is configured to appear on a device pin Clear To Send input for USARTO Active low signal indicates PINASSIGNO that the external device that is in communication with the USART is ready to accept data This feature is active when enabled by the CTSEn bit in CFG register and when configured to appear on a device pin When deasserted high by the external device the USART will complete transmitting any character already in progress then stop until CTS is again asserted low Table 109 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights re
226. Reserved Read value is undefined only zero should be written Monitor Idle interrupt clear Reserved Read value is undefined only zero should be written Event time out interrupt clear SCL time out interrupt clear Reserved Read value is undefined only zero should be written Reset value NA NA NA Time out value register The TIMEOUT register allows setting an upper limit to certain 12C bus times informing by status flag and or interrupt when those times are exceeded Two time outs are generated and software can elect to use either of them 1 EVENTTIMEOUT checks the time between bus events while the bus is not idle Start SCL rising SCL falling and Stop The EVENTTIMEOUT status flag in the STAT register is set if the time between any two events becomes longer than the time configured in the TIMEOUT register The EVENTTIMEOUT status flag can cause an interrupt if enabled to do so by the EVENTTIMEOUTEN bit in the INTENSET register 2 SCLTIMEOUT checks only the time that the SCL signal remains low while the bus is not idle The SCLTIMEOUT status flag in the STAT register is set if SCL remains low longer than the time configured in the TIMEOUT register The SCLTIMEOUT status flag can cause an interrupt if enabled to do so by the SCLTIMEOUTEN bit in the INTENSET register The SCLTIMEOUT can be used with the SMBus Also see Section 16 7 2 Time out All information provided in this document is subject
227. S SWCLK PIOO 2 R W 0x018 configuration for pin PlOO_2 SWDIO 0 0000 0090 Table 68 PIOO 11 R W 0x01C I O configuration for pin PlOO_11 This 0 0000 0080 Table 69 is the pin configuration for the true open drain pin PIOO 10 R W 0x020 configuration for pin PIOO 10 This 0 0000 0080 Table 70 is the pin configuration for the true open drain pin PIOO 16 R W 0x024 I O configuration for pin PIOO 16 0x0000 0090 Table 71 PIOO 15 R W 0x028 I O configuration for pin PIOO 15 0x0000 0090 Table 72 PIOO 1 R W 0x02C I O configuration for pin 0x0000 0090 Table 73 PIOO 1 ACMP H CLKIN 0x030 Reserved PIOO 9 R W 0x034 configuration for pin 0x0000 0090 Table 74 PIOO 9 XTALOUT PIOO 8 R W 0x038 I O configuration for pin PIOO_8 XTALIN 0x0000 0090 Table 75 PIOO 7 R W 0x03C I O configuration for PIOO 7 0x0000 0090 Table 76 PIOO 6 R W 0x040 configuration for pin 0x0000 0090 Table 77 PIOO_6 VDDCMP PIOO 0 R W 0x044 I O configuration for pin 0x0000 0090 Table 78 PIOO 0 ACMP 10 PIOO 14 R W 0x048 I O configuration for pin PIOO 14 0x0000 0090 Table 79 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 71 of 370 NXP Semiconductors UM10601 6 5 1 PIOO 17 register Chapter 6 LPC81x I O configuration IOCON Table 62 PIOO_17 register PIOO 17 address 0x4004 4000 bit description Bit Symbol Value Description Reset value 2 0
228. S pin is used by an external debug tool to communicate with and control the LPC81x This pin is pulled up internally The boundary scan mode and the pins needed are selected by hardware see Section 26 5 3 There is no access to the boundary scan pins through the switch matrix UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 328 of 370 NXP Semiconductors U M1 0601 Chapter 26 LPC81x Debugging Table 304 JTAG boundary scan pin description Function Pin name Type Description TCK SWCLK PIOO_3 JTAG Test Clock This pin is the clock for JTAG boundary scan when the RESET TCK pin is LOW TMS SWDIO PIOO_2 JTAG Test Mode Select The TMS pin selects the next state in the TAP state TMS machine This pin includes an internal pull up and is used for JTAG boundary scan when the RESET pin is LOW TDI PIOO_1 ACMP_12 JTAG Test Data In This is the serial data input for the shift register This pin CLKIN TDI includes an internal pull up and is used for JTAG boundary scan when the RESET pin is LOW TDO PIOO 0 ACMP 11 JTAG Test Data Output This is the serial data output from the shift register Data TDO is shifted out of the device on the negative edge of the TCK signal This pin is used TRST PIOO 4 WAKEUP TRST debug logic This pin includes an internal pull up and is used for JTAG boundary for JTAG boundary scan w
229. SEL pin is configured by bits in the CFG register SSEL asserted SSEL not asserted Reserved End of Transfer The asserted SSEL will be deasserted at the end of a transfer and 0 remain so for at least the time specified by the Transfer_delay value in the DLY register When EOT is not set data stalls can occur When EOT is set the transfer is completed and data stalls will not happen SSEL not deasserted This piece of data is not treated as the end of a transfer SSEL will not be deasserted at the end of this data SSEL deasserted This piece of data is treated as the end of a transfer SSEL will be deasserted at the end of this piece of data End of Frame Between frames a delay may be inserted as defined by the 0 Frame_delay value in the DLY register The end of a frame may not be particularly meaningful if the FRAME_DELAY value 0 This control can be used as part of the support for frame lengths greater than 16 bits Data not EOF This piece of data transmitted is not treated as the end of a frame Data EOF This piece of data is treated as the end of a frame causing the FRAME_DELAY time to be inserted before subsequent data is transmitted All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 243 of 370 NXP Semiconductors U M1 0601 Chapter 17 LPC81x SPIO 1 Table 210 SPI Transmitter Data and Control register
230. SLVCONTINUE ack data UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 345 of 370 NXP Semiconductors UM10601 UM10601 29 2 13 29 2 14 Chapter 29 LPC81x Code examples Slave write one byte to master Table 319 12C Code example Slave write one byte to master Address 0x23 Data Oxdd Polling mode LPC_ LPC_ if LPC_ Lf LPC_ LPC_ while LPC_I2C gt STAT amp 126 while LPC_I2C gt STAT amp 126 2C gt SLVADRO 0x23 lt lt 2C gt CFG 12C_CFG_SLVEN _STAT_S LPC_I2C gt STAT amp I2C STAT 2C gt SLVCTL I2C SLVCTL SLVCO _STAT_S LPC_I2C gt STAT amp I2C STAT 2C gt SLVDAT 2C gt SLVCTL 12C_SLVCT L_SLVCO LVPE _SLVSTATE LVPE _SLVSTATE 0xdd write data put address in address 0 register DINC l I2C STAT SLVST ADDR TINUE ack address DINC I2C STAT SLVSTX abort abort TINUE continue transaction Slave read one byte from master into subaddress Table 320 12C Code example Slave read one byte from master into subaddress Address 0x23 Polling mode LPC_ LPC_ whi LPC_ whi LPC_ whi data LPC_ le LPC_I2C gt STAT amp I2C_S1 if LPC_I2C gt S1 le LPC_I2C gt STAT amp if LPC_I2C gt S1 subaddress if subaddress
231. SPI gt STAT amp SPI STAT TXRDY LPC_SPI gt TXDATCTL SPI TXDATCTL FLEN 7 SPI TXDATCTL EOT I SPI TXDATCTL SSEL 0 Oxdd while LPC_SPI gt STAT amp SPI STAT RXRDY data LPC_SPI gt RXDAT if data Oxdd abort while LPC_SPI gt STAT amp SPI STAT MSTIDLE Transmit and receive 24 bits to from slave 0 interrupt mode Table 330 SPI Code example Transmit and receive 24 bits to from slave 0 interrupt mode LPC_SPI gt CFG SPI MASTER SPI ENABLE LPC_SPI gt INTENSET SPI STAT TXRDY SPI STAT RXRDY Wwhile LPC SPI INTENSET amp SPI STAT TXRDY SPI STAT RXRDY NVIC DisableIRQ Spi IRQn Transmit 8 bits to master Table 331 SPI Code example Transmit 8 bits to master LPC SPI CFG SPI ENABLE while LPC_SPI gt STAT amp SPI STAT TXRDY LPC_SPI gt TXDATCTL SPI TXDATCTL FLEN 7 SPI TXDATCTL RXIGNORE 0 while LPC_SPI gt STAT amp SPI STAT TXRDY LPC_SPI gt STAT SPI STAT SSD while LPC_SPI gt STAT amp SPI STAT SSD LPC_SPI gt STAT SPI STAT SSD Receive 8 bits to master Table 332 SPI Code example Receive 8 bits to master LPC_SPI gt CFG SPI CFG ENABLE while LPC_SPI gt STAT amp SPI STAT TXRDY LPC_SPI gt TXDATCTL SPI FLEN 7 while LPC_SPI gt STAT amp SPI STAT RXRDY data LPC_SPI gt RXDAT if data Oxdd abort All i
232. SYSPLL_PD bit to zero the PLL will resume its normal operation and will make the lock signal high once it has regained lock on the input clock 4 7 4 3 Divider ratio programming 4 7 4 3 1 Post divider The division ratio of the post divider is controlled by the PSEL bits The division ratio is two times the value of P selected by PSEL bits as shown in Table 20 This guarantees an output clock with a 50 duty cycle 4 7 4 3 2 Feedback divider The feedback divider s division ratio is controlled by the MSEL bits The division ratio between the PLL s output clock and the input clock is the decimal value on MSEL bits plus one as specified in Table 20 4 7 4 3 3 Changing the divider values Changing the divider ratio while the PLL is running is not recommended As there is no way to synchronize the change of the MSEL and PSEL values with the dividers the risk exists that the counter will read in an undefined value which could lead to unwanted spikes or drops in the frequency of the output clock The recommended way of changing between divider settings is to power down the PLL adjust the divider settings and then let the PLL start up again 4 7 4 4 Frequency selection The PLL frequency equations use the following parameters also see Figure 5 Table 51 PLL frequency parameters Parameter System PLL FCLKIN Frequency of sys pllclkin input clock to the system PLL from the SYSPLLCLKSEL multiplexer see Section 4 6 8 FCCO Frequency
233. TA Slave function data register 0 Read read the most recently received data for the Slave function Write transmit data using the Slave function 31 8 Reserved Read value is undefined only zero should be written NA All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 226 of 370 NXP Semiconductors U M1 0601 Chapter 16 LPC81x I2C bus interface 16 6 13 Slave Address registers The SLVADR O0 3 registers allow enabling and defining one of the addresses that can be automatically recognized by the 12C slave hardware The value in the SLVADRO register is qualified by the setting of the SLVQUALO register When the slave address is compared to the receive address the compare can be affected by the setting of the SLVQUALO register see Section 16 6 14 The 12 slave function has 4 address comparators The additional 3 address comparators do not include the address qualifier feature For handling of the general call address one of the 4 address registers can be programmed to respond to address 0 Table 199 Slave Address registers SLVADR 0 3 address 0x4005 0048 SLVADRO to 0x4005 0054 SLVADR3 bit description Bit Symbol Value Description Reset value 0 SADISABLE Slave Address n Disable 1 0 Enabled Slave Address n is enabled and will be recognized with any changes specified by the SLVQUALO register 1 Ignor
234. TALOUT pins which connect to the external crystal through the fixed pin function in the switch matrix XTALIN and XTALOUT can only be assigned to pins PIOO 8 and PIOO 9 1 In the IOCON block remove the pull up and pull down resistors in the IOCON registers for pins PIOO 8 and PIOO 9 2 In the switch matrix block enable the 1 bit functions for XTALIN and XTALOUT 3 In the SYSOSCCTRL register disable the BYPASS bit and select the oscillator frequency range according to the desired oscillator output clock All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 24 of 370 NXP Semiconductors U M1 0601 Chapter 4 LPC81x System configuration SYSCON Related registers Table 75 PIOO_8 register PIOO_8 address 0x4004 4038 bit description Table 74 PIOO_9 register PIOO_9 address 0x4004 4034 bit description Table 118 Pin enable register 0 PINENABLEO address 0x4000 1 bit description Table 22 System oscillator control register SYSOSCCTRL address 0x4004 8020 bit description 4 4 Pin description The SYSCON inputs and outputs are assigned to external pins through the switch matrix See Section 9 3 1 Connect an internal signal to a package pin to assign the CLKOUT function to a pin on the LPC81x package See Section 9 3 2 to enable the clock input th
235. TSEL1 register and So forth Remark Writing any value to either the PMCFG register or the PMSRC register or disabling the pattern match feature by clearing both the SEL PMATCH and ENA RXEV bits in the PMCTRL register to zeros will erase all edge detect history Table 104 Pattern match bit slice source register PMSRC address 0xA000 402C bit description Bit Symbol Value Description Reset value 7 0 Reserved Software should not write 1s to unused bits 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 107 of 370 NXP Semiconductors UM10601 Chapter 8 LPC81x Pin interrupts pattern match engine Table 104 Pattern match bit slice source register PMSRC address 0xA000 402C bit description Bit Symbol Value Description Reset value 10 8 Selects the input source for bit slice 0 0 0x0 Input 0 Selects the pin selected in the PINTSELO register as the source to bit slice 0 0x1 Input 1 Selects the pin selected in the PINTSEL1 register as the source to bit slice 0 0x2 Input 2 Selects the pin selected in the PINTSEL2 register as the source to bit slice 0 0x3 Input Selects the pin selected in the PINTSEL3 register as the source to bit slice 0 0x4 Input 4 Selects the pin selected in the PINTSEL4 register as the source to bit slice 0 0x5 Input 5 Selects the pin selected in the PINTSELS5 register
236. TXDATCTL addresses 0x4005 8018 SPIO 0x4005 C018 SPI1 bit description continued Bit Symbol Value Description Reset value 22 RXIGNORE Receive Ignore This allows data to be transmitted using the SPI without the need to 0 read unneeded data from the receiver to simplify the transmit process 0 Read received data Received data must be read in order to allow transmission to progress In slave mode an overrun error will occur if received data is not read before new data is received 1 Ignore received data Received data is ignored allowing transmission without reading unneeded received data No receiver flags are generated 23 Reserved Read value is undefined only zero should be written NA 27 24 LEN Data Length Specifies the data length from 1 to 16 bits Note that transfer lengths 0x0 greater than 16 bits are supported by implementing multiple sequential transmits 0x0 Data transfer is 1 bit in length 0x1 Data transfer is 2 bits in length 0 2 Data transfer is bits in length OxF Data transfer is 16 bits in length 31 28 Reserved Read value is undefined only zero should be written NA 17 6 8 SPI Transmitter Data Register The TXDAT register is written in order to send data via the SPI transmitter when control information is not changing during the transfer see Section 17 6 7 That data will be sent to the transmit shift register when it is available and another character may then be written to
237. T_N USART fractional baud rate generator 1 UARTFRG reset control 0 Assert the UARTFRG reset Clear the UARTFRG reset 3 UARTO_RST_N USARTO reset control 1 0 Assert the USARTO reset Clear the USARTO reset 4 UART1_RST_N USART1 reset control 1 0 Assert the USART reset Clear the USART1 reset 5 UART2_RST_N USART2 reset control 1 0 Assert the USART2 reset Clear the USART2 reset 6 l2C N 12C reset control 1 0 Assert the 12C reset Clear the 12C reset 7 MRT RST N Multi rate timer MRT reset control 1 0 Assert the MRT reset Clear the MRT reset 8 SCT RST N SCT reset control 1 0 Assert the SCT reset Clear the SCT reset 9 WKT RST N Self wake up timer WKT reset control 1 0 Assert the WKT reset Clear the WKT reset 10 GPIO RST N GPIO and GPIO pin interrupt reset control 1 0 Assert the GPIO reset Clear the GPIO reset 11 FLASH RST N Flash controller reset control 1 0 Assert the flash controller reset Clear the flash controller reset 12 ACMP RST N Analog comparator reset control 1 0 Assert the analog comparator reset Clear the analog comparator controller reset 31 13 Reserved UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 30 of 370 NXP Semiconductors U M1 0601 4 6 3 4 6 4 4 6 5 UM10601 Chapier 4 LPC81x System configuration SYSCON System PLL control register This register c
238. Table 37 PIOPORCAPO R 0x100 POR captured PIO status 0 user dependent Table 38 0x104 Reserved 3 IOCONCLKDIV6 R W 0x134 Peripheral clock 6 to the IOCON block for 0x0000 0000 Table 39 programmable glitch filter IOCONCLKDIV5 R W 0x138 Peripheral clock 5 to the IOCON block for 0x0000 0000 Table 39 programmable glitch filter IOCONCLKDIV4 R W 0x13C Peripheral clock 4 to the IOCON block for 0x0000 0000 Table 39 programmable glitch filter IOCONCLKDIV3 R W 0x140 Peripheral clock 3 to the IOCON block for 0x0000 0000 Table 39 programmable glitch filter IOCONCLKDIV2 R W 0x144 Peripheral clock 2 to the IOCON block for 0x0000 0000 Table 39 programmable glitch filter IOCONCLKDIV1 R W 0x148 Peripheral clock 1 to the IOCON block for 0x0000 0000 Table 39 programmable glitch filter IOCONCLKDIVO R W 0x14C Peripheral clock 0 to the IOCON block for 0x0000 0000 Table 39 programmable glitch filter BODCTRL R W 0x150 Brown Out Detect 0 Table 40 SYSTCKCAL R W 0x154 System tick counter calibration 0x0 Table 41 R W 0x168 Reserved IRQLATENCY R W 0x170 IQR delay Allows trade off between interrupt 0 0000 0010 Table 42 latency and determinism NMISRC R W 0x174 NMI Source Control 0 Table 43 PINTSELO R W 0x178 GPIO Pin Interrupt Select register 0 0 Table 44 PINTSEL1 R W 0x17C GPIO Pin Interrupt Select register 1 0 Table 44 PINTSEL2 R W 0x180 GPIO Pin Interrupt Select register 2 0 Table 44 PINTSEL3 R W 0x184 GPIO Pin Interrupt Select register 3 0 Table 44
239. The SYSAHBCLKCTRL register controls which memories and peripherals are running Table 30 The power to various analog blocks PLL oscillators the BOD circuit and the flash block can be controlled at any time individually through the PDRUNCFG register Table 49 Power configuration register PDRUNCFG address 0x4004 8238 bit description The clock source for the system clock can be selected from the IRC default the system oscillator or the watchdog oscillator see Figure 3 and related registers The system clock frequency can be selected by the SYSPLLCTRL Table 20 and the SYSAHBCLKDIV register Table 29 The USART and CLKOUT use individual peripheral clocks with their own clock dividers The peripheral clocks can be shut down through the corresponding clock divider registers Sleep mode In Sleep mode the system clock to the ARM Cortex M0 core is stopped and execution of instructions is suspended until either a reset or an interrupt occurs Peripheral functions if selected to be clocked in the SYSAHBCLKCTRL register continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution Sleep mode eliminates dynamic power used by the processor itself memory systems and related controllers and internal buses The processor state and registers peripheral registers and internal SRAM values are maintained and the logic levels of the pins remain static Power configuration
240. The value read from a reserved bit is not defined Once the WDEN WDPROTECT or WDRESET bits are set they can not be cleared by software Both flags are cleared by an external reset or a Watchdog timer reset WDTOF The Watchdog time out flag is set when the Watchdog times out when a feed error occurs or when PROTECT 1 and an attempt is made to write to the TC register This flag is cleared by software writing a O to this bit WDINT The Watchdog interrupt flag is set when the Watchdog counter reaches the value specified by WARNINT This flag is cleared when any reset occurs and is cleared by software by writing a O to this bit In all power modes except Deep power down mode a Watchdog reset or interrupt can occur when the watchdog is running and has an operating clock source The watchdog oscillator can be configured to keep running in Sleep Deep sleep modes and Power down modes If a watchdog interrupt occurs in Sleep Deep sleep mode or Power down mode and the WWDT interrupt is enabled in the NVIC the device will wake up Note that in Deep sleep and Power down modes the WWDT interrupt must be enabled in the STARTERP 1 register in addition to the NVIC See the following registers Table 46 Start logic 1 interrupt wake up enable register STARTERP1 address 0x4004 8214 bit description UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manua
241. USARTO USART1 USART2 IRC oscillator IOCON glitch filter watchdog oscillator MAINCLKSEL main clock select IRC oscillator IRC oscillator T mae system oscillator END CLKOUT pin SYSTEM PLL watchdog oscillator CLKIN CLKOUTSEL CLKOUT clock select SYSPLLCLKSEL system PLL clock select watchdog oscillator WWDT IRC oscillator WKT low power oscillator WKT aaa 005749 Fig 3 LPC81x clock generation 4 5 2 Power control of analog components The system control block controls the power to the analog components such as the oscillators and PLL the BOD and the analog comparator For details see the following registers Section 4 6 30 Deep sleep mode configuration register Section 4 6 3 System PLL control register Section 4 6 6 Watchdog oscillator control register Section 4 6 5 System oscillator control register UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 26 of 370 NXP Semiconductors U M1 0601 Chapter 4 LPC81x System configuration SYSCON 4 5 3 Configuration of reduced power modes The system control block configures analog blocks that can remain running in the reduced power modes the BOD and the watchdog oscillator for safe operation and enables various interrupts to wake up the chip
242. Write the slave address with the RW bit set to 1 to the Master data register MSTDAT See Table 196 Start the transmission by setting the MSTSTART bit to 1 in the Master control register See Table 194 The following happens The pending status is cleared and the 12 bus is busy The I2C master sends the start bit and address with the RW bit to the slave The slave sends 8 bit of data Wait for the pending status to be set MSTPENDING 1 by polling the STAT register Read 8 bits of data from the MSTDAT register Wait for the pending status to be set MSTPENDING 1 by polling the STAT register Stop the transmission by setting the MSTSTOP bit to 1 in the Master control register See Table 194 Write data to the slave and read back 2 bytes of data from the slave 1 Write the slave address with the RW bit set to 0 to the Master data register MSTDAT See Table 196 Start the transmission by setting the MSTSTART bit to 1 in the Master control register See Table 194 The following happens The pending status is cleared and the I2C bus is busy The 12C master sends the start bit and address with the RW bit to the slave Wait for the pending status to be set MSTPENDING 1 by polling the STAT register 4 Write 8 bits of data to the MSTDAT register 5 Continue with the transmission of the data by setting the MSTCONTINUE bit to 1 in the Master control register See Table 194 The following ha
243. Writing a 0 to has no effect Time out The self wake up timer has timed out This flag generates an interrupt request which can wake up the part from any reduced power mode including Deep power down if the clock source is the low power oscillator Writing a 1 clears this status bit All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 181 of 370 NXP Semiconductors U M1 0601 Chapter 13 LPC81x Self wake up timer WKT Table 164 Control register CTRL address 0x4000 8000 bit description Bit Symbol Value Description Reset value 2 CLEARCTR Clears the self wake up timer 0 0 No effect Reading this bit always returns 0 1 Clear the counter Counting is halted until a new count value is loaded 31 3 Reserved 13 6 2 Count register Do not write to this register while the counting is in progress Remark In general reading the timer state is not recommended There is no mechanism to ensure that some bits of this register don t change while a read is in progress if the read happens to coincide with an self wake up timer clock edge If you must read this value it is recommended to read it twice in succession Table 165 Counter register COUNT address 0x4000 800C bit description Bit Symbol Description Reset value 31 0 VALUE A write to this register pre loads start count value into the timer and starts the
244. able 117 0x024 R W 0 1 0 Pin enable register 0 Enables fixed pin 0x1B3 Table 118 functions ACMP 10 ACMP 11 SWCLK SWDIO XTALIN XTALOUT RESET CLKIN VDDCMP UM10601 9 5 1 Pin assign register 0 Table 109 Pin assign register 0 PINASSIGNO address 0x4000 C000 bit description Bit Reset value OxFF Symbol Description 7 0 UO TXD TXD function assignment The value is the pin number to be assigned to this function The following pins are available PIOO 0 0 to 17 0x11 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 127 of 370 NXP Semiconductors UM10601 UM10601 9 5 2 9 5 3 Chapter 9 LPC81x Switch matrix Table 109 Pin assign register 0 PINASSIGNO address 0x4000 C000 bit description Bit Symbol 15 8 UO I 23 16 UO RTS 31 24 UO CTS I Description Reset value UO RXD function assignment The value is the pin number to be OxFF assigned to this function The following pins are available PIOO 0 0 to 17 0x11 UO RTS function assignment The value is the pin number tobe OxFF assigned to this function The following pins are available PIOO 0 0 to 17 0x11 UO CTS function assignment The value is the pin number to be OxFF assigned to this function The following pins are available PIOO 0
245. able 14 Interrupt Priority Register 6 IPR6 address EXTTRACECMD address 0x4004 80FC bit OxE000 E418 bit description 22 lt 41 Table 15 Interrupt Priority Register 7 IPR7 address Table 38 POR captured PIO status register 0 OxE000 E41C bit description 22 PIOPORCAPO address 0x4004 8100 bit Table 16 SYSCON pin description 25 lt 41 Table 17 Register overview System configuration base Table 39 IOCON glitch filter clock divider registers 6 to 0 address 0x4004 8000 27 IOCONCLKDIV 6 0 address 0x4004 8134 Table 18 System memory remap register IOCONCLKDIV6 to 0x004 814C SYSMEMREMAP address 0x4004 8000 bit IOCONFILTCLKDIVO bit description 41 iiu costos Rr Wen RS en 29 Table 40 BOD control register BODCTRL address 0x4004 Table 19 Peripheral reset control register PRESETCTRL 8150 bit description 42 address 0x4004 8004 bit description 29 Table 41 System tick timer calibration register Table 20 System PLL control register SYSPLLCTRL SYSTCKCAL address 0x4004 8154 bit address 0x4004 8008 bit description 31 lt 42 Table 21 System PLL status register SYSPLLSTAT Table 42 IRQ latency register IRQLATENCY address address 0x4004 800C bit description
246. ach counter select unidirectional or bidirectional counting mode field BIDIR_L and or BIDIR Select the prescale factor for the counter clock CTRL register Clear the HALT_L and or HALT H bit By default the counters are halted and no events can occur To stop the counters by software at any time stop or halt the counter write to STOP L and or STOP H bits or HALT L and or HALT bits in the CTRL register When the counters are stopped both an event configured to clear the STOP bit or software writing a zero to the STOP bit can start the counter again When the counter are halted only a software write to clear the HALT bit can start the counter again No events can occur When the counters are halted software can set any SCT output HIGH or LOW directly by writing to the OUT register All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 160 of 370 NXP Semiconductors U M1 0601 10 7 12 10 7 13 UM10601 Chapter 10 LPC81x SCTimer PWM SCT The current state can be read at any time by reading the STATE register To change the current state by software that is independently of any event occurring set the HALT bit and write to the STATE register to change the state value Writing to the STATE register is only allowed when the counter is halted the HALT_L and or HALT_H bits are set
247. adder value The reference voltage Vref depends 0 on the LADREF bit below 00000 Vss 00001 1 x Vref 31 00010 2 x Vret 31 11111 Vref 6 LADREF Selects the reference voltage Vref for the voltage ladder 0 0 Supply pin Vpp 1 VDDCMP pin 317 Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 259 of 370 UM10601 Chapter 19 LPC81x Cyclic Redundancy Check CRC engine Rev 1 6 2 April 2014 User manual 19 1 How to read this chapter The CRC engine is available on all LPC81x parts 19 2 Features Supports three common polynomials CRC CCITT CRC 16 and CRC 32 CRC CCITT 16 x12 5 1 CRC 16 x18 x15 2 1 32 x32 26 x23 x22 x16 x12 x11 x10 4 x84 x74 x54 x44 x2 ex 1 Bit order reverse 1 s complement programmable setting for input data CRC sum Programmable seed number setting Accept any size of data width per write 8 16 or 32 bit 8 bit write 1 cycle operation 16 bit write 2 cycle operation 8 bit x 2 cycle 32 bit write 4 cycle operation 8 bit x 4 cycle 19 3 Basic configuration Enable the clock to the CRC engine in the SYSAHBCLKCTRL register Table 30 bit 13 19 4 Pin description The CRC engine has no configurable pins 19 5 General description The Cyclic Redundanc
248. al so the FRG distributes the output clocks as evenly as is practical Since the USART normally uses 16x overclocking the jitter in the fractional rate clock in these cases tends to disappear in the ultimate USART output For setting up the fractional divider use the following registers Table 35 USART fractional generator divider value register UARTFRGDIV address 0x4004 80F0 bit description Table 36 USART fractional generator multiplier value register UARTFRGMULT address 0x4004 80F4 bit description For details see Section 15 3 1 Configure the USART clock and baud rate 15 7 1 2 Baud Rate Generator BRG The Baud Rate Generator see Section 15 6 9 is used to divide the base clock to produce a rate 16 times the desired baud rate Typically standard baud rates can be generated by integer divides of higher baud rates 15 7 1 3 Baud rate calculations Base clock rates are 16x for asynchronous mode and 1x for synchronous mode 15 7 2 Synchronous mode Remark Sync mode transmit and receive operate at the incoming clock rate in slave mode and the BRG selected rate not divided by 16 in master mode 15 7 3 Flow control The USART supports both hardware and software flow control 15 7 3 1 Hardware flow control The USART supports hardware flow control using RTS and or CTS signalling If RTS is configured to appear on a device pin so that it can be sent to an external device it indicates to an external d
249. also set to 1 the interrupt for timer channel n and the global interrupt are raised Writing a 1 to this bit clears the interrupt request 1 RUN Indicates the state of TIMERn This bit is read only 0 0 Idle state TIMERn is stopped 1 Running TIMERn is running 31 2 Reserved 0 Idle channel register The idle channel register returns the lowest idle channel number The channel is considered idle when both flags is the STATUS register RUN and INTFLAG are zero In an application with multiple timers running independently you can calculate the register offset of the next idle timer by reading the idle channel number in this register The idle channel register allows you set up the next idle timer without checking the idle state of each timer All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 169 of 370 NXP Semiconductors U M1 0601 Chapter 11 LPC81x Multi Rate Timer MRT Table 153 Idle channel register IDLE_CH address 0x4000 40F4 bit description Bit Symbol Description Reset value 3 0 Reserved 0 7 4 CHAN Idle channel Reading the CHAN bits returns the lowest idle timer 0 channel If all timer channels are running CHAN 4 31 8 Reserved 0 11 6 6 Global interrupt flag register The global interrupt register combines the interrupt flags from the individual timer channels in one register S
250. alue OxFF FFFF 31 24 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined 12 7 Functional description The following figures illustrate several aspects of Watchdog Timer operation wocuu4 of Vf VS VE VAAN NEN NN Watchdog Counter 125A 1259 X 1258 X 1257 Early Feed Event Watchdog Reset Conditions WINDOW 0x1200 WARNINT Ox3FF TC 0x2000 Fig 25 Early watchdog feed with windowed mode enabled woeks CX CX C CX X S X Xd X e uu Watchdog Counter 1201 Y 1200 11FFJ 11FEY11FDY11FC Y 2000 Y1FFF 4FFEY1FFDY1FFC Correct Feed Event Watchdog Reset Conditions WDWINDOW 0x1200 WDWARNINT 0x3FF WDTC 0x2000 Fig 26 Correct watchdog feed with windowed mode enabled woeks S AVA V VY VY VYA S CAU VV X 0403 Y 0402 Y 0401 X 0400 03 FAX 03F9 Watchdog Interrupt Conditions WINDOW 0x1200 WARNINT Ox3FF TC 0x2000 Fig 27 Watchdog warning interrupt UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 179 of 370 UM10601 Chapter 13 LPC81x Self wake up timer WKT Rev 1 6 2 April 2014 User manual 13 1 How to read this cha
251. alue is undefined only zero should be NA written 2 TXRDY Transmitter Ready flag 1 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 202 of 370 NXP Semiconductors UM10601 Table 182 USART Interrupt Status register INTSTAT address 0x4006 4024 USARTO Chapter 15 LPC81x USARTO 1 2 0x4006 8024 USART1 0x4006 C024 USART2 bit description Bit Symbol Description Reset Value 4 8 Reserved Read value is undefined only zero should be NA written 5 DELTACTS This bit is set when a change in the state of the CTS input is 0 detected 6 TXDISINT Transmitter Disabled Interrupt flag 0 7 Reserved Read value is undefined only zero should be NA written 8 OVERRUNINT Overrun Error interrupt flag 0 10 9 Reserved Read value is undefined only zero should be NA written 11 DELTARXBRK This bit is set when a change in the state of receiver break 0 detection occurs 12 START This bit is set when a start is detected on the receiver input 0 13 FRAMERRINT Framing Error interrupt flag 0 14 PARITYERRINT Parity Error interrupt flag 0 15 RXNOISEINT Received Noise interrupt flag 0 31 16 Reserved Read value is undefined only zero should be NA written 15 7 Functional description UM10601 15 7 1 15 7 1 1 Clocking and Baud rates In order to use the USART clocking details must be define
252. aram Input parameter handle The handle to the uart instance param Refer to definition Return Error code ERR UART SEND ON UART sending is ongoing Description Send string end with X0 or raw data through UART 25 4 8 UART interrupt service routine Table 301 uart isr Routine uart isr Prototype void uart is UART HANDLE T handle Input parameter handle The handle to the uart instance Return None Description UART interrupt service routine To use this routine the corresponding USART interrupt must be enabled This function is invoked by the user ISR 25 4 9 Error codes Table 302 Error codes Return code 0x0008 0001 Error Code ERR UART RXD BUSY ERR UART 1 Description UART receive is busy 0x0008 0002 UM10601 ERR UART TXD BUSY UART transmit is busy 0x0008 0003 ERR UART OVERRUN FRA Overrun error Frame error ME PARITY NOISE parity error RxNoise error 0x0008 0004 ERR UART UNDERRUN Underrun error 0x0008 0005 ERR UART PARAM All information provided in this document is subject to legal disclaimers Parameter error NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 325 of 370 NXP Semiconductors UM10601 Chapter 25 LPC81x USART API ROM driver routines 25 4 10 UART ROM driver variables 25 4 10 1 25 4 10 2 UART HANDLE T 25 4 10 3 UM10601 UART CONFIG structure typdef struct UART CONFIG uint32 t s
253. are needs to set the data length in the transmitter control or transmitter data and control register first in order to handle reception with correct data length The programmed data length becomes active only when data is actually transmitted Therefore this must be done before any data can be received When control information remains static during transmit the TXDAT register should be used see Section 17 6 8 instead of the TXDATCTL register Control information can then be written separately via the TXCTL register see Section 17 6 9 The upper part of TXDATCTL bits 27 to 16 are the same bits contained in the TXCTL register The two registers simply provide two ways to access them For details on the slave select process see Section 17 7 4 For details on using multiple consecutive data transmits for data lengths larger than 16 bit see Section 17 7 5 Data lengths greater than 16 bits For details on data stalls see Section 17 7 6 Data stalls Table 210 SPI Transmitter Data and Control register TXDATCTL addresses 0x4005 8018 SPIO 0x4005 C018 SPI1 bit description Bit Symbol 15 0 TXDAT 16 TXSSEL N 19 17 20 EOT 21 EOF UM10601 Value Description Reset value Transmit Data This field provides from 1 to 16 bits of data to be transmitted 0 Transmit Slave Select This field asserts SSEL in master mode The output on the pin 0 is active LOW by default Remark The active state of the S
254. are typically reads and writes bytes to access individual pins but can read or write halfwords to sense or set the state of two pins and read or write words to sense or set the state of four pins Table 82 GPIO port 0 byte pin registers B 0 17 addresses 0xA000 0000 BO to 0xA000 0012 B17 bit description Bit Symbol Description Reset Access value 0 PBYTE Read state of the pin PIOO n regardless of direction ext R W masking or alternate function except that pins configured as analog I O always read as 0 Write loads the pin s output bit 7 1 Reserved 0 on read ignored on write 0 7 6 2 GPIO port word pin registers Each GPIO pin has a word register in this address range Any byte halfword or word read in this range will be all zeros if the pin is low or all ones if the pin is high regardless of direction masking or alternate function except that pins configured as analog I O always read as zeros Any write will clear the pin s output bit if the value written is all zeros else it will set the pin s output bit UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 91 of 370 NXP Semiconductors U M1 0601 UM10601 7 6 3 7 6 4 7 6 5 Chapter 7 LPC81x GPIO port Table 83 GPIO port 0 word pin registers W 0 17 addresses 0xA000 1000 WO to 0x5000 1048 W17 bit description Bit Symbol Description Rese
255. ary scan RESET LOW and the ARM SWD debug RESET HIGH The ARM SWD debug port is disabled while the part is in reset To perform boundary scan testing follow these steps Erase any user code residing in flash Power up the part with the RESET pin pulled HIGH externally Wait for at least 250 us Pull the RESET pin LOW externally Perform boundary scan operations Once the boundary scan operations are completed assert the TRST to enable the SWD debug mode and release the RESET pin pull HIGH Remark The JTAG interface cannot be used for debug purposes Remark POR BOD reset or a LOW on the TRST pin puts the test TAP controller in the Test Logic Reset state The first TCK clock while RESET HIGH places the test TAP in Run Test Idle mode All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 330 of 370 NXP Semiconductors U M1 0601 Chapter 26 LPC81x Debugging 26 5 4 Micro Trace Buffer MTB The MTB registers are located at memory address 0x1400 0000 and are described in Ref 4 The EXTTRACE register in the syscon block see Section 4 6 20 starts and stops tracing in conjunction with the TSTARTEN and TSTOPEN bits in the MTB MASTER register The trace is stored in the local SRAM starting at address 0x1000 0000 The trace memory location is configured in the MTB POSITION
256. as 0 occurred in the detection of a received break condition break condition asserted or deasserted All information provided in this document is subject to legal disclaimers NXP B V 2014 AII rights reserved User manual Rev 1 6 2 April 2014 198 of 370 NXP Semiconductors UM10601 15 6 5 Chapter 15 LPC81x USARTO 1 2 Table 176 USART Interrupt Enable read and set register INTENSET address 0x4006 400C USARTO 0x4006 800C USART1 0x4006 COOC USART2 bit description Bit Symbol 12 STARTEN 13 FRAMERREN 14 PARITYERREN 15 RXNOISEEN 31 16 Description Reset Value When 1 enables an interrupt when a received start bit has 0 been detected When 1 enables an interrupt when a framing error has been 0 detected When 1 enables an interrupt when a parity error has been 0 detected When 1 enables an interrupt when noise is detected See 0 description of the RXNOISEINT bit in Table 175 Reserved Read value is undefined only zero should be NA written USART Interrupt Enable Clear register The INTENCLR register is used to clear bits in the INTENSET register Table 177 USART Interrupt Enable clear register INTENCLR address 0x4006 4010 USARTO 0x4006 8010 USART1 0x4006 C010 USART2 bit description Bit Symbol Description Reset Value 0 RXRDYCLR Writing 1 clears the corresponding bit in the INTENSET 0 register 1 Reserved Read value is undefined only zero should
257. as the source to bit slice 0 0x6 Input 6 Selects the pin selected in the PINTSEL6 register as the source to bit slice 0 0 7 Input 7 Selects the pin selected in the PINTSEL7 register as the source to bit slice 0 13 11 SRC1 Selects the input source for bit slice 1 0 0x0 Input 0 Selects the pin selected in the PINTSELO register as the source to bit slice 1 0 1 Input 1 Selects the pin selected in the PINTSEL1 register as the source to bit slice 1 0 2 Input 2 Selects the pin selected in the PINTSEL2 register as the source to bit slice 1 0x3 Input 3 Selects the pin selected in the PINTSELS register as the source to bit slice 1 0x4 Input 4 Selects the pin selected in the PINTSEL4 register as the source to bit slice 1 0x5 Input 5 Selects the pin selected in the PINTSELS5 register as the source to bit slice 1 0x6 Input 6 Selects the pin selected in the PINTSEL6 register as the source to bit slice 1 0 7 Input 7 Selects the pin selected in the PINTSEL7 register as the source to bit slice 1 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 108 of 370 NXP Semiconductors UM10601 Chapter 8 LPC81x Pin interrupts pattern match engine Table 104 Pattern match bit slice source register PMSRC address 0xA000 402C bit description Bit Symbol Value Description Reset value 16 14 SRC2 Selects the input source for bit
258. at makes the processor take an exception System clock clock SCT clock synced inputs processing prescaler s match capture registers inputs control logic generation event 5 T outputs Fig 15 SCTimer PWM block diagram UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 135 of 370 NXP Semiconductors U M1 0601 Chapter 10 LPC81x SCTimer PWM SCT CLKMODE CKSEL INSYNC SCT clock system clock input edges inputs preClock events LIMIT H select mux LIMIT L e mux prescaler H H counter counter H counter L Unified counter STOP START HALT prescaler L select STOP L START L HALT L e 1 L counter CTRL H CTRL L Fig 16 SCTimer PWM counter and select logic 10 6 Register description The register addresses of the State Configurable Timer are shown in Table 120 For most of the SCT registers the register function depends on the setting of certain other register bits 1 The UNIFY bit in the CONFIG register determines whether the SCT is used as one 32 bit register for operation as one 32 bit counter timer or as two 16 bit counter timers named L and H The setting of the UNIFY bit is reflected in the register map UNIFY 1
259. basis When task is completed the callback function is called I2C Slave Receive Polling Table 280 12C Slave Receive Polling Routine Prototype Input parameter Return Description I2C Slave Receive Polling ErrorCode ti2c slave receive poll I2C HANDLE T Il2C PARAM I2C RESULT I2C HANDLE T Handle to the allocated SRAM area I2C Pointer to the I2C PARAM struct I2C RESULT Pointer to the 12C RESULT struct ErrorCode Receives data from master When the task is completed the function returns to the line after the call All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 311 of 370 NXP Semiconductors U M1 0601 Chapter 24 LPC81x I2C bus ROM API 24 4 9 12 Slave Transmit Polling Table 281 12C Slave Transmit Polling Routine I2C Slave Transmit Polling Prototype ErrorCode_t i2c_slave_transmit_poll I2C_HANDLE_T l2C Il2C RESULT Input parameter 12C HANDLE T Handle to the allocated SRAM area I2C Pointer to the I2C PARAM struct I2C RESULT Pointer to the 12C RESULT struct Return ErrorCode Description Sends data bytes back to master When the task is completed the function returns to the line after the call 24 4 10 12 Slave Receive Interrupt Table 282 12C Slave Receive Interrupt Routine I2C Slave Receive Inte
260. be NA written 2 TXRDYCLR Writing 1 clears the corresponding bit in the INTENSET 0 register 4 3 Reserved Read value is undefined only zero should be NA written 5 DELTACTSCLR Writing 1 clears the corresponding bit in the INTENSET 0 register 6 TXDISINTCLR Writing 1 clears the corresponding bit in the INTENSET 0 register 7 Reserved Read value is undefined only zero should be NA written 8 OVERRUNCLR Writing 1 clears the corresponding bit in the INTENSET 0 register 10 9 Reserved Read value is undefined only zero should be NA written 11 DELTARXBRKCLR Writing 1 clears the corresponding bit in the INTENSET 0 register 12 STARTCLR Writing 1 clears the corresponding bit in the INTENSET 0 register 13 FRAMERRCLR Writing 1 clears the corresponding bit in the INTENSET 0 register UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 199 of 370 NXP Semiconductors U M1 0601 UM10601 15 6 6 15 6 7 Chapter 15 LPC81x USARTO 1 2 Table 177 USART Interrupt Enable clear register INTENCLR address 0x4006 4010 USARTO 0x4006 8010 USART1 0x4006 C010 USART2 bit description Bit Symbol Description Reset Value 14 PARITYERRCLR Writing 1 clears the corresponding bit in the INTENSET 0 register 15 RXNOISECLR Writing 1 clears the corresponding bit in the INTENSET 0 register 31 16 Reserved R
261. be asserted by this master on SCL Other devices on the bus masters or slaves could lengthen this time This corresponds to the parameter t ow in the 12C bus specification I C bus specification parameters tgur and tsu sta have the same values and are also controlled by MSTSCLLOW 0 0 2 clocks Minimum SCL low time is 2 clocks of the 12C clock pre divider 0x1 3 clocks Minimum SCL low time is clocks of the 12C clock pre divider 0x2 4 clocks Minimum SCL low time is 4 clocks of the 12C clock pre divider 0 3 5 clocks Minimum SCL low time is 5 clocks of the 12C clock pre divider 0x4 6 clocks Minimum SCL low time is 6 clocks of the 12C clock pre divider 0 5 7 clocks Minimum SCL low time is 7 clocks of the 12C clock pre divider 0 6 8 clocks Minimum SCL low time is 8 clocks of the 12C clock pre divider 0x7 9 clocks Minimum SCL low time is 9 clocks of the 12C clock pre divider 3 Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 224 of 370 NXP Semiconductors U M1 0601 UM10601 16 6 10 16 6 11 Chapter 16 LPC81x I2C bus interface Table 195 Master Time register MSTTIME address 0x4005 0024 bit description continued Bit Symbol Value Description Reset value 64 MSTSCLHIGH Master SCL High time Specifies the minimum high time 0 that will be asserted by th
262. bit clears the interrupt request 3 GFLAG3 Monitors the interrupt flag of TIMERS 0 0 No pending interrupt Writing a zero is equivalent to no operation 1 Pending interrupt The interrupt is pending because TIMER3 has reached the end of the time interval If the INTEN bit in the CONTROLS register is also set to 1 the interrupt for timer channel 3 and the global interrupt are raised Writing a 1 to this bit clears the interrupt request 31 4 Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 170 of 370 UM10601 Chapter 12 LPC81x Windowed Watchdog Timer WWDT Rev 1 6 2 April 2014 User manual 12 1 How to read this chapter 12 2 Features The watchdog timer is identical on all LPC81x parts Internally resets chip if not reloaded during the programmable time out period Optional windowed operation requires reload to occur between a minimum and maximum time out period both programmable Optional warning interrupt can be generated at a programmable time prior to watchdog time out Programmable 24 bit timer with internal fixed pre scaler Selectable time period from 1 024 watchdog clocks Twpcik x 256 x 4 to over 67 million watchdog clocks x 224 x 4 in increments of 4 watchdog clocks Safe watchdog operation Once enabled requires a hardware reset or a Watchdog res
263. bject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 238 of 370 NXP Semiconductors UM10601 Chapter 17 LPC81x SPIO 1 17 6 3 SPI Status register The STAT register provides SPI status flags for software to read and a control bit for forcing an end of transfer Flags other than read only flags may be cleared by writing ones to corresponding bits of STAT STAT contains 2 error flags in slave mode only RXOV TXUR These are receiver overrun and transmit underrun respectively If either of these errors occur during operation the SPI should be disabled then re enabled in order to make sure all internal states are cleared before attempting to resume operation In this register the following notation is used RO Read only W1 write 1 to clear Table 206 SPI Status register STAT addresses 0x4005 8008 SPIO 0x4005 C008 SPI1 bit description Bit Symbol 0 RXRDY 1 TXRDY 2 RXOV 3 TXUR 4 SSA 5 SSD 6 STALLED UM10601 Description Receiver Ready flag When 1 indicates that data is available to be read from the receiver buffer Cleared after a read of the RXDAT register Transmitter Ready flag When 1 this bit indicates that data may be written to the transmit buffer Previous data may still be in the process of being transmitted Cleared when data is written to TXDAT or TXDATCTL until the data is moved to the transmit shift register
264. bort LPC_I2C gt SLVCTL I2C SLVCTL SLVCONTINUE ack address while LPC_I2C gt STAT amp I2C STAT SLVPENDING if LPC_I2C gt STAT amp I2C STAT SLVSTATE I2C STAT SLVST RX abort subaddress LPC_I2C gt SLVDAT read subaddress if subaddress abort LPC_I2C gt SLVCTL I2C SLVCTL SLVCONTINUE continue transaction while LPC_I2C gt STAT amp I2C STAT SLVPENDING if LPC_I2C gt STAT amp I2C STAT SLVSTATE I2C STAT SLVST ADDR abort LPC_I2C gt SLVCTL I2C SLVCTL SLVCONTINUE ack address while LPC_I2C gt STAT amp I2C STAT SLVPENDING if LPC_I2C gt STAT amp I2C STAT SLVSTATE I2C STAT SLVSTX abort LPC_I2C gt SLVDAT data subaddress write data from subaddress LPC_I2C gt SLVCTL I2C SLVCTL SLVCONTINUE continue transaction 29 2 16 Slave nack matched address from master Table 322 12C Code example Slave nack matched address from master Address 0x23 Polling mode LPC I2C SLVADRO 0x23 lt lt 1 put address in address 0 register LPC_I2C gt CFG I2C SLVEN while LPC_I2C gt STAT amp I2C STAT SLVPENDING if LPC_I2C gt STAT amp I2C STAT SLVSTATE I2C STAT SLVST ADDR abort LPC_I2C gt SLVCTL I2C SLVCTL SLVNACK nack address 29 2 17 Slave nack data from master Table 323 12C Code example Slave nack data from master Address 0x23 Polling mode LPC_I2C
265. bus pins PIOO 10 and PIOO 11 which do not have a programmable pull up resistor UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 69 of 370 NXP Semiconductors U M1 0601 UM10601 6 4 4 6 4 5 6 4 6 6 4 7 Chapter 6 LPC81x I O configuration IOCON The repeater mode enables the pull up resistor if the pin is high and enables the pull down resistor if the pin is low This causes the pin to retain its last known state if it is configured as an input and is not driven externally Repeater mode may typically be used to prevent a pin from floating and potentially using significant power if it floats to an indeterminate state if it is temporarily not driven Open drain mode An open drain mode can be enabled for all digital I O pins that are not the I2C bus pins This mode is not a true open drain mode The input cannot be pulled up above Vpp Remark As opposed to the true open drain I2C bus pins digital pins with configurable open drain mode are not 5 V tolerant when Vpp 0 Analog mode The switch matrix automatically configures the pin in analog mode whenever an analog input or output is selected as the pin s function I2C bus mode The I C bus pins PIOO_10 and PIOO 11 can be programmed to support a true open drain mode independently of whether the 12C function is selected or another digital function If t
266. cation Remark On the DIP8 package the ISP entry pin location remains at pin PIOO 1 See Table 231 UART No changes 12C No changes Power No changes profiles UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 270 of 370 NXP Semiconductors U M1 0601 Chapter 21 LPC81x Boot ROM 21 4 Pin description When the ISP entry pin is pulled LOW on reset the part enters ISP mode and the ISP command handler starts up In ISP mode pin PIOO 0 is connected to function UO_RXD and pin PIOO 4 is connected to function UO TXD on the USARTO block Table 231 Pin location in ISP mode ISP entry USART RXD USART TXD Marking Bootloader Package version PIOO 1 PIOO 0 PIOO 4 1A v 13 1 TSSOP20 SO20 TSSOP16 DIP8 XSON16 PIOO 1 PIOO 0 PIOO 4 2A v 13 2 TSSOP20 SO20 TSSOP16 DIP8 XSON16 PIOO 1 PIOO 0 PIOO 4 4C and v 13 4 and DIP8 later later PIOO 12 PIOO 0 4 4C and v 13 4 and TSSOP20 SO20 later later XSON16 TSSOP16 21 5 General description UM10601 21 5 1 Boot loader The boot loader controls initial operation after reset and also provides the means to accomplish programming of the flash memory via USART This could be initial programming of a blank device erasure and re programming of a previously programmed device or programming of the flash memory by the application program in a running system The
267. ccurs when the specified match and l O condition occur simultaneously All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 152 of 370 NXP Semiconductors U M1 0601 Chapter 10 LPC81x SCTimer PWM SCT Table 143 SCT event control register 0 to 5 EV 0 5 CTRL address 0x5000 4304 EVO CTRL to 0x5000 432C EV5_CTRL bit description Bit Symbol Value Description Reset value 14 STATELD This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest numbered event occurring for that state 0 Add STATEV value is added into STATE the carry out is ignored 1 Load STATEV value is loaded into STATE 19 15 STATEV This value is loaded into or added to the state selected by HEVENT depending on STATELD when this event is the highest numbered event occurring for that state If STATELD and STATEV are both zero there is no change to the STATE value 20 MATCHMEM If this bit is one and the COMBMODE field specifies a match component to the triggering of this event then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up LESS THEN OR EQUAL TO the match value when counting down If this bit is zero a match is only be active during the cycle when the counter is equal to the match value
268. ch channel can be programmed with an independent time interval Each channel operates independently from the other channels in one of the following modes Repeat interrupt mode See Section 11 5 1 One shot interrupt mode See Section 11 5 2 Bus stall mode See Section 11 5 3 The modes for each timer are set in the timer s control register See Table 151 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 164 of 370 NXP Semiconductors UM1 0601 Chapter 11 LPC81x Multi Rate Timer MRT 1 DEC D Q IRQ_GEN IRQO TIMER INTVAL 5 a c o Le ee stat HI Wi IRQ 1 3 CHANNEL 1 3 Fig 23 MRT block diagram 11 5 1 Repeat interrupt mode The repeat interrupt mode generates repeated interrupts after a selected time interval This mode can be used for software based PWM or PPM applications When the timer n is in idle state writing a non zero value IVALUE to the INTVALn register immediately loads the time interval value IVALUE 1 and the timer begins to count down from this value When the timer reaches zero an interrupt is generated the value in the INTVALn register IVALUE 1 is reloaded automatically and the timer starts to count down again While the timer is running in repeat interrupt mode you can perform the following actions Change the interval value on t
269. clude the content of reserved bits Table 155 Register overview Watchdog timer base address 0x4000 4000 Name Access Address Description offset MOD R W 0x000 Watchdog mode register This TC R W FEED WO TV RO WARNINT R W WINDOW R W register contains the basic mode and status of the Watchdog Timer 0x004 Watchdog timer constant register This 24 bit register determines the time out value 0x008 Watchdog feed sequence register Writing OxAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC 0x00C Watchdog timer value register This 24 bit register reads out the current value of the Watchdog timer 0x010 Reserved 0x014 Watchdog Warning Interrupt compare value 0x018 Watchdog Window compare value Reset Reference value 0 Table 156 OxFF Table 158 NA Table 159 OxFF Table 160 0 Table 161 OxFF FFFF Table 162 Watchdog mode register The WDMOD register controls the operation of the Watchdog Note that a watchdog feed must be performed before any changes to the WDMOD register take effect Table 156 Watchdog mode register MOD 0x4000 4000 bit description Bit Symbol 0 WDEN 1 WDRESET 2 WDTOF Value Description Reset value Watchdog enable bit Once this bit has been written with 0 a 1 it cannot be re written with a 0 Once this bit is set to one the watchdog timer starts running after a watchdog feed 0 The watchdog timer is stopp
270. command is used to erase one or more sector s of on chip flash memory The boot block can not be erased using this command This command only allows erasure of all user sectors when the code read protection is enabled Example E 2 3 lt CR gt lt LF gt erases the flash sectors 2 and 3 22 5 1 10 Blank check sector s sector numbers end sector numbers Table 248 UART ISP Blank check sector command Command Input Start Sector Number End Sector Number Should be greater than or equal to start sector number Return Code CMD SUCCESS SECTOR NOT BLANK followed by Offset of the first non blank word location Contents of non blank word location INVALID SECTOR PARAM ERROR Description This command is used to blank check or more sectors of on chip flash memory Blank check on sector 0 always fails as first 64 bytes are re mapped to flash boot block When CRP is enabled the blank check command returns 0 for the offset and value of sectors which are not blank Blank sectors are correctly reported irrespective of the CRP setting Example 2 3 lt CR gt lt LF gt blank checks the flash sectors 2 and 3 22 5 1 11 Read Part Identification number Table 249 UART ISP Read Part Identification command Command J Input None Return Code CMD SUCCESS followed by part identification number in ASCII see Table 250 Description This command is used to read the part identification number Table 250 Part
271. cted by the CLKSEL field is detected The counter is enabled when the prescaler is enabled and PRELIM 0 or the prescaler is equal to the value in PRELIM An I O component of an event can occur any SCT clock when its counter HALT bit is 0 In general a Match component of an event can only occur in a UT clock when its counter HALT and STOP bits are both 0 and the counter is enabled Table 146 shows when the various kinds of events can occur Table 146 Event conditions COMBMODE IOMODE Event can occur on clock IO Any Event can occur whenever HALT 0 type A MATCH Any Event can occur when HALT 0 and STOP 0 and the counter is enabled type OR Any From the IO component Event can occur whenever HALT 0 A From the match component Event can occur when HALT 0 and STOP 0 and the counter is enabled C AND LOW or HIGH Event can occur when HALT 0 and STOP 0 and the counter is enabled C AND RISE or FALL Event can occur whenever HALT 0 A UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 157 of 370 NXP Semiconductors U M1 0601 10 7 9 10 7 10 10 7 10 1 10 7 10 2 UM10601 Chapter 10 LPC81x SCTimer PWM SCT SCT operation In its simplest single state configuration the SCT operates as an event controlled one or bidirectional counter Events can be configured to b
272. cted for output by a 1 in its port s DIR register If either or both of these conditions is are not met writing to the pin has no effect There are multiple ways to change GPIO output bits All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 94 of 370 NXP Semiconductors U M1 0601 UM10601 7 7 3 7 7 4 Chapter 7 LPC81x GPIO port Writing to a Byte Pin register loads the output bit from the least significant bit Writing to a Word Pin register loads the output bit with the OR of all of the bits written This feature follows the definition of truth of a multi bit value in programming languages Writing to a port s PORT register loads the output bits of all the pins written to Writing to a port s MPORT register loads the output bits of pins identified by zeros in corresponding positions of the port s MASK register Writing ones to a port s SET register sets output bits Writing ones to a port s CLR register clears output bits Writing ones to a port s NOT register toggles complements inverts output bits The state of a port s output bits can be read from its SET register Reading any of the registers described in Section 7 7 1 returns the state of pins regardless of their direction or alternate functions Masked I O A port s MASK register defines which of its pins should be accessible in
273. ctional divider value is programmed in the UARTFRGDIV register See Table 35 2 The MULT value programmed in this register is the numerator of the fractional divider value used by the fractional rate generator to create the fractional component to the baud rate See also Section 15 3 1 Configure the USART clock and baud rate Section 15 7 1 Clocking and Baud rates Table 36 USART fractional generator multiplier value register UARTFRGMULT address 0x4004 80F4 bit description Bit Symbol Description Reset value 7 0 MULT Numerator of the fractional divider MULT is equal to the programmed 0 value 318 Reserved External trace buffer command register This register works in conjunction with the MTB master register to start and stop tracing Also see Section 26 5 4 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 40 of 370 NXP Semiconductors U M1 0601 UM10601 4 6 21 4 6 22 4 6 23 Chapier 4 LPC81x System configuration SYSCON Table 37 External trace buffer command register EXTTRACECMD address 0x4004 80FC bit description Bit Symbol Description Reset value 0 START Trace start command Writing a one to this bit sets the TSTART signal 0 to the MTB to HIGH and starts tracing if the TSTARTEN bit in the MTB master register is set to one as well 1 STOP Trace stop command W
274. d Command Input Status code Result Description Blank check sector s Command code 53 decimal Param0 Start Sector Number Param1 End Sector Number should be greater than or equal to start sector number CMD_SUCCESS BUSY SECTOR_NOT_BLANK INVALID SECTOR Result0 Offset of the first non blank word location if the Status Code is SECTOR NOT BLANK Result Contents of non blank word location This command is used to blank check a sector or multiple sectors of on chip flash memory To blank check a single sector use the same Start and End sector numbers 22 5 2 5 Read Part Identification number IAP Table 261 IAP Read Part Identification command Command Input Status code Result Description Read part identification number Command code 54 decimal Parameters None CMD_SUCCESS Result0 Part Identification Number This command is used to read the part identification number 22 5 2 6 Read Boot code version number IAP Table 262 IAP Read Boot Code version number command Command Input Status code Result Description Read boot code version number Command code 55 decimal Parameters None CMD_SUCCESS Result0 2 bytes of boot code version number Read as lt byte1 Major gt lt byte0 Minor gt This command is used to read the boot code version number UM10601 All information provided in this document is subject to legal disclaimers NXP B V 201
275. d in an application reset USARTO see Table 19 before using the IAP command 57 Reinvoke ISP See Table 264 UART _ The following deviations from the specification apply UART synchronous mode not supported API functions uart put line and uart get line do not return an interrupt on error See Table 299 and Table 300 UART API return codes are numbered 0x0007 0001 to 0x0007 0005 12 No changes Power changes profiles v13 2 2A ISP IAP The following updates compared to v13 1 apply The IAP erase page command allows multiple page erase Any start page number that is smaller or equal to the end page number is allowed as start in the IAP erase page command See Table 266 Code SECTOR NOT PREPARED FOR WRITE OPERATION in ISP command C Write RAM to flash is returned See Table 245 AP command 57 Reinvoke ISP can be called without resetting USARTO first SP command S Read CRC checksum added See Table 254 UART The following updates compared to v13 1 apply e UART synchronous mode supported API functions uart put line and uart get line do return an interrupt on error See Table 299 and Table 300 UART API return codes are numbered 0x0008 0001 to 0x0008 0005 See Table 302 12 No changes Power No changes profiles v13 4 4C ISP IAP The following update compared to v13 2 applies ISP entry pin moved to PIOO 12 on TSSOP XSON SOP packages Boot loader updated to accommodate for the new ISP entry pin lo
276. d in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 21 of 370 NXP Semiconductors U M1 0601 Chapter 3 LPC81x Nested Vectored Interrupt Controller NVIC 3 4 10 Interrupt Priority Register 6 The IPR6 register controls the priority of four peripheral interrupts Each interrupt can have one of 4 priorities where 0 is the highest priority Table 14 Interrupt Priority Register 6 IPR6 address 0xE000 E418 bit description Bit Symbol Description 5 0 These bits ignore writes and read as O 7 6 IP_PININTO Interrupt Priority 0 highest priority 3 lowest priority 13 8 These bits ignore writes and read as 0 15 14 IP_PININT1 Interrupt Priority 0 highest priority 3 lowest priority 21 16 These bits ignore writes and read as 0 23 22 IP_PININT2 Interrupt Priority 0 highest priority 3 lowest priority 29 24 These bits ignore writes and read as 0 31 30 IP PININT3 Interrupt Priority 0 highest priority 3 lowest priority 3 4 11 Interrupt Priority Register 7 The IPR7 register controls the priority of four peripheral interrupts Each interrupt can have one of 4 priorities where 0 is the highest priority Table 15 Interrupt Priority Register 7 IPR7 address 0xE000 E41C bit description Bit Symbol Description 5 0 These bits ignore writes and read as O 7 6 IP_PININT4 Interrupt Priority 0 highest prior
277. d in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 319 of 370 NXP Semiconductors U M1 0601 UM10601 24 5 5 Chapter 24 LPC81x I2C bus ROM API 12 Slave Mode Transmit Receive In slave mode polled routines are intended for testing purposes It is up to the user to decide whether to use the polled or interrupt driven mode While operating the Slave driver in polled mode can be useful for program development and debugging most applications will need the interrupt driven versions of Slave Receive and Transmit in the final software The following routines are polled routines err code i2c slave receive poll I2C HANDLE T I2C PARAM I2C RESULT err code i2c slave transmit poll I2C HANDLE T I2C PARAM I2C RESULT The following routines are interrupt driven routines err code i2c slave receive intr I2C HANDLE T I2C PARAM I2C RESULT err code i2c slave transmit intr I2C HANDLE T I2C PARAM I2C RESULT Where err code is the return state of the function An 0 indicates success All non zero indicates an error Refer to the Error Code Table e 2C PARM is a structure with parameters passed to the function Section 24 4 22 2C RESULT is a containing the results after the function executes Section 24 4 22 To initiate a master mode write read the I2C_PARAM has to be setup The 2 PARAM is a structure with various var
278. d on pin PIOO 1 Disable CLKIN GPIO function PIOO 1 default or any other movable function can be assigned to pin CLKIN 8 VDDCMP Enables fixed pin function Writing a 1 deselects the function and any movable 1 function can be assigned to this pin By default the fixed pin function is deselected and GPIO is assigned to this pin 0 Enable VDDCMP This function is enabled on pin PIOO 6 Disable VDDCMP GPIO function PIOO 6 default or any other movable function can be assigned to pin PIOO 6 31 9 Reserved UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 132 of 370 UM10601 Chapter 10 LPC81x SCTimer PWM SCT Rev 1 6 2 April 2014 User manual 10 1 How to read this chapter The SCTimer PWM SCT is available on all LPC81x parts 10 2 Features Two 16 bit counters or one 32 bit counter Counters clocked by bus clock or selected input Up counters or up down counters State variable allows sequencing across multiple counter cycles The following conditions define an event a counter match condition an input or output condition a combination of a match and or and input output condition in a specified state and the count direction Events control outputs interrupts and the SCTimer states Match register 0 can be used as an automatic limit n bi directional mode events can
279. d one byte from slave Address 0x23 Polling mode No error checking LPC_I2C gt CFG whi if LPC_I2C gt S1 LPC_I2C gt MSTDAT LPC_I2C gt MS while LPC_ if LPC_I2C gt S1 data LPC_ LPC_I2C gt MS le LPC I2C 5STAT CTL 2 gt 2C gt MSTDAT re f data 0 abo CTL I2C MSTCTL while LPC_I2C gt STAT 12C CFG MSTEN AT amp I2C STAT 0x23 1 12C MSTCTL amp I2C 8 2C STAT AT amp t amp I2C_S if LPC I2C 5 1 AT amp I2C STAT STS 1 STS AT STSTAT ad data STS1 STSTAT E E E amp I2C STAT MSTPENDING l 2 STAT IDLE address and 1 for RWn bit ART send start TAT_MSTPENDING abort I2C STAT MSTST RX abort 0 send stop TAT_MSTPENDING I2C STAT MSTST IDLE abort 29 2 5 Table 311 12C Code example Master write one byte to subaddress on slave Master write one byte to subaddress on slave Address 0x23 subaddress 0xaa Data Oxdd Polling mode No error checking LPC_I2C gt CFG if LPC_1I2C gt S1 LPC_12C gt MSTDAI subaddress LPC_I2C gt MS while LPC if LPC_12C LPC_I2C gt MS LPC_I2C gt MS while LPC_ S 5 C C 1 DAT if LPC_I2C gt S1 2C gt MSTDAT LPC_I2C gt while LP if LPC I2 LPC_I2C gt MS whi LPC_ gt 51 TCTL 12C_MS1 I2C gt STAT amp CTL
280. d since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0 4 High level Match for this bit slice occurs when there is a high level on the input specified for this bit slice in the PMSRC register 0 5 Low level Match occurs when there is a low level on the specified input Ox6 Constant 0 This bit slice never contributes to a match should be used to disable any unused bit slices 0 7 Event Non sticky rising or falling edge Match occurs an event i e when either a rising or falling edge is first detected on the specified input this is a non sticky version of value 0x3 This bit is cleared after one clock cycle UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 115 of 370 NXP Semiconductors U M1 0601 Chapter 8 LPC81x Pin interrupts pattern match engine Table 105 Pattern match bit slice configuration register PMCFG address 0xA000 4030 bit description continued Bit Symbol Value Description Reset value 28 26 CFG6 Specifies the match contribution condition for bit slice 6 0b000 0x0 Constant HIGH This bit slice always contributes to a product term match 0 1 Sticky rising edge Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared
281. d such as setting up the BRG and typically also setting up the FRG See Figure 29 Fractional Rate Generator FRG The Fractional Rate Generator can be used to obtain more precise baud rates when the peripheral clock is not a good multiple of standard or otherwise desirable baud rates The FRG is typically set up to produce an integer multiple of the highest required baud rate or a very close approximation The BRG is then used to obtain the actual baud rate needed The FRG register controls the USART Fractional Rate Generator which provides the base clock for the USART The Fractional Rate Generator creates a lower rate output clock by suppressing selected input clocks When not needed the value of 0 can be set for the FRG which will then not divide the input clock The FRG output clock is defined as the inputs clock divided by 1 MULT 256 where MULT is in the range of 1 to 255 This allows producing an output clock that ranges from the input clock divided by 1 1 256 to 1 255 256 just more than 1 to just less than 2 Any further division can be done specific to each USART block by the integer BRG divider contained in each USART All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 203 of 370 NXP Semiconductors U M1 0601 Chapter 15 LPC81x USARTO 1 2 The base clock produced by the FRG cannot be perfectly symmetric
282. ddress 0x4000 4000 INTVALO to 0x4000 4030 INTVAL3 bit description Bit Symbol Value Description Reset value 30 0 IVALUE Time interval load value This value is loaded into the 0 TIMERn register and the MRTn starts counting down from IVALUE 1 If the timer is idle writing a non zero value to this bit field starts the timer immediately If the timer is running writing a zero to this bit field does the following If LOAD 1 the timer stops immediately f LOAD 0 the timer stops at the end of the time interval 31 LOAD Determines how the timer interval value IVALUE 1 is 0 loaded into the TIMERn register This bit is write only Reading this bit always returns 0 0 No force load The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected 1 Force load The INTVALn interval value IVALUE 1 is immediately loaded into the TIMERn register while TIMERn is running 11 6 2 Timer register The timer register holds the current timer value This register is read only Table 150 Timer register TIMER 0 3 address 0x4000 4004 TIMERO to 0x4000 4034 TIMER3 bit description Bit Symbol Description Reset value 30 0 VALUE Holds the current timer value of the down counter The initial value OX00FF of the TIMERn register is loaded as IVALUE 1 from the INTVALn FFFF register either at the end of the time interval or immediately in the f
283. dge Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0 2 Sticky falling edge Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0x3 Sticky rising or falling edge Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0x4 High level Match for this bit slice occurs when there is a high level on the input specified for this bit slice in the PMSRC register 0 5 Low level Match occurs when there is a low level on the specified input 0 6 Constant 0 This bit slice never contributes to a match should be used to disable unused bit slices 0 7 Event Non sticky rising or falling edge Match occurs on an event i e when either a rising or falling edge is first detected on the specified input this is a non sticky version of value 0x3 This bit is cleared after one clock cycle 13 11 CFG1 Specifies the match contribution condition for bit slice 1 0b000 0x0 Constant HIGH This bit slice always contributes to a product term match 0x1 Sticky
284. dient of an event is a selected input or output signal UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 151 of 370 NXP Semiconductors U M1 0601 Chapter 10 LPC81x SCTimer PWM SCT When the UNIFY bit is 0 each event is associated with a particular counter by the HEVENT bit in its event control register An event cannot occur when its related counter is halted nor when the current state is not enabled to cause the event as specified in its event mask register An event is permanently disabled when its event state mask register contains all Os An enabled event can be programmed to occur based on a selected input or output edge or level and or based on its counter value matching a selected match register STOP bit 0 An event can be enabled by the event counter s HALT bit and STATE register In bi directional mode events can also be enabled based on the direction of count Each event can modify its counter STATE value If more than one event associated with the same counter occurs in a given clock cycle only the state change specified for the highest numbered event among them takes place Other actions dictated by any simultaneously occurring events all take place Table 143 SCT event control register 0 to 5 EV 0 5 CTRL address 0x5000 4304 EVO CTRL to 0x5000 432C EV5 CTRL bit description Bit Symbol 3 0 MATC
285. dowed watchdog timer WARNINT watchdog warning interrupt interrupt 13 BOD IRQ BOD interrupts BODINTVAL BOD interrupt level 14 Reserved 15 WKT IRQ Self wake up timer interrupt ALARMFLAG 23 16 Reserved 24 PININTO_IRQ Pin interrupt 0 or pattern PSTAT pin interrupt status match engine slice 0 interrupt 25 PININT1_IRQ Pin interrupt 1 or pattern PSTAT pin interrupt status match engine slice 1 interrupt 26 PININT2_IRQ Pin interrupt 2 or pattern PSTAT pin interrupt status match engine slice 2 interrupt 27 PININT3_IRQ Pin interrupt 3 or pattern PSTAT pin interrupt status match engine slice 3 interrupt 28 PININT4_IRQ Pin interrupt 4 or pattern PSTAT pin interrupt status match engine slice 4 interrupt UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 13 of 370 NXP Semiconductors U M1 0601 Chapter 3 LPC81x Nested Vectored Interrupt Controller NVIC Table 3 Connection of interrupt sources to the NVIC Interrupt Name Description Flags number 29 PININT5 IRQ Pin interrupt 5 or pattern PSTAT pin interrupt status match engine slice 5 interrupt 30 PININT6_IRQ Pin interrupt 6 or pattern PSTAT pin interrupt status match engine slice 6 interrupt 31 PININT7_IRQ Pin interrupt 7 or pattern PSTAT pin interrupt status match engine slice 7 interrupt 3 3 2 Non Maskable Interrupt NMI The LPC81x support
286. dress 0x4006 4010 USARTO 0x4006 8010 USART 1 0x4006 C010 USART2 bit description 199 Table 178 USART Receiver Data register RXDAT address 0x4006 4014 USARTO 0x4006 8014 USART1 0x4006 C014 USART2 bit description 200 Table 179 USART Receiver Data with Status register RXDATSTAT address 0x4006 4018 USARTO 0x4006 8018 USART1 0x4006 C018 UM10601 All information provided in this document is subject to legal disclaimers Chapter 30 Supplementary information USART2 bit description 200 Table 180 USART Transmitter Data Register TXDAT address 0x4006 401C USARTO 0x4006 801C USART1 0x4006 C01C USART2 bit lt 201 Table 181 USART Baud Rate Generator register BRG address 0x4006 4020 USARTO 0x4006 8020 USART1 0x4006 C020 USART2 bit lt 202 Table 182 USART Interrupt Status register INTSTAT address 0x4006 4024 USARTO 0x4006 8024 USART1 0x4006 C024 USART2 bit lt 202 Table 183 I2C bus pin description 210 Table 184 Register overview I2C base address 0x4005 0000 peer as 213 Table 185 I2C Configuration register CFG address 0x4005 0000 bit description 213 Table 186 12 Status register STAT address 0x4005 0004 bit description
287. e a Configure the register map for match registers See Table 130 Configure one or more match registers with a match value See Table 138 b c For each match value create a match event See Table 143 d If you want to create an interrupt on a match event enable the event for interrupt See Table 135 e If you want to create a match output on a pin connect the CTOUTn function to a pin see Section 10 4 and select an output for the match event in the EVn_CTRL register See Table 143 The EVn_CTRL registers also control what type of output signal is created 4 If you need to capture a timer value on a capture signal a Configure the register map for capture registers See Table 130 b Create one or more capture events See Table 143 c Connect the CTIN functions to pins see Section 10 4 and configure the signal to create an event See Table 143 5 Start the timer by writing to the CRTL register See Table 122 6 Read the capture registers to read the timer value at the time of the capture events 10 4 Pin description The SCT inputs and outputs are movable functions and are assigned to external pins through the switch matrix See Section 9 3 1 Connect an internal signal to a package pin to assign the SCT functions to pins on the LPC81x package Table 119 SCT pin description Function CTIN 0 CTIN 1 CTIN 2 CTIN 3 CTOUT 0 CTOUT 1 CTOUT 2 CTOUT 3 Direction Pin any any any any any
288. e memories and the peripherals The system clock can be shut down completely by setting the DIV field to zero Table 29 System clock divider register SYSAHBCLKDIV address 0x4004 8078 bit description Bit Symbol Description Reset value 7 0 DIV System AHB clock divider values 0x01 0 System clock disabled 1 Divide by 1 to 255 Divide by 255 31 8 Reserved System clock control register The SYSAHBCLKCTRL register enables the clocks to individual system and peripheral blocks The system clock bit 0 provides the clock for the AHB the bridge the ARM Cortex M0 the SYSCON block and the PMU This clock cannot be disabled Table 30 System clock control register SYSAHBCLKCTRL address 0x4004 8080 bit description Bit Symbol Value Description Reset value 0 SYS Enables the clock for the AHB the APB bridge the 1 Cortex MO core clocks SYSCON and the PMU This bit is read only and always reads as 1 0 Reserved 1 Enable 1 ROM Enables clock for ROM 1 0 Disable 1 Enable 2 RAM Enables clock for SRAM 1 0 Disable 1 Enable 3 FLASHREG Enables clock for flash register interface 1 0 Disable 1 Enable 4 FLASH Enables clock for flash 1 0 Disable 1 Enable 5 l2C Enables clock for 12C 0 0 Disable 1 Enable All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 36 of 370 NXP Semiconductors UM10601
289. e 165 Counter register COUNT address 0x4000 800C bit description 182 Table 166 Register overview SysTick timer base address OxEO00 000 184 Table 167 SysTick Timer Control and status register SYST_CSR OxE000 E010 bit description 185 Table 168 System Timer Reload value register SYST RVR OxE000 E014 bit description 185 Table 169 System Timer Current value register SYST 0 000 E018 bit description 185 Table 170 System Timer Calibration value register SYST CALIB 0 000 E01C bit description 186 Table 171 USART pin description 190 Table 172 Register overview USART base address 0x4006 4000 USARTO 0x4006 8000 USART1 0x4006 C000 2 193 Table 173 USART Configuration register CFG address 0x4006 4000 USARTO 0x4006 8000 USART1 0x4006 C000 USART2 bit description 194 Table 174 USART Control register CTL address 0x4006 4004 USARTO 0x4006 8004 USART 1 0x4006 C004 USART2 bit description 196 Table 175 USART Status register STAT address 0x4006 4008 USARTO 0x4006 8008 USART 1 0x4006 C008 USART2 bit description 197 Table 176 USART Interrupt Enable read and set register INTENSET address 0x4006 400C USARTO 0x4006 800C USART1 0x4006 USART2 bit description 198 Table 177 USART Interrupt Enable clear register INTENCLR ad
290. e 45 Start logic 0 pin wake up enable register 0 STARTERPO address 0x4004 8204 bit description and Table 44 Pin interrupt select registers PINTSEL 0 7 address 0x4004 8178 PINTSELO to 0x4004 8194 PINTSEL7 bit description To enable external or internal signals to wake up the part from Deep sleep or Power down modes Table 46 Start logic 1 interrupt wake up enable register STARTERP1 address 0x4004 8214 bit description All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 57 of 370 NXP Semiconductors UM10601 Chapter 5 LPC81x Reduced power modes and Power Management To configure the USART to wake up the part Section 15 3 2 Configure the USART for wake up For configuring the self wake up timer Section 13 5 e Fora list of all wake up sources Table 54 Wake up sources for reduced power modes Table 54 Wake up sources for reduced power modes Power mode Wake up source Sleep Any interrupt Deep sleep and Pin interrupts Power down BOD interrupt BOD reset WWDT interrupt WWDT reset En En Self Wake up Timer WKT time out Interrupt from USART SPI I2C peripheral Conditions able interrupt in NVIC able pin interrupts in NVIC and STARTERPO registers Enable interrupt in NVIC and STARTERP registers Enable interrupt in BODCTRL register BOD po
291. e USART transmitter block accepts data written by the CPU and buffers the data in the transmit holding register When the transmitter is available the transmit shift register takes that data formats it and serializes it to the serial output Un_TXD The Baud Rate Generator block divides the incoming clock to create a 16x baud rate clock in the standard asynchronous operating mode The BRG clock input source is the shared Fractional Rate Generator that runs from the common USART peripheral clock U PCLK In synchronous slave mode data is transmitted and received using the serial clock directly In synchronous master mode data is transmitted and received using the baud rate clock without division Status information from the transmitter and receiver is saved and provided via the Stat register Many of the status flags are able to generate interrupts as selected by software Remark The fractional value and the USART peripheral clock are shared between all USARTs UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 191 of 370 NXP Semiconductors U M1 0601 Chapter 15 LPC81x USARTO 1 2 SYSCON block system clock U PCLK Transmitter main clock gt UARTCLKDIV me Holding Register Baud Rate and Clocking Generation Interrupt Generation Status USARTO interrupt Flow Control Break
292. e counter match events an input or output level transitions on an input or output pin or a combination of match and input output behavior In response to an event the SCT output or outputs can transition or the SCT can perform other actions such as creating an interrupt or starting stopping or resetting the counter Multiple simultaneous actions are allowed for each event Furthermore any number of events can trigger one specific action of the SCT An action or multiple actions of the SCT uniquely define an event A state is defined by which events are enabled to trigger an SCT action or actions in any stage of the counter Events not selected for this state are ignored In a multi state configuration states change in response to events A state change is an additional action that the SCT can perform when the event occurs When an event is configured to change the state the new state defines a new set of events resulting in different actions of the SCT Through multiple cycles of the counter events can change the state multiple times and thus create a large variety of event controlled transitions on the SCT outputs and or interrupts Once configured the SCT can run continuously without software intervention and can generate multiple output patterns entirely under the control of events To configure the SCT see Section 10 7 10 To start run and stop the SCT see Section 10 7 11 To configure the SCT as simple event controlled co
293. e oscillator pins and the external reset input Table 16 SYSCON pin description Function Direction Pin Description SWM register Reference CLKOUT O any CLKOUT clock output PINASSIGN8 Table 117 CLKIN PIOO 1 ACMP I2 CLKIN External clock input to the system PINENABLEO Table 118 PLL Disable the ACMP 12 function in the PINENABLE register XTALIN PIOO 8 XTALIN Input to the system oscillator PINENABLEO Table 118 XTALOUT O PIOO 9 XTALOUT Output from the system oscillator PINENABLEO Table 118 RESET RESET PIOO 5 External reset input PINENABLEO Table 118 4 5 General description 4 5 1 Clock generation The system control block generates all clocks for the chip Only the low power oscillator used for wake up timing is controlled by the PMU Except for the USART clock and the clock to configure the glitch filters of the digital I O pins the clocks to the core and peripherals run at the same frequency The maximum system clock frequency is 30 MHz See Figure 3 Remark The main clock frequency is limited to 100 MHz UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 25 of 370 NXP Semiconductors U M1 0601 Chapter 4 LPC81x System configuration SYSCON SYSCON AHB clock 0 core system main clock always on memories and peripherals peripheral clocks SYSAHBCLKCTRL 1 19 system clock enable r
294. e product term endpoints Bit slice 7 is an endpoint by default no associated register bit CFGO 000 high level on the selected input input 1 for bit slice 0 CFG1 000 high level on the selected input input 1 for bit slice 1 CFG2 000 high level on the selected input input 2 for bit slice 2 CFG3 101 low level on the selected input input 2 for bit slice 3 CFG4 101 low level on the selected input input 3 for bit slice 4 CFG5 010 sticky falling edge on the selected input input 6 for bit slice 5 CFG6 000 high level on the selected input input 5 for bit slice 6 CFG7 111 event any edge non sticky on the selected input input 7 for bit slice 7 PMCTRL register Table 103 UM10601 BitO Setting this bit will select pattern matches to generate the pin interrupts in place of the normal pin interrupt mechanism For this example pin interrupt 0 will be asserted when a match is detected on the first product term which in this case is just a high level on input 1 Pin interrupt 2 will be asserted in response to a match on the second product term Pin interrupt 5 will be asserted when there is a match on the third product term Pin interrupt 7 will be asserted on a match on the last term Bit1 Setting this bit will cause the RxEv signal to the ARM CPU to be asserted whenever a match occurs on ANY of the product terms in the expression Otherwise the RXEV line will not be used Bit31 24 At a
295. e start and stop nterrupt latency control Select a source for the NMI Calibrate system tick timer 4 3 Basic configuration UM10601 Configure the SYSCON block as follows The SYSCON uses the CLKIN CLKOUT RESET and XTALIN OUT pins Configure the pin functions through the switch matrix See Section 4 4 Noclock configuration is needed The clock to the SYSCON block is always enabled By default the SYSCON block is clocked by the IRC 4 3 1 Set up the PLL The PLL creates a stable output clock at a higher frequency than the input clock If you need a main clock with a frequency higher than the 12 MHz IRC clock use the PLL to boost the input frequency 1 Power up the system PLL in the PDRUNCFG register Section 4 6 32 Power configuration register All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 23 of 370 NXP Semiconductors U M1 0601 UM10601 Chapter 4 LPC81x System configuration SYSCON Select the PLL input in the SYSPLLCLKSEL register You have the following input options IRC 12 MHz internal oscillator System oscillator External crystal oscillator using the XTALIN XTALOUT pins External clock input CLKIN Select this pin through the switch matrix Section 4 6 8 System PLL clock source select register Update the PLL clock source in the SYSPLLCLKUEN register
296. e up from Deep sleep or Power down 15 6 8 USART Transmitter Data Register 201 node ceased ace wee he ees 190 15 6 9 USART Baud Rate Generator register 202 15 4 __ 190 15 6 10 USART Interrupt Status register 202 15 5 General 191 15 7 Functional description 203 p 15 6 Register description 193 15 7 1 Clocking and Baud 203 15 6 1 USART Configuration register 194 15 7 1 1 Fractional Rate Generator FRG 203 15 6 2 USART Control 195 15 712 Baud Rate Generator 204 15 63 USART Status 197 15 7 1 3 Baud rate calculations 204 1564 USART Interrupt Enable read and set 15 7 2 Synchronous mode 204 register isses eee 198 15 7 3 Flow 204 15 6 5 USART Interrupt Enable Clear register 199 15 7 3 1 Hardware flow control 204 15 6 6 USART Receiver Data register 200 15 7 3 2 Software flow control 205 Chapter 16 LPC81x I2C bus interface 16 1 How to read this chapter 206 16 6 6 I2C Clock Divider register 222 16 2 Features 206 16 6 7 I2C Interrupt Status register 222 16 3 __
297. e update enable register 38 4 2 Features 23 4 6 17 CLKOUT clock divider register 39 4 3 Basic configuration 23 4 6 18 pid fractional generator divider value 39 ASA 23 E NU NAE AERA 4 3 2 Configure the main clock and system clock 24 46 19 aa generator multiplier value 40 etd E ME id hd 24 4 6 20 External trace buffer command register 40 i AM 4 6 21 POR captured PIO status register O 41 4 4 Pin lt 25 4 6 22 IOCON glitch filter clock divider registers 6 4 5 General 25 Eom O 41 4 5 1 Clock 25 4 6 0 control register 41 4 5 2 Power control of analog components 26 4 6 24 System tick counter calibration register 42 4 5 3 Configuration of reduced power modes 27 4 6 05 IRQ latency 42 4 5 4 Reset interrupt control 27 4 6 26 NMI source selection register 43 4 6 Register description 27 4 6 27 Pin interrupt select registers 43 4 6 1 System memory remap register 29 4 6 28 Start logic 0 pin wake up enable register 44 4 6 2 Peripheral reset control register 29 4 6 29 Start logic 1 interrupt wake up enable
298. e used in a system running at the main and system clock of 30 MHz with a need for maximum CPU processing power Since the specified 40 MHz clock is above the 30 MHz maximum set power returns PWR INVALID FREQ in result 0 without changing anything in the existing power setup An applicable power setup command 0 24 command 1 CPU EFFICIENCY command 2 24 LPC PWRD API set power command result The above code specifies that an application is running at the main and system clock of 24 MHz with emphasis on efficiency set power returns CMD SUCCESS in result 0 after configuring the microcontroller s internal power control features All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 305 of 370 UM10601 Chapter 24 LPC81x I2C bus ROM API Rev 1 6 2 April 2014 User manual 24 1 How to read this chapter The I2C bus ROM is available on all LPC81x parts 24 2 Features Simple I2C drivers to send and receive data on the I2C bus Polled and interrupt driven receive and transmit functions for master and slave modes 24 3 General description The drivers are callable for use by any application program to send or receive data on the I2C bus With the 12 drivers it is easy to produce working projects using the 12C interface The ROM routines allow the user to operate the I2
299. ead value is undefined only zero should be NA written USART Receiver Data register The RXDAT register contains the last character received before any overrun Remark Reading this register changes the status flags in the RXDATSTAT register Table 178 USART Receiver Data register RXDAT address 0x4006 4014 USARTO 0x4006 8014 USART1 0x4006 C014 USART2 bit description Bit Symbol Description Reset Value 8 0 RXDATA The USART Receiver Data register contains the next received 0 character The number of bits that are relevant depends on the USART configuration settings 31 9 Reserved the value read from a reserved bit is not defined NA USART Receiver Data with Status register The RXDATSTAT register contains the next complete character to be read and its relevant status flags This allows getting all information related to a received character with one 16 bit read Remark Reading this register changes the status flags Table 179 USART Receiver Data with Status register RXDATSTAT address 0x4006 4018 USARTO 0x4006 8018 USART1 0x4006 C018 USART2 bit description Bit Symbol Description Reset Value 8 0 RXDATA The USART Receiver Data register contains the next received 0 character The number of bits that are relevant depends on the USART configuration settings 12 9 Reserved the value read from a reserved bit is not defined NA 13 FRAMERR Framing Error status flag This bit is valid wh
300. eared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0 2 Sticky falling edge Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0x3 Sticky rising or falling edge Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0 4 High level Match for this bit slice occurs when there is a high level on the input specified for this bit slice in the PMSRC register 0 5 Low level Match occurs when there is a low level on the specified input 0 6 Constant 0 This bit slice never contributes to a match should be used to disable unused bit slices 0 7 Event Non sticky rising or falling edge Match occurs on an event i e when either a rising or falling edge is first detected on the specified input this is a non sticky version of value 0x3 This bit is cleared after one clock cycle UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 116 of 370 NXP Semiconductors U M1 0601 Chapter 8 LPC81x Pin interrupts pattern match engine 8 7 Functional description UM1
301. eate the fractional component of U_PCLK 2 The MULT value of the fractional divider is programmed in the UARTFRGMULT register See Table 36 Remark To use of the fractional baud rate generator you must write OxFF to this register to yield a denominator value of 256 All other values are not supported See also Section 15 3 1 Configure the USART clock and baud rate Section 15 7 1 Clocking and Baud rates All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 39 of 370 NXP Semiconductors U M1 0601 4 6 19 4 6 20 UM10601 Chapter 4 LPC81x System configuration SYSCON Table 35 USART fractional generator divider value register UARTFRGDIV address 0x4004 80F0 bit description Bit Symbol Description Reset value 7 0 DIV Denominator of the fractional divider DIV is equal to the programmed 0 value 1 Always set to OxFF to use with the fractional baud rate generator 31 8 Reserved 2 USART fractional generator multiplier value register All USART peripherals share a common clock U_PCLK which can be adjusted by a fractional divider U PCLK UARTCLKDIV 1 MULT DIV UARTCLKDIV is the USART clock configured in the UARTCLKDIV register The fractional portion 1 MULT DIV is determined by the two USART fractional divider registers in the SYSCON block 1 The DIV denominator of the fra
302. ected 0 2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 1543 CLK_DIV Select peripheral clock divider for input filter sampling clock 0 Value 0 7 is reserved 0 0 IOCONCLKDIVO 0 1 IOCONCLKDIV1 0 2 IOCONCLKDIV2 0x3 IOCONCLKDIV3 0x4 IOCONCLKDIVA 0x5 IOCONCLKDIV5 0 6 IOCONCLKDIVE6 31 16 Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 83 of 370 NXP Semiconductors UM10601 6 5 13 PIOO 9 register Chapter 6 LPC81x I O configuration IOCON Table 74 9 register PIOO 9 address 0x4004 4034 bit description Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 0x0 Inactive no pull down pull up resistor enabled 0 1 Pull down resistor enabled 0 2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled Remark This is not a true open drain mode 12 11 5 MODE Digital filter sample mode 0 0x0 Bypass inp
303. ects a peripheral interrupt as source for the NMI interrupt of the ARM Cortex M0 core For a list of all peripheral interrupts and their IRQ numbers see Table 3 For a description of the NMI functionality see Section 3 3 2 Remark When you want to change the interrupt source for the NMI you must first disable the NMI source by setting bit 31 in this register to 0 Then change the source by updating the IRQN bits and re enable the NMI source by setting bit 31 to 1 Table 43 NMI source selection register NMISRC address 0x4004 8174 bit description Bit Symbol Description Reset value 4 0 IRQN The IRQ number of the interrupt that acts as the Non Maskable Interrupt 0 NMI if bit 31 is 1 See Table 3 for the list of interrupt sources and their IRQ numbers 30 5 Reserved 31 NMIEN Write a 1 to this bit to enable the Non Maskable Interrupt NMI source 0 selected by bits 4 0 Remark If the NMISRC register is used to select an interrupt as the source of Non Maskable interrupts and the selected interrupt is enabled one interrupt request can result in both a Non Maskable and a normal interrupt This can be avoided by disabling the normal interrupt in the NVIC Pin interrupt select registers Each of these 8 registers selects one pin from all digital pins as the source of a pin interrupt or as the input to the pattern match engine To select a pin for any of the eight pin interrupts or pattern match engine inputs write the GPI
304. ed 1 The watchdog timer is running Watchdog reset enable bit Once this bit has been 0 written with a 1 it cannot be re written with a 0 A watchdog time out will not cause a chip reset A watchdog time out will cause a chip reset Watchdog time out flag Set when the watchdog timer 0 only times out by a feed error or by events associated with after WDPROTECT Cleared by software Causes a chip external reset if WDRESET 1 All information provided in this document is subject to legal disclaimers reset NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 175 of 370 NXP Semiconductors U M1 0601 Chapter 12 LPC81x Windowed Watchdog Timer WWDT Table 156 Watchdog mode register MOD 0x4000 4000 bit description Bit Symbol Value Description Reset value 3 WDINT Warning interrupt flag Set when the timer reaches the 0 value in WOWARNINT Cleared by software 4 WDPROTECT Watchdog update mode This bit can be set once by 0 software and is only cleared by a reset 0 The watchdog time out value TC can be changed at any time 1 The watchdog time out value TC can be changed only after the counter is below the value of WOWARNINT and WDWINDOW 5 LOCK 1 in this bit prevents disabling or powering down the 0 watchdog oscillator This bit can be set once by software and is only cleared by any reset 31 6 Reserved user software should not write ones to NA reserved bits
305. ed Enabled Enable the low power oscillator in Deep power down mode Setting this bit 0 causes the low power oscillator to remain running during Deep power down mode provided that bit 2 in this register is set as well You must set this bit for the self wake up timer to be able to wake up the part from Deep power down mode 3 LPOSCDPDEN Remark Do not set this bit unless you use the self wake up timer to wake up from Deep power down mode 0 Disabled 1 Enabled 31 4 Data retained during Deep power down mode 0x0 5 7 Functional description 5 7 1 Power management The LPC81x support a variety of power control features In Active mode when the chip is running power and clocks to selected peripherals can be optimized for power consumption In addition there are four special modes of processor power reduction with different peripherals running Sleep mode Deep sleep mode Power down mode and Deep power down mode UM10601 Table 59 Peripheral configuration in reduced power modes Peripheral Sleep mode Deep sleep Power down Deep mode mode power down mode IRC software configurable off off IRC output software configurable off off off Flash software configurable on off off BOD software configurable software software off configurable configurable PLL software configurable off off off SysOsc software configurable off off off WDosc WWDT software configurable software software off configurable configurable
306. ed HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled Remark This is not a true open drain mode 12 11 5 MODE Digital filter sample mode 0 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than one filter clock are rejected 0 2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 1543 CLK_DIV Select peripheral clock divider for input filter sampling clock 0 Value 0 7 is reserved 0 0 IOCONCLKDIVO 0 1 IOCONCLKDIV1 0 2 IOCONCLKDIV2 0x3 IOCONCLKDIV3 0 4 IOCONCLKDIVA 0x5 IOCONCLKDIV5 0 6 IOCONCLKDIVE6 31 16 Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 87 of 370 NXP Semiconductors UM10601 6 5 17 PIOO_0 register Chapter 6 LPC81x I O configuration IOCON Table 78 PIOO_0 register PIOO 0 address 0x4004 4044 bit description Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor 0b10 control 0x0 Inactive no pull down pull up resistor enabled 0 1 Pull down resistor enabled 0 2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Inp
307. ed configurations settings for 0 the Monitor function are not changed but the Monitor function is internally reset Disabled The I2C monitor function is disabled Enabled The 12C monitor function is enabled I C bus Time out Enable When disabled the time out 0 function is internally reset Disabled Time out function is disabled Enabled Time out function is enabled Both types of time out flags will be generated and will cause interrupts if they are enabled Typically only one time out will be used in a system Monitor function Clock Stretching 0 Disabled The monitor function will not perform clock stretching Software may not always be able to read data provided by the monitor function before it is overwritten This mode may be used when non invasive monitoring is critical Enabled The monitor function will perform clock stretching in order to ensure that software can read all incoming data supplied by the monitor function Reserved Read value is undefined only zero should be written All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 214 of 370 NXP Semiconductors UM10601 Chapter 16 LPC81x I2C bus interface 16 6 2 12 Status register The STAT register provides status flags and state information about all of the functions of the 12 block Some information in this register is read on
308. ed Slave Address n is ignored 7 1 SLVADR Seven bit slave address that is compared to received 0 addresses if enabled 31 8 Reserved Read value is undefined only zero should be NA written 16 6 14 Slave address Qualifier 0 register The SLVQUALO register can alter how Slave Address 0 is interpreted UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 227 of 370 NXP Semiconductors U M1 0601 UM10601 16 6 15 Chapter 16 LPC81x I2C bus interface Table 200 Slave address Qualifier 0 register SLVQUALO address 0x4005 0058 bit description Bit Symbol Value Description Reset Value 0 QUALMODEO Reserved Read value is undefined only zero should be 0 written 0 The SLVQUALO field is used as a logical mask for matching address 0 1 The SLVQUALO field is used to extend address 0 matching in a range of addresses 7 1 SLVQUALO Slave address Qualifier for address 0 A value of 0 causes 0 the address in SLVADRO to be used as is assuming that itis enabled If QUALMODEO 0 bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADRO register If QUALMODEO 1 an address range is matched for address 0 This range extends from the value defined by SLVADRO to the address defined by SLVQUALO address matches when SLVADRO 7
309. edundancy Check CRC engine Table 223 CRC checksum register SUM address 0x5000 0008 bit description Bit Symbol Description Reset value 31 0 SUM most recent CRC sum can be read through this 0x0000 FFFF register with selected bit order and 1 s complement post processes 19 6 4 CRC data register This register is a Write only register containing the data block for which the CRC sum will be calculated Table 224 CRC data register WR DATA address 0 5000 0008 bit description Bit Symbol 31 0 CRC WR DATA Description Reset value Data written to this register will be taken to perform calculation with selected bit order and 1 s complement pre process Any write size 8 16 or 32 bit are allowed and accept back to back transactions 19 7 Functional description UM10601 19 7 1 The following sections describe the register settings for each supported CRC standard CRC CCITT set up Polynomial x16 x12 x5 1 Seed Value OxFFFF Bit order reverse for data input NO 1 s complement for data input NO Bit order reverse for CRC sum NO 1 s complement for CRC sum NO MODE 0x0000 0000 SEED 0x0000 FFFF 19 7 2 CRC 16 set up Polynomial x16 x15 2 1 Seed Value 0x0000 Bit order reverse for data input YES 1 s complement for data input NO Bit order reverse for CRC sum YES 1 s complement for CRC sum NO CRC_MODE 0x0000 0015 CRC_SEED 0x000
310. en there is a character 0 to be read in the RXDAT register and reflects the status of that character This bit will set when the character in RXDAT was received with a missing stop bit at the expected location This could be an indication of a baud rate or configuration mismatch with the transmitting source All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 200 of 370 NXP Semiconductors U M1 0601 Chapter 15 LPC81x USARTO 1 2 Table 179 USART Receiver Data with Status register RXDATSTAT address 0x4006 4018 USARTO 0x4006 8018 USART1 0x4006 C018 USART2 bit description Bit Symbol Description Reset Value 14 PARITYERR Parity Error status flag This bit is valid when there is a character to 0 be read in the RXDAT register and reflects the status of that character This bit will be set when a parity error is detected in a received character 15 RXNOISE Received Noise flag See description of the RxNoiselnt bit in 0 Table 175 31 16 Reserved the value read from a reserved bit is not defined NA 15 6 8 USART Transmitter Data Register The TXDAT register is written in order to send data via the USART transmitter That data will be transferred to the transmit shift register when it is available and another character may then be written to TXDAT Table 180 USART Transmitter Data Register TXDAT address 0x40
311. ending set 0 Interrupt Clear Pending Register 0 register The ICPRO register allows clearing the pending state of the peripheral interrupts or for reading the pending state of those interrupts Set the pending state of interrupts through the ISPRO register Section 3 4 3 The bit description is as follows for all bits in this register Write Writing O has no effect writing 1 changes the interrupt state to not pending Read 0 indicates that the interrupt is not pending 1 indicates that the interrupt is pending Table 8 Interrupt clear pending register 0 register ICPRO address 0xE000 E280 bit description Bit Symbol Function Reset value 0 ICP_SPIO Interrupt pending clear 0 1 ICP_SPI1 Interrupt pending clear 0 2 Reserved 3 ICP_UARTO Interrupt pending clear 0 4 ICP_UART1 Interrupt pending clear 0 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 18 of 370 NXP Semiconductors UM10601 Chapter 3 LPC81x Nested Vectored Interrupt Controller NVIC Table 8 Interrupt clear pending register 0 register ICPRO address 0xE000 E280 bit description continued 23 16 24 25 26 27 28 29 30 31 Symbol ICP_UART2 ICP I2C ICP SCT ICP MRT ICP ICP WDT ICP BOD ICP FLASH ICP WKT ICP PININTO ICP PININT1 ICP PININT2 ICP PININT3 ICP_PININT4 ICP_PININT
312. entered Remark Hardware forces the analog blocks to be powered down in Deep sleep and Power down modes An exception are the BOD and watchdog oscillator which can be configured to remain running through this register The WDTOSC PD value written to the PDSLEEPCFG register is overwritten if the LOCK bit in the WWDT MOD register see Table 156 is set See Section 12 5 3 for details Table 47 Deep sleep configuration register PDSLEEPCFG address 0x4004 8230 bit description Bit Symbol Value Description Reset value 2 0 Reserved 0b111 3 BOD_PD BOD power down control for Deep sleep and 1 Power down mode 0 Powered 1 Powered down 5 4 Reserved 11 WDTOSC_PD Watchdog oscillator power down control for 1 Deep sleep and Power down mode Changing this bit to powered down has no effect when the LOCK bit in the WWDT MOD register is set In this case the watchdog oscillator is always running 0 Powered 1 Powered down 15 7 Reserved 06111111111 31 16 Reserved 0 Wake up configuration register This register controls the power configuration of the device when waking up from Deep sleep or Power down mode All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 46 of 370 NXP Semiconductors U M1 0601 UM10601 4 6 32 Chapter 4 LPC81x System configuration SYSCON Table 48 Wake up configuration register PDAWAKEC
313. er 170 11 5 2 One shot interrupt mode 166 11 5 3 One shot bus stall mode 166 Chapter 12 LPC81x Windowed Watchdog Timer WWDT 12 1 How to read this chapter 171 12 5 3 2 Changing the WWDT reload value 174 12 2 Features 171 12 6 Register description 175 123 Basic 171 12 6 1 Watchdog mode register 175 12 4 Pin 171 12 6 2 Watchdog Timer Constant register 177 ijr 12 6 3 Watchdog Feed register 177 i 1 p tar ool rd 55 Me 12 6 4 Watchdog Timer Value register 178 Dus hie sche UE ARM LL EE 12 6 5 Watchdog Timer Warning Interrupt register 178 12 5 2 Clocking and power control 173 12 6 6 Watchdog Timer Window reaister 178 12 5 3 Using the WWDT lock features 174 p 9 nn EE 12 5 3 1 Disabling the WWDT clock ig 1er BSCDRUDIEs 19 Chapter 13 LPC81x Self wake up timer WKT 13 1 How to read this 180 13 5 General description 180 13 2 Features cessi cde RR xx 180 13 51 clock sources 180 13 3 Basic 180 13 6 Register 181 13 4 Pin
314. er 347 29 2 Code examples 2 340 29 2 17 Slave nack data from master 347 29 2 1 lt 340 29 3 Code examples 348 29 2 2 Interrupt 341 29 3 1 Definitlons ii bem Lee bald 348 29 2 3 Master write one byte to slave 341 29 3 2 Interrupt handler 348 29 2 4 Master read one byte from slave 342 29 3 3 Transmit one byte to slave 0 349 29 2 5 Master write one byte to subaddress on 29 3 4 Receive one byte from slave 0 349 Slave MEE RI ep 342 29 3 5 Transmit and receive a byte to from slave 0 349 29 2 6 Master read one byte from subaddress on 29 3 6 Transmit and receive 24 bits to from slave 0 350 SlaVG m exem eed e ws 343 29 3 7 Transmit and receive 24 bits to from slave 0 29 2 7 Master receiving nack on address 343 interrupt 350 29 2 8 Master receiving nack ondata 344 29 3 8 Transmit 8 bits to master 350 29 2 9 Master sending nack and stop on data 344 29 3 9 Receive 8 bits to master 350 29 2 10 Master sending nack and repeated start on 29 3 10 Transmit and receive 24 bits to master 351 345 294 Code examples UART 351 29 2 11 Master sending nack and repeated start data 99 4 1
315. er This will be the value of the CTS input pin unless loopback mode is enabled This bit is set when a change in the state is detected for the CTS flag above 0 This bit is cleared by software Transmitter Disabled Interrupt flag When 1 this bit indicates that the USART 0 transmitter is fully idle after being disabled via the TXDIS in the CFG register TXDIS 1 Reserved Read value is undefined only zero should be written NA Overrun Error interrupt flag This flag is set when a new character is received 0 while the receiver buffer is still in use If this occurs the newly received character in the shift register is lost Reserved Read value is undefined only zero should be written NA Received Break This bit reflects the current state of the receiver break 0 detection logic It is set when the Un RXD pin remains low for 16 bit times Note that FRAMERRINT will also be set when this condition occurs because the stop bit s for the character would be missing RXBRK is cleared when the Un RXD pin goes high This bit is set when a change in the state of receiver break detection occurs 0 Cleared by software This bit is set when a start is detected on the receiver input Its purpose is 0 primarily to allow wake up from Deep sleep or Power down mode immediately when start is detected Cleared by software Framing Error interrupt flag This flag is set when a character is received with 0 a missing stop bit at the expected loca
316. er records events Writing ones to this register clears the corresponding flags and negates the SCT interrupt request if all enabled Flag bits are zero Table 135 SCT event flag register EVFLAG address 0x5000 40F4 bit description Bit Symbol Description Reset value 5 0 FLAG Bit is one if event has occurred since reset or a 1 was last written to 0 this bit event 0 bit 0 event 1 bit 1 event 5 bit 5 31 6 Reserved SCT conflict enable register This register enables the no change conflict events specified in the SCT conflict resolution register to request an IRQ All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 148 of 370 NXP Semiconductors U M1 0601 UM10601 10 6 17 10 6 18 Chapter 10 LPC81x SCTimer PWM SCT Table 136 SCT conflict enable register CONEN address 0x5000 40F8 bit description Bit Symbol Description Reset value 3 0 The SCT requests interrupt when bit n of this register andthe SCT 0 conflict flag register are both one output 0 bit 0 output 1 bit 1 output 3 bit 3 31 4 Reserved SCT conflict flag register This register records interrupt enabled no change conflict events and provides details of a bus error Writing ones to the NCFLAG bits clears the corresponding read bits and negates the SCT interrupt request if all enabled F
317. errupt mode is edge sensitive PMODE 0 the rising edge interrupt is enabled Ifthe pin interrupt mode is level sensitive PMODE 1 the level interrupt is enabled The IENF register configures the active level HIGH or LOW for this interrupt Table 94 Pin interrupt level or rising edge interrupt enable register IENR address 0xA000 4004 bit description Bit Symbol Description Reset Access value 7 0 ENRL Enables the rising edge or level interrupt for each pin 0 R W interrupt Bit n configures the pin interrupt selected in PINTSELn 0 Disable rising edge or level interrupt 1 Enable rising edge or level interrupt 31 8 Reserved Pin interrupt level or rising edge interrupt set register For each of the 8 pin interrupts selected in the PINTSELn registers see Section 4 6 27 one bit in the SIENR register sets the corresponding bit in the IENR register depending on the pin interrupt mode configured in the ISEL register e f the pin interrupt mode is edge sensitive PMODE 0 the rising edge interrupt is set e f the pin interrupt mode is level sensitive PMODE 1 the level interrupt is set Table 95 Pin interrupt level or rising edge interrupt set register SIENR address 0xA000 4008 bit description Bit Symbol Description Reset Access value 7 0 SETENRL Ones written to this address set bits in the IENR thus NA WO enabling interrupts Bit n sets bit n in the IENR register 0 No operation 1
318. ers is high 6 Reserved Read value is undefined only zero should be written NA 7 LOOP Loopback mode enable Loopback mode applies only to Master mode and connects 0 transmit and receive data connected together to allow simple software testing 0 Disabled 1 Enabled 8 SPOL SSEL Polarity select 0 0 Low The SSEL pin is active low The value in the SSEL fields of the RXDAT TXDATCTL and TXCTL registers related to SSEL is not inverted relative to the pins 1 High The SSEL pin is active high The value in the SSEL fields of the RXDAT TXDATCTL and TXCTL registers related to SSEL is inverted relative to the pins 31 9 Reserved Read value is undefined only zero should be written NA UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 237 of 370 NXP Semiconductors U M1 0601 Chapter 17 LPC81x SPIO 1 17 6 2 SPI Delay register The DLY register controls several programmable delays related to SPI signalling These delays apply only to master mode and are all stated in SPI clocks Timing details are shown in Section 17 7 2 1 Pre delay and Post delay Section 17 7 2 2 Frame delay Section 17 7 2 3 Transfer delay Table 205 SPI Delay register DLY addresses 0x4005 8004 SPIO 0x4005 C004 SPI1 bit description Bit Symbol Description Reset value 3 0 PRE DELAY Controls the amount of ti
319. erved User manual Rev 1 6 2 April 2014 294 of 370 NXP Semiconductors U M1 0601 Chapter 22 LPC81x Flash ISP and IAP programming Table 267 IAP Status codes Summary Status Mnemonic Description Code 3 DST_ADDR_ERROR Destination address is not on a correct boundary 4 SRC_ADDR_NOT_MAPPED Source address is not mapped in the memory map Count value is taken in to consideration where applicable 5 DST_ADDR_NOT_MAPPED Destination address is not mapped in the memory map Count value is taken in to consideration where applicable 6 COUNT_ERROR Byte count is not multiple of 4 or is not a permitted value INVALID SECTOR Sector number is invalid SECTOR NOT BLANK Sector is not blank 9 SECTOR NOT PREPARED Command to prepare sector for write operation was FOR WRITE OPERATION not executed 10 COMPARE ERROR Source and destination data is not same 11 BUSY Flash programming hardware interface is busy 22 6 Functional description UM10601 22 6 1 22 6 1 1 22 6 1 2 22 6 1 3 22 6 2 22 6 2 1 UART Communication protocol UART ISP commands should be sent as single ASCII strings Strings should be terminated with Carriage Return CR and or Line Feed LF control characters Extra CR and lt LF gt characters are ignored All ISP responses are sent as lt CR gt lt LF gt terminated ASCII strings Data is sent and received in plain binary format UART ISP command format Command Parameter
320. erved 0x0 IOCONCLKDIVO 0 1 IOCONCLKDIV1 0 2 IOCONCLKDIV2 0x3 IOCONCLKDIVS 0 4 IOCONCLKDIV4 0 5 IOCONCLKDIV5 0x6 IOCONCLKDIV6 31 16 Reserved UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 79 of 370 NXP Semiconductors UM10601 6 5 9 PIOO 10 register Chapter 6 LPC81x I O configuration IOCON Table 70 PIOO_10 register PIOO 10 address 0x4004 4020 bit description Bit Symbol Value Description Reset value 5 0 Reserved 0 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin 9 8 I2CMODE reads as 0 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 Reserved 1 Selects 12C mode 00 Select Standard mode I2CMODE 00 default or Standard I O functionality IZCMODE 01 if the pin function is GPIO FUNC 000 0 0 Standard mode Fast mode 12C 0 1 Standard I O functionality 0 2 Fast mode Plus 12C 0x3 Reserved 10 Reserved 12 11 5 MODE Digital filter sample mode 0 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than filter clock rejected 0 2 2 clock cycles Input pulses shorter than two filter clocks rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 15 13 CLK_DIV Select peripheral clock divider for input filter sampling clock 0 Value 0x7 i
321. erved Always write these bits as 0b110 Analog comparator power down Powered Powered down Reserved Reset value 0 0b1101 0b110 1 Device ID register This device ID register is a read only register and contains the part ID for each LPC81x part This register is also read by the ISP IAP commands see Table 250 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 48 of 370 NXP Semiconductors U M1 0601 4 7 Functional Chapter 4 LPC81x System configuration SYSCON Table 50 Device ID register DEVICE ID address 0x4004 83F8 bit description Bit Symbol Description Reset value 31 0 DEVICEID 0 0000 8100 LPC810M021FN8 part dependent 0x0000 8110 LPC811M001JDH16 0x0000 8120 LPC812M101JDH16 0x0000 8121 LPC812M101JD20 0x0000 8122 LPC812M101JDH20 0x0000 8122 LPC812M101JTB16 description 4 7 1 4 7 2 UM10601 Reset Reset has the following sources the RESET pin Watchdog Reset Power On Reset POR and Brown Out Detect BOD In addition there is an ARM software reset The RESET pin is a Schmitt trigger input pin Assertion of chip Reset by any source once the operating voltage attains a usable level starts the IRC causing reset to remain asserted until the external Reset is de asserted the oscillator is running and the flash controller has completed its initialization
322. es including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected UM10601 All information provided in this document is subject to legal disclaimers to result in personal injury death or severe property or environmental damage NXP Semiconductors and its suppliers accept no liability for inclusion and or use of NXP Semiconduc
323. es for clarification in Chapter 8 LPC800 Pin interrupts pattern match engine Updates for clarification in Section 9 4 switch matrix to pin functional diagram Updates for clarification in Chapter 5 LPC800 Reduced power modes and Power Management Unit PMU Section 3 3 2 Non Maskable Interrupt NMI and Section 3 3 3 Vector table offset added Bit fields corrected in Section 10 6 USART baudrate clock output removed from USART features 1 20121109 Preliminary LPC800 user manual Contact information For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 4 of 370 UM10601 Chapter 1 LPC81x Introductory information Rev 1 6 2 April 2014 User manual 1 1 Introduction 1 2 Features The LPC81x are an ARM Cortex M0 based low cost 32 bit MCU family operating at CPU frequencies of up to 30 MHz The LPC81x support up to 16 kB of flash memory and 4 kB of SRAM The peripheral complement of the LPC81x includes a CRC engine one I C bus interface up to three USARTS up to two SPI interfaces one multi rate timer self wake up timer and state configurable timer one comparator function configurable I O ports through a switch matrix an input pattern match engine and
324. es the level sensitivity depending on the pin interrupt mode configured in the ISEL register e f the pin interrupt mode is edge sensitive PMODE 0 the falling edge interrupt is enabled e If the pin interrupt mode is level sensitive PMODE 1 the active level of the level interrupt HIGH or LOW is configured Table 97 Pin interrupt active level or falling edge interrupt enable register IENF address 0xA000 4010 bit description Bit Symbol Description Reset Access value 7 0 ENAF Enables the falling edge or configures the active level interrupt 0 R W for each pin interrupt Bit n configures the pin interrupt selected in PINTSELn 0 Disable falling edge interrupt or set active interrupt level LOW 1 Enable falling edge interrupt enabled or set active interrupt level HIGH 31 8 Reserved 8 6 6 Pin interrupt active level or falling edge interrupt set register For each of the 8 pin interrupts selected in the PINTSELn registers see Section 4 6 27 one bit in the SIENF register sets the corresponding bit in the IENF register depending on the pin interrupt mode configured in the ISEL register e f the pin interrupt mode is edge sensitive PMODE 0 the falling edge interrupt is set e f the pin interrupt mode is level sensitive PMODE 1 the HIGH active interrupt is selected UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved U
325. escaler When enabled by a non zero PRE field in the Control register the prescaler acts as a clock divider for the counter like a fractional part of the counter value The prescaler is cleared whenever the counter is cleared or loaded for any of the following reasons Hardware reset e Software writing to the counter register e Software writing a 1 to the CLRCTR bit in the control register an event selected by a 1 in the counter limit register when BIDIR 0 When BIDIR is 0 a limit event caused by an I O signal can clear a non zero prescaler However a limit event caused by a Match only clears a non zero prescaler in one special case as described Section 10 7 8 A limit event when BIDIR is 1 does not clear the prescaler Rather it clears the DOWN bit in the Control register and decrements the counter on the same clock if the counter is enabled in that clock All information provided in this document is subject to legal disclaimers NXP B V 2014 AII rights reserved User manual Rev 1 6 2 April 2014 156 of 370 NXP Semiconductors U M1 0601 Chapter 10 LPC81x SCTimer PWM SCT 10 7 8 Match vs I O events Counter operation is complicated by the prescaler and by clock mode 01 in which the SCT clock is the bus clock However the prescaler and counter are enabled to count only when a selected edge is detected on a clock input The prescaler is enabled when the clock mode is not 01 or when the input edge sele
326. ess of direction masking or alternate functions except that pins configured as analog I O always read as Os Writing these registers loads the output bits of the pins written to regardless of the Mask register All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 92 of 370 NXP Semiconductors U M1 0601 7 6 6 7 6 7 7 6 8 UM10601 Chapter 7 LPC81x GPIO port Table 86 GPIO port 0 pin register PINO address 0xA000 2100 bit description Bit Symbol Description Reset Access value 17 0 PORTO Reads pin states or loads output bits bit O 0 bit1 ext R W PIOO 1 bit 17 PIOO 17 0 Read pin is low write clear output bit 1 Read pin is high write set output bit 31 18 Reserved 0 GPIO masked port pin registers These registers are similar to the PIN registers except that the value read is masked by ANDing with the inverted contents of the corresponding MASK register and writing to one of these registers only affects output register bits that are enabled by zeros in the corresponding MASK register Table 87 GPIO masked port 0 pin register MPINO address 0xA000 2180 bit description Bit Symbol Description Reset Access value 17 0 MPORTPO Masked port register bit 0 PIOO 0 bit 1 PIOO 1 bit ext R W 17 PIOO 17 0 Read pin is LOW and or the corresponding bit in
327. essor also wakes up on execution of an SEV instruction Reserved 0 5 4 Pin description In Deep power down only the WAKEUP pin PIOO 4 is functional The WAKEUP function can be disabled in the DPDCTRL register to lower the power consumption even more In this case enable the self wake up timer to provide an internal wake up signal See Section 5 6 3 Deep power down control register Remark When entering Deep power down mode an external pull up resistor is required on the WAKEUP pin to hold it HIGH In addition pull the RESET pin HIGH to prevent it from floating while in Deep power down mode UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 56 of 370 NXP Semiconductors U M1 0601 Chapter 5 LPC81x Reduced power modes and Power Management 5 5 General description UM10601 5 5 1 Power on the LPC81x is controlled by the PMU by the SYSCON block and the ARM Cortex M0 core The following reduced power modes are supported in order from highest to lowest power consumption 1 Sleep mode The sleep mode affects the ARM Cortex MO core only Peripherals and memories are active 2 Deep sleep and power down modes The Deep sleep and power down modes affect the core and the entire system with memories and peripherals Before entering deep sleep or power down you must switch the main clock to the
328. et to be disabled Incorrect feed sequence causes immediate watchdog event if enabled The watchdog reload value can optionally be protected such that it can only be changed after the warning interrupt time is reached Flag to indicate Watchdog reset The Watchdog clock WDCLK source is the WatchDog oscillator The Watchdog timer can be configured to run in Deep sleep or Power down mode Debug mode 12 3 Basic configuration The WWDT is configured through the following registers Power to the register interface WWDT PCLK clock In the SYSAHBCLKCTRL register set bit 17 in Table 30 Enable the WWDT clock source the watchdog oscillator in the PDRUNCFG register Table 49 This is the clock source for the timer base For waking up from a WWDT interrupt enable the watchdog interrupt for wake up in the STARTERP register Table 46 12 4 Pin description UM10601 The WWDT has no external pins All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 171 of 370 NXP Semiconductors U M1 0601 Chapter 12 LPC81x Windowed Watchdog Timer WWDT 12 5 General description The purpose of the Watchdog Timer is to reset or interrupt the microcontroller within a programmable time if it enters an erroneous state When enabled a watchdog reset is generated if the user program fails to feed reload the Watchd
329. etting and clearing each flag behaves in the same way as setting and clearing the INTFLAG bit in each of the STATUSn registers Table 154 Global interrupt flag register IRQ FLAG address 0x4000 40F8 bit description Bit Symbol Value Description Reset value 0 GFLAGO Monitors the interrupt flag of TIMERO 0 0 No pending interrupt Writing a zero is equivalent to no operation 1 Pending interrupt The interrupt is pending because TIMERO has reached the end of the time interval If the INTEN bit in the CONTROLO register is also set to 1 the interrupt for timer channel 0 and the global interrupt are raised Writing a 1 to this bit clears the interrupt request 1 GFLAG1 Monitors the interrupt flag of TIMER 0 0 No pending interrupt Writing a zero is equivalent to no operation 1 Pending interrupt The interrupt is pending because TIMER1 has reached the end of the time interval If the INTEN bit in the CONTROL 1 register is also set to 1 the interrupt for timer channel 1 and the global interrupt are raised Writing a 1 to this bit clears the interrupt request 2 GFLAG2 Monitors the interrupt flag of TIMER2 0 0 No pending interrupt Writing a zero is equivalent to no operation 1 Pending interrupt The interrupt is pending because TIMER2 has reached the end of the time interval If the INTEN bit in the CONTROL2 register is also set to 1 the interrupt for timer channel 2 and the global interrupt are raised Writing a 1 to this
330. evice the ability of the receiver to receive more data If connected to a pin and if enabled to do so the CTS input can allow an external device to throttle the USART transmitter Figure 31 shows an overview of RTS and CTS within the USART UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 204 of 370 NXP Semiconductors U M1 0601 Chapter 15 LPC81x USARTO 1 2 STAT CTS STAT DELTACTS change detect CFG CTSEN CFG LOOP Transmitter Receiver Fig 31 Hardware flow control using RTS and CTS 15 7 3 2 Software flow control Software flow control could include XON XOFF flow control or other mechanisms these are supported by the ability to check the current state of the CTS input and or have an interrupt when CTS changes state via the CTS and DELTACTS bits respectively in the STAT register and by the ability of software to gracefully turn off the transmitter via the TXDIS bit in the CTL register UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 205 of 370 16 1 How to read UM10601 Chapter 16 LPC81x I2C bus interface Rev 1 6 2 April 2014 User manual this chapter The I2C bus interface is available on all parts Read this chap
331. execute code and process data In this mode the device outperforms the default mode both in terms of providing higher CPU performance and lowering active current PWR LOW CURRENT is intended for those solutions that focus on lowering power consumption rather than CPU performance Param2 system clock The system clock is the clock rate at which the microcontroller core is running when set power is called This parameter is an integer between from 1 and 30 MHz inclusive 23 5 Functional description UM10601 23 5 1 23 5 1 1 Clock control See Section 23 5 1 1 to Section 23 5 1 6 for examples of the clock control API Invalid frequency device maximum clock rate exceeded command 0 12000 command 1 60000 command 2 CPU FREQ command 3 0 LPC PWRD API set pll command result The above code specifies a 12 MHz PLL input clock and a system clock of exactly 60 MHz The application was ready to infinitely wait for the PLL to lock But the expected system clock of 60 MHz exceeds the maximum of 30 MHz Therefore set pll returns PLL INVALID FREQ in result 0 and 12000 in result 1 without changing the PLL settings All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 303 of 370 NXP Semiconductors U M1 0601 UM10601 23 5 1 2 23 5 1 3 23 5 1 4 23 5 1 5 Chapter 23 LPC81x Power pr
332. following edge The SPI changes serial data on the first clock transition of 0 1 1 the transfer when the clock changes away from the rest low rising falling state Data is captured on the following edge 1 0 2 Same as mode 0 with SCK inverted high rising falling 1 1 3 Same as mode 1 with SCK inverted high falling rising 0 Data frame Fig 36 Basic SPI operating modes UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 247 of 370 NXP Semiconductors U M1 0601 Chapter 17 LPC81x SPIO 1 17 7 2 Frame delays Several delays can be specified for SPI frames These include Pre delay delay after SSEL is asserted before data clocking begins Post delay delay at the end of a data frame before SSEL is deasserted Frame delay delay between data frames when SSEL is not deasserted Transfer delay minimum duration of SSEL in the deasserted state between transfers 17 7 2 1 Pre delay and Post delay Pre delay and Post delay are illustrated by the examples in Figure 37 The Pre delay value controls the amount of time between SSEL being asserted and the beginning of the subsequent data frame The Post delay value controls the amount of time between the end of a data frame and the deassertion of SSEL Pre and post delay CPHA 0 Pre delay 2 Post delay 1 Modeo cpoL 0 sck s
333. for specific peripheral functions 0x104 Reserved 3 ICERO RW 0x180 Interrupt Clear Enable Register 0 This register allows disabling 0 Table 6 interrupts and reading back the interrupt enables for specific peripheral functions 0x184 Reserved 0 ISPRO RW 0x200 Interrupt Set Pending Register 0 This register allows changing the 0 Table 7 interrupt state to pending and reading back the interrupt pending state for specific peripheral functions 0x204 Reserved 0 ICPRO RW 0x280 Interrupt Clear Pending Register 0 This register allows changing the 0 Table 8 interrupt state to not pending and reading back the interrupt pending state for specific peripheral functions 0x284 Reserved 0 IABRO RO 0x300 Interrupt Active Bit Register O This register allows reading the 0 Table 9 current interrupt active state for specific peripheral functions 0x304 Reserved 0 IPRO RW 0x400 Interrupt Priority Registers 0 This register allows assigning a priority 0 Table 10 to each interrupt This register contains the 2 bit priority fields for interrupts 0 to 3 IPR1 RW 0x404 Interrupt Priority Registers 1 This register allows assigning a priority 0 Table 11 to each interrupt This register contains the 2 bit priority fields for interrupts 4 to 7 IPR2 RW 0x408 Interrupt Priority Registers 2 This register allows assigning a priority 0 Table 12 to each interrupt This register contains the 2 bit priority fields for interrupts 8 to
334. for the subsequent read with the correct partial I2C address For the Master function the I2C is simply instructed to perform the 2 byte addressing as a normal write operation followed either by more write data or by a Repeated Start with a repeat of the first part of the 10 bit slave address and then reading in the normal fashion For the Slave function the first part of the address is automatically matched in the same fashion as 7 bit addressing The Slave address qualifier feature see Section 16 6 14 can be used to intercept all potential 10 bit addresses first address byte values FO through F6 or just one In the case of Slave Receiver mode data is received in the normal fashion after software matches the first data byte to the remaining portion of the 10 bit address The Slave function should record the fact that it has been addressed in case there is a follow up read operation For Slave Transmitter mode the slave function responds to the initial address in the same fashion as for Slave Receiver mode and checks that it has previously been addressed with a full 10 bit address If the address matched is address 0 and address qualification is enabled software must check that the first part of the 10 bit address is a complete match to the previous address before acknowledging the address Clocking and power considerations The Master function of the I C always requires a peripheral clock to be running in order to operate The Slave
335. fter writing transmit data reading received data or any other housekeeping related to the next bus operation All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 223 of 370 NXP Semiconductors U M1 0601 Chapter 16 LPC81x I2C bus interface Table 194 Master Control register MSTCTL address 0x4005 0020 bit description Bit Symbol Value Description Reset value 1 MSTSTART Master Start control This bit is write only 0 0 No effect Start A Start will be generated on the 12C bus at the next allowed time 2 MSTSTOP Master Stop control This bit is write only 0 0 No effect 1 Stop A Stop will be generated on the I C bus at the next allowed time preceded by a NACK to the slave if the master is receiving data from the slave Master Receiver mode 31 Reserved Read value is undefined only zero should be 2 written 16 6 9 Master Time The MSTTIME register allows programming of certain times that may be controlled by the Master function These include the clock SCL high and low times repeated Start setup time and transmitted data setup time The 12 clock pre divider is described in Table 192 Table 195 Master Time register MSTTIME address 0x4005 0024 bit description Bit Symbol Value Description Reset value 2 0 MSTSCLLOW Master SCL Low time Specifies the minimum low time 0 that will
336. ftware should not write ones to reserved bits NA The value read from a reserved bit is not defined Flash signature stop address register Table 228 Flash Module Signature Stop register FMSSTOP 0x4004 0024 bit description Bit Symbol Value Description Reset value 16 0 Stop address for signature generation the word 0 specified by STOPA is included in the address range The address is in units of memory words not bytes 30 17 Reserved user software should not write ones to 0 reserved bits The value read from a reserved bit is not defined 31 STRTBIST When this bit is written to 1 signature generation starts 0 At the end of signature generation this bit is automatically cleared Flash signature generation result register The signature generation result register returns the flash signature produced by the embedded signature generator The generated flash signature can be used to verify the flash memory contents The generated signature can be compared with an expected signature and thus makes saves time and code space The method for generating the signature is described in Section 20 5 1 Table 229 FMSWO register bit description FMSWO address 0 4004 002C Bit Symbol Description Reset value 31 0 SIG 32 bit signature 20 5 Functional description UM10601 20 5 1 Flash signature generation The flash module contains a built in signature generator This generator can produce a
337. function Writing a 1 deselects the function and any movable 1 function can be assigned to this pin By default the fixed pin function is deselected and GPIO is assigned to this pin 0 Enable XTALIN This function is enabled on pin PIOO 8 Disable XTALIN GPIO function PIOO 8 default or any other movable function can be assigned to pin PIOO 8 5 XTALOUT EN Enables fixed pin function Writing a 1 deselects the function and any movable 1 function can be assigned to this pin By default the fixed pin function is deselected and GPIO is assigned to this pin 0 Enable XTALOUT This function is enabled on pin PIOO 9 1 Disable XTALOUT GPIO function PIOO 9 default or any other movable function can be assigned to pin PIOO 9 6 RESET EN Enables fixed pin function Writing a 1 deselects the function and any movable 0 function can be assigned to this pin This function is selected by default 0 Enable RESET This function is enabled on pin PIOO 5 Disable RESET GPIO function PIOO 5 is selected on this pin Any other movable function can be assigned to pin PIOO 5 7 CLKIN Enables fixed pin function Writing a 1 deselects the function and any movable 1 function can be assigned to this pin By default the fixed pin function is deselected and GPIO is assigned to this pin Functions CLKIN and ACMP 12 are connected to the same pin PIOO 1 To use CLKIN disable ACMP 12 in bit 1 of this register and enable CLKIN 0 Enable CLKIN This function is enable
338. generated when the System Tick counter counts down to 0 2 CLKSOURCE System Tick clock source selection When 1 the system clock 0 CPU clock is selected When 0 the system clock 2 is selected as the reference clock 15 39 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined 16 COUNTFLAG Returns 1 if the SysTick timer counted to 0 since the last read of 0 this register 31 17 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined System Timer Reload value register The SYST register is set to the value that will be loaded into the SysTick timer whenever it counts down to zero This register is loaded by software as part of timer initialization The SYST CALIB register may be read and used as the value for SYST RVR register if the CPU is running at the frequency intended for use with the SYST CALIB value Table 168 System Timer Reload value register SYST RVR 0xE000 E014 bit description Bit Symbol Description Reset value 23 0 RELOAD This is the value that is loaded into the System Tick counter when it 0 counts down to 0 31 24 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined System Timer Current value register The SYST register returns the current count from the System Tick counter when it is read
339. gister INTENCLR address 0x4005 000 bit description Bit Symbol Description Reset value 0 MSTPENDINGCLR Master Pending interrupt clear Writing 1 to this bit clears 0 the corresponding bit in the INTENSET register if implemented 3 1 Reserved Read value is undefined only zero should be NA written MSTARBLOSSCLR Master Arbitration Loss interrupt clear 0 5 Reserved Read value is undefined only zero should be NA written MSTSTSTPERRCLR Master Start Stop Error interrupt clear 0 Reserved Read value is undefined only zero shouldbe NA written 8 SLVPENDINGCLR Slave Pending interrupt clear 0 10 9 Reserved Read value is undefined only zero should be NA written 11 SLVNOTSTRCLR Slave Not Stretching interrupt clear 0 1442 Reserved Read value is undefined only zero should be All information provided in this document is subject to legal disclaimers written NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 220 of 370 NXP Semiconductors UM10601 UM10601 16 6 5 Chapter 16 LPC81x I2C bus interface Table 190 Interrupt Enable Clear register INTENCLR address 0x4005 000C bit description continued Bit Symbol 15 SLVDESELCLR 16 MONRDYCLR 17 MONOVCLR 18 19 MONIDLECLR 23 20 24 EVENTTIMEOUTCLR 25 SCLTIMEOUTCLR 31 26 Description Slave Deselect interrupt clear Monitor data Ready interrupt clear Monitor Overrun interrupt clear
340. gister When UNIFY 1 read or write the upper 16 bits of the 32 bit value to be loaded into the MATCHn register SCT capture control registers 0 to 4 REGMODEn bit 1 If UNIFY 1 in the CONFIG register only the _L bits are used If UNIFY 0 in the CONFIG register this register can be written to as two registers CAPCTRLn L and CAPCTRLn H Both the L and H registers can be read or written individually or in a single 32 bit read or write operation All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 150 of 370 NXP Semiconductors U M1 0601 Chapter 10 LPC81x SCTimer PWM SCT Each Capture Control register L H or unified 32 bit controls which events load the corresponding Capture register from the counter Table 141 SCT capture control registers 0 to 4 CAPCTRL 0 4 address 0x5000 4200 CAPCTRLO to 0x5000 4210 CAPCTRL4 bit description REGMODEn bit 1 Bit Symbol Description Reset value 5 0 CAPCONm L If bit mis one event m causes the CAPn L UNIFY 0 orthe 0 CAPn UNIFY 1 register to be loaded event 0 bit 0 event 1 bit 1 event 5 bit 5 15 6 Reserved 21 16 If bit mis one event m causes the CAPn_H UNIFY 0 0 register to be loaded event 0 bit 16 event 1 bit 17 event 5 bit 21 31 222 Reserved 10 6 22 SCT event state mask re
341. gisters 0 5 Each event has one associated SCT event state mask register that allow this event to happen in one or more states of the counter selected by the HEVENT bit in the corresponding EVn_CTRL register An event n is disabled when its EVn_STATE register contains all zeros since it is masked regardless of the current state In simple applications that do not use states write 0x01 to this register to enable an event Since the state always remains at its reset value of 0 writing 0x01 permanently enables this event for the default state 0 Table 142 SCT event state mask registers 0 to 5 EV 0 5 STATE addresses 0x5000 4300 EVO STATE to 0x5000 4328 EV5 STATE bit description Bit Symbol Description Reset value 0 0 STATEMASKO _ If this bit is set to one event n configured in the EVn_CTRL 0 register n 0 to 5 is enabled in state 0 If this bit is 0 the event is disabled masked in state 0 1 1 If this bit is set to one event n configured in the EVn_CTRL 0 register n 0 to 5 is enabled in state 1 If this bit is 0 the event is disabled masked in state 1 31 2 Reserved 10 6 23 SCT event control registers 0 to 5 This register defines the conditions for event n to occur other than the state variable which is defined by the state mask register Most events are associated with a particular counter high low or unified in which case the event can depend on a match to that register The other possible ingre
342. grammed to also generate an RXEV notification to the ARM CPU The RXEV signal can be connected to a pin Pattern match can be used in conjunction with software to create complex state machines based on pin inputs 8 3 Basic configuration Pin interrupts Select up to eight external interrupt pins from all GPIO port pins in the SYSCON block Table 44 The pin selection process is the same for pin interrupts and the pattern match engine The two features are mutually exclusive Enable the clock to the pin interrupt register block in the SYSAHBCLKCTRL register Table 30 bit 6 f you want to use the pin interrupts to wake up the part from deep sleep mode or power down mode enable the pin interrupt wake up feature in the STARTERPO register Table 45 Each selected pin interrupt is assigned to one interrupt in the NVIC interrupts 24 to 31 for pin interrupts 0 to 7 Pattern match engine Select up to eight external pins from all GPIO port pins in the SYSCON block Table 44 The pin selection process is the same for pin interrupts and the pattern match engine The two features are mutually exclusive UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 96 of 370 NXP Semiconductors U M1 0601 Chapter 8 LPC81x Pin interrupts pattern match engine Enable the clock to the pin interru
343. handle UART_CONFIG set UART init Table 296 uint8 t uart get char UART HANDLE T handle UART get character Table 297 void uart put char UART HANDLE handle uint8 t data UART put character Table 298 uint32 t uart get line UART HANDLE T handle UART PARAM T UART get line Table 299 param uint32 t uart put line UART HANDLE T handle UART PARAM T UART put line Table 300 param void uart is UART HANDLE T handle UART interrupt service routine Table 301 The following structure has to be defined to use the UART API typedef struct UARTD_API index of all the uart driver functions nt32_t uart_get_mem_size void UART HANDLE T uart_setup uint32_t base addr uint8 t ram nt32 t uart init UART HANDLE T handle UART_CONFIG_T set I polling functions nt8 t uart get char UART HANDLE T handle void uart put HANDLE T handle uint8_t data nt32 t uart get lineUART HANDLE T handle PARAM param uint32 t uart put HANDLE T handle T param interrupt functions void uart isr UART HANDLE T handle UARTD API II end of structure Eme Cm te define ROM DRIVER BASE 0x FFFIFF8UL define LPC_UART_API UARTD T ROM T ROM DRIVER BASE pUARTD See Section 21 5 2 for how to include the ROM driver structure 25 4 1 UART get memory size Table 294 uart get mem size
344. hange state values Chapter 10 LPC81x SCTimer PWM SCT matches select L matches MATCHSELi inputs ect gt event i outputs IOSELI OUTSELI IOCONDi COMBMODEi STATEMASKi select STATE L STATE HEVENTi Fig 19 Event selection 10 7 4 Output generation Figure 20 shows one output slice of the SCT Events gt Set NoChangeConflict i register i SETCLRi OUT e Select m gt Output i OiRES reg Clear register i SCT clock Fig 20 Output slice i 10 7 5 State logic The SCT can be configured as a timer counter with multiple programmable states The states are user defined through the events that can be captured in each particular state In a multi state SCT the SCT can change from one state to another state when a user defined event triggers a state change The state change is triggered through each event s EV CTRL register in one of the following ways The event can increment the current state number by a new value The event can write a new state value UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 155 of 370 NXP Semicond
345. hapter 24 LPC81x I2C bus ROM API to comply with LPCOpen code Remark about 5 V tolerance added for digital pins with configurable open drain mode See Section 6 4 4 Description of the EVn STATE register clarified See Table 142 SCT event state mask registers 0 to 5 EV 0 5 STATE addresses 0 5000 4300 EVO STATE to 0x5000 4328 EV5_STATE bit description Description of SLEEPFLAG bit corrected in the PCON register Reading a 1 indicates that the part was in sleep deep sleep or power down mode before wake up See Table 55 Register overview PMU base address 0x4002 0000 Added recommendation to use a software delay after power up of the system oscillator See Section 4 6 32 Power configuration register Section 4 7 1 Reset Section 4 7 2 Start up behavior Section 4 7 3 Brown out detection added for clarity Description of Go command clarified See Section 22 5 1 8 Go address lt mode gt Description of the ARM STIR register removed This register is not implemented in the ARMv6 M architecture Name SCT changed to SCTimer PWM for clarity where appropriate throughout the document Behavior of data stalls for different settings of the SPI TXDATCTL register bit EOT clarified Section 17 6 7 SPI Transmitter Data and Control register Add clock frequency parameter to IAP commands Copy RAM to flash Erase page and Erase sector Table 258 Table 259 Table 266 This parameter has been removed
346. has been matched by hardware Slave receive Received data is available Slave Receiver mode Slave transmit Data can be transmitted Slave Transmitter mode Reserved Slave Not Stretching Indicates when the slave function is stretching 1 RO the 12C clock This is needed in order to gracefully invoke Deep Sleep or Power down modes during slave operation This read only flag reflects the slave function status in real time Stretching The slave function is currently stretching the 12C bus clock Deep Sleep or Power down mode cannot be entered at this time Not stretching The slave function is not currently stretching the 12C bus clock Deep sleep or Power down mode could be entered at this time Slave address match Index This field is valid when the I C slave 0 RO function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers and provides an identification of the address that was matched It is possible that more than one address could be matched but only one match can be reported here Slave address 0 was matched Slave address 1 was matched Slave address 2 was matched Slave address 3 was matched All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 216 of 370 NXP Semiconductors U M1 0601 Chapter 16 LPC81x I2C bus interface Table
347. he part goes through the entire reset process 1 On the WAKEUP pin transition from HIGH to LOW The PMU will turn on the on chip voltage regulator When the core voltage reaches the power on reset POR trip point a system reset will be triggered and the chip re boots All registers except the DPDCTRL and GPREGO to GPREGSregisters will be in their reset state 2 Once the chip has booted read the deep power down flag in the PCON register Table 56 to verify that the reset was caused by a wake up event from Deep power down and was not a cold reset 3 Clear the deep power down flag in the PCON register Table 56 4 Optional Read the stored data in the general purpose registers Section 5 6 2 5 Set up the PMU for the next Deep power down cycle Remark The RESET pin has no functionality in Deep power down mode All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 66 of 370 NXP Semiconductors U M1 0601 Chapter 5 LPC81x Reduced power modes and Power Management 5 7 7 4 Programming Deep power down mode using the self wake up timer The following steps must be performed to enter Deep power down mode when using the self wake up timer for waking up 1 o fF W Iv T Enable the low power oscillator to run in Deep power down mode by setting bits 2 and 3 in the DPDCTRL register to 1 see Table 58
348. he Deep sleep mode All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 64 of 370 NXP Semiconductors U M1 0601 UM10601 Chapter 5 LPC81x Reduced power modes and Power Management 5 7 6 1 Power configuration in Power down mode Power consumption in Power down mode can be configured by the power configuration setting in the PDSLEEPCFG Table 47 register in the same way as for Deep sleep mode see Section 5 7 5 1 The watchdog oscillator can be left running in Power down mode if required for the WWDT The BOD circuit can be left running in Power down mode if required by the application 5 7 6 2 Programming Power down mode The following steps must be performed to enter Power down mode 1 2 The PM bits in the PCON register must be set to Ox2 Table 56 Select the power configuration in Power down mode in the PDSLEEPCFG Table 47 register Select the power configuration after wake up in the PDAWAKECFG Table 48 register If any of the available wake up interrupts are used for wake up enable the interrupts in the interrupt wake up registers Table 45 Table 46 and in the NVIC 5 Select the IRC as the main clock See Table 27 6 Write one to the SLEEPDEEP bit in the ARM Cortex M0 SCR register Table 53 7 Use the ARM WFI instruction 5 7 6 3 Wake up from Power down mode The microcont
349. he I C function is selected all three 12C modes Standard mode Fast mode and Fast mode plus are supported A digital glitch filter can be configured for all functions Pins PIOO 10 and PIOO 11 operate as high current sink drivers 20 mA independently of the programmed function Remark Pins PIOO 10 and PIOO 11 are 5 V tolerant when Vpp 0 and when Vpp is at operating voltage level Programmable glitch filter All GPIO pins are equipped with a programmable digital glitch filter The filter rejects input pulses with a selectable duration of shorter than one two or three cycles of a filter clock S MODE 1 2 or 3 For each individual pin the filter clock can be selected from one of seven peripheral clocks PCLKO to 6 which are derived from the main clock using the IOCONCLKDIVO to 6 registers The filter can also be bypassed entirely Any input pulses of duration Tpulse of either polarity will be rejected if Tpulse lt S MODE Input pulses of one filter clock cycle longer may also be rejected Tpuse S MODE 1 Remark The filtering effect is accomplished by requiring that the input signal be stable for S_MODE 1 successive edges of the filter clock before being passed on to the chip Enabling the filter results in delaying the signal to the internal logic and should be done only if specifically required by an application For high speed or time critical functions ensure that the filter is bypassed
350. he analog comparator output to any pin on the package that is not a supply or ground pin The comparator inputs and the reference voltage are fixed pin functions that must be enabled through the switch matrix and can only be assigned to special pins on the package See Section 9 3 1 Connect an internal signal to a package pin to assign the analog comparator output to any pin on the LPC81x package See Section 9 3 2 to enable the analog comparator inputs and the reference voltage input Table 216 Analog comparator pin description Function ACMP 11 12 O VDDCMP Type Pin Description SWM register Reference PIOO 0 ACMP 11 Comparator input 1 PINENABLEO Section 9 5 10 PIOO 1 ACMP I2 CLKIN Comparator input 2 Disable the CLKIN Section 9 5 10 function in the PINENABLEO register Comparator output PINASSIGN8 Section 9 5 9 PIOO_6 VDDCMP External reference voltage source for PINENABLEO Section 9 5 10 32 stage Voltage Ladder 18 5 General description UM10601 The analog comparator can compare voltage levels on external pins and internal voltages The comparator has 4 inputs multiplexed separately to its positive and negative inputs The multiplexers are controlled by the comparator register CTL see Figure 41 and Table 218 Input 0 of the multiplexer is the programmable voltage ladder output Bits 2 1 control the external inputs ACMP_1 2 1 Bits 6 of the multiplexe
351. he baud rate the following sequence should be used 1 Make sure the USART is not currently sending or receiving data 2 Disable the USART by writing a 0 to the Enable bit 0 may be written to the entire registers 3 Write the new BRGVAL 4 Write to the CFG register to set the Enable bit to 1 Table 181 USART Baud Rate Generator register BRG address 0x4006 4020 USARTO 0x4006 8020 USART1 0x4006 C020 USART2 bit description Bit Symbol Description Reset Value 15 0 BRGVAL This value is used to divide the USART input clock to determine the 0 baud rate based on the input clock from the FRG 0 The FRG clock is used directly by the USART function 1 The FRG clock is divided by 2 before use by the USART function 2 The FRG clock is divided by 3 before use by the USART function OxFFFF The FRG clock is divided by 65 536 before use by the USART function 31 16 Reserved Read value is undefined only zero should be written NA 15 6 10 USART Interrupt Status register The read only INTSTAT register provides a view of those interrupt flags that are currently enabled This can simplify software handling of interrupts See Table 175 for detailed descriptions of the interrupt flags Table 182 USART Interrupt Status register INTSTAT address 0x4006 4024 USARTO 0x4006 8024 USART1 0x4006 C024 USART2 bit description Bit Symbol Description Reset Value 0 RXRDY Receiver Ready flag 0 1 Reserved Read v
352. he next timer cycle by writing a new value gt 0 to the INTVALn register and setting the LOAD bit to 0 An interrupt is generated when the timer reaches zero On the next cycle the timer counts down from the new value Change the interval value on the fly immediately by writing a new value gt 0 to the INTVALn register and setting the LOAD bit to 1 The timer immediately starts to count down from the new timer interval value An interrupt is generated when the timer reaches 0 Stop the timer at the end of time interval by writing a O to the INTVALn register and setting the LOAD bit to 0 An interrupt is generated when the timer reaches zero Stop the timer immediately by writing a 0 to the INTVALn register and setting the LOAD bit to 1 No interrupt is generated when the INTVALn register is written UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 165 of 370 NXP Semiconductors U M1 0601 11 5 2 11 5 3 Chapter 11 LPC81x Multi Rate Timer MRT One shot interrupt mode The one shot interrupt generates one interrupt after a one time count With this mode you can generate a single interrupt at any point This mode can be used to introduce a specific delay in a software task When the timer is in the idle state writing a non zero value IVALUE to the INTVALn register immediately loads the time interval value IV
353. hen the RESET pin is LOW JTAG Test Reset The TRST pin be used to reset the test logic within the scan when the RESET pin is LOW 26 5 Functional description UM10601 26 5 1 26 5 2 Debug limitations It is recommended not to use the debug mode during Deep sleep or Power down mode mode During a debugging session the System Tick Timer is automatically stopped whenever the CPU is stopped Other peripherals are not affected Debug connections for SWD For debugging purposes it is useful to provide access to the ISP entry pin PIOO 1 This pin can be used to recover the part from configurations which would disable the SWD port such as improper PLL configuration reconfiguration of SWD pins entry into Deep power down mode out of reset etc This pin can be used for other functions such as GPIO but it should not be held LOW on power up or reset All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 329 of 370 NXP Semiconductors U M1 0601 UM10601 Chapter 26 LPC81x Debugging VDD VTREF LPC800 Signals from SWD connector 12 or PIOO 1 ISP entry The VTREF pin on the SWD connector enables the debug connector to match the target voltage Fig 52 Connecting the SWD pins to a standard SWD connector 26 5 3 Boundary scan The RESET pin selects between the JTAG bound
354. here 0 is the highest priority Table 12 Interrupt Priority Register 2 IPR2 address 0xE000 E408 bit description Bit Symbol Description 5 0 These bits ignore writes and read as 0 7 6 IP_l2C Interrupt Priority 0 highest priority 3 lowest priority 13 8 These bits ignore writes and read as 0 15 14 IP SCT Interrupt Priority 0 highest priority 3 lowest priority 21 16 These bits ignore writes and read as 0 23 22 IP Interrupt Priority 0 highest priority 3 lowest priority 29 24 These bits ignore writes and read as O 31 30 IP CMP Interrupt Priority 0 highest priority 3 lowest priority Interrupt Priority Register 3 The IPRG register controls the priority of four peripheral interrupts Each interrupt can have one of 4 priorities where 0 is the highest priority Table 13 Interrupt Priority Register 3 IPR3 address 0xE000 E40C bit description Bit Symbol Description 5 0 These bits ignore writes and read as O 7 6 IP WDT Interrupt Priority 0 highest priority 3 lowest priority 13 8 These bits ignore writes and read as 0 15 14 IP BOD Interrupt Priority 0 highest priority 3 lowest priority 21 16 These bits ignore writes and read as O 23 22 IP FLASH Interrupt Priority 0 highest priority 3 lowest priority 29 24 These bits ignore writes and read as O 31 30 IP WKT Interrupt Priority 0 highest priority 3 lowest priority All information provide
355. his limitation follows from the application of ECC to the flash write operation see Section 22 4 2 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 282 of 370 NXP Semiconductors UM10601 UM10601 Chapter 22 LPC81x Flash ISP and IAP programming 3 To avoid write disturbance a mechanism intrinsic to flash memories an erase should be performed after following 16 consecutive writes inside the same page Note that the erase operation then erases the entire sector Remark Once a page has been written to 16 times it is still possible to write to other pages within the same sector without performing a sector erase assuming that those pages have been erased previously Table 245 UART ISP Copy RAM to flash command Command Input Return Code Description Example Flash Address DST Destination flash address where data bytes are to be written The destination address should be a 64 byte boundary RAM Address SRC Source RAM address from where data bytes are to be read Number of Bytes Number of bytes to be written Should be 64 128 256 512 1024 CMD_SUCCESS SRC_ADDR_ERROR Address not on word boundary DST_ADDR_ERROR Address not on correct boundary SRC_ADDR_NOT_MAPPED DST_ADDR_NOT_MAPPED COUNT_ERROR Byte count is not 64 128 256 512 1024 SECTOR_NOT_PREPARED_FOR
356. i 22s se ios be ee Rer 169 Table 152 Status register STAT 0 3 address 0x4000 400C STATO to 0x4000 403C STAT3 bit description 169 Table 153 Idle channel register IDLE CH address 0x4000 40F4 bit description 170 Table 154 Global interrupt flag register IRQ FLAG address 0x4000 40F8 bit description 170 NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 357 of 370 NXP Semiconductors UM10601 Table 155 Register overview Watchdog timer base address 0 4000 4000 175 Table 156 Watchdog mode register MOD 0x4000 4000 bit description 175 Table 157 Watchdog operating modes selection 177 Table 158 Watchdog Timer Constant register TC 0x4000 4004 bit 177 Table 159 Watchdog Feed register FEED 0x4000 4008 bit description 178 Table 160 Watchdog Timer Value register TV 0x4000 400C bit description 178 Table 161 Watchdog Timer Warning Interrupt register WARNINT 0x4000 4014 bit description 178 Table 162 Watchdog Timer Window register WINDOW 0x4000 4018 bit description 179 Table 163 Register overview WKT base address 0x4000 8000 RR ERR bue e E 181 Table 164 Control register CTRL address 0x4000 8000 bit description 181 Tabl
357. iables needed by the I2C ROM Driver to operate correctly The structure contains the following Number of bytes to be transmitted Number of bytes to be received Pointer to the transmit buffer Pointer to the receive buffer Pointer to callback function Stop flag The RESULT structure contains the results after the function executes The structure contains the following Number of bytes transmitted Number of bytes received Remark The number of bytes transmitted is updated only fori2c slave send poll and i2c slave send intr The number of bytes received is updated only for i2c slave receive poll and 2 slave receive intr To initiate a slave mode communication the receive function is called This can be either the polling or interrupt driven function i2c slave receive poll or i2c slave receive intr respectively The receive buffer should be as large or larger than any data or command that will be received If the amount of data exceed the receive buffer size an error code will be returned All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 320 of 370 NXP Semiconductors UM1 0601 Chapter 24 LPC81x I2C bus ROM API In slave receive mode the driver receives data until one of the following are true Address matching set in the set slave addr function with the R W bi
358. ices concerning this document and the product s described herein have been included in section Legal information B V 2014 All rights reserved For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 2 April 2014 Document identifier UM10601 Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery amp Lifecycle Information NXP OM13069 598 OM13053
359. idirectional mode or changes the direction of count in bidirectional mode When the counter reaches all ones this state is always treated as a limit event and the counter is cleared in unidirectional mode or in bidirectional mode begins counting down on the next clock edge even if no limit event as defined by the SCT limit register has occurred Note that in addition to using this register to specify events that serve as limits it is also possible to automatically cause a limit condition whenever a match register 0 match occurs This eliminates the need to define an event for the sole purpose of creating a limit The AUTOLIMITL and AUTOLIMITH bits in the configuration register enable disable this feature see Table 121 Table 123 SCT limit register LIMIT address 0x5000 4008 bit description Bit Symbol Description Reset value 5 0 LIMMSK_L If bit n is one event is used as a counter limit forthe Lor 0 unified counter event 0 bit 0 event 1 bit 1 event 5 bit 5 156 Reserved 21 16 LIMMSK_H If bit is one event is used as a counter limit for the 0 counter event 0 bit 16 event 1 bit 17 event 5 bit 21 3122 Reserved SCT halt condition register If UNIFY 1 in the CONFIG register only the _L bits are used If UNIFY 0 in the CONFIG register this register can be written to as two registers HALT_L and HALT_H Both the L and H registers can be read or written individually or in a single 32 bi
360. illator can be calculated as wdt osc Fclkana 2 x 1 DIVSEL 9 3 kHz to 2 3 MHz nominal values Remark Any setting of the FREQSEL bits will yield a Fclkana value within 40 of the listed frequency value The watchdog oscillator is the clock source with the lowest power consumption If accurate timing is required use the IRC or system oscillator Remark The frequency of the watchdog oscillator is undefined after reset The watchdog oscillator frequency must be programmed by writing to the WDTOSCCTRL register before using the watchdog oscillator Table 23 Watchdog oscillator control register WDTOSCCTRL address 0x4004 8024 bit description Bit Symbol Value Description Reset value 4 0 DIVSEL Select divider for Fclkana 0 wdt_osc_clk Fclkana 2 x 1 DIVSEL 00000 2 x 1 DIVSEL 2 00001 2 x 1 DIVSEL 4 to 11111 2 x 1 DIVSEL 64 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 32 of 370 NXP Semiconductors U M1 0601 Chapter 4 LPC81x System configuration SYSCON Table 23 Watchdog oscillator control register WDTOSCCTRL address 0x4004 8024 bit description Bit Symbol Value Description Reset value 8 5 FREQSEL Select watchdog oscillator analog output frequency 0x00 0 1 0 6 MHz 0 2 1 05 MHz 0x3 1 4 MHz 0 4 1 75 MHz 0 5 2 1 MHz 0 6
361. imers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 362 of 370 NXP Semiconductors UM10601 4 7 4 3 2 Feedback 52 4 7 4 3 3 Changing the divider values 52 4 7 4 4 Frequency selection 52 Chapter 30 Supplementary information 4 7 4 4 4 Normal 52 4 7 4 4 2 PLL Power down mode 54 Chapter 5 LPC81x Reduced power modes and Power Management Unit PMU 5 1 How to read this 55 5 7 4 8 Programming Sleep mode 63 5 2 55 5 743 Wake up from Sleep mode 63 5 7 5 Deep sleep mode 63 5 3 Basic configuration 55 gurat 5 7 5 1 Power configuration in Deep sleep mode 63 5 8 1 Low power modes in the ARM Cortex MO 5752 Programming Deep sleep mode 63 55 7 5 2 Programming Deep sleep mode 5 3 1 1 System control register 55 B Hina B 5 4 n description a RM ac ES 56 5 7 6 1 Power configuration in Power down mode 65 5 5 General description Joa RRENA RR 57 5 7 6 2 Programming Power down mode 65 5 5 1 Wake up 57 5 7 6 3 Wake up from Power down mode 65 5 6 Register description 58
362. in Sleep mode Power consumption in Sleep mode is configured by the same settings as in Active mode All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 62 of 370 NXP Semiconductors U M1 0601 Chapter 5 LPC81x Reduced power modes and Power Management The clock remains running The system clock frequency remains the same as in Active mode but the processor is not clocked Analog and digital peripherals are selected as in Active mode 5 7 4 2 Programming Sleep mode The following steps must be performed to enter Sleep mode 1 The PM bits in the PCON register must be set to the default value 0 0 2 The SLEEPDEEP bit in the ARM Cortex M0 SCR register must be set to zero Table 53 3 Use the ARM Cortex M0 Wait For Interrupt WFI instruction 5 7 4 3 Wake up from Sleep mode Sleep mode is exited automatically when an interrupt enabled by the NVIC arrives at the processor or a reset occurs After wake up due to an interrupt the microcontroller returns to its original power configuration defined by the contents of the PDRUNCFG and the SYSAHBCLKDIV registers If a reset occurs the microcontroller enters the default configuration in Active mode 5 7 5 Deep sleep mode In Deep sleep mode the system clock to the processor is disabled as in Sleep mode All analog blocks are powered down except for the BOD c
363. in clock source update enable register address 0x4004 8234 bit description 47 MAINCLKUEN address 0x4004 8074 bit Table 49 Power configuration register PDRUNCFG UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 355 of 370 NXP Semiconductors UM10601 Chapter 30 Supplementary information address 0x4004 8238 bit description 48 Table 80 GPIO pins available 90 Table 50 Device ID register DEVICE ID address 0x4004 Table 81 Register overview GPIO port base address 83F8 bit 49 0xA000 0000 91 Table 51 PLL frequency parameters 52 Table 82 GPIO port 0 byte pin registers B 0 17 addresses Table 52 PLL configuration examples 53 0xA000 0000 BO to OxA000 0012 B17 bit Table 53 System control register SCR address 0xE000 description eiser eed dase et 91 ED10 bit description 56 Table 83 GPIO port 0 word pin registers W 0 17 Table 54 Wake up sources for reduced power modes 58 addresses 0xA000 1000 WO to 0x5000 1048 Table 55 Register overview PMU base address 0x4002 W17 bit 92 0000 rm 58 Table 84 GPIO direction port 0 register DIRO address Table 56 Power control register PCON address 0x4002 0xAO00
364. in error in v 1 3 Description of MRT one shot bus stall mode added See Section 11 5 3 One shot bus stall mode and Table 151 Control register CTRL 0 3 address 0x4000 4008 CTRLO to 0x4000 4038 CTRL3 bit description All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 2 of 370 NXP Semiconductors U M1 0601 LPC81x User manual Revision history continued Rev Date Description 1 3 20130722 LPC800 user manual Modifications explanation added to the SPI Transmitter data and control register See Table 211 Changed the ISP entry pin from PIOO_1 to PIOO_12 for TSSOP and SOP packages See Table 234 LPC800 flash and ISP configurations and Table 232 Pin location in ISP mode Requirement added for entering low power modes switch the main clock source to IRC before entering Deep sleep and Power down modes See Section 5 5 Section 5 7 5 2 and Section 5 7 6 2 Section 3 4 added Type numbers updated throughout the document to reflect new operating temperature range See Table 1 Ordering information and Table 2 Ordering options Boot Rom revision updated See Table 231 Boot loader versions Description of boot loader updated See Section 21 5 1 ADDRDET bit description corrected in Table 175 USART Control register CTL address 0x4006 4004 USARTO 0x4006 8004 USART 1 0x40
365. int32 t intstat LPC_SPI gt INTSTAT if intstat amp SPI STAT TXRDY if tx state 0 LPC_SPI gt TXDATCTL SPI_TXDATCTL_FLEN 15 SPI TXDATCTL SSEL N 0xe Oxdddd tx statet if tx state 1 LPC_SPI gt TXDATCTL SPI TXDATCTL FLEN 7 SPI_TXDATCTL_SSEL_N 0xe Oxdd LPC_SPI gt INTENCLR SPI_STAT_TXRDY if intstat amp SPI_STAT_RXRDY if rx_state 0 data LPC_SPI gt RXDAT if data 0Oxdddd abort rx_statett if rx state 1 data LPC_SPI gt RXDAT if data 0 abort LPC_SPI gt INTENCLR SPI_STAT_RXRDY UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 348 of 370 NXP Semiconductors UM1 0601 UM10601 Chapter 29 LPC81x Code examples 29 3 3 Transmit one byte to slave 0 29 3 4 29 3 5 Table 326 SPI Code example Transmit one byte to slave 0 LPC_SPI gt CFG SPI_CFG_MASTER SPI_CFG_ENABLE while LPC_SPI gt STAT amp SPI STAT TXRDY LPC_SPI gt TXDATCTL SPI TXDATCTL FLEN 7 SPI TXDATCTL RXIGNORE SPI TXDATCTL EOT SPI TXDATCTL SSEL 0 0 while LPC_SPI gt STAT amp SPI STAT MSTIDLE Receive one byte from slave 0 Table 327 SPI Code example Receive one byte from slave 0 LPC_SPI gt CFG SPI CFG MASTER SPI CFG ENABLE while LPC_SPI gt STAT amp SPI STAT TXRDY LPC_SPI gt TXDATCTL
366. interrupt enable bit for each potential USART interrupt A complete value may be read from this register Writing a 1 to any implemented bit position causes that bit to be set INTENCLR W 0x010 Interrupt Enable Clear register Allows clearing any combination Table 177 of bits in the INTENSET register Writing a 1 to any implemented bit position causes the corresponding bit to be cleared RXDAT R 0x014 Receiver Data register Contains the last character received Table 178 RXDATSTAT R 0x018 Receiver Data with Status register Combines the last character Table 179 received with the current USART receive status Allows software to recover incoming data and status together TXDAT R W Ox01C Transmit Data register Data to be transmitted is written here 0 Table 180 BRG R W 0x020 Baud Rate Generator register 16 bit integer baud rate divisor 0 Table 181 value INTSTAT R 0x024 Interrupt status register Reflects interrupts that are currently 0x0005 Table 182 enabled ES UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 193 of 370 NXP Semiconductors UM10601 Chapter 15 LPC81x USARTO 1 2 15 6 1 USART Configuration register The CFG register contains communication and mode settings for aspects of the USART that would normally be configured once in an application Remark If software needs to change configuration values the fo
367. ion is detected the interrupt associated with bit slice 7 PININT7 IRQ will be asserted All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 101 of 370 NXP Semiconductors UM10601 Chapter 8 LPC81x Pin interrupts pattern match engine The ORed result of all three minterms asserts the RXEV request to the CPU and the GPIO INT BMAT output That is if any of the three minterms are true the output is asserted Related links Section 8 7 2 8 6 Register description UM10601 8 6 1 Table 92 Register overview Pin interrupts and pattern match engine base address 0xA000 4000 Name Access Address Description Reset Reference offset value ISEL R W 0x000 Pin Interrupt Mode register 0 Table 93 IENR R W 0x004 Pin interrupt level or rising edge interrupt 0 Table 94 enable register SIENR WO 0x008 Pin interrupt level or rising edge interrupt Table 95 set register CIENR WO 0x00C Pin interrupt level rising edge interrupt NA Table 96 clear register IENF R W 0x010 Pin interrupt active level or falling edge 0 Table 97 interrupt enable register SIENF WO 0x014 Pin interrupt active level or falling edge NA Table 98 interrupt set register CIENF WO 0x018 Pin interrupt active level or falling edge NA Table 99 interrupt clear register RISE R W 0x01C Pin interrupt rising edge register 0 Table 100 FALL R W 0x020 Pin in
368. ion provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 183 of 370 NXP Semiconductors U M1 0601 Chapter 14 LPC81x ARM Cortex SysTick Timer SysTick The SysTick timer is an integral part of the Cortex M0 The SysTick timer is intended to generate a fixed 10 millisecond interrupt for use by an operating system or other system management software Since the SysTick timer is a part of the Cortex MO it facilitates porting of software by providing a standard timer that is available on Cortex MO based devices The SysTick timer can be used for An RTOS tick timer which fires at a programmable rate for example 100 Hz and invokes a SysTick routine A high speed alarm timer using the core clock Asimple counter Software can use this to measure time to completion and time used Aninternal clock source control based on missing meeting durations The COUNTFLAG bit field in the control and status register can be used to determine if an action completed within a set duration as part of a dynamic clock management control loop Refer to Ref 5 for details 14 6 Register description The SysTick timer registers are located on the ARM Cortex MO private peripheral bus see Figure 2 and are part of the ARM Cortex MO core peripherals For details see Ref 5 Table 166 Register overview SysTick timer base address 0xE000 E000 Na
369. iption The power consumption in Active and Sleep modes can be optimized for the application through simple calls to the power profile The power configuration routine configures the LPC81x for one of the following power modes Default mode corresponding to power configuration after reset CPU performance mode corresponding to optimized processing capability Efficiency mode corresponding to optimized balance of current consumption and CPU performance Low current mode corresponding to lowest power consumption In addition the power profile includes routines to select the optimal PLL settings for a given system clock and PLL input clock Remark Disable all interrupts before making calls to the power profile API You can re enable the interrupts after the power profile API calls have completed The API calls to the ROM are performed by executing functions which are pointed by a pointer within the ROM Driver Table Figure 46 shows the pointer structure used to call the Power Profiles API UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 297 of 370 NXP Semiconductors U M1 0601 Chapter 23 LPC81x Power profile ROM driver Power API function table set pll Ox1FFF 1FF8 ROM Driver Table 0x00 0x04 0x08 0x0C Ptr to PowerAPI Table Ptr to Device Table n
370. iption Bit Symbol Description Reset value 0 ISE SPIO Interrupt enable 0 1 ISE SPI Interrupt enable 0 2 Reserved 5 3 ISE_UARTO Interrupt enable 0 4 ISE_UART1 Interrupt enable 0 5 ISE_UART2 Interrupt enable 0 6 Reserved 7 Reserved 8 ISE_I2C Interrupt enable 0 9 ISE_SCT Interrupt enable 0 10 ISE_MRT Interrupt enable 0 11 ISE_CMP Interrupt enable 0 12 ISE_WDT Interrupt enable 0 13 ISE_BOD Interrupt enable 0 14 ISE_FLASH Interrupt enable 0 15 ISE_WKT Interrupt enable 0 23 16 Reserved 24 ISE PININTO Interrupt enable 0 25 ISE PININT1 Interrupt enable 0 26 ISE PININT2 Interrupt enable 0 27 ISE PININT3 Interrupt enable 0 28 ISE PININT4 Interrupt enable 0 29 ISE PININT5 Interrupt enable 0 30 ISE_PININT6 Interrupt enable 0 31 ISE_PININT7 Interrupt enable 0 Interrupt clear enable register 0 The ICERO register allows disabling the peripheral interrupts or for reading the enabled state of those interrupts Enable interrupts through the ISERO registers Section 3 4 1 The bit description is as follows for all bits in this register Write Writing O has no effect writing 1 disables the interrupt Read 0 indicates that the interrupt is disabled 1 indicates that the interrupt is enabled All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 16 of 370 NXP Semiconductors UM10601
371. ircuit and the watchdog oscillator which can be selected or deselected during Deep sleep mode in the PDSLEEPCFG register The main clock and therefore all peripheral clocks are disabled except for the clock to the watchdog timer if the watchdog oscillator is selected The IRC is running but its output is disabled The flash is in stand by mode Deep sleep mode eliminates all power used by analog peripherals and all dynamic power used by the processor itself memory systems and related controllers and internal buses The processor state and registers peripheral registers and internal SRAM values are maintained and the logic levels of the pins remain static 5 7 5 1 Power configuration in Deep sleep mode Power consumption in Deep sleep mode is determined by the Deep sleep power configuration setting in the PDSLEEPCFG Table 47 register The watchdog oscillator can be left running in Deep sleep mode if required for the WWDT The BOD circuit can be left running in Deep sleep mode if required by the application 5 7 5 2 Programming Deep sleep mode The following steps must be performed to enter Deep sleep mode 1 The PM bits in the PCON register must be set to 0 1 Table 56 2 Select the power configuration in Deep sleep mode in the PDSLEEPCFG Table 47 register UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 63
372. is master on SCL Other masters in a multi master system could shorten this time This corresponds to the parameter in the IPC bus specification I C bus specification parameters tsu sto and tup srA have the same values and are also controlled by MSTSCLHIGH 0 0 2 clocks Minimum SCL high time is 2 clock of the 12C clock pre divider 0 1 clocks Minimum SCL high time is clocks of the I2C clock pre divider 0 2 4clocks Minimum SCL high time is 4 clock of the 12C clock pre divider 0x3 5 clocks Minimum SCL high time is 5 clock of the I2C clock pre divider 0x4 6clocks Minimum SCL high time is 6 clock of the 12C clock pre divider 0 5 7 clocks Minimum SCL high time is 7 clock of the 12C clock pre divider 0x6 8clocks Minimum SCL high time is 8 clock of the 12C clock pre divider 0x7 9 clocks Minimum SCL high time is 9 clocks of the 12C clock pre divider 317 Reserved Read value is undefined only zero should be written Master Data register The MSTDAT register provides the means to read the most recently received data for the Master function and to transmit data using the Master function Table 196 Master Data register MSTDAT address 0x4005 0028 bit description Bit Symbol Description Reset value 7 0 DATA Master function data register 0 Read read the most recently received data for the Master function Write transmit data using the Master function 31 8 Reserved Read
373. is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 188 of 370 NXP Semiconductors U M1 0601 Chapter 15 LPC81x USARTO 1 2 SYSCON block system clock SYSAHBCLKCTRL 14 16 main clock UARTCLKDIV USARTO BAUD SERIAL CLOCK UARTFRGMULT GENERATOR UARTFRGDIV USART1 BAUD SERIAL CLOCK U1 SCLK U PCLK GENERATOR UARTCLKDIV 1 MULT DIV USART2 TET BAUD SERIAL CLOCK GENERATOR Fig 29 USART clocking For details on the clock configuration see Section 15 7 1 Clocking and Baud rates 15 3 2 Configure the USART for wake up The USART can wake up the system from sleep mode in asynchronous or synchronous mode on any enabled USART interrupt If the USART is configured for synchronous slave mode the USART block can create an interrupt on a received signal even when the USART block receives no clocks from the ARM Cortex MO core that is in Deep sleep or Power down mode As long as the USART receives a clock signal from the master it can receive up to one byte in the RXDAT register while in Deep sleep or Power down mode Any interrupt raised as part of the receive data process can then wake up the part 15 3 2 1 Wake up from Sleep mode Configure the USART in either asynchronous mode or synchronous mode See Table 173 Enable the USART interrupt in the NVIC Any USART interrupt wakes up the part from slee
374. ister MONRXDAT address 0x4005 0080 bit description 228 Table 202 SPI Pin 234 Table 203 Register overview SPI base address 0x4005 8000 SPIO and 0x4008 C000 SPI 236 Table 204 SPI Configuration register CFG addresses 0x4005 8000 SP10 0x4005 C000 SPI1 bit description 237 Table 205 SPI Delay register DLY addresses 0x4005 8004 NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 358 of 370 NXP Semiconductors UM10601 SPIO 0x4005 C004 SPI1 bit description 238 Table 206 SPI Status register STAT addresses 0x4005 8008 SPIO 0x4005 C008 SPI1 bit description cece rind ee 239 Table 207 SPI Interrupt Enable read and Set register INTENSET addresses 0x4005 800C SPIO 0x4005 COOC SPI1 bit description 240 Table 208 SPI Interrupt Enable clear register INTENCLR addresses 0x4005 8010 SPIO 0x4005 C010 SPI1 bit description 242 Table 209 SPI Receiver Data register RXDAT addresses 0x4005 8014 SPIO 0x4005 C014 SPI1 bit descriptlori sez ccd the 242 Table 210 SPI Transmitter Data and Control register TXDATCTL addresses 0x4005 8018 SPIO 0x4005 C018 SPI1 bit description 243 Table 211 SPI Transmitter Data Register TXDAT addresses 0x4005 801C SPIO 0x4005 1 SPI1 bit description
375. ister is to allow the user to select a trade off between interrupt response time and determinism Setting this parameter to a very low value e g zero will guarantee the best possible interrupt performance but will also introduce a significant degree of uncertainty and jitter Requiring the system to always take a larger number of cycles whether it needs it or not will reduce the amount of uncertainty but may not necessarily eliminate it Theoretically the ARM Cortex MO core should always be able to service an interrupt request within 15 cycles However system factors external to the cpu such as bus latencies or peripheral response times can increase the time required to complete a previous instruction before an interrupt can be serviced Therefore accurately specifying a minimum number of cycles that will ensure determinism will depend on the application The default setting for this register is 0x010 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 42 of 370 NXP Semiconductors U M1 0601 UM10601 4 6 26 4 6 27 Chapter 4 LPC81x System configuration SYSCON Table 42 IRQ latency register IRQLATENCY address 0x4004 8170 bit description Bit Symbol Description Reset value 7 0 LATENCY 8 bit latency value 0x010 31 8 gt Reserved NMI source selection register The NMI source selection register sel
376. ith an address of 0x0000 0200 or greater Example G 512 T CR LF branches to address 0x0000 0200 in Thumb mode The GO command is usually used after the flash image has been updated and a RESET is desired For this the GO command should point to the RESET handler Since the device is still in ISP the RESET handler should do the following Re initialize the SP pointer to the application default Set the SYSMEMREMAP to either 0x01 or 0x02 While the ISP mode the SYSMEMREMAP is set to 0x00 Alternatively the following snippet can be loaded into the RAM for execution SCB gt AIRCR 0x05FA0004 Hissue system reset while 1 should never come here The snippet will issue a system reset request to the core 22 5 1 9 Erase sector s lt start sector number gt lt end sector number gt Table 247 UART ISP Erase sector command Command E Input Start Sector Number End Sector Number Should be greater than or equal to start sector number UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 284 of 370 NXP Semiconductors U M1 0601 Chapter 22 LPC81x Flash ISP and IAP programming Table 247 UART ISP Erase sector command Command E Return Code CMD SUCCESS BUSY INVALID SECTOR SECTOR NOT PREPARED FOR WRITE OPERATION CMD LOCKED PARAM ERROR CODE READ PROTECTION ENABLED Description This
377. ith parameters passed to the function Refer to Section 24 4 22 e 2C RESULT is a containing the results after the function executes All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 318 of 370 NXP Semiconductors U M1 0601 Chapter 24 LPC81x I2C bus ROM API To initiate a master mode write read the I2C_PARAM has to be setup I2C PARAM is a structure with various variables needed by the I2C ROM Driver to operate correctly The structure contains the following Number of bytes to be transmitted Number of bytes to be receive Pointer to the transmit buffer Pointer to the receive buffer Pointer to callback function Stop flag The RESULT structure contains the results after the function executes The structure contains the following Number of bytes transmitted Number of bytes received Remark The number of bytes transmitted will be updated for i2c master transmit intr and i2c master transmit poll The number of bytes received will only be update on i2c master receive poll 2 master receive intr i2c master tx rx poll and i2c master tx rx intr In all the master mode routines the transmit buffer s first byte must be the slave address with the R W bit set to 0 To enable a master read the receive buffer s first byte must be the slave address with the R W bit set to
378. ither of these requirements is not met set pl l returns PLL INVALID FREQ and returns as Result1 since the PLL setting is unchanged Param2 mode The first priority of set pllis to find a setup that generates the system clock at exactly the rate specified in Paramf If it is unlikely that an exact match can be found input parameter mode Param2 should be used to specify if the actual system clock can be less than or equal greater than or equal or approximately the value specified as the expected system clock Paramf A call specifying FREQ EQU will only succeed if the PLL can output exactly the frequency requested in Paramf CPU FREQ LTE can be used if the requested frequency should not be exceeded such as overall current consumption and or power budget reasons CPU FREQ GTE helps applications that need a minimum level of CPU processing capabilities CPU FREQ APPROX results in a system clock that is as close as possible to the requested value it may be greater than or less than the requested value If an illegal mode is specified set returns PLL INVALID MODE If the expected system clock is out of the range supported by this routine set pll returns PLL FREQ NOT FOUND In these cases the current PLL setting is not changed and Param0 is returned as Result1 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2
379. its MPORT register Zeroes in MASK enable the corresponding pins to be read from and written to MPORT Ones in MASK force a pin to read as 0 and its output bit to be unaffected by writes to MPORT When a port s MASK register contains all zeros its PORT and MPORT registers operate identically for reading and writing Applications in which interrupts can result in Masked GPIO operation or in task switching among tasks that do Masked GPIO operation must treat code that uses the Mask register as a protected restricted region This can be done by interrupt disabling or by using a semaphore The simpler way to protect a block of code that uses a MASK register is to disable interrupts before setting the MASK register and re enable them after the last operation that uses the MPORT or MASK register More efficiently software can dedicate a semaphore to the MASK registers and set capture the semaphore controlling exclusive use of the MASK registers before setting the MASK registers and release the semaphore after the last operation that uses the MPORT or MASK registers Recommended practices The following lists some recommended uses for using the GPIO port registers For initial setup after Reset or re initialization write the PORT registers To change the state of one pin write a Byte Pin or Word Pin register To change the state of multiple pins at a time write the SET and or CLR registers To change the state of multiple pins in
380. its in INTENSET are mapped in locations that correspond to the flags in the STAT register The complete set of interrupt enables may be read from this register Writing ones to implemented bits in this register causes those bits to be set The INTENCLR register is used to clear bits in this register See Table 206 for details of the interrupts Table 207 SPI Interrupt Enable read and Set register INTENSET addresses 0 4005 800C SPIO 0x4005 CO0C SPI1 bit description Bit Symbol Value Description Reset value 0 RXRDYEN Determines whether an interrupt occurs when receiver data is available 0 0 No interrupt will be generated when receiver data is available An interrupt will be generated when receiver data is available in the RXDAT register 1 TXRDYEN Determines whether an interrupt occurs when the transmitter holding register is 0 available 0 No interrupt will be generated when the transmitter holding register is available An interrupt will be generated when data may be written to TXDAT 2 RXOVEN Determines whether an interrupt occurs when a receiver overrun occurs This happens 0 in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use The interface prevents receiver overrun in Master mode by not allowing a new transmission to begin when a receiver overrun would otherwise occur 0 No interrupt will be generated when a receiver overrun occurs An interr
381. ity 3 lowest priority 13 8 These bits ignore writes and read as 0 15 14 IP PININT5 Interrupt Priority 0 highest priority 3 lowest priority 21 16 These bits ignore writes and read as O 23 22 IP PININT6 Interrupt Priority O highest priority 3 lowest priority 29 24 These bits ignore writes and read as O 31 30 IP PININT7 Interrupt Priority O highest priority 3 lowest priority UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 22 of 370 UM10601 Chapter 4 LPC81x System configuration SYSCON Rev 1 6 2 April 2014 User manual 4 1 How to read this chapter The system configuration block is identical for all LPC81x parts USART2 and SPI1 are only available on parts LPC812M101JDH20 and LPC812M101JDH16 and the corresponding clocks reset and wake up control bits are reserved for all other parts 4 2 Features Clock control Configure the system PLL Configure system oscillator and watchdog oscillator Enable clocks to individual peripherals and memories Configure clock output Configure clock dividers digital filter clock and USART baud rate clock Monitor and release reset to individual peripherals Select pins for external pin interrupts and pattern match engine Configuration of reduced power modes Wake up control BOD configuration MTB trac
382. k SPI_PCLK remains active in sleep mode the SPI can wake up the part independently of whether the SPI block is configured in master or slave mode In Deep sleep or Power down mode the SPI clock is turned off as are all peripheral clocks However if the SPI is configured in slave mode and an external master provides the clock signal the SPI can create an interrupt asynchronously This interrupt if enabled in the STARTERP 1 register in the NVIC and in the SPI s INTENSET register can then wake up the core 17 3 1 1 Wake up from Sleep mode Configure the SPI in either master or slave mode See Table 204 Enable the SPI interrupt in the NVIC Any SPI interrupt wakes up the part from sleep mode Enable the SPI interrupt in the INTENSET register Table 207 17 3 1 2 Wake up from Deep sleep or Power down mode Configure the SPI in slave mode See Table 204 You must connect the SCK function to a pin and connect the pin to the master Enable the SPI interrupt in the STARTERP 1 register See Table 46 Start logic 1 interrupt wake up enable register STARTERP1 address 0x4004 8214 bit description In the PDAWAKE register configure all peripherals that need to be running when the part wakes up Enable the SPI interrupt in the NVIC Enable the interrupt in the INTENSET register which configures the interrupt as wake up event Table 207 Examples are the following wake up events Achangein the state of the SSEL pin
383. k diagram 235 Fig 36 Basic SPI operating modes 247 Fig 37 Pre delay and Post delay timing 248 Fig 38 249 Fig 39 Transfer delay timing 250 Fig 40 Examples of data stalls 253 Fig 41 Comparator block diagram 256 Fig 42 CRC block diagram 261 Fig 43 Boot ROM 272 Fig 44 Boot process flowchart 275 Fig 45 IAP parameter passing 290 Fig 46 Power profiles pointer structure 298 Fig 47 LPC81x clock configuration for power API use 298 Fig 48 Power profiles 302 Fig 49 I2C bus driver routines pointer structure 307 Fig 50 12 slave mode set up address packing 318 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 361 of 370 NXP Semiconductors UM10601 30 6 Contents Chapter 30 Supplementary information Chapter 1 LPC81x Introductory information 1 1 Introduction 5 1 4 Block diagram 8 1 2 Features iis ete eee ew eee ee eee an 5 1 5 General description 9 1 3 Ordering
384. k source select register This register selects the clock source for the system PLL The SYSPLLCLKUEN register see Section 4 6 9 must be toggled from LOW to HIGH for the update to take effect Table 25 System PLL clock source select register SYSPLLCLKSEL address 0x4004 8040 bit description Bit Symbol Value Description Reset value 1 0 SEL System PLL clock source 0 0 0 IRC 0 1 Crystal Oscillator SYSOSC 0 2 Reserved 0x3 CLKIN External clock input 31 22 Reserved UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 34 of 370 NXP Semiconductors U M1 0601 Chapter 4 LPC81x System configuration SYSCON 4 6 9 System PLL clock source update register 4 6 10 4 6 11 This register updates the clock source of the system PLL with the new input clock after the SYSPLLCLKSEL register has been written to In order for the update to take effect first write a zero to the SYSPLLUEN register and then write a one to SYSPLLUEN Table 26 System PLL clock source update enable register SYSPLLCLKUEN address 0x4004 8044 bit description Bit Symbol Value Description Reset value 0 ENA Enable system PLL clock source update 0 0 No change 1 Update clock source 31 1 Reserved Main clock source select register This register selects the main system clock which can be the system PLL sys pllclkout
385. l Rev 1 6 2 April 2014 176 of 370 NXP Semiconductors U M1 0601 UM10601 12 6 2 12 6 3 Chapter 12 LPC81x Windowed Watchdog Timer WWDT Table 157 Watchdog operating modes selection WDEN WDRESET Mode of Operation 0 X 0or1 Debug Operate without the Watchdog running 1 0 Watchdog interrupt mode the watchdog warning interrupt will be generated but watchdog reset will not When this mode is selected the watchdog counter reaching the value specified by WOWARNINT will set the WDINT flag and the Watchdog interrupt request will be generated 1 1 Watchdog reset mode both the watchdog interrupt and watchdog reset are enabled When this mode is selected the watchdog counter reaching the value specified by WOWARNINT will set the WDINT flag and the Watchdog interrupt request will be generated and the watchdog counter reaching zero will reset the microcontroller A watchdog feed prior to reaching the value of WDWINDOW will also cause a watchdog reset Watchdog Timer Constant register The TC register determines the time out value Every time a feed sequence occurs the value in the TC is loaded into the Watchdog timer The TC resets to 0x00 OOFF Writing a value below OxFF will cause 0x00 OOFF to be loaded into the TC Thus the minimum time out interval is Twpcik x 256 x 4 If the WDPROTECT bit in WDMOD 1 an attempt to change the value of TC before the watchdog counter is below the values of WDWARNINT and WDWINDOW
386. lag bits are zero Table 137 SCT conflict flag register CONFLAG address 0x5000 40FC bit description Bit Symbol Description Reset value 3 0 NCFLAG Bit n is one if a no change conflict event occurred on outputn 0 since reset or a 1 was last written to this bit output 0 bit 0 output 1 bit 1 output 3 bit 3 29 4 Reserved 30 BUSERRL most recent bus error from this SCT involved writing CTR 0 L Unified STATE L Unified MATCH L Unified or the Output register when the L U counter was not halted A word write to certain L and H registers can be half successful and half unsuccessful 31 BUSERRH most recent bus error from this SCT involved writing CTR 0 H STATE H MATCH H or the Output register when the H counter was not halted SCT match registers 0 to 4 REGMODEn bit 0 Match registers are compared to the counters to help create events When the UNIFY bit is 0 the L and registers are independently compared to the L and counters When UNIFY is 1 the L and H registers hold a 32 bit value that is compared to the unified counter A Match can only occur in a clock in which the counter is running STOP and HALT are both 0 Match registers can be read at any time Writing to the MATCH L MATCH H or unified register is only allowed when the corresponding counter is halted HALT bits are set to 1 in the CTRL register Match events occur in the SCT clock in which the counter is or would be i
387. le LPC_I2C gt STAT amp if LPC_I2C gt S1 if data subaddress 2C gt SLVADRO 0x23 lt lt 1 2C gt CFG I2C CFG SLVEN pu AT SL LVSTA LVCON AT SL AT amp I2C STAT S 2C gt SLVCTL I2C SLVCTL S 12C_S1 AT amp I2C_STAT_SLVSTA LPC_I2C gt SLVDAT re l Qxaa abort L I2C SLVCTL SLVCON I2C STAT SL LVSTA AT amp I2C STAT S LVDAT bort 2C gt SLVCT 0xdd subaddress LPC_I2C gt S LVCON a 2C gt SLVCTL 12C_SLVCTL_S t address in address 0 register VPENDING I2C STAT SLVST ADDR abort TINUE ack address VPENDING I2C STAT SLVST RX abort ad subaddress TINUE ack data VPENDING I2C STAT SLVST RX abort read data into subaddress TINUE ack data All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 346 of 370 NXP Semiconductors UM1 0601 Chapter 29 LPC81x Code examples 29 2 15 Slave write one byte to master from subaddress Table 321 12C Code example Slave write one byte to master from subaddress Address 0x23 Polling mode LPC_I2C gt SLVADRO 0x23 lt lt 1 put address in address 0 register LPC I2C CFG I2C while LPC_I2C gt STAT amp I2C STAT SLVPENDING if LPC_I2C gt STAT amp I2C STAT SLVSTATE I2C STAT SLVST ADDR a
388. le 264 IAP Reinvoke 15 294 0000 bit 262 Table 265 IAP ReadUID command 294 Table 222 CRC seed register SEED address 0x5000 Table 266 IAP Erase page command 294 0004 bit description 262 Table 267 IAP Status codes Summary 294 Table 223 CRC checksum register SUM address 0x5000 Table 268 Memory mapping in debug mode 296 0008 bit 263 Table 269 Power profile calls 299 Table 224 CRC data register WR DATA address 0x5000 Table 270 1_ 299 0008 bit 263 Table 271 routine 302 Table 225 Register overview FMC base address 0x4004 Table 272 12 calls 307 0000 1 1 nei ec dine eee ering Picked 265 Table 273 ISR 309 Table 226 Flash configuration register FLASHCFG Table 274 126 Master Transmit Polling 309 address 0x4004 0010 bit description 265 Table 275 12C Master Receive Polling 310 Table 227 Flash Module Signature Start register Table 276 I2C Master Transmit and Receive Polling 310 FMSSTART 0x4004 0020 bit description 266 Table 277 I2C Master Transmit Interrupt 310 Table 228 Flash Modu
389. le Signature Stop register Table 278 I2C Master Receive Interrupt 311 FMSSTOP 0 4004 0024 bit description 266 Table 279 12C Master Transmit Receive Interrupt 311 Table 229 FMSWO register bit description FMSWO Table 280 I2C Slave Receive Polling 311 address 0 4004 0020 266 Table 281 12 Slave Transmit Polling 312 Table 230 Boot loader versions 270 Table 282 12 Slave Receive Interrupt 312 Table 231 Pin location in ISP mode 271 Table 283 I2C Slave Transmit Interrupt 312 Table 232 273 Table 284 12 Set Slave Address 313 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 359 of 370 NXP Semiconductors UM10601 Chapter 30 Supplementary information Table 285 126 Get Memory Size 313 Table 286 l2C Setup 313 Table 287 l2C Set Bit Rate 313 Table 288 12 Get Firmware Version 314 Table 289 l2C Get 5 lt 314 Table 290 l2C time out 314 Table 291 Error codes 314 Table 292 12 Status code 315 Table 293 UART calls
390. lid user code is as follows The reserved Cortex M0 exception vector location 7 offset 0 0000 001C in the vector table should contain the 2 s complement of the check sum of table entries 0 through 6 This causes the checksum of the first 8 table entries to be 0 The bootloader code checksums the first 8 locations in sector O of the flash If the result is 0 then execution control is transferred to the user code If the signature is not valid the auto baud routine synchronizes with the host via serial port USARTO The host should send a Ox3F as a synchronization character and wait for a response The host side serial port settings should be 8 data bits 1 stop bit and no parity The auto baud routine measures the bit time of the received synchronization character in All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 273 of 370 NXP Semiconductors U M1 0601 UM10601 Chapter 21 LPC81x Boot ROM terms of its own frequency the 12 MHz IRC frequency and programs the baud rate generator of the serial port It also sends an ASCII string Synchronized lt CR gt lt LF gt to the host In response the host should send the same string Synchronized CR LF The boot loader auto baud routine looks at the received characters to verify synchronization If synchronization is verified then OK lt CR gt lt LF gt string is
391. limit causes the counter to be cleared to zero in uni directional mode or to change the direction of count in bi directional mode Software can write to set or clear this bit at any time This bit applies to both the higher and lower registers when the UNIFY bit is set A one in this bit will cause a match on match register 0 to be treated as a de facto LIMIT condition without the need to define an associated event As with any LIMIT event this automatic limit causes the counter to be cleared to zero in uni directional mode or to change the direction of count in bi directional mode Software can write to set or clear this bit at any time This bit is not used when the UNIFY bit is set Reserved 10 6 2 UM10601 SCT control register If UNIFY 1 in the CONFIG register only the _L bits are used If UNIFY 0 in the CONFIG register this register can be written to as two registers CTRL_L and CTRL_H Both the L and H registers can be read or written individually or in a single 32 bit read or write operation All bits in this register can be written to when the counter is stopped or halted When the counter is running the only bits that can be written are STOP or HALT Other bits can be written in a subsequent write after HALT is set to 1 Remark If CLKMODE 0x3 is selected wait at least 12 system clock cycles between a write access to the H L or unified version of this register and the next write access This restriction does
392. ll information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 144 of 370 NXP Semiconductors U M1 0601 UM10601 Chapter 10 LPC81x SCTimer PWM SCT 10 6 9 SCT input register 10 6 10 Software can read the state of the SCT inputs in this read only register in slightly different forms 1 The AIN bit represents the input sampled by the SCT clock This corresponds to a nearly direct read out of the input but can cause spurious fluctuations in case of an asynchronous input signal 2 The SIN bit represents the input sampled by the SCT clock after the INSYNC select this signal is also used for event generation Ifthe INSYNC bit is set for the input the input is synchronized to the SCT clock using three SCT clock cycles resulting in a stable signal that is delayed by three SCT clock cycles Ifthe INSYNC bit is not set the SIN bit value is the same as the AIN bit value Table 129 SCT input register INPUT address 0x5000 4048 bit description Bit Symbol Description Reset value 0 AINO Input 0 state Direct read pin 1 AIN1 Input 1 state Direct read pin 2 AIN2 Input 2 state Direct read pin 3 AIN3 Input 3 state Direct read pin 15 4 Reserved 16 SINO Input 0 state 17 SIN1 Input 1 state 18 SIN2 Input 2 state 19 SIN3 Input 3 state 31 20 Reserved gt SCT match capture registers mode
393. ll rights reserved User manual Rev 1 6 2 April 2014 360 of 370 NXP Semiconductors UM10601 30 5 Figures Chapter 30 Supplementary information Fig 1 LPC81x block 8 Fig 51 USART driver routines pointer structure 322 Fig 2 LPC81x Memory 11 Fig 52 Connecting the SWD pins to a standard SWD Fig 3 LPC81x clock 26 COMMOCION usum bebe eta ee 330 Fig4 50 Fig 53 Pin configuration DIP8 package Fig5 System PLL block diagram 51 810 021 8 332 Fig6 Pin configuration 69 Fig 54 Pin configuration TSSOP16 package Fig 7 Pin interrupt connections 98 LPC811M001JDH16 and Fig 8 Pattern match engine connections 99 LPC812M101JDH16 332 Fig 9 Pattern match bit slice with detect logic 100 Fig 55 Pin configuration SO20 package Fig 10 Pattern match engine examples sticky edge 812 101 020 332 Plu Pm 119 Fig 56 Pin configuration TSSOP20 package Fig 11 Pattern match engine examples Windowed 812 101 20 333 non sticky edge detect evaluates as true 119 Fig 57 Pin configuration XSON16 package Fig 12 Pattern match engine examples Windowed
394. llowing sequence should be used 1 Make sure the USART is not currently sending or receiving data 2 Disable the USART by writing a 0 to the Enable bit 0 may be written to the entire register 3 Write the new configuration value with the ENABLE bit set to 1 Table 173 USART Configuration register CFG address 0x4006 4000 USARTO 0x4006 8000 USART1 0x4006 C000 USART2 bit description Bit Symbol Value Description Reset Value 0 ENABLE USART Enable 0 0 Disabled The USART is disabled and the internal state 3 2 DATALEN machine and counters are reset While Enable 0 all USART interrupts are disabled When Enable is set again CFG and most other control bits remain unchanged For instance when re enabled the USART will immediately generate a TxRdy interrupt if enabled in the INTENSET register because the transmitter has been reset and is therefore available Enabled The USART is enabled for operation Reserved Read value is undefined only zero should be NA written Selects the data size for the USART 00 Ox0 7 bit Data length 0 1 8 bit Data length Ox2 9 bit data length The 9th bit is commonly used for addressing in multidrop mode See the ADDRDET bit in the CTL register 0x3 Reserved 5 4 PARITYSEL Selects what type of parity is used by the USART 00 0x0 No parity 0x1 Reserved 0x2 Even parity Adds a bit to each character such that the number of 1s in a transmitted character is even and the
395. lock See Section 8 3 1 The pattern match engine output is assigned to an external pin through the switch matrix See Section 9 3 1 Connect an internal signal to a package pin for the steps that you need to follow to assign the GPIO pattern match function to a pin on the LPC81x package Table 91 Pin interrupt pattern match engine pin description Function Direction Pin Description SWM register Reference GPIO INT BMAT any GPIO pattern match PINASSIGN8 Table 117 output 8 5 General description Pins with configurable functions can serve as external interrupts or inputs to the pattern match engine You can configure up to eight pins total using the PINTSEL registers in the SYSCON block for these features UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 97 of 370 NXP Semiconductors U M1 0601 Chapter 8 LPC81x Pin interrupts pattern match engine 8 5 1 Pin interrupts From all available GPIO pins up to eight pins can be selected in the system control block to serve as external interrupt pins see Table 44 The external interrupt pins are connected to eight individual interrupts in the NVIC and are created based on rising or falling edges or on the input level on the pin SYSCON all pins PlOO_m BER pea gt NVIC pin interrupt 0 all pins m EDGE LEVEL NVIC pin interrupt 7 DET
396. lts are here when returned uint32 t n bytes sent uint32 t n bytes recd I2C RESULT Error structure The error code returned by the I2C ROM driver is an enum structure The Error structure is as follows typedef enum LPC_OK 0 lt enum value returned on Success ERROR ERR_I2C_BASE 0x00060000 0x00060001 ERR _I2C_NAK ERR_12C_BASEt1 0x00060002 ERR_I2C_BUFFER_OVERFLOW 0x00060003 ERR_I2C_BYTE_COUNT_ERR 0x00060004 ERR I2C LOSS OF ARBRITRATION 0x00060005 ERR I2C SLAVE ADDRESSED 0x00060006 ERR I2C LOSS OF ARBRITRATION NAK BIT 0x00060007 ERR I2C GENERAL FAILURE 0x00060008 ERR I2C RECS SET TO DEFAULT ErrorCode t 12C Mode The i2c get status function returns the current status of the I2C engine The return codes can be defined as an enum structure typedef enum I2C mode IDLE MASTER SEND MASTER RECEIVE SLAVE SEND SLAVE RECEIVE I2C MODE T 24 5 Functional description UM10601 24 5 1 I2C Set up Before calling any setup functions in the I2C ROM the application program is responsible for doing the following 1 Enable the clock to the I2C peripheral All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 316 of 370 NXP Semiconductors U M1 0601 UM10601 24 5 2 24 5 3 Chapter
397. lude the ROM driver structure set This routine sets up the system PLL according to the calling arguments If the expected clock can be obtained by simply dividing the system PLL input set p l bypasses the PLL to lower system power consumption Remark Before this routine is invoked the PLL clock source IRC system oscillator must be selected Table 25 the main clock source must be set to the input clock to the system PLL Table 27 and the system AHB clock divider must be set to 1 Table 29 set pll attempts to find a PLL setup that matches the calling parameters Once a combination of a feedback divider value SYSPLLCTRL M a post divider ratio SYSPLLCTRL P and the system AHB clock divider SYSAHBCLKDIV is found set pll applies the selected values and switches the main clock source selection to the system PLL clock out if necessary The routine returns a result code that indicates if the system PLL was successfully set PLL CMD SUCCESS or not in which case the result code identifies what went wrong The current system frequency value is also returned The application should use this information to adjust other clocks in the device the SSP UART and WDT clocks and or clockout Table 270 set pll routine Routine set pll Input ParamO0 system PLL input frequency in kHz Param1 expected system clock in KHz Param2 mode CPU FREQ CPU FREQ LTE CPU FREQ CPU FREQ APPROX Param3 system PL
398. ly and some flags can be cleared by writing a 1 to them Access to bits in this register varies RO Read only W1 write 1 to clear Details on the master and slave states described in the MSTSTATE and SLVSTATE bits in this register are listed in Table 187 and Table 188 Table 186 1 Status register STAT address 0x4005 0004 bit description Bit Symbol 0 MSTPENDING 3 1 MSTSTATE 4 MSTARBLOSS Value Description Reset Access value Master Pending Indicates that the Master is waiting to continue 1 RO 0 0 0 1 0 2 0x3 0x4 communication on the 12C bus pending or is idle When the master is pending the MSTSTATE bits indicate what type of software service if any the master expects This flag will cause an interrupt when set if enabled via the INTENSET register If the master is in the idle state and no communication is needed mask this interrupt In progress Communication is in progress and the Master function is busy and cannot currently accept a command Pending The Master function needs software service or is in the idle state If the master is not in the idle state it is waiting to receive or transmit data or the NACK bit Master State code The master state code reflects the master state 0 RO when the MSTPENDING bit is set that is the master is pending or in the idle state Each value of this field indicates a specific required service for the Master function All other values are reserved
399. manual 5 1 How to read this chapter The LPC81x provides an on chip API in the boot ROM to optimize power consumption in active and sleep modes See Table 269 Power profile API calls Read this chapter to configure the reduced power modes Deep sleep mode Power down mode and Deep power down mode 5 2 Features Reduced power modes control Low power oscillator control Five general purpose backup registers to retain data in Deep power down mode 5 3 Basic configuration The PMU is always on as long as Vpp is present If the open drain pins PIOO 10 and PIOO 11 are not pinned out you must enable their output driver and drive the outputs internally LOW to minimize power consumption in the low power modes See Section 6 3 5 3 1 Low power modes in the ARM Cortex M0 core Entering and exiting the low power modes is always controlled by the ARM Cortex M0 core The SCR register is the software interface for controlling the core s actions when entering a low power mode The SCR register is located on the ARM private peripheral bus For details see Ref 3 5 3 1 1 System control register The System control register SCR controls entry to and exit from a low power state This register is located on the private peripheral bus and is a R W register with reset value of 0x0000 0000 The SCR register allows to put the ARM core into sleep mode or the entire system in Deep sleep or Power down mode To set the low powe
400. mber of Bytes Number of bytes to be written Count should be a multiple of 4 Return Code CMD SUCCESS ADDR_ERROR Address not on word boundary ADDR_NOT_MAPPED COUNT_ERROR Byte count is not multiple of 4 PARAM_ERROR CODE_READ_PROTECTION_ENABLED Description This command is used to download data to RAM This command is blocked when code read protection levels 2 or 3 are enabled Writing to addresses below 0x1000 0300 is disabled for CRP1 Example W 268436224 4 lt CR gt lt LF gt writes 4 bytes of data to address 0x1000 0300 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 281 of 370 NXP Semiconductors U M1 0601 22 5 1 5 22 5 1 6 22 5 1 7 UM10601 Chapter 22 LPC81x Flash ISP and IAP programming Read Memory lt address gt lt number of bytes gt Reads the plain binary code of the data stream followed by the CMD_SUCCESS return code Table 243 UART ISP Read Memory command Command R Input Start Address Address from where data bytes are to be read This address should be a word boundary Number of Bytes Number of bytes to be read Count should be a multiple of 4 Return Code CMD_SUCCESS followed by actual data plain binary ADDR ERROR Address not on word boundary ADDR NOT MAPPED COUNT ERROR Byte count is not a multiple of 4 PARAM ERROR CODE READ PROTECTION ENA
401. me Access Address Description Reset value offset SYST CSR R W 0x010 System Timer Control and status register 0x000 0000 SYST_RVR R W 0x014 System Timer Reload value register 0 SYST_CVR R W 0x018 System Timer Current value register 0 SYST_CALIB R W 0x01C System Timer Calibration value register 0x4 1 Reset Value reflects the data stored in used bits only It does not include content of reserved bits 14 6 1 System Timer Control and status register The SYST CSR register contains control information for the SysTick timer and provides a status flag This register is part of the ARM Cortex MO core system timer register block For a bit description of this register see Ref 5 This register determines the clock source for the system tick timer UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 184 of 370 NXP Semiconductors U M1 0601 UM10601 14 6 2 14 6 3 Chapter 14 LPC81x ARM Cortex SysTick Timer SysTick Table 167 SysTick Timer Control and status register SYST_CSR 0xE000 E010 bit description Bit Symbol Description Reset value 0 ENABLE System Tick counter enable When 1 the counter is enabled 0 When 0 the counter is disabled 1 TICKINT System Tick interrupt enable When 1 the System Tick interrupt 0 is enabled When 0 the System Tick interrupt is disabled When enabled the interrupt is
402. me between SSEL assertion and the beginning of a data 0 transfer There is always one SPI clock time between SSEL assertion and the first clock edge This is not considered part of the pre delay 0 0 No additional time is inserted 0 1 1 SPI clock time is inserted 0 2 2 SPI clock times are inserted OxF 15 SPI clock times are inserted 7 4 POST_DELAY Controls the amount of time between the end of a data transfer and SSEL 0 deassertion 0x0 No additional time is inserted 0x1 1 SPI clock time is inserted 0 2 2 SPI clock times are inserted OxF 15 SPI clock times are inserted 11 8 FRAME DELAY If the EOF flag is set controls the minimum amount of time between the current frame 0 and the next frame or SSEL deassertion if EOT 0x0 No additional time is inserted 0 1 1 SPI clock time is inserted 0x2 2 SPI clock times are inserted OxF 15 SPI clock times are inserted 15 12 TRANSFER DELAY Controls the minimum amount of time that the SSEL is deasserted between transfers 0 0x0 The minimum time that SSEL is deasserted is 1 SPI clock time Zero added time 0 1 The minimum time that SSEL is deasserted is 2 SPI clock times 0x2 The minimum time that SSEL is deasserted is 3 SPI clock times OxF The minimum time that SSEL is deasserted is 16 SPI clock times 31 16 Reserved Read value is undefined only zero should be written NA UM10601 All information provided in this document is su
403. ment The value is the pin number to OxXFF be assigned to this function The following pins are available PIOO 0 2 0 to PIOO 17 Ox11 Pin assign register 7 Table 116 Pin assign register 7 PINASSIGN7 address 0x4000 C01C bit description Bit Symbol 7 0 CTOUT 1 O 15 8 CTOUT 2 O 23 16 CTOUT 3 O 31 24 12 SDA IO Description Reset value CTOUT 1 function assignment The value is the pin number to OxXFF be assigned to this function The following pins are available PIOO 0 0 to PIOO 17 0x11 CTOUT 2 function assignment The value is the pin number to OxFF be assigned to this function The following pins are available PIOO 0 2 0 to PIOO 17 Ox11 CTOUT function assignment The value is the pin number to OxXFF be assigned to this function The following pins are available PIOO 0 2 0 to PIOO 17 Ox11 I2C SDA function assignment The value is the pin number to be assigned to this function The following pins are available PIOO 0 2 0 to PIOO 17 Ox11 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 130 of 370 NXP Semiconductors UM10601 Chapter 9 LPC81x Switch matrix 9 5 9 Pin assign register 8 Table 117 Pin assign register 8 PINASSIGN8 address 0x4000 C020 bit description Bit Symbol Description Reset value 7 0 12 _ SCL IO I
404. ment is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 177 of 370 NXP Semiconductors U M1 0601 UM10601 12 6 4 12 6 5 12 6 6 Chapter 12 LPC81x Windowed Watchdog Timer WWDT Table 159 Watchdog Feed register FEED 0x4000 4008 bit description Bit Symbol Description Reset Value 7 0 FEED Feed value should be OxAA followed by 0x55 NA 31 8 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined Watchdog Timer Value register The WDTV register is used to read the current value of Watchdog timer counter When reading the value of the 24 bit counter the lock and synchronization procedure takes up to 6 WDCLK cycles plus 6 PCLK cycles so the value of WDTV is older than the actual value of the timer when it s being read by the CPU Table 160 Watchdog Timer Value register TV 0x4000 400C bit description Bit Symbol Description Reset Value 23 0 COUNT Counter timer value 0x00 OOFF 31 24 Reserved user software should not write ones to reserved bits The NA value read from a reserved bit is not defined Watchdog Timer Warning Interrupt register The WDWARNINT register determines the watchdog timer counter value that will generate a watchdog interrupt When the watchdog timer counter matches the value defined by WARNINT an interrupt will be generated after the subsequen
405. mers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 241 of 370 NXP Semiconductors UM10601 Chapter 17 LPC81x SPIO 1 17 6 5 SPI Interrupt Enable Clear register The INTENCLR register is used to clear interrupt enable bits in the INTENSET register 17 6 6 UM10601 Table 208 SPI Interrupt Enable clear register INTENCLR addresses 0x4005 8010 SPIO 0x4005 C010 SPI1 bit description Bit Symbol 0 RXRDYEN 1 TXRDYEN 2 RXOVEN 3 TXUREN 4 SSAEN 5 SSDEN 31 6 Description Writing 1 clears the corresponding bits in the INTENSET register Writing 1 clears the corresponding bits in the INTENSET register Writing 1 clears the corresponding bits in the INTENSET register Writing 1 clears the corresponding bits in the INTENSET register Writing 1 clears the corresponding bits in the INTENSET register Writing 1 clears the corresponding bits in the INTENSET register Reserved Read value is undefined only zero should be written Reset value SPI Receiver Data register The read only RXDAT register provides the means to read the most recently received data The value of SSEL can be read along with the data For details on the slave select process see Section 17 7 4 Table 209 SPI Receiver Data register RXDAT addresses 0x4005 8014 SPIO 0x4005 C014 SPI1 bit description Bit Symbol 15 0 RXDAT 16 RXSSEL_N 19 17 20 SOT 31 21 De
406. mination For put line function transfer without termination 0x01 For get line function stop transfer when 11 lt CR gt lt LF gt are received For uart put line function transfer is stopped after I reaching V lt CR gt lt LF gt characters are sent out after that 0x02 For uart get line function stop transfer when LP Il is received For uart_put_line function transfer is stopped after I reaching V A lt LF gt character is sent out after that 0x03 For uart_get_line function RESERVED All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 326 of 370 NXP Semiconductors UM1 0601 UM10601 Chapter 25 LPC81x USART API ROM driver routines 11 For uart put line function transfer is stopped after I reaching 0 uintl6_t driver mode 0x00 Polling mode function is blocked until transfer is II finished 0x01 Intr mode function exit immediately callback function Il is invoked when transfer is finished 0x02 RESERVED UART CALLBK T callback func pt callback function UART PARAM All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 327 of 370 UM10601 Chapter 26 LPC81x Debugging Rev 1 6 2 April 2014 User manual 26 1 How to read
407. mit Polling Table 274 Il2C RESULT ErrorCode ti2c master receive poll I2C HANDLE T 12C PARAM 12C Master Receive Polling Table 275 2 RESULT ErrorCode t i2c master tx rx poll l2C HANDLE l2C_PARAM I2C Master Transmit and Receive 276 Il2C RESULT Polling ErrorCode ti2c master transmit intr 2C HANDLE T 12C PARAM 12C Master Transmit Interrupt Table 277 126 RESULT ErrorCode ti2c master receive intr 2C HANDLE T 12C _ 12C Master Receive Interrupt Table 278 126 RESULT ErrorCode ti2c master tx rx intr I 2C HANDLE T I2C I2C Master Transmit Receive Table 279 I2C RESULT Interrupt UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 307 of 370 NXP Semiconductors UM10601 Table 272 12C API calls Chapter 24 LPC81x I2C bus ROM API API call ErrorCode t i2c slave receive poll I2C HANDLE 126 PARAM Il2C RESULT ErrorCode t i2c slave transmit poll IBC HANDLE l2C 126 RESULT ErrorCode t i2c slave receive intr I 2C HANDLE T I2C I2C RESULT ErrorCode t i2c slave transmit intr l2C HANDLE Il2C I2C RESULT ErrorCode ti2c set slave addr I2C HANDLE slave 0 3 slave mask 0 3 uint32 ti2c get mem size void I2C HANDLE T i2c setu
408. mitter is disabled after any character currently being transmitted is complete This feature can be used to facilitate software flow control Reserved Read value is undefined only zero should be NA written Continuous Clock generation By default SCLK is only 0 output while data is being transmitted in synchronous mode Clock on character In synchronous mode SCLK cycles only when characters are being sent on Un TXD or to complete a character that is being received Continuous clock SCLK runs continuously in synchronous mode allowing characters to be received on Un RxD independently from transmission on Un TXD Clear Continuous Clock 0 No affect on the CC bit Auto clear The CC bit is automatically cleared when a complete character has been received This bit is cleared at the same time Reserved Read value is undefined only zero should be NA written UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 196 of 370 NXP Semiconductors UM10601 15 6 3 Chapter 15 LPC81x USARTO 1 2 USART Status register The STAT register primarily provides a complete set of USART status flags for software to read Flags other than read only flags may be cleared by writing ones to corresponding bits of STAT Interrupt status flags that are read only and cannot be cleared by software can be masked using the INTE
409. module Rising edges falling edges or both edges can set the COMPEDGE bit and thus request an interrupt COMPEDGE and the interrupt request are cleared when software writes a 1 to EDGECLR UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 256 of 370 NXP Semiconductors U M1 0601 Chapter 18 LPC81x Analog comparator 18 5 4 Comparator outputs The comparator output conditioned by COMPSA bit can be routed to an external pin When COMPSA is 0 and the comparator interrupt is disabled the comparator can be used with the bus clock disabled Table 30 System clock control register SYSAHBCLKCTRL address 0x4004 8080 bit description to save power if the control registers don t need to be written The status of the comparator output can be observed through the comparator status register bit The comparator output can be routed to the SCT via the switch matrix allowing to capture the time of a voltage crossing or to count crossings in either or both directions See Section 18 3 1 Connect the comparator output to the SCT 18 6 Register description UM10601 18 6 1 Table 217 Register overview Analog comparator base address 0x4002 4000 Name Access Address Description Reset Reference offset value CTRL R W 0x000 Comparator control register 0 Table 218 LAD R W 0x004 Voltage ladder register 0
410. mpliant with the full I2C specification PIOO_12 3 2 2 1 PU PIOO_12 General purpose digital input output pin ISP entry on the SO20 TSSOP20 TSSOP16 packages starting with chip version 4C see Table 231 A LOW level on this pin during reset starts the ISP command handler See pin PIOO 1 for the DIP8 package and chip versions 1A and 2A PIOO 13 2 1 B VO PIOO 13 General purpose digital input output pin PIOO 14 20 VO PIOO 14 General purpose digital input output pin PIOO 15 11 VO PIOO 15 General purpose digital input output pin PIOO 16 10 1 VO E PU 16 General purpose digital input output pin PIOO 17 1 VO PIOO 17 General purpose digital input output pin Vpp 15 12 6 E 3 3 V supply voltage Vss 16 13 7 Ground 1 Pin state at reset for default function Input Al Analog Input O Output PU internal pull up enabled pins pulled up to full Vpp level IA inactive no pull up down enabled 2 5 V tolerant pad providing digital I O functions with configurable pull up pull down resistors and configurable hysteresis includes high current output driver 3 True open drain pin I2C bus pins compliant with the I2C bus specification for 12 standard mode I2C Fast mode and 12C Fast mode Plus Do not use this pad for high speed applications such as SPI or USART Remark If this pin is not available on the package prevent it
411. n description When the ISP entry pin see Table 233 is pulled LOW on reset the part enters ISP mode and the ISP command handler starts up In ISP mode pin PIOO 0 is connected to function UO RXD and pin PIOO 4 is connected to function UO TXD on the USARTO block Remark The ISP entry pin location depends on the chip version and package See Table 231 22 4 General description 22 4 4 Flash configuration Most IAP and ISP commands operate on sectors and specify sector numbers In addition a page erase command is supported The following table shows the correspondence between page numbers sector numbers and memory addresses UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 276 of 370 NXP Semiconductors U M1 0601 UM10601 22 4 2 Chapter 22 LPC81x Flash ISP and IAP programming The size of a sector is 1 kB and the size of a page is 64 Byte One sector contains 16 pages Table 234 LPC81x flash configuration Sector Sector Page Address range 4kB 8 kB 16 kB number size number flash flash flash kB 0 1 0 15 0x0000 0000 0x0000 yes yes yes 1 1 16 31 0x0000 0400 0x0000 07FF yes yes yes 2 1 32 47 0x0000 0800 0x0000 OBFF yes yes yes 3 1 48 63 0x0000 0x0000 OFFF yes yes yes 4 1 64 79 0x0000 1000 0x0000 13FF yes yes 5 1 80 95 0x0000 1400 0x0000 17FF yes yes 6 1 96
412. n register 139 10 6 18 SCT match registers 0 to 4 REGMODEn 10 6 2 SCT control register 140 po RET 149 10 6 3 SCT limit register 142 10 6 19 SCT capture registers 0 to 4 REGMODEn bit 10 6 4 halt condition register 142 zl dence dat ees 150 10 6 5 SCT stop condition register 143 10 6 20 SCT match reload registers 0 to 4 REGMODEn 10 6 6 SCT start condition register 143 bitS tiU ke 150 10 6 7 SCT counter register 143 10 6 21 SCT capture control registers 0 to 4 REGMODEn 10 6 8 SCT state 144 1 150 10 6 9 input register 145 10 6 22 SCT event state mask registers 0 to 5 151 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 364 of 370 NXP Semiconductors UM10601 Chapter 30 Supplementary information 10 6 28 SCT event control registers 0 to 5 151 10 7 8 Match vs I O events 157 10 6 24 SCT output set registers 0 to 3 153 10 79 5 158 10 6 25 SCT output clear registers 0 t03 153 10 7 10 Configure the SCT 158 10 7 Functional description 154 1
413. n the same pin number to the ACMP OUT function and an SCT input CTIN n This connects the comparator output to input n of the SCT You can loop back the USART transmit output to the receive input by assigning the same pin number to Un RXD and Un TXD It is not allowed to connect more than one output or bidirectional function to a pin When you assign any function to a pin through the switch matrix the GPIO output becomes disabled Enabling any analog fixed pin function disables all digital functions on the same pin UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 124 of 370 NXP Semiconductors UM10601 Chapter 9 LPC81x Switch matrix 9 41 Movable functions Table 107 Movable functions assign to pins PIOO 0 to PIOO 17 through switch matrix Function name Description SWM Pin assign Reference register UO TXD O Transmitter output for USARTO PINASSIGNO Table 109 UO RXD Receiver input for USARTO PINASSIGNO Table 109 UO RTS Request To Send output for USARTO PINASSIGNO Table 109 UO CTS Clear To Send input for USARTO PINASSIGNO Table 109 UO SCLK Serial clock input output for USARTO in synchronous PINASSIGN1 Table 110 mode U1_TXD Transmitter output for USART1 PINASSIGN1 Table 110 U1_RXD Receiver input for USART1 PINASSIGN1 Table 110 U1 RTS Request To Send output for USART1 PI
414. ncremented to the next value When a Match event limits its counter as described in Section 10 6 3 the value in the Match register is the last value of the counter before it is cleared to zero or decremented if BIDIR is 1 There is no write through from Reload registers to Match registers Before starting a counter software can write one value to the Match register used in the first cycle of the counter and a different value to the corresponding Match Reload register used in the second cycle All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 149 of 370 NXP Semiconductors U M1 0601 UM10601 10 6 19 10 6 20 10 6 21 Chapter 10 LPC81x SCTimer PWM SCT Table 138 SCT match registers 0 to 4 MATCH 0 4 address 0x5000 4100 MATCHO to 0x5000 4110 MATCH4 bit description REGMODEn bit 0 Bit Symbol Description Reset value 15 0 VALMATCH L When UNIFY read or write the 16 bit value to be compared 0 to the L counter When UNIFY 1 read or write the lower 16 bits of the 32 bit value to be compared to the unified counter 31 16 VALMATCH When UNIFY 0 read or write the 16 bit value to be compared 0 to the H counter When UNIFY 1 read or write the upper 16 bits of the 32 bit value to be compared to the unified counter SCT capture registers 0 to 4 REGMODEn bit 1 These registers allow softwa
415. nformation provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 350 of 370 NXP Semiconductors UM10601 Chapter 29 29 3 10 Transmit and receive 24 bits to master Table 333 SPI Code example LPC81x Code examples Transmit and receive 24 bits to master LPC SPI CFG SPI ENABLE while LPC_SPI gt STAT amp SPI STAT TXRDY LPC_SPI gt TXDATCTL SPI TXDATCTL FLEN 15 0xdddd while LPC_SPI gt STAT amp SPI STAT TXRDY LPC_SPI gt TXDATCTL SPI TXDATCTL FLEN 7 Oxdd while LPC_SPI gt STAT amp SPI STAT RXRDY data LPC_SPI gt RXDAT if data Oxdddd abort while LPC_SPI gt STAT amp SPI STAT RXRDY data LPC_SPI gt RXDAT if data 0 abort 29 4 Code examples UART 29 4 1 Definitions Table 334 UART Code example UART defines define UART_CFG_ENABLE 0 1 lt lt 0 define UART_CFG_DATALEN d d 7 lt lt 2 define UART_STAT_RXRDY 0 1 lt lt 0 define UART_STAT_TXRDY 0 1 lt lt 2 define UART_STAT_TXIDLE 0 1 lt lt 3 29 4 2 Interrupt handler Table 335 UART Code example Interrupt handler void Usart_IRQHandler uint32_t intstat LPC_USART gt INTSTAT if intstat amp UART_STAT_RXRDY if tx rdy flag abort tx rdy flag 0 LPC_USART gt TXDAT LPC_USART gt RXDAT LPC_USART
416. ng edge interrupt disabled 31 8 Reserved Pin interrupt rising edge register This register contains ones for pin interrupts selected in the PINTSELn registers see Section 4 6 27 on which a rising edge has been detected Writing ones to this register clears rising edge detection Ones in this register assert an interrupt request for pins that are enabled for rising edge interrupts All edges are detected for all pins selected by the PINTSELn registers regardless of whether they are interrupt enabled Table 100 Pin interrupt rising edge register RISE address 0xA000 401C bit description Bit Symbol Description Reset Access value 70 RDET Rising edge detect Bit n detects the rising edge of the pin 0 R W selected in PINTSELn Read 0 No rising edge has been detected on this pin since Reset or the last time a one was written to this bit Write 0 no operation Read 1 a rising edge has been detected since Reset or the last time a one was written to this bit Write 1 clear rising edge detection for this pin 31 8 Reserved All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 105 of 370 NXP Semiconductors U M1 0601 UM10601 8 6 9 8 6 10 8 6 11 Chapter 8 LPC81x Pin interrupts pattern match engine Pin interrupt falling edge register This register contains ones for pin interrupts selec
417. nified register is only allowed when the corresponding counter is halted HALT bits are set to 1 in the CTRL register The state variable is the main feature that distinguishes the SCT from other counter timer PWM blocks Events can be made to occur only in certain states Events in turn can perform the following actions set and clear outputs limit stop and start the counter cause interrupts modify the state variable The value of a state variable is completely under the control of the application If an application does not use states the value of the state variable remains zero which is the default value A state variable can be used to track and control multiple cycles of the associated counter in any desired operational sequence The state variable is logically associated with a state machine diagram which represents the SCT configuration See Section 10 6 22 and 10 6 23 for more about the relationship between states and events The STATELD STADEVY fields in the event control registers of all defined events set all possible values for the state variable The change of the state variable during multiple counter cycles reflects how the associated state machine moves from one state to the next Table 128 SCT state register STATE address 0x5000 4044 bit description Bit Symbol Description Reset value 4 0 STATE L State variable 0 15 5 Reserved 20 16 STATE State variable 0 31 21 Reserved UM10601 A
418. nitor Overrun interrupt Enable The MonOv interrupt is disabled The MonOv interrupt is enabled Reserved Read value is undefined only zero should be written Reset value 0 NA NA NA NA NA NA NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 219 of 370 NXP Semiconductors UM10601 UM10601 16 6 4 Chapter 16 LPC81x I2C bus interface Table 189 Interrupt Enable Set and read register INTENSET address 0x4005 0008 bit description Bit Symbol Value Description Reset value 19 MONIDLEEN Monitor Idle interrupt Enable 0 0 The Monldle interrupt is disabled 1 The Monldle interrupt is enabled 23 20 Reserved Read value is undefined only zero NA should be written 24 EVENTTIMEOUTEN Event time out interrupt Enable 0 0 The Event time out interrupt is disabled 1 The Event time out interrupt is enabled 25 SCLTIMEOUTEN SCL time out interrupt Enable 0 0 The SCL time out interrupt is disabled 1 The SCL time out interrupt is enabled 31 26 Reserved Read value is undefined only zero NA should be written Interrupt Enable Clear register Writing a 1 to a bit position in INTENCLR clears the corresponding position in the INTENSET register disabling that interrupt INTENCLR is a write only register Bits that do not correspond to defined bits in INTENSET are reserved and only zeroes should be written to them Table 190 Interrupt Enable Clear re
419. nitor data has not overrun Overrun A Monitor data overrun has occurred This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register Writing 1 to this bit clears the flag 18 MONACTIVE Monitor Active flag This flag indicates when the Monitor function 0 RO considers the IC bus to be active Active is defined here as when some Master is on the bus a bus Start has occurred more recently than a bus Stop 0 Inactive The Monitor function considers the 12C bus to be inactive Active The Monitor function considers the 12C bus to be active 19 MONIDLE Monitor Idle flag This flag is set when the Monitor function sees the 0 W1 12 bus change from active to inactive This can be used by software to decide when to process data accumulated by the Monitor function This flag will cause an interrupt when set if enabled via the INTENSET register The flag can be cleared by writing a 1 to this bit 0 Not idle The 12C bus is not idle or this flag has been cleared by software 1 Idle The 12 bus has gone idle at least once since the last time this flag was cleared by software 23 20 Reserved Read value is undefined only zero should be written NA NA UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 217 of 370 NXP Semiconductors U M1 0601 Chapter 16 LPC81x I2C bus interface Table 1
420. not apply when writing to the HALT bit or bits and then writing to the CTRL register again to restart the counters for example because software must update the MATCH register which is only allowed when the counters are halted All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 140 of 370 NXP Semiconductors UM10601 Chapter 10 LPC81x SCTimer PWM SCT Table 122 SCT control register CTRL address 0x5000 4004 bit description Bit Symbol 0 DOWN_L 1 STOP_L 2 HALT_L CLRCTR_L BIDIR_L 12 5 PRE_L 1543 16 DOWN_H 17 STOP_H 18 HALT H 19 CLRCTRH 20 BIDIR H Value Description Reset value This bit is 1 when the L or unified counter is counting down Hardware sets this bit 0 when the counter limit is reached and BIDIR is 1 Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0 When this bit is 1 and HALT is 0 the L or unified counter does not run but I O events 0 related to the counter can occur If such an event matches the mask in the Start register this bit is cleared and counting resumes When this bit is 1 the L or unified counter does not run and no events can occur 1 reset sets this bit When the HALT L bit is one the STOP L bit is cleared If you want to remove the halt condition and keep the SCT in the stop condition no
421. ns Name Pattern Description programmed in 0x0000 02FC NO ISP 0 4 69 7370 CRP1 0x12345678 CRP2 0x87654321 CRP3 0x43218765 Prevents sampling of the ISP entry pin for entering ISP mode The ISP entry pin is available for other uses Access to chip via the SWD pins is disabled This mode allows partial flash update using the following ISP commands and restrictions Write to RAM command should not access RAM below 0x1000 0300 Access to addresses below 0x1000 0200 is disabled Copy RAM to flash command can not write to Sector 0 Erase command can erase Sector 0 only when all sectors are selected for erase Compare command is disabled Read Memory command is disabled This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased Since compare command is disabled in case of partial updates the secondary loader should implement checksum mechanism to verify the integrity of the flash Access to chip via the SWD pins is disabled The following ISP commands are disabled Read Memory Write to RAM Go Copy RAM to flash Compare When CRP2 is enabled the ISP erase command only allows erasure of all user sectors Access to chip via the SWD pins is disabled ISP entry by pulling the ISP entry pin LOW is disabled if a valid user code is present in flash sector 0 This mode effectively disables ISP override using the ISP entry pin It is up to the user s applica
422. ns PINASSIGNO to 8 All movable functions are digital functions Assign movable functions to pin numbers through the 8 bits of the PINASSIGN register associated with this function Once the function is assigned a pin PIOO n it is connected through this pin to a physical pin on the package Remark You can assign only one digital output function to an external pin at any given time Remark You can assign more than one digital input function to one external pin 2 Fixed pin functions PINENABLEO Some functions require pins with special characteristics and cannot be moved to other physical pins Hence these functions are mapped to a fixed port pin Examples of fixed pin functions are the oscillator pins or comparator inputs Each fixed pin function is associated with one bit in the PINENABLEO register which selects or deselects the function Ifa fixed pin function is deselected any movable function can be assigned to its port and pin Ifa fixed pin function is deselected and no movable function is assigned to this the pin is assigned its GPIO function On reset all fixed pin functions are deselected Ifa fixed pin analog function is selected its assigned pin cannot be used for other function UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 126 of 370 NXP Semiconductors UM10601
423. nsfer_delay timing UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 250 of 370 NXP Semiconductors U M1 0601 17 7 3 17 7 3 1 17 7 4 17 7 5 UM10601 Chapter 17 LPC81x SPIO 1 Clocking and data rates In order to use the SPI clocking details must be defined This includes configuring the system clock and selection of the clock divider value in DIV See Figure 34 Data rate calculations The SPI interface is designed to operate asynchronously from any on chip clocks and without the need for overclocking In slave mode this means that the SCK from the external master is used directly to run the transmit and receive shift registers and other logic In master mode the SPI rate clock produced by the SPI clock divider is used directly as the outgoing SCK The SPI clock divider is an integer divider The SPI in master mode can be set to run at the same speed as the selected PCLK or at lower integer divide rates The SPI rate will be PCLK SPIn DIVVAL In slave mode the clock is taken from the SCK input and the SPI clock divider is not used Slave select The SPI block provides for one Slave Select input in slave mode or output in master mode The SSEL can be set for normal polarity active low or can be inverted active high Representation of the SSEL in a register is always active low If the SSEL i
424. ny given time bits 0 2 5 and or 7 may be high if the corresponding product terms are currently matching The remaining bits will always be low All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 118 of 370 NXP Semiconductors U M1 0601 Chapter 8 LPC81x Pin interrupts pattern match engine 8 7 3 Pattern match engine edge detect examples slice 0 INOre SRCO 0 CFGO 0x3 PROD_ENPTSO 0x0 sticky rising edge detection slice 1 IN1ev minterm IN1 INOre IN1ev pin interrupt raised on falling edge on input 1 any time NVIC pin interrupt 1 and GPIO_INT_BMAT output after INO has gone HIGH SRC1 1 CFG1 0 7 PROD_ENPTS1 0x1 non sticky edge detection Figure shows pattern match functionality only and accurate timing is not implied Inputs INn are shown synchronized to the system clock for simplicity Fig 10 Pattern match engine examples sticky edge detect slice 0 INO SRCO 0 0x4 PROD ENPTSO 0x0 high level detection slice 1 IN1ev minterm f INOIN1ev IN1 A pin interrupt raised on rising edge of IN1 during NVIC pin interrupt 1 and GPIO INT BMAT output the HIGH level ot ING SRC1 1 CFG1 0 7 PROD_ENPTS1 0x1 non sticky edge detection J Figure shows pattern match functionality only and accurate timing is not implied In
425. o bit O of this register then write a one UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 38 of 370 NXP Semiconductors U M1 0601 UM10601 4 6 17 4 6 18 Chapter 4 LPC81x System configuration SYSCON Table 33 CLKOUT clock source update enable register CLKOUTUEN address 0x4004 80E4 bit description Bit Symbol Value Description Reset value 0 ENA Enable CLKOUT clock source update 0 0 No change 1 Update clock source 31 1 Reserved CLKOUT clock divider register This register determines the divider value for the signal on the CLKOUT pin Table 34 CLKOUT clock divider registers CLKOUTDIV address 0 4004 80E8 bit description Bit Symbol Description Reset value 7 0 DIV CLKOUT clock divider values 0 0 Disable CLKOUT clock divider 1 Divide by 1 to 255 Divide by 255 31 8 Reserved USART fractional generator divider value register All USART peripherals share a common clock U_PCLK which can be adjusted by a fractional divider U_PCLK UARTCLKDIV 1 MULT DIV UARTCLKDIV is the USART clock configured in the UARTCLKDIV register The fractional portion 1 MULT DIV is determined by the two USART fractional divider registers in the SYSCON block 1 The DIV value programmed in this register is the denominator of the divider used by the fractional rate generator to cr
426. o disable any unused bit slices 0 7 Event Non sticky rising or falling edge Match occurs on an event i e when either a rising or falling edge is first detected on the specified input this is a non sticky version of value 0x3 This bit is cleared after one clock cycle 19 17 CFG3 Specifies the match contribution condition for bit slice 3 0b000 0x0 Constant HIGH This bit slice always contributes to a product term match 0 1 Sticky rising edge Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0 2 Sticky falling edge Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0x3 Sticky rising or falling edge Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0 4 High level Match for this bit slice occurs when there is a high level on the input specified for this bit slice in the PMSRC register 0 5 Low level Match occurs when there is a low level on the specified input Ox6 Constant 0 This bit slice never contributes to a match should be
427. ocation and the matching ECC byte are evaluated If the ECC mechanism detects a single error in the fetched data a correction will be applied before data are provided to the CPU When a write request into the user accessible Flash is made writing the user specified content is accompanied by a matching ECC value calculated and stored in the ECC memory All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 277 of 370 NXP Semiconduc tors UM10601 22 4 3 Chapter 22 LPC81x Flash ISP and IAP programming When a sector of Flash memory is erased the corresponding ECC bits are also erased Once a 6 bit ECC is written it can not be updated unless it is erased first Therefore for the implemented ECC mechanism to perform properly data must be written into the flash memory in groups of 4 bytes or multiples of 4 aligned as described above Code Read Protection CRP Code Read Protection is a mechanism that allows the user to enable different levels of security in the system so that access to the on chip flash and use of the ISP can be restricted When needed CRP is invoked by programming a specific pattern in flash location at 0x0000 02FC IAP commands are not affected by the code read protection Important any CRP change becomes effective only after the device has gone through a power cycle Table 235 Code Read Protection optio
428. ock Examples of functions are the GPIOs the UART transmit output TXD or the clock output CLKOUT Many peripherals have several functions that must be connected to external pins The switch matrix also enables the output driver for digital functions that are outputs The electrical pin characteristics for both inputs and outputs internal pull up down resistors inverter digital filter open drain mode are configured by the IOCON block for each pin On the LPC81x most functions can be assigned through the switch matrix to any external pin that is not a power or ground pin These functions are called movable functions A few functions like the crystal oscillator pins XTALIN XTALOUT or the analog comparator inputs can only be assigned to one particular external pin with the appropriate electrical characteristics These functions are called fixed pin functions If a fixed pin function is not used it can be replaced by any other movable function For fixed pin analog functions the switch matrix enables the analog input or output and disables the digital pad GPIOs are special fixed pin functions Each GPIO is assigned to one and only one external pin by default External pins are therefore identified by their fixed pin GPIO function The level on a digital input is always reflected in the GPIO port register and in the pin interrupt pattern match state if selected regardless of which digital function is assigned to the pin through the swi
429. ode the counter begins to count down from the current value on the next clock edge Set the corresponding event bit in the HALT register for the event to halt the counter If the counter is halted it stops counting and no new events can occur The counter operation can only be restored by clearing the HALT_L and or the HALT_H bits in the CTRL register Set the corresponding event bit in the STOP register for the event to stop the counter If the counter is stopped it stops counting However an event that is configured as a transition on an input output can restart the counter Set the corresponding event bit in the START register for the event to restart the counting Only events that are defined by an input changing can be used to restart the counter 4 Define which events contribute to the SCT interrupt UM10601 Set the corresponding event bit in the EVEN and the EVFLAG registers to enable the event to contribute to the SCT interrupt All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 159 of 370 NXP Semiconductors U M1 0601 Chapter 10 LPC81x SCTimer PWM SCT 10 7 10 4 Configure multiple states 1 In the EVn_STATE register for each event up to 6 events one register per event select the state or states up to 2 in which this event is allowed to occur Each state can be selected for more than one event
430. of 370 NXP Semiconductors U M1 0601 UM10601 Chapter 5 LPC81x Reduced power modes and Power Management 3 Select the power configuration after wake up in the PDAWAKECFG Table 48 register 4 If any of the available wake up interrupts are needed for wake up enable the interrupts in the interrupt wake up registers Table 45 Table 46 and in the NVIC 5 Select the IRC as the main clock See Table 27 6 Write one to the SLEEPDEEP bit in the ARM Cortex M0 SCR register Table 53 7 Use the ARM WFI instruction 5 7 5 3 Wake up from Deep sleep mode The microcontroller can wake up from Deep sleep mode in the following ways Signal on one of the eight pin interrupts selected in Table 44 Each pin interrupt must also be enabled in the STARTERPO register Table 45 and in the NVIC e BOD signal if the BOD is enabled the PDSLEEPCFG register BOD interrupt using the deep sleep interrupt wake up register 1 Table 46 The BOD interrupt must be enabled in the NVIC The BOD interrupt must be selected in the BODCTRL register Reset from the BOD circuit In this case the BOD circuit must be enabled in the PDSLEEPCFG register and the BOD reset must be enabled in the BODCTRL register Table 40 WWDT signal if the watchdog oscillator is enabled in the PDSLEEPCFG register WWDT interrupt using the interrupt wake up register 1 Table 46 The WWDT interrupt must be enabled in the NVIC The WWDT interrupt
431. ofile ROM driver Invalid frequency selection system clock divider restrictions command 0 12000 command 1 40 command 2 CPU FREQ LTE command 3 0 LPC PWRD API set pll command result The above code specifies a 12 MHz PLL input clock a system clock of no more than 40 kHz and no time out while waiting for the PLL to lock Since the maximum divider value for the system clock is 255 and running at 40 kHz would need a divide by value of 300 set returns PLL INVALID FREQ in 0 and 12000 in result 1 without changing the PLL settings Exact solution cannot be found PLL command 0 12000 command 1 25000 command 2 CPU_FREQ_EQU command 3 0 LPC_PWRD_API gt set_pll command result The above code specifies a 12 MHz PLL input clock and a system clock of exactly 25 MHz The application was ready to infinitely wait for the PLL to lock Since there is no valid PLL setup within earlier mentioned restrictions set pll returns PLL FREQ NOT FOUND in result 0 and 12000 in result 1 without changing the PLL settings System clock less than or equal to the expected value command 0 12000 command 1 25000 command 2 CPU FREQ LTE command 3 0 LPC PWRD API set pll command result The above code specifies a 12 MHz PLL input clock a system clock of no more than 25 MHz and no locking time out set_p returns PLL CMD SUCCESS in result 0 and 24000 in result 1 The
432. og within a predetermined amount of time When a watchdog window is programmed an early watchdog feed is also treated as a watchdog event This allows preventing situations where a system failure may still feed the watchdog For example application code could be stuck in an interrupt service that contains a watchdog feed Setting the window such that this would result in an early feed will generate a watchdog event allowing for system recovery The Watchdog consists of a fixed divide by 4 pre scaler and a 24 bit counter which decrements when clocked The minimum value from which the counter decrements is OxFF Setting a value lower than OxFF causes OxFF to be loaded in the counter Hence the minimum Watchdog interval is Twpcik x 256 x 4 and the maximum Watchdog interval is TwpcLk x 224 x 4 in multiples of x 4 The Watchdog should be used in the following manner e Set the Watchdog timer constant reload value the TC register Set the Watchdog timer operating mode in the MOD register e Seta value for the watchdog window time the WINDOW register if windowed operation is desired Seta value for the watchdog warning interrupt in the WARNINT register if a warning interrupt is desired Enable the Watchdog by writing OxAA followed by 0x55 to the FEED register The Watchdog must be fed again before the Watchdog counter reaches zero in order to prevent a watchdog event If a window value is programmed the feed
433. ollowed by the offset of first mismatch COUNT_ERROR Byte count is not a multiple of 4 ADDR_ERROR ADDR_NOT_MAPPED PARAM_ERROR Description This command is used to compare the memory contents at two locations Example M 8192 268468224 4 lt CR gt lt LF gt compares 4 bytes from the RAM address 0x1000 8000 to the 4 bytes from the flash address 0x2000 ReadUID Table 253 UART ISP ReadUID command Command N Input None Return Code CMD SUCCESS followed by four 32 bit words of E sort test information in ASCII format The word sent at the lowest address is sent first Description This command is used to read the unique ID Read CRC checksum address no of bytes gt Get the CRC checksum of a block of RAM or flash CMD SUCCESS followed by 8 bytes of CRC checksum in ASCII format The checksum is calculated as follows All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 286 of 370 NXP Semiconductors U M1 0601 Chapter 22 LPC81x Flash ISP and IAP programming CRC 32 polynomial x32 x26 x23 x22 x16 12 11 10 8 7 X5 X4 2 1 Seed Value OxFFFF FFFF No bit order reverse for data input No 1 s complement for data input No bit order reverse for CRC sum No 1 s complement for CRC sum Table 254 UART ISP Read CRC checksum command Command S Input Address
434. ollowing cases INTVALn register is updated in the idle state INTVALn register is updated with LOAD 1 When the timer is in idle state reading this bit fields returns 1 OxOOFF FFFF 31 Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 168 of 370 NXP Semiconductors U M1 0601 UM10601 11 6 3 11 6 4 11 6 5 Chapter 11 LPC81x Multi Rate Timer MRT Control register The control register configures the mode for each MRT and enables the interrupt Table 151 Control register CTRL 0 3 address 0x4000 4008 CTRLO to 0x4000 4038 CTRL3 bit description Bit Symbol Value Description Reset value 0 INTEN Enable the TIMERn interrupt 0 0 Disable 1 Enable 2 1 MODE Selects timer mode 0 0x0 Repeat interrupt mode 0x1 One shot interrupt mode 0x2 One shot bus stall mode 0x3 Reserved 31 3 Reserved 0 Status register This register indicates the status of each MRT Table 152 Status register STAT 0 3 address 0x4000 400C STATO to 0x4000 403C STAT3 bit description Bit Symbol Value Description Reset value 0 INTFLAG Monitors the interrupt flag 0 0 No pending interrupt Writing a zero is equivalent to no operation 1 Pending interrupt The interrupt is pending because TIMERn has reached the end of the time interval If the INTEN bit in the CONTROLn is
435. on with divider that can reflect the crystal oscillator the main clock the IRC or the watchdog oscillator Power control Integrated PMU Power Management Unit to minimize power consumption Reduced power modes Sleep mode Deep sleep mode Power down mode and Deep power down mode Wake up from Deep sleep and Power down modes on activity on USART SPI and 12 peripherals Timer controlled self wake up from Deep power down mode Power On Reset POR Brownout detect Unique device serial number for identification Single power supply Operating temperature range 40 C to 105 C except for the DIP8 package which is available for a temperature range of 40 C to 85 C Available as DIP8 XSON16 TSSOP16 SO20 and TSSOP20 package All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 6 of 370 NXP Semiconductors U M1 0601 Chapter 1 LPC81x Introductory information 1 3 Ordering information Table 1 Ordering information Type number Package Name Description Version LPC810M021FN8 DIP8 plastic dual in line package 8 leads 300 mil SOT097 2 LPC811M001JDH16 TSSOP16 plastic thin shrink small outline package 16 leads body width 4 4 mm SOT403 1 LPC812M101JDH16 TSSOP16 plastic thin shrink small outline package 16 leads body width 4 4 mm SOT403 1 LPC812M101JD20 SO20 plastic
436. onding interrupts in the NVIC See Table 3 Connection of interrupt sources to the NVIC Table 45 Start logic 0 pin wake up enable register 0 STARTERPO address 0x4004 8204 bit description Bit Symbol Value Description Reset value 0 PINTO GPIO pin interrupt 0 wake up 0 0 Disabled 1 Enabled 1 PINT1 GPIO pin interrupt 1 wake up 0 0 Disabled 1 Enabled 2 PINT2 GPIO pin interrupt 2 wake up 0 0 Disabled 1 Enabled 3 GPIO interrupt 3 wake up 0 0 Disabled 1 Enabled 4 PINT4 GPIO pin interrupt 4 wake up 0 0 Disabled 1 Enabled 5 PINT5 GPIO pin interrupt 5 wake up 0 0 Disabled 1 Enabled 6 PINT6 GPIO pin interrupt 6 wake up 0 0 Disabled 1 Enabled 7 PINT7 GPIO pin interrupt 7 wake up 0 0 Disabled 1 Enabled 31 8 Reserved UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 44 of 370 NXP Semiconductors U M1 0601 Chapter 4 LPC81x System configuration SYSCON 4 6 29 Start logic 1 interrupt wake up enable register This register selects which interrupts wake the LPC81x from deep sleep and power down modes Remark Also enable the corresponding interrupts in the NVIC See Table 3 Connection of interrupt sources to the NVIC Table 46 Start logic 1 interrupt wake up enable register STARTERP1 address 0x4004 8214 bit description Bit Symbol Value Description Reset value
437. onditions for each bit slice that cause that bit slice to contribute to a pattern match The seven LSBs of this register specify which bit slices are the end points of product terms in the boolean expression i e where OR terms are to be inserted in the expression Two types of edge detection on each input are possible All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 111 of 370 NXP Semiconductors U M1 0601 Chapter 8 LPC81x Pin interrupts pattern match engine Sticky A rising edge a falling edge or a rising or falling edge that is detected at any time after the edge detection mechanism has been cleared The input qualifies as detected the detect logic output remains HIGH until the pattern match engine detect logic is cleared again Non sticky Every time an edge rising or falling is detected the detect logic output for this pin goes HIGH This bit is cleared after one clock cycle and the edge detect logic can detect another edge Remark To clear the pattern match engine detect logic write any value to either the PMCFG register or the PMSRC register or disable the pattern match feature by clearing both the SEL PMATCH and ENA RXEV bits in the PMCTRL register to zeros This will erase all edge detect history To select whether a slice marks the final component in a minterm of the boolean expression write a
438. onnects and enables the system PLL and configures the PLL multiplier and divider values The PLL accepts an input frequency from 10 MHz to 25 MHz from various clock sources The input frequency is multiplied to a higher frequency and then divided down to provide the actual clock used by the CPU peripherals and memories The PLL can produce a clock up to the maximum allowed for the CPU Remark The divider values for P and M must be selected so that the PLL output clock frequency FCLKOUT is lower than 100 MHz Table 20 System PLL control register SYSPLLCTRL address 0x4004 8008 bit description Bit Symbol Value Description Reset value 4 0 MSEL Feedback divider value The division value M is the 0 programmed MSEL value 1 00000 Division ratio M 1 Division ratio M 32 6 5 PSEL Post divider ratio P The division ratio is 2 x P 0 0x0 P 1 0 1 2 0 2 4 0x3 P 8 317 Reserved Do not write ones to reserved bits System PLL status register This register is a Read only register and supplies the PLL lock status see Section 4 7 4 1 Table 21 System PLL status register SYSPLLSTAT address 0x4004 800C bit description Bit Symbol Value Description Reset value 0 LOCK PLL lock status 0 0 PLL not locked 1 PLL locked 31 1 Reserved System oscillator control register This register configures the frequency range for the system oscillator The system oscillator itself is powered on or off in the P
439. ons The following exceptions apply For full I2C bus compatibility assign the I2C functions to the open drain pins PIOO 11 PIOO 10 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 333 of 370 NXP Semiconductors U M1 0601 Chapter 27 LPC81x Packages and pin description Do not assign more than one output to any pin However more than one input can be assigned to a pin Once any function is assigned to a pin the pin s GPIO functionality is disabled Pin PIOO_4 triggers a wake up from Deep power down mode If you need to wake up from Deep power down mode via an external pin do not assign any movable function to this pin The JTAG functions TDO TDI TMS and TRST are selected on pins PIOO 0 to PIOO 4 by hardware when the part is in boundary scan mode Table 305 Pin description table fixed pins Type Reset Description Symbol gt state O eo 2 lt do v amp SO o o9 5 E A PIOO_0 ACMP_11 19 16 8 BIIO 0 General purpose digital input output port 0 pin 0 TDO In ISP mode this is the USARTO receive pin UO RXD In boundary scan mode TDO Test Data Out s ACMP 11 Analog comparator input 1 PIOO 1 ACMP 12 12 9 5 B IO PIOO 1 General purpose digital input output pin CLKIN TDI In boundary scan mode TDI Test Data In
440. or equal to the 23 4 1 2 2 300 expected 304 23 4 1 3 Param3 system PLL lock time out 301 23 5 1 6 System clock approximately equal to the expected 23 4 2 Set POW iia cca ke ee gos 301 value _ 305 23 4 2 1 main clock 303 23 5 2 Power control 305 23 4 2 2 1 303 23 5 2 1 Invalid frequency device maximum clock rate 23 4 8 3 Param2 system clock 303 exceeded 305 23 5 Functional description 303 23 522 An applicable power setup 305 23 5 1 Clock 303 Chapter 24 LPC81x I2C bus ROM API 24 1 How to read this chapter 306 24 4 15 12 Set Bit 313 24 2 306 24 4 16 12C Get Firmware Version 314 24 3 General 306 Ec 2d 244 API description 307 24419 NECEM 314 2441 ISR handler s 309 24420 12 315 suum 12C Master Transmit 309 244 21 12 ROM driver variables 315 2449 Master Receive Polling 310 24421 2 815 24 4 4 I2C Ma
441. or example when compensating for a settling time and thus no CPU activity is required For longer wait times use the one shot interrupt mode which allows other enabled interrupts to be serviced Remark Because the MRT resides on the APB the total amount of wait cycles inserted in bus stall mode 3 cycles have to be added to IVALUE to account for the AHB to APB bridge 11 6 Register description UM10601 The reset values shown in Table 148 are POR reset values All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 166 of 370 NXP Semiconductors U M1 0601 Chapter 11 LPC81x Multi Rate Timer MRT Table 148 Register overview MRT base address 0x4000 4000 Name Access Address Description Reset value Reference offset INTVALO R W 0x0 MRTO Time interval value register This value is 0 Table 149 loaded into the TIMERO register TIMERO R 0 4 Timer register This register reads the value Ox7FFFFFFF Table 150 of the down counter CTRLO R W 0x8 MRTO Control register This register controls the 0 Table 151 MRTO modes STATO R W OxC MRTO Status register 0 Table 152 INTVAL1 R W 0x10 Time interval value register This value is 0 Table 149 loaded into the TIMER register TIMER1 R W 0x14 Timer register This register reads the value Ox7FFF FFFF Table 150 of the down counter CTRL1 R W 0x18 MRT1
442. or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from competent authorities 30 3 3 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners I C bus logo is a trademark of NXP B V NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 354 of 370 NXP Semiconductors UM10601 Chapter 30 Supplementary information 30 4 Tables Table 1 Ordering information 7 description ics Rm een x 35 Table 2 Ordering 7 Table 29 System clock divider register SYSAHBCLKDIV Table 3 Connection of interrupt sources to the NVIC 12 address 0x4004 8078 bit description 36 Table 4 Register overview NVIC base address 0xE000 Table 30 System clock control register E000 erus mex yd x nee ees 15 SYSAHBCLKCTRL address 0x4004 8080 bit Table 5 Interrupt Set Enable Register 0 register ISERO description 36 address 0xE000 E100 bit description 16 Table 31 USART clock divider register UARTCLKDIV Table 6 Interrupt clear enable register 0 ICERO address address 0x4004 8094 bit description
443. or written individually or in a single 32 bit read or write operation In this case the L and H registers count independently under the control of the other registers Writing to the COUNT L COUNT H or unified register is only allowed when the corresponding counter is halted HALT bits are set to 1 in the CTRL register Software can read the counter registers at any time All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 143 of 370 NXP Semiconductors U M1 0601 10 6 8 Chapter 10 LPC81x SCTimer PWM SCT Table 127 SCT counter register COUNT address 0x5000 4040 bit description Bit Symbol Description Reset value 15 0 CTR_L When UNIFY 0 read or write the 16 bit L counter value When 0 UNIFY 1 read or write the lower 16 bits of the 32 bit unified counter 31 16 When UNIFY 0 read or write the 16 bit H counter value When 0 UNIFY 1 read or write the upper 16 bits of the 32 bit unified counter SCT state register If UNIFY 1 in the CONFIG register only the _L bits are used If UNIFY 0 in the CONFIG register this register can be written to as two registers STATE_L and STATE_H Both the L and H registers can be read or written individually or in a single 32 bit read or write operation Software can read the state associated with a counter at any time Writing to the STATE_L STATE_H or u
444. ory map addresses 0x0000 0000 to 0x0000 0200 Table 18 System memory remap register SYSMEMREMAP address 0x4004 8000 bit description Bit Symbol Value Description Reset value 1 0 MAP System memory remap Value 0x3 is reserved 0x2 0x0 Boot Loader Mode Interrupt vectors are re mapped to Boot ROM 0 1 User RAM Mode Interrupt vectors re mapped to Static RAM 0 2 User Flash Mode Interrupt vectors are not re mapped and reside in Flash 31 22 Reserved 4 6 2 Peripheral reset control register The PRESETCTRL register allows software to reset specific peripherals A zero in any assigned bit in this register resets the specified peripheral A 1 clears the reset and allows the peripheral to operate Table 19 Peripheral reset control register PRESETCTRL address 0x4004 8004 bit description Bit Symbol Value Description Reset value 0 SPIO_RST_N SPIO reset control 1 0 Assert the SPIO reset 1 Clear the SPIO reset 1 SPI1_RST_N SPI1 reset control 1 0 Assert the SPI1 reset 1 Clear the SPI1 reset UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 29 of 370 NXP Semiconductors U M1 0601 Chapter 4 LPC81x System configuration SYSCON Table 19 Peripheral reset control register PRESETCTRL address 0x4004 8004 bit description Bit Symbol Value Description Reset value 2 UARTFRG_RS
445. ot a true open drain mode 12 11 5 MODE Digital filter sample mode 0 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than one filter clock are rejected 0 2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 1543 CLK_DIV Select peripheral clock divider for input filter sampling clock 0 Value 0 7 is reserved 0 0 IOCONCLKDIVO 0 1 IOCONCLKDIV1 0 2 IOCONCLKDIV2 0x3 IOCONCLKDIV3 0x4 IOCONCLKDIVA 0x5 IOCONCLKDIV5 0 6 IOCONCLKDIVE6 31 16 Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 85 of 370 NXP Semiconductors UM10601 6 5 15 PIOO 7 register Chapter 6 LPC81x I O configuration IOCON Table 76 PIOO_7 register PIOO 7 address 0x4004 403C bit description Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor 0b10 control 0x0 Inactive no pull down pull up resistor enabled 0 1 Pull down resistor enabled 0 2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 5 Reserved 0b001 1
446. ould be NA written 11 SYNCEN Selects synchronous or asynchronous operation 0 0 Asynchronous mode is selected Synchronous mode is selected 12 CLKPOL Selects the clock polarity and sampling edge of received 0 data in synchronous mode 0 Falling edge Un RXD is sampled on the falling edge of SCLK 1 Rising edge Un RXD is sampled on the rising edge of SCLK 13 Reserved Read value is undefined only zero should be NA written 14 SYNCMST Synchronous mode Master select 0 0 Slave When synchronous mode is enabled the USART is a slave 1 Master When synchronous mode is enabled the USART is a master 15 LOOP Selects data loopback mode 0 0 Normal operation Loopback mode This provides a mechanism to perform diagnostic loopback testing for USART data Serial data from the transmitter Un TXD is connected internally to serial input of the receive Un RXD Un TXD and Un RTS activity will also appear on external pins if these functions are configured to appear on device pins The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN 31 16 Reserved Read value is undefined only zero should be NA written 15 6 2 USART Control register The CTL register controls aspects of USART operation that are more likely to change during operation UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2
447. ould be greater than or equal to start sector number Status code CMD SUCCESS BUSY INVALID SECTOR Result None Description This command must be executed before executing Copy RAM to flash or Erase Sector s command Successful execution of the Copy RAM to flash or Erase Sector s command causes relevant sectors to be protected again The boot sector can not be prepared by this command To prepare a single sector use the same Start and End sector numbers 22 5 2 2 Copy RAM to flash IAP See Section 22 5 1 4 for limitations on the write to flash process UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 290 of 370 NXP Semiconductors UM10601 Chapter 22 LPC81x Flash ISP and IAP programming Table 258 IAP Copy RAM to flash command Command Input Status code Result Description Copy RAM to flash Command code 51 decimal ParamO DST Destination flash address where data bytes are to be written This address should be a 64 byte boundary Param1 SRC Source RAM address from which data bytes are to be read This address should be a word boundary Param2 Number of bytes to be written Should be 64 128 256 512 1024 Param3 System Clock Frequency CCLK in kHz CMD SUCCESS SRC ADDR ERROR Address not a word boundary DST ADDR ERROR Address not on correct boundary
448. p i2c base addr start of ram ErrorCode t i2c set bitrate I2C HANDLE P in hz bitrate in bps uint32 ti2c get firmware version void I2C MODE T i2c get status I2C HANDLE ErrorCode t i2c set timeout I2C HANDLE T h i2c uint32 t timeout Description 12C Slave Receive Polling I2C Slave Transmit Polling I2C Slave Receive Interrupt I2C Slave Transmit Interrupt 12 Set Slave Address I2C Get Memory Size I2C Setup I2C Set Bit Rate I2C Get Firmware Version I2C Get Status 12 time out value Reference Table 280 Table 281 Table 282 Table 283 Table 284 Table 285 Table 286 Table 287 Table 288 Table 289 Table 290 The following structure has to be defined to use the 12C typedef struct I2CD_API index of all the i2c driver functions I2C HANDLE T h_i2c ISR interrupt service request aster_transmit_poll 12C_HANDLE_T h i2c I2C PARAM ptp 12C RESULT ptr receive poll I2C HANDLE T h i2c I2C PARAM ptp I2C RESULT ptr tx rx poll I2C HANDLE T h i2c 12C_PARAM ptp 12C RESULT ptr transmit intr I2C HANDLE T h i2c I2C PARAM ptp receive intr I2C HANDLE T h i2c I2C PARAM ptp aster tx rx intr I2C HANDLE T h i2c I2C PARAM ptp I2C RESULT 2c slave receive poll I2C HANDLE T h i2c I2C PARAM ptp I2C RESULT 2c slave transmit poll I2C HANDLE T h i2c I2C PARAM ptp
449. p mode Enable the USART interrupt in the INTENSET register Table 176 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 189 of 370 NXP Semiconductors UM10601 Chapter 15 LPC81x USARTO 1 2 15 3 2 2 Wake up from Deep sleep or Power down mode Configure the USART in synchronous slave mode See Table 173 You must connect the SCLK function to a pin and connect the pin to the master Enable the USART interrupt in the STARTERP1 register See Table 46 Start logic 1 interrupt wake up enable register STARTERP1 address 0x4004 8214 bit description Enable the USART interrupt in the NVIC In the PDAWAKE register configure all peripherals that need to be running when the part wakes up The USART wakes up the part from Deep sleep or Power down mode on all events that cause an interrupt and areal so enabled in the INTENSET register Typical wake up events are A start bit has been received The RXDAT buffer has received a byte Data is ready to be transmitted in the TXDAT buffer and a serial clock from the master has been received A change in the state of the CTS pin if the CTS function is connected Remark By enabling or disabling the interrupt in the INTENSET register Table 176 you can customize when the wake up occurs in the USART receive transmit protocol 15 4 Pin description The USA
450. peater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 5 Reserved 0b001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled Remark This is not a true open drain mode 12 11 5 MODE Digital filter sample mode 0 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than one filter clock are rejected 0 2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 1543 CLK_DIV Select peripheral clock divider for input filter sampling clock 0 Value 0 7 is reserved 0 0 IOCONCLKDIVO 0 1 IOCONCLKDIV1 0 2 IOCONCLKDIV2 0x3 IOCONCLKDIV3 0x4 IOCONCLKDIVA 0x5 IOCONCLKDIV5 0 6 IOCONCLKDIVE6 31 16 Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 89 of 370 UM10601 Chapter 7 LPC81x GPIO port Rev 1 6 2 April 2014 User manual 7 1 How to read this chapter 7 2 Features All GPIO registers refer to 32 pins per port Depending on the package type not all pins are available and the corresponding bits in the GPIO registers are reserved see Table 80 Table 80 GPIO pins available Package GPIO Port 0
451. pective reload registers Software can write to set or clear this bit at any time This bit applies to both the higher and lower registers when the UNIFY bit is set 8 NORELOAD A 1 in this bit prevents the higher match registers from being reloaded from their 0 respective reload registers Software can write to set or clear this bit at any time This bit is not used when the UNIFY bit is set UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 139 of 370 NXP Semiconductors U M1 0601 Chapter 10 LPC81x SCTimer PWM SCT Table 121 SCT configuration register CONFIG address 0x5000 4000 bit description continued Bit Symbol 16 9 INSYNC 17 AUTOLIMIT_L 18 AUTOLIMIT_H 31 19 Value Description Reset value Synchronization for input N bit 9 input 0 bit 10 input 1 bit 16 input 7 1 A 1 one of these bits subjects the corresponding input to synchronization to the SCT clock before it is used to create an event If an input is synchronous to the SCT clock keep its bit O for faster response When the CLKMODE field is 1x the bit in this field corresponding to the input selected by the CKSEL field is not used A in this bit causes a match on match register 0 to be treated as a de facto LIMIT condition without the need to define an associated event As with any LIMIT event this automatic
452. ppens The pending status is cleared and the I2C bus is busy The l2C master sends the data bits to the slave address 6 Wait for the pending status to be set MSTPENDING 1 by polling the STAT register 7 Write the slave address with the RW bit set to 1 to the Master data register MSTDAT See Table 196 Re start the transmission setting the MSTSTART bit to 1 in the Master control register See Table 194 The following happens The pending status is cleared and the I2C bus is busy The 12C master sends the start bit and address with the RW bit to the slave All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 208 of 370 NXP Semiconductors U M1 0601 Chapter 16 LPC81x I2C bus interface The slave sends 8 bit of data 9 Wait for the pending status to be set MSTPENDING 1 by polling the STAT register 10 Read the first byte of data from the MSTDAT register 11 Wait for the pending status to be set MSTPENDING 1 by polling the STAT register 12 Repeat reading data from the slave by setting the MSTCONTINUE bit to 1 in the Master control register 13 Wait for the pending status to be set MSTPENDING 1 by polling the STAT register 14 Read the second byte of data from the MSTDAT register 15 Stop the transmission by setting the MSTSTOP bit to 1 in the Master control register See Table 194
453. pt register block in the SYSAHBCLKCTRL register Table 30 bit 6 Each bit slice of the pattern match engine is assigned to one interrupt in the NVIC interrupts 24 to 31 for slices O to 7 The combined interrupt from all slices or slice combinations can be connected to the ARM RXEV request and to pin function GPIO INT BMAT through the switch matrix movable function register PINASSIGN8 Table 117 8 3 1 Configure pins as pin interrupts or as inputs to the pattern match engine Follow these steps to configure pins as pin interrupts 1 Determine the pins that serve as pin interrupts on the LPC81x package See the data sheet for determining the GPIO port pin number associated with the package pin 2 For each pin interrupt program the GPIO port pin number into one of the eight PINTSEL registers in the SYSCON block Remark The port pin number serves to identify the pin to the PINTSEL register Any function including GPIO can be assigned to this pin through the switch matrix 3 Enable each pin interrupt in the NVIC Once the pin interrupts or pattern match inputs are configured you can set up the pin interrupt detection levels or the pattern match boolean expression See Section 4 6 27 Pin interrupt select registers the SYSCON block for the PINTSEL registers 8 4 Pin description The inputs to the pin interrupt and pattern match engine are determined by the pin interrupt select registers in the SYSCON b
454. pter 13 2 Features The self wake up timer is available on all LPC81x parts 32 bit loadable down counter Counter starts automatically when a count value is loaded Time out generates an interrupt wake up request The WKT resides in a separate always on power domain The WKT supports two clock sources One clock source originates from the always on power domain The WKT can be used for waking up the part from any low power mode including Deep power down mode or for general purpose timing 13 3 Basic configuration In the SYSAHBCLKCTRL register set bit 9 Table 30 to enable the clock to the register interface Clear the WKT reset using the PRESETCTRL register Table 19 The WKT interrupt is connected to interrupt 15 in the NVIC Enable the low power oscillator in the PMU Table 58 Enable the IRC and IRC output in the PDRUNCFG register Table 49 See Section 5 7 1 to enable the various power down modes 13 4 Pin description The WKT has no configurable pins 13 5 General description UM10601 13 5 1 The self wake up timer is a 32 bit loadable down counter Writing any non zero value to this timer automatically enables the counter and launches a count down sequence When the counter is being used as a wake up timer this write can occur just prior to entering a reduced power mode When a starting count value is loaded the self wake up timer automatically turns on counts from the pre loaded val
455. puts INn are shown synchronized to the system clock for simplicity Fig 11 Pattern match engine examples Windowed non sticky edge detect evaluates as true UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 119 of 370 NXP Semiconductors UM10601 Chapter 8 LPC81x Pin interrupts pattern match engine SRCO 0 CFGO 0x4 PROD ENPTSO 0x0 high level detection slice 1 IN1ev NVIC pin interrupt 1 and GPIO INT BMAT output SRC1 1 CFG1 0 7 PROD_ENPTS1 0x1 non sticky edge detection 2 INO IN1 ev no pin interrupt raised IN1 does not change while INO level is HIGH Figure shows pattern match functionality only and accurate timing is not implied Inputs INn are shown synchronized to the system clock for simplicity Fig 12 Pattern match engine examples Windowed non sticky edge detect evaluates as false UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 120 of 370 UM10601 Chapter 9 LPC81x Switch matrix Rev 1 6 2 April 2014 User manual 9 1 How to read this chapter 9 2 Features The switch matrix is identical for all LPC81x parts The USART2 and SPI1 functions are only available on parts LPC812M101JDH20 and LPC81
456. quired Interrupt capability 18 3 Basic configuration UM10601 Configure the analog comparator using the following registers In the SYSAHBCLKCTRL register set bit 19 Table 30 to enable the clock to the register interface You can enable or disable the power to the analog comparator through the PDRUNCFG register Table 49 Clear the analog comparator peripheral reset using the PRESETCTRL register Table 19 The analog comparator interrupt is connected to interrupt 11 in the NVIC Configure the analog comparator pin functions through the switch matrix See Section 18 4 18 3 1 Connect the comparator output to the SCT You can use the comparator output function ACMP_O to start or stop the SCT or more generally create an SCT event To create an SCT event connect AMP O as follows T 2 Using the switch matrix connect ACMP_O to a pin See Table 216 Using the switch matrix connect any of the SCT input functions to the same pin See Table 119 The selected SCT input can now monitor the ACMP O function All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 254 of 370 NXP Semiconductors U M1 0601 Chapter 18 LPC81x Analog comparator 18 4 Pin description The analog comparator reference voltage the inputs and the output are assigned to external pins through the switch matrix You can assign t
457. r INPUT address 0x5000 4048 bit 145 Table 130 SCT match capture registers mode register REGMODE address 0x5000 404C bit description 22i beanie eee ee eet 146 Table 131 SCT output register OUTPUT address 0x5000 4050 bit 146 Table 132 SCT bidirectional output control register OUTPUTDIRCTRL address 0x5000 4054 bit description 146 UM10601 All information provided in this document is subject to legal disclaimers Chapter 30 Supplementary information Table 133 SCT conflict resolution register RES address 0x5000 4058 bit description 147 Table 134 SCT flag enable register EVEN address 0x5000 bit description 148 Table 135 SCT event flag register EVFLAG address 0x5000 40F4 bit description 148 Table 136 SCT conflict enable register CONEN address 0x5000 40F8 bit description 149 Table 137 SCT conflict flag register CONFLAG address 0x5000 40FC bit description 149 Table 138 SCT match registers 0 to 4 MATCH 0 4 address 0x5000 4100 to 0x5000 4110 MATCH4 bit description REGMODEn lo m 150 Table 139 SCT capture registers 0 to 4 CAP 0 4 address 0x5000 4100 CAPO to 0x5000 4110 CAP4 bit description REGMODEn bit 1 150 Table 140 SCT match reload registers 0 to 4 MATCHREL 0
458. r 0x0000 0000 Table 142 EV2_CTRL R W 0x314 SCT event 2 control register 0x0000 0000 Table 143 EV3_STATE R W 0x318 SCT event 3 state register 0x0000 0000 Table 142 EV3 CTRL R W Ox31C SCT event 3 control register 0x0000 0000 Table 143 EV4 STATE R W 0x320 SCT event 4 state register 0x0000 0000 Table 142 EV4 CTRL R W 0x324 SCT event 4 control register 0x0000 0000 Table 143 EV5 STATE R W 0x328 SCT event 5 state register 0x0000 0000 Table 142 EV5 CTRL R W Ox32C event 5 control register 0x0000 0000 Table 143 OUTO SET R W 0x500 SCT output 0 set register 0x0000 0000 Table 144 OUTO CLR R W 0x504 SCT output 0 clear register 0x0000 0000 Table 145 OUT1_SET R W 0x508 SCT output 1 set register 0x0000 0000 Table 144 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 138 of 370 NXP Semiconductors UM10601 Table 120 Register overview State Configurable Timer base address 0x5000 4000 continued Chapter 10 LPC81x SCTimer PWM SCT Name OUT1_CLR OUT2 SET OUT2 CLR OUT3 SET OUT3 CLR Access Address Description Reset value Reference offset R W Ox50C SCT output 1 clear register 0x0000 0000 Table 145 R W 0x510 SCT output 2 set register 0x0000 0000 Table 144 R W 0x514 SCT output 2 clear register 0x0000 0000 Table 145 R W 0x518 SCT output 3 set register 0x0000 0000 Table 144 R W 0x51C SCT output 3 clear register 0x0000 0000 Table 145
459. r 122 2 or 122 2 or 122 2 or 122 2 or 122 2 or 121 2 or 122 2 or 121 1 NUI 1 NUI 2 or 12 2 or 121 2 or 12 2 or 121 2 or 12 2 or 121 2 or 12 1 1 NUI 1 NISI 1 NE 3 B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 338 of 370 NXP Semiconductors UM10601 Table 306 Cortex MO instruction summary Chapter 28 LPC81x Appendix Operation Description Assembler Cycles Branch Conditional B cc label 1 or 24 Unconditional B lt label gt 2 With link BL lt label gt 3 With exchange BX Rm 2 With link and exchange BLX Rm 2 Extend Signed halfword to word SXTH Rd Rm 1 Signed byte to word SXTB Rd Rm 1 Unsigned halfword UXTH Rd Rm 1 Unsigned byte UXTB Rd Rm 1 Reverse Bytes in word REV Rd Rm 1 Bytes in both halfwords REV16 Rd Rm 1 Signed bottom half word REVSH Rd Rm 1 State change Supervisor Call SVC lt imm gt 5 Disable interrupts CPSID i 1 Enable interrupts CPSIE i 1 Read special register MRS Rad lt specreg gt 3 Write special register MSR lt specreg gt Rn 3 Breakpoint BKPT lt imm gt 5 Hint Send event SEV 1 Wait for interrupt WFI 216 Wait for event WFE 216 Yield YIELDUI 1 No operation NOP 1 Barriers Instruction synchronization ISB 3 Data memory DMB 3 Data synchronization DSB 3 1 Nisthe number of elements in the list 2 2 cycles if to AHB interface or SCS 1 cycle if to single cycle I O port 3 Nisthe numbe
460. r Ready Transmitter Ready Receiver Idle change in receiver break detect Framing error Parity error Overrun Underrun Delta CTS detect and receiver sample noise detected Loopback mode for testing of data and flow control 15 3 Basic configuration UM10601 Remark The on chip USART API provides software routines to configure and use the USART See Table 293 Configure USART0 1 2 for receiving and transmitting data Inthe SYSAHBCLKCTRL register set bit 14 to 16 Table 30 to enable the clock to the register interfaces All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 187 of 370 NXP Semiconductors U M1 0601 15 3 1 UM10601 Chapter 15 LPC81x USARTO 1 2 e Clear the USARTO0 1 2 peripheral resets using the PRESETCTRL register Table 19 Enable or disable the USARTO 1 2 interrupts in slots 3 to 5 in the NVIC e Configure the USARTO 1 2 pin functions through the switch matrix See Section 15 4 Configure the USART clock and baud rate See Section 15 3 1 Configure the USARTO0 1 2 to wake up the part from low power modes Configure the USART to receive and transmit data in synchronous slave mode See Section 15 3 2 Configure the USART clock and baud rate All three USARTs use a common peripheral clock PCLK and if needed a fractional baud rate generator The peripheral clock and the f
461. r and clocks are shut off to the entire chip with the exception of the WAKEUP pin and the self wake up timer During Deep power down mode the contents of the SRAM and registers are not retained except for a small amount of data which can be stored in the general purpose registers of the PMU block All functional pins are tri stated in Deep power down mode except for the WAKEUP pin In this mode you must pull the RESET pin HIGH externally Remark Setting bit 3 in the PCON register Table 56 prevents the part from entering Deep power down mode Power configuration in Deep power down mode Deep power down mode has no configuration options All clocks the core and all peripherals are powered down Only the WAKEUP pin and the self wake up timer are powered Programming Deep power down mode using the WAKEUP pin The following steps must be performed to enter Deep power down mode when using the WAKEUP pin for waking up Pull the WAKEUP pin externally HIGH Ensure that bit 3 in the PCON register Table 56 is cleared Write Ox3 to the PM bits in the PCON register see Table 56 Store data to be retained in the general purpose registers Section 5 6 2 Write one to the SLEEPDEEP bit in the ARM Cortex M0 SCR register Table 53 Use the ARM WFI instruction o FWD 5 7 7 3 Wake up from Deep power down mode using the WAKEUP pin UM10601 Pulling the WAKEUP pin LOW wakes up the LPC81x from Deep power down and t
462. r controls internal reference voltage input All other bits are reserved All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 255 of 370 NXP Semiconductors U M1 0601 Chapter 18 LPC81x Analog comparator ext VDDCMP Voo LADREF M 9f LADEN amp nACOMP PD VOLTAGE LADDER OUT COMP VP SEL I1 COMPSTAT ACMP 12 VSS VSS VSS internal 0 9V BANDGAP VSS n c to ACMP COMPSA COMP VM SEL EDGESEL ACOMP_RST_N COMPEDGE to INTERRUPT 2 OF 3 SAMPLING EDGECLR or e CONTROL STATUS REGISTER BITS EDGE DETECT ACOMP_RST_N Fig 41 Comparator block diagram 18 5 1 Reference voltages The voltage ladder can use two reference voltages from the VDDCMP or the Vpp pin The voltage ladder selects one of 32 steps between the pin voltage and Vss inclusive The voltage on VDDCMP should not exceed that on Vpp 18 5 2 Settling times After the voltage ladder is powered on it requires stabilization time until comparisons using it are accurate Much shorter settling times apply after the LADSEL value is changed and when either or both voltage sources are changed Software can deal with these factors by repeatedly reading the comparator output until a number of readings yield the same result 18 5 3 Interrupts The interrupt output comes from edge detection circuitry in this
463. r high counter 16 bit Table 123 HALT R W Ox00C SCT halt condition register 0x0000 0000 Table 124 HALT L R W 0x00C SCT halt condition register low counter 16 bit Table 124 HALT_H R W Ox00E SCT halt condition register high counter 16 bit Table 124 STOP R W 0x010 SCT stop condition register 0x0000 0000 Table 125 STOP_L R W 0x010 SCT stop condition register low counter 16 bit Table 125 STOP_H R W 0x012 SCT stop condition register high counter 16 bit Table 125 START R W 0x014 SCT start condition register 0x0000 0000 Table 126 START_L R W 0x014 SCT start condition register low counter 16 bit Table 126 START_H R W 0x016 SCT start condition register high counter 16 bit Table 126 0x018 Reserved 0x03C COUNT R W 0x040 SCT counter register 0x0000 0000 Table 127 COUNT_L R W 0x040 SCT counter register low counter 16 bit Table 127 COUNT_H R W 0x042 SCT counter register high counter 16 bit Table 127 STATE R W 0x044 SCT state register 0x0000 0000 Table 128 STATE_L R W 0x044 SCT state register low counter 16 bit Table 128 STATE_H R W 0x046 SCT state register high counter 16 bit Table 128 INPUT RO 0x048 SCT input register 0x0000 0000 Table 129 REGMODE R W 0x04C SCT match capture registers mode register 0x0000 0000 Table 130 REGMODE_L R W 0x04C SCT match capture registers mode register low Table 130 counter 16 bit REGMODE_H R W 0x04E SCT match capture registers mode register high Table 130 counter 16 bit OUTPUT R W 0x050 SCT output
464. r in the following way in the EVn_CTRL registers up to 6 one register per event Select whether the event occurs on an input or output changing on an input or output level a match condition of the counter or a combination of match and input output conditions in field COMBMODE For a match condition Select the match register that contains the match condition for the event to occur Enter the number of the selected match register in field MATCHSEL If using L and H counters define whether the event occurs on matching the L or the H counter in field HEVENT For an SCT input or output level or transition Select the input number or the output number that is associated with this event in fields IOSEL and OUTSEL Define how the selected input or output triggers the event edge or level sensitive in field IOCOND 2 Define what the effect of each event is on the SCT outputs in the OUTn_SET or OUTn_CLR registers up to 4 outputs one register per output For each SCT output select which events set or clear this output More than one event can change the output and each event can change multiple outputs 3 Define how each event affects the counter Set the corresponding event bit in the LIMIT register for the event to set an upper limit for the counter When a limit event occurs in unidirectional mode the counter is cleared to zero and begins counting up on the next clock edge When a limit event occurs in bidirectional m
465. r mode Send data and continue or send a Stop or Address plus Write was previously sent and Acknowledged by Repeated Start slave 3 Slave NACKed address Send a Stop or Repeated Start Slave NACKed transmitted data Send a Stop or Repeated Start Table 188 Slave function state codes SLVSTATE SlvState Description Actions 0 Address plus R W received At least one of the 4 Software can further check the address if needed for slave addresses has been matched by hardware instance if a subset of addresses qualified by SLVQUALO is to be used Software can ACK or NACK the address by writing 1 to either SLVCONTINUE or SLVNACK Also see Section 16 7 3 regarding 10 bit addressing 1 Received data is available Slave Receiver mode Read data reply with an ACK or a NACK Data can be transmitted Slave Transmitter mode Send data Reserved UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 218 of 370 NXP Semiconductors UM10601 UM10601 Chapter 16 LPC81x I2C bus interface 16 6 3 Interrupt Enable Set and read register The INTENSET register controls which 12C status flags generate interrupts Writing a 1 to a bit position in this register enables an interrupt in the corresponding position in the STAT register if an interrupt is supported there Reading INTENSET indicates which interrupts are currently enabled
466. r mode to Slave mode or the reverse an unusual case the SPI should be disabled and re enabled with the new configuration Table 204 SPI Configuration register CFG addresses 0x4005 8000 SPIO 0x4005 C000 SPI1 bit description Bit Symbol Value Description Reset value 0 ENABLE SPI enable 0 0 Disabled The SPI is disabled and the internal state machine and counters are reset 1 Enabled The SPI is enabled for operation Reserved Read value is undefined only zero should be written NA 2 MASTER Master mode select 0 0 Slave mode The SPI will operate in slave mode SCK MOSI and the SSEL signals are inputs MISO is an output 1 Master mode The SPI will operate in master mode SCK MOSI and the SSEL signals are outputs MISO is an input 3 LSBF LSB First mode enable 0 0 Standard Data is transmitted and received in standard MSB first order 1 Reverse Data is transmitted and received in reverse order LSB first 4 CPHA Clock Phase select 0 0 Change The SPI captures serial data on the first clock transition of the transfer when the clock changes away from the rest state Data is changed on the following edge 1 Capture The SPI changes serial data on the first clock transition of the transfer when the clock changes away from the rest state Data is captured on the following edge 5 CPOL Clock Polarity select 0 0 Low The rest state of the clock between transfers is low 1 High The rest state of the clock between transf
467. r of elements in the list including PC or LR 4 2iftaken 1 if not taken 5 Cycle count depends on core and debug configuration 6 Excludes time spend waiting for an interrupt or event Executes as NOP UM10601 All information provided in this document is subject to legal disclaimers Rev 1 6 2 April 2014 NXP B V 2014 All rights reserved 339 of 370 User manual UM10601 Chapter 29 LPC81x Code examples Rev 1 6 2 April 2014 29 1 How to read this chapter User manual This chapter contains code examples to help understand how to use the registers of various peripheral blocks when writing software drivers For a comprehensive description of each peripheral and register interface see the respective chapter Remark The code listings are for illustrative purposes only and are not intended to be application ready functions 29 2 Code examples I2C 29 2 1 Definitions Table 307 12C Code example 12C defines defi defi defi defi defi defi defi defi defi defi defi defi defi defi defi defi defi defi defi ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne 2C_CFG_MSTEN 0 1 LVEN 0x2 51 TSTATE 0 TST_IDLE 0x0 TST_RX 0x2 TST_TX 0x4 TST_NACK_ADDR 0x6 2C_CFG_S 2C_STAT 2C_STAT 2C_STAT 2C_STAT 2C_STAT 2C_STAT c2 C20 CO CO PENDING 0 1
468. r routine with SYSAHBCLKDIV 1 System clock divider register see Table 29 and Figure 47 set power returns a result code that reports whether the power setting was successfully changed or not All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 301 of 370 NXP Semiconductors UM10601 Chapter 23 LPC81x Power profile ROM driver Fig 48 Power profiles usage using power profiles and changing system clock current_clock new clock new mode use power routine call to change mode to DEFAULT use either clocking routine call or custom code to change system clock from current_clock to new_clock use power routine call to change mode to new_mode end Table 271 set_power routine Routine Input Result set_power ParamO0 main clock in MHz Param1 mode DEFAULT CPU PERFORMANCE PWR EFFICIENCY LOW CURRENT 2 system clock in MHz Result0 CMD SUCCESS PWR INVALID FREQ PWR INVALID MODE The following definitions are needed for set power routine calls set power mode options define define define define PWR_DEFAULT 0 PWR_CPU_PERFORMANCE 1 PWR_EFFICIENCY 2 PWR_LOW_CURRENT 3 set power result0 options define define define UM10601
469. r state with SLEEPDEEP 1 to either deep sleep or power down or to enter the Deep power down mode use the PCON register Table 56 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 55 of 370 NXP Semiconductors UM10601 Chapter 5 LPC81x Reduced power modes and Power Management Table 53 System control register SCR address 0xE000 ED10 bit description Bit Symbol 0 SLEEPONEXIT 2 SLEEPDEEP 3 7 SEVONPEND 31 5 Description Reset value Reserved 0 Indicates sleep on exit when returning from Handler mode to 0 Thread mode 0 do not sleep when returning to Thread mode 1 enter sleep or deep sleep on return from an ISR to Thread mode Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application Controls whether the processor uses sleep or deep sleep as 0 its low power mode 0 sleep 1 deep sleep Reserved Send Event on Pending bit 0 only enabled interrupts or events can wake up the processor disabled interrupts are excluded 1 enabled events and all interrupts including disabled interrupts can wake up the processor When an event or interrupt enters pending state the event signal wakes up the processor from WFE If the processor is not waiting for an event the event is registered and affects the next WFE The proc
470. ractional divider for the baud rate calculation are set up in the SYSCON block as follows see Figure 29 1 Configure the UART clock by writing a value UARTCLKDIV gt 0 in the USART peripheral clock divider register This is the divided main clock common to all USARTS Section 4 6 14 USART clock divider register If a fractional value is needed to obtain a particular baud rate program the fractional divider The fractional divider value is the fraction of MULT DIV The MULT value is programmed in the UARTFRGMULT register and the DIV value is programmedwith the fixed value of 256 the UARTFRGDIV register in the SYSCON block U_PCLK UARTCLKDIV 1 MULT DIV The following rules apply for MULT and DIV Always set DIV to 256 by programming the UARTFRGDIV register with the value of OxFF Program any value between 0 and 255 in the UARTFRGMULT register Section 4 6 19 USART fractional generator multiplier value register Section 4 6 18 USART fractional generator divider value register In asynchronous mode Configure the baud rate divider BRGVAL in the USARTn BRG register The baud rate divider divides the common USART peripheral clock by a factor of 16 multiplied by the baud rate value to provide the baud rate U_PCLK 16 x BRGVAL Section 15 6 9 USART Baud Rate Generator register 4 In synchronous mode The serial clock is Un SCLK PCLK BRGVAL All information provided in this document
471. ram unsigned int status_result command param unsigned int x status result unsigned int 0 Define pointer to function type which takes two parameters and returns void Note the IAP returns the result with the base address of the table residing in R1 typedef void IAP unsigned int unsigned int IAP iap entry Setting the function pointer iap_entry IAP IAP LOCATION To call the IAP use the following statement iap entry command param status result As per the ARM specification The ARM Thumb Procedure Call Standard SWS ESPC 0002 A 05 up to 4 parameters can be passed in the rO r1 r2 and r3 registers respectively Additional parameters are passed on the stack Up to 4 parameters can be returned in the rO r1 r2 and r3 registers respectively Additional parameters are returned indirectly via memory Some of the IAP calls require more than 4 parameters If the ARM suggested scheme is used for the parameter passing returning then it might create problems due to difference in the C compiler implementation from different vendors The suggested parameter passing scheme reduces such risk The flash memory is not accessible during a write or erase operation IAP commands which results in a flash write erase operation use 32 bytes of space in the top portion of the on chip RAM for execution The user program should not be use this space if IAP flash programming is permitted in the application Table 25
472. ration where applicable 6 COUNT ERROR Byte count is not multiple of 4 or is not a permitted value UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 287 of 370 NXP Semiconductors U M1 0601 UM10601 22 5 2 Chapter 22 LPC81x Flash ISP and IAP programming Table 255 UART ISP Return Codes Summary Return Mnemonic Description Code 7 INVALID SECTOR Sector number is invalid or end sector number is greater than start sector number SECTOR NOT BLANK Sector is not blank SECTOR NOT PREPARED FOR Command to prepare sector for write operation WRITE OPERATION was not executed 10 COMPARE ERROR Source and destination data not equal 11 BUSY Flash programming hardware interface is busy 12 PARAM ERROR Insufficient number of parameters or invalid parameter 13 ADDR ERROR Address is not on word boundary 14 ADDR NOT MAPPED Address is not mapped in the memory map Count value is taken in to consideration where applicable 15 CMD LOCKED Command is locked 16 INVALID CODE Unlock code is invalid 17 INVALID BAUD RATE Invalid baud rate setting 18 INVALID STOP BIT Invalid stop bit setting 19 CODE READ PROTECTION Code read protection enabled ENABLED IAP commands For in application programming the IAP routine should be called with a word pointer in register rO pointing to memory RAM containing command code and parameters Res
473. re start address register 0 Table 227 FMSSTOP R W 0x024 Signature stop address register 0 Table 228 FMSWO R 0x02C Signature word Table 229 Flash configuration register Access to the flash memory can be configured independently of the system frequency by writing to the FLASHCFG register Remark When using the Power API do not change the waitstates in efficiency low current or performance modes Table 226 Flash configuration register FLASHCFG address 0x4004 0010 bit description Bit Symbol Value Description Reset value 1 0 FLASHTIM Flash memory access time FLASHTIM 1 is equal to the 0 1 number of system clocks used for flash access 0x0 1 system clock flash access time 0 1 2 system clocks flash access time 0 2 Reserved 0x3 Reserved 31 2 Reserved User software must not change the value of these bits Bits 31 2 must be written back exactly as read UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 265 of 370 NXP Semiconductors U M1 0601 20 4 2 20 4 3 20 4 4 Chapter 20 LPC81x Flash controller Flash signature start address register Table 227 Flash Module Signature Start register FMSSTART 0x4004 0020 bit description Bit Symbol Description Reset value 16 0 START Signature generation start address corresponds to AHB byte 0 address bits 20 4 31 17 Reserved user so
474. re stop address register FMSSTOP The start and stop addresses must be aligned to 32 bit boundaries Signature generation is started by setting the STRTBIST bit in the FMSSTOP register Setting the STRTBIST bit is typically combined with the signature stop address in a single write Table 227 and Table 228 show the bit assignments in the FMSSTART and FMSSTOP registers respectively Signature generation A signature can be generated for any part of the flash contents The address range to be used for signature generation is defined by writing the start address to the FMSSTART register and the stop address to the FMSSTOP register The signature generation is started by writing a 1 to the SIG START bit in the FMSSTOP register Starting the signature generation is typically combined with defining the stop address which is done in the STOP bits of the same register The time that the signature generation takes is proportional to the address range for which the signature is generated Reading of the flash memory for signature generation uses a self timed read mechanism and does not depend on any configurable timing settings for the flash A safe estimation for the duration of the signature generation is Duration int 60 tcy 3 x FMSSTOP FMSSTART 1 When signature generation is triggered via software the duration is in AHB clock cycles and tcy is the time in ns for one AHB clock The SIG DONE bit in FMSTAT can be polled by
475. re to read the counter values at which the event selected by the corresponding Capture Control registers occurred Table 139 SCT capture registers 0 to 4 CAP 0 4 address 0x5000 4100 CAPO to 0x5000 4110 CAP4 bit description REGMODEn bit 1 Bit Symbol Description Reset value 15 0 VALCAP_L When UNIFY 0 read the 16 bit counter value at which this 0 register was last captured When UNIFY 1 read the lower 16 bits of the 32 bit value at which this register was last captured 31 16 VALCAP_H When UNIFY read the 16 bit counter value at which this 0 register was last captured When UNIFY 1 read the upper 16 bits of the 32 bit value at which this register was last captured SCT match reload registers 0 to 4 REGMODEn bit 0 A Match register L H or unified 32 bit is loaded from the corresponding Reload register when BIDIR is 0 and the counter reaches its limit condition or when BIDIR is 1 and the counter reaches 0 Table 140 SCT match reload registers 0 to 4 MATCHREL 0 4 address 0x5000 4200 MATCHRELO to 0x5000 4210 MATCHRELA bit description REGMODEn bit 0 Bit Symbol Description Reset value 15 0 RELOAD When UNIFY 0 read or write the 16 bit value to be loaded into 0 the SCTMATCHn L register When UNIFY 1 read or write the lower 16 bits of the 32 bit value to be loaded into the MATCHn register 31 16 RELOAD When UNIFY 0 read or write the 16 bit to be loaded into the 0 MATCHn H re
476. re user configured in the MSTTIME register for Master operation and the SLVTIME register for Slave operation See Section 16 7 1 1 Rate calculations for details on bus rate setup Table 192 I C Clock Divider register CLKDIV address 0x4005 0014 bit description Bit Symbol Description Reset value 15 0 DIVVAL This field controls how the clock PCLK is used by the 12C functions 0 that need an internal clock in order to operate 0x0000 PCLK is used directly by the 12C function 0x0001 PCLK is divided by 2 before use by the I C function 0x0002 PCLK is divided by 3 before use by the I C function OxFFFF PCLK is divided by 65 536 before use by the I C function 31 16 Reserved Read value is undefined only zero should be written NA I2C Interrupt Status register The INTSTAT register provides register provides a view of those interrupt flags that are currently enabled This can simplify software handling of interrupts See Table 186 for detailed descriptions of the interrupt flags All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 222 of 370 NXP Semiconductors UM10601 UM10601 16 6 8 Chapter 16 LPC81x I2C bus interface Table 193 12 Interrupt Status register INTSTAT address 0x4005 0018 bit description Bit 10 9 11 14 12 15 16 17 18 19 23 20 24 25 31 26 Symbol
477. receiving nack on address Table 313 12C Code example Master receive nack on address Address 0x23 Polling mode No error checking if LPC_ LPC_I2C gt LPC_I2C gt if LPC_ if LPC_ 2C gt 1 MSTDAT MSTCTL 2C gt 1 2C gt S1 AT amp while LPC_I2C gt STAT AT amp AT amp LPC_I2C gt CFG I2C CFG MSTEN while LPC I2C 5STAT amp I2C STAT MSTPENDING 2C STAT 0x23 I2C MSTCTL amp I2C 2C STAT LPC I2C MSTCTL I2C_MSTCTL_ while LPC I2C 5STAT amp I2C 2C STAT 5 5 STSTATE I2C STAT MSTST IDLE abort 0 address and 0 for RWn bit STSTART send start TAT_MSTPENDING STSTATE I2C_STAT_MSTST_NACK_ADDR abort STSTOP stop transaction TAT_MSTPENDING STSTATE I2C STAT MSTST IDLE abort All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 343 of 370 NXP Semiconductors UM10601 UM10601 29 2 8 29 2 9 Table 314 12C Code example Master receiving nack on data Chapter 29 LPC81x Code examples Master receive nack on data Address 0x23 data Oxdd Polling mode No error checking LPC_I2C gt CFG I2C MSTEN while LPC_I2C gt STAT amp I2C STAT MSTPE if LPC_I2C gt STAT amp
478. register If UNIFY 1 in the CONFIG register only the _L bits of this register are used The L bits control whether each set of match capture registers operates as unified 32 bit capture match registers If UNIFY 0 in the CONFIG register this register can be written to as two registers REGMODE_L and REGMODE_H Both the L and H registers can be read or written individually or in a single 32 bit read or write operation The _L bits registers control the L match capture registers and the _H bits registers control the H match capture registers The SCT contains 5 Match Capture register pairs The Register Mode register selects whether each register pair acts as a Match register See Section 10 6 18 or as a Capture register see Section 10 6 19 Each Match Capture register has an accompanying register which serves as a Reload register when the register is used as a Match register Section 10 6 20 or as a Capture Control register when the register is used as a capture register Section 10 6 21 REGMODE_H is used only when the UNIFY bit is 0 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 145 of 370 NXP Semiconductors U M1 0601 10 6 11 10 6 12 Chapter 10 LPC81x SCTimer PWM SCT Table 130 SCT match capture registers mode register REGMODE address 0x5000 404C bit description Bit Symbol Description Reset value
479. register 0x0000 0000 Table 131 OUTPUTDIRCTRL R W 0x054 SCT output counter direction control register 0x0000 0000 Table 132 RES R W 0x058 SCT conflict resolution register 0x0000 0000 Table 133 0 05 0 060 0 064 Reserved OxOEC EVEN R W OxOFO SCT event enable register 0x0000 0000 Table 134 EVFLAG R W Ox0F4 SCT event flag register 0x0000 0000 Table 135 CONEN R W OxOF8 SCT conflict enable register 0x0000 0000 Table 136 CONFLAG R W OxOFC SCT conflict flag register 0x0000 0000 Table 137 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 137 of 370 NXP Semiconductors UM10601 Chapter 10 LPC81x SCTimer PWM SCT Table 120 Register overview State Configurable Timer base address 0x5000 4000 continued Name Access Address Description Reset value Reference offset MATCHO to MATCH4 R W 0x100 to SCT match value register of match channels O to 0 0000 0000 Table 137 0x110 4 REGMODO to REGMODE4 0 MATCH_LO to R W 0x100 to SCT match value register of match channels O Table 137 MATCH_L4 0x110 4 low counter 16 bit REGMODO L to REGMODE4 L 0 MATCH_HO to R W 0x102 to SCT match value register of match channels O Table 137 MATCH_H4 0x112 4 high counter 16 bit REGMODO to REGMODE4 0 4 0 100 SCT capture register of capture channel 0 to 4 0x0000 0000 Table 1
480. register 45 4 6 3 System PLL control register 31 4 6 30 Deep sleep mode configuration register 46 4 6 4 System PLL status register 31 4631 Wake up configuration register 46 4 6 5 System oscillator control register 31 4 6 32 Power configuration register 47 4 6 6 Watchdog oscillator control register 32 46 33 Device ID register 48 4 6 7 System reset status register 34 4 7 Functional description 49 4 6 8 System PLL clock source select register 34 4 7 1 eee Reis Mane ahead 49 4 6 9 System PLL clock source update register 35 4 7 2 Start up 49 4 6 10 Main clock source select register 35 4 7 3 Brown out 50 4 6 11 Main clock source update enable register 35 4 7 4 System PLL functional description 50 4 6 12 System clock divider register 36 4 74 1 Lock 51 4 6 13 System clock control register 36 4 7 4 2 Power down 51 4 6 14 USART clock divider register 38 4 7 4 3 Divider ratio programming 52 4 6 15 CLKOUT clock source select register 38 4 7 4 3 1 Post divider 52 UM10601 All information provided in this document is subject to legal discla
481. ress 1 0x01 Table 199 SLVADR2 R W 0x50 Slave address 2 0x01 Table 199 SLVADR3 R W 0x54 Slave address 3 0x01 Table 199 SLVQUALO R W 0x58 Slave Qualification for address 0 0 Table 200 MONRXDAT RO 0x80 Monitor receiver data register 0 Table 201 16 6 1 12C Configuration register The CFG register contains mode settings that apply to Master Slave and Monitor functions Table 185 12C Configuration register CFG address 0x4005 0000 bit description Bit Symbol Value Description Reset Value 0 MSTEN Master Enable When disabled configurations settings for 0 the Master function are not changed but the Master function is internally reset 0 Disabled The I C Master function is disabled 1 Enabled The I C Master function is enabled 1 SLVEN Slave Enable When disabled configurations settings for 0 the Slave function are not changed but the Slave function is internally reset 0 Disabled The slave function is disabled 1 Enabled The slave function is enabled UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 213 of 370 NXP Semiconductors UM10601 UM10601 Chapter 16 LPC81x I2C bus interface Table 185 12C Configuration register CFG address 0x4005 0000 bit description Bit 31 5 Symbol MONEN TIMEOUTEN MONCLKSTR Value Description Reset Value Monitor Enable When disabl
482. rising edge Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0x2 Sticky falling edge Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0x3 Sticky rising or falling edge Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0 4 High level Match for this bit slice occurs when there is a high level the input specified for this bit slice in the PMSRC register 0 5 Low level Match occurs when there is a low level on the specified input 0 6 Constant 0 This bit slice never contributes to a match should be used to disable unused bit slices 0 7 Event Non sticky rising or falling edge Match occurs on an event i e when either rising or falling edge is first detected on the specified input this is a non sticky version of value 0x3 This bit is cleared after one clock cycle UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2
483. riting a one to this bit sets the TSTOP signal 0 in the MTB to HIGH and stops tracing if the TSTOPEN bit in the MTB master register is set to one as well 31 2 Reserved 0 POR captured PIO status register 0 The PIOPORCAPO register captures the state of GPIO port 0 at power on reset Each bit represents the reset state of one GPIO pin This register is a read only status register Table 38 POR captured PIO status register 0 PIOPORCAPO address 0x4004 8100 bit description Bit Symbol Description Reset value 17 0 PIOSTAT State of PIOO 17 through PIOO 0 at power on reset Implementation dependent 31 18 Reserved IOCON glitch filter clock divider registers 6 to 0 These registers individually configure the seven peripheral input clocks IOCONFILTR PCLK to the IOCON programmable glitch filter The clocks can be shut down by setting the DIV bits to OxO Table 39 IOCON glitch filter clock divider registers 6 to 0 IOCONCLKDIV 6 0 address 0x4004 8134 IOCONCLKDIV6 to 0x004 814C IOCONFILTCLKDIVO bit description Bit Symbol Description Reset value 7 0 DIV IOCON glitch filter clock divider values 0 0 Disable IOCONFILTR_PCLK 1 Divide by 1 to 255 Divide by 255 318 Reserved 0x00 BOD control register The BOD control register selects four separate threshold values for sending a BOD interrupt to the NVIC and for forced reset Reset and interrupt threshold values listed in Table 40 are typical values
484. roller can wake up from Power down mode in the same way as from Deep sleep mode Signal on one of the eight pin interrupts selected in Table 44 Each pin interrupt must also be enabled in the STARTERPO register Table 45 and in the NVIC BOD signal if the BOD is enabled in the PDSLEEPCFG register BOD interrupt using the interrupt wake up register 1 Table 46 The BOD interrupt must be enabled in the NVIC The BOD interrupt must be selected in the BODCTRL register Reset from the BOD circuit In this case the BOD reset must be enabled in the BODCTRL register Table 40 WWDT signal if the watchdog oscillator is enabled in the PDSLEEPCFG register WWDT interrupt using the interrupt wake up register 1 Table 46 The WWDT interrupt must be enabled in the NVIC The WWDT interrupt must be set in the WWDT MOD register Reset from the watchdog timer The WWDT reset must be set in the WWDT MOD register Via any of the USART blocks See Section 15 3 2 Configure the USART for wake up Via the I2C See Section 16 3 2 Via any of the SPI blocks See Section 17 3 1 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 65 of 370 NXP Semiconductors U M1 0601 5 7 7 5 7 7 1 5 7 7 2 Chapter 5 LPC81x Reduced power modes and Power Management Deep power down mode In Deep power down mode powe
485. rrupt Prototype ErrorCode_t i2c_slave_receive_intr I2C_HANDLE_T 126 I2C RESULT Input parameter 12C HANDLE T Handle to the allocated SRAM area I2C Pointer to the I2C PARAM struct I2C RESULT Pointer to the 12C RESULT struct Return ErrorCode Description Receives data from master Program control will be returned immediately and task will be completed on an interrupt driven basis When task is completed the callback function is called 24 4 11 12 Slave Transmit Interrupt Table 283 12C Slave Transmit Interrupt Routine I2C Slave Transmit Interrupt Prototype ErrorCode_t i2c_slave_transmit_intr l2C_HANDLE_T 12C_PARAM I2C RESULT Input parameter 126 HANDLE T Handle to the allocated SRAM area I2C Pointer to the I2C PARAM struct I2C RESULT Pointer to the 12C RESULT struct Return ErrorCode Description Sends data to the Master Program control will be returned immediately and task will be completed on an interrupt driven basis When task is completed the callback function is called UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 312 of 370 NXP Semiconductors UM10601 UM10601 24 4 12 24 4 13 24 4 14 24 4 15 Chapter 24 LPC81x I2C bus ROM API 12C Set Slave Address Table 284 12 Set Slave Address
486. rrupts The SysTick timer is clocked from the CPU clock the system clock see Figure 3 or from the reference clock which is fixed to half the frequency of the CPU clock In order to generate recurring interrupts at a specific interval the SYST_RVR register must be initialized with the correct value for the desired interval A default value is provided in the SYST_CALIB register and may be changed by software Example timer calculation To use the system tick timer do the following 1 Program the SYST_RVR register with the reload value RELOAD to obtain the desired time interval 2 Clear the SYST_CVR register by writing to it This ensures that the timer will count from the SYST_RVR value rather than an arbitrary value when the timer is enabled 3 Program the SYST_SCR register with the value 0x7 which enables the SysTick timer and the SysTick timer interrupt The following example illustrates selecting the SysTick timer reload value to obtain a 10 ms time interval with the system clock set to 20 MHz Example system clock 20 MHz The system tick clock system clock 20 MHz Bit CLKSOURCE in the SYST_CSR register set to 1 system clock RELOAD system tick clock frequency x 10 ms 1 20 MHz x 10 ms 1 200000 1 199999 0x00030DSF All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 186 of 370 UM10601 Chap
487. rs sss 93 7 6 Register description 91 7 6 9 GPIO port toggle registers 94 7 6 1 GPIO port byte pin registers 91 77 Functional description 94 7 6 2 GPIO port word pin registers 91 7 7 1 Reading pin 94 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 363 of 370 NXP Semiconductors UM10601 7 7 2 7 7 3 GPIO o tp t 94 Masked 95 Chapter 8 LPC81x Pin interrupts pattern match engine Chapter 30 Supplementary information Recommended 95 8 1 How read this chapter 96 8 6 4 Pin interrupt level or rising edge interrupt clear 8 2 Features 96 103 8 3 Basic 96 8 6 5 Pin VA ede level or falling edge PAD AM t enable S level or taling edge 8 4 Pin 97 867 Pin interrupt active level or falling edge interrupt 8 5 General description 97 clear register 105 8 5 1 Pin
488. rsions See Table 231 Pin location in ISP mode 21 2 Features 8 on chip boot ROM Contains the boot loader with In System Programming ISP facility and the following APIs In Application Programming IAP of flash memory Power profiles for optimizing power consumption and system performance USART drivers I2C drivers 21 3 Basic configuration The clock to the ROM is enabled by default No configuration is required to use the ROM 21 3 4 Boot loader versions The LPC81x boot loader may be updated for a new chip version You can determine the boot loader version using the ISP command Read Boot code version see Section 22 5 1 12 or from the part marking UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 269 of 370 NXP Semiconductors UM10601 Table 230 Boot loader versions Chapter 21 LPC81x Boot ROM Bootloader Marking Description version v13 1 initial 1A ISP IAP The following deviations from the specification apply version The the IAP erase page command allows only single page erase The start page parameter must the same as the end page parameter See Table 266 Code SECTOR NOT PREPARED FORWRITE OPERATION in ISP command C Write RAM to flash is not returned See Table 245 The ISP mode uses the USARTO interface for communication If USARTO is use
489. rted The set up is as follows 1 Allocate SRAM for the I2C ROM Driver by making a call to the i2c get mem size function 2 Create the I2C handle by making a call to the i2c_setup function 3 Set the 12 operating frequency by making a call to the i2c set bitrate function 4 Set the slave address by making a call to the i2c set slave addr function The I2C ROM driver allows setting up to 4 slave addresses and 4 address masks as well as possibly enabling the General Call address The four slave address bytes are packed into the 4 byte variable Slave address byte 0 is the least significant byte and Slave address byte 3 is the most significant byte The Slave address mask bytes are ordered the same way in the other 32 bit variable When in slave All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 317 of 370 NXP Semiconductors UM1 0601 UM10601 24 5 4 Chapter 24 LPC81x I2C bus ROM API receive mode all of these addresses or groups if masks are used will be monitored for a match If the General Call bit least significant bit of any of the four slave address bytes is set then the General Call address of 0x00 is monitored as well 31 25 24 23 17 16 15 9 8 7 1 0 Slave Address 3 GC Slave Address 2 GC Slave Address 1 GC Slave Address 0 GC Fig 50 12 sla
490. running then you can change the halt and stop condition with one single write to this register Remark Once set this bit can only be cleared by software to restore counter operation Writing a 1 to this bit clears the H counter This bit always reads as O Direction select Up The H counter counts up to its limit condition then is cleared to zero Bidirectional The H counter counts up to its limit then counts down to a limit condition or to 0 28 21 H Specifies the factor by which the SCT clock is prescaled to produce the counter 0 clock The counter clock is clocked at the rate of the SCT clock divided by PRELH 1 Remark Clear the counter by writing a 1 to the CLRCTR bit whenever changing the PRE value 31 29 Reserved UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 141 of 370 NXP Semiconductors U M1 0601 UM10601 Chapter 10 LPC81x SCTimer PWM SCT 10 6 3 SCT limit register 10 6 4 If UNIFY 1 in the CONFIG register only the _L bits are used If UNIFY 0 in the CONFIG register this register can be written to as two registers LIMIT_L and LIMIT_H Both the L and H registers can be read or written individually or in a single 32 bit read or write operation The bits in this register set which events act as counter limits When a limit event occurs the counter is cleared to zero in un
491. rupt 3 in the NVIC is raised if the minterm evaluates as true 4 PROD_EN Determines whether slice 4 is an endpoint 0 DPTS4 0 No effect Slice 4 is not an endpoint endpoint Slice 4 is the endpoint of a product term minterm Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true 5 PROD_EN Determines whether slice 5 is an endpoint 0 DPTSS 0 No effect Slice 5 is not an endpoint 1 endpoint Slice 5 is the endpoint of a product term minterm Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 112 of 370 NXP Semiconductors U M1 0601 Chapter 8 LPC81x Pin interrupts pattern match engine Table 105 Pattern match bit slice configuration register PMCFG address 0xA000 4030 bit description continued Bit Symbol Value Description Reset value 6 PROD EN Determines whether slice 6 is an endpoint 0 DPTS6 0 No effect Slice 6 is not an endpoint 1 endpoint Slice 6 is the endpoint of a product term minterm Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true 7 Reserved Bit slice 7 is automatically considered a product end point 0 10 8 CFGO Specifies the match contribution condition for bit slice 0 06000 0x0 Constant HIGH This bit slice always contributes to a product term match 0 1 Sticky rising e
492. rved User manual Rev 1 6 2 April 2014 280 of 370 NXP Semiconductors U M1 0601 UM10601 22 5 1 2 22 5 1 3 22 5 1 4 Chapter 22 LPC81x Flash ISP and IAP programming Set Baud Rate lt Baud Rate gt lt stop bit gt Table 240 UART ISP Set Baud Rate command Command B Input Baud Rate 9600 19200 38400 57600 115200 Stop bit 1 2 Return Code CMD SUCCESS INVALID BAUD RATE INVALID STOP BIT PARAM ERROR Description This command is used to change the baud rate The new baud rate is effective after the command handler sends the CMD SUCCESS return code Example B 57600 1 lt CR gt lt LF gt sets the serial port to baud rate 57600 bps 1 stop bit Echo setting Table 241 UART ISP Echo command Command A Input Setting ON 1 OFF 0 Return Code CMD SUCCESS PARAM ERROR Description The default setting for echo command is ON When ON the ISP command handler sends the received serial data back to the host Example A 0 lt CR gt lt LF gt turns echo off Write to RAM start address gt number of bytes gt The host should send the plain binary code after receiving the CMD SUCCESS return code This ISP command handler responds with OK lt CR gt lt LF gt when the transfer has finished Table 242 UART ISP Write to RAM command Command Input Start Address RAM address where data bytes are to be written This address should be a word boundary Nu
493. rved User manual Rev 1 6 2 April 2014 368 of 370 NXP Semiconductors UM10601 Chapter 30 Supplementary information 25 4 6 UART 325 25 4 10 UART ROM driver variables 326 25 4 7 UART 325 25 4 10 1 UART_CONFIG structure 326 25 4 8 UART interrupt service routine 325 25 4 10 2 UART_HANDLE_T 326 25 4 9 Error 325 25 4 10 3 UART 326 Chapter 26 LPC81x Debugging 26 1 How to read this chapter 328 26 5 Functional description 329 26 2 328 26 5 1 Debug limitations 329 26 3 General 328 26 52 Debug connections for SWD 329 26 5 3 Boundary lt 330 26 4 Pin 328 2654 Micro Trace Buffer MTB 331 Chapter 27 LPC81x Packages and pin description 27 1 Packages asc yen 332 27 2 Pin description 333 Chapter 28 LPC81x Appendix 28 1 How to read this chapter 337 28 2 General description 337 Chapter 29 LPC81x Code examples 29 1 How to read this chapter 340 29 2 16 Slave nack matched address from mast
494. s 2 2 General description UM10601 The LPC81x incorporates several distinct memory regions Figure 2 shows the overall map of the entire address space from the user program viewpoint following reset The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals Each peripheral is allocated 16 kB of space simplifying the address decoding The registers incorporated into the ARM Cortex M0 core such as NVIC SysTick and sleep mode control are located on the private peripheral bus The GPIO port and pin interrupt pattern match registers are accessed by the ARM Cortex M0 single cycle I O enabled port IOP All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 10 of 370 NXP Semiconductors U M1 0601 Chapter 2 LPC81x Memory mapping 2 2 1 Memory mapping APB peripherals 0x4008 0000 LPC81xM 4GB 1 OxFFFF 31 28 reserved S reserved 0xE010 0000 M OxE000 0000 0x4006 C000 USART1 reserved 0x4006 8000 0xA000 8000 USARTO 0x4006 4000 reserved pin interrupts pattern match 0xA000 4000 0x4006 0000 SP GPIO oA reserved A 0x4005 8000 reserve 0x9009 8000 0x4005 4000 12C 0x5000 4000 0 5000 0000 0x4004 C000 SYSCON 0x4004 8000 SS reserved S i anon ones ee IOGON 0x4004 4000 X 1
495. s All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 161 of 370 NXP Semiconductors UM10601 Chapter 10 LPC81x SCTimer PWM SCT counter STATE 0 Fig 22 SCT configuration example input transition events EV2 MATO match MATO dod AUTOLIMIT AUTOLIMIT Evi EV1 Ne EV3 EVO EVO EN EN SCT output 0 STATE 1 STATE 0 MATO MATO MATO AUTOLIMIT AUTOLIMIT AUTOLIMIT x EVA EV4 E EDS x x E EVO EVO This application of the SCT uses the following configuration all register values not listed in Table 147 are set to their default values Table 147 SCT configuration example Configuration Counter Clock base Match Capture registers Define match values Define match reload values Define when event 0 occurs Define when event 1 occurs UM10601 Registers CONFIG CONFIG CTRL CONFIG REGMODE 2 3 4 MATCHRELO 1 2 3 4 EVO CTRL EV1 CTRL All information provided in this document is subject to legal disclaimers Setting Uses one counter UNIFY 1 Enable the autolimit for MATO AUTOLIMIT 1 Uses unidirectional counter BIDIR L 0 Uses default values for clock configuration Configure one match register for each match event by setting REGMODE LL bits 0 1 2
496. s Enable bits in INTENSET are mapped in locations that correspond to the flags in the STAT register The complete set of interrupt enables may be read from this register Writing ones to implemented bits in this register causes those bits to be set The INTENCLR register is used to clear bits in this register Table 176 USART Interrupt Enable read and set register INTENSET address 0x4006 400C USARTO 0x4006 800C USART1 0x4006 COOC USART2 bit description Bit Symbol Description Reset Value 0 RXRDYEN When 1 enables an interrupt when there is a received 0 character available to be read from the RXDAT register 1 Reserved Read value is undefined only zero should be NA written 2 TXRDYEN When 1 enables an interrupt when the TXDAT register is 0 available to take another character to transmit 4 3 Reserved Read value is undefined only zero should be NA written 5 DELTACTSEN When 1 enables an interrupt when there is a change in the 0 state of the CTS input 6 TXDISINTEN When 1 enables an interrupt when the transmitter is fully 0 disabled as indicated by the TXDISINT flag in STAT See description of the TXDISINT bit for details 7 Reserved Read value is undefined only zero should be NA written 8 OVERRUNEN When 1 enables an interrupt when an overrun error 0 occurred 10 9 Reserved Read value is undefined only zero should be NA written 11 DELTARXBRKEN When 1 enables an interrupt when a change of state h
497. s inverted this is done as the signal leaves enters the SPI block In slave mode the asserted SSEL that is connected to a pin will activate the SPI In master mode the SSEL that is connected to a pin will be output as defined in the SPI registers In master mode the Slave Select is configured by the TXSSELN field which appears in both the TXCTL and TXDATCTL registers In slave mode the state of the SSEL is saved along with received data in the RXSSEL field of the RXDAT register Data lengths greater than 16 bits The SPI interface handles data frame sizes from 1 to 16 bits directly Larger sizes can be handled by splitting data up into groups of 16 bits or less For example 24 bits can be supported as 2 groups of 16 bits and 8 bits or 2 groups of 12 bits among others Frames of any size including greater than 32 bits can supported in the same way Details of how to handle larger data widths depend somewhat on other SPI configuration options For instance if it is intended for Slave Selects to be deasserted between frames then this must be suppressed when a larger frame is split into more than one part Sending 2 groups of 12 bits with SSEL deasserted between 24 bit increments for instance would require changing the value of the EOF bit on alternate 12 bit frames All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 251 of 3
498. s U M1 0601 UM10601 Chapter 1 LPC81x Introductory information State Configurable Timer SCTimer PWM or SCT with input and output functions including capture and match assigned to pins through the switch matrix Multiple channel multi rate timer MRT for repetitive interrupt generation at up to four programmable fixed rates Self Wake up Timer WKT clocked from either the IRC or a low power low frequency internal oscillator CRC engine Windowed Watchdog timer WWDT Analog peripherals Comparator with external voltage reference with pin functions assigned or enabled through the switch matrix Serial interfaces Three USART interfaces with pin functions assigned through the switch matrix Two SPI controllers with pin functions assigned through the switch matrix I C bus interface with pin functions assigned through the switch matrix Clock generation 12 MHz internal RC oscillator trimmed to 1 96 accuracy that can optionally be used as a system clock Crystal oscillator with an operating range of 1 MHz to 25 MHz Programmable watchdog oscillator with a frequency range of 9 4 kHz to 2 3 MHz 10 kHz low power oscillator for the WKT PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal May be run from the system oscillator the external clock input CLKIN or the internal RC oscillator Clock output functi
499. s effect All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 47 of 370 NXP Semiconductors UM10601 UM10601 4 6 33 Chapter 4 LPC81x System configuration SYSCON The system oscillator requires typically 500 us to start up after the SYSOSC_PD bit has been changed from 1 to 0 There is no hardware flag to monitor the state of the system oscillator Therefore add a software delay of about 500 us before using the system oscillator after power up Table 49 Power configuration register PDRUNCFG address 0x4004 8238 bit description Bit 0 11 8 14 12 15 31 16 Symbol IRCOUT_PD IRC_PD FLASH_PD BOD PD SYSOSC PD WDTOSC PD SYSPLL PD ACMP Value Description IRC oscillator output power Powered Powered down IRC oscillator power down Powered Powered down Flash power down Powered Powered down BOD power down Powered Powered down Reserved Crystal oscillator power down After power up add a software delay of approximately 500 us before using Powered Powered down Watchdog oscillator power down Changing this bit to powered down has no effect when the LOCK bit in the WWDT MOD register is set In this case the watchdog oscillator is always running Powered Powered down System PLL power down Powered Powered down Reserved Always write these bits as 0b1101 Res
500. s reserved 0 0 IOCONCLKDIVO Ox1 IOCONCLKDIV1 0 2 IOCONCLKDIV2 0x3 IOCONCLKDIVS 0 4 IOCONCLKDIV4 0 5 IOCONCLKDIV5 0 6 IOCONCLKDIV6 31 16 Reserved UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 80 of 370 NXP Semiconductors UM10601 6 5 10 PIOO 16 register Chapter 6 LPC81x I O configuration IOCON Table 71 PIOO_16 register PIOO 16 address 0x4004 4024 bit description Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor 0b10 control 0x0 Inactive no pull down pull up resistor enabled 0 1 Pull down resistor enabled 0 2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 5 Reserved 0b001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled Remark This is not a true open drain mode 12 11 5 MODE Digital filter sample mode 0 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than one filter clock are rejected 0 2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 1543 CLK_
501. s subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 68 of 370 NXP Semiconductors U M1 0601 Chapter 6 LPC81x I O configuration IOCON 6 4 General description 6 4 4 Pin configuration Vpp Vpp open drain enable pin configured output enable t oE ote as digital output driver data output strong E pull down Vpp weak pull up pull up enable repeater mode mi weak pin configured enable m pull down as digital input pull down enable lt 1 data input PROGRAMMABLE GLITCH FILTER select data inverter select glitch filter select analog input pin configured arises ii as analog input Fig 6 Pin configuration 6 4 2 Pin function The pin function is determined entirely through the switch matrix By default one of the GPIO functions is assigned to each pin The switch matrix can assign all functions from the movable function table to any pin in the IOCON block or enable a special function like an analog input on a specific pin Related links Table 107 Movable functions assign to pins PIOO 0 to PIOO 17 through switch matrix 6 4 3 Pin mode The MODE bit in the IOCON register allows enabling or disabling an on chip pull up resistor for each pin By default all pull up resistors are enabled except for the I2C
502. s the NMI which can be triggered by an peripheral interrupt or triggered by software The NMI has the highest priority exception other than the reset You can set up any peripheral interrupt listed in Table 3 as NMI using the NMISRC register in the SYSCON block Table 43 To avoid using the same peripheral interrupt as NMI exception and normal interrupt disable the interrupt in the NVIC when you configure it as NMI 3 3 3 Vector table offset The vector table contains the reset value of the stack pointer and the start addresses also called exception vectors for all exception handlers On system reset the vector table is located at address 0x0000 0000 Software can write to the VTOR register in the NVIC to relocate the vector table start address to a different memory location For a description of the VTOR register see Ref 5 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 14 of 370 NXP Semiconductors U M1 0601 Chapter 3 LPC81x Nested Vectored Interrupt Controller NVIC 3 4 Register description The NVIC registers are located on the ARM private peripheral bus Table 4 Register overview NVIC base address 0xE000 E000 Name Access Address Description Reset Reference offset value ISERO RW 0x100 Interrupt Set Enable Register 0 This register allows enabling 0 Table 5 interrupts and reading back the interrupt enables
503. scription Receiver Data This contains the next piece of received data The number of bits that are used depends on the FLen setting in TXCTL TXDATCTL Slave Select for receive This field allows the state of the SSEL pin to be saved along with received data The value will reflect the SSEL pin for both master and slave operation A zero indicates that a slave select is active The actual polarity of each slave select pin is configured by the related SPOL bit in CFG Reserved Start of Transfer flag This flag will be 1 if this is the first data after SSEL went from deasserted to asserted i e any previous transfer has ended This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bit Reserved the value read from a reserved bit is not defined Reset value undefined undefined NA All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 242 of 370 NXP Semiconductors U M1 0601 Chapter 17 LPC81x SPIO 1 17 6 7 SPI Transmitter Data and Control register The TXDATCTL register provides a location where both transmit data and control information can be written simultaneously This allows detailed control of the SPI without a separate write of control information for each piece of data Remark The SPI has no receiver control registers Hence softw
504. ser manual Rev 1 6 2 April 2014 104 of 370 NXP Semiconductors U M1 0601 UM10601 8 6 7 8 6 8 Chapter 8 LPC81x Pin interrupts pattern match engine Table 98 Pin interrupt active level or falling edge interrupt set register SIENF address 0xA000 4014 bit description Bit Symbol Description Reset Access value 7 0 SETENAF Ones written to this address set bits in the IENF thus NA WO enabling interrupts Bit n sets bit n in the IENF register 0 No operation 1 Select HIGH active interrupt or enable falling edge interrupt 31 8 Reserved Pin interrupt active level or falling edge interrupt clear register For each of the 8 pin interrupts selected in the PINTSELn registers see Section 4 6 27 one bit in the CIENF register sets the corresponding bit in the IENF register depending on the pin interrupt mode configured in the ISEL register e f the pin interrupt mode is edge sensitive PMODE 0 the falling edge interrupt is cleared e f the pin interrupt mode is level sensitive PMODE 1 the LOW active interrupt is selected Table 99 Pin interrupt active level or falling edge interrupt clear register CIENF address 0xA000 4018 bit description Bit Symbol Description Reset Access value 7 0 Ones written to this address clears bits in the IENF thus NA WO disabling interrupts Bit n clears bit n in the IENF register 0 No operation 1 LOW active interrupt selected or falli
505. served User manual Rev 1 6 2 April 2014 190 of 370 NXP Semiconductors UM10601 Chapter 15 LPC81x USARTO 1 2 Table 171 USART pin description Function Direction Pin UO_SCLK I O any U1_TXD any U1 1 any U1 RTS U1 CTS U1_SCLK I O any U2_TXD any U2 RXD any U2 RTS any U2 CTS l any U2_SCLK I O any Description Serial clock input output for USARTO in synchronous mode Clock input or output in synchronous mode Transmitter output for USART1 Serial transmit data Receiver input for USART1 Request To Send output for USART1 Clear To Send input for USART1 Serial clock input output for USART1 in synchronous mode Transmitter output for USART2 Serial transmit data Receiver input for USART2 Request To Send output for USART2 Clear To Send input for USART2 Serial clock input output for USART2 in synchronous mode SWM register PINASSIGN1 PINASSIGN1 PINASSIGN1 PINASSIGN1 PINASSIGN2 PINASSIGN2 PINASSIGN2 PINASSIGN2 PINASSIGN3 PINASSIGN3 PINASSIGN3 Reference Table 110 Table 110 Table 110 Table 110 Table 111 Table 111 Table 111 Table 111 Table 112 Table 112 Table 112 15 5 General description The USART receiver block monitors the serial input line Un_RXD for valid input The receiver shift register assembles characters as they are received after which they are passed to the receiver buffer register to await access by the CPU Th
506. sing edges of the input and feedback clocks Only when this difference is smaller than the so called lock criterion for more than eight consecutive input clock periods the lock output switches from low to high A single too large phase difference immediately resets the counter and causes the lock signal to drop if it was high Requiring eight phase measurements in a row to be below a certain figure ensures that the lock detector will not indicate lock until both the phase and frequency of the input and feedback clocks are very well aligned This effectively prevents false lock indications and thus ensures a glitch free lock signal Power down control To reduce the power consumption when the PLL clock is not needed a PLL Power down mode has been incorporated This mode is enabled by setting the SYSPLL_PD bit to one in the Power down configuration register Table 49 In this mode the internal current All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 51 of 370 NXP Semiconductors U M1 0601 Chapter 4 LPC81x System configuration SYSCON reference will be turned off the oscillator and the phase frequency detector will be stopped and the dividers will enter a reset state While in PLL Power down mode the lock output will be low to indicate that the PLL is not in lock When the PLL Power down mode is terminated by setting the
507. software to determine when signature generation is complete After signature generation a 32 bit signature can be read from the FMSWO register The 32 bit signature reflects the corrected data read from the flash and the flash parity bits and check bit values Content verification The signature as it is read from the FMSWO register must be equal to the reference signature The following pseudo code shows the algorithm to derive the reference signature sign 0 FOR address FMSSTART START to FMSSTOP STOPA FOR 0 TO 30 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 267 of 370 NXP Semiconductors U M1 0601 Chapter 20 LPC81x Flash controller nextSign i f Q address 1 sign i 1 nextSign 31 f Q address 31 sign 0 sign 10 sign 30 sign 31 sign nextSign signature32 sign UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 268 of 370 UM10601 Chapter 21 LPC81x Boot ROM Rev 1 6 2 April 2014 User manual 21 1 How to read this chapter The boot loader is identical for all parts The Boot ROM implementation changes with the chip version See Section 21 3 1 In addition the ISP entry pin location is different for different chip ve
508. ss 0xA000 4028 bit description 88 bit 107 Table 79 PIOO 14 register PIOO 14 address 0x4004 Table 104 Pattern match bit slice source register PMSRC 4048 bit description 89 address 0xA000 402C bit description 107 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 356 of 370 NXP Semiconductors UM10601 Table 105 Pattern match bit slice configuration register PMCFG address 0xA000 4030 bit description 112 Table 106 Pin interrupt registers for edge and level sensitive pins 117 Table 107 Movable functions assign to pins PIOO_0 to PIOO 17 through switch matrix 125 Table 108 Register overview Switch matrix base address 0x4000 C000 127 Table 109 Pin assign register 0 PINASSIGNO address 0x4000 C000 bit description 127 Table 110 Pin assign register 1 PINASSIGN1 address 0x4000 C004 bit description 128 Table 111 Pin assign register 2 PINASSIGN2 address 0x4000 C008 bit description 128 Table 112 Pin assign register 3 PINASSIGNS address 0x4000 bit description 129 Table 113 Pin assign register 4 PINASSIGN4 address 0x4000 C010 bit description 129 Table
509. ster DPDCTRL address 0x4002 0014 bit description Bit Symbol Value Description Reset value 0 WAKEUPHYS WAKEUP pin hysteresis enable 0 0 Disabled Hysteresis for WAKEUP pin disabled 1 Enabled Hysteresis for WAKEUP pin enabled 1 WAKEPAD WAKEUP pin disable Setting this bit disables the wake up pin so it can be 0 DISABLE used for other purposes Remark Never set this bit if you intend to use a pin to wake up the part from Deep power down mode You can only disable the wake up pin if the self wake up timer is enabled and configured Remark Setting this bit is not necessary if Deep power down mode is not used 0 Enabled The wake up function is enabled on pin PIOO 4 1 Disabled Setting this bit disables the wake up function on pin PIOO 4 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 60 of 370 UM10601 Chapter 5 LPC81x Reduced power modes and Power Management NXP Semiconductors Table 58 Deep power down control register DPDCTRL address 0x4002 0014 bit description Bit Symbol continued Reset value Value Description 2 LPOSCEN Enable the low power oscillator for use with the 10 kHz self wake up timer 0 clock You must set this bit if the CLKSEL bit in the self wake up timer CTRL bit is set Do not enable the low power oscillator if the self wake up timer is clocked by the divided IRC 0 Disabl
510. ster Transmit and Receive Polling 310 244 22 and RESULT structure 315 24 4 5 12 Master Transmit Interrupt 310 24423 Error structure 316 24 4 6 I2C Master Receive Interrupt 311 24424 12C 316 24 4 7 I2C Master Transmit Receive Interrupt 311 er 24 4 8 12C Slave Receive Polling 311 e s ds 24 44 9 12 Slave Transmit Polling 312 2 ide 24 4 10 2C Slave Receive Interrupt 312 Ms be duct sae piatat 317 24 4 11 I2C Slave Transmit Interrupt 312 2 318 24 4 12 12 Set Slave Address 313 HMM b RM 24443 I2C Get Memory 313 2s c em 244 144 12 313 m LC Chapter 25 LPC81x USART API ROM driver routines 25 1 How to read this chapter 322 25 4 1 UART get memory size 323 25 227 Feal l98 Ra 322 2542 324 25 3 General 322 oe ae SUUS SAUCE REN RMON 728 25 4 5 UART put 324 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights rese
511. t 0 1 ACMP 11 0x2 ACMP 12 0x3 Reserved 0x4 Reserved 0x5 Reserved 0x6 Internal reference voltage bandgap 0 7 Reserved 19 14 Reserved Write as 0 0 20 EDGECLR Interrupt clear bit To clear the COMPEDGE bitand 0 thus negate the interrupt request toggle the EDGECLR bit by first writing a 1 and then a 0 21 COMPSTAT Comparator status This bit reflects the state of the 0 comparator output 22 Reserved Write as O 0 23 COMPEDGE Comparator edge detect status 0 24 Reserved Write as O 0 26 25 HYS Controls the hysteresis of the comparator When the 0 comparator is outputting a certain state this is the difference between the selected signals in the opposite direction from the state being output that will switch the output 0x0 None the output will switch as the voltages cross 0 1 5 mV 0 2 10 mV 0x3 20 mV 31 27 Reserved E UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 258 of 370 NXP Semiconductors U M1 0601 Chapter 18 LPC81x Analog comparator 18 6 2 Voltage ladder register This register enables and controls the voltage ladder The fraction of the reference voltage produced by the ladder is programmable in steps of 1 31 Table 219 Voltage ladder register LAD address 0x4002 4004 bit description Bit Symbol Value Description Reset value LADEN Voltage ladder enable 0 5 1 LADSEL Voltage l
512. t Byte immediate offset Word register offset Halfword register offset Signed halfword register offset Byte register offset Signed byte register offset PC relative SP relative Multiple excluding base Multiple including base Word immediate offset Halfword immediate offset Byte immediate offset Word register offset Halfword register offset Byte register offset SP relative Multiple Push Push with link register Pop Pop and return All information provided in this document is subject to legal disclaimers Assembler ANDS Rd Rd Rm EORS Rd Rd Rm ORRS Rd Rd Rm BICS Rd Rd Rm MVNS Rd Rm TST Rn Rm LSLS Rd Rm lt shift gt LSLS Rd Rd Rs LSRS Rd Rm lt shift gt LSRS Rd Rd Rs ASRS Rd Rm lt shift gt ASRS Rd Rd Rs RORS Rd Rd Rs LDR Rd Rn lt imm gt LDRH Rd Rn lt imm gt LDRB Rd Rn lt imm gt LDR Rd Rn Rm LDRH Rd Rn Rm LDRSH Rd Rn Rm LDRB Rd Rn Rm LDRSB Rd Rn Rm LDR Rd label LDR Rd SP lt imm gt LDM Rn lt loreglist gt LDM Rn lt loreglist gt STR Rd Rn lt imm gt STRH Rd Rn lt imm gt STRB Rd Rn lt imm gt STR Rd Rn Rm STRH Rd Rn Rm STRB Rd Rn Rm STR Rd SP lt imm gt STM Ral lt loreglist gt PUSH lt loreglist gt PUSH lt loreglist gt LR POP lt loreglist gt POP lt loreglist gt PC Cycles k k er ee Cee re Cr Ce Ce 1 2 or 122 2 or 121 2 o
513. t running then you can change the halt and stop condition with one single write to this register Remark Once set only software can clear this bit to restore counter operation Writing a 1 to this bit clears the L or unified counter This bit always reads as 0 0 L or unified counter direction select Up The counter counts up to its limit condition then is cleared to zero Bidirectional The counter counts up to its limit then counts down to a limit condition or to 0 Specifies the factor by which the SCT clock is prescaled to produce the L or unified 0 counter clock The counter clock is clocked at the rate of the SCT clock divided by PRE_L 1 Remark Clear the counter by writing a 1 to the CLRCTR bit whenever changing the PRE value Reserved This bit is 1 when the H counter is counting down Hardware sets this bit whenthe 0 counter limit is reached and BIDIR is 1 Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0 When this bit is 1 and HALT is 0 the H counter does not run but I O events related 0 to the counter can occur If such an event matches the mask in the Start register this bit is cleared and counting resumes When this bit is 1 the counter does not run and no events can occur A reset sets 1 this bit When the HALT bit is one the STOP bit is cleared If you want to remove the halt condition and keep the SCT in the stop condition not
514. t 4 1 RESET PIOO 5 PIOO 7 LPC800 E PIOO_4 WAKEUP TRST 020 Vss SWCLK PIOO_3 TCK Vpp PIOO 8 gt SWDIO PIOO 2 TMS PIOO 8 XTALIN pin number 8 PIOO 11 PIOO_9 XTALOUT PIOO 10 PIOO_1 ACMP_2 CLKIN TDI e pin number 16 PIOO 16 PIOO 15 assign FUNC RXD PINASSIGNO bits 15 8 0x10 function UO TXD assign FUNC UO TXD PINASSIGNO bits 7 0 0x8 assigned to SO20 package pin 14 function UO RXD assigned to SO20 package pin 10 A pin is identified for the purpose of programming the switch matrix by its default GPIO port pin number Fig 13 Example Connect function UO RXD and UO TXD to pins 10 and 14 on the SO20 package The switch matrix connects all internal signals listed in the table of movable functions through the pin assignment registers to external pins on the package External pins are identified by their default GPIO pin number PIOO n Follow these steps to connect an internal signal FUNC to an external pin An example of a movable function is the UART transmit signal TXD 1 Find the function FUNC in the list of movable functions in Table 107 or in the data sheet 2 Use the LPC81x data sheet to decide which pin x on the LPC81x package to connect FUNC to 3 Use the pin description table to find the default GPIO function PIOO n assigned to package pin x m is the pin number 4 Locate the pin assignment register for the function FUNC in the switch matrix register
515. t Access value 31 0 PWORD Read 0 is LOW ext R W Write 0 clear output bit Read OxFFFF FFFF pin is HIGH Write any value 0x0000 0001 to OxFFFF FFFF set output bit Remark Only 0 or OxFFFF FFFF can be read Writing any value other than 0 will set the output bit GPIO port direction registers Each GPIO port has one direction register for configuring the port pins as inputs or outputs Table 84 GPIO direction port 0 register DIRO address 0xA000 2000 bit description Bit Symbol Description Reset Access value 17 0 DIRPO Selects pin direction for pin PIOO n bit 0 PIOO 0 bit1 0 R W PIOO 1 bit 17 PIOO 17 0 input 1 output 31 18 Reserved 0 GPIO port mask registers These registers affect writing and reading the MPORT registers Zeroes in these registers enable reading and writing ones disable writing and result in zeros in corresponding positions when reading Table 85 GPIO mask port 0 register MASKO address 0xA000 2080 bit description Bit Symbol Description Reset Access value 17 0 Controls which bits corresponding to PIOO n are active in the 0 R W POMPORT register bit PIOO 0 bit 1 PIOO 1 bit 17 PIOO 17 0 Read MPORT pin state write MPORT load output bit 1 Read MPORT 0 write MPORT output bit not affected 31 18 Reserved 0 GPIO port pin registers Reading these registers returns the current state of the pins read regardl
516. t WDCLK A match of the watchdog timer counter to WARNINT occurs when the bottom 10 bits of the counter have the same value as the 10 bits of WARNINT and the remaining upper bits of the counter are all 0 This gives a maximum time of 1 023 watchdog timer counts 4 096 watchdog clocks for the interrupt to occur prior to a watchdog event If WARNINT is 0 the interrupt will occur at the same time as the watchdog event Table 161 Watchdog Timer Warning Interrupt register WARNINT 0x4000 4014 bit description Bit Symbol Description Reset Value 9 0 WARNINT Watchdog warning interrupt compare value 0 31 10 Reserved user software should not write ones to reserved bits The NA value read from a reserved bit is not defined Watchdog Timer Window register The WINDOW register determines the highest WDTV value allowed when a watchdog feed is performed If a feed sequence occurs when WDTV is greater than the value in WINDOW a watchdog event will occur WINDOW resets to the maximum possible WDTV value so windowing is not in effect All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 178 of 370 NXP Semiconductors U M1 0601 Chapter 12 LPC81x Windowed Watchdog Timer WWDT Table 162 Watchdog Timer Window register WINDOW 0x4000 4018 bit description Bit Symbol Description Reset Value 23 0 WINDOW Watchdog window v
517. t read or write operation Remark Any event halting the counter disables its operation until software clears the HALT bit or bits in the CTRL register Table 122 Table 124 SCT halt condition register HALT address 0x5004 400C bit description Bit Symbol Description Reset value 5 0 HALTMSK L If bit n is one event n sets the HALT L bit in the CTRL register 0 event 0 bit 0 event 1 bit 1 event 5 bit 5 156 Reserved 21 16 HALTMSK If bit n is one event sets the HALT bit the CTRL register 0 event 0 bit 16 event 1 bit 17 event 5 bit 21 31 22 Reserved All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 142 of 370 NXP Semiconductors U M1 0601 UM10601 10 6 5 10 6 6 10 6 7 Chapter 10 LPC81x SCTimer PWM SCT SCT stop condition register If UNIFY 1 in the CONFIG register only the _L bits are used If UNIFY 0 in the CONFIG register this register can be written to as two registers STOPT_L and STOP_H Both the L and H registers can be read or written individually or in a single 32 bit read or write operation Table 125 SCT stop condition register STOP address 0x5000 4010 bit description Bit Symbol Description Reset value 5 0 STOPMSK L If bit n is one event n sets the STOP L bit in the CTRL register 0 event 0 bit 0 event 1 bit 1 event
518. t set to 1 STOP or repeated START is received Anerror condition is detected When using the interrupt function calls the callback functions must be define Upon the completion of a read write as specified by the PARAM structure the callback functions will be invoked 24 5 6 12C time out feature timeout Timeout time value Specifies the timeout interval value in increments of 16 I2C function clocks Min value is 16 LH if timeout 0 timeout feature is disabled if timeout 0 time value is timeout 16 i2c function clock ErrorCode t i2c set timeout I2C HANDLE T h_i2c uint32 t timeout I2C DRIVER TypeDef h declare pointer to i2c structure handle h I2C DRIVER TypeDef h_i2c assign handle pointer address if timeout 0 h i2c base TimeOut timeout 1 lt lt 4 Enable timeout feature h gt i2c_base gt CFG BI2C TIMEOUT EN else disable timeout feature h i2c base CFG amp BI2C_TIMEOUT_EN return LPC_OK i2c_set_timeout UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 321 of 370 UM10601 Chapter 25 LPC81x USART API ROM driver routines Rev 1 6 2 April 2014 User manual 25 1 How to read this chapter The USART ROM driver routines are available on all LPC81x parts 25 2 Features Send and receive characters in asynchronous or synchrono
519. tch matrix UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 123 of 370 NXP Semiconductors U M1 0601 Chapter 9 LPC81x Switch matrix SYSCON PIN PINTSEL 7 0 INTERRUPT ur digital input sms Dx digital output ena analog ena a GPIO_INT_BMAT USARTO DIGITAL PERIPHERAL DIGITAL PERIPHERAL ANALOG gt PERIPHERAL UO RXD Fig 14 Functional diagram of the switch matrix Remark From all movable and fixed pin functions you can assign multiple functions to the same pin but no more than one output or bidirectional function see Figure 14 Use the following guidelines when assigning pins Itis allowed to connect one input signal on a pin to multiple internal inputs by programming the same pin number in more than one PINASSIGN register Example You can enable the CLKIN input in the PINENABLEO register on pin PIOO 1 and also assign one ore more SCT inputs to pin PIOO 1 through the PINASSIGN registers to feed the CLKIN into the SCT You can send the input on one pin to all SCT inputs to use as an SCT abort signal It is allowed to let one digital output function control one or more digital inputs by programming the same pin number in the PINASSIGN register bit fields for the output and inputs Example You can assig
520. ted a Start event on the I C bus 1 Start detect The monitor function has detected a Start event on the 12C bus All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 228 of 370 NXP Semiconductors U M1 0601 Chapter 16 LPC81x I2C bus interface Table 201 Monitor data register MONRXDAT address 0x4005 0080 bit description Bit Symbol Value Description Reset value 9 MONRESTART Monitor Received Repeated Start 0 0 No start detect The monitor function has not detected a Repeated Start event on the I2C bus 1 Repeated start detect The monitor function has detected a Repeated Start event on the I C bus 10 MONNACK Monitor Received NACK 0 0 Acknowledged The data currently being provided by the monitor function was acknowledged by at least one master or slave receiver 1 Not acknowledged The data currently being provided by the monitor function was not acknowledged by any receiver 31 11 Reserved Read value is undefined only zero should be NA written 16 7 Functional description UM10601 16 7 1 16 7 1 1 16 7 2 Bus rates and timing considerations Due to the nature of the I C bus it is generally not possible to guarantee a specific clock rate on the SCL pin On the I2C bus the clock can be stretched by any slave device extended by software overhead time etc In a multi master system the
521. ted complemented by writing ones to these write only registers regardless of MASK registers Table 90 GPIO toggle port 0 register address 0xA000 2300 bit description Bit Symbol Description Reset Access value 17 0 NOTPO Toggle output bits NA WO 0 no operation 1 Toggle output bit 31 18 Reserved 0 description 7 7 1 7 7 2 UM10601 Reading pin state Software can read the state of all GPIO pins except those selected for an analog function in the switch matrix logic A pin does not have to be selected for GPIO in the switch matrix in order to read its state There are several ways to read the pin state The state of a single pin can be read with 7 high order zeros from a Byte Pin register The state of a single pin can be read in all bits of a byte halfword or word from a Word Pin register The state of multiple pins in a port can be read as a byte halfword or word from a PORT register The state of a selected subset of the pins in a port can be read from a Masked Port MPORT register Pins having a 1 in the port s Mask register will read as 0 from its MPORT register GPIO output Each GPIO pin has an output bit in the GPIO block These output bits are the targets of write operations to the pins Two conditions must be met in order for a pin s output bit to be driven onto the pin 1 The pin must be selected for GPIO operation in the switch matrix 2 The pin must be sele
522. ted in the PINTSELn registers see Section 4 6 27 on which a falling edge has been detected Writing ones to this register clears falling edge detection Ones in this register assert an interrupt request for pins that are enabled for falling edge interrupts All edges are detected for all pins selected by the PINTSELn registers regardless of whether they are interrupt enabled Table 101 Pin interrupt falling edge register FALL address 0xA000 4020 bit description Bit Symbol Description Reset Access value 7 0 FDET Falling edge detect Bit n detects the falling edge of the pin 0 R W selected in PINTSELn Read 0 No falling edge has been detected on this pin since Reset or the last time a one was written to this bit Write 0 no operation Read 1 a falling edge has been detected since Reset or the last time a one was written to this bit Write 1 clear falling edge detection for this pin 318 Reserved Pin interrupt status register Reading this register returns ones for pin interrupts that are currently requesting an interrupt For pins identified as edge sensitive in the Interrupt Select register writing ones to this register clears both rising and falling edge detection for the pin For level sensitive pins writing ones inverts the corresponding bit in the Active level register thus switching the active level on the pin Table 102 Pin interrupt status register IST address 0xA000 4024 bit description Bit S
523. ter 15 LPC81x USART0 1 2 Rev 1 6 2 April 2014 User manual 15 1 How to read this chapter 15 2 Features USARTO and USART1 are available on all parts USART2 is available on parts LPC812M101JDH16 and LPC812M101JDH20 only Read this chapter for a description of the USART peripheral and the software interface The LPC81x also provides an on chip ROM based USART API to configure and operate the USART See Table 293 See Section 29 4 Code examples UART for code examples that explain how to program the register interface e 7 8 or 9 data bits and 1 or 2 stop bits Synchronous mode with master or slave operation Includes data phase selection and continuous clock option Multiprocessor multidrop 9 bit mode with software address compare RS 485 possible with software address detection and transceiver direction control Parity generation and checking odd even or none One transmit and one receive data buffer RTS CTS for hardware signaling for automatic flow control Software flow control can be performed using Delta CTS detect Transmit Disable control and any GPIO as an RTS output Received data and status can optionally be read from a single register Break generation and detection Receive data is 2 of 3 sample voting Status flag set when one sample differs Built in Baud Rate Generator e A fractional rate divider is shared among all USARTS Interrupts available for Receive
524. ter if you want to understand the I2C operation and the software interface and want to learn how to use the 12C for wake up from reduced power modes The LPC81x provides an on chip ROM based 12 API to configure and operate the I2C See Table 272 2 API calls See Section 29 2 Code examples I2C for code examples that explain how to program the register interface 16 2 Features Independent Master Slave and Monitor functions Supports both Multi master and Multi master with Slave functions Multiple IC slave addresses supported in hardware One slave address can be selectively qualified with a bit mask or an address range in order to respond to multiple 12C bus addresses 10 bit addressing supported with software assist Supports SMBus 16 3 Basic configuration Configure I2C using the following registers UM10601 In the SYSAHBCLKCTRL register set bit 5 Table 30 to enable the clock to the register interface Clear the I2C peripheral reset using the PRESETCTRL register Table 19 Enable disable the 12C interrupt in interrupt slots 8 in the NVIC Configure the I2C pin functions through the switch matrix See Section 16 4 The peripheral clock for the I2C is the system clock see Figure 32 All information provided in this document is subject to legal disclaimers NXP B V 2014 AII rights reserved User manual Rev 1 6 2 April 2014 206 of 370 NXP Semiconductors U M1 0601 UM10601
525. terface any of these events is longer than the time configured in the TIMEOUT register This time out could be useful in monitoring 12C bus within a system as part of a method to keep the bus running of problems occur The second type of I C time out is reflected by the SCLTIMEOUT flag in the STAT register This time out is asserted when the SCL signal remains low longer than the time configured in the TIMEOUT register This corresponds to SMBus time out parameter TriMEour In this situation a slave could reset its own I C interface in case it is the offending device If all listening slaves including masters that can be addressed as slaves do this then the bus will be released unless it is a current master causing the problem Refer to the SMBus specification for more details Both types of time out are generated when the I C bus is considered busy Ten bit addressing Ten bit addressing is accomplished by the IC master sending a second address byte to extend a particular range of standard 7 bit addresses In the case of the master writing to the slave the I C frame simply continues with data after the 2 address bytes For the master to read from a slave it needs to reverse the data direction after the second address byte This is done by sending a Repeated Start followed by a repeat of the same standard 7 bit address with a Read bit The slave must remember that it had been addressed by the previous write operation and stay selected
526. terrupt falling edge register 0 Table 101 IST R W 0x024 Pin interrupt status register 0 Table 102 PMCTRL R W 0x028 Pattern match interrupt control register 0 Table 103 PMSRC R W 0x02C Pattern match interrupt bit slice source 0 Table 104 register PMCFG R W 0x030 Pattern match interrupt bit slice 0 Table 105 configuration register Pin interrupt mode register For each of the 8 pin interrupts selected in the PINTSELn registers see Section 4 6 27 one bit in the ISEL register determines whether the interrupt is edge or level sensitive Table 93 Pin interrupt mode register ISEL address 0xA000 4000 bit description Bit Symbol Description 7 0 PMODE Selects the interrupt mode for each pin interrupt Bit Reserved configures the pin interrupt selected in PINTSELn 0 Edge sensitive 1 Level sensitive Reset Access value 0 R W All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 102 of 370 NXP Semiconductors U M1 0601 UM10601 8 6 2 8 6 3 8 6 4 Chapter 8 LPC81x Pin interrupts pattern match engine Pin interrupt level or rising edge interrupt enable register For each of the 8 pin interrupts selected in the PINTSELn registers see Section 4 6 27 one bit in the IENR register enables the interrupt depending on the pin interrupt mode configured in the ISEL register e Ifthe pin int
527. that the interrupt is pending Table 7 Interrupt set pending register 0 register ISPRO address 0xE000 E200 bit description Bit Symbol Description Reset value 0 ISP_SPIO Interrupt pending set 0 1 ISP_SPI1 Interrupt pending set 0 2 Reserved All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 17 of 370 NXP Semiconductors UM10601 UM10601 3 4 4 Chapter 3 LPC81x Nested Vectored Interrupt Controller NVIC Table 7 Interrupt set pending register 0 register ISPRO address 0xE000 E200 bit description continued Bit Symbol Description Reset value 3 ISP UARTO Interrupt pending set 0 4 ISP UART1 Interrupt pending set 0 5 ICE UART2 Interrupt pending set 0 6 Reserved 7 Reserved 8 ISP I2C Interrupt pending set 0 9 ISP SCT Interrupt pending set 0 10 ISP MRT Interrupt pending set 0 11 ISP CMP Interrupt pending set 0 12 ISP WDT Interrupt pending set 0 13 ISP BOD Interrupt pending set 0 14 ISP FLASH Interrupt pending set 0 15 ISP WKT Interrupt pending set 0 23 16 Reserved 24 ISP_PININTO Interrupt pending set 0 25 ISP_PININT1 Interrupt pending set 0 26 ISP_PININT2 Interrupt pending set 0 27 ISP_PININT3 Interrupt pending set 0 28 ISP_PININT4 Interrupt pending set 0 29 ISP_PININT5 Interrupt pending set 0 30 ISP_PININT6 Interrupt pending set 0 31 ISP_PININT7 Interrupt p
528. the SETCLR1 field 0 2 Clear output or set based the SETCLR1 field 0x3 Toggle output UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 147 of 370 NXP Semiconductors U M1 0601 10 6 14 10 6 15 10 6 16 UM10601 Chapter 10 LPC81x SCTimer PWM SCT Table 133 SCT conflict resolution register RES address 0x5000 4058 bit description Bit Symbol Value Description Reset value 5 4 O2RES Effect of simultaneous set and clear on output 2 0 0x0 No change 0 1 Set output or clear based on the SETCLR2 field 0x2 Clear output n or set based on the SETCLR2 field 0x3 Toggle output 7 6 O3RES Effect of simultaneous set and clear on output 3 0 0x0 No change 0 1 Set output or clear based on the SETCLR3 field 0 2 Clear output or set based on the SETCLR3 field 0x3 Toggle output 31 8 Reserved SCT flag enable register This register enables flags to request an interrupt if the FLAGn bit in the SCT event flag register Section 10 6 15 is also set Table 134 SCT flag enable register EVEN address 0x5000 40F0 bit description Bit Symbol Description Reset value 5 0 IEN The SCT requests an interrupt when bit n of this register and the 0 event flag register are both one event 0 bit 0 event 1 bit 1 event 5 bit 5 31 6 Reserved SCT event flag register This regist
529. the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0 4 High level Match for this bit slice occurs when there is a high level on the input specified for this bit slice in the PMSRC register 0 5 Low level Match occurs when there is a low level on the specified input Ox6 Constant 0 This bit slice never contributes to a match should be used to disable any unused bit slices 0 7 Event Non sticky rising or falling edge Match occurs an event i e when either a rising or falling edge is first detected on the specified input this is a non sticky version of value 0x3 This bit is cleared after one clock cycle 25 23 CFG5 Specifies the match contribution condition for bit slice 5 0b000 0x0 Constant HIGH This bit slice always contributes to a product term match 0 1 Sticky rising edge Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0 2 Sticky falling edge Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0x3 Sticky rising or falling edge Match occurs if either a rising or falling edge on the specified input has occurre
530. this chapter The debug functionality is identical for all LPC81x parts 26 2 Features Supports ARM Serial Wire Debug mode Direct debug access to all memories registers and peripherals No target resources are required for the debugging session Four breakpoints Two data watchpoints that can also be used as triggers Supports JTAG boundary scan Micro Trace Buffer MTB supported 26 3 General description Debug functions are integrated into the ARM Cortex M0 Serial wire debug functions are supported The ARM Cortex M0 is configured to support up to four breakpoints and two watchpoints Support for boundary scan and Micro Trace Buffer is available 26 4 Pin description The SWD functions are assigned to pins through the switch matrix The SWD functions are fixed pin functions that are enabled through the switch matrix and can only be assigned to special pins on the package The SWD functions are enabled by default See Section 9 3 2 to enable the analog comparator inputs and the reference voltage input Table 303 SWD pin description Function Type Pin Description SWM register Reference SWCLK SWCLK PIOO 3 Serial Wire Clock This pin is the clock for SWD PINENABLEO Table 118 TCLK debug logic when in the Serial Wire Debug mode SWD This pin is pulled up internally SWDIO SWDIO PIOO 2 Serial wire debug data input output The SWDIO 118 TM
531. tion This could be an indication of a baud rate or configuration mismatch with the transmitting source All information provided in this document is subject to legal disclaimers Reset Access value RO RO RO RO RO W1 RO NA W1 NA RO W1 W1 W1 NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 197 of 370 NXP Semiconductors U M1 0601 Chapter 15 LPC81x USARTO 1 2 Table 175 USART Status register STAT address 0x4006 4008 USARTO 0x4006 8008 USART1 0x4006 C008 USART2 bit description Bit Symbol 14 PARITYERRINT 15 RXNOISEINT 31 16 Description Reset Access value 1 Parity Error interrupt flag This flag is set when a parity error is detected ina 0 W1 received character Received Noise interrupt flag Three samples of received data are taken in 0 W1 order to determine the value of each received data bit except in synchronous mode This acts as a noise filter if one sample disagrees This flag is set when a received data bit contains one disagreeing sample This could indicate line noise a baud rate or character format mismatch or loss of synchronization during data reception Reserved Read value is undefined only zero should be written NA NA 1 RO Read only W1 write 1 to clear 15 6 4 USART Interrupt Enable read and set register UM10601 The INTENSET register is used to enable various USART interrupt source
532. tion Reset Access value Master Start Stop Error flag This flag can be cleared by software 0 W1 0x0 0x1 0x2 0x3 0x0 0x1 0x2 0x3 writing a 1 to this bit It is also cleared automatically a 1 is written to MstContinue No Start Stop Error has occurred Start stop error has occurred The Master function has experienced a Start Stop Error A Start or Stop was detected at a time when it is not allowed by the 12C specification The Master interface has stopped driving the bus and gone to an idle state no action is required A request for a Start could be made or software could attempt to insure that the bus has not stalled Reserved Read value is undefined only zero should be written NA NA Slave Pending Indicates that the Slave function is waiting to continue 0 RO communication on the l2C bus and needs software service This flag will cause an interrupt when set if enabled via INTENSET The SLVPENDING flag is read only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SL VCTL register In progress The Slave function does not currently need service Pending The Slave function needs service Information on what is needed can be found in the adjacent SLVSTATE field Slave State code Each value of this field indicates a specific required 0 RO service for the Slave function All other values are reserved Slave address Address plus R W received At least one of the four slave addresses
533. tion to provide a flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via UART Caution If CRP3 is selected no future factory testing can be performed on the device UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 278 of 370 NXP Semiconductors UM10601 UM10601 22 4 3 1 Chapter 22 LPC81x Flash ISP and IAP programming Table 236 Code Read Protection hardware software interaction CRP option None None None CRP1 CRP1 CRP2 CRP2 CRP3 CRP1 CRP2 CRP3 User Code Valid at reset No x Yes Yes High Yes Yes Low Yes Yes High No Yes Low No Yes High No Yes Low No Yes x No No x No No x No No x No ISP entry pin SWD enabled Part enters ISP mode Yes No Yes No Yes No Yes No Yes Yes Yes partial flash update in ISP mode Yes NA Yes NA Yes NA No NA Yes No No Table 237 ISP commands allowed for different CRP levels ISP command Unlock Set Baud Rate Echo Write to RAM Read Memory Prepare sector s for write operation Copy RAM to flash Go Erase sector s Blank check sector s Read Part ID Read Boot code version Compare ReadUID CRP1 yes yes yes yes above 0x1000 0300 only no yes yes not to sector 0 no yes sector 0 can only be erased when all sectors are erased no
534. tors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether the Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products
535. type Input parameter Return Description I2C Master Receive Polling ErrorCode_t i2c master receive poll IBC HANDLE T Il2C I2C RESULT I2C HANDLE T Handle to the allocated SRAM area I2C Pointer to the I2C PARAM struct I2C RESULT Pointer to the 12C RESULT struct ErrorCode Receives bytes from slave and put into receive buffer The slave address with the R W bit 20 is expected in the first byte of the send buffer After the task is finished the slave address with the R W bit 1 is in the first byte of the receive buffer STOP condition is sent at end unless stop flag 0 When the task is completed the function returns to the line after the call I2C Master Transmit and Receive Polling Table 276 12C Master Transmit and Receive Polling Routine Prototype Input parameter Return Description I2C Master Transmit and Receive Polling ErrorCode ti2c master tx rx poll Il2C HANDLE 126 I2C RESULT I2C HANDLE T Handle to the allocated SRAM area I2C Pointer to the I2C PARAM struct I2C RESULT Pointer to the 12C RESULT struct ErrorCode First transmit bytes in the send buffer to a slave and seconaly receives bytes from slave and store it in the receive buffer The slave address with the R W bit 0 is expected in the first byte of the send buffer After the task is finished the slave address with the R W bit 1 is in the first
536. uctors U M1 0601 UM10601 10 7 6 10 7 7 Chapter 10 LPC81x SCTimer PWM SCT If an event increments the state number beyond the number of available states the SCT enters a locked state in which all further events are ignored while the counter is still running Software must interfere to change out of this state Software can capture the counter value and potentially create an interrupt and write to all outputs when the event moving the SCT into a locked state occurs Later while the SCT is in the locked state software can read the counter again to record the time passed since the locking event and can also read the state variable to obtain the current state number If the SCT registers an event that forces an abort putting the SCT in a locked state can be a safe way to record the time that has passed since the abort event while no new events are allowed to occur Since multiple states any state number between the maximum implemented state and 31 are locked states multiple abort or error events can be defined each incrementing the state number by a different value Interrupt generation The SCT generates one interrupt to the NVIC Events gt Enable Flags t 1 t register EM SCT interrupt NoChange Conflict Conflict Conflict events Flags Enable register register Fig 21 SCT interrupt generation Clearing the pr
537. ue down to zero generates an interrupt and or a wake up request and then turns itself off until re launched by a subsequent software write WKT clock sources The self wake up timer can be clocked from two alternative clock sources A 750 kHz clock derived from the IRC oscillator This is the default clock All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 180 of 370 NXP Semiconductors U M1 0601 Chapter 13 LPC81x Self wake up timer WKT A10 kHz low power clock with a dedicated on chip oscillator as clock source The IRC derived clock is much more accurate than the alternative low power clock However the IRC is not available in most low power modes This clock must not be selected when the timer is being used to wake up from a power mode where the IRC is disabled The alternative clock source is a nominally 10 kHz low power clock sourced from a dedicated oscillator This oscillator resides in the always on voltage domain so it can be programmed to continue operating in Deep power down mode when power is removed from the rest of the part This clock is also be available during other low power modes when the IRC clock is shut down The Low Power oscillator is not accurate approximately 40 96 over process and temperature The frequency may still drift while counting is in progress due to reduced chip temperat
538. ult of the IAP command is returned in the result table pointed to by register r1 The user can reuse the command table for result by passing the same pointer in registers rO and r1 The parameter table should be big enough to hold all the results in case the number of results are more than number of parameters Parameter passing is illustrated in the Figure 45 The number of parameters and results vary according to the IAP command The maximum number of parameters is 5 passed to the Copy RAM to FLASH command The maximum number of results is 4 returned by the ReadUID command The command handler sends the status code INVALID COMMAND when an undefined command is received The IAP routine resides at Ox1FFF 1FFO location and it is thumb code To call an IAP function do the following Define the IAP location entry point Since the Oth bit of the IAP location is set there will be a change to Thumb instruction set when the program counter branches to this address define IAP LOCATION Ox I ffflffl Define data structure or pointers to pass IAP command table and result table to the IAP function unsigned int command param 5 unsigned int status result 4 or All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 288 of 370 NXP Semiconductors U M1 0601 Chapter 22 LPC81x Flash ISP and IAP programming unsigned int command_pa
539. unter timer see Section 10 7 12 Configure the SCT To set up the SCT for multiple events and states perform the following configuration steps Configure the counter 1 Configure the L and H counters in the CONFIG register by selecting two independent 16 bit counters L counter and H counter or one combined 32 bit counter in the UNIFY field 2 Select the SCT clock source in the CONFIG register fields CLKMODE and CLKSEL from any of the inputs or an internal clock Configure the match and capture registers 1 Select how many match and capture registers the application uses total of up to 5 Inthe REGMODE register select for each of the 5 match capture register pairs whether the register is used as a match register or capture register 2 Define match conditions for each match register selected Each match register MATCH sets one match value if a 32 bit counter is used or two match values if the L and H 16 bit counters are used Each match reload register MATCHRELOAD sets a reload value that is loaded into the match register when the counter reaches a limit condition or the value All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 158 of 370 NXP Semiconductors UM10601 Chapter 10 LPC81x SCTimer PWM SCT 10 7 10 3 Configure events and event responses 1 Define when each event can occu
540. upt will be generated if a receiver overrun occurs 3 TXUREN Determines whether an interrupt occurs when a transmitter underrun occurs This 0 happens in slave mode when there is a need to transmit data when none is available 0 No interrupt will be generated when the transmitter underruns An interrupt will be generated if the transmitter underruns UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 240 of 370 NXP Semiconductors U M1 0601 Chapter 17 LPC81x SPIO 1 Table 207 SPI Interrupt Enable read and Set register INTENSET addresses 0 4005 800C SPIO 0x4005 C00C SPI1 bit description Bit Symbol Value Description Reset value 4 SSAEN Determines whether an interrupt occurs when the Slave Select is asserted 0 0 No interrupt will be generated when any Slave Select transitions from deasserted to asserted 1 An interrupt will be generated when any Slave Select transitions from deasserted to asserted 5 SSDEN Determines whether an interrupt occurs when the Slave Select is deasserted 0 0 No interrupt will be generated when all asserted Slave Selects transition to deasserted An interrupt will be generated when all asserted Slave Selects transition to deasserted 31 6 Reserved Read value is undefined only zero should be written NA UM10601 All information provided in this document is subject to legal disclai
541. ure after a low power mode is entered 13 6 Register description 13 6 1 Table 163 Register overview WKT base address 0x4000 8000 Name Access Address Description Reset Reference offset value CTRL R W 0x0 Self wake up timer control register 0 Table 164 COUNT R W OxC Counter register Table 165 Control register The WKT interrupt must be enabled in the NVIC to wake up the part using the self wake up counter Table 164 Conirol register CTRL address 0x4000 8000 bit description Bit Symbol 0 CLKSEL 1 ALARMFLAG UM10601 Value Description Reset value Select the self wake up timer clock source 0 Divided IRC clock This clock runs at 750 kHz and provides time out periods of up to approximately 95 minutes in 1 33 us increments Remark This clock is not available in not available in Deep sleep power down deep power down modes Do not select this option if the timer is to be used to wake up from one of these modes Low power clock This is the nominally 10 kHz clock and provides time out periods of up to approximately 119 hours in 100 us increments The accuracy of this clock is limited to 40 over temperature and processing Remark This clock is available in all power modes Prior to use the low power oscillator must be enabled The oscillator must also be set to remain active in Deep power down if needed Wake up or alarm timer flag No time out The self wake up timer has not timed out
542. us mode Send and receive multiple characters line in asynchronous or synchronous UART mode 25 3 General description The UART API handles sending and receiving characters using any of the USART blocks in asynchronous mode Remark Because all USARTS share a common fractional divider the uart init routine returns the value for the common divider UART driver routines function table uart get mem size Ptr to ROM Driver table Ox1FFF 1FF8 uart isr ROM Driver Table Ptr to Device Table 0 Ptr to Device Table 1 Ptr to Device Table 2 Ptr to Device Table 3 0x04 0x08 0 0 0 10 Ptr to Device Table 4 Ptr to UART driver routines Ptr to Device Table Fig 51 USART driver routines pointer structure 0x14 0x24 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 322 of 370 NXP Semiconductors U M1 0601 Chapter 25 LPC81x USART API ROM driver routines 25 4 API description The UART API contains functions to send and receive characters via any of the USART blocks Table 293 UART API calls API call Description Reference uint32_t ramsize_in_bytes uart_get_mem_size void UART get memory size Table 294 UART HANDLE T uart setup uint32 t base addr uint8 t ram UART set up Table 295 uint32 t uart ini UART HANDLE T
543. used to disable any unused bit slices 0 7 Event Non sticky rising or falling edge Match occurs an event i e when either a rising or falling edge is first detected on the specified input this is a non sticky version of value 0x3 This bit is cleared after one clock cycle UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 114 of 370 NXP Semiconductors U M1 0601 Chapter 8 LPC81x Pin interrupts pattern match engine Table 105 Pattern match bit slice configuration register PMCFG address 0xA000 4030 bit description continued Bit Symbol Value Description Reset value 22 20 CFG4 Specifies the match contribution condition for bit slice 4 0b000 0x0 Constant HIGH This bit slice always contributes to a product term match 0 1 Sticky rising edge Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0 2 Sticky falling edge Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared This bit is only cleared when the PMCFG or the PMSRC registers are written to 0x3 Sticky rising or falling edge Match occurs if either a rising or falling edge on the specified input has occurred since
544. ut filter 0 1 1 clock cycle Input pulses shorter than one filter clock are rejected 0 2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 1543 CLK_DIV Select peripheral clock divider for input filter sampling clock 0 Value 0 7 is reserved 0 0 IOCONCLKDIVO 0 1 IOCONCLKDIV1 0 2 IOCONCLKDIV2 0x3 IOCONCLKDIV3 0 4 IOCONCLKDIVA 0x5 IOCONCLKDIV5 0 6 IOCONCLKDIVE6 31 16 Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 84 of 370 NXP Semiconductors UM10601 6 5 14 8 register Chapter 6 LPC81x I O configuration IOCON Table 75 PIOO_8 register PIOO 8 address 0x4004 4038 bit description Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor 0b10 control 0x0 Inactive no pull down pull up resistor enabled 0 1 Pull down resistor enabled 0 2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 5 Reserved 0b001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled Remark This is n
545. ut not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 5 Reserved 0b001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled Remark This is not a true open drain mode 12 11 5 MODE Digital filter sample mode 0 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than one filter clock are rejected 0 2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 1543 CLK_DIV Select peripheral clock divider for input filter sampling clock 0 Value 0 7 is reserved 0 0 IOCONCLKDIVO 0 1 IOCONCLKDIV1 0 2 IOCONCLKDIV2 0x3 IOCONCLKDIV3 0x4 IOCONCLKDIVA 0x5 IOCONCLKDIV5 0 6 IOCONCLKDIVE6 31 16 Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 88 of 370 NXP Semiconductors UM10601 6 5 18 PIOO 14 register Chapter 6 LPC81x I O configuration IOCON Table 79 PIOO 14 register PIOO 14 address 0x4004 4048 bit description Bit Symbol Value Description Reset value 2 0 Reserved 0 4 3 MODE Selects function mode on chip pull up pull down resistor 0b10 control 0x0 Inactive no pull down pull up resistor enabled 0 1 Pull down resistor enabled 0 2 Pull up resistor enabled 0x3 Re
546. ve mode set up address packing size in bytes LPC I2CD API i2c get mem size i2c handle LPC I2CD API i2c setup LPC I2C BASE uint32 t amp I2C Handle 0 error code LPC I2CD API i2c set bitrate I2C HANDLE T i2c handle PCLK in Hz bps in hz error code LPC I2CD API i2Cc set slave addr I2C HANDLE T i2c handle slave slave addr mask 12C Master Transmit Receive The Master mode drivers give the user the choice of either polled wait for the message to finish or interrupt driven routines non blocking Polled routines are recommended for testing purposes or very simple 12C applications These routines allow the Master to send to Slaves with 7 bit or 10 bit addresses The following routines are polled routines err code i2c master transmit poll I2C HANDLE T I2C PARAM I2C RESULT err code i2c master receive poll I2C HANDLE T I2C PARAM I2C_RESULT err code i2c master tx rx poll I2C HANDLE T I2C PARAM I2C RESULT The following routines are interrupt driven routines err code i2c master transmit intr I2C HANDLE T I2C PARAM I2C RESULT err code i2c master receive intr I2C HANDLE T I2C PARAM I2C RESULT err code i2c master tx rx intr I2C HANDLE T I2C_PARAM I2C RESULT Where err code is the return state of the function An 0 indicates success All non zero indicates an error Refer to Error Table e 2C PARM is a structure w
547. ved 0x02C Reserved SYSRSTSTAT R W 0x030 System reset status register 0 Table 24 SYSPLLCLKSEL R W 0x040 System PLL clock source select 0 Table 25 SYSPLLCLKUEN R W 0x044 System PLL clock source update enable 0 Table 26 MAINCLKSEL R W 0x070 Main clock source select 0 Table 27 MAINCLKUEN R W 0x074 Main clock source update enable 0 Table 28 SYSAHBCLKDIV R W 0x078 System clock divider 1 Table 29 SYSAHBCLKCTRL R W 0x080 System clock control OxDF Table 30 UARTCLKDIV R W 0x094 USART clock divider 0 Table 31 0x098 Reserved UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 27 of 370 NXP Semiconductors UM10601 Chapter 4 LPC81x System configuration SYSCON Table 17 Register overview System configuration base address 0x4004 8000 continued Name Access Offset Description Reset value Reference 0x09C Reserved Reserved 0x0BC 0x0CC Reserved CLKOUTSEL R W OxOEO CLKOUT clock source select 0 Table 32 CLKOUTUEN R W Ox0E4 CLKOUT clock source update enable 0 Table 33 CLKOUTDIV R W OxOE8 CLKOUT clock divider 0 Table 34 UARTFRGDIV R W Ox0FO USART1 to USART4 common fractional 0 Table 35 generator divider value UARTFRGMULT R W Ox0F4 USART1 to USART4 common fractional 0 Table 36 generator multiplier value EXTTRACECMD R W OxOFC External trace buffer command register 0
548. ved 0 0 IOCONCLKDIVO 0 1 IOCONCLKDIV1 0 2 IOCONCLKDIV2 0x3 IOCONCLKDIV3 0x4 IOCONCLKDIVA 0x5 IOCONCLKDIV5 0 6 IOCONCLKDIVE6 31 16 Reserved 0 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 78 of 370 NXP Semiconductors UM10601 6 5 8 PIOO 11 register Chapter 6 LPC81x I O configuration IOCON Table 69 11 register PIOO 11 address 0x4004 401C bit description Bit Symbol Value Description Reset value 5 0 Reserved 0 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin 9 8 I2CMODE reads as 0 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 Reserved 1 Selects 12C mode 00 Select Standard mode I2ZCMODE 00 default or Standard I O functionality I PCMODE 01 if the pin function is GPIO FUNC 000 0x0 Standard mode Fast mode 12C 0x1 Standard I O functionality 0 2 Fast mode Plus 12C 0x3 Reserved 10 Reserved 12 11 5 MODE Digital filter sample mode 0 0x0 Bypass input filter 0 1 1 clock cycle Input pulses shorter than one filter clock are rejected 0 2 2 clock cycles Input pulses shorter than two filter clocks are rejected 0x3 3 clock cycles Input pulses shorter than three filter clocks are rejected 15 13 CLK_DIV Select peripheral clock divider for input filter sampling 0 clock Value 0x7 is res
549. ven whenever the Master bit in the CFG register equals 1 regardless of the state of the Enable bit Master In Slave Out The MISO signal transfers serial data from the slave to the master When the SPI is a master serial data is input from this signal When the SPI is a slave serial data is output to this signal MISO is driven when the SPI block is enabled the Master bit in the CFG register equals 0 and when the slave is selected by one or more SSEL signals Slave Select When the SPI interface is a master it will drive the SSEL signals to an active state before the start of serial data and then release them to an inactive state after the serial data has been sent By default this signal is active low but can be selected to operate as active high When the SPI is a slave any SSEL in an active state indicates that this slave is being addressed The SSEL pin is driven whenever the Master bit in the CFG register equals 1 regardless of the state of the Enable bit Serial Clock Master Out Slave In Master In Slave Out Slave Select SWM register PINASSIGN3 PINASSIGN4 PINASSIGN4 PINASSIGN4 PINASSIGN4 PINASSIGN5 PINASSIGN5 PINASSIGN5 Reference Table 112 Table 113 Table 113 Table 113 Table 113 Table 114 Table 114 Table 114 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014
550. vent 0 is enabled in state 0 Set STATEMSK1 bit 0 to 1 Set all other bits to 0 Event 1 is enabled in state 0 Set STATEMSK2 bit 0 to 1 Set all other bits to 0 Event 2 is enabled in state 0 Set STATEMSK3 bit 1 to 1 Set all other bits to 0 Event 3 is enabled in state 1 Set STATEMSKA bit 1 to 1 Set all other bits to 0 Event 4 is enabled in state 1 Set STATEMSK 5 bit 1 to 1 Set all other bits to 0 Event 5 is enabled in state 1 UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 163 of 370 UM10601 Chapter 11 LPC81x Multi Rate Timer MRT Rev 1 6 2 April 2014 User manual 11 1 How to read this chapter The MRT is available on all LPC81x parts 11 2 Features 31 bit interrupt timer Four channels independently counting down from individually set values Repeat and one shot interrupt modes 11 3 Basic configuration Configure the MRT using the following registers Inthe SYSAHBCLKCTRL register set bit 10 Table 30 to enable the clock to the register interface Clear the MRT reset using the PRESETCTRL register Table 19 The global MRT interrupt is connected to interrupt 10 in the NVIC 11 4 Pin description The MRT has no configurable pins 11 5 General description The Multi Rate Timer MRT provides a repetitive interrupt timer with four channels Ea
551. wered in PDSLEEPCFG register Enable reset in BODCTRL register BOD powered in PDSLEEPCFG register Enable interrupt in NVIC and STARTERP registers WWDT running Enable WWDT in WWDT MOD register and feed Enable interrupt in WWDT MOD register WDOsc powered in PDSLEEPCFG register WWDT running Enable reset in WWDT MOD register WDOsc powered in PDSLEEPCFG register Enable interrupt in NVIC and STARTERP registers Enable low power oscillator in the DPDCTRL register in the PCON block Select low power clock for WKT clock in the WKT CTRL register Start the WKT by writing a time out value to the WKT COUNT register Enable interrupt in NVIC and STARTERP 1 registers Enable USART I2C SPI interrupts Provide an external clock signal to the peripheral Configure the USART in synchronous slave mode and I2C and SPI in slave mode Deep power down WAKEUP pin 4 Enable the WAKEUP function in the DPDCTRL register in the PMU WKT time out Enable the low power oscillator in the DPDCTRL register in the PMU Enable the low power oscillator to keep running in Deep power down mode in the DPDCTRL register in the PMU Select low power clock for WKT clock in the WKT CTRL register Start WKT by writing a time out value to the WKT COUNT register 5 6 Register description Table 55 Register overview PMU base address 0x4002 0000 Name PCON GPREGO GPREG1 UM10601 Access Address Description Reset Reference offset value R
552. west priority 21 16 These bits ignore writes and read as O 23 22 Reserved 29 24 These bits ignore writes and read as O 31 30 IP UARTO Interrupt Priority 0 highest priority 3 lowest priority Interrupt Priority Register 1 The IPR1 register controls the priority of four peripheral interrupts Each interrupt can have one of 4 priorities where 0 is the highest priority Table 11 Interrupt Priority Register 1 IPR1 address 0xE000 E404 bit description Bit Symbol Description 5 0 These bits ignore writes and read as O 7 6 IP_UART1 Interrupt Priority 0 highest priority 3 lowest priority 13 8 These bits ignore writes and read as O 15 14 IP UART2 Interrupt Priority O highest priority 3 lowest priority All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 20 of 370 NXP Semiconductors U M1 0601 3 4 8 3 4 9 UM10601 Chapter 3 LPC81x Nested Vectored Interrupt Controller NVIC Table 11 Interrupt Priority Register 1 IPR1 address 0xE000 E404 bit description Bit Symbol Description 21 16 These bits ignore writes and read as 0 23 22 Reserved 29 24 These bits ignore writes and read as 0 31 30 Reserved Interrupt Priority Register 2 The IPR2 register controls the priority of four peripheral interrupts Each interrupt can have one of 4 priorities w
553. when the internal clocks are shut down in Deep sleep and Power down modes For details see the following registers Section 4 6 32 Power configuration register Section 4 6 29 Start logic 1 interrupt wake up enable register 4 5 4 Reset and interrupt control The peripheral reset control register in the system control register allows to assert and release individual peripheral resets See Table 19 Up to eight external pin interrupts can be assigned to any digital pin in the system control block see Section 4 6 27 Pin interrupt select registers 4 6 Register description All system control block registers reside on word address boundaries Details of the registers appear in the description of each function Reset values describe the content of the registers after the boot loader has executed All address offsets not shown in Table 17 are reserved and should not be written to Table 17 Register overview System configuration base address 0x4004 8000 Name Access Offset Description Reset value Reference SYSMEMREMAP RAN 0x000 System memory remap 0x2 Table 18 PRESETCTRL RAN 0x004 Peripheral reset control 0x0000 1FFF 19 SYSPLLCTRL R W 0x008 System PLL control 0 Table 20 SYSPLLSTAT R 0x00C System PLL status 0 Table 21 0x010 Reserved F 0x014 Reserved SYSOSCCTRL R W 0x020 System oscillator control 0x000 Table 22 WDTOSCCTRL R W 0x024 Watchdog oscillator control 0 0 Table 23 0 028 Reser
554. will cause a watchdog reset and set the WDTOF flag Table 158 Watchdog Timer Constant register TC 0x4000 4004 bit description Bit Symbol Description Reset Value 23 0 COUNT Watchdog time out value 0x00 OOFF 31 24 Reserved user software should not write ones to reserved bits The NA value read from a reserved bit is not defined Watchdog Feed register Writing OxAA followed by 0x55 to this register will reload the Watchdog timer with the WDTC value This operation will also start the Watchdog if it is enabled via the WDMOD register Setting the WDEN bit in the WDMOD register is not sufficient to enable the Watchdog A valid feed sequence must be completed after setting WDEN before the Watchdog is capable of generating a reset Until then the Watchdog will ignore feed errors After writing OxAA to WDFEED access to any Watchdog register other than writing 0x55 to WDFEED causes an immediate reset interrupt when the Watchdog is enabled and sets the WDTOF flag The reset will be generated during the second PCLK following an incorrect access to a Watchdog register during a feed sequence It is good practice to disable interrupts around a feed sequence if the application is such that an interrupt might result in rescheduling processor control away from the current task in the middle of the feed and then lead to some other access to the WDT before control is returned to the interrupted task All information provided in this docu
555. y Check CRC generator with programmable polynomial settings supports several CRC standards commonly used UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 260 of 370 NXP Semiconductors UM10601 Chapter 19 LPC81x Cyclic Redundancy Check CRC engine CRC MODE CRC SEED sna BIT REVERSE BIT REVERSE CRC SUM Fig 42 CRC block diagram UM10601 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 261 of 370 NXP Semiconductors U M1 0601 Chapter 19 LPC81x Cyclic Redundancy Check CRC engine 19 6 Register description UM10601 19 6 1 19 6 2 19 6 3 Table 220 Register overview CRC engine base address 0x5000 0000 Name Access Address Description Reset value Reference offset MODE R W 0x000 CRC mode register 0x0000 0000 Table 221 SEED R W 0x004 CRC seed register 0x0000 FFFF Table 222 SUM RO 0x008 CRC checksum register 0x0000 FFFF Table 223 WR_DATA WO 0x008 CRC data register Table 224 CRC mode register Table 221 CRC mode register MODE address 0x5000 0000 bit description Bit Symbol Description Reset value 1 0 CRC_P
556. ymbol Description Reset Access value 7 0 PSTAT Pin interrupt status Bit n returns the status clears the edge 0 R W interrupt or inverts the active level of the pin selected in PINTSELn Read 0 interrupt is not being requested for this interrupt pin Write 0 no operation Read 1 interrupt is being requested for this interrupt pin Write 1 edge sensitive clear rising and falling edge detection for this pin Write 1 level sensitive switch the active level for this pin in the IENF register 31 8 Reserved Pattern Match Interrupt Control Register The pattern match control register contains one bit to select pattern match interrupt generation as opposed to pin interrupts which share the same interrupt request lines and another to enable the RXEV output to the cpu This register also allows the current state of any pattern matches to be read If the pattern match feature is not used either for interrupt generation or for RXEV assertion bits SEL PMATCH and ENA RXEV of this register should be left at O to conserve power All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 1 6 2 April 2014 106 of 370 NXP Semiconductors U M1 0601 8 6 12 Chapter 8 LPC81x Pin interrupts pattern match engine Remark Set up the pattern match configuration in the PMSRC and PMCFG registers before writing to this register to enable or re
557. ys clk in hz Sytem clock in hz uint32 t baudrate in hz Baudrate in hz uint8 t config bit 1 0 00 7 bits length 01 8 bits lenght others reserved I 00 No Parity 01 reserved 10 Even 11 Odd I 0 1 Stop bit 1 2 Stop bits uint8 t sync mod bit0 O Async mode Sync mode 110101 0 Un is sampled on the falling edge of SCLK Il 1 Un_RXD is sampled on the rising edge of SCLK 110102 O Start and stop bits are transmitted as in asynchronous mode 1 1 Start and stop bits are not transmitted bit3 O the UART is a slave on Sync mode 1 1 UART is a master on Sync mode uintl6 t error en Bit0 OverrunEn bitl UnderrunEn bit2 FrameErrEn I bit3 ParityErrEn bit4 RxNoiseEn The handle to the instance of the UART driver Each UART has one handle so there can be several handles for up to three UART blocks This handle is created by Init API and used by the transfer functions for the corresponding UART block typedef void UART PARAM T UART HANDLE T define TYPE for uart handle pointer typedef struct uart_A parms passed to uart driver function uint8 t buffer The pointer of buffer For uart get line function buffer for receiving data For uart put line function buffer for transmitting data IN The size of buffer The number of bytes transmitted received transfer mode 0x00 For uart get line function transfer without ter

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