Motorola Digital Signal Processors
Contents
1. 12 202 212 22 2 2 222022202202 2020202022202 2 22 2 2 k k RO 000001 51 52 0110 8A0000 loopl move 53 P 0111 08068 add 54 55 P 0112 200045 emp 56 0113 OBFOA2 jsne 00011D 57 P 0115 200055 cmp 58 0116 OBFOA2 jsne 59 0118 21AE00 move 60 P 0119 200003 tst 61 P 011A OBFOAA jseq 62 011 0 0110 jmp 63 64 65 X ERR 66 P 011D 638000 move 67 P 011E 000000 nop 68 P 011F 205800 move 69 P 0120 630000 move 70 P 0121 00000C rts ga 72 73 Y_ERR 74 P 0122 6B8000 move 75 20123 000000 nop 76 P 0124 205B00 move 77 P 0125 6B0000 move 78 0126 00000C rts 79 80 8h COUNT 82 P 0127 6B8100 move 83 P 0128 000000 nop 84 P 0129 205B00 move 85 P 012A 6B0100 move 86 012 00000C rts 87 88 END 0 Errors 0 Warnings pass counter Ye 1 3 r3yY 1l Figure 1 6 PSRAM Interface Initialization Code shee MOTOROLA SECTION 2 A Simple Dynamic RAM Interface for the DSP56001 The high Many DSP applications such as audio special ef density of DRAM fects require large amounts of memory If the system results from the _throughputcan tolerate a slight reduction in memory simplicity of the access speed significant cost reductions can be real storage cells using dynamic RAM DRAM in place of static each cell RAM SRAM This section presents a simple imple consists ofa mentation of a DRAM interface to the D2. Refer to the data sheets specific to the PSRAMs selected particular application gn Figure 1 1 Pseudo Static RAM Auto Refresh Timing in which 2 rows are re freshed in succession Note that either E1 or E2 can disable the device Please refer to the data sheets specific to the PSRAMs selected for any particular application MOTOROLA 1 3 1 1 DSP56001 Memory I O Basics Memory interface to the DSP56001 occurs over Port A of the processor Port A consists of 24 bi directional data lines 00 023 16 address lines A0 A15 three memory reference lines PS DS X Y and two data strobes RD WR Additionally a pair of bus access control signals Bus Request Bus Grant BR BG can be used to synchronize access requests between the processor and another device attempting to gain mastership of the bus The bus access pins have al ternate functions Bus Strobe Wait BS WT which allow external circuitry to insert additional wait states in external bus cycles To minimize power consump tion the address lines remain stable until the beginning of the next external access The memory reference signals PS DS and X Y are deasserted during periods when the external bus is idle but are not deasserted during successive accesses to the same external memory space Setting bit 7 of the processor s Operating Mode Reg ister OMR causes the bus access control bits to assume the Bus Strobe Wait
3. quick and dirty test of B SRAM prototype board 8 9 This code configures the SCI SCLK eutput to generate the P SRAM 20 refresh timing An incrementing pattern is written to the device 21 at X 1000 and Y 1000 and then fthese locations are read and compared 22 with the expected data If an error detected an error counter 23 is incremented X 0000 holds the count of errors found while accessing 24 X memory and Y 0000 holds the Y memory error count 25 4 26 This quickie only tests the interface for data transfer and refresh 27 interference It does NOT ex reise the refresh logic functionality 28 29 At the end of each pass i e when the 24 bit pattern rolls over to 0 30 a pass counter is incremented This counter is at Y 0001 31 H 32 The pass counter and the error logs are located in on chip RAM in order 33 to allow limited error analysis after any type of crash These 34 locations should be cleared before starting the test Subsequent 35 restarts can continu the logging without initializing these locations 36 2 37 P 0100 org P 100 38 39 0100 08F4BE movep 2200 X SFFFE 2 wait states in X Y 002200 40 0102 08 4 0 movep 44 0002 X FFFO 10 bit async mode00002 41 P 0104 08F4B2 movep 107F X EFF2 SCI internal CLK pinconfigured 00107F 42 ICM RCM 0 internal clock 43 SCLK output prescale 1 1 44 divide fosc by 4 12741 45 0106 08FA4Al movep 0004 X SFFE1 SCL
4. 0024 0025 0026 0027 0028 0029 0030 0031 0032 0033 0034 0035 0036 0037 0038 0039 004 004 004 004 004 004 004 004 004 004 0050 o 014 o module dram6 title Dynamic RAM Timing Controller Ver 2 06 September 1990 MOTOROLA INC 001 device P16R4 INPUTS CLK pin 1 DSP56001 Clock BS pin 3 BUS Strobe from DSP56001 Rreq pin 4 latched request for refresh cycle C Mux pin 6 H Column Mux Select 0 7 H Select Bank 0 Xsel pin 8 H Select X ram CSin pin 9 EXT RAM Address decode OE pin 1 OE OUTPUTS REGISTERED OUTPUTS 00 1 State bit 0 ol pin 6 State bit 1 RASM pin 5 State bit 2 also RASn Rrst pin 4 Refresh Request Reset COMBINATORIAL OUTPUTS Win pin 9 Bus Wait CASn pin 8 Column Address Strobe for DRAN A09 pin 2 DRAM address bit 9 High Low 1 0 H L C K X zo D C o Ria ga ug Ostate Rrst RASn Q1 Q0 Idle L l0540 Jj Rtime 1 0 0 0 Ctimel 105150 13 Ctime2 Prel 1 1 1 15 Pre2 1 1 0 I RF1 05150 0713 RF2 0 0 0 0 RF3 15 RFA 0 0 1 1 17 5 0 0 0 1 1 RP1 01 01 14 2 4 1 0 1 1 XX1 0 1 1 0 just in case it wakes up lost XX2 Orl iyi 17 XX3 1 0 0 1 15 sheet 1 of 2 Figure 2 6 PLD Design File generated by ABEL for the
5. 128K 24 bit words of data space With the DSP56001 operating from a 33MHz clock this mem ory subsystem will operate with 2 wait states for non consecutive accesses MOTOROLA 1 1 Pseudo Static RAM PSRAM combines the economies of DRAM with the straightforward interface of fully Static RAM to provide 128K bytes in a 32 pin DIP Internally the device contains a dy namic RAM array with on board address multiplexing an internal refresh row counter and an internal refresh timer The memory array is divided into eight sections each con sisting of a of 512 row x 256 column matrix of storage cells forming a byte wide memory which is 128K locations deep The device is pin compatible with the 128Kx8 SRAM JEDEC pinout with the exception of pin 1 on standard SRAMs this pin would be a no connect on PSRAM it is the re fresh strobe F These features enable the PSRAM to replace fully static RAM in many applications with a minimum amount of glue PSRAM has two complementary enable lines and E2 During read and write opera tions these enable lines must strobe the address into the device This is another difference between PSRAM and fully static RAM Since the PSRAM is based on DRAM storage elements it requires a precharge delay between successive accesses and a periodic refresh PSRAM supports three different re fresh modes CE only refresh auto refresh and self refresh CE only refresh requires external hardware
6. BS m x a 2 tc N tc a MC74AC74 LK Y 6 ADR MUX SELECT OCK 1 gt 2 3 gt MC74AC04 4 DSP56001 to DRAM Schematic provides 256k words of expansion memory tothe DSP56000 Application Development System 2 10 MOTOROLA 2 2 Circuit Description The DRAM interface example provides three dis tinct functions Memory Address Multiplexing Refresh Generation General Timing and Control As stated earlier DRAMs require input addresses to be subdivided into two groups row addresses and column addresses Referring to the schematic in Figure 2 4 two MC74AC157 s multiplex 16 bits of input address 8 of the DRAM s 9 address input pins The PAL16R4 7 multiplexes the Bank Select bit and X Y onto the 9th DRAM address input pin Together these 18 bits delineate two complete banks of data memory each containing 64K 24 bit words of memory and 64K 24 bit words of Y memory this example bit 0 of Port B drives the bank select signal BANKO Flip Flop A of the MC74AC74 generates a refresh request on the rising edge of SCLK and holds the request until the PAL16R4 7 controller executes a refresh cycle and then resets the Flip Flop As Shown in Figure 2 5 the controller defers a refresh cycle until any access currently in progress com pletes If the subsequent DSP56001 instruction cycle does not access this DRAM array this refresh i
7. BS WT mode In this mode the BS pin is asserted at the beginning of every external access and is released during T3 of each ex ternal cycle Assertion of the WT pin during T2 while BS is asserted adds wait states to the bus cycle Wait states will continue to be inserted until two falling edges of EXTAL occur in succession with the release of WT WT should never be asserted when BS is inactive 1 4 MOTOROLA When the DSP56001 is reading data from the bus the data must be stable for the specified setup and hold periods before and after respectively the rising edge of the read strobe RD During processor write opera tions to the external bus the data is valid for a specified time before and after the rising edge of the write strobe WR These relationships in are shown in the simplified PSRAM timing diagram of Figure 1 4 For DRAM tim ing see Figure 2 3 For more detailed information refer to the DSP56001 User s Manual and the DSP56001 Data Sheet 1 2 Memory Subsystem Overview The circuit in Figure 1 2 is designed to serve as an ex tension of the Motorola DSP56000 ADS Application Development Module ADM The Static RAM on the ADM should be configured to reside solely within the DSP56001 program space The PSRAMs and their interface circuitry are attached to the DSP56001 s Data and Address Buses via ADM connector J3 The PSRAM bank consists of three devices Each device provides 128K storage cells for each of
8. DRAM Ini 2 14 MOTOROLA ate diagram Qstate cate Idle CASn 1 WTn CSin if CSin if CSin amp if Rreq cate Rtime CASn 1 WTn amp BS BS amp Rreg THEN Idle 5 Rreq THEN Rtime THEN RF1 CSin amp BS goto Ctimel ate Ctimel CASn 0 WIn 1 goto Ctime2 cate Ctime2 CASn 0 WIn 1 goto Prel cate Prel CASn 1 WIn CSin amp BS goto Pre2 cate Pre2 CASn 1 WIn CSin amp BS goto Idle Refresh States cate RF1 CASn 0 WIn CSin amp BS gotofRF2 cate RF2 CASn 0 WIn CSin amp BS goto RES zate CASn 0 WIn CSin amp BS goto RF4 cate RF4 CASn 1 WIn CSin amp BS goto RF5 cate RFS CASn 1 WIn CSin amp BS goto RP1 cate RPl CASn 1 WIn CSin amp BS goto RP2 zate RP2 CASn 1 WIn CSin amp BS goto Idle cate XX1 goto Idle if lost go home PAL cate XX2 goto Idle cate XX3 goto Idle juations A09 BankO amp C Mux 4 Xsel amp C Mux YD 6 PLD Design File generated by ABEL for the DRAM Interface sheet 2 of 2 MOTOROLA 2 15 Motorola DSP56000 MacroCrossAssembleWVersion3 0290 09 0610 54 50dra 20 21 22 23 24 25 26 27 28 29 30 31 P2 e 34 88 36 37 38 39 40 41 42 43 44 45 page 255 66 3 3 5 SKK KKK k c
9. HEN 1 Ben 0 g goto Idle deassert HEN and quit 0074e State S5 goto Idle these are dummies just in case 0075e State 56 goto Idle 0076e State S7 goto Idle 0077e equations 0078e 02 01 00 ck CLK 0079e RESET CIK 0080e HRw ck CLK 0081e 0082e MODA RESET Q amp IRQA 0083e MODB RESET 0 amp IROB 0084e Test vectors 0085e CLK Addr IOW IOR IROB gt HRw RESET MODB 0086e C h34 0 1 0 1 gt 0 1 0 1 write to port sets write dir 0087e 74 0 1 0 1 gt 0 0 1 0 write to reset address asserts reset 0088e C h34 1 0 0 1 gt 1 0 1 0 read from normal address reset 0089e C h34 0 1 0 12 gt 0 1 0 1 write to normal address deasserts reset 0090e C h34 1 170 4 gt 0 1 0 1 0091e 7 34 1 11 gt 0 1 1 1 0092e Test_vectors 0093e CLK Addr IOW IOR gt HEN Ben HRw 0094e c h24 07 gt 201 this is NOT for wrong addr 0095e 34 0 0 gt 1 01 cycle starts addresses valid 0096e C h3g DE gt 1 01 0097 C n34 1 0 gt 1 113 read cycle identified by IOR T 0098e C h3451 0 gt 0 11 0099e C n34 1 0 gt 0 0 1 0100e C n34 1 0 gt 0 0 1 0101e h34 1 0 gt 0 0 1 0102e 7 h34 1 1 gt 0 11 010 C4 h34 1 1 gt 1 115 0104e C h34 0 1 gt 1 01 0105 0106 2 Figure 3 2 PLD Definition for the I
10. cmp y0 a now check Y data 1A 2 jsne ERR j and log differences000126 1 21AE00 move bl a this allows data to roll over 1D 200003 tst a check for start of new loop 1 OBFOAA jseq COUNT j and increment count if yes00012B 20 0C0114 jmp loopl kkk AK ke e ld e e e ke e e e x X ERR error handler for X memory 21 638000move X 0 r3 get last count from storage 22 000000nop P Can t use Wet 23 205B00move r3 bump count 24 630000move r3 X 0 save new count 25 00000Crts back to the salt mine aee c MP ke Y_ERR error handler for Y memory 26 6B8000move Y 0 r3 27 000000 28 205B00move r3 refer to X ERR for comments 29 6B0000move r3 Y 0 2A 00000Crts Fielat Sa COUNT pass counter 2B 6B8100move Y 1 r3 2C 000000nop 2D 205B00move 13 refer to X ERR for comments 2E 6B0100move r3 Y 1 2F 00000Crts END rs 7 DRAM Interface Initialization Code Sheet 2 of 2 MOTOROLA 2 17 The 8 registers which comprise the DSP56001 Host Interface are mapped into the ISA bus I O space Communications with the DSP56001 including program bootstrapping are accomplished via reads and writes to the appropriate register SECTION 3 A Simple ISA Bus Interface for the DSP56001 The Host Port ofthe DSP56001 provides much of the logic necessary for interfacing this device to an other processor With very litt
11. or software to provide periodic addressing of each of the 512 rows Use of this method would add a considerable amount of interface hardware or would cause significant degradation to software performance Self refresh can be entered after 8 ms in standby mode In this mode the on board refresh timer and refresh counter are used to provide the refresh sequencing A delay slightly greater than one access cycle is required when leaving this mode before data read write operations can proceed This mode is useful for long standby periods but is not suitable for device refresh during periods of normal DSP activity due to the unique timing requirements To use this mode during idle periods would require mode selection logic as well as the circuitry associated with one of the other active access modes 1 2 MOTOROLA e Auto refresh occurs when the PSRAM is disabled by either of the device select inputs going false followed the refresh pin F going active For each transition of F one row of each section is refreshed and the refresh row counter is advanced in preparation for the next refresh cycle The example presented in this note uses this mode because it requires the least amount of external logic and impacts the normal DSP software only when a data transfer contends with a refresh cycle Figure 1 1 depicts an auto refresh cycle in which two rows are refreshed in suc cession Note that either E1 or E2 can disable the device
12. single capacitor During write op erations the capacitor is either charged to the one state or discharged to the zero state The charge stored by the capacitor is quite small typical capaci tor values are on the order of 35 125 fF fF 1 x 10 lS farads Due to leakage the capacitor s charge must be periodically refreshed in order to retain the stored information The DRAM circuitry will refresh all of the cells within a row whenever the rowas addressed Thus by cycling through all 512 possible row address combinations the entire array is refreshed On the 514256 more than 8 ms is allowed to elapse between subsequent refreshes of any particular row This can be accomplished by refreshing suc cessive rows at 15 6 ms intervals 512 x 15 6ms 8 ms The MCM514256A supports three refresh modes RAS only refresh CAS before RAS refresh and Hidden Refresh Figure 2 2 RAS only refresh requires the processor to place successive row addresses on the address 2 2 MOTOROLA 2 3 MOTOROLA lines which would require either more complex interface circuitry or determin istic software action i e interrupts could not be allowed to delay the refresh cycle The Hidden Refresh mode has the disadvantage of maintaining output data on the DRAM data lines prohibiting any bus activity during the refresh cy cle CAS before RAS refresh utilizes an on chip refresh row counter and three states the device bus during the
13. 038 0039 0040 state_diagram Ostate 0041 State Idle Fn 1 CSout CSin WIn 1 0042 if Busy amp Rreq THEN I 0043 ELSE P 0044 State Prl Fn 1 CSout 1 WIn CSin goto P 0045 State Pr2 Fn 1 CSout 1 WIn CSin 0046 if Rreq THEN F 0047 ELSE R 0048 State RF3 Fn 0 CSout 1 WIn CSin goto R 0049 State RF4 Fn 0 CSout 1 WIn CSin goto R 0050 State 5 Fn 1 CSout 1 WIn CSin goto R 0051 State RF6 Fn 1 CSout 1 WIn CSin goto F 0052 State FIM Fn 1 CSout CSin WIn 1 goto I 0053 0054 END Figure 1 5 DSP56001 to PSRAM PLD Definition for the ABEL package which implements the state diagram in Figure 1 5 1 14 MOTOROLA Motorola DSP56000 Macro CrossAssemblerVersion3 0290 09 0615 06 48psram_ex asm Page 1 1 page 255 66 3 3 5 2 H KKK KKK KKK KKK KK KKK KKK KKK KKK KK KK KKK KK KK KKK KKK KK KK KR A 3 Motorola Austin DSP Operation July 17 1990 4 5 COPYRIGHT C BY MOTOROLA INC ALL RIGHTS RESERVED 6 7 ALTHOUGH THE INFORMATION CONTAINED HEREIN 8 AS WELL AS ANY INFORMATION PROVIDED RELATIVE 9 THERETO HAS BEEN CAREFULLY REVIEWED AND IS 0 ve BELIEVED ACCURATE MOTOROLA ASSUMES NO 11 LIABILITY ARISING OUT OF ITS APPLICATION OR 2 USE NEITHER DOES IT CONVEY ANY LICENSE UNDER 3 pe ITS PATENT RIGHTS NOR THE RIGHTS OTHERS e 4 2 5 6 psram ex asm pseudo static ram exerciser 7
14. 6001 P memory space All data memory X memory and Y memory is provided by the DRAMs on the prototype board The DRAMs and their interface circuitry are attached to the DSP56001 s Data and Address Buses via ADM connector J3 In order to minimize the component count the re fresh request timing is supplied by the SCI clock SCLK Initialization software configures this clock to provide a pulse train with a 15 us period Once initial ized the generation of this signal is completely transparentito any code executing on the DSP56001 Figure 2 7 is a listing of the initialization code and a short pass fail memory test routine The value load ed into the SCI Clock Control Register SCCR at X FFF2 will vary as a function of the system clock frequency For a 33 MHz clock a value of 107F yields the desired refresh rate of 15 6 us per row A second task of the initialization software is the selec tion of the BS WT mode of operation which allows an external source to insert wait states into bus cy cles The interface uses this feature when pre charge and refresh delays are needed The memory bank consists of six MCM514256A de vices Since each device provides 256K storage cells for each of the 4 data bits an array of 256K 24 bit MOTOROLA 2 7 words is formed The DSP56001 can address 64K 24 bit words in each of its two data spaces X mem ory and Y memory This DRAM array can fully populate two of these data spaces To utilize t
15. 8 data bits form ing an array of 128K 24 bit words The DSP56001 can address 64K 24 bit words in each of its two data spaces X memory and Y memory Therefore this PSRAM array fully populates both of the processor s data spaces MOTOROLA 1 5 1 6 MOTOROLA CTOR is J3 of DSP56000 ADM AD z ARA 3 128K x8 ADO7 PSEUDO STATIC ADO8 RAM MC74AC04 CLOCK 3 gt 4 PAL16R4 7 m REFRESH CYCLE STROBE REFRESH REQUEST MEMORY BUSY MC74AC74 SCLK 2 DSP56001 to PSRAM Schematic provides two functions it controls the refresh cycles and it generates precharge delays This is a schematic depiction of the interface circuit MOTOROLA In order to minimize the component count the re fresh request timing is supplied by the processor s Serial Control Interface SCI clock SCLK Initial ization software configures this clock to provide a pulse train with a 15 us period Once initialized the generation of this signal is completely transparent to any code executing on the processor Figure 1 6 is a listing of the initialization code and a short pass fail memory test routine The value loaded into the SCI Clock Control Register SCCR at X FFF2 will vary as a function of the system clock frequency For a 33 MHz clock a value of 107F will yield the desired refresh rate of 15 6 us per r
16. A MOTOROLA TO T1 T2 Tw Tw Tw Tw T3 TO T1 T2 Tw Tw Tw Tw Tw Tw T3 TO ADOR D0 23 DATA to PSRAM DATA to PSRAM STATE IDLE IDLE IDLE IDLE Prei Pre2 FIM IDLE IDLE Figure 1 4 DSP56001 to PSRAM Timing shows the operation of the controller as itprogresses through a pair of successive memory accesses he timing diagram in Figure 1 4 shows the operation MOTOROLA MOTOROLA 0001 module pseudo 0002 title Pseudo Static RAM Timing Controller Ver 1 0003 MOTOROLA INC 17 July 1990 0004 0005 001 device P16R4 0006 0007 INPUTS 0008 CLK pin DSP56001 Clock 0009 CSin pin 2 EXT RAM Address decode 0010 Busy pin 3 BUSY F E 0011 Rreq pin 4 latched request for refresh 0012 0013 OE pin 1 OE 0014 0015 OUTPUTS REGISTERED OUTPUTS 0016 Q0 pin 45 State bit 0 0017 01 6 State bit 1 0018 Q2 pin 5 State bit 2 amp Busy clr 0019 03 pin 4 State bit 3 not used 0020 0021 COMBINATORIAL OUTPUTS 0022 WIn pin 9 Bus Wait 0023 Fn pin 8 Clear refresh cycle request 0024 CSout pin 37 Chip Select for EXT RAM 0025 0026 High Low 1 0 0027 H L C K X OU ES MEE T 0028 0029 Ostate 02 01 00 1 0030 Idle TIT 1 0031 Pri 1 1 0 1 0032 Pr2 1 0 0 0033 RE3 1 0 1 1 0034 4 DuL 15 0035 RES 0 0 0 1 0036 RF6 05 5 0 11 0037 FIM 0 LL 35 0
17. K PC2 selected as SCLK000004 46 P 0108 08 4 movep 0004 X FFE3 SCLK pin configured as output 000004 47 P 010A 60 400 move 1000 r0 r0 points to the two addresses 001000 48 P 010C OAFA67 bset 77 OMR BS WT selected 49 0100 221400 move r0 r4 pointer reg for Y moves 50 010 45F41B clr b gt 000001 x1 constant for increment Figure 1 6 PSRAM Interface Initialization Code used to initialize and run a simple functionality test sheet 1 of 2 MOTOROLA 1 15 MOTOROLA MotorolaDSP56000MacroCross Assembler 3 02 90 09 0615 06 48psra Pa a X r0 a Y 04 store the data in X X1 b X r0 x0Y r4 y0 retrieve data P form the next data pat x0 a if X data not correct X ERR j bump error count y0 a now check Y data Y ERR j and log differences 0 bl a this allows data to roll a check for start of new lc COUNT and increment count if ye loopl RRR 2 12 20212202 202020202 202 202022 22 2 I IK error handler for X me X 0 r3 get last count from store P Can t use it yet 53 bump count r3 X 0 save new count back to the salt mine 32 32 32 12 error handler for Y me Y FLOGS 13 r3 Y 0 J
18. MC74AC74 is clocked by the rising edge of BS which occurs at the end of each external bus cycle In the event that the bus cycle which has just ended was an active cycle for the PSRAM array the PSRAM address decode DS in this example will be latched into Flip Flop A The PLD will receive MEMORY BUSY status indicating that a pre charge cycle is in progress The PLD will hold off further PSRAM activity until sufficient precharge delay has elapsed Note that no extra delay is seen by the DSP56001 if the subsequent cycle does not access this particular PSRAM If multiple banks of PSRAM are used bank interleaving strategies can result in most or all of the precharge cycles being hidden MOTOROLA 1 9 behind activity in complementarysmemory banks Similarly if the DSP56001 is executing code out of an external SRAM in another bank the precharge activ ity would be transparent The ABEL design file forthe PAL16R4 7 is a very simple Mealy type state machine see Figure 1 5 It controls the chip enabling of the PSRAM as well as the assertion of WT which goes to the DSP56001 to hold off bus activity In addition the machine provides resets for the external latches The function of the PLD is shown in the state diagram of Figure 1 3 D IRefresh Req amp IBUSY Refresh Req Figure 1 3 PSRAM Interface State Diagram implemented in a sin 1 ABEL is a trademark of the data I O Corporation 1 10 MOTOROL
19. Motorola Digital Signal Processors DSP56001 Interface Techniques and Examples by Roman Robles Digital Signal Processor Operation MOTOROLA APR11 Motorola reserves the right to make changes without further notice to any products here in Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical pa rameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by customer s technical ex perts Motorola does not convey any license under its patent rights nor the rights of oth ers Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affili ates and distributors harmless against all claims c
20. OLA 0 Operating Mode Register 1 3 p PAL sarita hod kx EU ea 1 11 2 8 2 9 3 1 1 11 2 9 3 1 Power Consumption 1 3 Precharge 2 3 2 9 Pseudo Static RAM 1 2 PSRAM raa comae uere use xu eura 1 11 R RAS acuto 2 9 424 a elei 1 3 3 5 References 1 12 Refresh are dean 2 2 Refresh Cycle 1 6 2 8 Refresh Mode 1 2 Refresh Request Timing 1 5 2 5 Reset near Ced vx 3 2 Row Address 5 2 2 2 3 Row Addresses 2 2 8 S SCI 1 5 2 5 Self Refresh 1 2 SRAM u 220202 14 25805582 2 5 State Diagram 1 6 State 2 2 1 11 3 2 Static RAM 2 2 1 _w Wait State 1 3 1 5 1 7 1 11 2 1 2 4 2 5 Write rna 1 3 2 2 2 4 2 6 3 5 Write Back 2 3 INDEX 2 MOTOROLA REFERENCES 1 Eggebrecht Lewis Interfacing to the IBM Personal Computer Howard W Sams amp Company 1988 2 DRAM Refresh Modes Motorola Application Note AN987 3 Motorolas DSP56000 DSP56001 Digital Sign
21. RAM Memory Address Multiplexing 2 3 Figure 22 DRAM Refresh Modes 2 4 Figure 2 3 DSP56001 to DRAM Timing 2 5 Figure 24 DSP56001 to DRAM Schematic 2 8 Figure 2 5 DRAM Interface State Diagram 2 10 Figure 2 6 _PLD Design File DRAM Interface 2 13 Figure 2 7 DRAM Interface Initialization Code 2 15 Figure 3 1 DSP56001 to ISA Bus Interface Schematic 3 2 Figure 3 2 Definition for the ISA Bus Interface 3 6 Figure 3 3 DSP56001 to ISA Bus Interface Timing 3 8 Figure 4 1 Example Program of DSP56000 Host Interface Using C Language 4 4 MOTOROLA PSRAM combines the economies of DRAM with the straightforward interface of fully Static RAM to provide 128K bytes in a 32 pin SECTION 1 Interfacing Motorola s DSP56001 to Pseudo Static RAM When the design definition of a DSP subsystem calls for a large memory space the cost of populating this space with static RAM SRAM can be prohibitive Al though SRAM offers the advantages of high speed and a very simple interface the complex structure of the SRAM storage cell results in SRAM price density ratios which are inferior to those of dynamic RAM Pseudo Static RAM PSRAM presents one possible compro mise between the contradictory requirements of high density low cost high speed and interface simplicity This section presents a simple implementation of a PSRAM interface to the DSP56001 Using an array of three 128K x 8 PSRAMs the circuit provides access to
22. SA Bus Interface Sheet 2 of 2 MOTOROLA 3 7 PROCESSOR CLOCK ISA BUS A0 A15 HEN Buffer Enable 1 EB T2 T3 Tw T4 A HR W Write HR W Read Figure 3 3 DSP56001 to ISA Bus Interface Timing shows the timing for both a read and a write operation 3 8 MOTOROLA The C language source code and the source for the PLD used in the hardware interface are both available on Motorola s Dr BuB BBS SECTION 4 Communicate with the DSP56000 Host Interface Using C Language 4 1 Introduction Interfacing a DSP56000 1 2 target system to an ISA bus is only partially complete when the hardware is in place Download software is the other element re quired before debugging begins The specific target hardware determines the types of tasks relegated to the download software We assume that the user has a target system similar to the DSP to ISA interface described in Figure 3 1 4 2 Example Program The following example uses the DSP56002 The download task can be subdivided into four steps reset the DSP verify that the DSP is present at the expected location transfer code into the DSP s internal P RAM terminate the boot execute the loaded application Assume that the DSP56002 s target host interface HI registers have been mapped by the interface MOTOROLA 4 1 hardware into t
23. SP56001 single transistor Using an array of six MCM514256A P70 256K x 4 and a single DRAMS the circuit provides access to 256K 24 bit capacitor words of data space With the DSP56001 operating from a 33MHz clock this interface can run with 2 wait states for non consecutive accesses For purposes of cir cuit simplicity the device s fast page mode is not utilized in the following example MOTOROLA 2 1 DRAM Basics The 514256 DRAM is a 1 megabit part organized as 4 sections of 256Kbits each Each of the 4 sections is subdivided 512 x 512 matrix of storage cells with each storage cell containing one bit of information The mem ory cells are uniquely identified by their associated row and column numbers address In order to reduce the package size the row addresses and the column addresses of the DRAM cells are multiplexed onto the same pins Latches on the device are loaded with the column and row portions of the address by the signals Col umn Address Strobe CAS and Row Address Strobe RAS respectively During a normal memory access the cell s row number is placed on the address lines and RAS is asserted After the specified row address hold time the cell s column number is placed on the same address lines and CAS is asserted This sequence is illustrated in Figure 2 1 The high density of DRAM results from the simplicity of the storage cells each cell consists of a single transistor and a
24. The part is pro grammed as Mealy type state machine and simply advances through a sequence which selects the appropriate address portion i e row or column address generates GAS and RAS which the DRAMs require and generates memory pre charge delays by forcing the DSP56001 to insert wait states in any bus cycle which occurs immediately after a cycle to same DRAM array This pre charge time is transparent when subse quent memory cycles do not access the same memory devices For this reason if more than one DRAM array is present interleaving the arrays may yield significant improvement in the performance of the memory subsystem The timing diagram in Figure 2 3 shows the operation of the controller as it progresses through a pair of successive memory accesses The diagram illustrates the case where the DRAM array was not accessed during the instruction cycle immediately preceding the start of the diagram When operating with EXTAL at 33 MHz the length of each T period is 15 1 us The four Tw periods in the first access cycle are the result of the DSP56001 s Bus Control Register BCR being programmed to insert 2 wait states in cycles to this portion of its memory map During the second cycle the controller has inserted another 2 wait states four Tw periods in order to allow the DRAM MOTOROLA 2 13 0001 0002 0003 0004 0005 0006 0007 0008 0009 00 00 00 00 00 00 00 00 00 0019 0020 0021 0022 0023
25. al 17 SetReset 0 1 StateDir HRw Host Read WRITE buffer direction ReadDir 1 WritDir O 1 StateNo 02 00 12 Idle 0 0 0 S1 0 0 1 52 0 1 0 53 0 1 1 54 1 00 11 55 1 0 1 56 1 1 0 57 2 1 1 1 AEN amp A9 6 A8 amp A7 amp amp A5 6 4 amp IOR Wcyc AEN amp A9 amp A8 amp A7 6 amp A5 amp A4 amp IOW Addr AEN A14 A9 A8 A7 A6 A5 A4 state_diagram StateReset state Normal if ELSE Wcyc amp A14 THEN SetReset Normal shown in Figure 3 1 Figure 3 2 PLD Definition for the ISA Bus Interface for the PAL22V10 Sheet 1 of 2 3 6 MOTOROLA 0055e state SetReset if Wcyc amp A14 THEN Normal 0056e ELSE SetReset 0057 0058e state diagram StateDir 0059e state ReadDir if IOW THEN WritDir 0060e ELSE ReadDir 0061e state WritDir if IOR THEN ReadDir 0062e ELSE WritDir 0063e 0064e state diagram StateNo 0065e State Idle HEN 1 Ben 1 0066e if Rcyc Wcyc THEN Idle stay put if not for me 0067e ELSE 51 0068e State S1 HEN 1 Ben 1 goto S2 allow time to select 74AC245 direction 0069e State 52 HEN 1 Ben 0 goto S3 Now enable the 74AC245 output 0070e State S3 HEN 0 Ben 0 assert HEN 0071e if Rcyc Wcyc THEN S3 adn loop until the end of the 1 0 cycle 0072e ELSE 84 0073e State 54
26. al Processor User s Manual DSP56000UM AD Rev 2 4 Motorola sDSP56001 56 BitGeneral Purpose Digital Signal Processor Advance Information DSP56001 D Rev 1 5 Motorola FACT Data DL138 Rev 1 6 Motorola s MCM514256A Data sheet Motorola Memory Data DL113 Rev 5 pp 84 98 7 Page Nibble and Static Column Modes Motorola Application Note AN986 8 PAL Device Handbook Advanced Micro Devices Monolithic Memories Inc 1988 9 PAL Devices Databook Advanced Micro MOTOROLA Reference 1
27. e PLD used in the hardware interface are both available on Motorola s Dr BUB BBS MW MOTOROLA 4 3 MOTOROLA hostio c host I F test compiled with Tubro C version 2 01 20 May 1992 include lt stdio h gt include lt dos h gt include lt process h gt define RSTADDR 0x0350 ISA bus address of RESET latch el define BASE 0x0340 ISA bus address of Host Interface define ICR BASE define CVR BASE 1 define ISR BASE 2 define IVR BASE 3 define RXH BASE 5 define RXM BASE 6 define RXL BASE 7 define TXH BASE 5 define TXM BASE 6 define TXL BASE 7 define DELAY 10000 define BOOTSIZE1 7 define BOOTSIZE2 9 int reset56 int unsigned char BRK KR RR kk kk kk 2 2 2 2 2 2 22 simple code to send an incrementing pattern of bytes to host BORK KK KK KK SS kk ke kk kk ke kk kk ko kk ko ke koe JH org p 0 begin unsigned char BOOT1 0 08 0 4 0 0 movep 0001 x FFEO 0x00 0x00 0x01 f 0x08 0xC8 0x2B 5 movep A0 x FFEB 0x00 0x00 0x08 inc A Ox0A 0xA9 0x81 jclr f1 x FFE9 0x00 0x00 0x04 g 0x0C 0x00 0x00 jmp lt begin void main unsigned char tI int k system ELs BRK KR KK RK RRR ke kk kk 2 kk kk 2 2 2 kk 2 2 2 2 2 2 22 Kok boot the 56002 with the patter
28. es 4 2 MOTOROLA ence of a functional DSP56002 host interface by reading four of the HI registers and by checking for presence of the default values This is a good check of the DSP56002 reset sequence if it does not re set properly and detect the desired boot mode the HI will not be enabled and of the interface hard ware s ability to read the HI If the proper default values are not sensed the program exits and re turns to the command line prompt If a DSP56002 is found at the expected address the ISA download program proceeds to load the ini tial target code into the DSP s internal P RAM at addresses P 0000 01FF Recall that this process occurs while the DSP56002 on chip PLL is set to multiply the external oscillator frequency by one so it can be a relatively slow process if the DSP is be ing run from a slow external clock To save time when loading DSP routines which do not require the entire on chip P RAM space the boot can be termi nated early by setting HOST FLAG bit 0 as is shown in the listing in Figure 4 1 For brevity the actual code to be downloaded is present in the ex ample as a statically declared buffer The user may prefer to write a function to place LOD or CLD for matted disk data into a buffer which is passed to the download function This example should serve as a beginning for a host download capability through the DSP56000 1 2 Host Interface The C language source code and the source for th
29. he DSP for k 0 k lt DELAY k wait inportb RSTADDR clear reset for k 0 k lt DELAY k wait again printf nRESET CYCLED Wn eye candy then verify that DSP56002 is present read the icr cvr isr ivr and look for default values in these registers Refer to the DSP56000 1 2 Family User s Manual for a complete description of Host Interface Port B fand its register set icr rd inportb ICR Interrupt Control Register s b 0x00 ay cvr rd inportb CVR 7 Command Vector Register s b 0x12 isr rd inportb ISR Interrupt Status Register s b 0x06 ivr rd inportb IVR Interrupt Vector Register s b 0x0F printf n HOST I F RETURNED ICR 2X IVR 2X ISR 2X IVR 2X a Tor rd cwvr rd ist rd ivr rd if icr rd 0x00 rd 0x12 Sard 0x06 ivr rd OxOF if default values printf RESET FAILED NOT found advise return 1 and return error Figure 4 1 Example Program of DSP56000 Host Interface Using C Language sheet 2 of 3 4 6 MOTOROLA else h BOOT THE DSP for 0 j 0 i codesize i NOTE always send the lsbyte last while inportb ISR amp 0x02 2 wait for TXDE 1 outportb TXH codeptr 3 send upper byte outportb codeptr 3 send middle byte outportb TXL codeptr 3 se
30. he ISA bus I O address space from 0x340 through 0x347 Refer to the DSP56002 Us er s Manual SECTION 5 for a description of the HI register set visible to the host processor Addition ally the target hardware has a latch attached to the DSP56002 RESET which can be set RESET as serted by ISA bus writes to 0x350 the data is ignored and cleared ISA bus reads from the same address The C language program which appears in Figure 4 1 performs all of the download tasks listed above After some initialization of the screen the code jumps to the download routine RESET56 This routine re sets the DSP and waits for a short delay to assure that the device receives a reset pulse of adequate duration Following this the reset is released and another delay is invoked simply to provide time for the target system to recognize the release of reset and to start executing the routine in its internal boot strap ROM This routine will sample the mode selection lines MODA IRQA MODB IRQB MODC NMI to determine the type of boot desired from a target processor via the HI in this case branch to the ROM code which will initialize the DSP56002 as required for booting from the HI start receiving code from the selected bootstrap peripheral the HI jump to the start of the newly downloaded code upon completion of the boot After the reset sequence the download routine which is running on the ISA bus host will check for the pr
31. his po tential a bit from the DSP56001 s Port B is usedas a bank selector The configuration of this bit is also handled by the initialization software Note of caution accesses to the DSP56001 s in ternal peripherals and internal data do not generate external memory cycles and as such are not subject to control by the bank selection logic The interface requires complementary phases of the same clock which drives the DSP56001 In systems operating from an external clock source this should be easy to provide In this example the DSP56001 clock was buffered by a CMOS inverter which was subsequently used to drive the interface circuitry It is essential that the device used to buffer this clock has a very high input impedance The oscillator on the DSP56001 cannot drive a TTL input load Note that the Vcc and Gnd pins of the 256Kx4 DRAM do not follow the usual polarity conventions Consult the MCM514256A data sheet for pinout information 2 8 MOTOROLA MOTOROLA 2 9 x a B25 CTOR is J3 of DSP56000 ADM es Resistors 22 OHMS gla ajajalajalalalalalajaja ADOO ADO1 ADO2 AD03 2 4008 3 ADO9 5 AD10 ADT1 MCM514256 P70 DYNAMIC RAM SIX o o S Jo In 25 2525 Oy Calo LS fo fo bo E Ef MC74AC157 XY JANKO M Pu i
32. k k ck k ck k ck ck ck k kCk kckck ck k ck k ck k ckck ck k ck k ck k ck k ck k ck k KKK KKK Motorola Austin DSP Operation August 15 1990 COPYRIGHT C BY MOTOROLA INC ALL RIGHTS RESERVED ALTHOUGH THE INFORMATION CONTAINED HEREIN AS WELL AS ANYedNFORMATION PROVIDED RELATIVE THERETO HAS BEEN CAREFULLY REVIEWED AND IS BELIEVED ACCURATE MOTOROLA ASSUMES NO LIABILITY ARISING OUT OF ITS APPLICATION OR USE NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS X X Xx XR OX X HF A dram ex asm dynamic ram exerciser qu ck and dirty test of DRAM prototype board This code configures the SCI SCLK output to generate the P S refresh timing An incrementing pattern is written to the d at 51000 and Y 1000 and then these locations are read and compared with the expected data If an error is detected a errorecounter is incremented X 0000 holds the count of err found while accessing X memory and Y 0000 holds the Y memor errof count This quickie only tests the interface for data transfer and refresh interference It does NOT exercise the refresh logic functionality Bit 0 of PORT B is used to select between two banks of 64k x 24 X 2 but this is not used in this exercise the end of each pass i e when the 24 bit pattern rolls to 0 a pass counter is incremented This counter is at Y 0 The pass counter and the error logs are located in on chip R in o
33. le external logic this port can be used to interconnect the DSP56001 and an ISA Bus host processor i e a PC Clone This brief note describes one implementation of such an interface using only two external parts 3 1 Interface Circuit Overview The interface consists of a single PAL22V10 and one MC74ACT245 octal data transceiver The PLD gener ates the control signals required by the Host Interface of the DSP56001 HEN HR W as well as the boot mode selection during reset The schematic of the in terface appears in Figure 3 1 The PLD definition is shown in Figure 3 2 The MC74ACT245 buffers the data lines between the Host Interface and the ISA Bus The Host Interface address lines are not buffered in this example be cause the DSP56001 load to these lines is equivalent to that of a typical CMOS buffer In some cases add ing a buffer to these lines might be desirable MOTOROLA 3 1 NOTE CONNECTOR is J1 of ISA BUS All Series Resistors15K OHMS mos B30 A27 A26 A25 A24 A23 A22 A17 A11 B14 B13 A02 A03 A04 A05 A06 A07 A08 A09 K HEN HR W MODA IRQA MODB IRQB RESET o gt N N a lt a DSP56001 MC74ACT245 A31 A30 A29 Figure 3 1 DSP56001 to ISA Bus Interface Schematic illustrates how simple the circuitry is to connect to the ISA bus MOTOROLA 3 2 Detailed Circ
34. nd low byte outportb ICR 0x08 terminate Host Boot return 0 Figure 4 1 Example Program of DSP56000 Host Interface Using C Language sheet 3 of 3 MOTOROLA 4 7 INDEX A ABEL en ie 1 8 1 11 2 9 2 10 Application Development Module 1 5 2 5 Application Development System 2 7 Assembly Language Program 1 11 Auto Refresh 1 1 1 2 B Bank Interleaving 1 6 Bank Select 4 2 8 3 2 Bus 2 13 Bus Control Register 1 7 1 11 Bus Interface Timing 3 6 CAE pi eui Hees S agr en 2 9 CE only Refresh 1 2 Column Address Strobe 2 2 2 3 Column Addresses 2 8 p BRAM ODD oe here 2 2 2 5 Dynamic RAM 2 1 F Fast Page Mode 2 3 H Host Interface 3 2 Initialization 1 5 2 5 2 11 Interleaving 1 11 ISA BUS xui s widen ed oie oa dad ene don 3 1 ISA Bus Interface 3 3 3 4 M Memory 1 5 2 5 Multiple 1 6 MOTOR
35. nes during reset During a transfer cycle to from the Host Interface Registers the PLD functions as a simple state ma chine which sequences the control signals for the bus transceiver and the data strobe Because the ISA bus I O cycles have relatively long periods slower PLD s often prove adequate When attach ing this interface to 33 MHz machines a 15 ns PLD is recommended 3 3 Timing Figure 3 3 depicts the timing relationships present during Bus I O Read cycles and I O Write cy cles The duty cycle of the processor clock has a 2 1 ratio of low period to high period and a frequency of one third that of the master oscillator During an I O cycle either IOW or IOR will be asserted The most critical aspect of this interface is the rela tionship between Host Enable HEN and the other interface signals The Host address lines 2 and Host Read Write HR W must remain stable during the period in which HEN is asserted The propagation delays associated with the MC74ACT245 transceiver have been considered 3 4 MOTOROLA and the complications typical of asynchronous in terfaces have been avoided by running the PLD clock from the system oscillator which operates at 3x the processor clock During successive cycles of the oscillator the transceiver s direction is estab lished the transceiver is enabled and HEN is strobed The ISA bus indicates the completion of the data transfer by releasing IOR or IOW as ap p
36. nimum parts count and therefore minimum expense the fast page mode of the 514256 is not utilized For more detailed information on the MCM41256A refer to the Motorola Memory Data Book DL113 Rev 5 pp 2 84 through 2 98 CAS RAS Only RAS an oS U CAS Before RAS m MEMORY CYCLE gt REFRESH CYCLE CAS Im Hidden DATA OUT VALID DATA OUT Figure 2 2 DRAM Refresh Modes are available but the CAS before RAS mode has clear advantages for DSP applications MOTOROLA 2 5 TO T1 T2 Tw Tw Tw Tw T3 TO T1 T2 Tw Tw Tw Tw Tw Tw Tw Tw T3 TO om TU GOL ff 0 8 ROW COLUMN ROW COLUMN w V fluv v A W e My UN D0 23 _ DATA to DRAM mm DATA to DRAM STATE Idle RTime 2 Pre1 Pre2 IDLE RTIME CTimeCTime2 1 Pre2 0 DSPL Figure 2 3 DSP56001 to DRAM Timing shows two back to back write operations NOTE Figure 2 3 shows the timing relationship be tween the DSP56001 Port A and a DRAM module The Port A interface is described in Section 1 2 DSP56001 Memory Basics MOTOROLA 2 1 Circuit Overview The circuit in Figure 2 4 is designed to serve as an extension of the MOTOROLA DSP56000ADS Ap plication Development Module ADM The SRAM on the ADM should be configured to appear only in the DSP5
37. ns to host routine RRR KK RK KKK Ekk Rkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk printf n BOOTING 56002 Incrementing Patterns to Host if reset56 BOOTSIZE1 BOOT1 1 exit 1 Figure 4 1 Example Program of DSP56000 Host Interface Using C Language sheet 7 of 3 MOTOROLA 4 5 printf n TESTING DATA READ 56002 to HOST Wn k OxFFFF outportb 0 assure proper mode DMA off etc while inportb ISR amp 0x01 0 wait for RXDF j inportb RXL amp OxFF get first pattern do while inportb ISR amp 0x01 0 wait for RXDF 1 i inportb RXL amp OxFF get next pattern if i j41 OxFF check and advise printf n ERROR Revd 2X ExpeCB amp d 2 1 3 j i re sync pattern while k printf n READ TEST COMPLETE n n BRK IK IK RR kk Ck ke KR IR IK RAR AR Ko kk k kk k kkk AA AS routine to reset and boot the DSP56001 2 BRK IK IK RK KK IK k k k k k k k k RR KK int reset56 int codesize unsigned char codeptr unsigned char icr rd cvr rd isr rd ivr rd int i j k first assert reset Leave reset asserted for a while before releasing it give the DSP time exit reset sample the MODA MODB MODC pins and start the bootstrap code outp int RSTADDR 0 reset t
38. osts damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola 4 are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportuni ty Affirmative Action Employer SECTION 1 Interfacing Motorola s DSP56001 to Pseudo Static RAM SECTION 2 A Simple Dynamic RAM Interface for the DSP56001 SECTION 3 A Simple ISA Bus Interface for the DSP56001 SECTION 4 Communicate with the DSP56000 Host Interface Using C Language INDEX REFERENCES Table of Contents 1 1 1 2 1 3 1 4 2 1 2 2 2 8 3 1 3 2 3 3 4 1 4 2 DSP56001 Memory I O Basics 1 4 Memory Subsystem Overview Circuit Description Summary Circuit Overview Circuit Description Summary Interface Circuit Overview Detailed Circuit Description Timing Introduction Example Program 1 5 1 8 1 11 2 6 2 9 2 12 3 1 3 4 4 4 Index 1 Reference 1 MOTOROLA Illustrations Figure 1 1 Pseudo Static RAM Auto Refresh Timing 1 3 Figure 1 2 DSP56001 to PSRAM Schematic 1 6 Figure 1 3 PSRAM Interface State Diagram 1 9 Figure 1 4 DSP56001 to PSRAM Timing 1 10 Figure 1 5 DSP56001 to PSRAM PLD Definition 1 13 Figure 16 PSRAM Interface Initialization Code 1 14 Figure 2 1 D
39. ow A second task of the initialization software is the se lection of the BS WT mode of operation This mode allows external source to insert wait states into bus cycles and is employed by the interface when precharge and refresh delays are needed The interface operates from the same clock which drives the processor In systems operating from an external clock source this should be easy to provide In this example the DSP56001 clock is buffered by a CMOS inverter which subsequently drives the inter face circuitry It is essential that the device used to buffer this clock has a very high input impedance The oscillator on the DSP56001 cannot drive a TTL input load 1 8 MOTOROLA 1 3 Circuit Description Figure 1 2 is a schematic depiction of the interface circuit Basically the interface provides two functions it controls the refresh cycles and it generates pre charge delays Section B of the MC74AC74 generates a refresh re quest on the rising edge of SCLK and holds the request until the PAL16R4 7 controller executes a re fresh cycle and resets the Flip Flop As shown in Figure 1 3 the controller defers a refresh cycle until any access currently in progress completes If the subsequent DSP56001 instruction cycle does not ac cess this PSRAM array this refresh is transparent If the subsequent cycle does access this area of mem ory then wait states are inserted until the refresh completes Section A of the
40. rder to allow limited error analysis after any type of 0108 08 4 0 movep 0002 X SFFF 10 bit async mode 00000 010A 08F4B2 movep 107F X SFFF2 SCI internal CLK pin configure TCM RCM 0 internal clock crash These locations should be cleared before starting test Subsequent restarts can continue the logging without initializing these locations P 0100 org P 100 P 0100 08F4BE movep 2200 X FFFE 2 wait states in X Y P 0102 08F4A2 movep 1 X SFFE2 Port B Bit 0 is output P 0104 08 4 4 movep 0 X SFFE4 Port data is all 0750 P 0106 08 4 0 movep 0 X FFEO Port is G P I O 00000 Figure 2 7 DRAM Interface Initialization Code provides both the initialization of the DRAM interface and a simple test of the Sheet 1 of 2 2 16 MOTOROLA TCM RCM 0 SCLK internal clock output prescale 1 1 divide fosc by 4 127 1 OC 08F4A1 movep 0004 X FFE1 SCLK PC2 selected as SCLK000004 OE 60F400 move gt 1000 r0 r0 points to the two addresses 001000 10 OAFA67 bset 7 OMR BS WT selected 11 221400 mover 0 r4 pointer reg for Y moves 12 45F41B clrb gt 000001 x1 constant for increment000001 14 8A0000 loopl move a X r0 a Y r4 store the data in Y 15 C08068 add x1 bX r0 x0Y r4 y0 retrieve data and form the next data pattern 16 200045 cmp x0 a if X data not correct 17 OBFOA2 jsne X ERR j bump error count000121 19 200055
41. refresh cycle The CAS before RAS mode is employed in this example because it requires very little external circuitry and provides for bus activity concurrent with the refresh cycle A requirement related to refresh is pre charge During read operations some of the charge on the cell s capacitor isTost and the memory device must re write the information back into the cell The DRAM automatically performs this write back operation after every read but external access must be delayed until the pre charge is complete ROW COLUMN A0 A8 ADDRESS ADDRESS Figure 2 1 DRAM Memory Address Multiplexing to reduce the pack age size the row addresses and the column addresses of the DRAM cells are multiplexed onto the same pins Latches on the device are loaded with the column and row portions of the address by the signals Column Address Strobe CAS and Row Address Strobe RAS 2 4 MOTOROLA Many DRAMs available today offer special access modes which can yield im proved performance in specific situations The MCM514256A DRAM supports a fast page mode in which successive accesses to cells in the same row can be read written much faster than in normal random access situations Although this feature would yield improved memory bandwidth in many DSP applications the need for external address latches and comparators would add significant complexity to the circuit Since the design goal of this example is mi
42. ropriate to the direction of transfer and the PLD deasserts HEN on the following oscillator cycle The MC74ACT245 is disabled on the device en able Successive oscillator cycles Please refer to the DSP56001 User s Manual Mo torola Document DSP56001 D for a complete description of the operation of the DSP56001 MOTOROLA 3 5 0001e 0002e 0003e 0004e 0005e 0006e 0007e 0008e 0009e 0010e 0011e 0012e 0013e 0014e 0015e 0016e 0017e 0018e 0019e 0020e 0021e 0022e 0023e 0024e 0025e 0026e 0027e 0028e 0029e 0030e 0031e 0032e 0033e 0034e 0035e 0036e 0037e 0038e 0039e 0040e 0041e 0042e 0043e 0044e 0045e 0046e 0047e 0048e 0049e 0050e 0051e 0052e 0053e 0054e module pcio2 title ISA IBM PC Interface Ver 2 MOTOROLA INC 14 February 1991 001 device P22V10 INPUTS CLK pin ISA Bus Clock AEN pin 9 Address Enable NOT DMA cycle A14 A9 A8 pin 8 7 6 ADDRESS Bits14 09 08 7 6 5 4 5 4 3 2 ADDRESS Bits 07 04 IOR IOW pin 0 11 I Q Read I O Write IROA IROB pin 3 23 OUTPUTS MODA MODB pin 4 22 RESET pin 21 Reset latched 02 01 00 pin 20 19 18 HEN pin 7 HOST ENABLE HRw pin 6 HOST R W Ben pin an Buffer Enable for 74AC245 RESET ISTYPE reg D Buffer 02 01 00 5 reg_D Buffer HRw ISTYPE reg_D Buffer High Low 1 0 H L C K X 21 0 99 2 x StateReset RESET Norm
43. s transparent If the subsequent cycle does access these DRAMS then wait states are inserted until the refresh completes The refresh cycle is very similar to a normal access cycle with the exception of CAS being asserted before RAS The states of RD WR and the address lines are irrelevant MOTOROLA 2 11 REFRESH CYCLE MEMORY ACCESS CYCLE 5 DRAM Interface State Diagram implemented single PAL By asserting CAS before the assertion of RAS a re fresh cycle is initiated At the completion of the refresh cycle the refresh row counter aboard the DRAMs advances in preparation for the next re fresh cycle The interface circuit described here refreshes one row 15 us so that all 512 rows are refreshed within the 8 ms required by the DRAMs In order to reduce the reflected energy on the address lines they are terminated with 22 ohm series resistors placed as close to the drivers as is practical Flip Flop B of the MC74AC74 is clocked from the complementary phase of EXTAL and generates the multiplexer steering control signal ADR MUX SELECT This signal places the row portion of the address on the DRAM address lines atthe beginning of a memory cycle and later selects the column portion of the address at the appropri ate point in the cycle 2 12 MOTOROLA The PAL16R4 7 PLD performs the timing control tasks required by the DRAM The ABEL definition of this PLD appears in Figure 2 6
44. uit Description The ISA bus delineates two types of bus accesses memory and I O The distinction is made by the use of separate read and write strobes for each type of access The interface in this example is mapped into the ISA Bus processor s I O space insthe ad dress range 340 34F In order to provide a facility for bootstrap initiation the RESET pin of the DSP56001 is driven by a latch which is mapped into the host I O space Writes to any I O address in the range 348 34F will assert RESET to the DSP56001 A write to any address within the range 340 347 will deassert the RE SET latch The 8 registers which comprise the DSP56001 Host Interface are mapped into the ISA bus I O space between address 340 347 inclusive Communications with the DSP56001 including program bootstrapping are accomplished via l O reads and writes to the appropriate register Please refer to the DSP56001 User s Manual es pecially chapter 10 for a detailed description of the Host Interface and its usage The bootstrap mode on the DSP56001 is select ed via the processor s MODA and MODB inputs The PLD provides the proper logic levels on these lines during reset After reset the MODA and MOTOROLA 3 3 MODB inputs reflect the state of the interrupt re quest inputs IRQA and IRQB thus permitting the normal use of the external interrupt structure of the DSP56001 without forcing constraints on the be havior of the interrupt li
Download Pdf Manuals
Related Search