EP405 1.5 (DES0162), User Manual
Contents
1. MT NVRTC SDRAM FLASH EXTERNAL BUS EBC SDRAM i i I2C SEP SWITCH i BCSR gt P PPC405GP GPr SWI STTM CLOCK LEDO 1 2 3 UARTO ur Y Y RS 232 RS 232 FENET PCI Y Y Y Y JTAG SERIAL 0 SERIAL 1 10BASET PC 104 PLUS TRACE EBC BUS P3 P6 P7 100BASETX P8 P4 EXPANSION P5 P1 P2 P10 P11 T00101C Figure 2 1 Simplified Block Diagram PPC405GP GPr Clocking 700M0067RC1 Refer to PowerPC Processor in this chapter The system clock or SysCIk on the EP board is supplied from an MPC9446 Clock Fanout Buffer device The input to the clock buffer device is a 66 67 MHZ oscilla tor During hard reset the board is configured for either PCI synchronous clocking mode or PCI asynchronous clocking mode depending on the M66EN signal of the PCI bus The MPC9446 device on the board provides the system clock input SysCIk to the processor at 33 MHz For 33 MHz PCI synchronous clocking oper ation the PCI bus clock is the system clock input For 66 MHz PCI asynchronous clocking operation the PCI bus clock is the PCI clock input PciCIk to the proces sor sourced from the MPC9446 device at 66 MHz Chapter 2 Description Computing Engines EP405 1 5 POWER JTAG 0000000 TRACE SERIAL PORTO 10BASET 100BASETX SERIAL PORT 12. D 0 31 A 0 31 gt U8 AO WP ACC Al D15 A27 A2 DQO A26 rE A5 DQ3 A22 A6 DQ4 D10 A21 A7 DQ5 D9 A8 DQ6 A20 D8 AG AQ DQ7 A18 A10 TE A11 DQ8 FT A12 DQ9 DE E A13 DQ10 ba A14 DQ11 A14 D3 E A16 DQ13 Ye A17 DQ14 Fr A18 DQ15 A 1 Fe A19 Aa A20 RY BY m 2 A S A23 3 3V H BYTE CSOn gt CE OE WE RESET U9 A29 fen AO WP ACC A1 A27 D31 A26 A2 DQ0 D30 A3 DQ1 A25 D29 A4 DQ2 A24 D28 22 A5 DG3 A22 A6 DQ4 D26 A21 A7 DOR D25 A8 DQ6 A20 D24 A10 A18 A17 u pee et A16 A12 DQ9 D21 A13 DQ10 A15 D20 ro A14 DQ11 SE roe A15 DQ12 D a E A16 DQ13 Dir Fer A17 DQ14 Dre Fr A19 BB A20 RY BY Ro A21 i A22 A23 3 3V BYTE CE OE WE RESET T00157B Figure 2 4 FLASH Address and Data Lines Table 2 1 FLASH Devices Device AM29LV160MB Device ID 2249 AM29LV320ML 227E 221D 2200 AM29LV640ML 227E 220C 2201 AM29LV128ML 227E 2212 2200 AM29LV256ML 227E 2212 2201 700M0067RC 1 Computing Engines EP405 1 5 Chapter 2 Description The tollowing guidelines apply to x32 ported FLASH memory e FLASH devices configured in 16 bit mode e Sector and chip erases should be performed only on a long word basis e Programming should be done on a long word basis if possible e One bank of FLASH with contig
3. O 0 00 OJO AA olo k O G O NOTES 1 Refer to Table 10 1 for interrupt definitions 2 Select an XIRQ by writing an XIRQ index to BCSR5 then choose which processor IRQ line to route the selected XIRQ to by writ ing to BCSR6 Table 7 7 40 700M0067RC1 Computing Engines EP405 1 5 Chapter 7 Board Control and Status Registers Table 7 7 BCSR6 XIRQ Routing Byte Address F400 0006 Selected XIRQ Function i Definition RSIRQO RSIRQ1 RSIRQ2 RSIRQ3 Function Select SYSERR Select STTM Select RTC Select FENET Select NB Select SB Select RI Reserved Select XIRQO Select XIRQ1 Select XIRQ2 Select XIRQ3 Select XIRQ4 Select XIRQ5 Select XIRQ6 Reserved reset value 0000 0111 O O O O 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 mr nr CO O O mr O O k CE OO O O m Unused XIRQ routing Function Enable XIRQ on IRQO Enable XIRQ on IRQ1 Enable XIRQ on IRQ2 Enable XIRQ on IRQ3 Enable XIRQ on IRQ4 Enable XIRQ on IRQ5 Enable XIRQ on IRQ6 Disable XIRQ NOTES 1 Refer to Table 10 1 for interrupt definitions 2 Processor IRO 0 6 3 Select an XIRQ by writing to BCSR5
4. Figure A 3 EP405 Board Mechanicals Front and Back i 2 33 O gt KAIGHI I BOARD KIGH I ANGLE INCHES 0 330 0 173 8 4 4 4 BOARD MILLIMETERS Figure A 4 Straight and Right Angle Pin Dimensions 700M0067RC 1 Computing Engines EP405 1 5 700M0067RC1 59 Embedded Planet 4760 Richmond Road Suite 400 Warrensville Heights OH 44128 www embeddedplanet com Form 700M0067RC1 Litho in U S A Oct2004 Copyright 2004 Embedded Planet LLC All Rights Reserved Computing Engines EP405 1 5 Phone 216 245 4180 Fax 216 292 0561
5. LED 4 user programmable via control register 2 Bus expansion Processor bus EBC expansion receptacle I O expansion PCI interface via the PC 104 Plus specification 5 VDC supply Single power supply source board draws 1 5 A maximum Operating temperature 0 C to 70 C 32 C to 158 F 700M0067RC1 9 Chapter 1 Introduction Computing Engines EP405 1 5 Table 1 1 Hardware Features continued BCSR Board control and status registers NOTES 1 With optional error checking and correction ECC 2 The bus expansion receptacle allows add on cards to interface to the processor s EBC bus The expansion receptacle also includes the I2C bus 3 Contact Embedded Planet for information about industrial temperature version board 4 The means of disconnection from the mains power supply is the plug 5 No serviceable parts EP405 1 5 Versus EP405 1 3 1 4 SDRAM EBC FLASH Clocking Dipswitch Jumper This section explains the differences between the EP405 1 5 board and the EP405 1 3 1 4 boards The option for ECC memory was added to the EP405 1 5 board This is a build option for the board The PCUNT PerWE signal was added to the EBC bus connector P1 P10 of the EP405 1 5 board The EBC pinout has not changed from the EP405 1 3 1 4 boards to the EP405 1 5 board except for this added signal The EBC connector reference designators and connector pin numbering have changed on th
6. PlanetCore Utilities 700M0067RC1 The EP board in its simplest form is shipped with the PlanetCore boot loader software refer to PlanetCore in Chapter 2 This code verifies the integrity of the hardware allows configuration changes and allows downloading of user code As additional functions are added the program will be updated and made avail able from Embedded Planet Upgrades are provided as files containing Freescale s records The s record data is a program which is downloaded to RAM either using one of the two serial ports and a terminal emulation program or using the 31 Chapter 5 Operation 32 RS 232 Connection User Applications Computing Engines EP405 1 5 Ethernet port and a TFTP server Once downloaded the program runs and replaces the regions of FLASH containing the current code Refer to the PlanetCore User Manuals for information about the PlanetCore boot loader FLASH burner and diagnostics and utilities A 2x 5 header to DB 9 or DB 25 connection is required tor RS 232 communica tion Tables 4 4 and 4 5 provide the pinouts for the headers The EP board has its serial ports wired as DTE A null modem type of connection is required when interfacing to a DTE port For DTE DB9 3 TXD DB25 2 TXD DB9 2 RXD DB25 3 RXD DB9 8 CTS DB25 5 CTS DB9 7 RTS DB25 4 RTS DB9 5 GND DB25 7 GND PlanetCore assumes the board is connected to a dumb terminal or a PC based ter minal emulator
7. 5 VDC from an expansion card The 5 VDC power option requires a regulated 4 75 to 5 25 VDC supply The EP board itself fully configured but with no expansion cards draws 1 5 A maximum at VCC 4 75 VDC to 5 25 VDC T 0 C to 70 C 32 C to 158 E Power Connector The power connector P9 is a barrel type connector The specifications for the mating connector are as follows Inner diameter 2 5 mm 0 100 inches Outer diameter 5 5 mm 0 218 inches Barrel Length gt 9 5 mm 0 375 inches Outer shell is GND Inner shell is 5 VDC Expansion Card It is recommended that the supply voltage for an expansion card be derived from the 5 VDC pins of the expansion connector This keeps the processor memory core which runs at 3 3 VDC very clean 700M0067RC1 23 Chapter 4 Connectors and Headers Computing Engines EP405 1 5 Earth Ground Earth ground connections are made through the four mounting holes on the EP board Earth ground is connected to signal ground in one place on the EP board Signal ground can be optionally disconnected from earth ground by removing RO1 from the EP board Table 3 2 RO1 is populated by default because the EP boards are designed to be powered by a wall cube unit and wall cubes supplied with the units have their grounds GND isolated Applications must consider how the EP board will be powered and whether or not EARTH_GND should be connected to DIGITAL_GND signal ground via RO1 on the E
8. RESET EBC EXPANSION BEBBBBEBBBBBEBEBBEBBEBBEEN BEBBBBEBBEBEBBBBEBBBEBEE BEBBBBBEBBEBBEEBEBBBEBBBEEN BEBBEBBEBBEBBBEBEBBBEBEEN BBBBBBBBBEBBHBEBBEBEBEBBEEBEE L D L L D I I L T T T T Oe TTT TTT TE O P2 E1 P1 E1 e e A1 E 0000 0000 PC 104 PLUS 0 00 P6 P7 00000 00000 150000 10000 7 O ETHERNET T00106C Figure 2 2 EP405 Board Top View Memory BCSR SEP The board can be ordered with a variety of memory configurations and optionally supports ECC memory Table 1 1 SDRAM Micron Samsung refer to SDRAM Organization in this chapter FLASH AMD AM29DLxxxM AM29LVxxxM and NVRAM Dallas Semiconductor DS13xx DS15xx Board control and status registers BCSR provide hardware control and status to the processor BCSR bits selectively enable disable and configure board features and control LEDs read switch settings SW1 and provide status indications The BCSR registers of the EP boards are implemented in control logic within a com plex programmable logic device CPLD Refer to the Chapter 7 for BCSR pro gramming information The serial EEPROM SEP stores configuration parameters for the board These configuration parameters are set using PlanetCore refer to PlanetCore in this chapter The SEP part is a 2 wire serial EEPROM Its functionality is equivalent to the Atmel AT24C04 part Refer to the Chapter 9 for programming information for this IC device 700
9. 10 1 Title Page FLASH Peripheral Bank Access Parameters EBC0_BnAP 34 NVRTC BCSR Peripheral Bank Configuration Register EBC0_B4CR 34 NVRTC BCSR Peripheral Bank Access Parameters EBC0_B4APD 35 BC RO O I ee een 37 BCSR1 PCI Control and Status iii 38 BCSR2 FLASH NVRAM and POR Control and Status 38 BCSR3 FENET and UART Control 39 BESRA PET Status and Maki uuu iai a a te 39 BCSR5 XIRQ Select 40 BESRO XIRO Routine uu anan n reed 41 BCSR7 XIRO Status Onboard un aan 42 BESRSERTRO ats External ea 42 BCSR9 Switch Status and LED Control ss 42 BCSR10 GPIO 17 23 or IRQ 0 6 Select and PAR Control 43 BCSR11 GPIO 1 8 Direction Control 43 BCSR12 GPIO 9 16 Direction Control 44 BCSR13 GPIO 17 23 Direction Control 44 BCSR15 CPLD Code Revision sica 45 SDRAM Configuration Register SDRAMO_CFG ss 47 SDRAM Memory Bank Configuration Registers SDRAM0_B0CR 48 SDRAM Timing Register SDRAMO II uy uu entres 48 SDRAM Refresh Timer Register SDRAM
10. Chapter 3 Setup Computing Engines EP405 1 5 Dipswitch The four pole dipswitch SW1 located on the board is readable via an onboard status register Table 7 10 The switch is intended for user applications but has some reserved settings Table 3 3 describes the switch settings refer to Figure 2 3 tor the location of the dipswitch Table 3 3 Dipswitch SW1 Settings Pole Positions 1234 Function D 24 27 0000 or 1111 Normal operating mode 0001 Reserved for manufacture test 0010 Reserved for fallback mode 0011 through 1110 User specified NOTE down on closed position will read back a logic 0 in the status register up off open position will read back a logic 1 in the status register 22 700M0067RC1 Connectors and Headers Chapter 4 The EP405 board has the following connectors for I O functions and expandabil ity e One RJ 45 connector with integrated LEDs for the fast Ethernet port 100BaseTX 10BaseT e Two headers for RS 232 serial ports e One barrel connector for power e One EBC bus expansion connector e One PC 104 Plus connector e Two headers for auxiliary functions JTAG and TRACE This chapter describes these connectors and headers Refer to Figures 2 2 and 2 3 for the locations of these connectors and headers Power There are different options for powering the EP board e 5 VDC supplied through the barrel connector This is the standard option for powering the board
11. Computing Engines EP405 1 5 DES0162 User Manual Developing Embedded Applications and Products Utilizing IBM PowerPC 4xx Processors 700M0067RC1 700M0067RC1 Computing Engines EP405 1 5 Copyright Notice Trademarks 700M0067RC 1 Copyright O 2004 Embedded Planet LLC All Rights Reserved This manual is copyrighted by Embedded Planet LLC No part of this document may be copied or reproduced in any form or by any means without the express written permission of Embedded Planet LLC Embedded Planet LLC reserves the right to modify the information contained herein as necessary and the customer should ensure that it has the most recent revision of the document Embedded Planet assumes no responsibility for any errors which may appear in this document This manual in whole or in part is to be considered the intellectual property of Embedded Planet The manual and all information explained and derived there from are protected by the license to which you agreed upon opening this package This document is intended for the sole purpose of the owner of an Embedded Planet computing engine to develop applications using PlanetCore Neither the document nor reproductions of it nor information derived from it is to be given to others nor used for any other purpose other than for development of Embedded Planet computing engine applications by original authorized owners of Embedded Planet products Embedded Planet Linu
12. DMA e Ethernet and media access layer MAL interfaces Two serial ports e Inter integrated circuit C interface e General purpose I O GPIO EBC Bus Expansion The EBC Expansion Bus connectors are two 5 x 20 high density surface mount connectors This interface along with the PCI bus interface allow I O expansion cards to be designed and interfaced to the EP board Most peripheral signals are routed to the connectors for processor interface Refer to Figures 2 2 and 2 3 for the connector locations and EBC Bus Expansion Connector in Chapter 4 for con nector pinouts The P1 P10 P2 P11 connectors give access to numerous CPU external signal lines including some of the following interface signals e Peripheral bus clock PerClk e Peripheral address bus PerAddr0 31 e Peripheral data bus PerData0 31 e Peripheral parity bus PerPar0 3 e Chip selects PerCS0 7 Read not write PerR W e Write byte enables or read write byte enables PerW BE0 3 e Output enable PerOE e Write enable PerWE 700M0067RC1 Computing Engines EP405 1 5 Chapter 2 Description e Peripheral data error input PerErr e External interrupt IRQ0 6 e General purpose I O GPIO0 23 IC serial clock I2CSCL DC serial data 2CSDA SDRAM Organization Memory Clock 16 MByte 32 MByte 64 MByte 128 MByte Paged based SDRAM MemCIkOut1 0 100 MHz or 133 MHz 64 Mbit 4M x 16 bit devices 2 Micron MT48LC4M1
13. Address F400 000A reset value 0000 0000 NOTES 1 When GPIO is enabled the corresponding XIRQ status is latched 0 or not pending in BCSR8 Table 7 9 Function GPIO or IRQ select O enable GPIO17 1 enable XIRQ0 Definition Chapter 7 Board Control and Status Registers 0 enable GPIO18 1 enable XIRQ1 O enable GPIO19 1 enable XIRQ2 0 enable GPIO20 1 enable XIRQ3 O enable GPIO21 1 enable XIRQ4 0 enable GPIO22 1 enable XIRQ5 0 enable GPIO23 1 enable XIRQ6 PAR control O disable PAR O 3 1 enable PAR O 3 2 When XIRQ is enabled the corresponding direction bit in BCSR13 has no affect Table 7 14 Table 7 12 BCSR11 GPIO 1 8 Direction Control Byte Address F400 000B reset value 0000 0000 700M0067RC1 Function GPIO direction control Definition 0 GPIO1 output CPU to external 1 GPIO1 input external to CPU 0 GPIO2 output CPU to external 1 GPIO2 input external to CPU 0 GPIO3 output CPU to external 1 GPIO3 input external to CPU 0 GPIO4 output CPU to external 1 GPIO4 input external to CPU 0 GPIO5 output CPU to external 1 GPIO5 input external to CPU 0 GPIO6 output CPU to external 1 GPIO6 input external to CPU 0 GPIO7 output CPU to external 1 GPIO7 input external to CPU 0 GPIO8 output CPU to external 1 GPIO8 input exter
14. D11 D14 G perCLK gt O D12 Sr Q peroEn lt B16 D13 Diz perR_Wn B17 G D14 D18 E perBLASTn B18 5 D15 D19 5 perREADY B19 G T00103B Figure 4 1 EBC Bus Expansion Connector P1 P10 Pinout S1 pe H pue sJ0 099uuo2 p 181deU9 G s0pd3 seulbuj Bunnduuoo LOYZI00W00Z DC P2E P11A A16 E1 A17 Eo A18 E3 A19 E4 O 179 A20 E6 A21 E7 S A22 E8 A23 E9 E10 O A24 Ett A25 E12 G A26 E13 O A27 E14 O E15 O A28 E16 O A29 E17 O A30 E18 A31 E19 E20 LO P2C P11C P2AP11E x Cl oO x_GPIO16_perCS7n AL O 2 O x_GPIO17_IRQO A2 O x lt C3 G x GPIO18 IRQ1 A3 O 5 0V O C4 O x GPIO19 IRG2 A4 O C5 O A5 O x C6 oO x_GPIO20_IRQ3 A6 O x C7 O x_GPIO21_IRQ4 AT O 08 0 x_GPIO22_IRQ5 A8 O 5 0V O O x_GPIO23_IRQ6 ar E x_GPIO24_legacy_newmode dmaREQ0 Att To CPLD Gyo ES dmaREQ1 A12 C13 dmaREQ2 A13 CSOL CSOXn lt O KREG O CLKSYNC lt lt C14 Lo Al4 O lt C15 O A15 O C16 o CFG0_dmaACK0 gt A16 Oo 017 O CFG1 dmaACK1 gt A1Z O I2CSDA C18 O CFG2 dmaACK2 gt A18 5 I2CSCL gt C19 O CFG3_dmaACK3 gt A19 4O P2D P11B P2B P11D D16 D1 O perw
15. DC devices that reside on the DC bus If a master PC device where designed onto an expansion card then the SCL signal must also be programmed for open drain operation The EP board sets both I2C signals to open drain operation SEP Format and Interface Structure Data is stored in the EEPROM device as a series of ASCII records Each record is terminated with the NEWLINE character ASCII hex 0x0A and the last record is terminated with two NEWLINE characters All data bytes after the double NEW LINE of the last record have the binary value OxFF Each record consists of a name and a value that are separated by an character A name identifies the meaning of the value which follows it For example the record HZ 50 declares the system frequency in MHZ to be 50 For more infor mation on the names used in records refer to the PlanetCore User Manuals STTM Format and Interface Structure 700M0067RC1 The driver for the STTM sets the interrupt out for low true operation Interrupt routing is per BCSR6 Table 7 7 and is disabled when PlanetCore is not testing the STIM The driver returns the temperature of the device and also a calibrated temperature for reporting ambient air temperature The calibration parameter is programmed into the SEP and is used to extrapolate ambient air temperature 51 52 Computing Engines EP405 1 5 700M0067RC1 Interrupt Structure Chapter 10 Interrupt enabling and routing are determined by the B
16. and requires user intervention for the diagnostics The dumb ter minal or PC serial port should be set as follows e 9600 baud default e 8 data bits e 1 stop bit e No parity e No hardware handshake Proper interfacing to the serial port via the correct RS 232 connections must be insured as described in RS 232 Connection in this chapter The dumb terminal or PC serial port might require the CTS signal to be true In this case the RTS signal which is driven true from the serial port should also be connected in the cable path to the CTS signal on the dumb terminal or PC serial port 700M0067RC1 Chip Select Programming Chapter 6 Table 6 1 contains the chip select mapping for the EP405 board Table 6 1 Chip Select Mapping Chip Select Function Address FLASH FFFF FFFF minus actual FLASH size Comment 4 8 16 32 64 MBytes Unused Unused Unused Control and status registers F400 0000 BCSR 16 bytes 512K space decoded NVRTC F420 0000 0 32 128 or 512 KBytes Top 16 bytes are the RTC Unused Unused NOTE Unused Can be used to access FLASH if CS0 is used for expansion FLASH Refer to BCSR2 information Table 7 3 1 All chip selects are available at the EBC expansion receptacle P1 P10 P2 P11 FLASH Chip Select Setup Software must program two EBC registers for FLASH memory chip select contig uration e Peripheral Bank C
17. i 24 JA RT aiseee E O E 24 IRACE Por sia i a a D 24 Fast ECE PO ii ee oi a 25 T IlOI a a e Pr TE 25 el ee a a S een 25 PC 1102 15 Connecior uuu u u u u ii ea 26 EBC Bus Expansion CORRECI N mena ia i ri o as Aa 26 Chapter 5 ODA een danses ne 31 Jo B B END gt S r p ST 31 Fast Erben POLE a o a mene as 31 J KC ORE Til ee o i een er ee ree 31 As A e O ee 32 User ADD l SITIO oa 32 Chapter 6 Chip Select Programming 33 PEA STE NP lec Li a ie 33 NVRIC and BESREhip Select X p anna 34 Chapter 7 Board Control and Status Registers 37 Chapter 8 SDRAM Programming T 47 lili l r L nenas 47 CO ol Register G euer rare 47 700M0067RC1 5 Computing Engines EP405 1 5 Contents continued Chapter 9 I2C Devices and Addressing 51 SEP Format and Interface Structure ne 51 STTM Format and Interface Structure sss sese 51 Chapter 10 Interrupt Structure ass i anses etant 53 Appendix A Mechanical Dimensions 55 List of Figures No 2 2 2 3 2 4 4 1 4 2 A 1 A 2 A 3 A 4 List of Tables No 1
18. minimum 133MHz Reserved Leave at reset state 700M0067RC1 Computing Engines EP405 1 5 Chapter 8 SDRAM Programming Table 8 3 SDRAM Timing Register SDRAM0_TR continued Description 27 29 RFTA xxx tRTC tRC CAS before RAS Auto refresh command to next activate command Samsung Micron tRFC 66 nsec where xxx is 011 7 clks minimum 100 MHz 101 9 clks minimum 133 MHz 30 31 RCD XX IRCD RAS to CAS delay 20 nsec minimum where xx is 01 2 clks minimum 100 MHz 10 3 clks minimum 133 MHz NOTE 1 Whichever is larger Table 8 4 SDRAM Refresh Timer Register SDRAMO_RTR Description 00 Always 00 XXXXXXXXXXX Interval refresh rate where XXXXXXXXXXX is 100 MHz 00011000011 Micron 64 msec 4096 cycles 15 625 usec refresh rate 0x0618 for full 16 bit field 1560 x 10 nsec 15 60 usec refresh rate 00001100000 Samsung 64 msec 8192 cycles 7 813 usec refresh rate 0x0300 for full 16 bit field 768 x 10 nsec 7 68 usec refresh rate 133 MHz 00100000001 Micron 64 msec 4096 cycles 15 625 usec refresh rate 0x0808 for full 16 bit field 2056 x 7 6 nsec 15 58 usec refresh rate 00010000000 Samsung 64 msec 8192 cycles 7 813 usec refresh rate 0x0400 for full 16 bit field 1024 x 7 6 nsec 7 76 usec refresh rate Always 000 Reserved Leave at reset state Table 8 5 SDRAM ECC Configuration Register SDRAMO_ECCCF
19. off timing O PerClk cycles TH Transfer hold 0 PerClk cycles RE Disable PerReady SOR Sample on ready PerReady disabled BEM timing active for only write cycles PEN Disable parity checking 700M0067RC1 Reserved Leave at reset state 35 36 Computing Engines EP405 1 5 700M0067RC1 Board Control and Status Registers Chapter 7 The EP405 board has onboard control and status registers These registers are con fisured as x8 ports The registers are defined as shown in Tables 7 1 through 7 15 Register values at reset values in binary Register 0 ID Register 1 0000 0000 Register 2 0000 0000 Register 3 0000 1111 Register 4 0000 1111 Register 5 0000 0000 Register 6 0000 0111 Register 7 0000 0000 Register 8 0000 0000 Register 9 uuuu 0000 Register 10 0000 0000 Register 11 0000 0000 Register 12 0000 0000 Register 13 0000 0000 Register 14 Reserved Register 15 Revision Table 7 1 BCSR0 Board ID Byte Address F400 0000 Function reset value ID NN NO OI O N O 700M0067RC1 Board ID PCI control and status FLASH NVRAM and POR control and status FENET and UART control PCI status and masking XIRQ select XIRQ routing XIRQ status onboard XIRQ status external Switch status uuuu dipswitch setting and LED control GPIO 17 23 or XIRO 0 6 select and PAR cont
20. online help e Configured via EEPROM settings e Robust serial and Ethernet tftp communications and data transfers e Can download s record or binary images e Can boot user applications from FLASH or via TFIP e Diagnostic tests memory FLASH DRAM NVRAM and Ethernet The diagnostics and utilities have the following features and benefits e Diagnostics are available for CPU board testing Can be removed if not needed to free up FLASH memory space e Available in RAM version e Uses monitor port for user interface The FLASH burner has the following features and benefits e Resides as a separate program not resident in FLASH conserves memory e Can be incorporated into the build process to place programs into FLASH memory Erases and programs AMD FLASH memory using a one step process FLASH burner image is in an s record format loaded by the boot loader or debugger e Multiple sections of FLASH can be programmed in one file To use the FLASH burner the code can be loaded and executed from the boot loader or it can be loaded and executed from a debugger if no loader is present in FLASH Once started the burner uses the monitor terminal for a user interface 700M0067RC1 Setup Chapter 3 This chapter describes the various strappings and dipswitch settings that setup the EP405 board for operation The straps are zero ohm surface mount resistors The dipswitch has four positions Jumpers Jumper JP1 co
21. ready PerReady disabled 25 BEM 0 timing active for only write cycles 26 PEN 0 Disable parity checking 27 31 Reserved Leave at reset state NOTE At POR EBCO_BOAP 0x7f8ffe80 slowest possible bus timings NVRTC and BCSR Chip Select Setup Software must program two EBC registers for NVRTC and BCSR chip select con figuration e Peripheral Bank Configuration Register EBCO_B4CR e Peripheral Bank Access Parameters EBCO_B4AP The NVRTC and BCSR share PerCS4 PerClk is 50 MHz The register settings are for a 4 MByte block and based on 150 nsec NVRAM Table 6 4 NVRTC BCSR Peripheral Bank Configuration Register EBC0_B4CR Description Base address select Specifies the bank starting address The bank starting address must be a multiple of the bank size programmed in the BS field BS 4 MByte bank BU read write BW 8 bit bus Reserved Leave at reset state 700M0067RC1 Computing Engines EP405 1 5 Chapter 6 Chip Select Programming Table 6 5 NVRTC BCSR Peripheral Bank Access Parameters EBCO_B4AP BME Description Bursting disabled TWT 00001000 Transfer wait 8 PerClk cycles Reserved Leave at reset state CSN 01 Chip select on timing 1 PerClk cycle OEN 01 Output enable on timing PerOE one PerClk cycle after PerCS4 WBN 00 Write byte enable on timing O PerClk cycles WBF 00 Write byte enable
22. 1 1 2 2 1 2 2 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 5 9 1 6 1 6 2 Title Page Silili L Block Digg roni esra e states ee aera 13 EP405 Doard TOP VIEW au ai iai in a a in 14 EP405 Board Bottom VIEW senil 15 FLASH Address and Data Lines 18 EBC Bus Expansion Connector P1 P10 Pinout ss 28 EBC Bus Expansion Connector P2 P11 Pinout ss 29 EMOS bere tae Mam vs exe gel gl AN TO D 56 EP405 Board Mechanicals Bottom ss 57 EP405 Board Mechanicals Front and Back 58 Straight and Right Angle Pin Dimensions ss 58 Title Page I ware TO il u u rpg 9 Reterente Docu menie u uu i i ee nasa 11 SIL V UD uuu ee ie lada 18 FOD A a Busen 19 LL Jumper a eu Ss E a 21 D AD E o O ER 21 Dipswitch SWI SO un S een 22 TAG Debug Port Pine ut ES nani te a de 24 TRACE Port PMOUE PA unun ea 24 asthr hernetPormTPPinoutr v u u uuu uu ai i usa ae Banasa 25 Serial POP 0 Pik EO Se ee oo ae 25 SHALL DEL Ee ELA H een i i r i a aa en iss 26 De LED Deo uuu aaa een 31 FastEibernet Tort LUDE danas r i a Ra 31 Chip Selec Mapp INE A TT toned 33 FLASH Peripheral Bank Configuration Register EBC0_BnCR 33 700M0067RC 1 Computing Engines EP405 1 5 List of Tables continued 700M0067RC1 No 6 3 6 4 6 5 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 7 10 7 11 7 12 7 13 7 14 7 15 8 2 8 3 8 5 8 6
23. 6A2TG 8E 75 2 MBytes x 4 banks x 2 devices 16 MBytes total 2 bit bank address at A 8 9 12 bit row address at A 10 21 8 bit column address at A 22 29 128 Mbit 8M x 16 bit devices 2 Micron MT48LC8M16A2TG 8E 75 4 MBytes x 4 banks x 2 devices 32 MBytes total 2 bit bank address at A 7 8 12 bit row address at A 9 20 9 bit column address at A 21 29 256 Mbit 16M x 16 bit devices 2 Micron MT48LC16M16A2TG 7E 75 8 MBytes x 4 banks x 2 devices 64 MBytes total 2 bit bank address at A 6 7 13 bit row address at A 8 20 9 bit column address at A 21 29 512 Mbit 32M x 16 bit devices 2 Micron MT48LC32M16A2TG 7E 75 16 MBytes x 4 banks x 2 devices 128 MBytes total 2 bit bank address at A 6 7 13 bit row address at A 8 20 10 bit column address at A 5 21 29 FLASH Organization 700M0067RC1 This section summarizes the FLASH memory devices currently used on the EP board Refer to the AMD data sheets for detailed information about these FLASH memory devices Figure 2 4 shows the address and data line connections An off set is needed when issuing commands to the FLASH devices due to the address line connections Table 2 1 lists the FLASH memory devices and their device IDs Command codes for all devices are the same Device ID varies among the different devices Sector addresses also vary among the different devices Chapter 2 Description Computing Engines EP405 1 5
24. 9 output CPU to external 1 GPIO19 input external to CPU GPIO20_DIR 0 GPIO20 output CPU to external 1 GPIO20 input external to CPU GPIO21_DIR 0 GPIO21 output CPU to external 1 GPIO21 input external to CPU GPIO22_DIR 0 GPIO22 output CPU to external 1 GPIO22 input external to CPU GPIO23_DIR 0 GPIO23 output CPU to external 1 GPIO23 input external to CPU Unused 700M0067RC1 Computing Engines EP405 1 5 Chapter 7 Board Control and Status Registers Table 7 15 BCSR15 CPLD Code Revision Byte Address Function i Definition F400 000F CPLD revision REV revision of CPLD code reset value REV 0 4 2 3 4 5 6 7 700M0067RC 1 45 46 Computing Engines EP405 1 5 700M0067RC1 SDRAM Programming Chapter 8 Initialization 1 Set up all related SDRAMO_xxxx registers except SDRAMO_CFG DCE 2 Wait 100 usec Micron or 200 usec Samsung for SDRAM device powerup sequence This is the delay defined for SAMSUNG LVTTL SDRAM devices 3 Set SDRAMO_CFGIDCE to enable the SDRAM controller The SDRAM con troller will automatically perform the initialization procedure defined in the SDRAM controller section of the PPC405GP GPr User Manual Refer to SDRAM Organization in Chapter 2 for a description of the SDRAM mod ules Controller Register Setup Software must program a number of SDRAM control registers before th
25. BE0n B1 O D17 D2 O perWBE1n Bo O D18 D3 O perWBE2n B3 O D19 D4 5 perWBE3n B4 O D5 B5 D20 D6 HOLDREQ q BG o D7 B7 D22 e 2 CFG17 HOLDACK gt EXTREOn BS 2 re TAR CFG19_EXTACKn gt SE D24 DH O HOLDPRI B11 12 D25 D12 S BUSREQ B12 D26 D13 O perEXTRSTn B13 O D27 D14 5 XRSTn lt lt To CPLD B14 5 D19 O x PAR3 B19 O D20 J 9 T00110B Figure 4 2 EBC Bus Expansion Connector P2 P11 Pinout G sopd3 Sseulduj Bunnduloo SJOPeaH pue SJIOPSUUON y 19 deuo 30 Computing Engines EP405 1 5 700M0067RC1 Operation Board LEDs Chapter 5 This chapter describes the LED indications for the EP405 board It also provides some PlanetCore description and communication information The four user programmable LEDs Table 5 1 are under BCSR control Refer to Table 7 10 for LED control bit information Refer to Figure 2 3 for the locations of the LEDs Table 5 1 Board LED Definition Fast Ethernet Port LEDs Table 5 2 describes the indications given by the fast Ethernet port LEDs P5 refer to Figure 2 2 for the location of the port These LEDs are integrated into the Ether net port Table 5 2 Fast Ethernet Port LEDs Indication Left LED LED2 Right LED LED1 Link integrity bad No RXD or TXD activity Link integrity good and RXD or TXD activity and 10 Mbps Ethernet half duplex Ethernet Link integrity good and RXD or TXD activity and 100 Mbps Ethernet full duplex Ethernet
26. CELLIER Kunu m BERR RRR e ce ee ee o ee ee o ee eo ee ee o ee ee ee ee 00 eo ee ee e e e e e e e e e e a e e o O e e e e e 8 e e e e e e e e e e e O CRI CRO CR2 CR3 I 1 801 45 6 1 939 _ INCHES 49 3 MILLIMETERS _ a p 2 189 _ B 2 301 6 0 2 439 989 _ 2 551 62 0 2 689 64 8 68 3 T00156A Figure A 2 EP405 Board Mechanicals Bottom 700M0067RC 1 57 Appendix Mechanical Dimensions 58 Computing Engines EP405 1 5 mau 0 528 XXXI XXXI 0 368 134 de sooes LUMM sssss oe 6 4 0452 11 5 0 683 0 683 0 062 74 0 661 T 174 1 6 0 680 16 8 17 3 1 132 288 4358 L 29 4 1841 B 46 8 1 951 u L 496 2613 _ B 66 4 5734 A 69 4 L 3 423 95 9 L 3 775 _ 95 9 B 0 355 INCHES a poi D MILLIMETERS 0 138 0 136 ro ae O 0 433 y 0 258 110 6 5 i 0 089 0 429 L 23 0 136 MES 9 159 0 605 NOTE 0 840 154 1 MAXIMUM COMPONENT HEIGHT ON BOTTOM OF BOARD 538 WITHOUT PCI CONNECTOR IS 0 200 INCHES 5 1 MM B 1 000 _ 25 4 T00114B
27. CSR registers refer to Chapter 7 Upon power up or after reset no interrupt line is dedicated to any IRQ pin on the processor The following table identifies the possible IRQ lines that an onboard device or external peripheral could route to an IRQ signal via BCSR con trol Table 10 1 Interrupts Device Definition SYSERR System error STTM Serial temperature and thermal monitor RTC NVRAM real time clock FENET Fast Ethernet NB PCI North Bridge PCI bridge SB PCI South Bridge local or external PCI interrupt controller RI Serial port 0 ring indicator XIRQ0 External IRQ 0 XIRQ1 External IRQ 1 XIRQ2 External IRQ 2 XIRQ3 External IRQ 3 XIRQ4 External IRQ 4 XIRQ5 External IRQ 5 XIRQ6 External IRQ 6 NOTE 1 Selectable using BCSR4 Table 7 2 2 If an external PCI interrupt controller is used the SB IRQ should be routed from the South Bridge device to the EP405 through connector P8A at pin B30 This is normally a reserved RSVD pin 700M0067RC1 53 54 Computing Engines EP405 1 5 700M0067RC1 Mechanical Dimensions 700M0067RC1 This appendix contains mechanical dimension drawings needed to design the EP405 board into a product Figures A 1 A 2 A 3 and A 4 show the dimensions for the EP board NOTES 1 The dimensions in this document are believed correct but if this unit is to be placed into a housing that has cut outs an actual unit must be procured to ve
28. G Description Reserved Leave at reset state CEO Disabled ECC is not used CE1 Disabled ECC is not used CE2 Disabled ECC is not used CE3 Disabled ECC is not used Reserved Leave at reset state Table 8 6 SDRAM Power Management Idle Timer SDRAMO_PMIT Description Optional Defines the number of clock cycles that the SDRAM controller must be idle before a sleep request is asserted Power management SDRAMO_CFG PME 1 must be enabled Count is from 0 to 31 11111 Always 11111 Reserved Leave at reset state 700M0067RC1 49 50 Computing Engines EP405 1 5 700M0067RC1 I2C Devices and Addressing Chapter 9 The EP405 board has two devices on the I2C bus These two devices are a serial EEPROM SEP and a serial temperature and thermal monitor STTM Table 9 1 12C Address Map Device Function I2C Addressing SEP Configuration information OxA8 A9 for 1K 2K devices 128 256 x 8 OxA8 AB for 4K device 512 x 8 OxA8 AF for 8K device 1K x 8 STTM Serial temperature and thermal 0x90 91 8 bytes in device monitor The I2C bus also routes to the bus expansion header for possible use on expansion board designs The I2C interface pin SDA from the processor must be pro grammed as open drain The DC interface pin SCL from the processor does not necessarily have to be programmed as an open drain signal because presently there are no other master
29. M0067RC 1 Computing Engines EP405 1 5 STTM I O EBC Bus Expansion 700M0067RC 1 Chapter 2 Description BBEBBBBEBBBEBBEBBBEEBBEE A1 SW1 CR1 CRO CR2 cr B 0000 n 8 6 6 8 LEDS T00107C Figure 2 3 EP405 Board Bottom View The serial temperature and thermal monitor STTM is an onboard temperature sensor The STTM part is a 2 wire digital temperature sensor Its functionality is equivalent to the Microchip TCN75 part The minimum resolution provided by this part is a 9 bit temperature conversion Refer to the Chapter 9 for program ming information for this I C device The EP board has e One fast Ethernet port P5 This port uses a Level One LXT971A Ethernet transceiver The port connects to the MII port of the processor Communica tion is via the MII management port The tast Ethernet PHY address is either 0b00000 default or 0600001 depending on strapping option Table 3 2 Two serial port headers P6 and P7 The ports use UARTO and UARTI of the processor The serial ports use Maxim MAX3245E RS 232 transceivers or equivalent One JTAG port header P3 with right angle connector for debugger use One TRACE port header P4 with right angle connector for debugger use Refer to Chapter 4 for more information and pinouts for the connectors The EBC bus from the processor s external bus controller is brought out to the EBC bus expansion connector P1 P10 P2 P11 on
30. O_RTR ss 49 SDRAM ECC Configuration Register SDRAM0_ECCCFG 49 SDRAM Power Management Idle Timer SDRAM0_PMIT 49 PEA Mitra 51 A e mu uuu een 53 7 Computing Engines EP405 1 5 700M0067RC1 Introduction Chapter 1 The EP405 board is a highly integrated single board computer SBC based on the IBM PowerPC 405GP or 405GPr processor The EP board is in a PC 104 Plus board mechanical form factor and provides for PCI bus interface It does not con tain ISA functionality directly an add on expansion card can provide the ISA bus interface Functions The functions included on the EP405 are listed in Table 1 1 Table 1 1 Hardware Features Entity Function Processor PPC405GP up to 200 MHz or PPC405GPr up to 400 MHz SDRAM 16 32 64 128 MBytes FLASH 4 8 16 32 64 MBytes NVRTC 0 32 128 512 KBytes Top 16 bytes are the real time clock RTC Ethernet port 10BaseT 100BaseTX RJ 45 Serial port RS 232 UARTO 9 wire full modem control 2 x 5 header UART1 5 wire interface 2 x 5 header PCI PC 104 Plus connector 33 MHz PCI SYNC synchronous or 66 MHz PCI ASYNC asynchronous clocking modes supported Serial EEPROM I2C Serial temperature and thermal 12C monitor Debug JTAG RiscWatch for BDM TRACE RiscTrace for BDM Dipswitch 4 position slide switch read via status register
31. P board EARTH_GND and DIGITAL GND should be connected at only one point in the system Erratic behavior could occur if ground loops are induced into the system through multiple connections NOTE All connector housings e g Ethernet serial etc are connected to EARTH_GND JTAG Debug Port The JTAG debug port is P3 It is a 2 x 7 0 1 x 0 1 header Table 4 1 shows the JTAG debug port pinout Table 4 1 JTAG Debug Port Pinout P3 Function i Function 18 14 15 16 GND NOTE 1 Current limited with a 1K resistor TRACE Port The TRACE port is P4 It isa 2 x 10 0 1 x 0 1 header Table 4 2 shows the TRACE port pinout Table 4 2 TRACE Port Pinout P4 Function i Function 24 700M0067RC1 Computing Engines EP405 1 5 Chapter 4 Connectors and Headers Table 4 2 TRACE Port Pinout P4 continuea Function i Function Fast Ethernet Port Serial Port 0 Serial Port 1 700M0067RC1 The fast Ethernet 10BaseT 100BaseTX port is connector P5 FETH It is a shielded RJ 45 jack with integrated LEDs Table 4 3 shows the RJ 45 jack pinout The RJ 45 connector is shielded and tied to EARTH GROUND This Ethernet port is from the MII Table 4 3 Fast Ethernet Port Pinout P5 Function i Function 1 TXD 5 2 TXD 6 RXD 3 RXD 7 4 8 NOTE 1 Pin numbering is from rig
32. before selecting the desired routing Table 7 6 700M0067RC1 41 Chapter 7 Board Control and Status Registers Table 7 8 BCSR7 XIRQ Status Onboard Byte Address F400 0007 reset value 0000 0000 NOTE 1 Refer to Table 10 1 for interrupt definitions Function XIRQ source Computing Engines EP405 1 5 Definition State of SYSERR State of STTM State of NVRTC State of FENET State of NB State of SB State of RI Unused Table 7 9 BCSR8 XIRQ Status External Byte Address F400 0008 reset value 0000 0000 NOTES Function XIRQ source NN NO OI CGO D O Definition State of XIRQ0 State of XIRQ1 State of XIRQ2 State of XIRQ3 State of XIRQ4 State of XIRQ5 State of XIRQ6 Unused NO GT E ON O 1 Refer to Table 10 1 for interrupt definitions 2 BCSR10 enables XIRO 0 6 functionality Table 7 11 Table 7 10 BCSR9 Switch Status and LED Control Byte Address F400 0009 reset value uuuu 1111 42 Function Switch status Definition Dipswitch BCSR9 3 is position 1 on switch Switch closed logic 0 on Switch open logic 1 off LED control NN IO OI CGO D O LEDs BCSR9 7 is CR0 0 LED on 1 LED off Computing Engines EP405 1 5 Table 7 11 BCSR10 GPIO 17 23 or IRQ 0 6 Select and PAR Control Byte
33. ctor consists of P1 P10 and P2 P11 Each is a 5 x 20 high density receptacle This interface allows add on boards to be designed and interfaced directly to the EP board through the EBC bus EP board to expansion card spacing is not fixed The connector type chosen allows for variable stacking heights The receptacle part number used on the stan dard product is Samtec YFS 20 03 G 05 SB Refer to the Samtec Hi Density Stacker fact sheet for expansion card mating plug options YFI 20 xx y 05 zz or YFW 20 xx y 05 zz NOTE W and T are two different styles for the expansion card mating plug both are compati ble with the EP board The W gives several height options The board to board spacing can be adjusted by selecting one of the available Samtec mating connectors and appropriate stand offs Stand offs should be 3 16 inch hex metal stand offs so that EARTH_GND connections can be made from the expansion card to the EP board The stand offs should also have 4 40 threads to accommodate the 0 125 inch diameter mounting holes in the PCB NOTE Either 16 mm board spacing or cut outs in the expansion card are required to clear the RJ 45 connectors on the EP board The EP405 EBC bus expansion connector P1 P10 P2 P11 interface must be a 3 3 VDC only type of interface the I O is not 5 VDC I O tolerant 700M0067RC1 Computing Engines EP405 1 5 Chapter 4 Connectors and Headers Refer to Figure 4 1 for the P1 P10 connector pinout and Figure 4 2
34. e EP405 1 5 board silk screen Refer to Figure 4 1 Some EBC signals on the EP405 1 5 board no longer go through the CPLD In the documentation signals that go through the CPLD are identified with an x_ prefix The x_ has been removed in the EP405 1 5 board documentation for those signals that now connect directly to the processor The EP405 1 5 board supports up to 64 MBytes of FLASH memory using AMD MirrorBit FLASH devices The FLASH configuration is one bank and two FLASH devices refer to Figure 2 4 Each FLASH device is configured for 16 bit mode BYTE 3 3 VDC The EP405 1 3 1 4 boards support up to 32 MBytes of FLASH memory The FLASH configuration is two banks address decoding performed in CPLD and four FLASH devices two devices per bank Each FLASH device is configured for 16 bit mode BYTE 3 3 VDC The PLL clock driver Cypress W185 on the EP405 1 3 1 4 boards has been replaced by an MPC9446 clock buffer on the EP405 1 5 board As a result spread spectrum clocking is no longer supported The EP405 1 5 board uses a smaller dipswitch than the EP405 1 3 1 4 boards Also the location of the dipswitch has changed Refer to Figure 2 3 A jumper JP1 was added to configure the COP JTAG port Refer to Table 3 1 How to Use This Manual 1 Refer to Chapter 2 for a description of the board features and functions 700M0067RC1 Computing Engines EP405 1 5 Chapter 1 Introduction 2 Refer to Chapter 3 for setup in
35. e SDRAM controller can be started and memory accessed This involves writing to the fol lowing registers SDRAM configuration register SDRAMO_CFG e SDRAM memory bank configuration registers SDRAMO_BnCR e SDRAM timing register SDRAMO_TR e SDRAM refresh timer register SDRAMO_RTR e SDRAM ECC configuration register SDRAMO_ECCCFG e SDRAM power management idle timer SDRAMO_PMIT Refer to SDRAM Organization in Chapter 2 for a description of the SDRAM mod ules Refer to Tables 8 1 through 8 6 for the SDRAM register settings Table 8 1 SDRAM Configuration Register SDRAMO_CFG Description Enable SDRAM controller Important Set this only after a 100 usec Micron or 200 usec Samsung delay from power up and after all SDRAMO_xxxx registers have been initialized SRE Disable self refresh used for power management optional PME Disable power management optional MEMCHK Disable error checking optional REGEN Disable registered synchronized memory A registered SDRAM is a memory mod ule with onboard buffers that are driven via the SDRAM clock The buffers are regis tered to the SDRAM system clock 32 bit SDRAM width 16 bytes of burst read prefetch Place ECC 0 7 pins in high Z state ECC is not used 700M0067RC1 47 Chapter 8 SDRAM Programming Field EMDULR Computing Engines EP405 1 5 Table 8 1 SDRAM Configuration Register SDRAMO_CFG continued Descripti
36. for the P2 P11 connector pinout NOTE In Figures 4 1 and 4 2 the n appended to a signal name indicates active low The x at the beginning of a signal name means external 700M0067RC1 27 8 94 900N00 P1E P10A AO E1 A1 E2 A2 E3 5 A3 E4 O ES O A4 E6 5 A5 E7 G A6 E8 5 A7 E9 5 E10 O A8 Eil 5 A9 E12 O A10 E13 5 A11 E14 5 E15 O A12 E16 5 A13 E17 5 A14 E18 5 A15 E19 5 E20 G P1C P10C P1A P10E PENNEN Cito x CFG11 GPIO1 TS1E Al o 02109 x CFG12 GPIO2 TS2E A2 O 3109 x_GPIO3_TS10 A3 O 5 0V O C4 10 x_CFG21_GPIO4_TS20 PALO cs 5 x ass 6109 x_GPIO5_TS3 AGB O xC7 oO x_GPIO6_TS4 AT LO P O x_GPIO7_TS5 A8 O 5 0V O C9 LO x GPIO8 TS6 A9 O eo A10 Lo PS o x GPIO9 TRCCLK AMO 1210 x_perCSm gt Al2 O C1316 x_GPIO10_perCSin ABS 614 LS x_GPIO11_perCS2n A14 oO 4 015 y 480 016 0O x GPIO12 perCS3n A16 LO LAT O x_GPIO13_perCS4n Al o c18 o x_GPIO14_perCS5n A18 5 0V O C19 O x_GPIO15_perCS6n A19 Lo P1D P10B P1B P10D DO EOTO_TCO B1 DC E EOT1_TC1 B2 5 D2 D3 EOT2_TC2 B3 S D3 D4 S EOT3 TC3 B4 5 D5 5 lt E D6 Ds 5 B8 5 O D10 5 lt _ 10__o D8 D11 BI o D9 D12 O perCSOn B12 O D10 D13 S perERR B13 G
37. formation including option straps and dipswitch settings 3 Refer to Chapter 4 for a description of the connectors and headers available on the board 4 Refer to Chapter 5 for a description of the LED indications for the board and Ethernet port 5 Refer to Chapter 6 for chip select information 6 Refer to Chapter 7 for board control and status register BCSR programming information 7 Refer to Chapter 8 for SDRAM programming information 8 Refer to Chapter 9 for programming information for the onboard C devices 9 Refer to Chapter 10 for information about the possible interrupts and inter rupt routing Reference Documents 700M0067RC1 Table 1 2 lists additional Embedded Planet documents for the EP board Table 1 2 Reference Documents Document Number 700M0070R PlanetCore PPC4xx Boot Loader Description 700M0071R PlanetCore PPC4xx FLASH Burner 700M0079R__ PlanetCore PPC4xx Diagnostics and Utilities Computing Engines EP405 1 5 700M0067RC1 Description Chapter 2 This chapter provides some description of the EP405 board features including the PowerPC processor external interfaces bus expansion and PlanetCore Figure 2 1 is a simplified block diagram ot the EP board Figures 2 2 and 2 3 show the top and bottom view board layouts These figures show the headers unpopu lated i e without pins or connectors
38. ht 1 to left 8 when looking into the RJ 45 jack with the locking tab on top The serial port 0 UARTO is P6 Itisa2x 5 0 1x 0 1 header Table 4 4 shows the serial port pinout The port signals are surge protected with the transient voltage suppressors connected to EARTH GROUND The port is wired as DTE Table 4 4 Serial Port 0 Pinout P6 Function i Function The serial port 1 UART1 is P7 It is a 2 x 5 0 1 x 0 1 header Table 4 5 shows the serial port pinout The port signals are surge protected with the transient voltage suppressors connected to EARTH GROUND The port is wired as DTE 25 Chapter 4 Connectors and Headers 26 Computing Engines EP405 1 5 Table 4 5 Serial Port 1 Pinout P7 Function i Function NOTE 1 DTR can be driven via strapping option Table 3 2 by the RTS signal or by the system 5 VDC supply PC 104 Plus Connector The PC 104 Plus connector is P8 It is a standard 4x 30 2 millimeter connector as defined by the PC 104 Plus specification This interface allows PCI add on boards to be designed and interfaced to the EP board The PC 104 Plus connector is a through hole connector which means it can be populated on the top of the board only bottom of the board only or both top and bottom if desired Refer to the PC 104 Plus specification for pinout information EBC Bus Expansion Connector Important The EBC bus expansion conne
39. nal to CPU 43 Chapter 7 Board Control and Status Registers Computing Engines EP405 1 5 Table 7 13 BCSR12 GPIO 9 16 Direction Control Byte des Function Definition F400 000C GPIO direction control O RAW 0 GPIO9 output CPU to external 1 GPIO9 input external to CPU reset value 0000 0000 1 RAW 0 GPIO10 or CS1 output CPU to external 1 GPIO10 input external to CPU 2 RAW 0 GPIO11 or CS2 output CPU to external 1 GPIO11 input external to CPU 3 RW O GPIO12 or CS3 output CPU to external 1 GPIO12 input external to CPU 4 RO 0 GPIO13 or CS4 output CPU to external 5 RW 0 GPIO14 or CS5 output CPU to external 1 GPIO14 input external to CPU 6 RW O GPIO15 or CS6 output CPU to external 1 GPIO15 input external to CPU 7 RWW O GPIO16 or CS7 output CPU to external 1 GPIO16 input external to CPU NOTE 1 CS4 is always used CPU to external since it is used as the BCSR chip select Table 7 14 BCSR13 GPIO 17 23 Direction Control Byte Address F400 000D reset value 0000 0000 NOTE 1 BCSR10 selects either GPIO 17 23 or IRQ 0 6 functionality Table 7 11 44 Function GPIO direction control Mnemonic GPIO17_DIR Definition 0 GPIO17 output CPU to external 1 GPIO17 input external to CPU GPIO18_DIR 0 GPIO18 output CPU to external 1 GPIO18 input external to CPU GPIO19_DIR 0 GPIO1
40. nfigures P3 as either a JTAG port or a COP port Table 3 1 describes the jumper settings refer to Figure 2 2 for the location of the jumper Table 3 1 JP1 Jumper Purpose Setting Function COP P3 operates in COP mode to support hardware and software development and debugging JTAG CPLD only JTAG chain active at P3 These settings put only the CPLD in the JTAG chain JTAG complete JTAG chain active at P3 These settings complete the JTAG chain from P3 to the processor the processor to the CPLD then the CPLD to P3 Straps Table 3 2 describes the various strap settings refer to Figures 2 2 and 2 3 for the locations of the straps Table 3 2 Strap Settings Purpose Function Earth ground RO1 Populated EARTH_GND connected to DIGITAL_GND at one point Not populated EARTH_GND not connected to DIGITAL_GND FENET PHY RO6 1 2 PHY address 00000 address RO6 1 3 PHY address 00001 UART1 RO7 1 2 RS 232 transceiver drives the DTR true all the time 5 VDC minimum at 1 67 mA RO7 1 3 5 VDC rail drives the DTR signal all the time for powering IR keyboards PCI VIO ROA10 3 3 VDC VIO supplied ROB10 5 VDC VIO supplied M66EN signal RO12 in Force 33 MHz operation M66EN signal low RO12 out Normal operation NOTES 1 All mounting holes and shields on connectors are connected together and to EARTH_GND 2 Only one resistor option populated at a time 700M0067RC1 21
41. on Disable memory data unless read option Reserved BA Leave at reset state Description Set the base address to 0x00000000 Reserved Leave at reset state SZ Size of the SDRAM module being used where xxx is 010 16 MByte module 011 32 MByte module 100 64 MByte module 101 128 MByte module Reserved Leave at reset state AM Addressing mode where xxx is 011 mode 4 12 x 8 x 4 16 MByte module 001 mode 2 12 x 9 x 4 32 MByte module 010 mode 3 13 x 9 x 4 64 MByte module or 13 x 10 x 4 128 MByte module Reserved Leave at reset state BE Reserved Memory bank enable where x is 1 to enable physical bank if SDRAM is populated 0 to disable physical bank if SDRAM is not populated Table 8 3 SDRAM Timing Register SDRAMO_TR Description Leave at reset state CASL Set SDRAM CAS latency where xx is 01 CAS latency 2 clks 100 MHz 10 CAS latency 3 clks 133 MHz Reserved Leave at reset state PTA tRP Precharge to next activate command 20 nsec minimum where xx is 10 3 clks minimum 100 MHz 11 4 clks minimum 133 MHz tWR or tRD Read write to precharge command 20 nsec minimum where xx is 01 2 clks minimum 100 MHz 10 3 clks minimum 133 MHz tCMS tSS tCS Command leadoff 2 nsec Micron CMS Samsung tSS where xx is 01 2 clks minimum 100MHz 10 3 clks
42. onal TmrClk input control 0 disable TMRCLK logic 0 1 enable TMRCLK PerCLK 5 POR control 0 system will not be POR 1 system will be POR NOTES 1 BCSR2 7 must be set to a 1 for this bit to POR the system 2 This bit is self clearing if setto a 1 and BCSR2 7 1 0 POR reset function is disabled 1 POR reset function is enabled NOTES 1 This bit must be set to a 1 for the BCSR2 6 bit to be functional 2 This bit and the BCSR2 6 bit can be set to a 1 simultaneously to initiate a system POR 700M0067RC1 Computing Engines EP405 1 5 Chapter 7 Board Control and Status Registers Table 7 4 BCSR3 FENET and UART Control Byte Address Function Definition F400 0003 FENET control 0 RW O disable FETH PHY 1 enable FETH PHY reset value 0000 0000 1 RW 0 power down and tri state all MII transceiver signals 1 power up and enable MII transceiver signals UART control 2 RAW 0 disable UARTO transceiver 1 enable UARTO transceiver 3 RW 0 disable UART1 transceiver 1 enable UART1 transceiver RO 0000 200 MHz Ro 0001 266 MHz 0010 333 MHz RO 0011 400 MHz RO CPU speed N O 0 amp NOTE 1 BCSR3 1 must be set before BCSR3 0 is set BCSR3 0 should be reset before BCSR3 1 is reset Table 7 5 BCSR4 PCI Status and Masking Byte Address F400 0004 PCI IRQ status O PCI INTA is not pending 1 PCI INTA is
43. onfiguration Register EBCO_BOCR or EBC0_B7CR e Peripheral Bank Access Parameters EBCO_BOAP or EBCO_B7AP The FLASH memory can use either PerCS0 or PerCS7 depending on BCSR2 Table 7 3 PerClk is 50 MHz The register settings are for a 64 MByte block and based on 70 nsec FLASH Table 6 2 FLASH Peripheral Bank Configuration Register EBC0_BnCR Description Base address select Specifies the bank starting address The bank starting address must be a multiple of the bank size programmed in the BS field 64 MByte bank 700M0067RC1 read write 33 Chapter 6 Chip Select Programming 34 Computing Engines EP405 1 5 Table 6 2 FLASH Peripheral Bank Configuration Register EBC0_BnCR continued Field BW Description 32 bit bus Reserved Leave at reset state NOTE At POR EBCO_BOCR Oxffe28000 2 MByte read only Table 6 3 FLASH Peripheral Bank Access Parameters EBC0_BnAP Description 0 BME 0 Bursting disabled 1 8 TWT 00000100 Transfer wait 4 PerClk cycles 9 11 Reserved Leave at reset state 12 13 CSN 00 Chip select on timing O PerClk cycles 14 15 OEN 00 Output enable on timing 0 PerClk cycles 16 17 WBN 00 Write byte enable on timing 0 PerClk cycles 18 19 WBF 00 Write byte enable off timing 0 PerClk cycles 20 22 TH 000 Transfer hold 0 PerClk cycles 23 RE 0 Disable PerReady 24 SOR 0 Sample on
44. pending reset value 0000 1111 0 PCI INTB is not pending 1 PCI INTB is pending O PCI INTC is not pending 1 PCI INTC is pending 0 PCI INTD is not pending 1 PCI INTD is pending PCI IRQ masking 2 0 PCI INTA is enabled 1 PCI INTA is masked 0 PCI INTB is enabled 1 PCI INTB is masked O PCI INTC is enabled 1 PCI INTC is masked O PCI INTD is enabled 1 PCI INTD is masked Function i Definition NOTES 1 A masked INT level will not generate an IACK vector if that respective level is asserted or pending 2 When an INT level is masked its status is still available via BCSR4 0 through BCSR4 3 3 Select and route the SB device to use PCI INTA INTB INTC and INTD All four PCI interrupts are routed to a single processor interrupt Check BCSR4 to determine which PCI interrupt occurred 700M0067RC1 39 Chapter 7 Board Control and Status Registers Computing Engines EP405 1 5 Table 7 6 BCSR5 XIRQ Select Byte Address F400 0005 Unused Function i Definition reset value 0000 0000 XIRQ index Function Select SYSERR Select STTM Select RTC Select FENET Select NB Select SB Select RI Reserved Select XIRQ0 Select XIRQ1 Select XIRQ2 Select XIRQ3 Select XIRQ4 Select XIRQ5 Select XIRQ6 Reserved O O NN O O O D O St O O IO O C
45. rify all required connector cut outs In addition the vendor s data sheets for the connectors should be referenced to deter mine the tolerances of the connectors 2 An add on card can be designed with cut outs to clear high components on the EP board if necessary 3 The PC 104 Plus connector P8 is a through hole connector which means it can be pop ulated on the top of the board only bottom of the board only or both top and bottom if desired 4 The EBC connectors P1 P10 P2 P11 are surface mount connectors They can be pop ulated on either the top or the bottom of the board Figure A 1 shows the connector locations on the top of the board Their locations on the bottom of the board are exactly the same Fig A 2 The drawing shows the locations of the key holes for placing the connectors 5 The pin headers can optionally be populated with either straight pins or right angle pins Figure A 4 shows the pin dimensions The right angle pins extent 0 33 inches 8 4 millimeters past the edge of the board as shown in the figure Appendix 55 96 94 900IN00 3 575 2 874 73 0 0 591 15 0 300 m 7 6 0 120 3 0 3 200 81 3 3 260 82 8 INCHES MILLIMETERS 3 460 3 380 87 9 3 355 85 2 gt T00104D Figure A 1 EP405 Board Mechanical Top SUOISUSUI edIueygay V Xipuaddy G sopd3 seuiBuz Buyndwog Computing Engines EP405 1 5 Appendix Mechanical Dimensions
46. rol GPIO 1 8 direction control GPIO 9 16 direction control GPIO 17 23 direction control CPLD code revision Definition ID 0000 0111 EP405 revision 1 5 37 Chapter 7 Board Control and Status Registers Table 7 2 BCSR1 PCI Control and Status Byte Address F400 0001 reset value 0000 0000 Function Reserved Computing Engines EP405 1 5 Definition Reads back 1 PCI bus speed status M66EN 0 33 MHZ PCI 1 66 MHZ PCI Reserved Reads back 0 PCI IRQ control 0 disable local PCI IRQ routing and status 1 enable local PCI IRQ routing and status PCI clocking status 0 33 MHz SYNC mode 1 66 MHz ASYNC mode Reserved Reads back 0 Table 7 3 BCSR2 FLASH NVRAM and POR Control and Status Byte Address F400 0002 reset value 0000 0000 38 Function FLASH control and status Definition 0 CS0 usable on expansion FLASH CS7 can be enabled to local FLASH 1 CS0 enabled to local FLASH CS7 not used on EP405 NOTE BCSR2 1 must be a 1 to enable CS7 to local FLASH 0 CS7 not used on EP405 1 CS7 enabled to local FLASH NOTE Only functional if BCSR2 0 1 0 local FLASH is write protected 1 local FLASH is not write protected 0 FLASH operation executing and busy 1 FLASH operation complete NVRTC control O disable CS4 to NVRTC 1 enable CS4 to NVRTC NOTE When disabled RTC is still functi
47. the board This allows inter facing add on boards to the processor The C bus is also routed to the connector Chapter 2 Description PCI Interrupt Control Computing Engines EP405 1 5 The PCI bus from the processor s PCI interface is brought out to the PC 104 Plus connector P8 The PPC405GP GPr processor provides the host PCI bridge com monly referred to as North Bridge and a PCI arbiter There is onboard IRQ routing and status features implemented in a CPLD that can be enabled or disabled by setting bits in a BCSR register This along with the inter rupt controller of the processor provide board and PCT interrupt request control If desired an add on board can provide the PCI IRQ controller along with a PCI to ISA bridge commonly referred to as South Bridge NOTE The EP405 board supports PCI host mode only PowerPC Processor The EP board incorporates an IBM PowerPC 405GP or 405GPr embedded proces sor This 32 bit reduced instruction set computer RISC processor includes an integrated PowerPC core and peripheral interfaces that can be used in a variety of controller applications It is particularly well suited for both communications and networking applications The PPC405GP GPr provides high performance and low power consumption The processor has integrated peripheral functions for I O interface which include e SDRAM controller e External bus controller EBC e PCI bus interface e Direct memory access
48. uous address space I O Interface Signals Table 2 2 lists the I O interface signals used on the EP board Table 2 2 1 0 Signals Interface Signal Serial ports UARTO_DCD UARTO_DSR UARTO_DTR UARTO_RI UARTO_RTS UARTO_Rx UARTO_TX UART1_CTS JUART1_DSR UART1_DTRJUART1_RTS UART1_Rx UART1_Tx Ethernet EMCMDIO PHYMDIO EMCTxDO EMCTxD1 EMCTxD2 EMCTxD3 EMCTxEn EMCTxErr PHYCol PHYCrS PHYRxCIk PHYRxDO PHYRxD1 PHYRxD2 PHYRxD3 PHYRxDV PHYRxErr PHYTxClk IICSCL IICSDA 700M0067RC1 19 Chapter 2 Description PlanetCore Boot Loader Diagnostics and Utilities FLASH Burner 20 Computing Engines EP405 1 5 PlanetCore consists of Target based application boot loader e Host based FLASH burner PlanetCore is included with each Embedded Planet software development plat form and computing engine The EP board is shipped with the boot loader program residing in FLASH mem ory The boot loader utilities provide the ability to initialize the CPU board and auto execute an operating system or application Refer to the PlanetCore User Manuals for complete information about these utilities The boot loader has the following features and benefits Small memory footprint lt 256KB e Boots quickly e Can optionally test the DRAM during startup Command line interface via monitor port has
49. x Planet Blue Planet RPX LITE and RPX LICC are trademarks or registered trademarks of Embedded Planet Freescale and PowerQUICC are trademarks of Freescale Semiconductor Inc IBM and PowerPC are registered trademarks of International Business Machines Inc Wind River Systems VxWorks and Tornado are registered trademarks of Wind River Systems Inc All other names and trademarks are the property of their respective owners and are hereby acknowledged Computing Engines EP405 1 5 700M0067RC1 Computing Engines EP405 1 5 Contents Chapter 1 Introduction anne den i a re 9 ETO u suu mu ss D 9 EP405 1 5 Versus EP405 13 14 ais a oo 10 Howto Use This Manual 10 Reference DOCUMENTS en ee nern 11 Chapter 2 Description si i i e i i 13 Pole I iO S SOL u iii i i r e i i p a 16 EBS DOS EAS O SG ias a a rue 16 DERAM OPS Sha OK putas 17 PLA SF T b 7 O0 ee OE a nd ie 17 I Ci AG nd Spira 19 ii C DLE uu a i a a i E IS ne 20 Chapier ELL u u u ausi une einu aa a sk i i P i p a a iai 21 JG ES sis ii ai a i i i a i i a E 21 LEAD S ono i a i aaa Aon as 21 RI WAC Wr sory i i i a a i na 22 Chapter 4 Connectors and Headers J 23 BOWIE x ia E i a ao a a aa i o a a 23 Power CORRE LO ios 23 kp S 0100 C IT aka i ai as ai k a i i 23 Harto ib ul u ii i i i i i a ii i
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