1 My board “Family” is C8051F34x-DK Trouble
Contents
1. PLO PLT 23 0 P3 7 19 Instructions amp Addressing 7F The 8051 has five addressing modes and IF five groups of instructions m i Direct Addressing instructions using direct addressing are two bytes long an 8 19 bit op code followed by 8 bit address 4 The address is either byte location 16 specific bit in a bit addressable byte 13 Indirect Addressing instructions 12 l specify a register which contains the 0 address of the operand Must instructions which use indirect addressing are only 1 00 byte long making them efficient z execution time and space 0A 09 8 bit addresses use registers RO R7 16 bit addresses use the DPTR register 05 Bank 02 Register Instructions Register instructions use the contents of of Ro one of the registers RO R7 as the Working operand Always 1 byte long A few register specific ipis i addresses are shown to the left bit addresses registers shown inside 20 Table 2 2 Predefined bit addresses for 8051 Bit Bit Table 2 3 Predefined data addresses Symbol position address Meaning for 8051 Hexadecimal Symbol2. Target S06 1F 10 Tool Evol Piaclide c290E11200 h date point er Timers Timer ter PAD Module 3 1 Stop execution of example program Copyright 2005 77 AUTH DATE 11 01 ilizc amp Laboostories This 1 cohen the ar LED tha 0051720 targa fave tases seccod wring the interrupt hendler icr Timer Tarpet Tool chain Eval include 4 80516200 16 021 SER Definitions foy PCA0 Mocule 2 ui gt AD emnt ter nc SEP Step through program it woazate an ii ferta specified by wing SILK 46 ate ta void Tis Init int counter TIRON Tia zcuiins changem the xtate of the LED whenever Timer void Tisar2 ISR void intermupe 0 clear Timer _ L IED change xtate c O a me g BEES ni AUTH BV 7 DATE 11 OCT Ot Thio prossem floshes the ccn L 29O05LF3 m tory fiv meccnd using the is y 17 7 Target 9051710 47 Tool cobain Eval 1 7 16 bit Definiticns for s ri DP eerie 1212241 THF PCAOCE atrit PCAOCPZ 2 16 Set a breakpoint Pe Eat Yww foet Debug Toce Ure fb semm ms onfigure Tis autc re 18 gaterve
3. Priority Internal Digital Signals Lowest Priority 1 Port Latches IS TSCLK 0 0 0 7 a 1 7 8 P2 0 P2 7 g P3 0 P3 7 ABRO XBR1 ABR2 PIMDIN Ri PUMDOUT PIMDOUT P2MDOUT P34DOUT 1 To Extemal Memory al Interface pu npe Figure 2 6 Block Diagram of Lower Port I O to P1 0 P1 7 P2 0 P2 7 DGHD 20 0 E p2 7 Av E m Analog Power bB pi 0 ArNi B 7 E Tor E ir me o nsT E VDD SFR Bus gt G4kbyte FLASH External Data Memory Bus Bus Control Address Bus Data Bus Figure 2 3 Block Diagram of 8051 020 Specs Analog Peripherals 10 Bit ADC C8051F340 1 2 3 4 5 6 7 A B only Up to 200 ksps Built in analog multiplexer with single ended and differential mode VREF from external pin internal reference or VDD Built in temperature sensor External conversion start input option Two comparators Internal voltage reference C8051F340 1 2 3 4 5 6 7 A B only Brown out detector and POR Circuitry USB Function Controller USB specification 2 0 compliant Full speed 12 Mbps or low speed 1 5 Mbps operation Integrated clock recovery no external crystal required for full speed or low speed Supports eight flexible endpoints 1 kB USB buffer memory Integrated t
4. i Transistor V uppl T closed switch SHpP y Vous GROUND Current into gate equivalent circuit Vout Output is either grounded or floating Transistor OFF external pull up resistor is open switch required to produce a high Vout pulled to Vsupply output Current from supply Open Collector outputs are low powered solid state switches Although the term Open Collector stipulates the use of bipolar transistors NPN type or PNP type as a switch nowadays Field Effect Transistors FET or MOSFET are used Unlike electro mechanical switches e g pushbuttons or dry contact relays these OC switches are very fast use little power are inexpensive do not bounce and do not wear However OC s are also more limited in terms of voltage and current rating as well as being polarized i e they have a plus and minus terminal and thus DC only switching capability They are less tolerant to overload abuse than electromechanical devices Usually these switches have higher resistance and voltage drop Totem pole outputs Only one at one time 4 Ve Vec Y k 3 Vout 3 t output low Output high n Y Transistor acts like a switch Upper transistor OEE Upper transistor ON Output isa voltage divider Lower transistor ON Lower transistor OFF Looking al Transisior Level Looking Remember that gates are made fr
5. 16 Alternate Functions all the pins of port 3 have an alternate function enable alt function by writing a 1 to the corresponding bit in the port latch SPI full duplex A serial port interrupt is issued in order to read or write serial port data Reciever frame double buffered keep receiving while servicing Tx and Rx buffers are accessed at the same location in the SFR space the SBUF register Writing loads Tx reading offloads Rx Four modes of operation 0 half duplex synchronous Tx and Rx but not simultaneous TXD and RXD for synchronous operation Mode 1 full duplex async Data and out through RXD and TXD Frame Start Bit 8 data bits Stop Bit Interface for data is SBUF Mode 2 Similar to mode 1 with two exceptions 9 data bits ninth bit obtained from TB8 SCON baud rate determined by SMOD in PCON reg is 1 32 or 1 64 of oscillator frequency Mode 3 same as mode 2 except baud rate is variable PCON of the 8 bits in the PCON power control register only bit 7 SMOD is implemented in the standard 8051 17 Interrupts replaces polling and buffering 5 sources of interrupts Two from external pins INTO and INT1 Two from the Timer Counter and TF1 One from the serial port TI or SI The interrupt sources are associated with bit locations in registers Each or all can be enabled by setting or clearing the appropriate bit in the IE register If enabled an interrupt will cause a call t
6. aad ab gueaecrste interes apt at ified counte veing ite tine bere it int counts teed counts Geter pe charmes the state ct the LED T mar cvertlovs void interrupt 5 claar Tirar interrupt flag chesz4e viote LED Port Configuration Digital Peripherals 51 8051 Controller Core External Memory Interface LS EE ES ES E Ps BERERERE DIDNDNN a AIND AIN TS Figure 1 1 C8051F340 1 4 5 Block Diagram 8051 8751 is the same as 8051 except it replaces ROM with UVEPROM e 4K bytes ROM e 5 interrupt sources 2 external e 128 bytes RAM e 1 duplex serial port e Two 16 bit counters timers e 1 bit level Boolean processor Table 1 1 Product Selection Guide lash Memory Bytes Supply Voltage Regulator F RAM Extemal Memory Interface EMIF 10 bit 200 ksps ADC EN Temperature Sensor 1 E 8 AE 05 Programmable Counter 5 a TR e gt a LL z Ordering Part Number Calibrated Internal Osci Digital Port m Analog Comparators Voltage Reference E cs D E X B C8051F340 GQ 10 Bit ADC ADCO C8051F340 1 2 3 4 5 6 7 A B Only The ADCO subsystem for the C8051F34x devices consists of two analog multiplexers referred to collectively as AMUXO and a 200 ksps 10 bit
7. in their high voltage non active logic 1 state These devices usually operate with an external pull up resistor that holds the signal line high until a device on the wire sinks enough current to pull the line low Many devices can be attached to the signal wire If all devices attached to the wire are in their non active state the pull up will hold the wire at a high voltage If one or more devices are in the active state the signal wire voltage will be low An open collector open drain signal wire can also be bi directional Bi directional means that a device can both output and input a signal on the wire at the same time In addition to controlling the state of its pin that is connected to the signal wire active or non active a device can also sense the voltage level of the signal wire Although the output of a open collector open drain device may be in the non active high state the wire attached to the device may be in the active low state due to activity of another device attached to the wire The bi directional nature of an open collector open drain device is what makes this circuit so important in interconnecting many devices on a common line The I2C Bus and SMBus uses this technique for connecting up to 127 devices Open drain refers to the drain terminal of a MOS FET transistor Open collector is the same concept on a bipolar device Open collector outputs Vsu supply Vout single transistor ON or OFF Vout
8. 5 Time Counter 1 External Flag P3 4 Timer Cauntet 0 External Flag Poo B3H nterrupt 1 nput Pin P3 2 BIH Interrupt Q Input Pin Serial Port Transmit Pin P3 0 BOH Serial Pon Receive Pin Priority of Serial Port Enterrupt P3 BBH Priority of Timer 1 Interrupt R2 BAH Priority of External Interrupt 1 BSH Priority of Timer 0 TPO B amp H Priority of External Interrupt 21 Immediate Operand has a numeric constant or it s symbolic name following the opcode Index Addressing two uses reading data tables from program memory space implementing jump tables In each case a 16 bit register holds the base address and the accumulator holds an 8 bit displacement or index The address of the jump is the sum of the 16 bit base and the 8 bit displacement Because unsigned the result is always a forward reference The base register is either DPTR or PC Operand Modifiers before an operand means indirect addressing is being used before operand means it is an immediate operand constant Instruction Groups arithmetic logic data transfer Boolean branching Instruction Sets Mnemonic Description Cycle Arithmetic Operations ADD Add register to accumulator ADD Add direct byte to accumulator ADD A RI Add indirect RAM to accumulator ADD A data Add immediate data to accumulator ADDC A Rn Add register to accumulator with carry fl
9. Bytes Value Range signed char 8 1 128 to 127 unsigned char 1 255 enum 16 2 32768 to 32767 signed short 16 2 32768 to 32767 unsigned short 16 2 0 to 65535 signed int 16 2 32768 to 32767 unsigned int 16 2 0 to 65535 signed long 32 4 2147483648 to 2147483647 unsigned long 32 4 0 to 4294967295 oat 32 4 1 175494E 38 to 3 402823E 38 1 0 to 1 1 Otol spec FUNC Ress sfr 1 0 to 255 sfr16 16 2 0 to 65535 28 There is no explicit compare instruction it has been absorbed into a special branching instruction Data transfer instructions are compatible with all addressing modes The Boolean operators are associated with the 8051 single bit Boolean processor 29 Branching instructions include calls returns and various conditional and unconditional jumps Conditional jumps are relative to the first byte of the next instruction Jumps are given as signed twos compliment 8 bit numbers the range is 128 to 127 bytes forward and backwards Jumps e short relative offset e long 16 bit address access full memory e absolute 11 bit address 8 lower bits 3 upper bits combined with a 5 bit operation specific CJNE combines the functions of separate compare and jump instructions NOP 1 byte instruction which does nothing takes one machine cycle Use for padding delay loops canbe used to determine pulse width Single Bit Boolean Processor all port lines as well as 128 bits of RAM and many bits in the SFR r
10. Resistor Transistor Sources Output Switch 5 Current Oh Sinks shorted Current lt Figure 8 1 Simplified 1 port circuit Figure 8 2 Quasi bi directional pin 5 5 330 to 470 Ohms rete 80C32 gt 4 mis 80C32 CPU Pin races Sources equires from 7 LED Current 10 20 mA for Port 1 irre Full Brightness bit 0 Transistor ETT 4E Output Figure 8 3 Driving a LED m 4 s directly from a port pin Current ad L Optional Base Current Limiting Figure 8 4 NPN transistor for greater load current TOV E J 5v 80 32 Port 1 to 4 7K Transistor Tu Simplified Bit o ee a Input Circuit L toLoad Forces Current 1 CPU Pin into Pin S Eum Current 330 to LAU ij qoem 470 Ohms Input Current d ONwhe Limiting VE Substrate Outpu LOW m Diode Voltage 7 LED Vss Vf Forces Current 80C32 Out of Pin pu Figure 8 5 PNP transistor output driver Figure 8 6 pin voltage limits 15 V W Internal CPU Resistor Sources Current wr fi af 1 0 Output Switch Switch Sinks OFF Switc Current ON open shorted DATA BUS MEM ADDRESS PRGM ADDRESS REG MEM WRITE DATA _ DATA BUS MEM READ DATA RESET IRQS CLOCK STOP Figure 2 1 Block Diagram of CIP 51
11. address ACC CY PSW T DFH Carry Flag PSW 6 DEH Auxiliary Carry Flag PSW S DSH Flag 0 PSW 4 Resister Bank Select Bit 1 Accumulator PAW DSH Register Bank Select Bu 0 Multiplication Register PSW D2H Overflow Flag Data Pointer high byte PSW 0 D H Parity Flag Data Pointer low byte TCON 7 Timer 1 Overflow Flag Interrupt Enable TcON 6 SEH Timer 1 Run Control Bit Interrupt Priority TCON S 8DH Timer 0 Overflow Flag Port 0 TCON 4 8CH Timer 0 Run Control Bir Part 1 TCON 3 Interrupt 1 Edge Flag Pon 2 TCON Interrupt 1 Type Control Bit Port 3 TCON 89H Interrupt Edge Flag Program Status Word 0 88H Interrupt 0 Type Control Bit Serial Port Buffer SCON 7 9FH Serial Mode Control Bit 0 Serial Port Controller SCON 6 9EH Serial Mode Control Bit 1 stack Pointer SCON S 9DH Serial Mode Control Bit 2 Timer Control SCON 4 9CH Receiver Enable Timer 0 high byte SCON 3 9BH Transmit Bit Timer 1 high byte SCON 3 Receive Bit 8 Timer 0 low byte SCON 99H Transmit Interrupt Flag Timer 1 low byte Timer Mode SCONO 98H Receive Interrupt Flag IE 7 AFH Enable All Interrupts IE 4 ACH Enable Serial Port Interrupt IE 3 ABH Enable Timer 1 Interrupt TE 2 AAH Enable External nterrupt 1 ASH Enable Timer 0 Interrupt ASH Enable External Interrupt Read Data for External Memory P36 Write Data for External Memory P3
12. amp 051 Notes My board Family is C8051F34x DK Trouble installing and or using the development kit please use the following support resources C8051F xxx Development Kit User s Guide click Browse Documentation Application Note AN104 Integrating Keil 8051 Tools Into the Silicon Labs IDE Latest versions of Application Notes can be found at http www silabs com products microcontroller applications asp MCU Knowledgebase available at www silabs com SUPPORT Applications Engineer online information request form available at www silabs com SUPPORT Open project file Family Blinky C wsp located at C SiLabs MCU Examples lt Family gt Blinky tdt gem ere s s 21 E Click on Family Blinky c to open source file seus e Select Connection Options from Options menu Select USB Debug Adapter c ASID Seal Adapa 2 COMPORT Baud R e Select Correct Debug Interface C8051FOxx gt JTAG C8051F1xx gt JTAG C8051F2xx gt JTAG C8051F3xx gt 2 8051 4 C2 C8051F5xx C2 C8051F8xx C2 gt and pL the program 45 amp t baat jaie 0 Copyrisht 2006 AUTH BV 7 DATE 11 OCT Mt This prossom floshes the LED on the CJOBIFX R tory five t meccnd using the istarrapt handler fca
13. ag ADDCO direct Add direct byte to A with carry flag ADDC A RI Add indirect RAM to A with carry flag ADDC A data Add immediate data to A with carry flag SUBE Subtract register from A with borrow SUBE A direct Subtract direct byte from A with borrow SUBB Subtract indirect RAM from A with borrow SUBE A data Subtract immediate data from A with borrow INC Increment accumulator INC Rn Increment register INC direct Increment direct byte INC RI Increment indirect RAM DEC A Decrement accumulator DEC Rn Decrement register DEC direct Decrement direct byte DEC R Decrement indirect INC DPTR Increment data pointer MUL AB Multiply A and B DIV AB Divide A by B DA Decimal adjust accumulator 22 Logic Operations ANL ANL ANL ANL ANL ANL ORL ORL ORL ORL ORL ORL XRL XRL XRL CLR CPL RL RLC RR RRC SWAP A direct A amp Ri A dala direct A direct data A direct A amp Ri A dala direct A direct data direct A amp Ri A dala direct A direct data AND register to accumulator AND direct byte to accumulator AND indirect RAM to accumulatar AND immediate data to accumulator AND immediate data to direct byte OR immediate data to direct byte Exclusive OR register to accumulator Exclusive OR direct byte to accumu
14. carry OR direct bit to carry flag OR complement of direct bit to carry Move direct bit to carry flag Move carry flag to direct bit Absolute subroutine call Long subroutine call short jump relative addr Jump indirect relative to the DPTR Jump if accumulator is zero Jump if carry flag is set Jump if carry flag is not set Jump if direct bit is set Jump if direct bit is not set Jump if direct bit is set and clear bit BP RB IO Compare direct byte to A and jump if not equal Compare immediate to A and jump if not equal Compare immed to reg and jump if not equal Compare immed to ind and jump if not equal Decrement register and jump if not zero Po ho Bo Bo Bo Decrement direct byte and jump if not zero Mo operation 25 Assembler directives are used to define symbols reserve memory space store values in program memory and switch between different memory spaces There are also directives that set the location counter for the active segment and identify the end of the source file EOL Define symbol DATA Define internal memory symbol IDATA Define indirectly addressed internal memory sym bol XDATA Define external memory symbol BIT Define internal bit memory symbol CODE Define program memory symbol Ds Reserve bytes of data memory DBIT Reserve bits of bit memory DB Store byte values in program memory DW Store word values i
15. egister This is useful in many on off kinds of control applications such as I O switches lamps relays stepper motor drives etc Carry The Boolean Accumulator Bit 7 of the PSW is the carry bit it is the equivalent of an accumulator for the Boolean processor Carry bit is known by several names depending on function CY when referring to a bit address C used in register specific instructions which reference the carry bit CLR C one byte register instruction clears the carry bit CLR CY 2 byte instruction that clears the carry bit by referencing its address in the SFR space Bits from SFR register from internal RAM and from I O ports can be read into CY AND and OR operations can be performed on the CY and result written back to a bit address Extensive bit manipulation can be done without having to resort to extraneous code 30 31 32 33
16. gt Output 0 Input 1 gt Output 0 Resistor SOUFrces Gate Current laure 1 12 NMOS FET Figure 1 12 Field NM effect transistor FET Source OFF schematic diagram open Figure 1 14 NMOS inverter circuit CMOS Inverter Equivalent Equivalent Power Output LOW Output P channel 1 FET OFF P FET ON Sources Current Output Output LOW Output HI E ON ba N FET OFF inks N channel Current Ground Figure 1 15 CMOS inverter circuit and equivalent output n Equivalent Equivalent Output LOW Output HI FET OFF Figure 1 16 Logic output voltage is current dependent 13 Ay t 3 Buffer AND OR F F A B AOR Figure 1 18 Logic symbols symbolic notation and truth tables Tri State Inverting Buffer Output ENabled Output DiSabled A lt OFF Input Output 1 0 Truth Table Doc oO NC Switch Switch ON OFF closed open Symbol and Function Equivalent Circuit Active and Passive Figure 1 19 Active and passive states of a tri state buffer Vec External Resistor Output L Output Pin Pin Active Pull Up Passive Pull Up Totem Pole Open Collector Figure 3 11 TTL outputs totem pole and open collector 14 V V Resistor Sources BE Current 01 O
17. l speci iod Lis counts wrung 2579 48 tas wotd Timer2_Init int counts Ztcp Tiser2 wee 1 12 TOON UxsbD seer clocked Thim routine changes the state of the LED void Timar2 ISR void intexcapt 1 0 LED Open Debug windows 578 jen oad wczera or um t This rostame changer the stete cf t void ISE woid interrapt 5 Connect to Target Board D DM Suv Du iatl P Execute example program Green LED on target board flashes as program runs oea xx Quows Cau gt xam e XR FE 5 ija Ee Blinky Copyright 2005 Silicon Llabceatcries Iac 22 14 DATE 21 OCT Ot progres Leche sreen LED co the 1 30 te tive tines second A X the interrupt ian jas for Tira Taxget CHOLLFI0Ox Toal chai REII Rval c in PCAN Module 2 ou tor Execute program breakpoint encountered pt ven Protect Oday Tess Optore as qure Tiwez2 ta Must t an c F wal by Lo mer Init 124 coms PCM 000 be RIEL comt R2 2 1 This scatine chasges the estate cf the LED mu change xtate View modify Peripherals Registers Memory eo ate to bit
18. lator Exclusive OR indirect to accumulator Exclusive OR immediate data to accumulator Exclusive OR accumulator to direct byte n3 Exclusive OR immediate data to direct byte Rotate accumulator left through carry Rotate accumulator right Rotate accumulator right through carry swap nibbles within the accumulator 23 Data Transfer MON MON MON MON MON MOV MON MOV MOV MOV MOV MOV MOV MOV MOVC MOVC MOVX MOVX MOVX MOVX PUSH POP XCHD direct amp data Move immediate data to direct byte 2 ARN Exchange register with accumulator 1 A direct Exchange direct byte with accumulator Ri Exchange indirect RAM with accumulator 1 1 A RI Exchange low order nibble indir RAM with A 1 24 Boolean Variable Manipulation CLR CLR SETB SETB CPL CPL ANL ANL ORL ORL MOV MOV Program and Machine Control C bit bit bit C bit C bit C bit C bit C bit bit C ACALL 11 LCALL addri6 RET RETI AJMP LIMP SJMP JMP JZ JNZ JC JNC JB JNB JBC CJNE CJNE CJNE CJNE DJNZ DJNZ NOP addr11 addr16 rel A DPTR rel rel rel bit rel bit rel bit rel A direct rel data Rn data rel Ri data rel Rn rel direct rel G Complement direct bit AND direct bit to carry flag AND complement of direct bit to
19. m 32 pin QFN C8051F342 3 6 7 9 A B Temperature Range 40 to 85 Port gt 5 64 32 8051 CPU ISP FLASH 48 25 mips KB RAM FLEXIBLE DEBUG INTERRUPTS CIRCUITRY Stack Pointer 8 bits wide max size 256 bytes Grows upward SP incremented before data are stored per a push or call Data Pointer 16 bit held in two 8 bit parts Holds 16 bit address for certain instructions Can be used as single 16 bit reg or two 8 bit regs Port Latches PO P1 P2 P3 32 IO pins organized into four 8 bit ports B bit port outputs are latched Serial Data Buffer two regs which share a common address Data written to SBUF goes to a transmit buffer and is held for serial transmission Data read from the SBUF comes from the serial data receive buffer Timer Registers THO and TLO are high and low bytes of the 16 bit counter timer 0 Likewise for counters 1 and 2 Control Registers registers for control and status of the interrupt system timer counter system and serial port They are IP interrupt priority TCON timer control IE interrupt enabled SCON serial port control TMOD timer mode PCON power control Open Collector Open Drain Open collector open drain is a circuit technique which allows multiple devices to communicate bi directionally on a single wire Open collector open drain devices sink flow current in their low voltage active logic 0 state or are high impedance no current flows
20. n program memory ORG set segment location counter END of assembly language source file CSEG select program memory space DSEG Select internal memory data space Select external memory data space ISEG Select indirectly addressed internal BSEG Select bit addressable memory space memory space USING Select register bank IF Beein conditional assembly block ELSE Alternative conditional assembly block ENDIF End conditional assembly block refer to 8051 Cross Assembler User s Manual chapter 5 in 8051 directory for definitions 26 program memory up to 64 Kbytes data directly addressable data memory allowing fastest access to variables in the first 128 bytes of the on chip RAM idata indirectly addressable data memory across the full 256 bytes of the on chip RAM bdata bit addressable data memory allowing bit access of character and integer ables stored inside the 16 bytes on chip bit data space xdata external data memory up to 64 Kbytes pdata paged external data memory allowing access 256 bytes at a time through port 0 up to 64k bytes up to 64k bytes 256 bytes 256 bytes 8052 upper RAM _ _ _ 128 bytes 128 bytes 128 bits z bdata data idata pdata Figure 4 1 Six different memory areas in an 8051 system 27 The selection of memory types for the different variables directly affects the effi ciency of your final program As rule
21. o one of the predefined locations in RAM RETI return from interrupt pops last address before jump from stack Maskable an interrupt which can be blocked by software Interrupts which occur while masked are called pending Priority scheme is necessary for interrupts which occur simultaneously The 8051 has a two tier priority scheme high and low Set bits in the IP register to assign one of two priority levels to each interrupt The second tier of priority is used to resolve simultaneous interrupts within the same interrupt level 8051 shortest response time 3 machine cycles 9 machine cycles is the worst case Interrupts can be either level activated or transition edge activated The 8051 has the following predefined vector addresses RESET OOH EXTIO 03H TIMERO 0BH EXTI1 13H TIMER1 1BH SINT 23H 18 Intel 8051 Mic rosrehirtectu re 0 7 2 0 p2 7 p m um UEM 1 1 Port 1 55 1 RAM Addr EFRO Register ROM Interrupt Serial Part and Timer Blocks Incrementer Program Counter PSEHH AL EMP ROGH EAH VPP 22 E CONS
22. om transistors Hence we are looking at both views Enlarge Image Figure 4 Using a Pull up Resistor with an Open Collector Output Enlarge Image Figure 7 Wired OR Connection 10 Wiring an NPN Style Output to a PLC gt Pull Up Resistor Wiring a PNP Style Output to a Collector Base Emitter Current Fow Source Control Sink Figure 1 7 Operation of a bipolar transistor Pull Down Resistor Collector Base p aN Emitter Sink Current Flow Control Source Figure 1 8 Operation of a bipolar NPN transistor 11 Transistor Inverter Input 1 gt Output 0 aad Output Transistor Switch Transistor Inverter Equivalent Circuit Equivalent Circuit Figure 1 10 The transistor inverter input 1 and transistor ON The transistor configuration is at left and the equivalent circuit is at right Transistor Inverter Input 0 Output 1 Resistor Sources Current 1 n Transistor FF Transistor Switch OFF Figure 1 11 The transistor inverter input Transistor Inverter Equivalent Circuit Resistor Current 0 a 1 a r Circuit 0 and transistor OFF The transistor OFF configuration is at left and the equivalent circuit is at right 12 voltage Drain NMOS FET Inverter NMOS FET Inverter Input 1
23. ransceiver no external resistors required On Chip Debug On chip debug circuitry facilitates full speed non intrusive in system debug No emulator required Provides breakpoints single stepping inspect modify memory and registers Superior performance to emulation systems using ICE chips target pods and sockets Voltage Supply Input 2 7 to 5 25 V Voltages from 3 6 to 5 25 V supported using On Chip Voltage Regulator 10 bit 200 ksps PRECISION INTERNAL OSCILLATORS High Speed 8051 uC Core Pipelined instruction architecture executes 70 of Instructions in 1 or 2 system clocks 48 MIPS and 25 MIPS versions available Expanded interrupt handler Memory 4352 or 2304 Bytes RAM 64 or 32 kB Flash In system programmable in 512 byte sectors Digital Peripherals 40 25 Port All 5 V tolerant with high sink current Hardware enhanced SPI SMBus and one or two enhanced UART serial ports Four general purpose 16 bit counter timers 16 bit programmable counter array PCA with five cap ture compare modules External Memory Interface EMIF Clock Sources Internal Oscillator 0 25 accuracy with clock recovery enabled Supports all USB and UART modes External Oscillator Crystal RC C or clock 1 or 2 Pin modes Low Frequency 80 kHz Internal Oscillator Can switch between clock sources on the fly Packages 48 pin TQFP C8051F340 1 4 5 8 C 32 LQFP C8051F342 3 6 7 9 A B D 5x5 m
24. successive approximation register ADC with integrated track and hold and programmable window detector The AMUXO data conversion modes and window detector are all configured under software control via the Special Function Registers shown in Figure 5 1 ADCO operates in both Single ended and Differential modes and may be configured to measure voltages at port pins the Temperature Sensor output or VDD with respect to a port pin VREF or GND The connection options for AMUXO are detailed in SFR Definition 5 1 and SFR Definition 5 2 The ADCO subsystem is enabled only when the ADOEN bit in the ADCO Control register ADCOCN is set to logic 1 The ADCO subsystem is in low power shutdown when this bit is logic O ADOBUSY Timer 0 Cwerfiow Timer 2 Qwerfiow Timer 1 Cwerfiow CNVETR Input Timer 3 Qwerficw ADCOL Window kl Cr 22 Logic Figure 5 1 ADCO Functional Block Diagram IC Pins YOO Temp Part IO Pins GNO 21 Geiections on 32 001 package 20 Selections on 45 package PROGRAM DATA MEMORY FLASH OxFFFF OxF COD DxFBFF FLASH In System Programmable in 512 Byte Sectors 0000 DATA MEMORY INTERNAL DATA ADDRESS SPACE PEE Upper 128 RAM Special Function Indirect Addressing Registers Only Direct Addressing Only Ox7F Direct and Indirect Addressing Lower 128 RAM 0 30 Direct and Indirect x2F Addressing 0
25. use the of type to store variables that require fast and access of time ifi also be opu inside the sssable internal ize should go inside the iE me arge ir xdata memory area There may be variables whose memory types are not declared explicitly by memory type specifiers or you may not want to go through the trouble of specifying the memory types of every variable because they are all in the same memory area Possibly your pro gram is small enough so that everything would fit into the on chip memory In those cases the following memory model definitions allow you to choose either an overall memory area for the entire program or function or a default memory type for those variables that are not declared explicitly small Variables and local data are defined to reside in internal data memory the same as if they were defined by the data specifier compact Variables and local data are defined to reside in external data memory the same as if they were defined by the pdata specifier large Variables and local data are defined to reside in external data memory the same as if they were defined by the xdata specifier The selection of a memory model can be done either at compile time in the Options pull down menu of Franklin s ProView for example or by using the C directive pragma inside the source code The default memory model is small Data Type Bits
26. x20 x1F 0 00 EXTERNAL DATA ADDRESS SPACE OxFFFF Of Chip Available only on devices ith 0 1000 OxDFFF Ux TFF 00000 Figure 9 2 On Chip Memory Map for 64 Devices 3 Special Function Registers The direct access data memory locations from 0x80 to OxFF constitute the special function registers SFRs The SFRs The CIP 51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional SFRs used to configure and access the sub systems unique to the MCU Table 9 2 Special Function Register SFR Memory Map SPIOCN PCAOL PCAO0H PCAOCPLD PCAOCPHO PCAOCPL4 4 VDMOCN FO P1MDIN P2MDIN P3MDIN P4MDIN 2 E8 PCAOCPL3 PCAOCPHS SMOD D8 PCAOCN PCAOMD PCADCPMO PCADCPMi PCADCPM2 PCADCPMS PCADCPM4 P3SKIP Do 15 P2SKIP Ca TMR2CN REGOCN TMRZRLL TMRZRLH TMR2L gt co ps IP CLKMUL ADCOL ADCOH P3 OscicL SBRLL1 SBRLH1 FLSCL FLKEY CLKSEL EMIOCN SBCON1 P4MDOUT PFEOCN AD 2 SPIOCFG SPIDCKR SPIODAT POMDOUT PIMDOUT P2MDOUT P3MDOUT 98 CPTOCN 1 CPTOMD CPTOMX en TMR3 TMRSH USBODAT IT 1h 88 o TW PSCTL 80 PO sP DPH EMIOCF OSCLCN PCON 1 9 HB 4 C D Highest
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