MODEL P104-DIO-96 USER MANUAL
Contents
1. stack that has the holes for Pin C19 and icles B10 blocked please cut these two pins as ee shown from the solder side of this board bs It is not necessary to block the holes on ce the component side of the board O O EB Pin 1 AB Figure 2 1 PC 104 Key Information 10 Manual P104 DIO 96 Chapter 3 Option Selection Most PCI bus signals are common to all four boards in the PCI stack However there are four unique signal groups one for each board The slide switches select which signal group goes to each card The card in the stack closest to the CPU board must get signal group 0 3 775 Figure 3 1 Option Selection Map 11 Manual P104 DIO 96 Chapter 4 Address Selection The system BIOS or operating system will assign the address This board occupies 32 bytes of I O space PCI architecture is Plug and Play This means that the BIOS or Operating System determines the resources assigned to PCI cards rather than you selecting those resources with switches or jumpers As a result you cannot set or change the card s base address You can only determine what the system has assigned To determine the base address that has been assigned run the PCIFind EXE or PCINT utility program provided This utility will display a list of all of the cards detected on the PCI bus the addresses assigned to each function on each of the boards and the respective IRQs if any allotted Alternatively some operating systems Wi2. et all I O lines are set as inputs Output buffers are automatically set by hardware logic according to the control register states Control registers are located at base addresses 3 7 B and F Bit assignments in each of these control registers are as follows DO Port C Lo C0 C3 1 Input 0 Output T Input 0 Output Backward Compatible Must be 0 Port C Hi C4 C7 Table 5 2 Control Register Bit Assignments Note Because all I O pins are buffered the 8255 individual bit control feature is not available The hardware uses the control registers to manage buffer direction on this board The board emulates four Intel 8255 PPls The bit assignments and functionality of the control register has been kept to maintain backward compatibility with existing software The emulated 8255 chips differ from the original in that when a port is configured to be outputs the I O pins default to a HIGH state rather than a LOW state A port that is programmed to be inputs may have a value written to it A READ of the port will return the state of the I O pins in that case When that port is configured to be an output latch the value previously written to it will be driven on the I O pins The board will occupy two spaces in memory One space is I O mapped and burst READs or WRITEs will not work The other space is memory mapped and should be found below the 1 megabyte boundary to facilitate DOC programs and bursts of four double words are possib
3. fast blow fuse in your circuits in order to avoid possible damage to the host computer The board occupies 32 bytes within the PCI I O space The base address is assigned by the system Refer to the Option Selection Section of this manual for a detailed description 5 Manual P104 DIO 96 Specification Data Transfer Rate I O Mapped 33MHz bus From I O connector to PCI bus 7 37M bytes per second in 8255 emulation mode From PCI bus to I O connector 14 74M bytes per second in 8255 emulation mode e From I O connector to PCI bus 9M bytes per second with Fast PPI port map e From PCI bus to I O connector 18M bytes per second with Fast PPI port map Data Transfer Rate Memory Mapped 33MHz bus From I O Connector to PCI bus 12M bytes per second in 8255 emulation mode From PCI bus to I O connector 24M bytes per second in 8255 emulation mode From I O connector to PCI bus 28M bytes per second with Fast PPI port map e From PCI bus to I O connector 18M bytes per second with Fast PPI port map Digital Inputs TTL Compatible Logic High 2 0 to 5 0 VDC Logic Low 0 5 to 0 8 VDC Input Load High 10uA Input Load Low 10uA Digital Outputs Logic High 2 5 VDC min source 32 mA e Logic Low 0 5 VDC max sink 64 mA Power Output 5 VDC from computer bus onboard resettable 0 5A fuse on each digital group s I O connector Power Required 290 mA typical at 5V all I O pins disconnected all I O ports se
4. hich is found to be defective will be repaired or replaced subject to the following considerations Terms and Conditions If a unit is suspected of failure contact ACCES Customer Service department Be prepared to give the unit model number serial number and a description of the failure symptom s We may suggest some simple tests to confirm the failure We will assign a Return Material Authorization RMA number which must appear on the outer label of the return package All units components should be properly packed for handling and returned with freight prepaid to the ACCES designated Service Center and will be returned to the customer s user s site freight prepaid and invoiced Coverage First Three Years Returned unit part will be repaired and or replaced at ACCES option with no charge for labor or parts not excluded by warranty Warranty commences with equipment shipment Following Years Throughout your equipment s lifetime ACCES stands ready to provide on site or in plant service at reasonable rates similar to those of other manufacturers in the industry Equipment Not Manufactured by ACCES Equipment provided but not manufactured by ACCES is warranted and will be repaired according to the terms and conditions of the respective equipment manufacturer s warranty General Under this Warranty liability of ACCES is limited to replacing repairing or issuing credit at ACCES discretion for any products which are proved to be defective dur
5. ing the warranty period In no case is ACCES liable for consequential or special damage arriving from use or misuse of our product The customer is responsible for all charges caused by modifications or additions to ACCES equipment not approved in writing by ACCES or if in ACCES opinion the equipment has been subjected to abnormal use Abnormal use for purposes of this warranty is defined as any use to which the equipment is exposed other than that use specified or intended as evidenced by purchase or sales representation Other than the above no other warranty expressed or implied shall apply to any and all such equipment furnished or sold by ACCES 3 Manual P104 DIO 96 Table of Contents Table of Contents on oerte reet ree HE Eo enerverende SEE e din 2 Chapter 1 Introduction ae 5 Chapter 2 Installation sr near 8 Figure 2 1 PC 104 Key Information ara 10 Chapter 3 Option Selection u ito nds 2er 11 Figure 3 1 Option Selection Map cccccccccccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeseeeeeeeeeeeess 11 Chapter 4 Address Selection 44444444444400Hnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 12 Chapter 5 Programming 2 32 02 eit edelen 13 Table 5 1 Base REGISIONS un touc beat uice NR obtain 13 Table 5 2 Control Register Bit Assignments 14 Chapter 6 Connector Pin Assignments sssssssssssssss 16 4 Manual P104 DIO 96 Chapter 1 In
6. le The PCIFIND EXE program will display the board s locations in memory The user may specify one of two register mappings see the Base Registers table in the Programming chapter 8255 standard or an enhanced speed map The latter allows the user to read from or write to more ports with a single operation 32 bits versus 24 bits Because many motherboard s reset circuits do not accurately wait for the 3 3V power supply to finish the power on sequence before using the board at each power up it is necessary to issue a single Write to Base 1F to Reset the onboard circuitry 14 Manual P104 DIO 96 Programming Example The following programming example is provided as a guide to assist you in developing your working software In this example the board base address is 2D00 hex and I O lines of Port 0 are to be setup as follows port A Input port B Output port C hi Input port C lo Output Configure bits of the Control Register as pe jo o lt Data Mel Dt 0 Port B output DO 0 Port C Lo output This corresponds to 98 hex If the card base address is 2D00 hex use the BASIC OUT command to write to the control register as follows 10 BASEADDR amp H2D00 20 OUT BASEADDR 3 amp H98 To read the inputs at Port A and the upper nybble of Port C use the BASIC INPUT command 30 X INP BASEADDR Read Port A 40 Y INP BASEADDR 2 16 Read Port C Hi To set outputs high 1 at P
7. ndows 95 98 2000 can be queried to determine which resources were assigned In these operating systems you can use either PCIFind DOS PCINT Windows95 98 NT or the Device Manager utility from the System Applet of the control panel The board is installed in the Data Acquisition class of the Device Manager list Selecting the card clicking Properties and then selecting the Resources Tab will display a list of the resources allocated to the card The PCI bus supports 64K of I O space Your board s addresses may be located anywhere in the 0400 to FFEO hex range PCIFind uses the Vendor ID and Device ID to search for your board then reads the base address and IRQ If you want to determine the base address and IRQ yourself use the following information The Vendor ID for the board is 494F ASCII for IO The Device ID for the board is Ox0C69 12 Manual P104 DIO 96 Chapter 5 Programming The board is an I O mapped device that is easily configured from any language and any language can easily perform digital I O through the board s ports This is especially true if the form of the data is byte or word wide All references to the I O ports would be in absolute port addressing However a table could be used to convert the byte or word data ports to a logical reference Developing Your Own Software If you wish to gain a better understanding of the programs listed in the previous section then the information in the following paragraph
8. ort B and the lower nybble of Port C 50 OUT BASEADDR 1 amp HFF Turn on all Port B bits 60 OUT BASEADDR 2 amp HF Turn on all bits of Port C Lo 15 Manual P104 DIO 96 Chapter 6 Connector Pin Assignments Note that the board uses four 50 pin Headers each with equitable pinouts Assignment Pin Assignment Pin PC7 1 2 Port C Hi RCO 3 Q 3 PC5 5 gt 6 PC4 7 5 8 PC3 9 O 10 PC2 11 X 12 Port GLa PC1 13 5 14 PCO 15 o 16 PB7 17 5 18 PB6 19 D 20 PB5 21 22 PB4 23 i 24 hele PB3 25 5 26 PB2 27 D 28 PB1 29 D 30 PBO 31 Q 32 PA7 33 E 34 PA6 35 Z 36 PA5 37 38 PA4 39 5 40 EON PA3 41 gt 42 PA2 43 LJ 44 PA1 45 46 PAO 47 lt 48 5 VDC 49 50 16 Manual P104 DIO 96 Customer Comments If you experience any problems with this manual or just want to give us some feedback please email us at manuals accesio com Please detail any errors you find and include your mailing address so that we can send you any manual updates ACCES I O PRODUCTS INC 10623 Roselle Street San Diego CA 92121 Tel 858 550 9559 FAX 858 550 7322 www accesio com 17 Manual P104 DIO 96
9. reserved etc Similarly the CPU s interrupt controller resources INTA INTB INTC INTD will be distributed among the cards in the stack A set of four to one multiplexers and two slide switches are used to select which PCI clock IDSEL and INT lines are routed to the board s PCI bus interface Only four boards are allowed in a PCI Plus stack each board must get a specific set of signals These signals are selected with two slide switches labeled SEL 1 and SEL 2 which form a binary value to control the mux SEL 1 is the least significant bit and SEL 2 is the most significant bit If the board is closest to the CPU slide both switches to the right This will select the signal with the longest trace on the CPU board signal group 0 If this product is the farthest board from the CPU slide both switches to the left This will select the signal with the shortest trace on the CPU board signal group 3 Place the SEL 1 switch to the left and SEL 2 to the right to select signal group 1 place the SEL 1 switch to the right and SEL 2 to the left to select signal group 2 9 Manual P104 DIO 96 To install the board Turn off the computer power Position the slide switches to select the clock IDSEL and interrupt signal group Install the card in a PC 104 Plus stack Install I O cables at P1 and P2 Inspect for proper fit of the card and cable and then tighten the screws Oo RON If you are installing this board into a PC 104 Pino 9
10. s will be of interest to you Four register locations are required per 24 bit group Thus the 96 uses a total of 16 registers for groups 0 through 3 nl Standard 8255 Compatibility Option Improved Speed Option Offset Base 0 Base 1 Base 2 Base 3 Base 4 Base 5 Base 6 Write Group 0 Port A Group 0 Port B Group 0 Port C Group 0 CMD Group 1 Port A Group 1 Port B Group 1 Port C Group 0 Port A Group 0 Port B Group 0 Port C Group 1 Port A Group 1 Port B Group 1 Port C Write G G G G G G G roup 0 Port A roup 0 Port B roup 0 Port C roup 1 Port A roup 1 Port B roup 1 Port C roup 2 Port A Read Group 0 Port A Group 0 Port B Group 0 Port C Group 1 Port A Group 1 Port B Group 1 Port C Group 2 Port A Group 2 Port B Group 2 Port A Group 2 Port A Group 2 Port C Group 2 Port C Group 3 Port A Group 3 Port A meh mem mom wei we mer oomscw _ onwscm Base 10 Reserved Reserved Reserved Reserved through Base 1E Table 5 1 Base Registers 13 Manual P104 DIO 96 The board is designed to use each of these PPI s in mode 0 wherein a There are two 8 bit ports A and B and two 4 bit ports C Hi and C Lo b Any port can be configured as an input or an output C Outputs are latched d Inputs are not latched Each PPI contains a control register This Write only 8 bit register is used to set the mode and direction of the ports At Power Up or Res
11. t as inputs Environmental Operating Temperature 20 C to 70 C Storage Temperature 50 C to 120 C Humidity 0 to 90 RH non condensing 6 Manual P104 DIO 96 LHO M3QV3H Od Nid 0S Ue E EUR AJN dadang ana ana EEEE 4344N8 dnd dnd Sve Ste Ove Ove Sve Sve Ove Ove i g Z LHOd Y3AY3H IAI Nid 0S CPLD LOGIC uaddng wading dng ana a344N9 uaddng Ang dna Sve Sve ove Ove Sve Sve Ove Ove L LHO YS0VSH Od NId 08 0 LHOd H3QV3H OAI Nid 0S PC 104 and PCI 104 STACK POSITION JUMPERS o e o e x e n 32 BIT PCI BUS INTERFACE PC 104 PLUS OR PCI 104 BUS Figure 1 1 Block Diagram Manual P104 DIO 96 Chapter 2 Installation A printed Quick Start Guide QSG is packed with the board for your convenience If you ve already performed the steps from the QSG you may find this chapter to be redundant and may skip forward to begin developing your application The software provided with this PC 104 Plus Board is on CD and must be installed onto your hard disk prior to use To do this perform the following steps as appropriate for your operating system Substitute the appropriate drive letter for your CD ROM where you see d in the examples below CD Installation The following instructions assume the CD ROM drive is drive D Please substitute the appropriate drive letter for your system as necessary DOS 1 Place the CD into your CD ROM drive 2 Type lL Jere to change the ac
12. tive drive to the CD ROM drive 3 Type UNI s TfAl Je to run the install program 4 Follow the on screen prompts to install the software for this board WINDOWS 1 Place the CD into your CD ROM drive 2 The system should automatically run the install program If the install program does not run promptly click START RUN and type SANSAL click OK or press Eed 3 Follow the on screen prompts to install the software for this board LINUX 1 Please refer to linux htm on the CD ROM for information on installing under linux 8 Manual P104 DIO 96 Installing the Hardware Before installing the board please run Setup exe The Setup program can be used to assist in configuring the two switches on the board Our setup program will lead the user through the process of setting the options on the board the program does not set the options on the board The PCI bus clock trace length from the CPU to the cards in the stack is tuned so that the clock edge arrives at the interface when data is valid Since boards in the PC 104 stack are at different distances from the CPU provision is made on the CPU board to supply four clock signals with compensating trace lengths Two signals from other groups must be likewise selected IDSEL and INT When the PCI bus is being initialized the operating system will enable each card with a hard wired select line and read it s configuration registers An address is assigned space in the memory map and I O map is
13. troduction Each I O line of this board is buffered and capable of sourcing 32mA or sinking 64mA The board simulates Programmable Peripheral Interface chips PPI to provide a computer interface to digital I O lines Each PPI supports two 8 bit ports A B and two 4 bit ports Chi Ciow Each port can be configured to function as either inputs or output latches The I O line buffers types 74ABT240 and 74ABT245 are configured automatically by hardware logic for input or output according to the PPI Control Register direction software assignment The board may be shipped with a register map optimized for a higher speed than the pure i8255 port address map See the Programming section for an explanation of how a 25 increase in I O speed is achieved Outputs of the I O buffers are pulled up through 10KO resistors to 5VDC On power up all I O pins are inputs This means that the lines are at a logic HIGH The user may request the factory to remove these 10KO resistors so that the I O lines will not be driven on power up 10 UA leakage per pin I O wiring connections are via 50 pin headers on the board This provides compatibility with OPTO 22 Gordos Potter amp Brumfield Western Reserve Controls etc module mounting racks Every second conductor of the flat cables is grounded to minimize crosstalk If needed for external circuits 5VDC power is available on each I O connector at pin 49 If you use this power we recommend that you include a 1A
14. ya ACCES I O PRODUCTS INC 10623 Roselle Street San Diego CA 92121 858 550 9559 FAX 858 550 7322 contactus accesio com www accesio com MODEL P104 DIO 96 USER MANUAL FILE mp104 dio 96 A1j Notice The information in this document is provided for reference only ACCES does not assume any liability arising out of the application or use of the information or products described herein This document may contain or reference information and products protected by copyrights or patents and does not convey any license under the patent rights of ACCES nor the rights of others IBM PC PC XT and PC AT are registered trademarks of the International Business Machines Corporation Printed in USA Copyright 2006 by ACCES I O Products Inc 10623 Roselle Street San Diego CA 92121 All rights reserved WARNING ALWAYS CONNECT AND DISCONNECT YOUR FIELD CABLING WITH THE COMPUTER POWER OFF ALWAYS TURN COMPUTER POWER OFF BEFORE INSTALLING A CARD CONNECTING AND DISCONNECTING CABLES OR INSTALLING CARDS INTO A SYSTEM WITH THE COMPUTER OR FIELD POWER ON MAY CAUSE DAMAGE TO THE I O CARD AND WILL VOID ALL WARRANTIES IMPLIED OR EXPRESSED 2 Manual P104 DIO 96 Warranty Prior to shipment ACCES equipment is thoroughly inspected and tested to applicable specifications However should equipment failure occur ACCES assures its customers that prompt service and support will be available All equipment originally manufactured by ACCES w
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