For Approve Only SH69P20B
Contents
1. Sl 22 Seating Plane e y See Detail F Symbol Dimensions in inches Dimensions in mm 0 110 Max 2 79 Max 0 004 Min 0 10 Min A2 0 092 0 005 2 33 0 13 Lom p sm 0 002 0 05 0 002 0 05 D 0 455 0 015 11 56 0 38 E 0 295 0 010 7 49 0 25 zo 0 50 0 050 x 0 006 1 27 0 15 0 376 9 50 0 406 0 012 10 31 0 31 Notes 1 The maximum value of dimension D includes end flash 2 Dimension E does not include resin fins 3 Dimension e1 is for PC Board surface mount pad pitch design reference only 4 Dimension S includes end flash 29 For Approve Only SH69P20B Data Sheet Version History Version Content Date 0 0 Original June 2004 302. x 15 PORTB 0 796 OSCO 725 420 PORTB 1 666 16 OSCI 767 749 5 PORTB 2 536 PORTA 0 587 749 5 17 w PORTCO e 26 For Approve Only SH69P20B Ordering Information Part No Packages SH69P20BH Chip form SH69P20BM 18L SOP SH69P20B 18L DIP 27 For Approve Only SH69P20B Package Informations DIP 18L Outline Dimensions unit inches mm D E Perr cr ar hr url LE Base Plane Seating Plane a Dimensions in inches Dimension in mm 0 175 Max 4 45 Max 0 010 Min 0 25 Min A2 0 130 0 010 3 30 0 25 0 018 0 004 0 46 0 10 0 002 0 05 0 060 0 004 1 52 40 10 0 002 0 05 C 0 010 0 004 0 25 0 10 0 002 0 05 0 900 Typ 0 920 Max 22 86 Typ 23 37 Max 0 300 0 010 7 62 0 25 0 250 Typ 0 262 Max 6 35 Typ 6 65 Max 0 100 0 010 2 54 0 25 0 L 0 130 0 010 3 30 0 25 NECEM zo 0 345 x 0 035 8 76 0 89 0 055 1 40 Notes 1 The maximum value of dimension D includes end flash 2 Dimension E1 does not include resin fins 3 Dimension S includes end flash 28 For Approve Only SH69P20B SOP 18L W B Outline Dimensions unit inches mm
3. CY ADCM 00000 1bbb xxx xxxx AC lt Mx AC CY CY ADD 00001 Obbb xxx AC lt ADDM 00001 1bbb xxx xxxx AC Mx AC CY SBC 00010 Obbb xxx xxxx AC lt Mx CY CY SBCM 00010 1bbb xxx xxxx AC Mx AC CY SUB 00011 Obbb xxx xxxx AC lt Mx 1 CY SUBM 00011 1bbb xxx xxxx AC Mx lt AC 1 CY EOR 00100 Obbb xxx xxxx AC lt Mx AC EORM 00100 1bbb AC lt Mx AC OR 00101 Obbb xxxx AC lt Mx AC ORM 00101 1bbb xxx xxxx AC Mx lt Mx AC AND 00110 Obbb xxx xxxx AC lt Mx amp AC ANDM 00110 1bbb xxx xxxx AC Mx Mx amp AC 0 gt AC 3 AC 0 gt CY AC shift right one bit UU UU UU Vg VgL SHR 11110 0000 000 0000 Immediate Type Lemos comm xi xi ow xi onoma Decimal Adjustment DAA X 11001 0110 xxxx AC Mx Decimal adjustment for add DAS X 11001 1010 xxxx AC Mx Decimal adjustment for sub CY 17 For Approve Only SH69P20B Transfer Instructions X B STA B 00111 1bbb xxxx Mx LDI 01111 1 I MEN Control Instructions Mnemonic Instruction Code Function Flag Change 10010
4. RBCER PORT INTERRUPT O E gt DETECT PORTINT c o VV PC 3 PCOUT 2 PC 2 PCOUT 1 PC 1 PCOUT 0 gt lt PC 0 PCOUT 3 gt 13 For Approve Only SH69P20B 7 Interrupt Two interrupt sources are available on SH69P20B TimerO interrupt Port B C interrupts Falling Rising edge 7 1 Interrupt Control Bits and Interrupt Service The interrupt control flags are mapped on 00 and 01 of the system register They can be accessed or tested by the program Those flags are cleared to 0 at initialization by the chip reset Remarks Interrupt enable flags Interrupt request flags When IEx is set to 1 and the interrupt request is generated IRQx is 1 the interrupt will be activated and vector address will be generated from the priority PLA corresponding to the interrupt sources When an interrupt occurs the PC and CY flag will be saved into stack memory and jump to interrupt service vector address After the interrupt occurs all interrupt enable flags IEx are reset to 0 automatically so when IRQx is 1 and IEx is set to 1 again the interrupt will be activated and vector address will be generated from the priority PLA corresponding to the interrupt sources 1 2 3 4 5 Inst cycle Instruction Instruction Instruction Execution Execution Execution N 1 12 Vector Generated Fetch Vector address Interrupt Generated Interrupt Accepted Stack
5. 5 0 1uF AP2 a Operating voltage 5 0V b Oscillator Crystal 4MHz c PORTA PULL UP ON lt lt o o 2 o o o o 211 24 For Approve Only SH69P20B AP3 a Operating voltage 5 0V b Oscillator Ceramic 455KHz c PORTA PULL UP ON 0 o eo o VO gt o o o EH o 10 m NN 0 1u 100p OSCO 100p AP4 a Operating voltage 5 0V b Oscillator RC 1MHz c PORTA C I O PULL UP ON d TimerO input TO y o lt gt 1 oo 7 10KO p N E L 0 1uF gt 80 0 1uF 1000p 25 For Approve Only SH69P20B Bonding Diagram R 5 T T T T S E T A A NN A C T 0 3 2 C C C C C 4 0 GND1 1879 6um OSCO GND2 P P N P P V cc coo o R R R R R R R T T TT CT GT B B B B c c 0 1 2 3 0 1 2 3 1920 24um Note 1 GND1 bonding to ground 2 GND2 bonding to Substratum 3 Substratum connects to ground Pad Location unit
6. WDT Period TWDT 3 0V Frequency Stability RC A F F Low Voltage Reset Electrical Characteristics VDD Parameter RC oscillator 1MHz F 3 0V 2 7 V F 3 0V 2 4 5 5V GND OV 25 C Fosc 4MHz unless otherwise specified Condition LVR Voltage 1 LVR enable LVR Voltage 2 LVR enable 20 For Approve Only SH69P20B AC Characteristics Paramor ___ Tw Wax Unt Tw 3 mw omwen N Proscar divide ww mw tow Puse wan mm Timing Waveform TO Input Waveform TO RESET Osc Built in RC Tosi M gt 21 For Approve Only SH69P20B Typical RC Oscillator Resistor vs Frequency 5V for reference only 5V RC Frequency 10000 00 N 1000 00 0 o LL 100 00 10 00 60 00 110 00 160 00 210 00 260 00 310 00 360 00 R kQ Typical RC Oscillator Resistor vs Frequency for reference only 10000 00 3V RC Frequancy k Hz 1000 00 Fosc 100 00 10 00 60 00 110 00 160 00 210 00 260 00 310 00 360 00 2
7. lt ifAC 0 rece BA2 X 10110 PC ifAC 2 1 10111 lt X 3 ST 1 CALL X 11000 PC X Not including p PC ST lt hhhh lt 1 C wur _ sme Horr ree rence Where __ __ RTNW L 11010 000h hhh Immediate data RAM bank Every 7F as one RAM bank Table Branch Register ROM page 18 SH69P20B Absolute Maximum Rating Comments DC Supply Voltage 0 3V to 7 0V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to this device Input Output Voltage GND 0 3V to Vpp 0 3V These are stress ratings only Functional operation of this device under these or any other conditions above those indicated in the operational sections of this specification is Operating Ambient Temperature s 40 C to 85 not implied or intended Exposure to the absolute maximum rating conditions for extended periods may affect device Storage Temperature 55 C to 125 C reliability DC Electrical Characteristics Voo 5 0V GND OV 25 C Fosc 4MHz unless otherwise specified Parameter in 3 Condition Operating Voltage A
8. 0 R W PORTC 1111 Bit0 3 is reserved 0B 0D User should always keep it to 0000 in the program Equivalent Circuit for a Single I O Pin PULL EN AND PH PL AND AND o DATA WRITE RESET PIN 5 CONTROL PXXOUT WRITE RESET 2011 GND PULL EN gt o AND IL PH PL View 11 For Approve Only SH69P20B System Register 15 1B Address Bit3 Bit2 Bit1 R W Remarks Power On Bit1 PBC interrupt rising failing edge set 15 PULLEN PH PL PBCFR R W Bit2 PORT Pull high low set 010 Bit3 PORT Pull high low enable control PA3OUT 2 PA1OUT R W PORTA input output control 0000 PB3OUT 2 PB10UT PBOOUT R W input output control 0000 18 PC3OUT PC2OUT PC1OUT PCOOUT R W PORTC input output control Bit0 3 is reserved 19 1 User should always keep it to 1111 in the program PAXOUT PBXOUT PCXOUT PDXOUT PEXOUT X 0 1 2 3 PFXOUT X 0 1 1 Used as an output buffer 0 Used as an input buffer Power on initial PBCFR 1 Rising Edge interrupt 0 Falling Edge interrupt PH PL 1 Port Pull high resistor ON 0 Port Pull low resistor ON PULLEN 1 Port Pull high Pull low enable 0 Port Pull high Pull low disable Programming Notice In user
9. Automatic re loads counter 8 level prescaler Interrupt on overflow from FF to 00 The simplified timer block diagram is shown below TOE TOS 5 1 Configuration and Operation TimerO consists of an 8 bit write only timer load register TLOL TLOH and an 8 bit read only timer counter TCOL TCOH Both counter and load register have low order digits and high order digits Writing data into the timer load register TLOL TLOH can initialize the timer counter Load register programming Write the low order digit first and then the high order digit The timer counter is loaded with the contents of the load register automatically when the high order digit is written or the counter counts overflow from FF to 00 Timer Load Register Since the register H controls the physical READ and WRITE operation please follow these rules Write Operation First write Low nibble Then write High nibble to update the counter PRE SCALER TOM ML 8 BIT COUNTER Read Operation High nibble first Followed by Low nibble Load Reg L Load Reg H Latch Reg L For Approve Only SH69P20B 5 2 Interrupt The timer overflow will generate an internal interrupt request when the counter counts overflow from FF to 00 If the interrupt enable flag is enabled then a timer interrupt service routine will proceed This can also be used to waken the CPU from the HALT mode 5 3 Mode Regi
10. For Approve Only PRELIMINARY Features SH6610C Based Single Chip 4 Bit Micro Controller OTPROM 1K X 16 bits RAM 64 X 4 bits data memory Operation Voltage 2 4V 5 5V Typical 5 0V 12 CMOS Bi directional I O Pins Built in Pull high and Pull low Resistor for PortA PortC 4 Level Subroutine Nesting including interrupts One 8 Bit Auto Re load Timer Counter Warm Up timer Powerful Interrupt Sources Interrupt External Interrupts PORTB amp PORTC rising falling edge General Description SINO WEALTH SH69P20B OTP 1K 4 Bit Micro controller Oscillator OTP option Crystal Oscillator 32 768k 4MHz Ceramic Resonator 400k 4MHz RC Oscillator 400k 4MHz External Clock 30k 4MHz Instruction cycle time 4 32 768kHz 122us for 32 768kHz OSC clock 4 AMHz 1us for 4MHz OSC clock Two Low Power Operation Modes HALT and STOP Reset Built in Watch Dog Timer WDT OTP option Built in Power On Reset POR Built in Low Voltage Reset LVR Two LVR Level OTP option Level 1 2 5V Level 2 4 0V OTP type amp Code protection The SH69P20B is a 4 bit micro controller This chip integrates the SH6610C 4 bit CPU core with SRAM 1K OTPROM Timer and Ports Pin Configuration PORTA2 1 PORTA3 2 0 6 7 2 8 PORTB 3 9 5 PORTA 1 0 OSCI OSCO PORTC 3 POR
11. The limitation is applied for the TO period time only The pulse width is not limited by this equation It is summarized as follows 4 tosc 2AT TO TimerO period gt For Approve Only SH69P20B System Register 1C Address Bm2 Bm BIO 1C TO 2 REN edge Bit1 TO signal source TOE TO signal edge 0 Increment on low to high transition TO pin Power on initial 1 Increment on high to low transition TO pin TOS TO signal source 0 OSC A Power on initial 1 Transition on TO pin TOS osca 0 M U gt 8bits TO 1 x x EOR TOE 3 Built in RC Oscillator 2 0 WDT Enable OTP option WDT amp Warm 3 WDTreset _UP Counter M WDT Timeout 10 For Approve Only SH69P20B 6 I O Ports The SH69P20B provides 22 1 pins The port control register controls ON OFF of the output buffer The following sections show the circuit configuration of I O ports Every I O pin has an internal pull high pull low resistor which is controlled by PULLEN and PH PL of 15 Each of these ports contains 4 bits I O pins The port control register can set ports as input or output Port I O mapping address is shown as follows Address Bit3 Bit2 R W Remarks Power On 08 PA 3 PA 2 PA 1 PA 0 R W PORTA 1111 09 PB 3 PB 2 PB 1 0 R W PORTB 1111 0A PC 3 PC 2 PC 1
12. The program counter normally increases by one 1 for every execution of an instruction except for the following cases 1 When executing a jump instruction such as JMP BAO 2 When executing a subroutine call instruction CALL 3 When an interrupt occurs 4 When the chip is in the INITIAL RESET mode The program counter is loaded with data corresponding to each instruction 1 2 ALU and CY ALU performs arithmetic and logic operations The ALU provides the following functions Binary addition subtraction ADC SBC ADD SUB ADI SBI Decimal adjustment for addition subtraction DAA DAS Logic operations AND EOR OR ANDIM EORIM ORIM Decision BAO BA1 BA2 BA3 BAZ BNZ BC BNC Logic Shift SHR The Carry Flag CY holds the ALU overflow which the arithmetic operation generates During an interrupt servicing or call instruction the carry flag is pushed into the stack and retrieved back from the stack by the RTNI instruction It is unaffected by the RTNW instruction 2 OTP ROM For Approve Only SH69P20B 1 3 Accumulator AC The Accumulator is a 4 bit register holding the results of the arithmetic logic unit In conjunction with the ALU data transfer between the accumulator and system register or data memory can be performed 1 4 Table Branch Register TBR Table Data can be stored in program memory and can be referenced by using Table Branch TJMP and Return Constant RTNW instructions The T
13. s program it is necessary to always kept the bit0 3 equal 1 of system register 19H 1BH In user s program it is necessary to always kept the bit0 3 equal 0 of system register 0BH 0DH For reference after the chip reset power on LVR Pin or WDT Reset follow instructions should be put in the start of user s program LDI 19H 1111B LDI 1AH 1111B LDI 1BH 1111B LDI 0000B LDI OCH 00008 LDI 00008 12 For Approve Only SH69P20B PORTB amp PORTC Interrupt The PORTB and PORTO are used as port interrupt sources Since PORT is a bit programmable I O so only the input port can generate an external interrupt When PBCFR is clear to 0 any one of the PORTB and PORTC input pin transitions from to GND will generate an interrupt request And further falling edge transition would not be able to make interrupt request until all of the pins return to VDD When PBCFR is set to 1 any one of the PORTB and PORTO input pin transitions from GND to will generate an interrupt request And further rising edge transition would not be able to make interrupt request until all of the pins return to GND The port interrupt function block diagram is shown below PBOUT 3 PB 3 PBOUT 2 PB 2 PBOUT 1 1 PBOUT 0 PB 0 PCOUT 3 PC 3 PCOUT 2 PC 2 PCOUT 1 1 PCOUT 0 PC 0 PBOUT 3 PB 3 PBOUT 2 PB 2 PBOUT 1 1 PBOUT 0 0 2
14. 0B 00 0 TBR 3 TBR 2 TBR 1 0 XXXX uuuu 1 3 INX 2 INX 1 0 XXXX uuuu 10 11 12 13 14 15 PULLEN PH PL PBCFR 16 PA2OUT PA1OUT PAOOUT 17 PB3OUT PB2OUT PB1OUT PBOOUT 18 PC3OUT 200 PC1OUT PCOOUT 19 1B 1C TOS 1D 1E 1F Legend x unknown unchanged unimplemented read as 0 For Approve Only SH69P20B 3 3 Others Initial State Others After any Reset Program Counter PC 000 CY Undefined Accumulator AC Undefined Data Memory Undefined 4 System Clock and Oscillator System clock generator produces the basic clock pulses that provide the system clock to the CPU and any peripherals Instruction cycle time 1 4 32 768kHz 122us for 32 768kHz Oscillator 2 4 4MHz 1us for 4MHz Oscillator 4 1 Oscillator Type 1 Crystal oscillator 32 768kHz 4MHz C1 Crystal 4MHz C2 2 Ceramic resonator 400kHz 4MHz C1 Ceramic 400k AMHz C2 3 RC oscillator 400kHz 4MHz VDD R OSCI C1 1000p OSCO 4 External input clock 30kHz 4MHz OSCI External clock source OSCO 5 For Approve Only SH69P20B SH69P20B has one 8 bit timer The time counter has the following features 8 bit up counting timer counter
15. 2 For Approve Only SH69P20B In System Programming Notice for OTP The In System Programming technology is valid for SinoWealth OTP chip The Programming Interface of the OTP chip must be set on the user s application PCB and users can assemble all components including the OTP chip in the application PCB before programming the OTP chip Of course it s accessible bonding OTP chip only first and then programming code and finally assembling other components Since the programming timing of Programming Interface is very sensitive therefore four jumpers are needed VPP SDA SCK to separate the programming pins from the application circuit as shown in the following diagram Application PCB OTP Chip VPP VDD SCK OTP Writer SDA 19 9 To Application Circuit Jumper The recommended step is as follow for these jumpers 1 The jumper is Open to separate the programming pins from the application circuit before programming the code 2 Connect the programming interface with OTP Writer and Begin Programming code 3 Disconnect OTP writer and short these jumpers when programming is finished For more detail information please refer to the OTP writer user manual 23 For Approve Only SH69P20B Application Circuits for reference only AP1 a Operating voltage 5 0V b Oscillator Crystal 32 768KHz c PORTA PULL UP ON
16. NX 1 INX O R W Pseudo index register 10 DPL 3 DPL 2 DPL 1 DPL O R W Data pointer for INX low nibble 11 DPM 2 DPM 1 0 R W Data pointer for INX middle nibble 12 DPH 2 DPH 1 R W Data pointer for INX high nibble 13 14 Reserved Bit1 PBC interrupt rising failing edge set 15 PULLEN PH PL PBCFR R W Bit2 PORT Pull high low set Bit3 PORT Pull high low enable control 16 PA3OUT PA2OUT PA1OUT PAOOUT R W PORTA input output control 17 PB3OUT PB2OUT PB1OUT PBOOUT R W PORTB input output control 18 PC2OUT PC1OUT PCOOUT R W PORTC input output control Bit0 3 is reserved Always keep it to 711118 19 1B in the User s program Refer to 1 notice me nw Bi To sga sdo 1D Reserved 1E WDT W WDT timer reset write 1 to reset WDT 1F Reserved System Register 0E 12 refer to SH6610C User manual For Approve Only SH69P20B Power On Reset Address Bit 3 Bit 2 Bit 1 Bit 0 Reset WDT Reset Low Voltage Reset 00 IETO IEP 0 0 0 0 01 IRQTO IRQP 0 0 0 0 02 2 TMO 1 0 0 000 000 503 04 TLO 3 TLO 2 TLO 1 TLO O 0000 0000 05 THO 3 0 2 THO 1 0 0 0000 0000 06 07 08 PA 3 PA 2 PA 1 0 1111 1111 509 PB 3 PB 2 PB 1 0 1111 1111 0A PC 3 PC 2 PC 1 0 1111 1111
17. TC 2 PORTC 1 0 V0 0 Block Diagram XTAL RC OTP OPTION OTP PROTECT WATCHDOG OUT TIMER INTERRUPT GND For Approve Only SH69P20B RESET PORTA 3 0 PORTB 3 0 PORTC 3 0 For Approve Only SH69P20B Pin Description Normal Mode Pin No Designation Descriptions 17 18 1 2 PORTA 0 3 Bit programmable TO Timer Clock Counter input pin Schmitt trigger input RESET Reset input active low Schmitt trigger input GND Ground pin Bit programmable 0 3 Vector Interrupt Active rising or falling edge by system register setup Bit programmable I O PORTE 0 3 Vector Interrupt Active rising or falling edge by system register setup VDD Power supply pin OSCO OSC output pin No output in RC mode OSC input pin connected to a crystal ceramic or external resistor Description Programming Power supply 5 5 GND Ground Los Function Description 1 CPU The CPU contains the following function blocks Program Counter Arithmetic Logic Unit ALU Carry Flag Accumulator Table Branch Register Data Pointer INX DPH DPM and DPL and the Stack 1 1 PC Program Counter The Program Counter is used to address the 4K program ROM It consists of 12 bits the Page Register PC11 and the Ripple Carry Counters PC10 PC9 PC8 PC7 PC6 PC5 PC2 PC1 and PCO
18. able Branch Register TBR and Accumulator AC is placed by an offset address in program ROM TJMP instruction branch into address 11 PC8 X 28 TBR AC The address is determined by RTNW to return look up value into TBR AC ROM code bit7 bit4 is placed into TBR and bit3 bitO into AC 1 5 Data Pointer The Data Pointer can indirectly address data memory Pointer address is located in register DPH 3 bits DPM 3 bits and DPL 4 bits The addressing range can have 3FFH locations Pseudo index address INX is used to read or write Data memory then RAM address bit9 comes from DPH DPM and DPL 1 6 Stack A group of registers are used to save the contents of CY amp PC 11 0 sequentially for each subroutine call or interrupt It is organized into 13 bits X 4 levels The MSB is saved for CY 4 levels are the maximum allowed for subroutine calls and interrupts Note The contents of the Stack are returned sequentially to the PC with the return instructions RTNI RTNW The stack is operated on the first in last out basis This 4 level nesting includes both subroutine calls and interrupt requests Note that a program execution may enter an abnormal state if the number of calls and interrupt requests exceeds 4 and the bottom of the stack will be shifted out The SH69P20B can address up to 1K X 16bits words of the program area from 000 to 3FF Service routine serves as the starting vector address Add
19. cs 3 0V GND 25 Fosc 4MHz unless otherwise specified Parameter Condition Operating Voltage Operating Current All output pins unloaded Execute NOP instruction Stand by Current HALT All output pins unloaded Stand by Current STOP All output pins unloaded LVR off If LVR on IsB2x 1582 2uA WDT off If WDT on IsB2X 1582 20uA Input Low Voltage GND 0 2 X VDD ports pins tri state Input Low Voltage GND 0 15 X RESET TO Input Low Voltage GND 0 15 X OSCI Driven by external clock Input High Voltage 0 8 X VDD ports pins tri state Input High Voltage 0 85 X VDD RESET TO Input High Voltage 0 85 X VDD V OSCI Driven by external Clock ports GND lt lt VDD Output High Voltage ports loH 7mA 3V Output Low Voltage User Notice Max Current into 100mA Max Current out of GND 150mA Max Output current sunk by any 1 port 50mA Max Output current sourced by any 1 port 40mA 0 4 ports loL 8mA AC Electrical Characteristics 3 0V GND OV 25 C unless otherwise specified Parameter Symbol Condition Oscillator Start Time 1 Crystal Osc 32 768kHz Vpp 3 0V RESET pulse width low TRESET 3 0V
20. egister 1E was mu The input clock of the watchdog timer is generated by a built in RC oscillator so that the WDT will always run even in the STOP mode SH69P20B generates a RESET condition when the watchdog times out The watchdog can be enabled or disabled permanently by using the OTP option To prevent its timing out and generating a device RESET condition you should write this bit as 1 before timing out The WDT has a time out period of more than 7ms typical 18ms If longer time out periods are desired a prescaler with a division ratio of up to 1 2048 can be assigned to the WDT under software controlled by writing to the TMO register Pre scaler divide ratio TMO0 2 TMO 1 0 Prescaler Divide Ratio Timer out Period 1 1 1 1 1 7ms 1 1 0 1 2 14ms 1 0 1 1 4 28ms 1 0 0 1 8 56ms 0 1 1 1 32 224ms 0 1 0 1 128 896ms 0 0 1 1 512 3 584ms 0 0 0 1 2048 Power on initial 14 336ms WDT Time 0 875ms out Period NON min PRESCALER TMO 307 5 Internal 7ms mi RGOSC SCALER 1 18 12 14 18 132 1128 1512 12048 Final WDT Time out period 15 5 69 20 10 HALT and STOP Mode After the execution of HALT instruction the device will enter halt mode In the halt mode CPU will stop operating But peripheral circuit TimerO will keep operating After the execution of STOP instruction t
21. he device will enter stop mode In the stop mode the whole chip including oscillator will stop operating without watchdog timer if it is enabled In HALT mode SH69P20B can be waked up if any interrupt occurs In STOP mode SH69P20B can be waked up if port interrupt occurs or watchdog timer overflow WDT is enabled 11 OTP Option 11 1 Oscillator External Clock System Clock is provided by External Clock through OSCI RC Osc System Clock is provided by External RC through OSCI Crystal Ceremic Resonator 400k 4M System Clock is provided by Crystal Ceremic Resonator through OSCI and OSCO X tal 32768 System Clock is provided by Crystal 32 768k through OSCI and OSCO 11 2 Watchdog Timer Enable Enable the watchdog timer Disable Disable the watchdog timer 11 3 LVR Off Disable the LVR function On Enable the LVR function 11 4 LVR Voltage 4 Generate an internal reset signal when lt 4V if LVR enable 2 5V Generate an internal reset signal when lt 2 5V if LVR enable 11 5 Osc 32k 2M The Oscillator frequency is between 32768Hz and 2MHz 2M 4M The Oscillator frequency is between 2MHz and 4MHz 16 r For Approve Only SH69P20B Instruction Set All instructions are one cycle and one word instructions The characteristic is memory oriented operation Arithmetic and Logical Instruction Accumulator Type Mnemonic Instruction Code Function Flag Change ADC 00000 Obbb xxxx lt
22. ing Reset IE X Start at vector address During the SH6610C CPU interrupt service the user can enable any interrupt enable flag before returning from the interrupt The servicing sequence diagram shows the next interrupt and the next nesting interrupt occurrences If the interrupt request is ready and the instruction of execution N is IE enable then the interrupt will start immediately after the next two instruction executions However if instruction 11 or instruction I2 disables the interrupt request or enable flag then the interrupt service will be terminated Interrupt Servicing Sequence Diagram Interrupt Nesting 14 For Approve Only SH69P20B 8 Low Voltage Reset LVR The LVR function is to monitor the supply voltage and generate an internal reset in the device It is typically used in AC line applications or large battery where large loads may be switched in and cause the device voltage to temporarily fall below the specified operating minimum The LVR function is selected by OTP option The LVR circuit has the following functions generates an internal reset signal when lt VLVR cancels the internal reset signal when gt VLvR Here power supply voltage VLvR LVR detect voltage There are two levels selected by OTP option Level 1 2 3 2 7V typical 2 5V Level 2 3 8 4 2V typical 4 0V LVR can be enabled or disabled permanently by OTP option 9 Watch Dog Timer WDT System R
23. ll output pins unloaded Execute NOP instruction Stand by Current HALT All output pins unloaded All output pins unloaded Stand by Current STOP LVR off If LVR on IsB2x 1582 2uA WDT off If WDT on IsB2x 1582 20 Input Low Voltage GND 0 2 X ports pins tri state Operating Current Input Low Voltage GND 0 15 X RESET TO Input Low Voltage GND 0 15 X OSCI Driven by external clock Input High Voltage 0 8 X VDD ports pins tri state Input High Voltage 0 85 VDD RESET TO Input High Voltage 0 85 X OSCI Driven by external Clock Input Leakage Current fe ports GND lt lt Input Leakage Current m2 5 Vreser GND 0 25V Input Leakage Current Input Leakage Current uA GND lt OSCI PULL HIGH PULL LOW resistor ports 10mA Output Low Voltage VoL ports loL 20mA 1 1 1 Input Leakage Current 115 3 Pull high Pull low Resistor RP 150 VOH Output High Voltage Parameter Symbol in 2 Condition Oscillator Start Time X tal osc 32 768kHz RESET pulse width low TRESET 5 0V WDT Period TwDT 5 0V Frequency Stability RC A F F RC Oscillator F 5 0V F 4 5V F 5 0V 19 For Approve Only SH69P20B DC Electrical Characteristi
24. ress Instruction Remarks 000H JMP Instruction Jump to RESET service routine 001H NOP Reserved 002H JMP Instruction Jump to TIMERO service routine 003H NOP Reserved 004H JMP Instruction Jump to PBC service routine 3 For Approve Only SH69P20B The built in RAM consists of general purpose data memories and system registers Direct addressing in one instruction can access both data memory and system register The memory allocation map is shown below 000 01F System register and I O 020 05F Data memory 64 X 4 bits 3 1 The Configuration of the System Register Address Bit3 Bit2 Bit1 R W Remarks 00 R W Interrupt enable flags 01 IRQTO IRQP R W Interrupt request flags 02 TMO 2 TMO 1 0 0 R W TimerO Mode register Prescaler 03 Reserved 04 TLO 3 TLO 2 TLO 1 TLO O R W TimerO load counter register low digit 05 THO 3 2 THO 1 0 R W TimerO load counter register high digit 06 07 Reserved 08 PA 3 PA 2 0 R W PORTA 09 PB 3 PB 2 PB 1 PB O R W PORTB 0A PC 3 PC 2 PC 1 0 R W PORTC Bit0 3 is reserved Always keep it to 0000B 0B 0D in the User s program Refer to 1 notice 0E TBR 3 TBR 2 TBR 1 TBR O R W Table Branch Register INX 3 INX 2 I
25. ster The timer can be programmed in several different prescaler ratios by setting the Timer Mode register TMO The 8 bit counter counts prescaler overflow output pulses The timer mode registers TMO are 3 bit registers used for timer control as shown in table1 These mode registers select the input pulse sources into the timer Timer 0 Mode Register 02 Prescaler Divide Ratio Ratio N 12 2048 initial 12 512 12 128 127 32 12 8 4 2 5 4 External Clock Event TO as Source When an external clock event input is used for the TMO it is synchronized with the CPU system clock Therefore the external source must follow certain constraints The output from the TOM multiplex is TOC It is sampled by the system clock in instruction frame cycle Therefore it is necessary for the TOC to be high at least 2 tosc and low at least 2 tosc When the prescaler ratio is set to 2 the TOC is the same as the system clock input Therefore the requirements are as follows TOCH TO high time gt 2 tosc AT TOL TOCL TO low 2 tosc AT Note AT 20ns When another prescaler ratio is selected the TMO is scaled by the asynchronous ripple counter and so the prescaler output is symmetrical Then 20 N TO TOC high time TOC low time 2 Where TO TimerO input period prescaler value The requirement is therefore gt 2 tose AT or TO gt
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