Home

Chapter 5-Electronics - antares

1. PIE Picture of the UNIV1 Board Associated Technical Notes e 3 LCM 08 01 A UNIVI user s manual e 3 LCM 08 02 A MODBUS reference guide Page 5 49 Next Up Previous Contents PBS 2 1 014 BIDIANT board in LCM container and SCM container Schematic diagramme of the BIDIANT transceiver Mntieal Fihre LYPECL Laser Driver MAX3667 Laser PIN diode Optical Filter Tiahla taser lacer omponent pense Fol hiaai Thiac Imod Imad p WotR Mah e Mat T Transimpedance LVPECL Limiting Amplifier a Ar e Filter MC2045 CS The main specifications of the BIDIANT transceiver board are e Bidirectional distribution of Ethernet or clock distribution using only one optical fibre e Ethernet transmission between LCM slaves and LCM master inside sector with 1310 1310 nm bi directional capability e Clock distribution inside sector with 1310 1550 nm for LCM and 1550 1310nm for SCM containers e Modulation current between 5 to 60 mA with a maximum optical power of 3 dBm for laser diode e Laser diode current between 5 to 30 mA with APC power control e Receiver part with transimpedance and limiting amplifier with a sensitivity better than 23 dBm for 1310 1550 nm and 20 dBm for 1310 1310 nm e Each transceiver board produce voltages to allow monitoring of the laser diode modulation and bias current These parameters can be read by the Slow Control of t
2. 33 ps C TVC drift as a function of temperature Nts 24 bits Dynamic range of the Time Stamp TWinin 12 ns 70 ns Minimum LO trigger pulse width The maximum pulse width is 4 TW nin Vthy 9 15 mV 5 mV Minimum LO trigger threshold DVthy 9 20 Threshold accuracy including drift Tbr 20 ns 100ns_ 0 lt Tby lt 200 ns Return timing of the L1 trigger Tbr lus 35 us Return timing of the L2 trigger Links to ARS event formats e STATUS event e RTS event e CRM event e SPE event e WAVEFORM event e WAVEFORM DYNODES event Page 5 35 Link to ARS Slow control parameters PPT TPP EPO SUPE EEE TT TZZZINI amp TOU Ea 300 2200000010 90000008 Photo of the ARS chip Associated Technical Notes e 3 LCM 15 01 C ARS motherboard e Elec 2000 6 ARSI Analogue Ring Sampler and ARS CONV Users Manual V1 9 e ARS results for physicists Page 5 36 Next Up Previous Contents PBS 2 1 005 MLCM_ BIDICON board in Master LCM container Schematic diagramme of the LCM_BIDICON board UNIV 1 function With slow control with MODBUS PS485 protocol The main functions of the MLCM_BIDICON board are e Concentration of Ethernet channels from each LCM slaves of one sector e Optical electrical conversion with BIDIANT daughters boards transceivers 4 boards one for each LCM slave container e Monitoring of the Voltage of each BIDIANT daughter board e Slow contr
3. Next Previous Contents Chapter 5 Electronics Introduction DAQ and Slow control function Power Distribution Clock Distribution Trigger distribution Hardware Implementation Reliability qualification and Accelerated Stress tests Test benches and test scenarios Electronics PBS and Individual Object Description o PBS 2 1 LCM Local Control Module electronics of a Storey o PBS 2 2 SCM String Control Module DAQ SC clock distribution sensors acoustic positioning o PBS 2 3 SPM String Power Module power conversion for each string o PBS 2 4 JB Junction Box Clock distribution and trigger construction o PBS 2 5 ONSHORE Clock Clock objects on shore Page 5 1 Next Up Previous revious Contents Electronics Introduction The main purpose of the ANTARES electronics is to provide a hardware implementation in which the following functions can be performed e data acquisition slow control e power distribution e clock distribution e trigger distribution Technical aspects mechanics connections thermal cooling concerning all the boards are described in the section on Hardware implementation The reliability of the offshore electronics is an important issue and requires careful choice of components and testing of the electronics prior to deployment The electronics are located in various pressure resistant containers of the detector architecture as summar
4. Page 5 94 e ON SYNCPCI board to provide a heartbeat rate needed for the PC onshore synchronization e Slow Control for board monitoring List of References e 3 LCM 03 01 Numerical clock distribution for ANTARES Proposal e 3 LCM 03 02 Clock Distribution ON SHORE for ANTARES Proposal Page 5 95 Next Up Previous Contents PBS 2 5 004 ON WDM onshore Schematic diagramme of the ON_WDM board The main specifications of the ON_WDM module are e Bi directional electrical optical module using WDM Wavelength Division Multiplexing concept to send the reference clock and control words from ON_CLOCK to all LCM_CLOCK boards Receive status words from selected LCM_CLOCK board e The wavelength of the optical signals are 1535 nm from ON_WDM to SCM_WDMI and 1549 nm for the opposite direction e Slow control parameters reading for board monitoring with UNIV1 daughter board The main parameters are Optical signal reception Switching ON OFF laser driver Temperature measurement e The temperature of the laser is controlled byThermoelectric Cooler controller TEC DN1220 ThermoOptics Interfaces to e ON CLOCK board through the Input Output PECL channels 200 Mbits s e SCM_WDMI boards through the shore cable Optical fibre 50 Km e ON CRATEI for the Slow control functions by RS485 List of References Page 5 96 e 3 LCM 03 01 Numerical clock distribution for ANTARES Proposal e 3 LCM 03 02
5. e Optical I O to E O O E Board for Slow Control of the SCM e Optical I O from the MLCMs and to the JB Associated Technical Notes e http www nikhef nl n05 antares ETR_ Notes ETR2000 07s pdf e http www nikhef nl n05 antares ETR_Notes ETR2000 08s pdf Page 5 76 Next Previous Up Contents i Electrical Power System PBS list PBS 2 3 The String Power Module SPM Schematic view of the SPM sor J 370 ra teda D 7 ik HA E E Y B au ETA a al ESE amp 1 IT we I sio contro The String Power Module SPM is fed by the 1000 Vac of the Junction Box It converts the 1000 Vac to 400 Vdc for use in the LCMs of a string It also provides 48 Vdc for the control systems of the SPM and SCM The SPM consists of three pairs of ring core transformers each pair feeds two sectors and each has a fuse to prevent shorting of the 1000 V by a single transformer Each output has a Solid State Relay SSR which isolates a sector in the case of failure inside a LCM A Power Factor Corrector PFC circuit provides an almost resistive load to the transformer giving high efficiency rectification and low noise All output currents voltages and the supply temperatures are monitored by the Slow Control UNIV board All outputs can be switched on off by remote control Over temperature and over current situations are handled locally Page 5 77 The thermal cooling of the SPM is understudy th
6. RoR optical signals for accept event LCM_DAQ SC board L1 L2 RoR information for monitoring purposes LCM_CLOCK board for clock signal Enable Disable Trigger Pulse _Trig signals CRMW Continuous Rating Monitor Warning signal from ARS boards LCM upper lower via Optical fibres for L1 L2 RoR signals propagation Associated Technical Notes ANTARES Elec 2000 07 Level I Level 2 Offshore trigger 3 LCM 06 01 Trigger Board Interfaces Description 3 LCM 20 01 LCM internal organisation a proposal 3 LCM 03 02 Clock Board interfaces description Page 5 40 Next Up Previous Contents PBS 2 1 007 LCM CLOCK board in LCM container Schematics of the LCM_Clock board OVE conversion module BIDIANT transceiver FPGA decoding orders Transceiver with frame Two Bytes Mask reconstruction and clock z Broadcast Function reconstruction data otatus HOTLINK chips Slow control The main functions of the LCM_CLOCK board are e Distribution inside the LCM of the onshore reference clock 20 MHz to all boards which used this signal for the time stamp or command functions e Generation of synchronous commands via lines on the backplane for ARS Enable Reset DAQ Enable Reset acoustic positioning system low rate and high reset Trigger Enable window pulse e Return path possibility in order to read status byte from a specific LCM to shore station e Slow c
7. are received by a bi directional Ethernet concentrator board LCM_BIDICON and the optical signals are converted to electrical Page 5 5 signals The signals are passed via the backplane to the MLCM_SWITCH board where the five sets of signals are combined and then passed via coaxial SMB connectors to the MLCM_ DWDM board This board converts the gigabit Ethernet signals into optical signals of a DWDM system 1535 nm 1570 nm and sends them to the SCM e outlin shore side At r 14 2 erbe basic DIOR ot Ne process E D E G w 2 at 1310 nm ole receiver Figure 3 The onshore DWDM system Page 5 6 At the SCM the optical signals from the six MLCMs of a string are received by a passive optical multiplexer SCM_DWDM MUX and combined onto a single fibre each MLCM having its unique pair of wavelengths The Slow Control information is also included in the wavelength multiplexing as a seventh wavelength In order to do this the Slow Control information passes through the SCM DWDM board prior to inclusion The data then passes through the Junction Box to the shore station An equivalent system on shore demultiplexes the wavelengths as shown in figure 3 The optical power budget including all connections and feed throughs in the optical path has been studied for the DAQ clock and trigger distri
8. 1550nm k I Lem clock A 1310 nm A A 1549 nm lt Clock distribution The actual implementation of the clock distribution network is based on a bi directional communication system Between the shore and the JB the 1534 nm and 1549 nm wavelengths are used In the detector ICC and EMC the 1310 nm and 1550 nm wavelengths are used The return path is used to measure the propagation delay between the on shore clock system and the LCMSs in the detector This delay is measured using a commercial Time to Digital Converter SRS620 Stanford Research company A precision of better than 0 5 ns on the propagation time from shore to the addressed LCM only one LCM is addressed at a time has been obtained The return signal capability is also used to send data DAQ CLK STATUS to shore for test and debugging The complete list of data commands that can be transmitted by the clock system are given below CLK ARS RST TS reset time stamp of all ARSs global CLK ARSi LED PL generation of a LED pulse CLK ARS ENA enable disable the ARS addressable CLK DAQ RST hardware reboot of processor CLK DAQ ENA enable disable DAQ processors CLK TRIG ENA enable disable off shore trigger CLK TRIG PULSE enable temporarily the off shore trigger CLK AC RSTI acoustic reset slow CLK AC RST2 acoustic reset fast Page 5 11 Details of this clock distribution are described in the technical notes e 3 LCM 03 01 C Numerical clock distributio
9. 5 18 Next Previous Up Contents Reliability Qualification and Accelerated Stress Test The reliability of the offshore electronics is crucial for the long term operation of the detector The objectives for the overall reliability of the detector are discussed in Chapter 10 There are three ways to optimise the reliability of the off shore electronics e Choose the components in order to have the best mean time between failure compatible with availability price and power requirements e Require that all designs pass an electronics qualification test before adoption based on the expected environmental life profile e Define a common burning test scenario in order to eliminate bad manufacturing and infant mortality Electronics qualification In order to improve the reliability the environmental life profiles of the embedded electronics have been studied resulting in the following qualification tests for the design which will be verified on the first boards e Cold temperature Storage at 0 C in a wooden crate during transport e Dry heat storage at 60 C in a crate during transport working a few minutes at 40 C without its packaging Damp heat storage at 50 C and 93 relative humidity RH container open Condensation Damp heat at 40 C and 93 RH container open Immersion Working at 3 metres depth in 25 C seawater for 24 hours Salt fog Container closed on quay for one month wi
10. 5 5 5 5 5 gt va 3 Q 9 5 O O O O wa A x T D D D O D s A a a a lt a a lt 4 z z D D O ajja n Cll all all all all a 0000068 The main functions of the SCM_BACK board are e Distributes inside the SCM container all signals from or to each board inserted inside the SCM_CRATE e Distributes electrical power 5V 3 3V 2 5V 1 8V 12V 48V and common return all these power signals come from the POWER_BOX fixed on the SCM_CRATE e The SCM BACK interfaces between the optical modules signals and the ARS_MB POWER_BOX and COMPASS MB electronics boards e Each board has a fixed location in order to optimise EMC and parallel development e Controls the SPM container slow control function through a second RS485 twisted pair with MODBUS protocol Interfaces inside the SCM are e Each board inserted in the SCM_CRATE is connected to the SCM_ BACK with its rear connector 24 48 or 96 pins e connector interfaces with the laser beacon PMT configuration for one line only e connector interfaces with other containers for RS232 and second RS485 serial bus this connector also transmits the test signal for LCM DAQ SC board external test trigger signal This connector drives also the main RS485 serial bus for all boards inserted inside SCM_CRATE in order to test slow control without the LCM DAQ SC board e The second RS485 twisted pair controls the SPM slow control function e The boards inse
11. 5 69 Associated Technical Notes 3 LCM 03 01 Numerical clock distribution for ANTARES Proposal 3 LCM 03 02 Clock Board interfaces description 3 LCM 18 02 Clock distribution prototypes tests 3 SCM02 01 SCM internal organisation Page 5 70 Next Up Previous Contents PBS2 2 005 SCM CLOCK board in SCM container Schematic view of the Clock board FPGA decoding orders Transceiver with frame Two Bytes Mask reconstruction and clock eis Broadeast Function reconstruction ata fotatus HOTLINK chips EEEIEE IE a SR i dA Specifications e Distribution inside SCM container of the reference clock 20 MHz from shore to all boards which use this signal for physics time stamp for example ARS boards e Generation of synchronous signals for ARS Enable Reset DAQ Enable Reset Acoustic positioning system low rate and high reset Trigger Enable window pulse e Return path possibility in order to read status byte from specific LCM to shore station e Slow control parameters reading for board monitoring with UNIV1 daughter board The main parameters are optical signal detection temperature measurement laser bias current and modulation byte status filter addressing mask configuration etc Interfaces inside SCM are e DAO SC board for clock signal reset enable and slow_control RS485 bus by twisted pairs on backplane e SCM_WDM board with twisted pairs
12. Clock Distribution ON SHORE for ANTARES Proposal Page 5 97 Next Up Previous Contents PBS 2 5 005 ON_SYNCPCI ON SHORE PC CLOCK PCI SYNCCLOCK32 BRANDYWINE board PCI SyncClock32 Single slot 32 bit 5 Volt PCI module IRIG A B NASA 36 1 PPS sync inputs e GPS sync option maintains single slot e Have Quick sync input option e Propagation delay correction Zero latency time reads e Match Time output IRIG B time code output External Event time tags Three user programmable rates The main specifications of the ON_SYNCPCI module are e Provide absolute Date and Time in relationship with the UTC signal from the GPS e Provide Time stamp of the control word sending with 100ns precision time e Provide IRIG B protocol generator allowing absolute Date and Time sending to other computer Interfaces to e GPS UTC Universal coordinated Time output for synchronous time function e ON CLOCK board from Time stamp output to the PC SYNC Event time tags input e IRIG B generator output to reception of IRIG B PC Board with another computer List of References e 3 LCM 03 01 Numerical clock distribution for ANTARES Proposal e 3 LCM 03 02 Clock Distribution ON SHORE for ANTARES Proposal e http www brandywinecomm com Page 5 98 Up Previous Contents PBS2 5 006 ON_PCIO onshore PC CLOCK PCIO DIO 32HS National Instruments board Q lt S amp Figure 3 3 DAQCard 6533 Block Di
13. PECL on backplane SCM_BACK e Acoustic board SCM_RxTx boards for clock signal and resets by twisted pairs on backplane e ARS boards for clock signal and reset by twisted pairs on backplane Page 5 71 e ARS laser beacon for clock signal and reset by twisted pair on backplane e POWER BOX for voltage 5 V and 3 3 V by backplane Technical Notes e 3 LCM 03 01 Numerical clock distribution for ANTARES Proposal e 3 LCM 03 02 Clock Board interfaces description e 3 LCM 18 02 Clock distribution prototypes tests e 3 SCMO02 01 SCM internal organisation Page 5 72 Next Up Previous Contents PBS 2 2 006 SCM DWDM Board in SCM container Schematic diagramme of the SCM DWDM Board Single SCM DVWDM Board Channel Sea Side Board wigan i peereeeeseereeerenreeree ReadOnly si lt MODBUS 44a ti TEC_CNTL i Cooling i DWDM il BN OL A es bei Fast 2i BiDirectional e caiaiele neele sa AA E H Ethernet il Fast Ethernet Filter 9SOMHz Optical _ coded bitst p PECO SETS Connections i ECR i J mM HH t4 e SS Le x 3 3V 4 Power i 5 0V zi Conditioner o i The SCM DWDM Board converts the Fast Ethernet signals from the DAC SC Board into the optical signals of a Dense Wavelength Division Multiplexing DWDM system and vise versa Important parts on this board are the DWDM Laser and the Pin Diode Receiver The DWDM Laser is a Distributed Feedback type with very narrow s
14. and full duplex e Configured at power up Interfaces inside LCM are e Master LCM BIDIANT board The BIDIANT transceivers which receive the link coming from all the LCM DAQ SC boards of a sector are connected to 4 Fast Ethernet transceivers Page 5 57 via PECL signals over the backplane e MLCM DWDM for the Gigabit link over coaxial cables e LCM power box for power 3 3V and 2 5V e The local LCM DAQ SC board Page 5 58 Next Previous Up Contents pak PBS2 2 The String Control Module SCM The String Control Module SCM contains the electronics concerning the Slow Control clock and instruments for acoustic positioning and sea properties The SCM container is similar to the LCM container and is located in the Botttom String Socket BSS It is coupled to the String Power Module SPM The individual cards in the SCM have dedicated test benches as is the case for the LCM cards The tests foreseen for the SCMs are summarised in the page on Integrated SCM test benches Components in a SCM Objects in SCM Description FBS number SCM container Titanium container 1 2 006 SCM_CRATE support of boards and backplane 2 2 001 distributes signals between boards in SCM_BACKI SCM_CRATE 2 2 002 SCM WDMI optical transceiver WDM with clock 22 003 distribution SCM_REP optical transceiver to regenerate clock signal 2 2 004 SCM CLOCK Clock distribution for SCM 2 2
15. and thermal conduction Technical notes e 3 LCM 02 01 Integration LCM e 3 LCM 02 03 shielding 3 LCM 02 04 crown 1 3 LCM 02 05 crown 2 e 3 LCM 02 06 Slides Page 5 27 Next Up Previous Contents PBS 2 1 002 LCM BACK board in LCM container Schematic diagramme of LCM_BACK board ARS MB for ARS MB for ARS_MB for kdball LCM DWDM LCM SWITCH LCM BIDICON LCM DAO SC LCM TRIG LCM CLOCK LCM ACQUST Lem Acoust LCM ACQUST a The main functions of the LCM_BACK board are e Distribution inside the LCM container of all signals from or to each board inserted inside the LCM CRATE e Distribution of electrical power 5V 3 3V 2 5V 1 8V 12V 48V and common return all these power signals come from the POWER_BOxX fixed on the LCM CRATE which converts the 400V DC to all values needed inside the LCM e Interfaces between optical modules signals and the electronics boards ARS_MB POWER BOX and COMPASS MB Interfaces inside the LCM are e Each board inserted in the LCM CRATE is connected to the LCM _ BACK by its rear connector 24 48 or 96 pins The location of each board is fixed in order to optimise parallel development and connections to the EMC e 4 connectors provide the interface with the optical modules and the LED beacon e connector makes the interface with other containers for RS232 and the second RS485 serial bus this connector provides the test signal for
16. developed to measure and test this complete object The results of these tests are also entered on the Web pages for incorporation into the general database Examples of complete test benches are e LCM test bench scenario and for summary web page LCM test bench schematic e SCM test bench scenario and for summary web page SCM test bench schematic After integration of the electronics boards inside the containers these final objects are sent for line integration During the line integration of each LCM container the good functionality of the electronics and the connections between all objects are tested These results are also incorporated in the general database Page 5 21 Next Previous Up Contents PBS PBS2 1 The Local Control Module LCM The Local Control Module LCM contains the electronics boards for all functionalities at the storey level readout DAQ SC power clock and trigger It is housed in a LCM container and is linked to the next floors of LCM by 10 m of Electro Mechanical cable EMC The first LCM on the bottom is linked to the SCM SPM and the last LCM is connected to the Buoy Penetrator position Titanium tube Inner rack Connector position In a given sector there are 5 storeys one called the Master LCM which has an Ethernet switch a bidirectional concentrator and a DWDM board that are not in the other LCMs The 4 slave LCMs are of 3 types e s
17. e a oe __SSTTTO A RR LO triggere LIL Readout request Counting Rate Reset Time Stamp CRM Warning Monitor From CLOCK 20MHz gt The Analogue Ring Sampling chip performs the off shore processing of the PMT signals It is located on the ARS motherboard of a LCM container The anode signal is sent to the comparator the charge integrator the Pulse Shape Discriminator and the GHz waveform sampler When a pulse exceeds the LO trigger threshold of the comparator its charge is integrated and the waveform is sampled while the PSD analyses the pulse shape and compares it to the predefined mask At the end of the integration gate the PSD returns the binary result whether the pulse is of the SPE type or the Waveform WF type The timing of the signals is given by an external reference clock the Time Stamp TS counts the reference clock pulses and the Time to Voltage Converter TVC provides an analogue signal proportional to the time from the last clock signal to the instant when the pulse crossed the LO threshold A pipeline memory is used to store the analogue and digital data The pipeline consists of 16 memory cells to store up to 16 pulses Each memory cell contains two analogue values the integrated charge and the TVC and 26 bits of digital data the 24 bit Time Stamp the 1 bit PSD result and 1 bit to indicate if WF data has effectively been sampled Once this information has been stored in the pipeline the compar
18. on the network synchronisation concept used in the telecommunications industry in which digital data are superimposed on a high frequency reference clock The combined signal is sent to the detector and distributed to all LCMs In each LCM the original clock signal and the data are decoded A functional diagram of the clock system is shown below The reference clock is generated on shore ON_GPS using a high accuracy 20 MHz clock synchronised internally to the GPS time with an accuracy of 100 ns The clock is passed to the ON CLOCK board where any clock commands are superimposed The clock electrical signal is converted to an optical signal in the ON WDM board which transmits the signal to the Junction Box via a single optical fibre using standard telecommunication transceiver chips HOTLINK chips from Cypress company With this configuration the time jitter was measured to be less than 100 ps A passive splitter inside the Junction Box JB_SPLIT1 divides the optical clock signal into 16 different channels one for each string plus spares Inside the SCM an Optical Electrical conversion SCM _WDM regenerates the signal and an Electrical Optical conversion SCM_REP sends the clock signal to the LCM CLOCK board of each LCM container The LCM CLOCK board reconstructs the clock and decodes any associated command making them available on the LCM backplane Page 5 10 ON SHORE OFF SHORE Taps LCMI Line 1 Sector 1 A
19. only for board monitoring with UNIV1 daughter board The main parameters are optical signal detection laser temperature measurement laser Page 5 53 wavelength lock laser bias current and laser modulation current Interfaces inside MLCM are e DAO SC Board for Slow Control RS485 bus by twisted pairs on LCM backplane e MLCM SWITCH board signals via coaxial SMB connectors e Optical I O via the EMC to the SCM DWDM MUX amp DEMUX e Backplane for supply Voltages 3 3V and 5 0V Associated Technical Notes e http www nikhef nl n05 antares ETR_Notes ETR2000 07s pdf e http www nikhef nl n05 antares ETR_Notes ETR2000 08s pdf Page 5 54 Next Up Previous Contents PBS 2 1 017 LCM DAQ SC board in LCM container Schematic diagramme of the LCM _DAQ SC board Master LEM only Slave LEM only used For development Fiat paid BIDIANT ie bre ne 4 ib ytes 64 Wb ytes i Module l haster LEM switch via LEM_OPTCONx board ITAG Ethernet i Ethernet E o Trarscewer gt 100Base T CPU bus Motorola MAPE 860P RPE Oa Processor The main functions of the LCM _DAQ SC board are e Readout of the data produced by the ARS e Transmission of the resulting data through the line network e Processing of slow control data and commands e Possible transmission of trigger data special packets issued with each trigger containing the trigger time and geographical origin e Extend
20. optical link between Master and Slave LCMs 1 Gb Ethernet DA Q SC optical link only MLCM L1 and L2 RoR Trigger optical links Clock optical link e Test points inside the DUT must also be provided monitoring electrical parameters of interest O Interfaces with DUT are e LCM TRIG board in order to test the L2 2 storey Trigger capability e LCM DAQ SC board for Master Slave communication test e LCM SWITCH board for Ethernet communications with Master LCM Technical Notes 3 LCM 18 06 A LCM Test Bench Page 5 25 Next Up Previous Contents PBS 2 1 001 LCM CRATE inside LCM container Schematic view of the inner rack Optical device Alimentation Description e The LCM CRATE inner rack is housing the electronics embarked on the lines e It consists of an axial structure that links all the cards and the backplane e Electric and optical cables penetrate the container and are plug in cards e This structure looks like a cylindrical cage placed inside the LCM container and fixed in the lower bottom end cap by a crown Dimensions technological features e Effective inner diameter 155 mm e Effective inner length 550 mm e The selected material for all part of the inner rack is aluminium 2017 Both inner and outer diameters must be chamfered Interfaces inside LCM are Page 5 26 16 boards 1 electrical connection board 1 optical connection device LCM power box for voltage 4 shieldings for OEM
21. the ARS event time stamp to 32 bits Page 5 55 Interfaces inside LCM are Clock board LCM CLOCK for clock signal reset enable DAQ and Slow Control over Modbus Protocol Trigger board LCM_TRIG for Readout Request L2 and L1 trigger signals Acoustic boards ACOUST_RX_ PREAMP ACOUST_RX DSP and ACOUST_RX_CPU for slow control over Modbus Protocol ARS motherboards ARS_MB for data readout and Slow control Both slow control and readout are carried by the DAQ FPGA over the ARS protocol LCM power box for voltage 3 3V and 1 8V LCM optical connection board LCM_OPTCON via the BIDIANT transceiver daughter board in order to connect optical signals to the main cable Page 5 56 Up Previous Contents PBS 2 1 018 MLCM SWITCH board in Master LCM container Schematic of the MLCM_ SWITCH board SERA I SGRAM memory memory Allayer AL121 Allayer AL1022 EEPROM memory Cooxid Cables b To 1 Gigabit Master LCM Laser Bord Transceiver EEPROM memory 8 Ports 10 100 fb its 4s Fast Ethernet Switch 2 Ports 1 Gbits s Gigabit Ethernet Switch 5 Fast Ethernet Transceivers LEM Backplane pista The main functions of the MLCM_SWITCH board are e Merge all Ethernet link 100 Mbits s coming from the LCM DAQ SC boards of a sector into a single Ethernet link connected to the DWDM laser board 1 Gbits s e Common link characteristics Ethernet protocol bi directional
22. wavelength through the same optical splitter back to all the LCMs as the Read Out Request RoR The trigger construction in the LCM trigger board LCM_TRIG is performed using a Field Programmable Gate Array FPGA A local oscillator 100 MHz is used to generate the delays and pulse widths for the various trigger signals with a precision of 10 ns All the necessary trigger requirements delays and pulse widths are definable by Slow Control using the UNIVI board The L1 signal from an upper storey is passed via a single optical fibre to a lower storey where it can also be used in the construction of the L2 trigger decision of that storey The L2 and RoR signals are bi directional on one optical fibre of the EMC The L2 RoR optical fibre is daisy chained the whole length of a string As the signals propagate down L2 or up RoR the EMC cable they pass through many other LCM_TRIG boards and are regenerated each time in a BIDITRIG daughter board Two optical fibres plus two spares in the Main Electro Optical Cable MEOC are used to test and monitor the offshore trigger They are connected to the JB_TRIG board of the JB Page 5 13 Schematic view of the offshore trigger Page 5 14 Next Previous Up Contents Hardware implementation The Electro Mechanical Cable The connections between the SCM and the LCM are made by the electro mechanical cable EMC It comprises 9 copper wires for power d
23. without Optical Modules Page 5 31 Interfaces inside LCM e POWER BOX 2W total 48 V 2mA 12 V 4mA 6 V 160 mA 5 V 160mA 5V 1mA 3 3 V 250 mA GND e LCM TRIG LO L00 and L1 L2 LVDS signals e LCM CLOCK ACLK WREF_CLK 5 MHz EN_ACK RES_TS LVDS signals LED PL LVDS signals e LCM _DAQ SC CLK_OUT 40 MHz READOUTI READOUTO CRMW LVDS signals ARS RESET SC_VALID SC_CLK CMOS LVTTL signals SC DATA bi directional CMOS out CMOS LVTTL in SC_OE determines direction of SC_data for I O buffer WCLK_ERROR open collector signal weakly pulled up to 5 volt on LCM_ARS board e COMPASS ARS COMPASS temp analogue Interfaces to OM e LED PL twisted pairs through back plane connector e PMT anode and dynode signals via screened twisted pairs there will be space at the far end of the backplane where the incoming OM_LCM link will be connected to a cable going to the ARS_MB connector type of connector MCX type of cable RG178 4 cables per ARS MB Associated Technical Notes 3 LCM 15 01 ARS motherboard Page 5 32 Next Up Previous Contents PBS 2 1 004 1 The Analogue Ring Sampler Chip on ARS motherboard Schematic of the ARS signal processing 4x1 GHz ANALOG SAMPLING To DAQ board PMT 2 x amp bit ADC Fal nl vp to 16 pokes BEER Dy node Anode DATA FORMATING ANALOG sr DIA AAA cen o HL Ubi TIME STAMP 3
24. 005 SCM DWDM Optical transceiver for DWDM function with 22 006 IA laser and receiver part ACOUST RXTX EM Positioning system 2 2 007 ACOUST RXTX PREAMP Positioning system 2 2 008 ACOUST RXTX DSP2 Positioning system 2 2 009 ACOUST RXTX DSP1 Positioning system 22 010 ACOUST_ CPU Positioning system 22011 ACOUST POW Positioning system 2 2 012 Optical connections between main cable and SCM_OPTCON SCM_CRATE 2 2 013 Page 5 59 M DWDM SCM DWDM_ Optical mux and demux to separate or mix wavelengths from shore or Master LCM MUX DEMUX Controls and measures tiltmeters humidity and temperature sensors id LCM COMPASS MB analog pipeline with ADC conversion from PMT signal identical to LCM ARS MB POWER BOX Converts 400V to needed voltages id LCM Daughter board plugged on other board for Lee slow control MODBUS interface 2 1 013 LCM DAQ SC Data and slow control board which sends and 21 017 receives Ethernet Protocol Page 5 60 Up Previous Contents SCM Test Bench SCM Test Bench synoptic 8CM_OPTCON M2414 5A cm ae is 5 Power Supply Console i onso I Test bench Display amp Printer Specifications The SCM Test Bench will have to certify the full functionality of the SCM It will do so by checking that e the SCM correctly executes the SC commands e the SCM correctly send
25. 3 pC Single photoelectron pulse amplitude at the ARS1 input Di dd 1 5 V 3 5 V Dynamic range of the anode dynodel and dynode2 Waveform mode inputs Page 5 34 Daclk 2V 3 5 V Dynamic range of the Ac k input Gw 0 9 1 0 Waveform mode gain Lw 5 2 Integral linearity of the Waveform mode Dq 10 PE 13 PE Dynamic range of the anode input for charge measurement SPE mode GspE 7 3 Charge integrator transfer function mV pC LspE 5 2 Integral linearity of the integrator Nadd 5mVRMS 3mVRMS Total noise at the Waveform mode inputs Nq 0 5 pC Total noise at the SPE mode input RMS BW 120MHz 0 140 MHz Bandwidth of the Waveform mode inputs 3dB Ci 5 pF 40 pF Analogue input capacitance The maximum value is the worst case operating mode of the ARSI Ri 250 500 Expected resistance at the analogue inputs Th venin equivalent resistance Faclk 10MHz 20 MHz Aclk clock frequency Notice this frequency must be Fs 64 when Aclk is used as the reference sampling clock 15 MHz 25 MHz 20 MHz Readout clock frequency This clock divided by two is used as the ADC clock Napc 8 bits Dynamic range of the ADC Neff 7 a Effective number of ADC bits for a LSB of 6 mV 50 mV ns Stvc Eo 20 mV ns ia 120 mV ns TVC conversion linear slope Live 5 Integral linearity of the TVC Nrvec EEN ps Equivalent noise of the TVC m DStvc 4 3 ps mV TVC drift as a function of power supply 5 V DT tvc
26. 50 Hz frequency Reference technical note e 3 LCM 20 04 A Electronics qualification and AST scenario Page 5 20 Next Previous Up Contents Test Benches and test scenarios In parallel with the electronics development the development of the associated test benches and test scenarios is necessary The tests performed during fabrication and integration can be divided into three main types e Test scenarios for each board during the prototype phase every designer provides a test procedure which describes the test set up and the measurements along with the necessary software and hardware An example of this test scenario for the clock distribution function can be found in the Web link 3 LCM 18 02 A Clock Distribution Prototypes Tests e Manufacturer acceptation tests each board realised by the manufacturer or a laboratory must pass a test scenario before acceptation These tests verify each function of the board and incorporate burning tests AST scenario The results of these acceptation tests are directly entered on the Web pages one per electronics board or object in order that the results can be incorporated in the general database e Main objects integration tests After the acceptation test of each board the integration starts with insertion of boards inside the electronics crates After integration of all these boards the functionality of the total electronics crate is checked in a test bench
27. DWDM Board Single MLCM DWDM Board Channel Sea Side Board Modbus Br ReadOnly zil mopBus x i Teo cntL De i pono i DWDM DRIV g BiDirectional VO x cd ween eee ew eee Pa i i j x GbE Zf Sigabiteimeret piter osom Optical PECL 3 at 1 25Gbits _ i Connections i EGR s v H lia je oe i 7 y 0 6 3 3V 3 _ Power i 5 0V ail Conditioner peewee n A The MLCM DWDM Board converts the Gigabit ethernet signals from the LCM_ SWITCH Board into the optical signals of a Dense Wavelength Division Multiplexing DWDM system and vise versa Important parts on this board are the DWDM Laser and the Pin Diode Receiver The DWDM Laser is a Distributed Feedback type with very narrow spectral width operating in the 1550nm range at 1 25 Gb s The system is based on the ITU grid standards for DWDM applications with 400 GHz channel spacing The specific optical ITU channel wavelength A is obtained by very accurate temperature control with a Thermo Electric Cooler TEC Temperature stabilisation of lt 0 1 C is needed for 0 1 nm wavelength locking The Pin Diode Receiver with Trans Impedance Amplifier TIA and Limiting Amplifier LIM converts the optical signal A back to an electrical signal The main functions of MLCM DWDM Board are e Electro optical conversion and vise versa of Gigabit Ethernet 1000BASE CX signals e DWDM laser temperature control to lt 0 1 C e Slow control parameters read
28. LCM CRATE 21 012 all UNIVI Daughter board plugged on other board for slow ian control MODBUS interface BIDIANT Daughter optical transceiver board for Ethernet tasca and Clock signals BIDITRIG Daughter optical transceiver board for trigger 1 all signals DWDM transceiver board with laser receiver MLCM DWDM and DWDM filter dl MLCM only LCM_DAO SC Data and slow control board which sends and 21 017 all receives Ethernet Protocol MLCM SWITCH Gbit switch l IMLCM only List of references all 2 1 014 all http antares in2p3 fr internal deci km2 tableaux LCM and all references in that table in particular technical note 3 LCM 20 01 A describing the LCM internal organisation Page 5 23 Up Previous Contents MasterLCM SlaveLCM Test Bench Schematic view of the LCM Test Bench Physical Signal Emulation Digia Signal Deneralon The Test Bench consists of a main computer connected with a set of instruments and devices Each single board within the Design Under Test DUT is assumed to be already tested Specifications e The aim of the Test Bench is to test the overall functionality of SLCM MLCM series production e The results of the tests must be logged in order to ensure quality documents e All the DUT communication links must be tested These are Page 5 24 Physical signals from OMs LED ball and hydrophones 100 Mb Ethernet DAQ SC
29. LCM which combines the functionality of a LCM with that of network node in the offshore DAQ system Within each of these containers a number of electronics cards provide the desired functionality which are described in the individual object PBS pages The electronics cards are inserted in a crate and the power and signals are passed between boards via the backplane or via twisted pair wires Page 5 2 The connection between the various containers are provided by electro optical cables the power being transmitted via electrical wires and the signals via optical fibres The most relevant technical notes are listed at the end of each section Page 5 3 Next Previous Up Contents DAQ and Slow control functions The data acquisition and slow control functions are described in chapter 4 The electronics implementation is described here The readout chain is summarised in the figure below Functional schematic of the DAQ electronics The analog output signal of each PMT is processed by two Analogue Ring Sampler ARS chips located on the ARS motherboard ARS_MB The ARS produces a time stamped digitisation of the PMT signal Two digitisation modes are possible Single Photo Electron SPE and WaveForm WF A SPE event contains only the total charge of the PMT signal whereas the WF contains also a waveform sampling of the PMT output When a L1 or L2 trigger for a definition cf Chapter 4 on offsh
30. NTV board is based on a RS485 driver chip and uses the MODBUS protocol It is described in Page 5 7 detail in the technical notes 3 LCM 08 01 A and 3 LCM 08 02 A The instruments which have a RS232 link require a dedicated bridge Technical notes are available for more details e 3 LCM 15 01A ARS motherboard description 3 LCM 05 01 A LCM_DAQ SC board description 3 LCM 13 01 A Design specifications for the ANTARES DAQ DWDM Network Part I 3 LCM 13 02 A Design specifications for the ANTARES DAQ DWDM Network Part II 3 LCM 20 01 A LCM internal organisation ANTARES Elec 2000 6 ARS1 Analogue Ring Sampler amp ARS CONV Users Manual Version 1 9 3 LCM 08 01 A UNIVI board user s manual 3 LCM 08 02 A MODBUS protocol reference guide Page 5 8 Next Previous Up Contents Power distribution The distribution of power from the shore up to the level of the SPM is described in the Power section in chapter 7 In this section its implementation inside the SPM and the LCM are discussed A summary of the power distribution is displayed in the figure below LUM optic al modules section 1 etc g dc Shore Pressure veloci se EP Acoustic ae a4 doo SPM lev JE Ga cable type ww power voltage 97 number of mires Schematic view of the Power distribution The Junction Box provides each String Power Module SPM with 1000 Vac The SPM converts this voltage value
31. X in SCM container SCM DWDM MUX amp DEMUX schematic SCM DWDM Mux amp DeMux Ch0 to Ch5 cho 7 lt 5 MLCM DWDMs 3 7 Ch 1 a A ha T All passive NL Luo DVWDMs ie gt 2 using thinfilm Ch3 ke o o interference filters gt Ayio 6 gt 5 Ch 4 3 chs fr Ch 6 S SCM DWDM che gt A PP The SCM DWDM MUX amp DEMUX is a passive optical circuit inside the SCM container Optical signals to and from the MLCMs are split combined with Dense Wavelength Division Multiplexers and Demultiplexers The optical signals A 0 6 6 wavelengths from the MLCMs for DAQ and 1 for SCM SC are multiplexed with a DWDM Multiplexer into a single mono mode fiber The optical signals from the JB Shore Station Ay 0 6 are demultiplexed with a DWDM Demultiplexer into 7 output fibers Two sets of 6 wavelengths are used for DAQ Gigabit Ethernet and a 7 set is used for SCM SC Fast 100Mb Ethernet The DWDM Multiplexer and DWDM Demultiplexer use thin film interference filters the optical path is epoxy free The ITU wavelength grid used for these DWDMs is 400 GHz 3 2 nm The DWDM channels have a minimum bandwidth of 0 8 nm The main functions of SCM DWDM MUX amp DEMUX are e Multiplexing and demultiplexing of optical signals Optical signals are ITU defined channel wavelengths in the 1550 nm band on a 400 GHz grid All optical parts are passive Page 5 75 Interfaces inside SCM are
32. agram The main specifications of the ON_PCIO board are e Provide a high speed data transfer for the control word sending from users to the OFF SHORE modules Word lus Typical e Located in the PC_CLOCK control e Protocol OUTPUT 16 bits INPUT 8 bits with Handshaking mode and 8 control lines e Driver Software NI DAQ for LABVIEW Labwindows CVI Interfaces to e Connected to ON CLOCK module by large cable Data lines 32 Control lines 8 e Remote computers through PC_CLOCK by Ethernet to provide remote control word sending Page 5 99 List of References e 3 LCM 03 01 Numerical clock distribution for ANTARES Proposal e http www ni com Page 5 100
33. al connection device Page 5 80 e LCM power box for voltage e 4 shielding boards for OEM and thermal cooling Associated Technical drawings at http antares in2p3 fr internal deci km2 tableaux LCM htm e 3 LCM 02 01 Integration LCM e 3 LCM 02 03 shielding e 3 LCM 02 04 crown 1 e 3 LCM 02 05 crown 2 e 3 LCM 02 06 Slides 15 02 2001 M Jaquet P Lagier Page 5 81 Contents List of subsystems PBS list Mechanics Electronics Electrical Power The Junction Box list of objects The Junction Box JB is the heart of the ANTARES detector It receives Power from the onshore Power Hut via the Main Electro Optical Cable MEOC and distributes it to the strings via the Interconnecting Links IL Data Clock Trigger and Control signals also transit via the JB through the same cables Components are separated into mechanics electronics and power aspects and each of these aspects is described separately in the corresponding chapter Since it is is the first detector system we build to be installed in the sea it has the first PBS number The associated PBS numbering has been fixed by the collaboration organisational structure starting with 1 for mechanics 2 for electronics and 6 for power A list of the components can be found below e PBS 1 1 Junction Box mechanics part 2 Ti hemispheres and 1 PBS1 1 2 001 JB Vessel cylind spacer separates the transformer to Epon we JO Diaphragm the electronic volumes transm
34. ator the integrator and the TVC and Time Stamp functions are freed for the next pulse without waiting for the digitisation of the pulses in the pipeline Page 5 33 Waveform data is stored outside the pipeline The GHz waveform sampler has four synchronous channels sampling the reference clock the anode signal an attenuated anode signal and a dynode signal When a WF hit is found the waveform sampling continues until 128 samples have been stored for each of the four fast sampling channels then the sampler is blocked until these data are digitised or discarded If a WF event arrives when the WF sampler is occupied the pulse will be treated as a SPE pulse with a flag indicating that the waveform sampler was not available The Time Stamp is used to determine if a pulse is in a trigger readout window If a readout request is received the memory cell is read out the charge and the TVC are each converted to 8 bit digital values and the digital information for the event with a header added is formatted for transmission to shore For WF events the 128 clock samples and the corresponding 128 anode pulse samples are converted to digital form and added to the event packet for transmission For very large pulses all four waveform channels are digitised 128 samples each for the clock the anode the attenuated anode and the dynode signals If no readout request is received within a predefined lapse of time the memory cell and the fast sampling cel
35. bution see Technical Note 3 LCM 13 01 A The worst case is that of the DAQ distribution for a signal traversing the whole length of a string This situation is summarised in the following table Optical losses of the DAQ distribution Prono top to DWDM mux 30 OPTOCLIP connectors e 57 penetrators 0 01dB penetrator 0 6 dB EMC 350 m SMF28 0 1 dB DWDM MUX 3 6dB max ie DWDM to fibre 0 2 dB splice in SCM 0 1 dB wetmateable jumper connector 0 75 dB interlink cable from SCM to JB 500m 0 1 dB wetmateable jumper connector 0 75 dB internal JB splice 2 0 0 1 dB JB connector to MEOC S 1 5 dB ma Splice MEOC to shore fibre 2 0 0 1 dB shore fibre 5 km SMF28 1 0 dB splice shore fibre to broadband monitor splitter 1 0 2 dB splice broadband monitor splitter to DWDM 0 2 dB DWDM Demux 3 6dB max splice DWDM Demux to Detector 0 2 dB Avalanche Photo Diode 0 3 dB Total optical loss of passive network 26 dB Assuming a laser output power of 6 dBm and an avalanche phtodiode receiver with a typical sensitivity of 30 dBm this implies a power margin of 10 dB This margin is sufficient to compensate for normal ageing effects during the lifetime of the experiment In order to reduce optical losses and increase reliability fusion splicing of the optical fibres will be used wherever possible The electronics implementation of the Slow Control is ensured by the UNIV daughter board The U
36. ch optical module with 12 bits DAC with a 0 to 4 volts range 3 voltage commands e Measures the low voltage command value at the output of the DAC 3 voltage values e All these controls and measurements are performed through 2 UNIV1 functions with two different MODBUS addresses Interfaces inside LCM are Page 5 29 The standard interface is a 24 pins connector all signals come from the backplane via the LCM_ BACK board List of references e 3LCM 07 O1A technical note of COMPASS MB e PBS 5 6 Humidity sensor e PBS 5 2 Tilt meter and compass daughter board Page 5 30 Next Up Previous Contents PBS 2 1 004 ARS MB board in LCM MLCM container Schematic of the ARS motherboard Slow Control see n a Temp From PMT Anode Readout0 From PMT Dynode ir Readout1 Crmw LO Token passing L1 L2 ROR Aclk Wref_ clk e gt x Wclk_error Res_ts REL En_ack LED_PL Reset LOO CLK_Led_pulse The main functions of the ARS_MB board are e Interface of the 3 ARS chips to the LCM DAQ SC board ARS 0 and ARS1 1 are used for signal processing ARS 2 is used to generate of supplementary anode impulse trigger signal L00 with its separate slow control set trigger level th2 e Passing of the token between ARS1 0 and ARS1 1 e Generation of LED pulser pulse and peak value reference voltage 0 24 V e Use of attenuated LED pulser pulse for re injection in the anode for LCM tests
37. cting Link IL the interconnecting cable of the IL has 2 copper wires and 4 optical fibres The copper wires are used to transfer power from the JB to the SPM The optical fibres transmit signals between the JB and the SCM two fibres are used for the DAQ one for the clock and one fibre transmits both the L2 trigger and the readout request The Main Electro Optical Cable The JB is connected to shore by the Main Electro Optical Cable MEOC The MEOC has 48 fibres and one copper sheath The sheath is used to distribute the power from the power hut the return current flows through the sea water For the DAQ the JB connects each pair of optical fibres of a string to a corresponding pair of optical fibres in the MEOC A single optical fibre plus a spare is used for the distribution of the clock signal In addition 2 optical fibres plus 2 spares are Page 5 15 used to test and monitor the off shore trigger system The number of fibres in the MEOC is sufficient to allow for a larger number of detector strings than presently foreseen Containers The electronics boards are mounted in pressure resistant titanium containers A mechanical description of the containers is given in chapter 2 on mechanics Inside these containers the electronics boards are mounted on a common backplane The boards are mounted perpendicular to the backplane and can be exchanged independently All boards have the same dimensions The following figure shows the crate
38. ctl 102x33x95 out sensor60x60x60 e clock ROR 320x150x126 e control module 320x150x126 e low volt 256x131x100 e EOC terminall 10x170x150 e electrode Terminal 10x170x50 e current meas 250x200x65 e relay 200x135x63 e 2 relays 130x90x60 Dimensions technological features e Support interface diameter 800 mm e Total height 373 mm Page 5 84 Technical design 3 BJO 04 01 A Ensemble interne JB Page 5 85 Next Up Previous Contents PBS 2 4 002 JB SPLIT board in Junction Box container Schematic diagramme of the JB SPLIT board Optical Passive Splitter 2 input to 16 outputs The main specifications of the JB_SPLIT board are e Distribute to all lines of the detector optical clock signal with a division splitting function from 2 fibres to 16 outputs fibres e Two optical fibres come from shore in order to have a redundancy capability for better reliability e The reference of this optical component from E TEK company is TWSCBEO00PH215 we can find more details about this component in E TEK company web page www e tek com Interfaces inside JB are e Inputs and outputs optical fibres are connected to optical fibres which come from MEOC and each JB to the Interconnecting links by an optical connector from Deutsch company OPTOCLIP II standard e No electrical power needs passive component Page 5 86 Picture of this component inserted in crate for tests and measurem
39. d through the rear connector on SCM_BACK 200 Mbps Page 5 67 Technical Notes associated on WEB page e 3 SCM 02 01 B SCM internal organisation e 3 LCM 03 01 Numerical clock distribution for ANTARES Proposal e 3 LCM 03 02 Clock Distribution ON SHORE for ANTARES Proposal e 3 LCM 08 04 BIDIANT user s manual Page 5 68 Next Up Previous Contents PBS2 2 004 SCM_ REP board in SCM container Schematic of the SCM_REP board UNIVI function With slow control with MODBUS protocol The main specifications of the SCM_REP board are e Electrical to optical conversion between SCM_WDM board and each sector for clock distribution function e Electrical to optical conversion through the BIDIANT daughter boards plugged on SCM_REP board e The UNIVI function allows monitoring of the Vbias and Vmonitor voltage of each BIDIANT daugther boards and one temperature sensor e Inside each SCM container we have 2 SCM_REP boards in order to drive clock signals for the 6 sectors of a line Interfaces inside SCM are e Clock electrical signal goes from SCM WDM to SCM CLOCK and SCM_REP first and SCM_REP second in serial topology via a PECL twisted pair e DAQ board for clock signal reset enable and slow_control RS485 bus by twisted pairs on backplane e SCM_WDM board with twisted pairs PECL clock signal on backplane SCM_ BACK e POWER BOX for voltage 5V and 3 3V by backplane Page
40. e www e tek com e Power needs for this JB TRIG board is produced internally by a DC DC converter with standard 24 Volts input produced by the power box in the Junction Box Page 5 89 Up Previous Contents PBS2 5 On shore Clock objects The clock is produced on shore and sent to all the storeys The function is described in the relevant Electronics section about the clock distribution Object in Onshore CLOCK D er PBS escription container number ON_CRATEI Electronics crate 2 5 001 ON GPS GPS receiver producing reference signal for 25 002 sua clock distribution ON_CLOCK Coding decoding orders for clock 25 003 distribution ON _WDM Optical transceiver for clock distribution 2 5 004 ON_SYNCPCI 2 5 005 ON_PCIO digital interface for ON CLOCK board 2 5 006 Page 5 90 Next Up Previous Contents PBS 2 5 001 ON CRATE1 ON SHORE ON_SHORE schematic diagramme RIO Fa comol mta Bond wreck oo comm IRIG B Synchronisation Ethemet NTP protocol to other enremnitere The ON_CRATEI contains several boards in Europe format 100X160 e ON GPS module with GPS Global Positioning System REF HP 585404 including frequency doubler REF TLC2932 EVM e ON CLOCK module for interfacing the Clock Control Computer to the ON WDM module e ON _ WDM Wavelength Division Multiplexing optical module connected to the Junction box JB_SPLIT1 To Clock Control Computer e ON PCIO isa
41. e preferred solution is that adopted for the LCM container in which copper fingers connect to the walls of the SPM container Further details can be found in the internal note on SPM The components used satisfy military specifications the expected MTBF is of the order of 50 years Specifications Input Voltage to activate the local 680 1000 V slow control Voltage to deliver 6 output 720 1000V frequency range 48 55 Hz power factor 0 97 Cosphi 0 95 Nominal power 1300 WO Output 6 380 Vdc voltage variations 5 ripple 10 tt nominal power I80Watts maximum power 200 Watts overload protection fuse Output 1 48 Vdc nominal power 50 Watts SSS maximum power 60 Wats SSS overload protection fuse Monitoring 1 ac input voltage 6 de output voltages 6 dc output currents 1 ac leakage current to container 0 10mA 1 dc leakage current to container 0 10mA Page 5 78 Interfaces e JB via an Interconnecting Link cable e SCM Objects in SPM SPM CONTAINER PBS Description P number contains all the items below 1 2 007 support of boards and backplane 2 3 001 distributes signals between boards in SPM_CRATE aoe SPM_CRATE SPMBACKI xs SPM_CONNECTI connections inside SPM 2 3 003 BH SPM_CONNECT2 SPM CONTI SPM _CONT2 SPM _CONT3 SPM _CONT4 connections inside SPM 2 3 004 controls power distribut
42. ed Time Interfaces e The 20 MHz square signal is provided by a frequency doubler TLC2932 EVM from the 10 MHz GPS clock This reference clock is connected to the input clock ON CLOCK board e The 1 PPS output provides to the PC_CLOCK a synchronized signal in coincidence to the UTC e A RS232 interface allows keeping date time and GPS monitoring by using SCPI protocol List of References e 3 LCM 03 01 Numerical clock distribution for ANTARES Proposal e 3 LCM 03 02 Clock Distribution ON_SHORE for ANTARES Proposal Page 5 93 Next Up Previous Contents PBS 2 5 003 ON CLOCK onshore Schematic view of ON CLOCK board Back Panel Front Panel Reset GPS Data Word Control Word Input output i Slow l Control RS 232 ON_CRATE Control i The main specifications of the ON CLOCK module are e Shape and send control words from PC_CLOCK to the WDM optical module at 200 Mbps speed e Inthe receive mode shape the status frame from the offshore modules e Provide START and STOP signals corresponding to the sending and receiving frames for the propagation time measurement e Provide a control signal for the time stamp function Interfaces to e ON _WDM connected by twisted pairs in PECL logic for the send mode and receive mode e ON PCIO PC board connected it by large cable 32 bits for the sending control words e TDC Time to Digital Convert from start and stop output signal
43. ed with beryllium copper finger strips The power module is based upon a VICOR second generation DC to DC converter capable of operating with an input voltage range of 290 to 450 V The first converter generates an internal supply of 48 V which is used as the power input to all other converters within the module The SCM Power Supply is a copy of the LCM POWER _ BOX although less voltages are used in the SCM Output Specifications OUTPUT VOLTAGE in Volts MAXIMUM POWER in watts EricieNcy in EET TT 3 0 Os o switched outputs per channel ooa 20 Coa 5 5 15 70 5 0 50 72 3 3 50 72 2 5 8 0 64 1 8 see below 44 General remarks a All outputs with the exception of the 1 8 volt supply are fully isolated and there is no common connection within the power unit The 1 8 volt supply is derived from the 2 5 volt output and therefore the two supplies share the total power 8 watts b The maximum power quoted in the above table does not imply that this level of power is available for general use It is the maximum capability of the individual converters under ideal conditions The available power will depend upon load distribution efficiency and most importantly the thermal characteristics of the LCM c The efficiency quoted is the overall value from the 400 volt input to the particular output the efficiency is not constant with load and the above figures are only representative Page 5 43 d Final value
44. ent Technical Notes e 3 LCM 03 01 Numerical clock distribution for ANTARES Proposal e 3 LCM 18 02 Clock distribution prototypes tests Page 5 87 Next Up Previous Contents PBS2 4 003 JB TRIG board JB container Schematic of the JB TRIG transceiver board 2 to 16 Optical Splitter The main specifications of the JB TRIG transceiver board are Concentrate all L2 signals from each string of the detector and return the RoR signal to all lines This OR function is built with an optical splitter with 16 channels inputs and 2 channels outputs 2 for redundancy The optical OR signal between all L2 signals is converted to an electrical signal which is returned after an O E O conversion in a BIDITRIG board A second BIDITRIG board can be used if the first fails A spare channel optical channel is sent to shore in order to monitor the RoR signals of the detector Two fibres are reserved inside the MEOC for this function A pair of optical fibres are reserved to allowing sending of a fake L2 signal from shore Page 5 88 Interfaces inside LCM and JB are e The BIDITRIG daughter board has standard TTL input and output with 5V power voltage The BIDITRIG incorporates standard BIDI component with pigtail and standard OPTOCLIP II connector on optical fibre e The reference of this optical splitter 2 to 16 from E TEK company is TWSCBE00PH215 more details about this component can be found in E TEK company web pag
45. ers to be defined Associated Technical Notes 3 SCM 18 01 A Proposal for a SCM Test Bench to be released soon Page 5 62 Next Up Previous Contents PBS2 2 001 SCM CRATE in SCM container Schematic view of the Inner rack Optical device Alimentation shielding The design of the SCM_CRATE inner rack is e The SCM_CRATE inner rack houses the string control module offshore electronics e It consists of an axial structure that links all the cards and the backplane e Electric and optical cables penetrate the container and are plug in cards e This structure looks like a cylindrical cage placed inside the SCM container and fixed in the lower bottom end cap by a crown Dimensions technological features e Effective inner diameter 155 mm e Effective inner length 550 mm e The selected material for all part of the inner rack is aluminium 2017 Both inner and outer diameters must be chamfered Page 5 63 Interfaces inside SCM are 16 boards 1 electrical connection board o e optical connection device e SCM power box for voltage 4 shielding for OEM and thermal conduction Associated Technical designs e 3 LCM 02 01 Integration LCM e 3 LCM 02 03 shielding 3 LCM 02 04 crown 1 3 LCM 02 05 crown 2 e 3 LCM 02 06 Slides Page 5 64 Next Up Previous Contents PBS 2 2 002 SCM BACK board in SCM container Schematic diagramme of the SCM_BACK board 7 IE x allellellellells oO
46. fast interface PC board for sending address commands to ON CLOCK module e ON SYNCPC connected to PPS and Time Stamp from ON_CLOCK outputs Synchronize function Page 5 91 e Coml using a Slow Control MODBUS protocol for ON_CRATEI Monitoring function e Com2 using SCPI protocol for ON_GPS monitoring function To TDC Time to digital convert e Start stop Outputs TTL pulse for propagation time measurement between the onshore station and all offshore modules Technical Notes e 3 LCM 03 01 Numerical clock distribution for ANTARES Proposal e 3 LCM 03 02 Clock Distribution ON SHORE for ANTARES Proposal Page 5 92 Next Up Previous Contents PBS 2 5 002 ON_GPS ON SHORE ON_GPS Global Positioning System The HP 58540A GPS time and frequency reference receiver features Eight channel parallel tracking GPS engine C A Code L1 Carrier GPS T RAIM satellite error detection 24 Vde power operation SCPI Command set lt 1x10 frequency accuracy when locked to GPS lt 7x10 per day average frequency change when not locked to GPS 5 110 ns time accuracy with respect to UTC USNO MC Compatible with HP 58531A GPS timing receiver analysis and control software The main specifications of the ON_GPS module are e Provide a high accuracy clock 20 MHz 50ps jitter to the offshore electronic boards Provide the absolute date and time in coincidence to the UTC Universal Coordinat
47. fixed to the upper flange of the LCM container Interfaces inside LCM are e Maximum needs for optical connectors 27 30 OPTOCLIP II connectors are available e Maximum needs for optical fibers with LCM CRATE boards 9 for Master LCM and 2 Page 5 46 wires for 400V OPTCON prototype board picture Page 5 47 Next Up Previous Contents PBS 2 1 013 UNIVI board in LCM SCM JB containers Schematic diagramme of the UNIV1 board PIL7C756 CPU 12 ADCs 10 bits Power on DAC 12bits Reset DAC 12 bits R3485 bus pn i ee a fe et RS485 TTL lt P 16 I O logic Timer 16 bits A The main functions of UNIVI board are e Main hardware interface between the DAQ SC board and the setting and reading of the Slow Control parameters of each board inserted in the containers MODBUS protocol in micro controller with RTU format 10 12 Analog to Digital converters with 10 bits of precision o o e 2 Digital to Analog converters with 12 bits of precision e 16 digital pin selectable individual y in IN or OUT state o 1 timer with 16 bit range second serial bus with buffer transmission and reception Interfaces inside LCM SCM and JB are e The UNIVI board is a daughter board which drives all slow control functions for its main board Hardware adaptation are very small or not necessary Page 5 48 LALELE
48. he UNIV1 board Page 5 50 e Inputs and Outputs are differential in LVPECL format e Signal detection permits to detect optical power at the receiver Interfaces inside LCM e The BIDIANT transceivers are standard 2x9 pinout with additional pin for PIN diode bias voltage Between 3 to 10 Volts max Optical fibres are mounted with OPTOCLIP II connectors Picture of the BIDIANT board Page 5 51 Next Up Previous Contents PBS 2 1 015 BIDITRIG board in LCM container and JB containers Schematic diagramme of the BIDITRIG transceiver board Laser Driver Amplifier Vref Threshold Signal Comparator Signal Detect This board is a daughter board which is plugged on the LCM_ TRIG and JB_TRIG boards An example of a BIDITRIG board implementation can be seen with the picture of the BIDIANT board the external aspect is similar The main functions of the BIDITRIG transceiver board is the electrical optical conversion between TTL pulse of trigger signals L2 and RoR and monomode optical fibres inside the line cable Interfaces inside LCM and JB are e The BIDITRIG daughter board has standard TTL input and output Power needed 5 V e Like the BIDIANT daughter board the BIDITRIG incorporates standard BIDI component with pigtail and standard OPTOCLIP II connector on the optical fibres Page 5 52 Next Up Previous Contents PBS 2 1 016 MLCM DWDM Board in MLCM container Block diagramme of the MLCM
49. ion 2 3 005 controls power distribution 2 3 006 controls power distribution 2 3 007 controls power distribution 2 3 008 SPM LV Produces low voltage 23 009 SPM _ TRANSI transformer for HV AC 2 3 010 SPM FILTI electrical filter for power conversion 2 3 011 SPM_ REGUL Voltage regulator 2 3 012 SPM_DC DC DC DC conversion 2 3 013 SPM_FILT2 Electrical filter on output 2 3 014 SPM_HEAT1 Heat dissipator 2 3 015 Daughter board plugged on other board for UNINE slow control MODBUS interface ALOL List of References e Power section in Chapter 7 e SPM technical note to be released soon Page 5 79 PBS 2 3 001 SPM CRATE in SPM container Scheme of the Inner rack Optical device Alimentation Cards shielding SPM_CRATE is e The SPM_CRATE inner rack houses the String Power Module electronics e It consists of an axial structure that links all the cards and the backplane e Electric and optical cables penetrate the container and connect to the relevant cards e This structure looks like a cylindrical cage placed inside the SPM container and is fixed at the lower lid cap by a crown Dimensions technological features e Effective inner diameter 155 mm e Effective inner length 550 mm e The selected material for all part of the inner rack is aluminium 2017 Both inner and outer diameters must be chamfered Interfaces inside SPM are e 16 boards e electrical connection board e optic
50. ised in the line structure page or PBS Six main objects are relevant for the electronics discussion e The Local Control Modules LCM PBS2 1 contain the electronics for the readout of three Optical Modules OM and the various instruments located on a storey They also contain the electronics of the offshore trigger logic and the local power supply One LCM called Master Local Control Module MLCM is present in every sector and multiplexes in addtion the signal information from five storeys onto one optical fibre at a wavelength unique to that Storey e The String Power Module SPM PBS2 3 contains the power supply for the string e The String Control Module SCM PBS2 2 contains the electronics for the readout and control of the SPM and the instruments located at the bottom of the string e The Junction Box JB PBS2 4 is the central point of the detector it has connections to all detector strings and to shore It contains the power supply for the whole detector and the electronics for conversion of the trigger signals into a global readout request signal It also distributes the clock signals to all LCMs e The electronics for the generation of the master clock PBS2 5 is located at the shore station The main power supply is also located onshore in the power hut Each detector string consists of 1 SPM 1 SCM and 30 LCMs The LCMs inside a string are organised in 6 sectors each sector consists of 5 LCMs Each sector has a master
51. istribution and 21 optical fibres for data transmission For the DAQ each MLCM is connected to the SCM by one pair of optical fibres Each LCM in a sector is connected to its MLCM by a single bidirectional fibre For the distribution of the clock signal the bottom LCM of a sector is connected to the SCM by a single fibre the same fibre is used to daisy chain the signal through the sector The L2 trigger and readout request signals are daisy chained through the entire string on a single bidirectional fibre One additional fibre is used to transmit the L1 trigger between storeys The total number of fibres is thus 2 6 1 dag sc 6 clock 2 trigger 21 A schematic of the fibre connections is shown below and can be seen better by clicking here on on the icon The electrical power distribution in the EMC has a similar organisation The bottom LCM of each sector is connected to the SPM by a single copper wire The same wire is used to daisy chain the power distribution to the other LCMs of the same sector The return current of two sectors is combined into one copper wire Thus a total of 9 wires is is needed for the electrical power distribution on the string The connection between the SPM and the SCM passes through a sleeve joining the two modules This allows the power in the SPM to be separated from the optical fibres in the SCM The Interconnecting Link Each detector string is connect to the JB by an Interconne
52. it power and PBS1 1 2 003 Feed throughs diagnostic 7 holds penetrator for PES het el connection to EO cable PBS1 1 2 005 JB O ring PBS1 1 2 006 Balancing device PBS8 1 5 BESSER gives the si of the ame e PBS 2 4 Junction Box clock distribution and trigger construction PBS2 4 001 JB_ELECBOX contains electronics boards PBS2 4 002 JB_SPLIT1 passive splitters for clock distribution PBS2 4 003 JB_TRIGI RoR signal construction Daughter board plugged on other board for RESO UNIVI slow control MODBUS interface e PBS6 4 Junction Box Power part PBS6 4 1 Penetrators and bulkhead receptacles Page 5 82 PBS6 4 3 Power Remote diagnostic i PBS6 4 5 Cabling and Connections PBS6 4 6 Sensors PBS6 4 7 Remote Control links to TDR e Junction Box Mechanical Description e Electronics Power Distribution e Electrical Power system Page 5 83 Next Up Previous Contents PBS2 4 001 JB ELECBOX Schematic views of the JB ELECBOX Electronic box De Fixing gt jj device support Circular interface frame Requirements The main mechanical function is to support all the electronics box An assembly has been performed e e e All presently defined parts fit in e Connection and accessibility tests to be done e Assembly on JB container tests will be done in CPPM Listing components in electronics box e 16 out switch 105x116x130 e 7 out
53. lave 1 with acoustic cards slave 2 with LED Beacon e slave 3 with only the basic boards A map of the location of the instruments and LCM types along line 1 can be found here They will vary from line to line Each board inside the LCM is tested in a dedicated test bench Examples can be found in the technical notes A test bench of ARS SPE or Preliminary test of clock distribution The assembly of the LCM boards and the systematic tests of each LCM is described in the technical note 3 LCM 18 06 A and summarised in Integrated LCM test benches List of components inside the LCM LCM Objects in LCM Ci ca aL Description PBS number LCM CRATE B support of boards and backplane Page 5 22 2 1 002 all distributes signals between boards in LCM BACK LCM _ CRATE COMPASS MB measures positions with compass and tiltmeters controls PMT HV 2 1 003 all ARS MB Motherboard with 3 ARS1 chips 2 1 004 all ARSI analog pipeline with ADC conversion of PMT 2 1 004 1 all n signal Concentrates 4 optical transceivers from each Mom BIDICON LCM slave DAO channel 2 1 005 MLM only LCM TRIG Receives trigger from ARS boards and 2 1 006 all SA constructs trigger function receives optical clock distribution signal and LEM CLOCK distributes inside LCM crate e007 all POWER BOX Converts 400V to needed voltages l Optical and electrical connections between main LCM _OPTCON cable and
54. ls in the case of a WF event are erased and made available for subsequent pulses The main functions of the ARS chip are e Measurement of time of arrival and integrated charge of Single Photon Electron SPE PMT signals if confirmed by the trigger signals L1 or L2 e Pulse shape discrimination PSD to separate SPE events from NON SPE waveform events e Digitisation of waveform events measuring PMT anode attenuated anode and dynode signals as well as the sinusoidal time reference clock band filtered ACLK clock signal e Generation of LO signal when PMT anode signal crosses threshold th1 e Generation of Counting Rate Monitor Warning CRMW signal set to go off at a determined PMT pulse rate e Generation of WCLK_ERROR if the waveform digitizer Delay Locked loop DLL is unlocked ARS Specifications Parameter Min spec Max spec rs value Characteristics Vsup 4 75 V 5 25 V Operating power supplies range D 25 mV 25 mV Power supplies drift other than ADC sup 1 mV ADC power supply drift vdd_adc cna 15 C o Operating temperature 3 C Temperature drift Psup 250 mW n 200 mW Power consumption of the ARSI 5 V supplies 300 MHz 1 1GHz Waveform mode sampling frequency Number of Waveform mode channels anode two intermediate gain channels dynodes and Aclk clock Number of Waveform mode samples per ARSI NARS Number of ARS1 chips in the token ring VspE 60 mV 1
55. n proposal e 3 LCM 03 02 A Clock board interface e 3 LCM 18 02 A Clock distribution prototype tests e 3 LCM 20 O1 A BIDIANT user manual Page 5 12 Next Previous Up Contents Trigger system The offshore trigger is described in detail in chapter 4 the electronics implementation is presented here The offshore trigger allows the selection of a subsample of the total data flow for digitisation transmission and processing on shore The trigger is based on time coincidences of signals between optical modules of the same storey and also between adjacent storeys In order to construct the trigger the ARS mother board ARS_MB produces signals corresponding to whether the output of the each of the three PMTs has passed a lower threshold LO or a higher L00 threshold the thresholds are programmable via Slow Control These signals are sent via the LCM backplane to the LCM trigger board LCM_TRIG Here a decision based on time coincidences between the six set of signals is made as to whether to read out just the local triplet of OMs a L1 trigger or to initiate a global readout request L2 trigger If a L2 trigger is generated it is passed via the SCM to the Junction Box trigger board JB_TRIG1 Here the L2 triggers from all lines are optically merged ORed using a passive optical splitter The output of the splitter is regenerated using a BIDITRIG board and retransmitted at a different
56. ol interface with standard MODBUS protocol via the UNIV1 daughter board Interfaces inside LCM are e LCM DAO SC board for clock signal reset enable and Slow Control RS485 bus by twisted pairs on backplane e MLCM SWITCH board with twisted pairs PECL RX and TX signal on backplane e POWER BOX for voltage 5V and 3 3V from backplane Page 5 37 Associated Technical Notes e 3 LCM08 04 BIDIANT BIDIDEV User s manual e 3 LCM08 01 UNIVI User s manual e 3 LCM20 01 LCM internal organisation Page 5 38 Next Up Previous Contents PBS2 1 006 LCM TRIG in LCM container Schematic diagramme of the LCM_TRIG board The main functions of the LCM_module are e Reduce rate and size of data to that manageable by the DAQ system and the ONSHORE filter e Generate a LI trigger for local readout of the LCM e Generate a L2 trigger for global readout of the whole detector e A variety of options for the L1 and L2 trigger requirements based on coincidences between th0 thl signals of the local storey and the L1 trigger from the upper storey e Delays pulse widths configured by slow control via UNIV board precision of 10ns e BIDITRIG daughter board used to receive transmit L2 and RoR on single fibre Interfaces to e LCM DAO SC board by slow control RS485 bus by twisted pairs on backplane e ARS boards 1 2 3 4 by twisted pairs for Trigger 0 00 L1 L2 RoR signals Page 5 39 JB Junction Box L2
57. ontrol parameters reading for board monitoring with UNIV1 daughter board The main parameters are optical signal detection temperature measurement laser bias current and modulation byte status filter addressing mask configuration etc Interfaces inside LCM e LCM DAO SC board for clock signal reset enable and slow_control RS485 bus by twisted pairs on backplane e Trigger board LCM_TRIG clock signal and enable pulse twisted pairs on backplane e Acoustic boards ACOUST_RX PREAMP ACOUST_RX_DSP and ACOUST_RX_DSP for clock signal and resets by twisted pairs on backplane e ARS MB for clock signal and reset time stamp by twisted pairs on backplane Page 5 41 e ARS LED beacon for clock signal and reset by twisted pair on backplane e LCM power box for voltage 5V and 3 3V by backplane e LCM optical connection board LCM OPTCON via the BIDIANT transceiver to the main cable Associated Technical Notes e 3 LCM 03 01 Numerical clock distribution for ANTARES Proposal e 3 LCM 03 02 Clock Board interfaces description e 3 LCM 18 02 Clock distribution prototypes tests Page 5 42 Next Up Previous Contents PBS2 1 011 Power Box for LCM and SCM The LCM power module is contained within a copper housing which is mounted at one end of the power and data bus support assembly To minimise EMC radiation all input and output electrical connections are made through individual ceramic filters and the housing lid is seal
58. ore trigger is received the ARS begins the digitisation of the analog signal inside the analog pipeline for WF sampling or internal charge integration for the SPE event the resulting digital data packet is sent over the chip serial output to the DAQ board If no trigger is received within a fixed latency the signal is discarded The bandwidth of the readout system is increased using a Dense Wavelength Division Multiplexing DWDM and Ethernet switches Its implementation is summarised in Figure 2 Page 5 4 shore station M outline de to from tw ani oO o ye DE T U a D v Li lt 2 D cs n oc co c O a ie o E E di di pi 2 o SCM container elo receiver elo transmitter eio receiver elo receiver pa D 2 8 D 2 a switch MLC hl container CMH Gk LCMLUG hE M LC LEMHG LC Mi LCM LCM __1 L CM ccc Figure 2 The offshore DWDM system At the DAQ board of an LCM LCM_DAQ SC the data produced by three ARS motherboards is transmitted using the BIDIANT transceiver board via optical fibre 1310 nm to the MLCM At the MLCM the data from the five LCMs MLCM four slaves
59. orst case of a signal traversing the 30 connectors of a complete line the Page 5 16 maximum optical power loss is 3 dB e Reliability of plugging unplugging better than 0 05 dB e Reliability in time better than 40 years All the OPTCLIP II connectors are located on the LCM_OPTCON card Associated Technical Notes e 3 LCM 1301 A Design Specifications for the ANTARES optical DAQ DWDM Network Part I 3 LCM 18 04 A Thermal tests for LCM container 3 LCM 20 01 A LCM internal organisation for the electronics function implementation inside this container 3 SCM 20 01 A SCM internal organisation for the electronics function implementation inside this container 3 LCM 20 02 A LCM SCM boards mechanical dimensions and backplane connector implementation Page 5 17 ANTARES Fiber distribution In the line LOM 30 LOM 29 LOM 28 i MLCM27 aid LOM 26 LOM 25 LOM 24 LOM 23 MLOM 22 LOM 21 LOM 20 LOM 19 LOM 18 MLCM 17 LOM 16 LOM 15 LOM 14 LOM 13 MLOM 12 LOM 11 LOM 10 LOM 09 LOM 08 MLOM 07 LOM 05 LOM 05 LOM 04 LOM 03 MLOM 02 LOM 01 EMC 30 EMC 29 EMG 28 EMO 27 EMG 26 EMG 25 EMG 24 EMG 23 EMG 22 EMG 21 EMS 20 EMG 19 EMG 18 EMG 17 EMG 16 EMG 15 EMG 14 EMG 13 EMG 12 EMG 11 EMG 10 EMG 089 EMG 08 EMC OF EMS 05 EMG 05 EMS 04 EMO 03 EMO 02 OMOOOOBOOOOBOOOOB8OOO0OOB8OO0OO0O08oO00 EMG 01 O 21 ibers available in ihe EMC cable SCM ss Dalia Sbw Control _ Tigger bck Page
60. pectral width operating in the 1550nm range at 1 25 Gb s The system is based on the ITU grid standards for DWDM applications with 400 GHz channel spacing The specific optical ITU channel wavelength is obtained by very accurate temperature control with a Thermo Electric Cooler TEC Temperature stabilisation of lt 0 1 C is needed for 0 1nm wavelength locking The Pin Diode Receiver with Trans Impedance Amplifier TIA and Limiting Amplifier LIM converts the optical signal dy back to an electrical signal 4 The main specifications of SCM DWDM Board are e Electro Optical conversion and vice versa of Fast Ethernet 100BASE TX signals e DWDM Laser temperature control to lt 0 1 C e Slow control parameters Read Only for board monitoring with UNIV1 daughter board The main parameters are optical signal detection laser temperature measurement laser wavelength lock laser bias current and laser modulation current Interfaces inside SCM are e DAO SC Board for Slow Control RS485 bus by twisted pairs on SCM backplane Page 5 73 e DAQ SC Board Fast Ethernet signals via coaxial SMB connectors e Optical I O to the SCM DWDM MUX amp DEMUX e Backplane for Supply Voltages 3 3V and 5 0V Associated Technical Notes e http www nikhef nl n05 antares ETR_ Notes ETR2000 07s pdf e http www nikhef nl n05 antares ETR Notes ETR2000 08s pdf Page 5 74 Up Previous Contents PBS 2 2 014 SCM DWDM MUX amp DEMU
61. rted inside the SCM_ CRATE are o COMPASS MB ARS MB for laser beacon SCM DWDM LCM DAQ SC SCM_WDM SCM_ CLOCK SCM_ REP 2 boards SCM ACOUST1 to 6 and Page 5 65 POWER BOX Associated Technical Notes 3 SCM 20 01 SCM internal organisation Page 5 66 Next Up Previous Contents PBS 2 2 003 SCM WDM in SCM container Schematic diagramme of the SCM_WDM board PECL 1534 nm OPTIC FIBER OPTICAL CIRCULATOR 1549 nm The main specifications of the SCM WDM module are e Bi directional electrical optical module using WDM Wavelength Division Multiplexing concept to send the reference clock and control words from the ON CLOCK board to all the LCM_CLOCK boards e Receive status words from a selected LCM CLOCK board e The wavelength of the optical signals are 1535 nm from ON_ WDM to SCM _ WDM and 1549 nm for the opposite direction e The clock signal converted in electrical PECL format are sent to the SCM CLOCK SCM_REP boards in order to be regenerated and converted to optical signal for each sector e Slow control parameters reading for board monitoring with UNIV1 daughter board The main parameters are optical signal reception switching ON OFF laser driver temperature measurement e Temperature of the laser controlled by Thermoelectric Cooler controller TEC DN1220 ThermoOptics Interfaces to e SCM CLOCK board through the Input Output PECL channels 200 Mbps e SCM REP boar
62. s for the noise output from each supply will be given when the new prototype module is tested Detailed view of the electrical layout of the power module Slow Control The slow control has only two functions 1 Monitoring all output supplies voltage and current and the internal temperature of the module 2 Operating the optical switches which isolate the OM power under fault conditions Physical views of the LCM Power_Box i KAUST TJI Li eo BALI i E Pe t a i s Eg a i i 3 J l k F du Page 5 44 Page 5 45 Next Up Previous Contents PBS 2 1 012 LCM OPTCON board in LCM container Schematic of the LCM _OPTCON board To o From Taichi CRA Cable from Cable ta PEPENE nest The main function of the LCM_OPTCON board is the distribution of all optical fibres or power wires from the EMC to the LCM_CRATE boards or pass them to next floor Each cable penetrator has 21 optical monomode fibers and 9 power wires The LCM_OPTCON board includes optical connectors and solder contact points for signal distributions Optical connectors are OPTOCLIP II connectors from Deutsch company these connectors has been tested with a power loss insertion lower than 0 1 dB and reproducibility better than 0 05 dB For electrical power connection each LCM_OPTCON board includes PCB wire configuration which can be cut or assign for each floor before integration The LCM_OPTCON board is
63. s the data locally produced e the SCM correctly receives and internally distributes the CLOCK reference signal In addition it correctly executes the control instructions that it may receive along the CLOCK connection e the SCM correctly controls and or communicates with the devices locally connected SPM laser beacon acoustic transponder pressure or CTD sensor sound velocimeter e the SCM correctly elaborates the analog signals coming from the Laser Beacon photodiode and the acoustic transponder Interfaces to the SCM are e SPM connector 400 VDC power from Test Bench power supply to SCM RS485 twisted pair for SPM slow control emulation Page 5 61 e JB SPM side DATA SC and CLOCK fibers these connections will be made at the OPT_CON level e String side 6 CLOCK fibers these connections will be made at the OPT_CON level e Laser beacon connector 48 V power from SCM RS485 twisted pair for laser beacon SC emulation output pulse from SCM for laser drive and analog input from simulated photodiode to SCM e Acoustic transponder connector emulator for analog signal from acoustic transponder e Pressure or CTD sensor connector 48V power from SCM RS232 serial communication with sensor emulator e Sound velocimeter connector 48V power from SCM RS232 serial communication with sensor emulator e Backplane check that the 20 MHz clock from the Clock board is correctly distributed interface to the internal RS485 MODBUS oth
64. th 50 C and 1000 W m Rain container closed on quay for one month Thermal shocks From 50 C air to 15 C seawater Sinusoidal vibrations transport simulation 5 55 Hz on container without packaging Half sinusoidal shocks of 15 g acceleration and 50 Hz on container e Free fall height 700 mm on metallic or concrete floor Changes in the external appearance of objects can be tolerated as far as they do not impair the functionalities of the object The first electronics boards must pass these qualification criteria The qualification program is described in technical note 3 LCM 20 04 A Accelerated Stress Testing scenario AST The overwhelming majority of electronics failures are latent hidden manufacturing defects Once a robust design has been qualified testing for reliable field operation can be done much faster and cost effectively under stress levels that exceed the end use specifications An efficient stress screen is to simulate one year of a product s overall fatigue lifetime This should eliminate 90 of the front end life cycle bathtub curve of infant mortality leaving more than 20 years of normal use fatigue lifetime in the product Page 5 19 The following AST scenario is applied to all electronics cards before integration inside any crate container cf also 3_LCM 20 04 A e Temperature cycling from 10 C to 40 C 4 cycles during 2 hours e Vibration with 3 g acceleration during 30 mn with
65. the LCM DAQ SC board external test trigger signal This connector drives also the main RS485 serial bus for all boards inserted inside the LCM_CRATE in order to test slow control without the LCM DAQ SC board e The boards inserted inside the LCM CRATE are in the maximal configuration COMPASS _MB ARS MB for OM1 2 and 3 ARS_ MB for LED beacon LCM DWDM LCM_SWITCH MLCM_BIDICON LCM DAQ SC LCM _ CLOCK LCM TRIG LCM_ ACOUSTI 2 and 3 and POWER BOX Page 5 28 Next Up Previous Contents PBS 2 1 3 COMPASS MB board in LCM and SCM containers Schematic view of the COMPASS _ MB board Humidity Temp sensor of sensor ARS_MB 1 Temp sensor of Temp ARS_MB 2 sensor Temp sensor of ARS_MB3 Temp eee sensor Temp sensor of ARS_MB led TILT COMPASS Daughter board H control for OM2 R5232 H control for interface OM3 __ HY control for OMI The main specifications of the COMPASS_MB board are e Controls the Tilt compass daughter board with a RS485 MODBUS protocol and RS232 tilt compass daughter board bridge e Measures the humidity sensor which is included on the board for humidity control inside LCM and SCM containers e Measures temperature sensors 2 on the board e Reads the temperature sensors which are plugged on ARS_MB cards 1 temperature sensor for each ARS MB 3 sensors 1 from ARS MB LED if present e Controls the low voltage command of the high voltage of ea
66. to 400 Vdc which feeds the DC DC converters of the POWER BOX within the LCM The SPM also provides 48Vdc for use in the SCM and internally for the Slow Control functions of the SPM Power consumption of all the boards in the different LCM configurations was estimated each MLCM needs a total of 31 94 W each LCM slave 1 needs 23 9 W LCM slave 2 20 84 W and LCM slave 3 18 9 W Details are given in technical note 3 LCM 20 05 A Page 5 9 Next Previous Up Contents Clock Distribution The main purpose of the clock system is to provide a common clock signal to all ARSs It consists of a clock generator on shore a clock distribution system and a clock signal transceiver in each LCM In addition it can distribute a small number of other commands to the LCMs These commands can be addressed to a single LCM or to all LCMs simultaneously The same clock is also used by the acoustics positioning system The main specifications of the clock system are e generation of a 20 MHz clock signal e Distribution of the common clock signal to all LCMs e Distribution of synchronised data commands for common orders like DAQ start or stop run e Time stability better than 0 5 ns e Time correlation with the GPS time better than 100 ns e Possibility to measure delay propagation between on shore to each LCM or SCM container with a precision better than 1 ns for time calibration The clock system is based
67. with the power supply and some boards Electronics crate prototype with inserted boards and the POWER _BOX Flange with OMs Connectors Electronics Boards are inserted ee Power box Flange with 4007 to line cables 5V 48V etc Penetrators The thermal cooling of the electronics is ensured using copper screens inserted between the electronics boards These screens are in contact with the titanium container maintained at the ambient sea water temperature 14 via flexible copper fingers Hot electronics components are connected directly to these screens via a thermal bridge Laboratory measurements show that a thermal resistance of 17 watt can be obtained using this method see internal note 3 LCM 18 04 A The copper screens have a secondary function of providing electromagnetic shielding between sensitive analog functions such as the ARS motherboard ARS_MB and noisy digital functions such as the MLCM SWITCH For the electrical connections soldering is adopted in order to minimise the risk of oxidation of connector contacts All connectors between the boards and the backplane are gold plated For the optical connections fusion splicing is adopted wherever possible When necessary optical connectors will be used OPTOCLIP Il After qualification tests connectors from the Deutsch company have been chosen they have the following features e Optical power loss average 0 07 dB per connector max 0 1 dB For the w

Chapter 5-Electronics - antares

Contents

Download Pdf Manuals

Related Search

Related Contents