Errata to MCF5307 ColdFire Microprocessor User`s Manual
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1. for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola and A are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Affirmative Action Employer Motorola Literature Distribution Centers USA EUROPE Motorola Literature Distribution P O Box 5405 Denver Colorado 80217 Tel 1 800 441 2447 or 1 303 675 2140 World Wide Web Address http Idc nmd com JAPAN Nippon Motorola Ltd SPD Strategic Planning Office 4 32 1 Nishi Gotanda Shinagawa ku Tokyo 141 Japan Tel 81 3 5487 8488 ASIA PACIFIC Motorola Semiconductors H K Ltd Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po New Territories Hong Kong World Wide Web Address http sps motorola com mfax INTERNET http motorola com sps Technical Information Motorola Inc SPS Customer Support Center 1 800 521 6274 ele2. Order Number MCF5307UMAD D MOTOROLA Rev 0 1 2001 Semiconductor Products Sector ICS ROPR OCES SOR Errata to MCF5307 ColdFire Microprocessor User s Manual These errata describes corrections to the MCF5307 ColdFire Microprocessor User s Manual For convenience the section number and page number of the errata item in the user s manual are provided The MCF5307 device referred to in this document is the MCF5307FTxxB Please check the WWW at http www motorola com ColdFire for the latest updates This document contains information on a new product under development by als una Motorola Motorola reserves the right to change or discontinue this product without Digital DN A Motorola Inc 2001 All rights reserved Prom Wura Section Page 2 6 2 40 Changes Add the following text Note that if the upper 16 bits of a longword aligned fetch location contain an unknown illegal opcode while the lower 16 bits contain a Bxx B opcode where Bxx BRA BSR Bcc an incorrect re direction of the prefetch stream to an improper target location will occur An example of this is seen in the following code mov l 4 pc d0 1 4 a0 jmp a0 label long labell long label2 In this case the code would disassemble to the following X 6 207b 0c04 mov 1 X 2 4ed0 jmp X 0 wxyz 6040 pointer to labell example XHA gee ee es pointer to label2 In this example after the JMP instruction the label pointer
3. PARK 10 or 01 BWC should equal 000 MCF5307 ColdFire Microprocessor User s Manual Errata O MOTOROLA Section Page 12 5 2 1 12 13 12 5 2 2 12 13 18 9 18 23 20 1 20 2 20 3 20 4 M MOTOROLA Changes Add the following text NOTE Use the CPU to write to the UART transmitter buffer The DMA module is not able to properly transfer information from memory to the UART Add the following text Do not use single address access mode in cycle steal mode errant accesses may occur Add the following text NOTE Either do not allow external master access to SDRAM using the MCF5307 DRAM controller or provide external termination for SDRAM bus cycles by an external master The MCF5307 does not provide correct termination for external bus masters using the on chip SDRAM controller Add the following diagram and text Figure 1 shows the allowable undershoot voltage on the MCF5307 Note that 1 2 V undershoot is only allowable if it is present 1 or less of the total processor operating time Vi Gnd 0 8V Gnd 1 2V Not to exceed 0 15 C1 gt ret Figure 1 Undershoot Voltage Make the following changes in Table 20 6 Change the Min specification for B14 to 2 0 nS for 66 MHz Change the Min specification for B16 to 2 0 nS for 66 MHz MCF5307 ColdFire Microprocessor User s Manual Errata 5 Section Page Changes M MOTOROLA MCF5307 ColdFire Microprocessor User s Manual Errata Di
4. ctronic mail address cre wmkmail sps mot com Document Comments FAX 512 933 2625 Attn RISC Applications Engineering World Wide Web Addresses http www motorola com PowerPC http www motorola com netcomm http www motorola com Coldfire M MOTOROLA MCF5307UMAD D
5. disassembles to what looks like an unknown opcode wxyz any unknown opcode followed by a 16 bit opcode that looks like a Bxx B opcode but actually isn t In this case the branch acceleration logic calculates the target address and begins prefetching at X 0x44 This can be particularly problematic if the address that the acceleration logic jumps to is at an offset range that doesn t exist resulting in an illegal access More specifically if the 8 bit displacement that is decoded in the look alike Bxx b instruction branches to an offset 128 byte to 128 byte that no chip select is programmed to or where no memory exists then the bus cycle hangs However if the offset is in a chip select or memory range although the branch is to an improper address location the error eventually recovers when the JMP instruction at X 2 is executed in the operand execution pipeline To avoid this scenario put a 128 byte space at the beginning and end of any code sections that might be affected by this sequence so calculation of the improper target address does not impact system operation In addition the assembly language for label or case statements as defined above can be modified to guarantee the problem does not occur The use of the illegal opcode prior to the table of addresses prevents improper code re direction Note that the ColdFire ISA illegal opcode is different from the unknown illegal opcodes referenced above An example of the ille
6. gal opcode in a program is as follows mov l 6 pc d0 1 4 a0 offset changed to 6 jmp a0 illegal added instruction as workaround label long labell long label2 MCF5307 ColdFire Microprocessor User s Manual Errata A MOTOROLA Section Page Changes 3 1 2 3 3 Add the following text If 16 bit MAC instruction operands are being used from different halves of different CPU registers and if the V bit is being checked or if the MAC unit is operating in saturation mode code modifications are required to ensure that the overflow logic works properly For instance mac wRx u Ry 1 should be replaced with the following equivalent sequence swap Rx mac w Rx 1 Ry 1 swap Rx mac wRx 1 Ry u should be replaced with the following sequence swap Rx mac w Rx u Ry u swap Rx Of course the second swap instruction in each case should be removed if the MAC instruction specifies a memory operand that is to be loaded into the Rx register Similar sequences should be substituted for MSAC W instructions The case for 16 bit operands from different halves of the same CPU register y x is slightly more complicated The instruction mac w Rx u Rx l should be replaced with cmp 1 x amp 0x80008000 bne b labell mac w Rx 1 Rx 1 bra b label2 labell mac w Rx u Rx 1 label2 Similar sequences should be used for MSAC W instructions 5 4 4 5 11 In the description of the EMU bit replace the bit description wit
7. gitalDNA is a trademark of Motorola Inc The ColdFire name the ColdFire logotype and ColdFire 5307 are trademarks of International Business Machines Corporation used by Motorola under license from International Business Machines Corporation Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors There are no express or implied copyright licenses granted hereunder to design or fabricate PowerPC integrated circuits or integrated circuits based on the information in this document Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by customers technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or
8. h the following text Do not set bit 13 of the debug module s Configuration Status Register The quickest entry into emulator mode after reset is created with the following sequence 1 While in the BDM initiation sequence program a debug breakpoint trigger event by an operand reference to address 0x0 or 0x4 As part of this sequence the debug interrupt vector must also be initialized to the same address as the initial PC defined at address 4 M MOTOROLA MCF5307 ColdFire Microprocessor User s Manual Errata 3 Section Page 5 4 7 5 14 5 4 7 5 15 5 4 7 5 16 5 6 1 5 42 6 2 10 1 6 11 9 2 3 9 6 11 4 2 11 18 12 4 4 12 9 Changes 2 When the BDM GO command is received by the processor the reset exception processing fetches the longwords at addresses 0 and 4 in normal mode and then a debug interrupt is immediately generated before the first instruction is executed 3 Execution continues in emulator mode Replace the last two sentences in the first paragraph with the following Breakpoint logic can be configured as a single one level trigger or a combination of one level triggers TDR 15 0 define the first level trigger Add the following text NOTE The second level trigger does not work properly on the MCF5307 TDR 29 15 are effectively reserved bits In the description for the DI bit add the following text Do not set DI for word or longword breakpoints Add the following text If debug inte
9. rrupts are enabled disable the capturing of operand writes because the stream of PST 3 0 0xD values may not be contiguous Alternatively ignore PST 3 0 0x0 values occurring during a debug interrupt Let the debug interrupt exception processing be defined from the initial PST 3 0 0xD until PST 3 0 0x5 Table 6 6 PARK bit description add the following text NOTE If round robin mode 00 is selected ensure that DCR BWC is set higher than the value in the BCR If park on internal DMA 10 or park on ColdFire core 01 is selected select DCR BWC 000 Add the following text NOTE For interrupts sources with levels 1 6 write a higher level interrupt mask to the status register before setting the IMR After the IMR is set return the interrupt mask in the status register to its previous value Do not mask a level 7 interrupt in the IMR If these precautions are not followed a spurious interrupt may occur Add the following text NOTE Glitches may occur on the address lines unless EDGESEL is tied high or BCLKO is qualified with the assertion of SRAS or SCAS before connecting to the EDGESEL input These glitches do not affect DRAM controller operation and are within the undershoot limits specified by Figure 1 of this document Table 12 3 BWC bit description add the following text NOTE Do not select the 000 encoding when MPARK PARK 00 the BWC encoding must be set higher than the value in the BCR in this mode If MPARK
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