PROCCamLink IP User Guide
Contents
1. ccuccococecocouees 2 PROCCamLink Connections Block Diagram 3 Setting Up PROCCamLink Using PROCWiIZartd 5 Debugging PROCCamLink Using PROCW zarda 8 PROCCam Link IP Initialization Methods 10 Figures Figure 1 Signa flow for Base Medium and Full configuration 3 Figure 2 Signal flow for Double Base Configuration 4 Figure 3 Configuration Mode ICON cccssssssseseeeeeeeeeseeseeeeeeeeceessneeeesseeoaees 5 Figure 4 PROCCamLink Configuration Dialog cccceeesseeseesseeeeeeeeeeeees 6 Figure 5 PROCWizard Configuration Mode Window with Camera Link IP 7 Figure 6 Debug Configuration Mode ICON cccccssssseeseeeeseesseeeeeeeeeeeeeeees 8 Figure 7 PROCWizard Debug Mode Window with Camera Link IP 8 Introduction PROCCamLink P is a GIDEL Intellectual Property that provides a simple and convenient way to connect an external CameraLink camera to GIDEL PROC boards This connection is achieved via PSDB_CL or PSDB_CL2 daughterboards A block diagram in the next section Figure 1 and Figure 2 schematically shows the signal flow when using PSDB CL and PROCCamLink IP The camera signals are processed in two stages first by the PSDB_CL daughterboard and then by the CameraLink_Config module on the PROC board2. PROCWizard if a PROCCamLink core is added to the design For more detailed description of these methods please refer to the Proc API document CameraLinklnit class provides the following methods gt CameraLinklnit This is the CameraLinklnit object constructor gt WriteData The WriteData method writes data to serial communication port gt ReadData The ReadData method reads data from serial communication port gt SetWaitParam The SetWaitParam function sets the polling rate and timeout period for WriteData and ReadData functions gt SetBaud The SetBaud function sets the baud rate for the serial communication This function changes the values of CameraLinklnit internal members rather than actually changing the baud rate In order to physically change the port baud rate call Initialize method immediately after calling the SetBaud method 10 PROCCamLink Initialization Methods gt Initialize This method adjusts the port baud rate according to the values of CameraLinklnit internal members gt GetStatus This method returns the status of CameraLinklInit object The status is one of the following CLINK_OK Last CameraLink operation was successful CLINK_ERROR_INIT Last CameraLink operation could not be performed because the CameraLinklnit object was incorrectly initialized This error may occur if the Create function is called with incorrect parameters CLINK_ERROR_TIMEOUT Last CameraLi
3. in GIDEL PROCWizard The Configuration Mode is used to build designs in PROCWizard New items can be added to the design in this mode and existing items can be redesigned To enter the Configuration mode click the button in PROCWizard s toolbar as shown in the figure below File View Macro History Generate Mode Options Help Dal ala jejunia w Figure 3 Configuration Mode Icon Once in Configuration Mode you will see the design you are building represented by a tree of items To learn more about these items please refer to PROCWizard User Manual To add PROCCamLink to your design choose the IC item that represents the FPGA device to which the PSDB_CL daughterboard is connected Right click on this IC and choose IP Core gt Camera Link from the pop up menu This will open a dialog box shown in the Figure 4 This dialog box enables the user to configure the PROCCamLink IP Setting Up PROCCamLink IP Camera Link Serial Communication Frequency baud Check with your camera 3600 Mode Assignment tapshit Registered inputs Check this box to synchronize all the inpute with the Base channel gtrh_Cameralink Figure 4 PROCCamLink Configuration Dialog The following parameters are defined in this dialog box gt Mode defines the Camera Link mode to be used Base Medium or Full Camera Link configuration Base_1 or Base_2 for Double Base Camera Link configuration gt Serial Communi
4. The translated ready to use signals enter the user s module where they can immediately be operated by user s logic This system concept provides an easy way to connect to an external camera while freeing the designer from having to deal with hardware connections and board constrains Once the PROCCamLink IP has been set up PROCWizard automatically connects the required signals to the designer s module The signals entering the user s module are ready for immediate use and are arranged in the format the user has requested No further data translation is needed aa For more information please refer to PSDB CL Data Book PROCCamLink IP Key Features GiDEL PROCCamLink P was designed to provide a simple and convenient way to connect an external camera to GiDEL PROC boards using PSDB_CL or PSDB_CL2 daughter boards CameraLink IP key features include v Full support of all standard CameraLink modes base medium full and double base modes v Automatic and complete connection of CameraLink to user s HDL module v Serial Communication with camera v Optional synchronization of all Camera Link inputs with the Base channel input clock v Simple interface v Optimization for easy control by hardware and software PSDB_CL and PROCCamLink Connections Block Diagram This section schematically shows the signal flow when using PROCCamLink IP with PSDB_CL The camera data enters PSDB_CL daughterboard where it is converted fr
5. Wa AA AA AA E ee CEN mil YAFUTA LITA ETE i FOPRURPE TOR eet AETI TITE INI il f STEERER ERE TE 181 KINU r TOA FETTER EER RPE M M R RT EY ETT INE User Guide February 2008 GiDEL products and their generated products are not designed intended authorized or warranted to be suitable for use in life support applications devices or systems or other critical applications 1993 2008 by GiDEL Ltd All rights reserved GiDEL PROCStar IFM PROCSpark IFM PROC_DSP PSDB_CL PROCWizard PROCCamLink PROCMultiPort and other product names are trademarks of G DEL Ltd which may be registered in some jurisdictions This information is believed to be accurate and reliable but GIDEL Ltd assumes no responsibility for any errors that may appear in this document GiDEL reserves the right to make changes in the product specifications without prior notice Windows NT Windows XP Windows 2000 Stratix Il EP2S60 DDRII CameraLink and other brands and product names are trademarks or registered trademarks of their respective holders USA Worldwide 1600 Wyatt Drive Suite 1 2 Ha ilan Street P O Box 281 Santa Clara Or Akiva 30600 CA 95054 USA Israel Tel 1 408 969 0389 Tel 972 4 610 2500 Fax 1 866 615 6810 Fax 972 4 610 2501 sales usa GiDEL com sales eu GIDEL com Web www GiDEL com info GiIDEL com Contents IO HO IN err TE 1 PROCCam Link IP Key Features
6. cation Frequency sets the serial communication frequency with the camera from 9600 to 921600 baud gt Mode assignment defines output data width and the output standard tapsbit tap10bit tap12bit tap14bit tap16bit or RGB24bit for Base mode tap8bit tap10bit tap12bit RGB3Obit or RGB36bit for Medium mode tap8bit for Full mode gt Registered inputs checking this checkbox synchronizes all Camera Link inputs with the Base channel input clock not only sampling but full synchronization In this case a single strobe signal and a single validation signal will appear in the top level design instead of separate signals for each channel Ua For more details about Camera Link configuration see Specifications of the Camera Link Interface Standard for Digital Cameras and Frame Grabbers Setting Up PROCCamLink IP Clicking Finish adds the PROCCamLink IP to the design A Camera Link IP with all its elements can be cut and pasted or copied and pasted to another IC provided that the target IC has Camera Link Interface PROCCamLink design consists of camlink_config and user_camlink subdesigns Camlink_config is the CameraLink interface unit that provides the mechanisms required to communicate with a camera User cannot alter this unit or add functionality to it In order to add functionality or user s logic one must use the user_camlink subdesign This unit is added especially for that purpose All the CameraLink signals data clock
7. e ab Gorinector E E 8 0 2 4 cameraframe line data valid Camera Camera S_IXCC gt q Transmitter kaa a 5 S_CC Control Control CL in Control olle 0 _ user 2 cameracamera control Serial 2p Serial 2 s_rxSer 0 2 0 ci e ransciever rm A j o 715 5 E C 3 z dp omm Comm seel Coru lt 05 6 optional host controls gt RE ORES ee E PSDB_CL Seas ar OG Ee aaa a aaa ED uu _ if Module PCI Interface for Camera Control PROC Board From To PCI Data channels may be tap8 tap10 tap12 tap14 tap16 RGB24 RGB30 RGB36 in Base Medium Full modes or tap8 tap10 tap12 tap14 tap16 RGB24 in Double In Medium and Full modes all the data transfers may be synchronized to the base channel In this case a single strobe signal and a single validation signal will enter the user s design instead of separate signals for each channel as shown in the block diagram To activate this option select Registered inputs in PROC Wizard while configuring the CameraLink IP Figure 2 Signal flow for Double Base configuration GiDEL PROCWizard automatically generates all the units shown in the above block diagrams as well as the top level design For more information please refer to PROCWizard User Manual Setting Up PROCCamLink Using PROCWizard To set up the PROCCamLink P first enter the Configuration Screen
8. e written read on the fly to from registers and memories that appear in the design To enter the Debug mode click the me button in PROCWizard s toolbar as shown in the figure below File View Macro History Generate Mode Options Help Figure 6 Debug Configuration Mode Icon Once in Debug Mode you will see the design you are building represented by an item tree as shown in Figure 5 To access registers memories use the Read and Write buttons and the Data Hex field Untitled GiDELLtd PROC Wizard File View Macro History Generate Mode Options Help Su ala gt lilo lm la e alg Card Entity f user _camlink Mode Offset Hex EA Local Memory d pame Ae I TE Data Hex Write ABF_Into ac g gt gt gt ER ites wite eri F_camlink_contig Z seat H Fo ser com read 4 El F id data H EB F_ser_conn_vwrite Interrupt recewed j emor m F wi data Testing Files Operations gt F ser com status Sn eat E amp F ser com wr ena Reset interrupt counter F_ser_com_rd_ena Load Memory Fill EEE Increment real ELE Compare Figure 7 PROCWizard Debug Mode Window with Camera Link IP Debugging PROCCamLink IP Components registers and memories of camlink_config subdesign allow user to debug Serial Communication to camera o Register Ser_com_ck_dev is used to change Serial Communication frequency on the fly T
9. he value for this register is calculated as follows Ser_com_ck_dev_value PCI clock frequency Hz Serial communication frequency baud For example if the PROC Board is installed in PCI 64 66 MHz slot and Serial Communication frequency must be 9600 baud then the value that should be written to this register is Ser com ck dev value 66000000 9600 6875 1ADB Hex PROCWizard always uses hexadecimal values when reading writing registers memories o Fields Ser_com_wr_ena and Ser_com_rd_ena of ser_com_status register indicate whether the register is ready for the user to read write data from to camera O ready 1 not ready o Register wr data of ser com write register group enables user to write data to the camera each write transaction transfers 8 bits of data o Register rd data of ser com read register group enables user to read data from the camera each read transaction accesses 8 bits of data In addition user may use the Debugging Screen to read write data to PROCCamLink user s unit user_camlink and or to other units To learn more about debugging using PROCWizard please refer to chapter 6 in PROCWizard User Manual PROCCam Link IP Initialization Methods This section briefly describes the methods of CameraLinkInit class This class provides an API that can be used for implementation of an interface with PSDB_CL daughterboard An object of this class is automatically generated by G DEL
10. mLink IP Connections The block diagram below shows the signal flow when using Double Base configuration Base mode f CameraLink_config first CL Module GiDEL s IP N s_CameraLink_config second CL Module GiDEL s IP User s Acquisition Module f user CameraLink User s Acquisition Module s User CameraLink L araa a aaa a aaa a il f_tap f_rgb first image data channels Data 4 Data 28 f rx base 4 LVDS X 4 0 can X 28 0 28 0 E f_strb_base First 3 first camera clock CLKX CLKX f_rxclk base SI Base E lt p gt Connector 7 7 L 2 Z f FVAL f_LVAL f DVAL f_spare amera amera J E Transmitter Sees 4 S 2 18 camera frame line data valid Control Control Chin Control E S Sifa f Serial 22 Transciever 14 Serial 2 f_rxSer Ma Si IM a SSS SSN Sh st Comm Comm T CL in Serial Comm 2 T BEI Ue ere O _ gt o p doana oossoo F o Ow a 0 _ Optional host controls o 6 E e HP S E ais s tap s_rgb LL O 0 second image data channels en WA Data 28 S_rx_base E E li s_strb_base T 2110 AA Receiver X 28 0 C z V second camera clock Second 4 n i gt q v ur 2 Q 7 ZA p econd CLKX CLKX s _rxclk base z 8 JES AI spar
11. nk operation has timed out CLINK_ERROR_INVALID_INPUT Last CameraLink operation was not performed because the input value was incorrect gt Create This method is called by other methods of the Proc class This is an internal method and is not intended to be called by user Distributed by MaxxVision GmbH Sigmaringer Str 121 70567 Stuttgart Tel 49 711 997 996 3 Fax 49 711 997 996 50 www maxxvision com info maxxvision com 11
12. om LVDS serial data to standard parallel TTL signals These signals are then transferred to an FPGA on the PROC motherboard where they enter the CameraLink_Config module This module translates the signals and transports them over several buses to the top level design The top level design connects these buses to user s entity module where user can operate them Several configurations are available with PSDB CL Base Medium Full and Double Base The block diagram below shows the signal flow when using Base Medium or Full configuration Baia za 2 28 0 GLEZ a Medium Data i 2A viza m CLKY Eo EE 28 LL Data 2A xeago CLAM Camera d Control Serial 2 Comm WAL WA P CameraLink_config CL Module GiDEL s IP rx uli 28 0 rxclk full AIE lt EIE image data channels 7 z E _ medium z sib base sib medium sirb full E 24 0 5 5 camera clocks C sll l 5 Ale FVAL LVAL OVAL spare O reclk_ medium a E F iT le s z ui rm base J E 26 0 i za Oo Br 3 rack base l et optional hast contras 4 a a ACC E i T z CL m Contr T M reSar 5 o 8 CL m Serial Comm _if Module PCI Interface for Camera Control PROC Board ee Dm E G From To PCI Figure 1 Signa flow for Base Medium and Full configuration PROCCa
13. s and control signals enter this unit to allow maximum flexibility The structure of Camera Link design is shown in the figure below CameraLink Camera Link Double Base First tapS8bit baud 9600 F_camlink_config f ser com status OFFSET 0x20 0010 BITS 0 7 READ ONLY zx F ser comwr ena 0 lt UMEMNABLE Ox lt ENABLE Oxo e F_ser_com_rd_ena 1 EMABLE Ox0 S UNENABLE 0x1 fF ser com ck dew OFFSET 0x20 0020 BITS 0 31 WRITE ONLY PA FF ser com read OFFSET 0x30 0000 SIZE 0x100 READ ONLY HA F ser com write OFFSET 0x30 0100 SIZE 0 100 WRITE ONLY F user camlink Figure 5 PROCWizard Configuration Mode Window with Camera Link IP Right clicking on user_camlink allows the designer to add items to this subdesign Here the user can add clocks registers memories and register groups In addition the user can connect this subdesign with PROCMultiPort IP Ports For more information on subdesigns see paragraph Module entity chapter 4 in PROCWizard User Manual For more information on PROCMultiPort IP see paragraph IP Core MultiPort chapter 4 in PROCWizard User Manual Debugging PROCCamLink Using PROCWizard User can access components registers memories and register groups of both camlink_config and user_camlink subdesigns in PROCWizard Debug mode The Debug Mode is used to debug designs in real time using PROCWizard Data can b
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