ADSP-2100 Family User`s Manual, Serial Ports
Contents
1. MODULE RAM code_to_init_AB_SPORT1 Initialization code for autobuffer VAR DM CIRC tx_buffer 10 VAR DM CIRC rx_buffer 10 ENTRY sportl_inits set up I M and L registers sportl_inits I0 tx_buffer I0 contains address of tx_buffer MO 1 fill every location LO tx_buffer LO set to length of tx_buffer I1 rx_buffer Il points to rx_buffer L1 rx_buffer L1 set to length of rx_buffer set up SPORT1 for autobuffering AXO 0x0013 TX uses 10 MO RX uses I1 MO DM 0x3FEF AX0 autobuffering enabled set up SPORT1 for 8 kHz sampling and 2 048 MHz SCLK AXO 255 set RFSDIV to 255 for 8 kHz DM 0x3FF0 AX0O AXO 2 set SCLKDIV to 2 for 2 048 MHz SCLK DM Ox3FF5 AX0 set up SPORT1 for normal required framing internal SCLK internal generated framing AX0 0x6B27 normal framing 8 bit mu law DM 0x3FF2 AX0 internal clock framing set up interrupts IFC 6 clear any extraneous SPORT interrupts ICNTL 0 interrupt nesting disabled 5 Serial Ports IMASK 6 enable SPORT1 interrupts enable SPORT1 AX0 OxOC1F enable SPORT1 leave PWAIT DM Ox3FFF AX0 BWAIT as default Place first transfer value into TX1 AXO DM 1I0 M0O TX1 AX0O RTS ENDMOD Figure 5 24 Autobuffering Example Configuration Code 5 12 MULTICHANNEL FUNCTION SPORTO supports a multichannel function In the m2. control bits in the SPORTO control register are redefined Bits affected by multichannel mode are shown in Figure 5 25 At reset bit 15 is cleared disabling multichannel mode and enabling normal operation Figure 5 25 SPORTO Control Register With M ultichannel M ode E nabled The state of the multichannel length bit MCL bit 9 determines whether there are 24 or 32 channels i e whether the block length is 24 or 32 words A 0 selects 24 word blocks a 1 32 word blocks In multichannel mode the 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Pa Te eT AE I Ox3FFA Receive 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 Word Enables Ox3FF9 1 Channel Enabled 0 Channel Ignored ul I 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LELELLELI LTE LIL Ox3FF8 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 Word Enables Ox3FF7 word length is still set by the SLEN field in the SPORT control register and can be 3 to 16 bits Transmit The multichannel frame delay MFD is a 4 bit field specifying in binary the number of serial clock cycles between the frame sync signal and the first data bit This allows the processor to work with different types of T1 interface devices Figure 5 26 shows a variety of delays Figure 5 26 SPORT Multichannel Frame Delay E xamples The memory mapped receive enable register and transmit enable register are each 32 bits wide and made up of two contiguous sixteen bit registers as shown in
3. YBRXADDDORODEXOAOGOOOBEERRRRRERXOREREERREDO RAR OOOO DR 9 2 H 2 2 amp SPORT Control Register Internal Frame Sync 0X00 XXX1 X0XX 0011 External Frame Sync 0X00 XXX0 X0XX 0011 Figure 5 14 SPORT Receive Unframed M ode Normal Framing Be ee a NEES NS Nal Gah hes gh hea eg ey a RFS YAXXXXXXXXXXYXXX XXX XAXX AX XXX MANX XXX KXAXX oR ____ 65 _ 7 Oa Oaa SPORT Control Register Internal Frame Sync 0X01 XXX1 X0XX 0011 External Frame Sync 0X01 XXX0 X0XX 0011 Figure 5 15 SPORT Receive Unframed M ode Alternate Framing continuous receiving in the alternate framing mode In these four figures both the input timing requirement for an externally generated frame sync and the output timing characteristic of an internally generated frame sync are shown Note that the output meets the input timing requirement thus on processors with two SPORTs one SPORT could provide RFS for the other Pc RE Ne ee Ne Ne NA Ne Neal a A TFS OUTPUT S input VAX AXXXXXAXX VAX XXX AXA DT Oe Ge Glee Le cae A i BE SPORT Control Register Internal Frame Sync OXXX 101X OXXX 0011 External Frame Sync OXXX 100X OXXX 0011 Both Internal Framing Option and External Framing Option Shown Figure 5 16 SPORT Transmit Normal Framing SCLK FS OUTPUT TES inpor AAXXXAMAAXXXAAAXXXXAMAXXAA VAAAAAAAAAAAAAAAAAAAAAANAA DT TELT oe Ee ae Le Oe Oe A SPORT Control Register Internal Frame Sync OXXX 101X
4. 2 2 048 MHz 0 6 144 MHz Assumes CLKOUT frequency of 12 288 MHz Table 5 5 Common Serial Clock Frequencies Internally Generated If the value of SCLKDIV is changed while the internal serial clock is enabled the change in SCLK frequency takes effect at the start of the next rising edge of SCLK Note that the serial clock of SPORT1 the SCLK pin still functions when the port is being used in its alternate configuration as FO FI and two interrupts In this case SCLK is unresponsive to an external clock but can internally i aclock signal as described above 5 6 WORD LENGTH Each SPORT independently handles words of 3 to 16 bits The data is right justified in the SPORT data registers if it is fewer than 16 bits long The serial word length SLEN field in each SPORT control register determines the word length according to this formula Serial Word Length SLEN 1 5 Serial Ports SPORTO Control Register 0x3FF6 SPORT1 Control Register 0x3FF2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SLEN Serial Word Length 1 Figure5 4 SLEN Field In SPORT Control Register For example if you are using 8 bit serial words set SLEN to 7 0111 binary The SLEN field is bits 3 0 in the SPORT control register 0x3FF6 for SPORTO and 0x3FF2 for SPORT1 See Figure 5 4 on the next page Do not set SLEN to zero or one these SLEN values are not permitted 5 7 WORD FRAMING OPTIONS Framing signals identify the beginning of ea
5. 3 Read TXn it returns the 8 bit compressed data ul I N ul The code might look like this TXO AX0O linear data written to transmit register NOP any instruction AX1 TX0O compressed data transferred to AX1 Use the same procedure to expand data but use RXn instead of TXn RXO AX0 compressed data written to receive register NOP any instruction AX1 RXO expanded linear value transferred to AX1 5 11 AutoBuffering In normal operation a SPORT generates an interrupt when it has received or has started to transmit a data word Autobuffering provides a mechanism for receiving or transmitting an entire block of serial data before an interrupt is generated Service routines can operate on the entire block of data rather than on a single word reducing overhead significantly Autobuffering is available on both SPORTO and SPORT1 except on the ADSP 21msp58 59 which autobuffers only on SPORTO Autobuffering uses the circular buffer addressing capability of the DAGs With autobuffering enabled each serial data word is transferred or if multichannel operation is enabled each active word is transferred to or from data memory in a single overhead cycle Autobuffering to program memory is not supported This overhead cycle occurs independently of the instructions being executed and effectively suspends execution for one cycle or more if wait states are required when it happens No interrupt is generated fo
6. Figure 5 27 which can be found on the next page Each bit corresponds to a channel setting the bit enables that channel so that the processor will select its word from the 24 or 32 word block For example setting bit 0 selects word 0 bit 12 selects word 12 and so on Figure 5 27 SPORTO Multichannel Word E nable Registers 5 12 2 Multichannel Operation Received words for channels that are not enabled are ignored that is no interrupts are generated for these words no autobuffering occurs and no data is written to the RX0 register Likewise there are no interrupts and no autobuffering for transmit words that are not enabled During transmit word time slots for channels that are not enabled the data transmit DT pin is tristated Most aspects of SPORTO operate normally in the multichannel mode Specifically word length SLEN internal or external framing IRFS lt WORD 2 WORD 0 WORD 1 gt Peay Neal Nac Nae ea Np eee oy j B0 AAAAAAAA enoren AXX AXXKXAXK AAA e3 82 RFS C E DT is Ge Ee ae es E TDV frame signal inversion INVRFS companding DTYPE and autobuffering are unchanged in the multichannel mode Note It is important that RFS does not occur more than once per frame in multichannel mode Instead of providing frame synchronization the TFSO signal functions as a transmit data valid TDV signal in multichannel mode TDV is asserted while the transmitter is active TDV can be active h
7. Internal Frame Sync 0X10 XXX1 X0XX 0011 External Frame Sync 0X10 XXX0 X0XX 0011 Both Internal Framing Option and External Framing Option Shown Figure 5 10 SPORT Receive Normal Framing See ES A E NAA EAE AT NE Ne N RFS urur Smer V N A DR SPORT Control Register Internal Frame Sync 0X10 XXX1 X0XX 0011 External Frame Sync 0X10 XXX0 X0XX 0011 Both Internal Framing Option and External Framing Option Shown Figure 5 11 SPORT Continuous Receive Normal Framing RFS OUTPUT ON ff PFS eur O A R __ os _ e2 _ 6r 0 _______ m 2 _ amp _ 0 SPORT Control Register Internal Frame Sync 0X11 XXX1 X0XX 0011 External Frame Sync 0X11 XXX0 X0XX 0011 Both Internal Framing Option and External Framing Option Shown Figure 5 12 SPORT Receive Alternate F raming RFS ouput RFS nour TO R ooo eE SPORT Control Register Internal Frame Sync 0X11 XXX1 X0XX 0011 External Frame Sync 0X11 XXX0 X0XX 0011 Both Internal Framing Option and External Framing Option Shown Figure 5 13 SPORT Continuous Receive Alternate F raming low and X can be either The underlined bit values are the bits which set the modes illustrated in the example Figures 5 10 to 5 15 show framing for receiving data In Figures 5 10 and 5 11 the normal framing mode is shown for noncontinuous data any number of SCLK cycles between words and continuous data no SCLK cycles between words Figures 5 12 and 5 13 show noncontinuous and s o
8. RXO the contents of SPORTO receive register is transferred to AYO Because the SPORTs are interrupt driven these instructions would typically be executed within a interrupt service routine in response to a SPORT interrupt 5 4 SPORT ENABLE SPORTs are enabled through bits in the system control register This register is mapped to data memory address Ox3FFF Bit 12 enables SPORTO if it is a 1 and bit 11 enables SPORT1 if it is a 1 Both of these bits System Control Register Ox3FFF 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 Bae See L SPORT1 Configure 1 serial port 0 FI FO IRQO IRQ1 SCLK SPORT1 Enable 1 enabled 0 disabled SPORTO Enable 1 enabled 0 disabled Figure 5 2 SPORT Enables In The System Control Register 5 Serial Ports are cleared at reset disabling both SPORTs Bit 10 of the system control register determines the configuration of SPORTI either as a serial port or as interrupts and flags according to Table 5 4 on the next page If bit 10 is a 1 SPORT1 operates as a serial port if it is a 0 the alternate functions are in effect and bit 11 is ignored At reset bit 10 is a 1 so SPORT1 functions as a serial port Pin Name Alternate Name Alternate Function RFS1 IRQO External interrupt 0 TFS1 IRQ1 External interrupt 1 DR1 FI Flag input DT1 FO Flag output SCLK1 Same Same Table 5 4 SPORT1 Alternate Configuration 5 5 SERIAL CLOCKS Each SPORT operates on its own serial
9. logarithmically encoding and decoding data to minimize the number of bits that must be sent Both SPORTs share the companding hardware one expansion and one compression operation can occur in each processor cycle In the event of contention SPORTO has priority SPORTO Control Register 0x3FF6 SPORT1 Control Register Ox3FF2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PTO TTT TT zr DTYPE 00 Right justify zero fill unused MSBs 01 Right justify sign extend into unused MSBs 10 Compand using p law 11 Compand using A law Figure 5 22 DTYPE Field In SPORT Control Register 24 The ADSP 2100 family of processors supports both of the widely used algorithms for companding A law and p law The processor compands data according to the CCITT G 711 recommendation The type of companding can be selected independently for each SPORT If companding is not enabled there are two formats available for received data words of fewer than 16 bits one that fills unused MSBs with zeros and another that sign extends the MSB into the unused bits The type of companding as well as the non companding data format are controlled by the DTYPE field bits 5 4 in the SPORT control register Ox3FF6 for SPORTO and 0x3FF2 for SPORT1 as shown in Figure 5 22 When companding is enabled valid data in the RX0 or RX1 register is the right justified sign extended expanded value of the eight LSBs received Likewise a write to TXO or TX1 causes the 16 bit value to b
10. 1 Alternate Transmit Framing RFSW 0 Normal Receive Framing 1 Alternate Receive Framing Figure 5 7 TFSW And RFSW Bits In SPORT Control Register Serial Ports Framing modes for receiving and transmitting data are independent If the receive frame sync width RFSW bit or transmit frame sync width TFSW bit in the SPORT control register is a 0 normal framing is enabled If the RFSW or TFSW bit is a 1 alternate framing is used The RFSW bit is bit 12 in the SPORT control register Ox3FF6 for SPORTO and 0x3FF2 for SPORT1 and the TFSW bit is bit 10 These bits are both cleared at reset so that normal framing in both directions is enabled For examples of normal and alternate framing see Configuration Examples later in this chapter 5 7 4 Active High Or Active Low Framing sync signals for receiving and transmitting data can be either active high or active low and are configured independently If the invert RFS INVRES bit or invert TFS INVTFS bit in the SPORT control register is a 0 the corresponding frame sync signal is active high If the INVRFS or INVTFS bit is a 1 these BUS PPR agIS ASG des These controls apply SPORT1 Control Register O0x3FF2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INVRFS 0 Active High RFS 1 Active Low RFS INVTFS O0 Active High TFS 1 Active Low TFS Figure 5 8 INVTFS And INVRFS Bits In SPORT Control Register regardless of the source of frame sync signals they either control the polarity of in
11. OXXX 0011 External Frame Sync OXXX 100X OXXX 0011 Both Internal Framing Option and External Framing Option Shown Figure 5 17 SPORT Continuous Transmit Normal Framing TFS OU ee ee TFS input XXXXXXXXAXXXXAXXXXK AAXKAAAAAX AX AX PY Cae a Ym TODE SPORT Control Register Internal Frame Sync OXXX 111X 0XXX 0011 External Frame Sync 0XXX 110X 0XXX 0011 Both Internal Framing Option and External Framing Option Shown Note There is an asynchronous delay between TFS input and DT See the appropriate data sheet for specifications Figure 5 18 SPORT Transmit Alternate F raming as N KRT a AEA ENA A AT a Ne ES OUTPUT TFS INPUT XXXXXXXXXXXXXXXXKXYKK XXXXXXXXXXXXXXAXXKXKAXA DT 83 82 X 81 X Bo X B3 Y B2 Y B y Bo SPORT Control Register Internal Frame Sync OXXX 111X 0XXX 0011 External Frame Sync 0XXX 110X 0XXX 0011 Both Internal Framing Option and External Framing Option Shown Note There is an asynchronous delay between TFS input and DT See the appropriate data sheet for specifications Figure 5 19 SPORT Continuous Transmit Alternate F raming Figures 5 14 and 5 15 show the receive operation with normal framing and alternate framing respectively in the unframed mode There is a single the frame sync signal that occurs only at the start of the first word either one SCLK before the first bit normal or at the same time as the first bit alternate This mode is appropriate for multiword bursts continuous re
12. Serial Ports Ci 5 5 1 OVERVIEW Synchronous serial ports or SPORTs support a variety of serial data communications protocols and can provide a direct interconnection between processors in a multiprocessor system These ADSP 2100 family processors contain serial ports Number of Processor Serial Ports ADSP 2101 2 ADSP 2105 1 ADSP 2115 2 ADSP 2111 2 ADSP 2171 2 ADSP 2181 2 ADSP 21msp58 59 2 The serial ports designated SPORTO and SPORT1 have some differences that are described in this chapter On the ADSP 2105 only SPORT1 is provided 5 2 BASIC SPORT DESCRIPTION Each SPORT has a five pin interface Pin Name Function SCLK Serial clock RFS Receive frame synchronization TFS Transmit frame synchronization DR Serial data receive DT Serial data transmit Table 5 1 SPORT External Interface A SPORT receives serial data on its DR input and transmits serial data on its DT output It can receive and transmit simultaneously for full duplex operation The data bits are synchronous to the serial clock SCLK which is an output if the processor generates this clock or an input if the clock is generated externally Frame synchronization signals RFS and TFS are used to indicate the start of a serial data word or stream of serial words Figure 5 1 shows a simplified block diagram of a single SPORT Data to be transmitted is written from an internal processor register to the SPORT s TX register via the DMD bus This data is optiona
13. a For example an internally generated RFS output could be connected to an externally generated TFS input on the same SPORT for simultaneous transmit and receive operations This interconnection is especially useful for combo codec interfaces 5 7 3 Normal And Alternate Framing M odes In the normal framing mode the framing signal is checked at the falling edge of SCLK If the framing signal is asserted received data is latched on the next falling edge of SCLK and transmitted data is driven on the next rising edge of SCLK The framing signal is not checked again until the word has been transmitted or received If data transmission or reception is continuous i e the last bit of one word is followed without a break by the first bit of the next word then the framing signal should occur in the same SCLK cycle as the last bit of each word In the alternate framing mode the framing signal should be asserted in the same SCLK cycle as the first bit of a word Received data bits are latched on the falling edge of SCLK and transmitted bits are driven on the rising edge of SCLK but the framing signal is checked only on the first bit Internally generated frame sync signals remain asserted for the length of the serial word Externally generated frame sync signals are only checked during the first bit time SPORTO Control Register Ox3FF6 SPORT1 Control Register O0x3FF2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TFSW 0 Normal Transmit Framing
14. and The Receive Register j Do The Autobuffer Transfer Continue Main Program lt Figure 5 37 Receive Companding E xample Autobuffering only consumes the cycles necessary to perform the data transfer no additional cycles are lost fetching instructions The above diagram assumes that all instructions and data transfers occur in one Request gt SPORTO Receive Request gt SPORT1 Receive CLKOUT AAN A AS A AS aes EXEC B c AUTOBUFFER AUTOBUFFER D COMPAND EXPAND RXO EXPAND RX1 Sync Delay gt Expand RX0 lt _ ______ Expand RX1 lt ______ RXO Autobuffer Transfer lt _ ___ _ _ RX1 Autobuffer Transfer a Continue Main Program a Figure 5 38 Receive Companding E xample With Both Serial Ports processor cycle 5 13 9 Receive Companding Latency In addition to the cycles used for synchronization there are some additional delays possible due to receive companding The synchronized request is used by the processor to decide when to write the receive CLKOUT a a e S nh ee cn EXEC _ AUTOBUFFER D FETCH INT INT Sync Delay NOP Instruction Fetch Vector Execute First Instruction Of Interrupt Routine lt Figure 5 39 Autobuffering Interrupt Example 5 41 register with the expanded value This can only occur on instruction cycle boundaries and only one receive register can be expanded at a time On the ADSP 2100 family processors that ha
15. as the I register must be initialized to zero so that the circular buffer capability is not active For example IO 0x3FF2 MO 1 LO 0 DM I0 M0O 0x6B27 the constant 0x6B27 is written to address pointed to by 10 pointer then modified by MO DM I0O MO 0 address 0x3FF3 is set to 0 Either method works The second method requires only one cycle to configure the registers once the I M and L registers are initialized This method is however more prone to error because the registers are written indirectly You must make sure that the I register contains the intended value before the write 5 3 2 Receiving And Transmitting Data Each SPORT has a receive register and a transmit register These registers are not memory mapped but are identified by assembler mnemonics The transmit registers are named TXO and TX1 for SPORTO and SPORT1 respectively Receive registers are named RX0 and RX1 for SPORTO and SPORT1 respectively These registers can be accessed at any time during program execution using a data memory access with immediate address load of a non data register with immediate data or register to register move instruction types 3 7 and 17 For example the following instruction would ready SPORT1 to transmit a serial value assuming SPORT1 is configured and enabled TX1 AX0O the contents of AXO are transmitted on SPORT1 The following instruction would access a serial value received on SPORTO AYO
16. ated as an asynchronous system to the processor even if the processor is providing the serial clock Internal to the processor is a circuit which synchronizes the autobuffer or interrupt requests to the processor clock Figure 5 34 shows the synchronization delay for the serial ports assuming the setup and hold times are met for the current processor cycle The setup and hold times for the serial port requests are the same as shown on the data sheet for the IRQ2 signal If the setup and hold times are not met there is an additional processor cycle of delay added As shown in Figure 5 34 there is a two processor cycle delay before the autobuffer or interrupt request is acted on by the processor The same latencies exist for all external interrupts The processor can only service interrupt or autobuffer requests on instruction cycle boundaries so there may be additional latency cycles added due to the completion of an instruction 5 13 7 Instruction Completion Latencies There are several situations which can cause an instruction to take more than one processor cycle Any of the following can delay the processor s ability to service a pending interrupt or autobuffer request External memory wait states Bus request when an external access is required in go mode Bus request with go mode disabled Multiple external accesses required for a single instruction Request gt exec Cm y gt nt Sync Delay gt NOP In
17. ceive them from an external source The sources for transmit frame syncs and receive frames syncs can be set independently If the internal receive frame sync IRFS bit or internal transmit frame sync ITFS bit in the SPORT control register is a 0 the processor expects to receive a signal SPORTO Control Register O0x3FF6 SPORT1 Control Register 0x3FF2 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 le IRFS 0 External RFS Input 1 Internal RFS Output ITFS 0 External TFS Input 1 Internal TFS Output Figure 5 6 ITFS And IRFS Bits In SPORT Control Register on its frame sync pin RFS or TFS If the IRFS or ITFS bit is a 1 the processor generates its own frame sync signal and drives the RFS or TFS pin as an output The IRFS bit is bit 8 in the SPORT control register Ox3FF6 for SPORTO and 0x3FF2 for SPORT1 and the ITFS bit is bit 9 Both of these bits are cleared at reset that is both serial ports require externally generated frame sync signals for both transmitting and receiving data If frame sync signals are generated externally then RFS and TFS are inputs and the external source controls data transmission and reception The SPORT will wait for a transmit frame sync before transmitting data and for a receive frame sync before receiving data If frame sync signals are generated internally however then RFS and TFS are outputs and the processor controls the timing of data operations The SPORT outputs an internally gene
18. ception Bee tye Ne a Nee le as a Na el E a m VAAANAAAKAAAAAAAAAANAAAAAAAAMANAAAMAAANAAAAAAAAMAAAAAAAAAAAAAAAAAAAAANM SPORT Control Register Internal Frame Sync 0XXX 001X 0XXX 0011 External Frame Sync 0XXX 000X 0XXX 0011 Figure 5 20 SPORT Transmit Unframed M ode Normal Framing TFS WXXXXAAAAX XXX AAA AAAAAAAAAAAAAAAAAANAAAAAAAANAAAAAAAA AAAA SPORT Control Register Internal Frame Sync 0XXX 011X 0XXX 0011 External Frame Sync 0XXX 010X 0XXX 0011 Note There is an asynchronous delay between TFS input and DT See the appropriate data sheet for specifications Figure 5 21 SPORT Transmit U nframed M ode Alternate Framing Serial Ports 5 Figures 5 16 to 5 21 show framing for transmitting data and are very similar to Figures 5 10 to 5 15 In Figures 5 16 and 5 17 the normal framing mode is shown for noncontinuous data and continuous data Figures 5 18 and 5 19 show noncontinuous and continuous transmission in the alternate framing mode As with receive timing the TFS output meets the TFS input timing requirement Figures 5 20 and 5 21 show the transmit operation with normal framing and alternate framing respectively in the unframed mode There is a single the frame sync signal that occurs only at the start of the first word either one SCLK before the first bit normal or at the same time as the first bit alternate 5 10 COMPANDING AND DATA FORMAT Companding a contraction of COMpressing and exPANDing is the process of
19. ch serial word transfer The SPORTs have many ways of handling framing signals Transmit and receive framing are independent of each other All frame sync signals are sampled on the falling edge of the serial clock SCLK SPORTO Control Register 0x3FF6 SPORT1 Control Register Ox3FF2 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 S TFSR 0 Transmit Frame Sync Required 1st Word 1 Transmit Frame Sync Required Every Word RFSR 0 Receive Frame Sync Required 1st Word 1 Receive Frame Sync Required Every Word Figure 5 5 TFSR And RFSR Bits In SPORT Control Register Serial Ports 5 5 7 1 Frame Synchronization Word framing signals are optional If the receive frame sync required RFSR or transmit frame sync required TFSR bit in the SPORT control register is a 0 a frame sync signal is necessary to initiate communications but is ignored after the first bit is transferred Words are then transferred continuously unframed If the RFSR or TFSR bit is a 1 a frame sync signal is required at the start of every data word The RFSR bit is bit 13 in the SPORT control register Ox3FF6 for SPORTO and 0x3FF2 for SPORT1 and the TFSR bit is bit 11 These bits are both cleared at reset so that communication in both directions on both serial ports is unframed See Configuration Examples later in this chapter for examples of frame sync timing 5 7 2 Frame Sync Signal Source The processor can generate frame synchronization signals internally or re
20. clock signal The serial clock SCLK can be internally generated or received from an external source The ISCLK bit bit 14 in either the SPORTO or SPORT1 control register determines the SCLK source for the SPORT If this bit is a 1 the processor generates the SCLK signal if it is a 0 the processor expects to receive an external clock signal on SCLK At reset ISCLK is cleared so both serial ports are in the external clock mode When ISCLK is set internal generation of the SCLK signal begins on the next instruction cycle whether or not the corresponding SPORT is enabled SPORTO Control Register Ox3FF6 SPORT1 Control Register Ox3FF2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ISCLK 0 External Default 1 Internal Figure 5 3 ISCLK Bit In SPORT Control Register External serial clock frequencies may be as high as the processor s cycle rate up to a maximum of 13 824 MHz internal clock frequencies may be as high as one half the processor s clock rate The frequency of an internally generated clock is a function of the processor clock frequency as seen at the CLKOUT pin and the value of the 16 bit serial clock divide modulus register SCLKDIV Ox3FF5 for SPORTO and 0x3FF1 for SPORT1 CLKOUT frequency SCLK frequency 2 x SCLKDIV 1 Table 5 5 shows how some common SCLK frequencies correspond to values of SCLKDIV SCLKDIV SCLK Frequency 20479 300 Hz 5119 1200 Hz 639 9600 Hz 95 64 kHz 3 1 536 MHz
21. continued from previous page SPORTO inits Assumes a CLKIN of 12 288 MHz Internally generated SCLK will be 2 048 MHz and framing sync of 8 kHz AXO 255 DM Ox3FF4 AX0 RFSDIV 256 256 SCLKs between frame syncs 8 kHz framing AX0 2 DM 0x3FF5 AX0 SCLK 2 048 MHz AXO 0x6B27 DM Ox3FF6 AX0 internal SCLK RFS and TFS normal framing mu law companding 8 bit words SPORT ENABLE IFC Ox1E clear any extraneous SPORT interrupts ICNTL 0 interrupt nesting disabled AXO Ox1Cl1F both SPORTs enabled BWAIT and DM Ox3FFF AX0 PWAIT left as default IMASK Ox1E SPORT interrupts are enabled END SPORT INITIALIZATIONS Figure 5 9 Example SPORT Configuration Code 5 9 TIMING EXAMPLES This section contains examples of some combinations of the various framing options The timing diagrams show relationships between signals but are not scaled to show the actual timing parameters of the processor Consult the data sheet for actual timing parameters and values The examples assume a word length of four bits that is SLEN 3 Framing signals are active high that is INVRFS 0 and INVTFS 0 The value of the SPORT control register 0x3FF6 for SPORTO and 0x3FF2 for SPORT1 is shown for each example In these binary values 1 high 0 RFS output RFS put VA AXA AX XX XXX XX XXXXAXXAXX AX XAXAAX N DR O eE SPORT Control Register
22. e compressed to eight LSBs sign extended to the width of the transmit word before being written to the internal transmit register If the magnitude of the 16 bit value is greater than the 13 bit A law or 14 bit p law maximum the value is automatically compressed to the maximum positive or negative value 5 10 1 Companding Operation Example With hardware companding interfacing to a codec requires little additional programming effort See the codec hardware interfacing example in the last section of this chapter Here is a typical sequence of operations for transmitting companded data Write data to the TXn register The value in TXn is compressed The compressed value is written back to TXn After the frame sync signal has occurred if required TXn is written to the internal transmit register and the bits are sent MSB first As soon as the SPORT has started to send the second bit of the current word TXn can be written with the next word even though transmission of the first is not complete After the MSB has been transferred the SPORT generates the transmit interrupt to indicate that TXn is ready for the next data word If the framing signal is being provided externally the next word must be written to TXn early enough to allow for compression before the next framing signal arrives Here is a typical sequence of operations for receiving companded data Bits accumulate as received in the internal receive register When a comple
23. equency Ox3FF3 SPORTO autobuffer control register Ox3FF2 SPORT1 control register Flag output value Serial clock source Frame synchronization controls Companding mode Serial word length Ox3FF1 SPORT1 serial clock divide modulus determines frequency 0x3FFO SPORT1 receive frame sync divide modulus determines frequency Ox3FEF SPORT1 autobuffer control register not on ADSP 21msp58 59 SPORTO configuration registers are defined only on processors that have both SPORTO and SPORT1 Table 5 3 SPORT Configuration Registers There are two ways to initialize or to change values in SPORT configuration registers write a register to an immediate address instruction type 3 or write immediate data to an indirect address instruction type 2 With either method it is important to configure the serial port before enabling it The first method of programming configuration registers requires no setup of DAG registers but does require two instructions to perform the write For example AXO 0x6B27 DM Ox3FF2 AX0 the contents of AXO are written to the address 0x3FF2 AXO 0 DM 0x3FF3 AX0 the contents of AXO are written to address 0x3FF3 In the second method the DAG I index register must contain the data memory address of the configuration register to be written The modify M register which updates the I register after the write must also contain a valid value And the length L register that has the same number
24. g the pairing of I and M registers are the same as for other DAG operations the I and M registers must be in the same DAG numbered either 0 3 for DAG1 or 4 7 for DAG2 Consequently three bits identify the I register but only two bits are necessary to indicate the M register because the third bit MSB of the M register number must be the same as for the I register Likewise RIREG and RMREG indicate the numbers of the I and M registers respectively associated with the receive buffer The TBUF and RBUF bits enable transmit autobuffering and receive autobuffering respectively These bits are cleared to zeros at reset and after a reboot Consequently autobuffering in progress cannot continue through a reboot operation you must re enable autobuffering after a reboot 5 11 2 Autobuffering Example The code shown below is an example that sets up SPORT1 for autobuffering operation The code assumes that the processor is driven with a clock frequency of 12 288 MHz The SPORT will automatically transmit values from the circular buffer named tx_buffer It will receive values as they are sent to the SPORT and automatically transfer the data into the buffer named rx_buffer A transmit interrupt will be generated once all of the tx_buffer values have been transferred to TX1 but before the Serial Ports 5 last value has been loaded into the transmit shift register A receive interrupt will be generated once the rx_buffer has been completely filled
25. hey have the following priority which is the same as the SPORT interrupt priority Highest SPORTO Transmit SPORTO Receive SPORT1 Transmit Lowest SPORT1 Receive SPORTO Autobuffer Control Register Ox3FF3 SPORT1 Autobuffer Control Register Ox3FEF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EESE SP ee Se ee TIREG TMREG RIREG RMREG TBUF Transmit Autobuffering Enable RBUF Receive Autobuffering Enable Figure 5 23 SPORT Autobuffer Control Register In the worst case that all four autobuffer transfers are required at about the same time interrupt latency would increase by the time it takes for all the transfers to occur which is affected by wait states and bus request 5 11 1 Autobuffering Control Register In autobuffering mode an interrupt is generated when the modification of a specified I register in the DAG by the value in the specified M register in the DAG causes a modulus overflow pointer wraparound This means that the end of the buffer has been detected The autobuffering mode is enabled separately for receiving and transmitting by bits in the SPORT s autobuffer control register Ox3FF3 for SPORTO or 0x3FEF for SPORT1 shown in Figure 5 23 The I and M registers used for autobuffering are identified by fields in the autobuffer control register TIREG and TMREG are binary values that indicate the numbers of the I and M registers respectively associated with the transmit buffer The rules governin
26. hronization delay is two SCLK cycles There is additional delay if the previous data transmission has not TFS DT em y em X em X Wes emn j sek A A A REA Mao Interrupt or Autobuffer Request gt Figure 5 31 SPORT Interrupt or Autobuffer Timing Transmit 4 B it W ords No Companding completed the TX register cannot be loaded into the transmit shift register until the previous transmission is complete 5 13 4 Transmit Interrupt Timing Once the MSB has been transmitted the subsequent bits are transmitted on the rising edges of the SCLK The transmit interrupt or autobuffer request is generated internally on the falling edge of SCLK during the transmission of the second bit see Figure 5 31 below This timing gives the program time to load the TX register with the next data for continuous data transmission The transmit interrupt like any other interrupt must be synchronized to the processor clock Servicing is subject to the same latencies as other interrupts RFS DR KAYAK Bt ira ABT K emo ONNAN siea ETE e Nh gs Interrupt or Autobuffer Request gt Figure 5 32 SPORT Interrupt or Autobuffer Timing Receive 4 Bit W ords No Companding The transmit interrupt essentially means that it is all right to write a value to the TX register 5 13 5 Receive Interrupt Timing The receiver portion of the SPORT latches data on the DR pin on the falling edges of SCLK Receive interrupt timi
27. igh or low and its polarity is controlled by the INVTFS bit renamed INVTDV in this context If INVIDV is a 1 TDV is active low otherwise it is active high TDV can be used to enable additional buffer logic if required Figure 5 28 shows the start of a multichannel transfer As in earlier examples word length is four bits GLEN 3 and frame sync signals are active high Wichanefel frame delay MPD ions SCLK c VIBGP t purpose of illustration words 0 and 2 are selected for receiving and words 1 and 2 are selected for transmission Pires Jh Start Of Multichannel Transfer PRurddWokhdwda YomipiMteaWwdrd Modi Xn MeXndttiXnankl Mode X A K K XN with complete words represented in the waveforms instead of aon bits Receiving is active for all words and transmitting is active for XX A 0000 A A A pije The s only one geri PORT1 an suppo Itichannel o jor 5 33 34 Figure 5 29 Complete Multichannel Example 5 13 SPORT TIMING CONSIDERATIONS The SPORTs support full duplex operation and are normally interrupt driven That is whenever a SPORT transaction has completed the processor generates an internal interrupt Under most operating conditions the actual timing of the SPORT interrupts is not critical In some sophisticated DSP systems however it is important to know the timing of the interrupt relative to the operation of the serial port 5 13 1 Companding Delay Use of the companding circuit introduces latency in
28. l port data is continuous and the receiver and transmitter are working with the same frame signal the order of the transmit and receive autobuffer or interrupt operations may be affected by the latencies shown below in Figure 5 40 If the processor is free to handle the autobuffer requests in the order they are generated the receive autobuffer happens first and is then followed by the transmit autobuffer The order of these operations may change if the processor is not available to handle the requests due to any of the previously mentioned latencies In this case there are 1 serial clock cycles between the requests If the processor is subject to bus requests wait states or other latencies which are longer than 1 serial clock cycles both autobuffer operations may be held off Since the transmit autobuffer has a higher priority it s request will occur first Because of the priority of the autobuffer requests the use of a single I register more difficult or even impossible in some cases As long as there are no possible latency cases longer than the difference in the timing of the requests it is quite possible to use a single I register for serial port autobuffering
29. lly compressed in hardware then automatically transferred to the transmit shift register The bits in the shift register are shifted out on the SPORT s DT pin MSB first synchronous to the serial clock The receive portion of the SPORT accepts data from the DR pin synchronous to the serial clock When an entire word is received the data is optionally expanded then automatically transferred to the SPORT s RX register where it is available to the processor The following is a list of SPORT characteristics Many of the SPORT characteristics are configurable to allow flexibility in serial communication DMD Bus 16 a Companding TXn Hardware Transmit Data Register 16 Serial Control Internal Serial Clock Generator Transmit Shift Register Receive Shift Register v DT TFS SCLK t Y y Figure 5 1 Serial Port Block Diagram DR gt Bidirectional each SPORT has independent transmit and receive sections Double buffered each SPORT section both receive and transmit has a data register for transferring data words to and from other parts of the processor and a register for shifting data in or out The double buffering provides additional time to service the SPORT Clocking each SPORT can use an external serial clock or generate its own in a wide range of frequencies down to 0 Hz See Section 5 5 Word length each SPORT supports serial data word lengths from three
30. ng differs from transmit interrupt timing The receive interrupt or atitebttf er request occurs only after an entire word is RFS DR XXXXOXXMXXMXXXXMXX ers X eme X em Xeno NOONAN se A AAE ANN AT NAAN FE Interrupt or Autobuffer Request gt Figure 5 33 SPORT Interrupt or Autobuffer Timing Receive 4 Bit Words Companding E nabled ul I 37 received The interrupt request occurs on the rising edge of SCLK after a word is received see Figure 5 32 and indicates that new data in the RX register can be read Companding causes a delay in the same manner as for transmitting However the latency is transparent as the receive interrupt is generated after the expansion has taken place The LSB is received on the falling edge of SCLK One processor cycle elapses to allow synchronization to the processor clock One processor CLKOUT ee Processor Can Request Service The Request Here Setup Time lt _ Hold Time lt _ Figure 5 34 Synchronization of Autobuffer or Interrupt Request to Processor Clock cycle later the SPORT attempts to expand the data if companding is enabled and the other serial port is not using the companding circuitry Companding latencies as discussed above occur prior to generation of a receive interrupt Servicing the receive interrupt is subject to the same latencies as other interrupts 5 13 6 Interrupt amp Autobuffer Synchronization The serial ports are tre
31. pts are generated differently if autobuffering is enabled see Autobuffering later in this chapter 5 3 SPORT PROGRAMMING To the programmer the SPORT can be viewed as two functional sections The configuration section is a block of control registers mapped to data memory that the program must initialize before using the SPORTs The data section is a register file used to transmit and receive values through the SPORT 5 3 1 SPORT Configuration SPORT configuration is accomplished by setting bit and field values in configuration registers These registers are memory mapped in data memory space SPORTO configuration registers occupy locations 0x3FF3 to Ox3FFA SPORT1 configuration registers occupy locations 0x3FEF to Ox3FF2 The contents of these registers are summarized in Table 5 3 and in the register summary in Appendix E The effects of the various settings are described at length in the sections that follow Address Contents Ox3FFA SPORTO multichannel receive word enables 31 16 Ox3FF9 SPORTO multichannel receive word enables 15 0 Ox3FF8 SPORTO multichannel transmit word enables 31 16 Ox3FEF7 SPORTO0 multichannel transmit word enables 15 0 Ox3FF6 SPORTO control register Multichannel mode controls Serial clock source Frame synchronization controls Companding mode Serial word length Ox3FF5 SPORTO serial clock divide modulus determines frequency Ox3FF4 SPORTO receive frame sync divide modulus determines fr
32. r these individual data word transfers The autobuffer transfer cannot be duplicated by any instruction However an equivalent assembly language instruction would be DM I M RXO or Equivalent Instructions Only TXO DM I M The I and M registers used in the transfer are selected by fields in the SPORT s autobuffer control register The processor waits for the current instruction to finish before inserting the overhead cycle A delay in the autobuffer transfer occurs if the transfer is required during an instruction executing in multiple cycles for wait states for example If the transfer is required when the processor is waiting in an IDLE state the transfer is executed and the processor returns to IDLE When a data word transfer causes the circular buffer pointer to wrap around the SPORT interrupt is generated The receive interrupt occurs after the complete buffer has been received The transmit interrupt occurs when the last word is loaded into TXn prior to transmission Aside from the completion of an instruction requiring multiple cycles the automatic transfer of individual data words has the highest priority of any operation short of RESET including all interrupts Thus it is possible for an autobuffer transfer to increase the latency of an interrupt response if the interrupt happens to coincide with the transfer Up to four autobuffered transfers can occur in the case that two or more are needed in the same cycle t
33. rated transmit framing signal after data is loaded into the transmit TXO or TX1 register at the time needed to ensure continuous data transmission after the last bit of the current word is transmitted the exact time depends on the framing mode being used see Normal and Alternate Framing Modes the next section The occurrence of the transmit frame sync is a result of the availability of data in the transmit register With an internally generated receive framing signal the processor controls the timing of the receive data The external data source must provide data to the serial port synchronized to the receive framing signal the timing depends on the framing mode being used see Normal and Alternate Framing Modes the next section The processor generates RFS periodically on a multiple of SCLK cycles based on the value of the 16 bit receive frame sync divide modulus register RFSDIV 0x3FF4 for SPORTO and 0x3FFO for SPORT1 Number of SCLK cycles between RFS assertions RFSDIV 1 For example to allow 256 SCLK cycles between RFS assertions set RESDIV to 255 OxFF Values of RFSDIV 1 that are less than the word length are not recommended Note that frame sync signals may be generated internally even when Serial Ports 5 SCLK is supplied externally This provides a way to divide external clocks for any purpose You can also use one frame sync to generate a single signal for both transmit and receive dat
34. rupt The latency depends on five factors the frequency of the serial clock whether or not companding is enabled whether or not there is contention for the companding circuit whether the current word has finished transmitting and the logic level of the SCLK TX Written SCLK High TX Written Processor Clock E MSB Transmitted MSB Transmitted Alternate Framing Normal Framing Serial Clock TFS OUTPUT Normal Framing TFS OUTPUT Alternate Framing TX Written SCLK Low TX Written Processor Clock MSB Transmitted MSB Transmitted Alternate Framing Normal Framing Serial Clock High Low High TFS OUTPUT Normal Framing TFS OUTPUT Alternate Framing Figure 5 30 Clock Synchronization 35 when the data value was loaded into the transmit register Note that if the transmit frame sync is generated externally data starts transmitting when a frame sync signal is received After the TX register is loaded it takes three complete phases of the serial clock HIGH LOW and HIGH in that order to ensure synchronization see Figure 5 30 Once synchronization has been ensured and a frame sync generated the most significant bit of the transmit word is shifted out on the same rising edge as the frame sync if alternate framing is used and on the rising edge of the next serial clock if normal framing is used Therefore the worst case sync
35. struction Fetch Vector Execute First Instruction Of Interrupt Routine Figure 5 35 Interrupt Service E xample e A pending higher priority autobuffer or interrupt request e Interrupt being masked On instruction cycle boundaries the processor will service multiple pending interrupt or autobuffer requests in the following priority order Request gt CLKOUT af ee Nl a w a EXEC B AUTOBUFFER c Y Sync Delay gt Do The Autobuffer Transfer Continue Main Program Figure 5 36 Autobuffer Service E xample 5 39 SPORTO transmit autobuffer highest priority not on ADSP 2105 SPORTO receive autobuffer not on ADSP 2105 SPORT1 transmit autobuffer SPORT1 receive autobuffer Unmasked pending interrupts in priority order 5 13 8 Interrupt amp Autobuffer Service Example Figure 5 35 shows the execution of a serial port interrupt based on a request that meets the setup and hold time requirements This example is the same for a receive or a transmit interrupt request An additional latency cycle is consumed due to the fetching of the first instruction of the interrupt routine The interrupt can only be serviced on an instruction cycle boundary The above example in Figure 5 35 assumes all instructions are completed in one processor cycle Figure 5 36 shows the result of an autobuffer request that meets the setup and hold requirements Request gt CLKOUT EXEC Sync Delay Exp
36. te word is received it is written to RXn The value in RXn is expanded The expanded value is written back to RXn The receive interrupt for that SPORT is then generated 5 10 2 Contention For Companding Hardware Since both SPORTs share the companding hardware only one compression and one expansion operation can take place during a single machine cycle If contention arises such as when two expansions need to occur in the same cycle SPORTO has priority while SPORT1 is forced to wait one cycle The effects of contention however are usually small The instruction set does not support loading both TX0 and TX1 in the same cycle consequently these operations will be naturally out of phase for contention in many cases The overhead cycle for the receive operation occurs prior to the receive interrupt and does not increase the time needed to service the interrupt although it does affect the latency prior to receiving the interrupt 5 10 3 Companding Internal Data Because the values in the RX and TX registers are actually companded in place it is possible to use the companding hardware internally without any transmission or reception at all and without enabling the serial port This operation can be used for debugging or data conversion and requires a single cycle of overhead To compress data enable companding and then 1 Write data to TXn compression is calculated 2 Wait for one cycle TXn is written with compressed value
37. ternally generated signals or determine how externally generated signals are interpreted The INVRFS bit is bit 6 in the SPORT control register Ox3FF6 for SPORTO and 0x3FF2 for SPORT1 and the INVTFS bit is bit 7 These bits are both cleared at reset so that frame sync signals are active high 5 8 CONFIGURATION EXAMPLE The example code that follows illustrates how to configure the SPORTs This example configures both SPORTO and SPORT1 SPORTO is configured for an internally generated serial clock SCLK internally generated frame synchronization and p law companded 8 bit data This is a typical setup for communication with a combo codec SPORT1 is configured for an externally generated serial clock externally generated frame synchronization non companded 16 bit data and autobuffering This setup could be used to transfer data between processors in a multiprocessor system Only the needed memory mapped registers are initialized Notice that the SPORTs are configured before they are enabled and that any extraneous latched interrupts are cleared before interrupts are enabled SPORT INITIALIZATION CODE SPORT1 inits AX0 0x0017 DM Ox3FEF AX0 enable SPORT1 autobuffering TX autobuffer uses I0 and M0 RX autobuffer uses Il and M1 AX0 0x280F DM Ox3FF2 AX0 external serial clock RFS and TES RFS and TFS are required normal framing no companding and 16 bits continued on next page
38. to sixteen bits See Section 5 6 Framing each SPORT section receive and transmit can operate with or without frame synchronization signals for each data word with internally generated or externally generated frame signals with active high or active low frame signals with either of two pulse widths and frame signal timing See Section 5 7 Companding in hardware each SPORT can perform A law and p law companding according to CCITT recommendation G 711 See Section 5 10 Autobuffering with single cycle overhead using the DAGs each SPORT can automatically receive and or transmit an entire circular buffer of data with an overhead of only one cycle per data word Transfers between the SPORT and the circular buffer are automatic in this mode and do not require additional programming See Section 5 11 Interrupts each SPORT section receive and transmit generates an interrupt upon completing a data word transfer or after transferring an entire buffer if autobuffering is used See Section 5 13 Multichannel capability SPORTO can receive and transmit data selectively from channels of a serial bitstream that is time division multiplexed into 24 or 32 channels This is especially useful for T1 interfaces or as a network communication scheme for multiple processors See Section 5 12 Note The ADSP 2105 has only one serial port SPORT1 and does not support multichannel operation Alternate configuration SPORT1 can be configured as two e
39. two ways First compressing or expanding a data value takes a single processor cycle Second SPORTO has priority over SPORT1 if both require an expansion or compression operation in the same cycle in this case SPORT1 must wait one processor cycle See the section on companding earlier in this chapter for more details on companding 5 13 2 Clock Synchronization Delay Some SPORT timings depend on the processor clock Other timings depend on the serial clock SCLKO or SCLK1 These clocks are asynchronous There is a delay associated with synchronizing the serial clock to the processor clock whether the serial clock is internally or externally generated This delay is different for the transmit and receive interrupts as explained in the following sections 5 13 2 1 Startup Timing When a serial port is enabled by a write to the System Control Register it takes two SCLK cycles before it is actually enabled On the next third SCLK cycle the serial port becomes active looking for a frame sync 5 13 3 Internally Generarated Frame Sync Timing When internally generated frame syncs are used all that is necessary to transmit data from the programmer s point of view is to move the data into the appropriate TX register with an instruction such as TXO AXO Once data is written into the TX register the processor generates a frame sync after a synchronization delay This delay in turn affects the timing of the serial port transmit inter
40. ultichannel mode of operation serial data is time division multiplexed Each subsequent word belongs to the next consecutive channel so that for example a 24 word block of data contains one word for each of 24 channels SPORTO supports 32 or 24 channels and can automatically select words for particular channels while ignoring the others SPORTO Control Register Multichannel Version Ox3FF6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D DESEE B MFD INVTDV Invert Transmit Data Valid Multichannel Frame Delay MCL Multichannel Length MCE 0 24 Words Multichannel Enable 1 32 Words 1 Multichannel Operation In single channel mode receive and transmit framing identifies the start of a single word or continuous stream with independent receive and transmit operation In the multichannel mode the receive frame sync signal RFSO identifies the start of a 24 or 32 word block of serial data with the receiver and transmitter operating in parallel TFSO has an alternate function described below Note The ADSP 2105 has only one serial port SPORT1 and does not support multichannel operation 5 12 1 Multichannel Setup Multichannel operation is enabled by bit 15 in SPORT0 s control register 0x3FF6 When this bit is a 1 multichannel mode is enabled and some SCLK 9 8 7 6 5 4 3 2 1 First Bi irst Bit RFS MFD 9 RFS MFD 8 i RFS MFD 7 RFS MFD 6 ff RFS MFD 5 RFS MFD 1 tT RFS MFD 0
41. ve two serial ports i e all except the ADSP 2105 there is also a possibility of a delay due to the availability of the companding circuitry SPORTO has the higher priority When companding is enabled the autobuffer or interrupt request does not occur until the register has been expanded The next two diagrams show examples of autobuffering with companding and the latencies involved The following diagram shows the latency when there are two pending ecikr ds Nese Ne NAL La ye EN DR DT X BIT3 Y BIT2 X Bm x BITO BIT3 BIT2 BITO X pits pir2 Y Bm Y BITO BIT3 BIT2 BITO Y 42 Transmit Autobuffer Request Receive Autobuffer Request Figure 5 40 Using One Index Register for Transmit and Receive Autobuffer receive autobuffer requests with companding enabled 5 13 10 Interrupts With Autobuffering E nabled When autobuffering is enabled SPORT interrupts occur when the address modification done during the autobuffer operation causes a modulus wraparound The synchronization delay applies to this type of interrupt as well An example is shown below in Figure 5 39 5 13 11 Unusual Complications In most cases the serial port companding autobuffer and interrupt latencies are transparent to your application program When trying to use the same I register for more than one autobuffer channel it becomes important to make sure that the latencies do not effect the correct order of operations For example if the seria
42. xternal interrupt inputs TRQO and IRQ1 and the Flag In and Flag Out signals instead of as a serial port The internally generated serial clock may still be used in this configuration See Section 5 4 5 2 1 Interrupts Each SPORT has a receive interrupt and a transmit interrupt The priority of these interrupts is shown in Table 5 2 Highest SPORTO Transmit on 2 SPORT processors SPORTO Receive on 2 SPORT processors SPORT1 Transmit Lowest SPORTI Receive Table 5 2 SPORT Interrupt Priorities For complete details about how interrupts are handled see the Interrupts section in Chapter 3 Program Control 5 2 2 SPORT Operation Writing to a SPORT s TX register readies the SPORT for transmission the TFS signal initiates the transmission of serial data Once transmission has begun each value written to the TX register is transferred to the internal transmit shift register and subsequently the bits are sent MSB first Each bit is shifted out on the rising edge of SCLK After the first bit MSB of a word has been transferred the SPORT generates the transmit interrupt The TX register is now available for the next data word even though the transmission of the first word is ongoing In the receiving section bits accumulate as they are received in an internal receive register When a complete word has been received it is written to the RX register and the receive interrupt for that SPORT is generated Interru
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