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Arria V SoC Development Kit User Guide

1. RYAN 101 Innovation Drive San Jose CA 95134 www altera com UG 01147 1 2 Arria V SoC Development Kit User Guide P Feedback Subscribe 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services 150 9001 2008 Registered September 2015 Altera Corporation Arria V SoC Development Kit User Guide RYN Contents Chapter 1 About This Kit Kit Features Eterna Erase e a vd opido 1 1 dcs atone 1 1 Inspect the Boa
2. Ls The development kit includes an application called the Board Test System BTS and related design examples The BTS provides an easy to use interface to alter functional settings and observe the results You can use the BTS to test board components modify functional parameters observe performance and measure power usage While using the BTS you reconfigure the FPGA several times with test designs specific to the functionality you are testing To install the BTS follow the steps in Installing the Development Kit on page 2 3 The Board Test System GUI communicates over the JTAG bus to a test design running in the Arria V device Figure 5 1 shows the initial GUI for a board that is in the factory configuration Look for yellow highlights in the board picture around the corresponding components for each tab Figure 5 1 Board Test System Graphical User Interface Board Test System Configure Help About Detected the GPIO Project Board Name Arria V SoC Development Kit Rev B Board P N 6XX 44209R Serial number SASTSoC000066 Factory test version 13 0 1 0 MAC1 00 07 ed 27 00 8a 2 00 07 ed 27 00 8b HPS MAC 00 07 ed 27 00 8c MAX V ver 3 IUSB BlasterII on localhost USB 1 1 SOCVHPS 1 SASTFD3 G3 K3 SASTFD5G3 2 5 12702 324 22102 2210 3 September 2015 Altera Corporation Arria V SoC Development Kit User Guide 5 2 Chapter
3. 1 MSELO m ON up MSELO is 0 ON m OFF down MSELO is 1 Switch 2 has the following options 2 MSEL1 m ON MSEL1 is 0 ON m OFF down MSEL1 is 1 September 2015 Altera Corporation Arria V SoC Development Kit User Guide 3 4 Chapter 3 Board Setup and Defaults Factory Default Switch and Jumper Settings Table 3 2 SW3 DIP Switch Settings Part 2 of 2 Default Position Board Switch Label Function Switch 3 has the following options 3 MSEL2 m ON up MSEL2 is 0 ON m OFF down MSEL2 is 1 Switch 4 has the following options 4 MSEL3 m ON up 5 3 is 0 ON m OFF down MSEL3 is 1 Switch 5 has the following options 5 MSEL4 m ON up MSEL4 is 0 ON m OFF down MSELA is 1 3 Set the DIP switch bank SW4 to match Table 3 3 and Figure 3 1 In the following table up and down indicates the position of the switch with the board orientation as shown in Figure 3 1 Table 3 3 SW4 JTAG DIP Switch Settings Default Position Board Switch Label Function 1 HPS m ON up Do not Include HPS in the JTAG chain OFF m OFF down Include HPS in the JTAG chain ON Do not Include the FPGA in the JTAG OFF down Include the FPGA in the JTAG chain ON up Do not include the FMCA connector in the JTAG chain 3 FMCA ON OFF down Include the FMCA connector in the JTAG chain m ON up Do not include the MAX V syste
4. Converting Sof to pol nc lt 26 04 rex epp ese Se toe erroe A gti aed A 3 Quad SPI Flash Memory i eek eter dies dere ie edd TI ER CREE IEEE ey de A 4 Programming Quad SPI Flash using the Quartus II Programmer 4 SD Card i sepe eere pr e Pace Deer eae A 4 The SD Card Default HPS Boot Source 00 0 c ccc n A 4 Additional Information Document Revision History esses ee bh e dure ded de ele RE e gie ee a gines Info 1 How to Contact Altera er ore HERE der ac Bh dece dd eae b esce des Info 1 Typographic Conventions essc eee premere het e ERR HIR WERE HY KE CPC RR ee ecto Info 1 Arria V SoC Development Kit September 2015 Altera Corporation User Guide N DTE SYN 1 About This Kit The Altera Arria V system on a chip SoC Development Kit is a complete design environment that includes both the hardware and software you need to develop Arria V SoC designs Kit Features This section briefly describes the kit contents For a complete list of this kit s contents and capabilities refer to the Arria V SoC Development Kit page The Arria V SoC Development Kit includes the following hardware development board A development platform that allows you to develop and prototype hardware designs running on the Arria V SoC St For detailed information about the board components and interfaces refer to
5. eee neqae CPP PURA ep rend 5 3 Board Information CP REP 5 4 TAG ena bees ke RE bree e Vie treats Ve ad vate Ca 5 4 i Re EDI RAIE ER D e M ED COM EC EC 5 5 Character LCD e p diserte eh 5 5 User DIP Switch 5 5 User LEDs e oie 5 6 Push Switches eda pew RIGeeEka puc ER CR EE CERE Pe 5 6 ei ascidian cab ened ceed eee 5 6 EEPROM 5 7 REC 4 v3 seed e ie top bee ANS 5 7 The DDR3 A and DDR3 B Tabs 0 I n 5 8 Stall M C 5 8 sop 5 8 Performance Indicators eritre a shee vee ie Peed Ove ob he She 5 8 Error Control 2s cess POI OO MU ER ides Piece aches E ARS 5 9 Number of Addresses to Write and Read 5 9 The XCVR Libre ot tiie dak elena Rie tdi ae cea Sees dete eee 5 10 SPA aos Ese pere hips baut vee eet Varii 5 10 The ces eA RR PLU D UtURP od eed oe kd aed Y dr b ees 5 12 September 2015 Alte
6. orientation as shown in Figure 3 1 Table 3 1 SW2 DIP Switch Settings Board Default Switch Label Function Position Switch 1 has the following options 1 CLK125A m ON 0 On board oscillator is disabled OFF m OFF 1 On board oscillator is enabled Switch 2 has the following options m ON 0 On board programmable oscillator is 2 51570 enabled ON OFF 1 On board programmable oscillator is disabled Switch 3 has the following options m ON 0 Load the user design from flash at 3 FACT LOAD power up OFF m OFF 1 Load the user factory from flash at power up Switch 4 has the following options m ON 0 On Board USB Blaster I sends 4 Security FACTORY command at power up OFF m OFF 1 On Board USB Blaster does not send FACTORY command at power up 2 Set the DIP switch bank SW3 to match Table 3 2 and Figure 3 1 In the following table up and down indicates the position of the switch with the board orientation as shown in Figure 3 1 Important The default MSEL pin settings are set to all zeroes ON to select the fast passive parallel x16 mode For power up configuration from MAX V and CFI flash ensure that the MAX V design uses this same mode as does in the design in the install dir NkitsNarriaVST 5astfd5kf40es socNexamples maxs5 directory Table 3 2 SW3 DIP Switch Settings Part 1 of 2 Switch ed Function Switch 1 has the following options
7. 5 Board Test System Preparing the Board for the Board Test System Several designs are provided to test the major board features Each design provides data for one or more tabs in the application The Configure menu identifies the appropriate design to download to the FPGA for each tab After successful FPGA configuration the appropriate tab appears that allows you to exercise the related board features The Power Monitor button starts the Power Monitor application that measures and reports current power information for the board Because the application communicates over the JTAG bus to the MAX II device you can measure the power of any design in the FPGA including your own designs 7 The Board Test System and Power Monitor share the JTAG bus with other applications like the Nios II debugger and the SignalTap II Embedded Logic Analyzer Because the Quartus II programmer uses most of the bandwidth of the JTAG bus other applications using the JTAG bus might time out Be sure to close the other applications before attempting to reconfigure the FPGA using the Quartus II Programmer Preparing the Board for the Board Test System With the power to the board off follow these steps 1 Plug the included USB cable from J50 USB Blaster II interface to the host computer s USB port 2 Ensure that the development board switches and jumpers are set to the default positions as shown in the Factory Default Switch and Jumper Settings
8. 6 Total Power 43 48mW Stop Update Speed M r Arria V SoC Development Kit User Guide The following sections describe the Power Monitor controls U46 U60 U50 The three groups show the power rail graphs from the three LTC2977 power monitors on the board U46 HPS Power Monitor September 2015 Altera Corporation Chapter 5 Board Test System 5 17 The Clock Control U60 FPGA Power Monitor 1 U50 FPGA Power Monitor 2 They display the mA power consumption of your board over time The green line indicates the current value The red line indicates the maximum value read since the last reset You can enlarge a graph by clicking on it Click it again to restore the original size Temp on 2977 The temperature controls display only the temperature from the power supply manager not the FPGA Total Power These controls display the sum of all four rails for each group U34 and for U26 Controls This group contains the following controls m Start Starts the communication with the board to monitor power m Stop Stops the communication with the board to monitor power m Update speed Specifies how often to refresh the graph Log Results Specifies that a log file is saved to lt install dir gt kits arriaVST_5astfd5kf40es_soc examples board_test_system m MAX version Indicates the version of MAX V code currently running on the board The MAX V code resides in the lt install dir gt kits arria
9. Bridge interfaces As a part of the Altera SoC EDS the ARM 05 5 Altera Edition Toolkit provides a comprehensive set of embedded development tools for Altera SoCs ARM Development Studio 5 DS 5 Altera Edition Toolkit AINAN GOC DOL Complete information about the development board Manual Development Board Daughtercards Additional daughter cards available for purchase Documentation Arria V Devices Arria V device documentation Devices Purchase devices from the eStore Capture CIS Symbols Arria V OrCAD symbols Embedded Processing Nios 11 32 bit embedded processor solutions Arria V SoC Development Kit September 2015 Altera Corporation User Guide 2 Software Installation This chapter explains how to install the following software m Quartus II Subscription Edition Software optional m Altera SoC Embedded Development Suite EDS m Arria V SoC Development Kit software m On Board USB Blaster II driver If you do not need to develop FPGA designs you do not need to download the Quartus software For example when you only want to write software for the SoC HPS Installing the SoC EDS software along with USB II Blaster drivers provides a development kit JTAG programming environment About the Quartus II Software Your kit includes a license for the Development Kit Edition DKE of the Quartus II software Windows platform only For one year this license entitles you
10. Clock Control 51570 tab Figure 5 10 The Clock Control Clock Control m zl x ANU S 1570 x1 sis71 5 5338 1 r Serial port registers HS DIV 5 a Target frequency MHz 100 00 MHz RFREQ 02bc00ea16 Valid frequency range values are fXTAL 114 2851 MHz 10 00000000 to 810 00000000 MHz Messages Connected to the target The following sections describe the 51570 tab controls Serial Port Registers The Serial port registers control shows the current values from the Si570 registers fXTAL The fXTAL control shows the calculated internal fixed frequency crystal based on the serial port register values For more information about the fyrar value and how it is calculated refer to the 51570 51571 data sheet available on the Silicon Labs website ww w silabs com Target Frequency The Target frequency control allows you to specify the frequency of the clock Legal values are between 10 and 810 MHz with eight digits of precision to the right of the decimal point For example 421 31259873 is possible within 100 parts per million ppm The Target frequency control works in conjunction with the Set New Frequency control Arria V SoC Development Kit September 2015 Altera Corporation User Guide Chapter 5 Board Test System 5 19 Configuring the FPGA Using the Quartus II Programmer Default This control sets the frequency for the oscillator associated with the active
11. switch bank SW4 selects which interfaces are in the chain Refer to Table 3 3 on page 3 4 for detailed settings For details on the JTAG chain refer to the Arria V SoC Development Board Reference Manual For USB Blaster II configuration details refer to the On Board USB Blaster II page Arria V SoC Development Kit September 2015 Altera Corporation User Guide Chapter 5 Board Test System 5 5 Using the Board Test System The GPIO Tab The GPIO tab allows you to interact with all the general purpose user I O components on your board You can write to the character LCD read DIP switch settings turn LEDs on or off and detect push button presses Figure 5 3 shows the GPIO tab Figure 5 3 The GPIO Tab Board Test System Configure Help About Detected the GPIO Project The following sections describe the controls on the GPIO tab Character LCD The Character LCD controls allow you to display text strings on the character LCD on your board Type text in the text boxes and then click Display 7 If you exceed the 16 character display limit on either line a warning message appears User DIP Switch The read only User DIP switch control displays the current positions of the switches in the user DIP switch bank Change the switches on the board to see the graphical display change accordingly September 2015 Altera Corporation Arria V SoC Development Kit User Guide 5 6 Chapter 5
12. to most of the features of the Subscription Edition excluding the IP Base Suite After the year your DKE license will no longer be valid and you will not be permitted to use this version of the Quartus II software To continue using the Quartus II software you should download the free Quartus II Web edition or purchase a subscription to Quartus II software For more information refer to the Design Software page of the Altera website The Quartus II Development Kit Edition DKE software includes the following items m Quartus Software The Quartus II software including the Qsys system integration tool provides a comprehensive environment for network on a chip NoC design The Quartus II software integrates into nearly any design environment and provides interfaces to industry standard EDA tools m MegaCore IP Library A library that contains Altera IP MegaCore functions You can evaluate MegaCore functions by using the OpenCore Plus feature to do the following m Simulate behavior of a MegaCore function within your system m Verify functionality of your design and quickly and easily evaluate its size and speed m Generate time limited device programming files for designs that include MegaCore functions m Program a device and verify your design in hardware gt The OpenCore Plus hardware evaluation feature is an evaluation tool for prototyping only You must purchase a license to use a MegaCore function in productio
13. to the Factory Defaults on page 3 6 m Corrected steps in Converting sof to pof on page A 3 Corrected J39 BOOTSEL SHORT pins 1 2 Updated Activating Your License section in Chapter 2 December 2013 1 0 Initial release September 2015 1 2 June 2014 11 How to Contact Altera To locate the most up to date information about Altera products refer to the following table Contact 7 Contact Method Address Technical support Website www altera com support T Website www altera com training Technical training Email custrain altera com Product literature Website www altera com literature Nontechnical support general Email nacomp altera com software licensing Email authorization altera com Note to Table 1 You can also contact your local Altera sales office or sales representative Typographic Conventions The following table shows the typographic conventions this document uses Visual Cue Meaning Indicate command names dialog box titles dialog box options and other GUI Bold Typa with Capital labels For example Save As dialog box For GUI elements capitalization matches Letters the GUI Indicates directory names project names disk drive names file names file name bold type extensions software utility names and GUI labels For example qdesigns directory D drive and chiptrip gdf file Italic Type with Initial Capital L
14. using the Nios II EDS just as the hardware design was created using the Quartus II software CFI Flash Memory CFI Flash Memory Map CAUTION Table A 1 shows the default memory contents of the 512 Mb CFI flash device For the Board Update Portal to run correctly and update designs in the user memory this memory map must not be altered Table A 1 Byte Address Flash Memory Map Block Description KB Size Address Range Unused 20316 0x02CA 0000 OxO3FF FFFF User hardware 1 23330 0x0166 0000 0x02C9 FFFF Factory hardware GHRD 23330 0x0002 0000 0x0165 FFFF PFL option bits 32 0x0001 8000 0x00019FFF Reset vector 96 0x0000 0000 0001 7FFFF Altera recommends that you do not overwrite the factory hardware images unless you are an expert with Altera tools If you unintentionally overwrite the factory hardware or factory software image refer to Restoring the CFI Flash Device to the Factory Defaults on page 3 6 Programming CFI Flash Using the Quartus Il Programmer You can use the JTAG interface in Altera CPLDs to indirectly program the flash memory device The Altera CPLD JTAG block interfaces directly with the logic array in a special JTAG mode This mode brings the JTAG chain through the logic array instead of the Altera CPLD boundary scan cells BSC The PFL megafunction provides JTAG interface logic to do the following September 2015 Altera Corporation Arria V SoC Development Kit User Guide A
15. 2 Arria V SoC Development Kit User Guide Appendix A Programming Flash Memory CFI Flash Memory m Convert the JTAG stream provided by the Quartus II software m Program the CFI flash memory devices connected to the CPLD I O pins Figure A 1 shows an Altera CPLD configured as a bridge to program the CFI flash memory device through the JTAG interface Figure A 1 Programming the CFI Flash Memory With the JTAG Interface MAX II CPLD Altera Quartus Configuration Data FPGA Sofware 7 yO 77 gt via JTAG CREME 2 Altera FPGA Not Used Flash for Flash Programming Interface CFI Flash Memory Perform the following steps to program a user design to the flash device in the Quartus II Programmer The following flash writing procedure blinks the SEL 2 1 and 0 LEDs and does not support the Power Monitor Clock Control or other logic functions It should only be used for configuration 1 On the Tools menu in the Quartus II software click Programmer 2 In the Programmer window click Auto Detect 7 Ifyou do not see USB Blaster or the board s embedded USB Blaster II listed next to Hardware Setup refer to the Installing the USB Blaster II Driver on page 2 4 3 Click Change File and open install dir gt kits arriaVST_5astfd5kf40es_soc factory_recovery max2_PFL_writer pof 4 Turn on the Program Configure option for the pof file 5 Click Start to download the
16. Board Test System Using the Board Test System User LEDs This control displays the current state of the user LEDs Click the graphical representation of the LEDs to turn the board LEDs on and off You can click ALL to turn on and off all of the user LEDs at once Push Button Switches The read only Push Button switches control displays the current state of the board user push buttons Press a push button on the board to see the graphical display change accordingly The 126 Tab The I2C tab allows you to read and write 1 kilobit Kb to an EEPROM located at U28 on the development board Figure 5 4 shows the I2C tab Figure 5 4 The 126 Tab Board Test System Configure Help About 0000 0000 01000000 00000000 41727269 61205620 0000 0010 536F4320 44657665 6C6F706D 656E7420 0000 0020 4B697420 52657620 4200FFFF FFFFFFFF 0000 0030 FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF 0000 0040 FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF 0000 0050 FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF 0000 0060 FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF 0000 0070 FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF i RTC time 2013 11 06 11 04 00 Systemtime 2013 11 06 11 04 02 Detected the GPIO Project The following sections describe the controls on the I2C tab Arria V SoC Development Kit September 2015 Altera Corporation User Guide Chapter 5 Board Test System 5 7 Using the Boar
17. VST_5astfd5kf40es_soc factory_recovery and install dir gt kits arriaVST_5astfd5kf40es_soc examples max5 directories 57 Newer revisions of this code might be available on the Arria V SoC Development Kit page of the Altera website A table with the power rail information is available in the Arria V SoC Development Board Reference Manual The Clock Control The Clock Control application sets the 51570 X2 51571 X3 or 515338 031 programmable oscillators to any frequency between 10 MHz and 810 MHz The frequencies support eight digits of precision to the right of the decimal point The Clock Control application runs as a stand alone application ClockControl exe resides in the install dir NkitsNarriaVST 5astfd5kf40es socNexamplesVboard test system directory To start the application click Start gt All Programs gt Altera gt SoC Development Kit lt version gt gt Clock Control September 2015 Altera Corporation Arria V SoC Development Kit User Guide 5 18 Chapter 5 Board Test System The Clock Control St For more information about the programmable oscillators and the Arria V development board s clocking circuitry and clock input pins refer to the Arria V SoC Development Board Reference Manual The Clock Control communicates with the MAX V device on the board through the JTAG bus The programmable oscillators are connected to the MAX V device through a 2 wire serial bus Figure 5 10 shows the
18. asures and reports current power information To start the application click Power Monitor in the Board Test System application You can also run the Power Monitor as a stand alone application PowerMonitor exe resides in the lt install dir gt kits arriaVST_5astfd5kf40es_soc examples board_test_system directory In Windows click Start gt All Programs gt Altera gt Arria V SoC Development Kit lt version gt gt Power Monitor to start the application The Power Monitor communicates with the MAX V device on the board through the JTAG bus A power monitor circuit attached to the MAX V device allows you to measure the power that the Arria V FPGA is consuming Figure 5 9 shows the Power Monitor Figure 5 9 The Power Monitor 5 2977 Monitor ANOTE RYA U50 0 5 1 1V HPS 1149 90mV 1 5V HPS 1500 00mV 2 5V HPS 2500 12mV 3 3 HPS 3300 17mV Temp on 2977 Messages 28 41C Ioj xl U64 0 5 U54 0x62 800mA 100mA 100mA 389 160mA 2 5V FPGA 13 733mA 1 15V GXB 25 228mA 2500 12mV 1157 10mV 100mA 100mA 100mA 55 827mA 1 5V_FPGA 2482mA 1 15V VCCT 9 089 1500 00mV 1156 13mV 800mA 400mA 100mA 392 090mA 11 242432mA 1 5 VCCD 2 523mA 1150 88mV 1497 44mV 100mA 100mA 100mA 20 935mA VAR VCCIO 10 117mA 0 000mA 2532 837mA 0 00mV Temp on 2977 33 75C 2977 33 69C Total Power 1580 60mW Connected to the target Total Power 342 69mW Controls MAX Ver
19. ations DVD Request Form page of the Altera website Start the Arria V SoC Development Kit installer exe for Windows or unzip the installation image for Linux Choosean installation directory that is relative to the Quartus II software installation directory Follow the on screen instructions to complete the installation process For the latest issues and release notes Altera recommends that you review the readme txt located in the root directory of the kit installation September 2015 Altera Corporation Arria V SoC Development Kit User Guide 2 4 Chapter 2 Software Installation Installing the USB Blaster II Driver The installation program creates the Arria V SoC Development Kit directory structure shown in Figure 2 1 Figure 2 1 Arria V SoC Development Kit Installed Directory Structure lt install dir gt The default Windows installation directory is C altera lt version gt kits arriaVST 5astfd5kf40es soc far board design files demos f documents C examples __ factory_recovery Note to Figure 2 1 1 Early release versions might have slightly different directory names Table 2 1 lists the file directory names and a description of their contents Table 2 1 Installed Directory Contents Directory Name Description of Contents Contains schematic layout assembly and bill of material board design files Use these files as a hoard design fles starting point for a new prot
20. ays the data rate frequency in MHz which is equivalent to MBps m Bits Displays the number of bits transmitted since clicking Start m Inserted errors Displays the number of errors inserted by clicking Insert Error button Arria V SoC Development Kit September 2015 Altera Corporation User Guide Chapter 5 Board Test System 5 15 Using the Board Test System m Detected errors Displays the number of bit errors detected by the error checking circuitry BER Displays the bit error rate of the interface PLL lock Displays Yes if the SDI PLL is locked Pattern sync Displays Yes if the receiver has detected the input data pattern Start Starts the PRBS data test and begins to monitor and update screen with live test results Stop Stops the PRBS data test Insert Error Inserts an error into an SDI data stream that is detected by the receiver when in loopback using the included video cable m Clear Clears the Detected errors counter m PMA Setting Opens the PMA settings window that allows for adjusting the analog transceiver settings such as output voltage loopback settings and equalization m PRBS list 5elects the transmit pattern and sets the receive error detection circuitry to expect the same pattern for use in loopback testing September 2015 Altera Corporation Arria V SoC Development Kit User Guide 5 16 Chapter 5 Board Test System The Power Monitor The Power Monitor The Power Monitor me
21. card installed on the FMC connector for this test to work correctly The following sections describe the controls on the FMC A tab XCVR 106 and CMOS m Data rate Displays the current XCVR 106 or CMOS data rate in megabytes per second MBps m Freq Displays the data rate frequency in MHz which is equivalent to MBps m Bits Displays the number of bits transmitted since clicking Start m Inserted errors Displays the number of errors inserted by clicking Insert Error button Arria V SoC Development Kit September 2015 Altera Corporation User Guide Chapter 5 Board Test System 5 13 Using the Board Test System m Detected errors Displays the number of bit errors detected by the error checking circuitry BER Displays the bit error rate of the interface PLL lock Displays Yes if the SDI PLL is locked Pattern sync Displays Yes if the receiver has detected the input data pattern Start Starts the PRBS data test and begins to monitor and update screen with live test results Stop Stops the PRBS data test Insert Error Inserts an error into an SDI data stream that is detected by the receiver when in loopback using the included video cable m Clear Clears the Detected errors counter m PMA Setting Opens the PMA settings window that allows for adjusting the analog transceiver settings such as output voltage loopback settings and equalization m PRBS list 5elects the transmit pattern and sets t
22. d Test System EEPROM The serial DC EEPROM is 32 Kilobits m Start Address O0x0 m Range 0x1000 m Read Reads data from the 2 EEPROM St For more information on the EEPROM refer to the Arria V SoC Development Board Reference Manual RTC Real time clock m RTC Time Displays current time stored in RTC memory when you click Read It is not updated automatically System Time Displays current time from PC and is updated automatically m Read Reads the time from the RTC device on the board m Write System Time to RTC Writes the time to the RTC device on the board September 2015 Altera Corporation Arria V SoC Development Kit User Guide 5 8 Chapter 5 Board Test System Using the Board Test System The DDR3 A and DDR3 B Tabs These tabs allow you to read and write the DDR3 memory on your board Figure 5 5 shows the DDR3 A tab which has the same controls has the DDRS B tab Figure 5 5 The DDR3 A Tab Board Test System Configure Help About Write MBps 1636 805 Read MBps 1955 405 Total MBps 3592 210 Error control Detected errors 0 Inserted errors 0 cen Number of addresses to write and read 7 268435456 Detected DDR3 Project The following sections describe the controls on the DDR3 A tab Start The Start control initiates DDR3 memory transaction performance analysis Stop The Stop control terminates transaction perfo
23. design function properly September 2015 Altera Corporation Arria V SoC Development Kit User Guide 3 2 Chapter 3 Board Setup and Defaults Factory Default Switch and Jumper Settings The SD card Max V system controller and CFI flash are already programmed with the factory default files For more information refer to Appendix A Programming Flash Memory Figure 3 1 Switch Locations and Default Settings J3 FMCB FMCB_JTAG_EN o 5 SECURITY gt FACT LOAD 51570 CLK125A 01234 SW Arria V SoC FMC VAR um 12V um 15V mm 18V J7 ma 257 M m an J6 LMK OSC SEL 9 3210 3210 hu FPGA HPS Swa 5 Pose 2524 19 HPS SEL JTAG Jg ser Not a jumper J23 Not a jumper JTAG MIC SEL mm J28 Not a jumper Ji J37 J38 J39 J40 J41 CSELO CSEL1 BSELO BSEL1 BSEL2 1 571 01 6 7 01 0 oe jum CLK OSC2 J45 J46 SEL SELO Arria V SoC Development Kit User Guide September 2015 Altera Corporation Chapter 3 Board Setup and Defaults Factory Default Switch and Jumper Settings To restore the switches to their factory default settings perform these steps 1 Set the DIP switch bank SW2 to match Table 3 1 and Figure 3 1 In the following table ON indicates the switch is to the left according to the board
24. e list of items when the sequence of the items is not important c The hand points to information that requires special attention 2 The question mark directs you to a software help system with related information uc The feet direct you to another document or website with related information The multimedia icon directs you to a related multimedia presentation CAUTION A caution calls attention to a condition or possible situation that can damage or destroy the product or your work WARNING A warning calls attention to a condition or possible situation that can cause you injury The envelope links to the Email Subscription Management Center page of the Altera website where you can sign up to receive update notifications for Altera documents The feedback icon allows you to submit feedback to Altera about the document Methods for collecting feedback vary as appropriate for each document A Electromagnetic interference caused by modification of the kit contents is the sole responsibility of the user CAUTION Arria V SoC Development Kit User Guide September 2015 Altera Corporation Additional Information ae Typographic Conventions This equipment is designated for use only in an industrial research environment September 2015 Altera Corporation Arria V SoC Development Kit User Guide Mid Additional Information Typographic Conventions Arria V SoC Development Kit September 2015 Al
25. e transmitter buffer m First post Specifies the amount of pre emphasis on the first post tap of the transmitter buffer m Second post Specifies the amount of pre emphasis on the second post tap of the transmitter buffer m Equalizer Specifies the setting for the receiver equalizer DC gain Specifies the DC portion of the receiver equalizer m PRBS Selects the transmit pattern and sets the receive error detection circuitry to expect the same pattern for use in loopback testing September 2015 Altera Corporation Arria V SoC Development Kit User Guide 5 12 Chapter 5 Board Test System Using the Board Test System The FMC A Tab The FMC A tab allows you to perform loopback tests on the FMC A port Figure 5 7 shows the FMC A tab Figure 5 7 The FMC A Tab Board Test System Configure Help About System info cero 122 0 XEVA start stop rXCVR 106 cem apg Scie Start Stop Freq 10241 04MHz bits 2 762459 11 Inserted errors 0 Status Detected 0 PLL lock Yes __PMA Setting errors Pattern Yi a sme Yes 5 CMOS Data rate 200 00MBps Start Stop Freq 50 00MHz bits 4 299653e 09 1 Detected 0 PLL lock Yes Setting errors 000000e 00 Pattern sync Yes BER 0 Pres7 z Detected FMC Project 7 For factory testing you must have an FMC loopback
26. e when the progress bar reaches 100 6 Click Auto Detect and a flash device should show up attached to the MAX V in the main window 7 On the right click menu of the flash device click Change File 8 Select the flash image pof file install dir gt kits arriaVST_5astfd5kf40es_soc factory_recovery a5soc_one_page pof 9 Once the flash image pof is attached in the Quartus II Programmer turn on Page_0 and Option Bits 10 Click Start 11 After the flash writing process has completed power cycle the board and look for the MAX CONF DONE LED to turn ON if successful 12 Altera recommends that you return to the Max V System Controller factory design after completing the flash writing To do so program the Max V with the factory design file install dir gt kits arriaVST_5astfd5kf40es_soc factory_recovery max lt version gt pof For more information refer to Restoring the MAX V CPLD to the Factory Settings on page 3 6 57 The flash writer version blinks the SEL 1 and 0 LEDs and does not support the Power Monitor Clock Control or other logic functions It should only be used for configuration St Toensure that you have the most up to date factory restore files and information about this product refer to the Arria V SoC Development Kit page of the Altera website September 2015 Altera Corporation Arria V SoC Development Kit User Guide 3 8 Chapter 3 Board Setup and Defaults Restoring the CFI Flash Device
27. ed but without Ethernet access If you receive the No IP obtained message Altera recommends that you install the USB virtual COM port drivers to access the Linux system through a terminal window St For more information refer to the Configuring Serial Connection section of the Linux Getting Started page on RocketBoards org 57 There are several reasons why your board may fail to get and IP address in this step m Your port is not active or the cable is not plugged in You do not have a DHCP server Your DHCP server ran out of addresses a Your DHCP server was not allowed to respond to the board due to security filters such as MAC address filtering September 2015 Altera Corporation Arria V SoC Development Kit User Guide 4 2 Chapter 4 Board Update Portal Connecting to the Board Update Portal Web Page 4 Launch a web browser on a PC that is connected to the same network and enter the IP address from the LCD into the browser address bar The Board Update Portal web page appears in the browser gt You can click Arria V SoC Development Kit on the Board Update Portal web page to access the kit s home page for documentation updates and additional new designs Ma You can also navigate directly to the Arria V SoC Development Kit page of the Altera website to determine if you have the latest kit software Arria V SoC Development Kit September 2015 Altera Corporation User Guide N 5 Board Test System
28. esign that corresponds to the GPIO tab gt Under two conditions the BTS displays a message prompting you to configure your board with a valid BTS design m If you power up your board with the DIP switch SW2 3 in a position other than the on 0 position m If you load your own design into the FPGA with the Quartus Programmer Using the Board Test System This section describes each control in the BTS The Configure Menu Use the Configure menu to select the design you want to use Each design example on this menu tests different board features that corresponds to one or more application tabs For example if you select Configure with GPIO Design the System Info GPIO and I2C tabs become available for testing The BTS configuration circuit might cause a conflict with the default HPS booting sequence Both events program the FPGA To make sure the operation of the Configure menu works properly wait until you see the LCD display Hello Tim before you use the Configure menu CAUTION Figure 5 2 The Configure Menu Configure Help About Configure with GPIO Design Configure with DDR3 Design Configure with SFP SMA Design Configure with FMC Design The System Info Tab The System Info tab shows board s current configuration Figure 5 1 on page 5 1 shows the System Info tab The tab displays the contents of the MAX V registers the JTAG chain the board s MAC address the flash memory map and other details st
29. etters Indicate document titles For example Stratix IV Design Guidelines September 2015 Altera Corporation Arria V SoC Development Kit User Guide Info 2 Additional Information Typographic Conventions Visual Cue Meaning Indicates variables For example n 1 italic type Variable names are enclosed in angle brackets For example file name and project gt file Initial Capital Letters Indicate keyboard keys and menu names For example the Delete key and the Options menu Subheading Title Quotation marks indicate references to sections in a document and titles of Quartus Help topics For example Typographic Conventions Courier type Indicates signal port register bit block and primitive names For example data1 tdi and input The suffix n denotes an active low signal For example resetn Indicates command line commands and anything that must be typed exactly as it appears For example c qdesigns tutorial chiptrip gdf Also indicates sections of an actual file such as a Report File references to parts of files for example the AHDL keyword SUBDESIGN and logic function names for example TRI An angled arrow instructs you to press the Enter key 1 2 3 and Numbered steps indicate a list of items when the sequence of the items is important a b c and so on such as the steps listed in a procedure Bullets indicat
30. f the Quartus II software To continue using the Quartus II software you should download the free Quartus II Web Edition or purchase a subscription to Quartus II software Before using the Quartus II software you must activate your license identify specific users and computers and obtain and install a license file If you already have a licensed version of the subscription edition you can use that license file with this kit If not follow these steps 1 Log on at the myAltera Account Sign In web page and click Sign In 2 Onthe myAltera Home web page click the Self Service Licensing Center link 3 Locate the serial number printed on the side of the development kit box below the bottom bar code The number consists of alphanumeric characters and does not contain hyphens for example 5xxxSoCxxxxxxx 4 OntheSelf Service Licensing Center web page click the Find it with your License Activation Code link 5 In the Find Activate Products dialog box enter your development kit serial number and click Search 6 When your product appears turn on the check box next to the product name Arria V SoC Development Kit September 2015 Altera Corporation User Guide Chapter 2 Software Installation 2 3 Installing the Altera SoC Embedded Development Suite EDS 7 Click Activate Selected Products and click Close 8 When licensing is complete Altera emails a license dat file to you Store the file on your computer and use the L
31. figured with the default settings follow the instructions in Factory Default Switch and Jumper Settings on page 3 1 to return the board to its factory settings before proceeding The development board ships with the Golden System Reference Design binaries stored in the microSD card The microSD card also includes the following m Hardware reference design FPGA image Raw Binary File rbf file m HPS image preloader U Boot and Linux images m Filesystem and software examples 2 Power up the development board by using the included laptop power supply plugged into the board A Use only the supplied power supply Power regulation circuitry on the board can be damaged by power supplies with greater voltage and a lower rated power supply may not be able to provide enough power for the board Alternatively you can use the an ATX power from a PC by plugging a 4 pin output from that supply to J33 on the development board Make sure that the ATX supply is off when connecting to the board Hot swap is not supported and may damage the board s power supplies and other downstream devices CAUTION When configuration is complete the Config Done LED D38 illuminates signaling that the Arria V device configured successfully Factory Default Switch and Jumper Settings This section shows the factory settings Figure 3 1 for the Arria V SoC development board These settings ensure that the Board Update Portal and Golden System Reference
32. g Start m Inserted errors Displays the number of errors inserted by clicking Insert Error button Detected errors Displays the number of bit errors detected by the error checking circuitry BER Displays the bit error rate of the interface PLL lock Displays Yes if the SDI PLL is locked m Pattern sync Displays Yes if the receiver has detected the input data pattern m Start Starts the PRBS data test and begins to monitor and update screen with live test results m Stop Stops the PRBS data test Insert Error Inserts an error into a data stream that is detected by the receiver when in loopback using the included video cable With the Insert Error there are differences among the three ports SFP A Inserts 4 errors at 1 click due to 4 test blocks control SFP B Inserts 3 errors at 1 click due to 3 test blocks control SMA Inserts 1 error at 1 click m Clear Clears the Detected errors counter PMA Setting Opens the PMA settings window that allows for adjusting the analog transceiver settings such as output voltage loopback settings and equalization The following settings are available for analysis m Serial Loopback Routes the selected TX output signal back to the RX input signal on chip to verify operation without using an external loopback board m VOD Specifies the voltage output differential of the transmitter buffer m Pre emphasis tap m Pre Specifies the amount of pre emphasis on the pre tap of th
33. hange File and select the appropriate file install dir NkitsNarriaVST 5astfd5kf40es recovery max lt no_ver gt pof 5 Turn on the Program Configure option for the added file 6 Click Start to download the selected configuration file to the MAX V CPLD Configuration is complete when the progress bar reaches 100 St Toensurethat you have the most up to date factory restore files and product information refer to the Arria V SoC Development Kit page of the Altera website Restoring the CFI Flash Device to the Factory Defaults To program the factory image to the flash device in the Quartus II Programmer do the following steps 1 On the Tools menu in the Quartus II software click Programmer 2 In the Programmer window click Auto Detect Arria V SoC Development Kit September 2015 Altera Corporation User Guide Chapter 3 Board Setup and Defaults 3 7 Restoring the CFI Flash Device to the Factory Defaults 7 If you do not see USB Blaster the board s embedded USB Blaster II listed next to Hardware Setup refer to the Installing the USB Blaster II Driver on page 2 4 3 Click Change File and open the factory image file install dir gt kits arriaVST_5astfd5kf40es_soc factory_recovery max2_PFL_writer pof 4 Turn on the Program Configure option for the Programmer Object File pof file 5 Click Start to download the selected configuration file to the MAX V CPLD Configuration is complet
34. he receive error detection circuitry to expect the same pattern for use in loopback testing September 2015 Altera Corporation Arria V SoC Development Kit User Guide 5 14 Chapter 5 Board Test System Using the Board Test System The FMC B Tab The FMC B tab allows you to perform loopback tests on the FMC B port Figure 5 8 shows the B tab Figure 5 8 The FMC B Tab Board Test System Configure Help About 106 Data 2560 24MBps __ so stat stop Freq 10241 04MHz bits 1 130331 11 Inserted errors 0 setting PLL lock Yes Detected errors 0 Pattern Yes BER 0 000000 00 Jrres7 mj FFMC 6G Data rate 1638 54MBps Start Stop Freq 6554 28MHz Insert Error Clear bits 6 046180 10 Inserted 0 errors il PLL lock Yes Detected errors Pattern sync Yes BER 0 000000 00 Pres7 m r CMOS Data rate 200 00MBps Freq 50 00MHz bits 5 959526e 09 Status Inserted errors 0 5 PLL lock Yes Setting anu Pattern sync Yes 57 Detected FMC Project 7 For factory testing you must have an FMC loopback card installed on the FMC connector for this test to work correctly The following sections describe the controls on the FMC tab 106 66 CMOS m Data rate Displays the current or CMOS data rate in megabytes per second MBps m Freq Displ
35. icense Setup page of the Options dialog box in the Quartus II software to enable the software To license the Quartus II software you need your computer s network interface card NIC ID anumber that uniquely identifies your computer On the computer you use to run the Quartus II software type ipconfig all ata command prompt to determine the NIC ID Your NIC ID is the 12 digit hexadecimal number on the Physical Address line For complete licensing details refer to the Altera Software Installation and Licensing Manual Installing the Altera 506 Embedded Development Suite EDS The Altera SoC EDS is a comprehensive tool suite for embedded software development on Altera SoC devices It contains development tools utility programs run time software and application examples to expedite firmware and application software of SoC embedded systems As a part of the Altera SoC EDS the ARM DS 5 Altera Edition Toolkit provides a comprehensive set of embedded development tools for Altera SoCs For more information refer to the ARM Development Studio 5 DS 5 Altera Edition Toolkit For the steps to install the SoC EDS Tool Suite refer to the Altera SoC Embedded Design Suite User Guide Installing the Development Kit Perform these steps 1 Download the Arria V SoC Development Kit installer from the Arria V SoC Development Kit page of the Altera website Alternatively you can request a development kit DVD from the Altera Kit Install
36. lash Memory Programming Quad SPI Flash using the Quartus Il Programmer Although the quad SPI flash is not programmed by factory default you can program this device using quartus hps exe that resides in the quartus bin directory To use this tool open a command window and change directories to your 13 0 or later installation e g c altera 13 1 quartus bin To program an entire file to quad SPI flash starting at address 0 type quartus hps exe c programming cable index o P flash boot image bin For help and more options type quartus hps exe help SD Card Memory The SD Card Default HPS Boot Source The SD card is the default boot source for the HPS as selected by the BSEL jumpers The socket is designed to accept micro SD cards This kit comes with a microSD card micro to standard SD card adapter and a USB programming adapter To program the SD card do the following steps 1 Insert the SD card into the USB Programming adapter and insert the programming adapter into a USB port on your PC 2 In Windows you should see a pop up window asking what you d like to do with the flash device Click Cancel but note the drive letter it is mounted as You cannot drag and drop files onto the SD card because the file system is different You need to use a disk image program or preferably use a Cygwin installation such as the NIOS II Embedded Development System Nios II EDS 3 Start the Nios II Command Shell by clicking Sta
37. m controller in the JTAG chain 4 MAX OFF down Include the MAX V system controller in the JTAG chain Arria V SoC Development Kit September 2015 Altera Corporation User Guide Chapter 3 Board Setup and Defaults 3 5 Factory Default Switch and Jumper Settings 4 Set the following jumper blocks to match Table 3 4 and Figure 3 1 Table 3 4 Default Jumper Settings Board ee Default Reference Board Label Description Position m SHORT is not in the JTAG chain J3 FMCB SHORT OPEN FMCB is in the JTAG chain Variable voltage m 9 10 1 2 V m 8 15V J6 FMC 3 4 2 5 V m 5 6 1 8V m 3 4 25V m 1 2 not valid m SHORT Select to use SMA J7 LMK OSC SEL OPEN m OPEN Select to use on board VCXO SHORT Controls the HPS from On Board USB Blaster JTAG master OPEN Controls the HPS from MICTOR based J19 JTAG HPS SEL JTAG master such as DSTREAM or Lauterbach SHORT programming cables Also sets SW4 1 to ON to remove the On Board USB Blaster II from driving the HPS JTAG input port in this mode m SHORT The USB Blaster II is the source of the JTAG chain J21 JTAG SEL SHORT m OPEN The Mictor is the source of the JTAG chain m SHORT JTAG TRST input to HPS driven from the JTAG chain J28 JTAG MIC SEL OPEN OPEN JTAG TRST input to HPS driven from the MICTOR J37 CLKSELO Selects the HPS clock settings 1 B pins J38 CLKSEL1 Selects the HPS clock se
38. n September 2015 Altera Corporation Arria V SoC Development Kit User Guide 2 2 Chapter 2 Software Installation Installing the Quartus 11 Subscription Edition Software For more information about OpenCore Plus refer to AN 320 OpenCore Plus Evaluation of Megafunctions Ta Nios II Embedded Design Suite EDS A full featured set of tools that allows you to develop embedded software for the Nios II processor which you can include in your Altera FPGA designs Installing the Quartus Il Subscription Edition Software Included in the Quartus II Subscription Edition Software are the Quartus II software including Osys the Nios II EDS and the MegaCore IP Library To install the Altera development tools perform the following steps 1 Download the Quartus II Subscription Edition Software from the Quartus II Subscription Edition Software page of the Altera website Alternatively you can request a DVD from the Altera IP and Software DVD Request Form page of the Altera website 2 Follow the on screen instructions to complete the installation process If you have difficulty installing the Quartus II software refer to the Altera Software Installation and Licensing Manual Activating Your License Purchasing this kit entitles you to a one year license for the Development Kit Edition DKE of the Quartus II software After the year your DKE license will no longer be valid and you will not be permitted to use this version o
39. n Click Change File and select the path to the desired sof Turn on the Program Configure option for the added file g e N Click Start to download the selected file to the FPGA Configuration is complete when the progress bar reaches 100 September 2015 Altera Corporation Arria V SoC Development Kit User Guide 5 20 Chapter 5 Board Test System Configuring the FPGA Using the Quartus II Programmer La Using the Quartus II Programmer to configure a device on the board causes other JTAG based applications such as the Board Test System and the Power Monitor to lose their connection to the board Restart those applications after configuration is complete Arria V SoC Development Kit September 2015 Altera Corporation User Guide RYN Programming Flash Memory Ls This appendix describes programming information for the following memory devices Common flash interface CFI flash memory m Quad serial peripheral interface quad SPI flash memory m SD card flash memory The Arria V development board s flash memory comes preconfigured with the parallel flash loader PFL option bits to support FPGA designs to be written to any of the three locations Table A 1 The PFL is disabled by default Set SW2 3 to ON to enable FPGA programming from CFI flash memory on power up There are several other factory software files written to flash memory to support the Board Update Portal These software files were created
40. o generate a flash programming file you must use the Quartus II software and convert sof files to pof files To convert the files follow these steps 1 On the File menu click Convert Programming Files For Programming file type specify Programmer Object File pof For Configuration device select CFI 512Mb Click Options Boot info For Option bit address 32 bit hexadecimal type 0x18000 and click OK For Mode select Passive Parallel x16 For File name type a location and filename for the pof to be generated Under Input files to Convert select SOF Data MN GN S Click Add File on the right browse to the sof file you want to convert and click Open 9 Under Input files to Convert select SOF data again 10 Click Properties on the right a Select the page number and start address according to the memory map in Byte Address Flash Memory Map on page 1 For example to program the sof to User hardware 1 m Under Pages turn on 1 The software sets Selected Pages Comment to Page 1 m For Address mode for selected pages select Start m For Start Address 32 bit hexadecimal type 0x01660000 the User hardware 1 offset address b Click OK 11 Click Generate The pof file is generated in the location you selected in step 6 September 2015 Altera Corporation Arria V SoC Development Kit User Guide A 4 Appendix A Programming Flash Memory Quad SPI Flash Memory Quad SPI F
41. ored on the board The following sections describe the controls on the System Info tab September 2015 Altera Corporation Arria V SoC Development Kit User Guide S Chapter 5 Board Test System Using the Board Test System Board Information The Board information controls display static information about your board Board Name Indicates the official name of the board m Part number Indicates the part number of the board Serial number Indicates the serial number of the board m Factory test version Indicates the version of the Board Test System currently running on the board m MAC1 Indicates the MAC address of the board s ENET1 10 100 port m MAC2 Indicates the MAC address of the board s ENET2 10 100 port m HPS MAC1 Indicates the MAC address of the board s HPS 10 100 1000 Ethernet port m MAX ver Indicates the version of MAX V code currently running on the board The MAX V code resides in the install dir NkitsNarriaVST 5astfd5kf40es socNexamples directory Newer revisions of this code might be available on the Arria V SoC Development Kit page of the Altera website JTAG Chain The JTAG chain control shows all the devices currently in the JTAG chain The Arria V device is always the first device in the chain The JTAG chain is normally mastered by the On board USB Blaster II If you plug in an external USB Blaster cable to the JTAG header J35 the On Board USB Blaster II is disabled JTAG DIP
42. otype board design demos Contains demonstration applications documents Contains the kit documentation examples Contains the sample design files for the Arria V SoC Development Kit Contains the original data programmed onto the board before shipment Use this data to restore factory_recovery the board with its original factory contents Installing the USB Blaster II Driver The Arria V development board includes integrated USB Blaster circuitry for FPGA programming However for the host computer and board to communicate you must install the On Board USB Blaster II driver on the host computer T Installation instructions for the On Board USB Blaster II driver for your operating system are available on the Altera website On the Altera Programming Cable Driver Information page of the Altera website locate the table entry for your configuration and click the link to access the instructions For USB Blaster II configuration details refer to the On Board USB Blaster II page Arria V SoC Development Kit September 2015 Altera Corporation User Guide N DERYN 3 Board Setup and Defaults This chapter explains how to set up the Arria V SoC development board and restore defaults Setting Up the Board To prepare the board perform these steps 1 The development board ships with its board switches preconfigured to support the design examples in the kit If you suspect your board might not be currently con
43. power consumption and thermal modeling to determine whether your application requires additional cooling For information about measuring board and FPGA power in real time refer to The Power Monitor on page 5 16 St For more information about power consumption and thermal modeling refer to AN 358 Thermal Management for FPGAs References Use the following links in Table 1 1 to check the Altera website for other related information Table 1 1 Related Links and Documents Altera Website Link Information Arria V SoC Development Kit page Latest board design files and reference designs Open source community website supporting SoC development including Altera and Partner SoC development kit targets and related designs and documentation ARM Cortex A SoC On the dual core ARM Cortex A9 MPCore processor Getting Started for Software Developers Developing software for the Arria V SoC SoC Development Kit Hardware Developer Developing SoC Hardware designs on the Resource Center development kit Includes information on the Installing the SoC EDS Altera SoC Embedded Design Suite User and ARM DS 5 Preloader user guide Hard Guide Processor System HPS Flash programmer Bare Metal and Linux Compiler Yocto plugin Debugging The Golden System Reference Design GSRD RocketBoards org GSRD User Manual page on demonstrates the HPS ability to communicate RocketBoards org between HPS to the FPGA logic via the AXI
44. ra Corporation Arria V SoC Development Kit User Guide iv Contents XCVRA0G and CMOS osse teu races eee 5 12 Ihe Tab ates Sade e EU RE EE E CE EUIS EE Y RR ee aa E Reena ae 5 14 FMC T10G FMC6G CMOS Xe e REESE Eu eX RA U SG Nee OW E REPAS E 5 14 The Power Monitor e RU RP HRS RR ER C eS 5 16 46 60 050 estote e b quA 5 16 Conttols eee e E ER E PIG EAR ER tee Rabe RE EE 5 17 The Clock Control sss sessed etd betas teeta Pees 5 17 Serial Port Registers denis died ee ee P 5 18 EXDAL torso he sete eek tros 5 18 Target Frequency eta dor eia qd bcd ae a ae ae 5 18 Default tee 5 19 Seb New Frequency suede AUI nin ease 5 19 Configuring the FPGA Using the Quartus 5 19 Before Cong urng os at seta 5 19 Configuring the FPGA sss esce ren Pew avert I Yess E Verse EY va 5 19 Appendix A Programming Flash Memory Flash Mem Ory EEE 1 CFI Flash Memory Map YE Re ue Va qd e eate Valdes A 1 Programming CFI Flash Using the Quartus Programmer A 1
45. ration Arria V SoC Development Kit User Guide 5 10 Chapter 5 Board Test System Using the Board Test System The XCVR Tab The XCVR tab allows you to perform loopback tests on the SFP A SFP B and SMA ports Figure 5 6 shows the XCVR tab Figure 5 6 The XCRV Tab Board Test System Configure Help About Data rate 1250 00MBps Freq 10000 08MHz bits 5 287439e 10 Inserted errors 0 Detected errors 0 BER 0 000000e 00 SFPB Data rate 1250 00MBps Freq 10000 08MHz bits 5 299939e 10 Inserted errors 0 Detected errors 0 BER 0 000000e 00 gt SMA Data rate 1250 00MBps Freq 10000 08MHz bits 5 312439e 10 Inserted errors 0 Detected errors 0 BER 0 000000e 00 7 To perform these tests you need Two SFP optical or metal loopback cables to test both at the same time m Two matching SMA cables for the SMA loopback The following sections describe the controls on the XCVR tab SFP A SFP B SMA These groups displays the following SFP A SFP B SMA status information during the loopback test m Data rate Displays the current SFP A SFP B SMA data rate in megabytes per second MBps m Freq Displays the data rate frequency in MHz which is equivalent to MBps Arria V SoC Development Kit September 2015 Altera Corporation User Guide Chapter 5 Board Test System Using the Board Test System 5 11 m bits Displays the number of bits transmitted since clickin
46. rds i cese yes eth veh hi eee tad OU he Ve eden we sae pe si 1 1 References kissd eee bk ee GO Ree ERR ees G GERE ERE GGG eS Poe eee eee es 1 2 Chapter 2 Software Installation About the Quartus Software herr ra 2 1 Installing the Quartus II Subscription Edition Software 2 2 2 Activating Your License ae tala ee Sl de Roe oe Sedo es 2 2 Installing the Altera SoC Embedded Development Suite EDS 2 3 Installing the Development Kit II n 2 3 Installing the USB Blaster Driver oeeo 0 0 6 eee ees 2 4 Chapter 3 Board Setup and Defaults Up the Board ccce eee eene ep Per Pte deiecta e oth dee 3 1 Factory Default Switch and Jumper Settings 2 3 1 Restoring the MAX V CPLD to the Factory Settings 3 6 Restoring the CFI Flash Device to the Factory Defaults 00 c cece eee eee eee 3 6 Chapter 4 Board Update Portal Connecting to the Board Update Portal Web Page 0 00 4 1 Chapter 5 Board Test System Preparing the Board for the Board Test System 5 2 Running the Board Test System releg nnn nnn 5 2 Using the Board Test System 2 eee nnn 5 3 The Contisure eee esce e ee E 5 3 The System Info tese kem E eae ERA E RETRO
47. rmance analysis Performance Indicators These controls display current transaction performance analysis information collected since you last clicked Start m Write Read and Total performance bars Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve Arria V SoC Development Kit September 2015 Altera Corporation User Guide Chapter 5 Board Test System 5 9 Using the Board Test System m Write MBps Read MBps and Total MBps Show the number of bytes of data analyzed per second The data bus is 72 bits wide and the frequency is 400 MHz double data rate 800 Mbps per pin equating to a theoretical maximum bandwidth of 3200 Megabits per second or 400 MBps Error Control This control displays data errors detected during analysis and allows you to insert errors Detected errors Displays the number of data errors detected in the hardware m Inserted errors Displays the number of errors inserted into the transaction stream Insert Error Inserts a one word error into the transaction stream each time you click the button Insert Error is only enabled during transaction performance analysis m Clear Resets the Detected errors and Inserted errors counters to zeros Number of Addresses to Write and Read The Number of addresses to write and read control determines the number of addresses to use in each iteration of reads and writes September 2015 Altera Corpo
48. rt gt All Programs gt Altera version Nios II EDS Nios II Command Shell 4 Atthis shell type the command 1s dev enter The SD card will generally be mounted as sda sdb or sdc etc depending on other devices that may be present To be sure which is correct remove the card and type 1s dev enter Look for what changed since you type the command the first time Re insert the SD card and verify the name once more TW soy Uo Type dd if boot image filename img of dev sd card name enter Linux users use the same dd commands 7 Be careful using this programming command as it will overwrite whatever is found on the device pointed to in the of command Arria V SoC Development Kit September 2015 Altera Corporation User Guide Appendix A Programming Flash Memory A 5 SD Card Memory For more information refer to the Altera SoC Embedded Design Suite User Guide and RocketBoards org September 2015 Altera Corporation Arria V SoC Development Kit User Guide A 6 Appendix A Programming Flash Memory SD Card Memory Arria V SoC Development Kit September 2015 Altera Corporation User Guide S BAAN Additional Information This chapter provides additional information about the document and Altera Document Revision History The following table shows the revision history for this document Date Version Changes Corrected steps in Restoring the CFI Flash Device
49. section starting on page 3 1 3 Set the DIP switch SW2 3 to the user on 0 position Sz For more information about the board s DIP switch and jumper settings refer to the Arria V SoC Development Board Reference Manual 4 Turn on the power to the board The board loads the design stored in the user hardware 1 portion of flash memory into the FPGA If your board is still in the factory configuration or if you have downloaded a newer version of the Board Test System to flash memory through the Board Update Portal the design loads the GPIO SRAM and flash memory tests To ensure operating stability keep the USB cable connected and the board powered on when running the demonstration application The application cannot run correctly unless the USB cable is attached and the board is on CAUTION Running the Board Test System Navigate to the lt install dir gt kits arriaVST_5astfd5kf40es_soc examples board_test_system directory and run the BoardTestSystem exe application 57 Torun the BTS in Windows you can also click Start gt All Programs gt Altera gt Arria V SoC Development Kit version Board Test System Arria V SoC Development Kit September 2015 Altera Corporation User Guide Chapter 5 Board Test System 5 3 Using the Board Test System A GUI appears displaying the application tab that corresponds to the design running in the FPGA The Arria V development board s flash memory ships preconfigured with the d
50. selected configuration file to the MAX V CPLD Configuration is complete when the progress bar reaches 100 6 Click Auto Detect and a flash device should show up attached to the MAX V in the main window 7 Double click the graphic of the flash device in the device chain pane to display the Device s Properties dialog box 8 Select the flash image pof file generated from the Quartus II Convert Programming Files dialog box The default file name is output_file pof 9 After the flash image pof is attached in the Quartus II Programmer turn on Page 1 and Option Bits Page 0 is reserved for the GSRD factory design September 2015 Altera Corporation Appendix A Programming Flash Memory A 3 CFI Flash Memory 10 Click Start 11 After the flash writing process has completed power cycle the board and look for the MAX CONF DONE LED to turn ON if the writing process is successful 12 Altera recommends that you return to the Max V System Controller factory design after completing the flash writing To do so program the Max V with lt install dir gt kits arriaVST_5astfd5kf40es_soc factory_recovery max lt version gt pof For more information refer to Restoring the MAX V CPLD to the Factory Settings on page 3 6 Te For more information on programming flash memory refer to Parallel Flash Loader Megafunction User Guide and Using FPGA Based Parallel Flash Loader with the Quartus II Software Converting sof to pof T
51. tab back to its default value This can also be accomplished by power cycling the board Set New Frequency The Set New Frequency control sets the programmable oscillator frequency for the selected clock to the value in the Target frequency control for the programmable oscillators Frequency changes might take several milliseconds to take effect You might see glitches on the clock during this time Altera recommends resetting the FPGA logic after changing frequencies For more information about these programmable oscillators refer to the data sheets available on the Silicon Labs website www silabs com Configuring the FPGA Using the Quartus Il Programmer You can use the Quartus Programmer to configure the FPGA with your SRAM Object File sof file Before Configuring Ensure the following m The Quartus II Programmer and the USB Blaster II driver are installed on the host computer m The USB cable is connected to the development board Power to the board is on and no other applications that use the JTAG chain are running If the Quartus II Programmer window is already open and you power cycle the board to detect the JTAG chain do the following m Click Hardware Setup in the Quartus II Programmer window m Reselect USB Blaster II in order to properly detect the JTAG chain Configuring the FPGA Perform these steps 1 Start the Quartus II Programmer Click Auto Detect to display the devices in the JTAG chai
52. tera Corporation User Guide
53. the Arria V SoC Development Board Reference Manual MicroSD flash memory card Loopback FPGA mezzanine card FMC daughter card Power supply and cables The kit includes the following items Power supply and AC adapters for North America Japan Europe and the United Kingdom m One micro USB and two mini USB cables m Ethernet cable Before You Begin Before using the kit or installing the software check the kit contents and inspect the boards to verify that you received all of the items listed in Quick Start Guide printout in the box If any of the items are missing contact Altera before you proceed Inspect the Boards To inspect each board perform these steps 1 Place the board on an anti static surface and inspect it to ensure that it has not been damaged during shipment A Without proper anti static handling you can damage the board CAUTION Verify that all components on the boards appear in place and intact September 2015 Altera Corporation Arria V SoC Development Kit User Guide 1 2 Chapter 1 About This Kit Before You Begin a Insmaller applications with the Arria V development board a heat sink is not necessary However under extreme conditions or for engineering sample silicon the board might require additional cooling to stay within operating temperature guidelines The board has two holes near the FPGA that accommodate many different heat sinks including the Dynatron V31G You can perform
54. to the Factory Defaults Arria V SoC Development Kit September 2015 Altera Corporation User Guide RYN 4 Board Update Portal The Board Update Portal web page provides links to useful information on the Altera website You can use this web page to interact with your board m Blinking LEDs m Writing text messages to the LCD Mouse over the board photo to view features The Board Update Portal web page is served by the web server application running on the HPS on your board Connecting to the Board Update Portal Web Page Ensure that you have the following items are setup or installed m APC witha connection to a working Ethernet port on a DHCP enabled network A separate working Ethernet port connected to the same network for the board m The Ethernet and power cables that are included in the kit To connect to the Board Update Portal web page perform these steps 1 Ensure that the CSEL and BSEL jumpers Table 3 4 on page 3 5 and the DIP switch SW2 3 Table 3 1 on page 3 3 are in the factory default positions 2 Attach the Ethernet cable to the HPS Ethernet connector on the upper left of the board to your LAN 3 Power up the board The board connects to the LAN s gateway router and obtains an IP address and displays it to the LCD If no IP address is obtained the LCD displays No IP obtained If the system booted the LCD displays Hello Tim If the LCD displays No IP obtained your system partially boot
55. ttings p pins J39 BOOTSELO Selects the boot mode and source for the HPS 1 pins J40 BOOTSEL1 Selects the boot mode and source for the HPS 1 p ping J41 BOOTSEL2 Selects the boot mode and source for the HPS 1 Bins September 2015 Altera Corporation Arria V SoC Development Kit User Guide 3 6 Chapter 3 Board Setup and Defaults Restoring the MAX V CPLD to the Factory Settings Table 3 4 Default Jumper Settings Continued Board Default Reference Board Label Description Position 00 SHORT SHORT Selects the on board 25MHz clock 01 SHORT OPEN Selects SMA 145 46 osc2 cu SHORT m 10 OPEN SHORT Selects the on board SHORT 33MHz clock m 11 OPEN OPEN none Note to Table 3 4 1 For more information refer to the Arria V Device Handbook For more information about the FPGA board settings refer to the Arria V SoC Development Board Reference Manual Restoring the MAX V CPLD to the Factory Settings This section describes how to restore the original factory contents to the MAX V CPLD on the development board Make sure you have the Nios II EDS installed and then perform these steps 1 Set the board switches to the factory default settings described in Factory Default Switch and Jumper Settings on page 3 1 57 DIP switch SW4 4 includes the MAX V device in the JTAG chain 2 Launch the Quartus II Programmer 3 Click Auto Detect 4 Click C

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