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BAB-40/60 - ELTEC Elektronik AG

1. Table 9 Pin Assignment of BGB X201 Pin Row A Row B Row C Row D Row E 1 GND A08 A16 A24 TDO 2 A01 A09 A17 A25 TMS1 3 A02 A10 A18 A26 TCK 4 A03 A11 A19 A27 TRST 5 04 12 20 28 008 6 05 13 21 29 009 7 A06 A14 A22 A30 D10 8 A07 A15 A23 A31 D11 9 D16 D24 64kHz SIZEO D12 10 D17 D25 FC1 SIZE1 D13 11 D18 D26 FC2 5V D14 12 D19 D27 LIRQ1 GND D15 13 D20 D28 CSKBD 12V DOO 14 D21 D29 RESET 12V 15 022 030 2kHz 12VGND 002 16 D23 D31 BCLK3 DSACKO 17 DS GND HALT 004 18 AS 45V 45V D05 19 DSACK1 GND ISPEN GND D06 20 BERR 16MHz CSGRAF TDI 007 1 2 19 20 Hardware Manual 19 1 Specification Table 10 Pin Assignment of BEB X222 Pin Signal Pin Signal Pin Signal Pin Signal 1 12V 26 BGACK 51 Reserved 76 BGBEB 2 A0 27 2 52 5V 77 BERR 3 28 53 031 78 RESET 4 4 29 54 029 79 CSBEBO 5 A6 30 DSACK1 55 D27 80 SIZEO 6 A8 31 GND 56 D25 81 FCO 7 A10 32 DO 57 D23 82 5V 8 A12 33 D2 5
2. 0 0 0 0 D 00 0 6 6 0 6 0 6 6 6 0 6 0 6 0 9o 0 90 8 e Oro is O 009 25 O 6666 6 Q tf b b D 5 0 x1102 ae LY O 75 Yo 0 0 9 RR QA OK 1101 52255252 524525 5950505 5259595 5050505 5259595 5050505 125222522 201 705 701 J703 1 11605 15500000009 a E 5 8000000090 000 000 5 o 0 5902 0 o 0 o 100000 00005 o 32 Hardware Manual ELTEC 40 60 2 Installation 2 3 Jumpers and Switches 2 3 1 2 32 System Controller J301 Serial Interface CHAN 2 Configuration ELTEC This section lists all features user selectable b
3. 1 72 Local Interrupt Sources iuo Beh EX os rede AVV e ose vete 73 Default Parameters of RMon 2 8 located on 40 60 75 Hardware Manual ELTEC 40 60 List of Figures List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 ELTEC Page Block Diagram E etie uus 2 PCMCIA Installations edad ee RE SEXE ASTE RS AI 27 Installation 30 Location of Jumpers Interface Connectors and Switches 32 Serial Interface CHAN 2 Configuration 34 Relative Address Space ce eee ak eta Seda Pea SERO 45 PCMCIA Interface Configuration 46 Card Control Register 46 din cT 47 Card Status Register 48 Interrupt Vector Register 49 Window Register 50 Hardware Manual IX 40 60 X Hardware Manual ELTEC 40 60 Scope of Delivery Options Scope of Delivery Description Order No BAB 40 Basic Automation Board V BAB A400 B
4. 34 Table 17 1703 DTR Transmit Clock 1 34 Table 18 HEA0T Reset re ed o ede nece xe EAs M eg ERAS 35 Table 19 J1605 Pin 1 Connection of 35 Table 20 J1702 EEPROM Write 35 Table 21 Hex Switch 5901 VMEbus Slave 5 36 Table 22 Hex Switch S902 Hardware Configuration 36 Table 23 Address Assignment 40 60 37 Table 24 Local I O Address Assignment for 40 60 38 Table 25 Slave Base Address Register 39 Table 26 Enable Slave Register 40 Table 27 Intercommunication Register Location on 8 44 Table 28 Address Assignment 5 51 Table 29 Address Assignment of the Real Time 52 Table 30 Address Assignment of the System 53 Table 31 Address Assignment of Watchdog Registers 54 Table 32 Watchdog Configuration Register at
5. SC1 SCO Function don t care 0 Enable snooping don t care 1 Inhibit snooping Table 39 RAM Size RAM Size 7 5 Size 96000 1MB 96001 2 96010 4 MB 96011 8 MB 96100 16 MB 96101 32 MB 58 Hardware Manual ELTEC 40 60 3 11 Serial I O 3 11 1 Serial Communication Controller SCC ELTEC 3 Programmers Reference The BAB 40 60 offers two serial I O lines implemented by one Z8530 Serial Communication Controllers SCC CHAN 1 SCC channel A and B at address FEC6 4000 is hardwired to feature RS 232 two wire hardware handshake mode while CHAN 2 uses removable single inline level converters called SILC As shipped a RS 232 level converter SILC is installed which features hardware handshake as well as XON XOFF protocol The operating mode and data format of each channel can be programmed independently The baud rate generator is driven by the PCLK input at 5 MHz The time constant values in the following table are based on the clock frequency of 5 MHz Table 40 Time Constant Values for SCC Baud Rate Time Constant Error 38400 0 2 3 4510 19200 0 6 2 3003 9600 0 14 1 9719 7200 0 20 1 4931 4800 0 31 1 4449 3600 0 41 0 9824 2400 0 63 0 1653 2000 0 76 0 1645 1800 0 85 0 2288 1200 0 128 0 1628 600 0 258 0 1615 300 0 519 0 0321 150 0 1040 0 0321 134 5 1160 0 0
6. 35 2 3 00 ASwitCcheS s b wx E SEN qx RE 35 2 3 6 1 VMEbus Slave Address 5901 35 2 3 6 2 Hardware Configuration 902 36 3 Programmers Reference 37 S I Address M p i ss eese PER PUN LP pe Re Pues attis 37 3 2 DRAM eet m ee e e ag eite equ i e 39 3 2 1 RAM Access from the Local 2 39 3 2 RAM Access from the VMEbus 2 2 39 3 2 3 r Address Translatiom 5 y eov Fuera Rasa e Russe ees 40 2 24 une e o Baise Gee ae AUS sre egi Re t 4l 3 2 5 Access from the 41 3 2 6 Access from 41 3 3 VMEbus Interface elu hae es hee AER Ea Res A CRF HUS IG etg 42 3 3 1 System Controle NEUE NEN VEU Eat 42 3 3 2 WMEbus Master 43 3 3 2 1 Longword Access to Wordwide Slaves 43 3 3 2 2 Address Modifier 43 3 3 2 3 Read Modify Write Cycles 43 3 3 2 4 16 Slave Interface 5 44 347 PCMCEA Interface s edes e e Balboa
7. PCMCIA PCMCIAO Controller PCMCIA1 mm BEB Hardware Manual BAB 40 60 VMEbus X101 Row A Row C Row B X102 ELTEC 40 60 ELTEC 1 Specification The BAB 40 60 is a highly integrated high performance single board VMEbus computer with optional graphics display It is designed to offer as many features as possible on a single slot VMEbus board Suitable intelligent or high integrated components are used to achieve this density of computing power On the BAB 40 there is one 68040 CPU clocked at 50 or 66 MHz On chip caches for program and data 4 KB capacity each and the on chip floating point units allow 35 MIPS at 66 MHz The 68060 CPU on the BAB 60 offers 2 5 times the performance of a 68040 clocked at the same frequency Additionally backward compatibility with existing 68000 family software is guaranteed The main memory is placed on a separate PS 2 SIMM memory module This easily allows to expand the memory up to 32 MB without any changes necessary at the CPU board The main memory is directly accessed via the 32 bit processor bus The major drawback of the 68040 60 is the deletion of dynamic bus sizing This requires 68020 30 applications to be modified if they access word devices with longword instru
8. gt 4 elektronik mainz BAB 40 60 Basic Automation Board Hardware Manual Revision 1 A Revision History BAB 40 60 Rev Changes Date 1A First Edition valid for BAB 40 60 Hardware Revision 1 A 01 09 95 G M H K WARNING This equipment generates and can radiate radio frequencies If not installed in accordance with the instruction manual it may cause interference to radio communications The equipment has not been tested for compliance with the limits for class A computing devices pursuant to subpart J of part 15 of FCC rules which are designed to provide reasonable protection against such interference but temporary usage is permitted as per regulations Operation of this equipment in a residential area is likely to cause interference in which case the user at his own expense is required to take whatever measures may be required to shield the interference DISCLAIMER The information in this document has been carefully checked and is believed to be entirely reliable However no responsibility is assumed for inaccuracies ELTEC reserves the right to make changes to any products to improve reliability function or design ELTEC does not assume any liability arising out of the application or use of any product or circuit described in this manual neither does it convey any license under its patent rights nor the rights of others ELTEC products are not authorized for use as compon
9. oe 66 ELTEC Hardware Manual 100 Index Continued BAB 40 60 I Continued R Continued tdt uc a 49 61 tance ue SES 49 5 422 tetas cb 61 IVA s is tnd alos waste dox NUN 49 RS485 3 joes hints eat 61 IV sonos uds e e e 49 RS T secu e bdo a a DENT 47 TV nter nM E stitit 49 S OMM ME LT SCQ 9 SCRIPTS deret a 9 JEDEC unos ais m eee 8 DES s ront LER Fat eto Bel Oe ne pears 64 L SCSI Interface 9 Local I O Address Assignment 38 Serial NR Pam at 9 59 Local Interrupt Sources 73 SILC Less 4 9 28 61 locked cycle Reel ORA 74 SIMM 25 Longword Access to Wordwide Slaves 43 Status Display Lag aser copiae AN qeu Dia LN ELK 10 67 SYSCDR zm acon E E see 11 42 M SXSRESET TETT 11 29 System Control Register 70 40 66 System Controller 11 42 MML x lo ette ees y MIBE eta bud 22 T TAS iode ee us SAN ORR SEG 6 43 74 N T eas 13 9 12 Timing 45 Ceo et res 47 P Parameter RA
10. Font Use Helvetica 8 Pt Tables and drawings Helvetica 10 Pt Signal names formulars Times italic Notes Courier bold Program code function names commands Times bold Emphasized text e g headlines ELTEC Hardware Manual XV How to Use this Manual Continued BAB 40 60 Other Conventions Indicates information that requires close attention Indicates critical information that is essential to read gt Indicates information that is imperative to read Skipping this material possibly causes damage to the system XVI Hardware Manual ELTEC 40 60 1 Specification 1 Specification 1 1 Main Features One 68 EC 040 060 CPU at 50 MHz or 66 MHz Memory PS 2 SIMM memory module 1 2 8 16 32 MB for data program storage 44 MB s at 33 MHz bus speed 2KB SRAM and RTC for storage of variable system parameters MK48T12 MK48T18 8 KB DS1644 32 KB Up to 1 MBx 8 K EPROM Two PCMCIA sockets on front panel for two type I or PC Cards or one type III PC Card Flash SRAM and ATA HD only One internal PCMCIA socket type I type IL or with some restrictions type III Flash SRAM and ATA HD only Ethernet interface 32 bit ILACC VMEbus Interface Controller System controller and arbiter VMEbus interrupter and interrupt handler 32 bit slave BLT 20 MB s Master slave write posting IOC 2 gate array 68040 to 68020 bus convert
11. 3 Programmers Reference This register is used to select the interrupt vector of the PCMCIA After an interrupt request of a PCMCIA card the six MSBs of this register are passed to the CPU during an interrupt acknowledge cycle The two LSBs of the interrupt vector depend on the socket number which requested the interrupt Figure 11 Interrupt Vector Register IVR 7 6 5 4 3 2 1 0 38 0001 IV7 IV6 IV5 4 IV2 IV1 IVO write only V2 to Interrupt Vector Bit 2 to 7 This register is used to define the interrupt vector which is transferred to the base board during interrupt acknowledge cycles IVO to IV1 Interrupt Vector Bit 0 and 1 The bits 0 and 1 depend on the socket number which requested the interrupt 00 PCMCIAI 01 PCMCIA2 10 PCMCIAO 11 Reserved Only one interrupt vector register exists for all PCMCIA sockets Changing the vector for one socket will also affect the other interrupt vectors If more than one PC Card requests an interrupt PCMCIAO has the highest and PCMCIAI has the lowest priority Hardware Manual 49 3 Programmers Reference 3 4 6 Window Register WIR 3 5 VIC Timer 50 BAB 40 60 This register selects the higher address lines the REG signal of the PCMCIA interface The output enable of this register is controlled by the RST bit the CCR If RST is active 17 the output of the WIR is disabled REG is driven to 1 A21 to A25 are
12. 5 0000 Table 31 Address Assignment of Watchdog Registers Address Description Access Direction FEC3 0002 Port A Data Register System CIO read PA7 FEC5 0000 Watchdog Trigger write FEC5 2000 Watchdog Configuration write 54 Hardware Manual ELTEC 40 60 3 Programmers Reference Table 32 Watchdog Configuration Register at FEC5 2000 Value Function 00 Disable Watchdog 01 Enable Watchdog 130 ms 02 Enable Watchdog 260 ms 03 Enable Watchdog 520 ms 04 Enable Watchdog 1 04 s 05 Enable Watchdog 2 08 s 06 Enable Watchdog 4 16 s 07 Enable Watchdog 8 32 s 08 Enable Watchdog 16 64 s 09 Enable Watchdog 33 28 s 0A Enable Watchdog 1 min 6 s 0B Enable Watchdog 2 min 13 s 0C Enable Watchdog 4 min 26 s 0D Enable Watchdog 8 min 52 s Enable Watchdog 17 min 44 s Reserved Watchdog disabled 10 S1F Same as 00 0F but watchdog becomes locked ELTEC Hardware Manual 55 3 Programmers Reference BAB 40 60 3 9 Revision Information Revision information is stored on the board to give software the chance to distinguish between different versions and derivates of the BAB 40 60 The information consists of two parts First there are bits 3 7 of the IOC 2 s control register at SFEC7 00A8 Table 33 1OC 2 Control Register at FEC7 00A8
13. 5 2000 55 Table 33 IOC 2 Control Register at PBCT 00AS ver x RA RI 56 Table 34 Control Register Layout 2 2 NIA 56 ELTEC Hardware Manual VII List of Tables Continued BAB 40 60 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 VIII Page Address Map of the Serial EEPROM 57 Snoop Control Register Layout for 40 60 58 Snoop Control Encoding for 40 58 Snoop Control Encoding for 60 58 e teet Pede PDA qutd IP 58 Time Constant Values for SCC 1 59 Address Assignment ofthe 8 60 Pin Assignment for SIDOS UP poe wipe 62 Ethernet Controller Address 63 Register RNC ben Neben eu rete saa Coates 65 Reset Conditions k bse aise diate hae xU v UN Tv e Re este aimer se 68 System Control Register Layout System CIO 70 VIC Interrupt Priority
14. Default Data Definition Description RAM Address Default Data Definition Description RAM Address Default Data Definition RAM Address Default Data Description 3 Programmers Reference unsigned char rto baseaddr Start address of video frame buffer 0000 0CA2 0400 0000 unsigned short rto plnsizx rto plnsizy Size of graphic plane in X and Y direction 0000 0CA6 0000 0CA9 2048 1024 unsigned short rto plnsizx rto plnsizy Size of window in X and Y direction 0000 0CAA 0000 0CAD 640 480 unsigned char rto fcol rto bcol Number of foreground and background color Valid values 0 black 8 grey 1 navy blue 9 blue 2 dark green 10 green 3 dark cyan 11 cyan 4 dark red 12 red 5 dark magenta 13 magenta 6 dark yellow 14 yellow 7 light grey 15 white 0000 0CAF 0000 0CBO 0 15 Hardware Manual 91 3 Programmers Reference 3 21 67 Number of Columns and Lines 3 21 6 8 Video Descriptor Format 3 21 6 9 Position of Character Window 92 d BAB 40 60 Definition unsigned char rto noofclms rto nooflins Description This values define the number of columns and lines of the character window RAM Address 0000 0 0000 0CB2 Default Data 80 24 Definition unsigned char rto_vdform Description d Format of video descriptor Valid values 00 No position follows T
15. 30 0001 IEN CT1 CT2 Vpp RST 1 1 1 read and write EN Enable socket interrupt request and CT2 Command Timing These bits are used to define the minimum command pulse width to the socket interface The write pulse is one clock shorter than the read pulse This is done to generate a longer data hold time for write cycles to the socket interface For read cycles the card should be driven valid data one clock before the read command becomes inactive The complete cycle time setup command recover for read and write accesses 15 identical 46 Hardware Manual ELTEC 40 60 ELTEC Figure 9 Timing REG CE x 4016 IOR OE D x read IOW WE D x write 3 Programmers Reference setup command recovery Jie ug ix X BA Command Timing IOR or OR IOW or WE CT2 1 1 120 ns 80 ns 1 0 280 ns 240 ns 0 1 440 ns 400 ns 0 0 600 ns 560 ns The default reset value is 11 The setup and recovery timings are depending on the base board The absolute minimum timings are Read setup 60 ns Read recovery gt 20 ns Write setup gt 60 ns Write recovery gt 60 ns Vpp Vpp Enable This bit is used to switch the Vop voltage of the socket interface from 5 V to 12 V The default reset value is 5 V 07 RST Reset This bit is used to control the RESET of the card interface and the
16. xx PCMCIA VIC Timer LIRQ2 6 42 VIC SCSI Controller LIRQ1 2 41 VIC Keyboard Controller LIRQ1 2 41 VIC VIC ACFAIL 7 48 VIC VIC Failed Write Post 7 49 VIC VIC Arbitration Time out 7 4 VIC VIC SYSFAIL 7 4B VIC VIC Interrupter IACK 1 4 VIC x 1 4D VIC VIC ICMSO ICMS3 5 1C 1F VIC VIC ICGSO ICGS3 7 10 13 VIC 1 These levels are not changeable i e fixed in hardware all other levels are programmable via VIC register Also all vectors delivered by the VIC are programmable Individual interrupt levels are masked dynamically under software control by programming the appropriate VMEbus interrupt control register to ICR7 of the VIC This feature allows easy implementation of multi processor systems The VMEbus interrupt requests are always active low and level sensitive All VMEbus IRQs are disabled after the initialization of RMon To change this use the RMon setup menu For further details see the data sheet 1 068 Hardware Manual 73 3 Programmers Reference BAB 40 60 3 20 Indivisible Cycle Operation 3 20 1 Deadlock 3 20 2 TAS Violation 74 Resolution on 040 When a CPU performs a locked cycle to the 020 bus e g TAS to the VMEbus and someone wants to access the 040 bus from the 020 bus e g slave access from VMEbus to the local RAM there is a deadlock situation On normal reads or writes such a deadlock is resolved b
17. 00 Definition unsigned short bootp Description This value specifies the network boot port number 0 0000 0 0001 RAM Address 0000 0 Default Data 0000 Definition unsigned short nettout Description Time out value for network boot RAM Address 0000 0CIE Default Data 0010 Hardware Manual ELTEC 40 60 3 21 4 17 Server Name 3 21 5 3 21 5 1 Group E Board Information 0000 0C58 0000 0C9B Character Ports ELTEC 3 Programmers Reference Definition unsigned char sname 0x30 Description Server name This string must always be zero filled for a correct termination RAM Address 0000 0 20 Default Data 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Definition unsigned char portno Description Character I O port The upper nibble holds the input port number and the lower nibble holds the output port number Valid port numbers 0 Keyboard Graphic 1 SCCPortA 2 SCC Port B 3 FIFO RAM Address 0000 0 59 Default Data 00 This value may be overwritten depending on the hex switch S902 setting It also will be changed to 11 if no graphic interface is installed Hardware Manual 87 3 Programmers Refer
18. 0 If RST is 0 the WIR is enabled to drive the PCMCIA signals Figure 12 Window Register WIR 7 6 5 4 3 2 1 0 3 0000 25 24 23 22 21 write only REG Register Access During memory cycles this output chooses between attribute 0 and common 1 memory During I O cycles this signal switches between I O 0 and DMA 1 access 21 to A25 Address Lines 21 to 25 These bits define the socket address lines 21 to 25 The VIC contains a timer which can be programmed to output a periodic wave form on LIRQ2 The frequencies available are 50 Hz 100 Hz and 1000 Hz The timer is enabled and controlled by writing slave select control register 0 The interrupt is enabled and controlled by writing local interrupt control register 2 The clock tick timer is typically used as a time base for multi tasking operating systems such as OS 9 or LynxOS If other frequencies are needed one of the three counters timers that are included in the CIO may be used For more details about the timer refer to the VIC data sheet Hardware Manual ELTEC 40 60 3 Programmers Reference 3 6 Battery Backed Parameter RAM and Real Time Clock 3 6 1 Parameter RAM NVRAM ELTEC The real time clock is designed with the MK48T12 or 48 18 timekeeper RAM from SGS Thomson or DS1644 from Dallas The chip combines a 2KBx8 8KBx8 32KBx8 CMOS SRAM parameter RAM byte
19. 3 3 2 2 Address Modifier Source 3 3 2 3 Read Modify Write Cycles ELTEC 3 Programmers Reference The master interface of the BAB 40 60 board supports 8 16 and 32 bit data transfer cycles in A32 A24 and A16 addressing modes For a short overview see Section 1 4 Definition of Board Parameters Two different control lines of the system CIO enable longword breaking for the A32 and A24 A16 area 0 forces A24 A16 D16 data size on VMEbus 1 allows A24 A16 D32 data size on VMEbus PA4 0 allows A32 D32 data size on VMEbus 1 forces A32 D16 data size on VMEbus specifies the default values set by RMon Use the RMon setup menu for changes The VIC chip supplies the VMEbus address modifier signals This is done by either routing 2 line to AMO 2 or by driving these signals by an internal address modifier source register of the VIC FECO 10B7 The AM3 5 lines are driven depending on the actual data size or by the address modifier source register One CIO output signal is used to control this option PA2 0 uses CPU and address size dependent modifiers 1 uses VIC s address modifier source register specifies the default values set by RMon Use the RMon setup menu for changes For a detailed description of the address modifier values see Section A 2 Address Modifiers on VMEbus Read modify write cycles like TAS or CAS2 are supported by the BAB 40 60 The CAS2 instruction
20. Local Area Network Local Interrupt Request Medium Attachment Unit Memory Base Address Register Memory Management Unit Nonvolatile RAM Printed Circuit Board Personal Computer Memory Card International Association Programmable Logic Device Phase Locked Loop Random Access Memory Row Address Strobe Read Modify Write Cycle Real time Clock Request to Send Slave Base Address Register Small Computer Systems Interface System Control Register Serial Interface Level Converter Static RAM Slave Mask Register Transistor Transistor Logic VMEbus Interface Chip Video RAM Unaligned Transfer Hardware Manual ELTEC 40 60 How to Use this Manual How to Use this Manual Document Structure This manual is divided into the following chapters Chapter 1 Specification contains a list of distinguishing features a block diagram with a general description a description of the main building blocks and the board parameters Chapter 2 Installation describes the requirements and the step by step installation A table shows the default settings of jumpers and switches followed by a detailed description of adjustable functions Chapter 3 Programmer Reference shows the address map and describes the address ranges in detail Special functions are also described in this chapter The Appendix contains references to additional literature an index and a glossary and necessary extracts of data sheets Document Conventions Font Types
21. because only level 2 IACK cycles are routed to the BEB Hardware Manual 11 1 Specification 1 3 19 Software 12 BAB 40 60 The local BAB 40 60 firmware RMon is stored in the on board EPROM RMon provides the basic software layer of the board Any operating system or application software is based on the RMon and uses its functionality Power On Initialization Configuration Various Bootstraps Externally Callable I O Functions Application Hooks Power On Initialization After RESET or power on the local hardware VIC serial I O CIO video keyboard interface etc has to be initialized by the CPU The initialization is affected by certain parameters taken either from the on board NVRAM or from the EPROM default values Hex switch S902 selects whether the NVRAM or the default values are to be used The NVRAM parameters are certified by a checksum If the checksum test fails the default parameters are used independent of the switch setting After reset or power on an automatic selftest routine checks the functional groups of the board and displays its results Configuration The configuration program is completely menu driven The program interactively shows the configuration parameters and allows their modification I O Configuration e g serial I O AT keyboard on board video baud rate etc Video Mode Bootstrap Configuration Internet Address of ILACC VMEbus Interface Configu
22. output enable of the Window Register WIR Default reset value is 1 Hardware Manual 47 3 Programmers Reference BAB 40 60 3 4 4 Card Status This register reflects the status of the PCMCIA interface Ready Write Register CSR Protect Card Detect and Battery Status is available from this register Figure 10 Card Status Register CSR 7 6 5 4 3 2 1 0 34 0001 RDY WP BV2 BV1 1 1 1 read only RDY Ready Interrupt Request This bit reflects the state of the RDY IREQ pin of the socket In memory mode this input indicates the ready busy state of the card In I O mode it indicates an interrupt request WP Write Protect I O select 16 This bit reflects the state of the 1016 pin of the socket In memory mode this input is the status of the write protect switch of the card In I O mode it indicates that the I O address being accessed is capable of 16 bit operation CD Card Detect If this bit is set to 0 it indicates the presence of a card in the socket BV2 Battery Voltage 2 In memory mode this bit serves as the BVD2 battery warning status In DMA mode it may be used for DMA request Battery Voltage 1 In memory mode this bit serves as the BVD1 battery dead status In I O mode this is the STSCHG card internal status change 48 Hardware Manual ELTEC 40 60 3 4 5 Interrupt Vector Register IVR ELTEC gt
23. 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Definition unsigned char internethost 0x10 Description Internet host address Notation XXX XXX XXX XXX xxx address component all values ASCII This string must always be zero filled for a correct termination It is configurable by means of the setup utility RAM Address 0000 0 8 0000 0BD7 Default Data 30 2E 30 2E 30 2E 30 00 00 00 00 00 00 00 00 00 Hardware Manual 85 3 Programmers Reference 3 21 4 14 Internet Boot File Name 3 21 4 15 BootP Flag 3 21 4 16 Network Boot Time out 86 BAB 40 60 Definition unsigned char internetboot 0x40 Description Boot file address name Notation XXx xxx xxx xxx filename xxx address component all values ASCII This string must always be zero filled for a correct termination It is configurable by means of the setup utility RAM Address 0000 0BD8 0000 0C17 Default Data 30 2E 30 52 30 2E 30 53 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
24. 1 701 m X801 VGA Keyboard O X1101 30 Hardware Manual ELTEC 40 60 2 Installation 2 2 Default Board Setting Table 13 Default Settings Jumpers Switches Position Description J301 closed System controller enabled See Section 2 3 1 System Controller J301 J701 1 2 DCD from X702 connected to SILC See Section 2 3 2 Serial Interface CHAN 2 Configuration J702 1 2 DCD from SILC connected to SCC 3 4 7 37 MHz connected to SCC receive clock See Section 2 3 2 Serial Interface CHAN 2 Configuration J703 1 2 DTR from SCC connected to SILC See Section 2 3 2 Serial Interface CHAN 2 Configuration J1401 open No reset See Section 2 3 3 Reset J1401 J1605 1 2 See Section 2 3 4 Pin 1 Connection of EPROM J1605 J1702 closed Write enable for serial EEPROM seeSection 2 3 5 EEPROM Write Enable J1702 901 0 VMEbus slave address at 8000 0000 see Section 2 3 6 1 VMEbus Slave Address S901 902 0 Default initialization values see Section 2 3 6 2 Hardware Configuration S902 ELTEC Hardware Manual 31 2 Installation BAB 40 60 Figure 4 Location of Jumpers Interface Connectors and Switches in OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO n 0
25. 27 E27 or E17 500 40 BAB 40 or BAB 60 This value should not be modified d RAM Address C8E Default Data 40 Definition unsigned long rmon Description Base address of RMon jump table for user applicable routines RAM Address 0000 0 90 Default Data SFE80 0000 Hardware Manual 89 3 Programmers Reference 3 21 5 8 Size of Local UO Memory d 3 21 6 Group F Video Descriptor 3 21 6 1 Graphic d Mode d 3 21 6 2 Graphic Bit 90 40 60 Definition unsigned short memsize Description Size of local memory in MB found during cold or warmstart This value is changed by RMon RAM Address 0000 0 96 Default Data SFFFF Definition unsigned char rto_mode Description Bits 0 3 Internal number used as index in the video descriptor table Bit 5 Enable Digital output RAM Address 0000 0 0 Default Data 00 Definition unsigned char rto gbm Description Number of bits per pixel Valid values 03 8 bits per pixel 02 4 bits per pixel 01 2 bits per pixel 00 1 bit per pixel RAM Address 0000 0 1 Default Data 02 Hardware Manual ELTEC 40 60 3 21 6 3 Display Start Address 3 21 6 4 Size of Graphic Plane 3 21 6 5 of Display Window 3 21 6 6 Number of Fore Background Color ELTEC D L D L D Definition Description RAM Address
26. Hardware configuration from basic EPROM 1 Hardware configuration from SRAM 2 Reserved for ELTEC 3 RMon interactive mode on serial port 4 RMon interactive mode on dual ported RAM local address 9 000 5 7 Reserved for ELTEC 8 F Hardware configuration from SRAM and start program in user EPROM 5901 and 5902 have no direct influence A changed position becomes only effective after the next reset i e the software reads the switches and Hardware Manual programs the appropriate registers ELTEC 40 60 3 Programmers Reference 3 1 Address Map 3 Programmers Reference The BAB 40 60 is designed to utilize the entire 4 GB address range of the 68040 060 chip Using the address modifier of the VMEbus the address range may be enlarged by subdivision into data and program areas and or user and supervisor areas The BAB 40 60 recognizes two address areas the local address space and the global VMEbus address space Table 23 Address Assignment of BAB 40 60 Address Range Device VMEbus Cache 1 Burst Access Address Modifier Width b 0000 0000 01FF FFFF Local RAM local Y Y 32 0200 0000 03FF FFFF Local RAM mirrored local N Y 32 0400 0000 05FF FFFF Video RAM local Y N 32 0600 0000 07FF FFFF Video RAM mirrored local N Y 32 0800 0000 F BFF FFFF VMEbus Extended A32 N9 N 32 16 8 FC00 0000 FC3F FFFF PCMCIA1 local N N 16 8 F
27. LWORD 14 WRITE BR2 AM5 15 GND BR3 A23 16 DTACK AMO A22 17 GND AM1 A21 18 AS AM2 A20 19 GND AM3 A19 20 IACK GND A18 21 IACKIN SERCLK A17 22 16 23 AM4 GND A15 24 A07 IRQ7 A14 25 A06 IRQ6 A13 26 A05 IRQ5 A12 27 A04 IRQ4 A11 28 A03 IRQ3 A10 29 A02 IRQ2 A09 30 A01 IRQ1 8 31 12V 5STDBY 12 V 32 5V 5V 5V Signals in parentheses are not connected Hardware Manual BAB 40 60 ELTEC 40 60 Table 7 Pin Assignment of Connector X102 1 Specification Pin Signal Row A Signal Row B Signal Row C 1 5V SCSIDB1 2 SCSIDBO GND SCSIDB3 3 SCSIDB2 Reserved SCSIDB5 4 SCSIDB4 A24 SCSIDB7 5 SCSIDB6 A25 6 SCSIDBPO A26 7 A27 8 A28 9 A29 10 A30 11 A31 12 GND 13 5V 14 D16 15 D17 SCSIATN 16 D18 GND 17 GND D19 SCSIBSY 18 SCSIACK D20 SCSIRST 19 SCSIMSG D21 SCSISEL 20 SCSIC D D22 SCSIREQ 21 SCSII O D23 22 GND 23 D24 24 D25 25 D26 26 D27 27 D28 28 D29 29 D30 5V 30 031 31 GND 32 5V ELTEC Hardware Manual 17 1 Specification BAB 40 60 Table 8 Pin Assignment of Power Connector X103 Pin Description 1 Power Good ACFAIL 5 12 V 12 V GND 6 GND O AJ OIN 18 Hardware Manual ELTEC 40 60 ELTEC 1 Specification
28. an external SCSI terminator ELTEC Hardware Manual 21 1 Specification BAB 40 60 1 4 Definition of Board Parameters 141 VMEbus e VMEbus interface according to specification ANSI IEEE STD 1014 1987 Rev D1 4 VMEbus Master Capabilities MD32 MRMWS VMEbus Slave Capabilities SADO32 SRMW32 UAT BLT Arbiter Options PRL RRS 4 us to 480 us SYSCLOCK generation BBSY filter Requester Options Any one of BR 0 BR 1 BR 2 or BR 3 Programmable Release when done RWD Release on request ROR Release on bus clear ROC Bus capture and hold BCAP Programmable fair request timer 2 us 30 us Interrupt Handler and Generator Capabilities Interrupt handler and generator on IRQI to IRQ7 Interrupter Options Any one of where 1 lt n lt 7 22 Hardware Manual ELTEC 40 60 1 42 PCMCIA 1 4 3 Ethernet 1 44 SCSI 1 4 5 Serial 1 4 6 MTBF Values ELTEC 1 Specification Address Range programmable extended standard short I O extended access A31 A24 and mask short I O A15 A8 Default extended access 64 MB short I O 256 B Two type I or II PC Cards or one type III PC Card on the front One type I II or III PC Card internal Type III with mechnical restrictions see Section 2 1 2 PCMCIA Installation All sockets support Flash SRAM and ATA harddisk cards with 5 V supply voltage e AUI interface according to
29. be programmed to level sensitive and has to supply the vector because the ILACC has no provision built to do so Table 43 Ethernet Controller Address Layout Address Description FEC6 8002 Register Data Port RDP FEC6 8006 Register Address Port RAP A detailed description of the AM79C900 can be found in the data sheet ELTEC Hardware Manual 63 3 Programmers Reference BAB 40 60 3 13 SCSI Interface A Small Computer System Interface SCSI controller is built around a NCR53C710 chip The full specification ANSI K3T 9 2 is implemented supporting all standard SCSI features including arbitration disconnect reconnect and parity 3 131 SCSI Controller interrupt request line IRQ of the SCSI controller is connected to the LIRQI input of the VIC The NCR53C710 cannot supply its own vector so the VIC has to be programmed to supply a vector for the SCSI controller The VIC LICRI has to be programmed to level sensitive and has to supply the IRQ vector The BAB 40 60 uses Big Endian Bus Mode 2 of the NCR53C710 According to the SCSI specification the interconnecting flat cable must be terminated at both ends On the BAB 40 60 this is done by an active termination chip which can be enabled via PA6 of the system CIO 0 enable 1 disable If the BAB 40 60 board is not located at either end of the SCSI bus the termination must be disabled via setup menu of the RMon A detailed description of
30. drivers please contact ELTEC Hardware Manual 27 2 Installation 2 1 3 Board Installation 2 1 3 1 Serial 2 1 3 2 Graphics 2 1 4 Serial Interface Level Converter SILC 28 BAB 40 60 The installation of the BAB 40 60 on VMEbus is not complicated A suitably terminated VMEbus backplane is required The power supply must meet the specifications described in Section 1 4 Definition of Board Parameters The processor board requires 5 V supply voltage 12 V are needed for the RS 232 serial interface and the Ethernet interface RMon uses CHAN 1 of the SCC V CABL A144 can be used to connect a terminal 9600 baud 8 bit 1 stop bit no parity via X701 to the BAB 40 60 If a graphics module is installed it requires a monitor and AT keyboard with PS 2 connector A standard VGA monitor has to be connected to the 15 pin Sub D female connector and the keyboard has to be connected to 6 pin female miniature circular mini DIN connector Both connectors are located on the front panel A standard VGA monitor and a standard PS 2 compatible keyboard fit without modification For connection to an AT keyboard ADAP 210 is available The Serial Interface Level Converter SILC modules generally convert TTL level signals generated or accepted by the SCC to the appropriate signal levels for external transmission lines SILC modules for RS 232 RS 422 and RS 485 are available The mechanical outline of the SILC modules a
31. eh XI Related Prod cts z uu Reden a ee dete db ed doses osse aed XII Conventions ia en RERBA VE RR ARRA RE AURORA REY XIII How to USeithis Manual cite oe ete eet e RU BER ay RA dede RS XV 1 Specification Neb Nee MR Re ER ERN oda o ded 1 Ll ees etra euet Date e pae M 1 1 2 General Descriptions aes en ee e ze e 2 1 3 Technical duce Bete Rerum Ede ee Reemi Bid bed E 5 1 351 ee ten bald E Bar ea de Mendig bute ETT 6 1 3 2 RAM Module oet eod ede Ue e d e de Rte Bel 7 1 3 3 BCMCTA Interface eia eese utebare tW eee der e edd M ose de alg deen 8 L3 44 EPROM cs 8 1 3 5 Graphics Keyboard Interface 8 EthernetInterfaee i e DIRIGE E Deka tesa 8 1 37 SCST Interface c sedo ACRI ont Me RU ERI SU RATER RAS RIA IR 9 1 3 8 SenalllO ib Idee eue iier NN ES EIN es 9 1 3 9 GIO Counters Timers o cesser UA RAD 9 1 3 10 Parameter RAM and Real Time 9 13 11 Revision EEP
32. n 82 3 21 4 3 SESE Controller ID E ea er ede d 82 321 44 SCSI Controller Hardware 83 32145 SCSI Logical Unit 83 35 21 4 6 Special Boot Flag I 83 3 214017 Sector Size Seea 84 3 21 4 8 Base Address of RAM ROM PCMCIA Boot 84 3 21 4 9 Retry Counter for Network 84 3 21 4 10 Delay until Auto Starts 84 3 21 4 11 Logical Sector Offset 0 0 0 0 eee eee 85 3 21 4 12 Device Command eee e e Ra 85 3 21 4 13 Own Internet Address 85 3 21 4 14 Internet Boot File Name 86 3 214 15 BootP Flags oet nU eR UR sr ORC URDU ge 86 3 21 4 16 Network Boot Time out 86 3 21 2407 Server t aS oct ome Op con 87 3 21 5 Group E Board Information 0000 0C58 0000 0C9B 87 3215 1 POS xo er T Cc D 87 3 21 5 2 Watchdog Enable Flag 88 3 21 5 Watchdog Time Out Period 88 3 21 5 4 Internal Board Information 88 ELTEC Hardware Manual V Table of Contents Cont
33. the NCR53C710 controller chip can be found in the data sheet The first access to the NCR53C710 must set the EA bit in the DCNTL register of the NCR53C710 Accessing the NCR53C710 without the EA bit set will lock the CPU bus gt The NCR53C710 shares the LICRI input of the VIC with the keyboard controller 64 Hardware Manual ELTEC 40 60 3 Programmers Reference 3 14 IOC 2 ELTEC s Input Output Controller IOC 2 is ASIC intended to maximize the performance of ELTEC s CPU boards The IOC 2 is specially designed as data address bridge between a 68040 type local bus and VICO68 to support fast VMEbus master slave block transfers A second main function is a universal programmable I O bus interface with an appropriate address decoder 3 14 1 Register Set 25 IOC 2 registers are read write accessible using longword transfer cycles only The internal address decoder reserves an IOC 2 address space of 64 KB The following register map shows all internal registers and their corresponding register offset address The complete CPU register address is calculated by IOALR value Register OFFSET address Table 44 Register Map Offset Addr Symbol Name Reset Value Bus Interface Registers 70000 IOALR Address Location Register FECO 0000 70004 IODCRO Device Control Register 0 0000 0000 70008 IODCR1 Device Control Register 1 0000 0000 7000C IODCR2 Dev
34. to support either RS 232 or RS 422 485 standard via SILCs Serial Interface Level Converters The integrated real time clock allows the operating system to provide date and time for revision control The clock is powered by an internal lithium battery 2 8 32 KB of battery backed RAM are used for storage of system dependent parameters The four LED status display on the front panel indicates the condition of the processor Two hex code switches software readable are used by the firmware to set up the operating mode and the VMEbus base address of the board The VMEbus interface of the BAB 40 60 uses the 1 068 VMEbus Interface Controller gate array One 1M x 8 EPROM holds the firmware The on board Ethernet interface provides connection to most popular local area networks LAN A sophisticated SCSI 2 interface is also located on the BAB 40 60 The controller chip is very fast and intelligent so that it forms a very efficient SCSI interface with max transfer rates of 10 MB s The on board BAB extension bus BEB allows easy hardware extension of the BAB 40 60 using various mezzanine busses The BAB graphic bus BGB allows flexible extension of the BAB with graphics keyboard modules The three PCMCIA sockets support several types of PC Cards harddisks SRAM Flash EPROM Hardware Manual ELTEC 40 60 1 3 Technical Details ELTEC The BAB 40 60 consists of the following main blocks CPU RAM Modul
35. 000 General Control Registers 700A8 ICR 2 Control Register 0000 22 700 ITR IOC 2 Test Register 0000 0000 1 xx 2 IOD 7 0 during reset Hardware Manual ELTEC 40 60 3 Programmers Reference 3 15 Status Display The BAB 40 60 features a four LED display on the front panel This status display is designed as read write register and uses the least significant nibble of the byte As an example the following sequence illuminates the leftmost two LEDs move b S0C SFEC30000 The upper four bits of the display are write enable bits for the lower four bits Only those bits of the lower nibble are changed where corresponding bit in the upper nibble is clear ELTEC Hardware Manual 67 3 Programmers Reference 3 16 Reset 68 BAB 40 60 During power up or after actuation of the reset switch J1401 RESET is held low for approximately 1 s If the system controller is enabled the VMEbus is also reset because the VIC is configured as the VMEbus system controller Otherwise SYSRESET from the VMEbus is an input The reset switch or power up reset affects all modules and chips on the BAB 40 60 board and also the VMEbus SYSRESET line if jumper J301 is inserted A remote reset via VIC s reset register or a VMEbus SYSRESET behaves the same way as a power up reset except that the VMEbus configuration VIC register and master slave address is not changed Table 45 Reset Co
36. 250 110 0 1418 0 0321 75 0 2081 0 0160 50 0 3123 0 0000 Alternatively 7 3728 MHz oscillator can be used for baudrate generation of channel B CHAN 2 Hardware Manual 59 3 Programmers Reference 60 BAB 40 60 The interrupt request outputs of the SCC is connected to the LIRQ4 input of the VIC The Local Interrupt Control Register 4 LIRQ4 of the VIC has to be programmed for an active low level sensitive input The vectors are supplied by the SCC The VIC has to be programmed to generate interrupts on level 5 to the CPU Only CPU IACK level 5 cycles are routed to the SCC device Table 41 Address Assignment of the SCC Address Description FEC6 4000 Channel B Control Register SCC FEC6 4001 Channel B Date Register SCC FEC6 4002 Channel A Control Register SCC FEC6 4003 Channel A Data Register SCC Hardware Manual ELTEC 40 60 3 11 2 Serial Interface Level Converter SILC ELTEC 3 Programmers Reference The Serial Interface Level Converter SILC modules generally convert TTL level signals generated or accepted by the SCC to the appropriate signal levels for external transmission lines SILC modules for the specifications RS 232C RS 422 and RS 485 are available The mechanical outline of the SILC modules allows the changeability of the different SILC modules in the 16 pin pinouts on the BAB 40 60 SILC 200 for RS 232 EIA standard RS 232 was introduce
37. 5 FFFF Snoop Control Register byte write FEC6 0000 FEC6 3FFF Keyboard and Video Controller byte read write FEC6 4000 FEC6 7FFF Serial I O byte read write FEC6 8000 FEC6 BFFF ILACC read write FEC6 C000 FEC6 FFFF SCSI Controller read write FEC7 0000 FEC7 FFFF 2 read write FEC8 0000 FECF FFFF Reserved 5 Hardware Manual ELTEC 40 60 3 2 DRAM 32 1 3 2 2 RAM Access from the Local CPU RAM Access from the VMEbus ELTEC 3 Programmers Reference The base address of the DRAM is fixed to 0000 0000 After reset the EPROM is mapped to address 0000 0000 After some initialization the firmware enables the DRAM at 0000 0000 via PA5 of the system CIO The base address for VMEbus access is specified by the slave base address register SBR and the enable slave select register ESR of the BAB 40 60 The SBR is only accessible by the local CPUs by longword write cycles The SBR is undefined after reset and has to be written before the BAB 40 60 can be accessed from the VMEbus The ESR is cleared disabling all slave accesses by power on reset and the reset switch The ESR can only be accessed by byte write cycles Table 25 Slave Base Address Register Layout Register Address 31 24 23 16 15 8 7 0 SBR FECO 80F4 A32 unused ICF unused Decoder Decoder ext access short I O Do not use other addresses for
38. 6 5 RxD Receive Data 6 CTS Clear to Send Table 4 15 Pin AUI Connector ETHERNET X801 Pin Signal Description 1 5 Control In circuit Shield 2 CI A Control In circuit A 3 DO A Data Out circuit A 4 DI S Data In circuit Shield 5 DI A Data In circuit A 15 69 6 Voltage Common O O 7 Not connected E co S Control Out circuit Shield o9 9 CI B Control Out circuit B 10 DOB Data Out circuit B 9 O Olla 11 DO S Data Out circuit Shield 12 DI B Data In circuit B 13 VP Voltage Plus 14 VS Voltage Shield 15 n c Not connected Hardware Manual ELTEC 40 60 ELTEC 1 Specification Table 5 9 Pin Min D Connector male CHAN 2 X702 Pin Signal Description 1 DCD Data Carrier Detect 2 RxD Receive Data 3 TxD Transmit Data 4 DTR Data Terminal Ready 5 GND Signal Ground 6 DSR Data set ready 7 RTS Request to Send 8 CTS Clear to Send 9 n c not connected Hardware Manual 15 1 Specification 16 Table 6 Pin Assignment of VMEbus Connector X101 Pin Row A Row B Row C 1 D00 BBSY 2 001 BCLR D09 3 002 ACFAIL D10 4 D03 BGOIN D11 5 D04 BGOOUT 012 6 005 BG1IN D13 7 006 BG1OUT D14 8 D07 BG2lN D15 9 GND BG20UT GND 10 SYSCLK BGSIN SYSFAIL 11 GND BERR 12 DS1 BRO SYSRESET 13 DSO BR1
39. 60 ELTEC 40 60 Table of Contents Continued Page 3 20 Indivisible Cycle 1 74 3 20 1 Deadlock 74 3 20 2 TAS Violation 040 74 3 21 Default Parameters for 75 3 21 1 Group A I O Initialization 0000 0800 80000 0 78 321 1 VIG Parameter oou ete ts 78 3211 2 SCC Port A a WR e 79 32113 SCC Port B Parameter ere EI 79 324 14 ale iR ates secun eos 79 3 21 2 Group B Address Information 80000 0 0 0000 0 47 80 32124 IGE Addiesss i ree dey Sed GEMESSEN ts 80 3 21 22 VMEbus A32 Slave 80 32123 VMEb s 32 Slave Size e RE EAR ad rel aes 81 321 24 VMEbus Enable 81 3 21 3 Group C Hooks 0000 0B48 80000 0 6 81 3 21 4 Group D Boot Parameters 0000 0B70 80000 0 57 82 3214 1 Autoboot Flag ciet re t e bod e doen beds 82 321 4 2 Operating System xg Rex RACER cR RR
40. 8 D21 83 A31 9 A14 34 D4 59 D19 84 29 10 GND 35 D6 60 D17 85 A27 11 A16 36 D8 61 GND 86 A25 12 A18 37 D10 62 D15 87 A23 13 A20 38 D12 63 D13 88 A21 14 A22 39 D14 64 D11 89 A19 15 A24 40 GND 65 D9 90 A17 16 A26 41 D16 66 D7 91 GND 17 A28 42 D18 67 D5 92 A15 18 A30 43 D20 68 D3 93 A13 19 45V 44 D22 69 D1 94 A11 20 FC1 45 D24 70 GND 95 A9 21 SIZE1 46 D26 71 IACKBEB 96 A7 22 CSBEB1 47 D28 72 BRBEB 97 A5 23 DSACKO 48 D30 73 AS 98 A3 24 RMC 49 5V 74 Reserved 99 A1 25 50 Reserved 75 DS 100 12V 20 Hardware Manual 50 BAB 40 60 100 51 ELTEC 40 60 1 Specification Table 11 SCSI Connector 8 bit X103 on ADAP 200 Pin Description Pin Description 1 6 2 2 DBO 28 GND 4 DB1 30 GND 6 2 2 e 8 DB3 34 GND 10 4 36 BSY 12 085 38 14 DB6 40 RST 16 7 42 MSG 18 DB8 44 SEL 20 GND 46 CIO oe 22 GND 48 REQ 24 50 y o 26 TERM PWR 49 lo 50 odd pins of 50 pin SCSI connector except 25 are connected to ground Pin 25 is left open Pin 26 is connected to 5 V via a Shottky diode to supply power to
41. 802 3 SCSI 2 8 bit single ended Transfer Speed asynchronous transfer 5 MB s synchronous transfer 10 MB s 2 channels 50 b s 38 4 kb s 8325 h computed after MTL HDBK 217E 111555 h realistic value from industry standard experience Hardware Manual 23 1 Specification BAB 40 60 147 Environmental Storage Temperature Conditions 35 C to 85 Operating Temperature 0 C to 60 non condensing Maximum Operating Humidity 85 relative Air temperature with forced air cooling of approx 1 m sec 1 4 8 Power with all max options approx Requirements 3 6Atyp 5VDC 35 0 5 0 3 12 VDC 10 includes supply of external MAU 02Amax 0 1 Atyp 12 10 24 Hardware Manual ELTEC 40 60 2 Installation 2 1 Introduction 2 1 1 SIMM Installation ELTEC 2 Installation Carefully remove the board from the shipping carton Save the original shipping container and packing material for storing or reshipping the board Avoid touching integrated circuits except in an electrostatic free environment Electrostatic discharge can damage circuits or shorten their lifetime nspect the board for any shipping damage If undamaged the board can be prepared for system installation When unplugging boards from the rack or otherwise handling boards do always observe precautions for handling electrostatic de
42. AB 60 Basic Automation Board V BAB A600 Options Description Order No SCSI SCSI option V BAB Z001 The last letter of the order numbers refers to the hardware revision and is subject to changes Please contact ELTEC for information about valid order numbers Example V E16 B105 a Revision number subject to change ELTEC Hardware Manual XI Related Products BAB 40 60 Related Products Description Order No Documentation Hardware Manual BAB 40 60 V BAB A490 Service Manual BAB 40 60 including V BAB A491 Software Manual RMon W FIRM A209 BEB Specification V BEB A990 IOC 2 Data Sheet V DTBT A924 785230 V DTBT A935 MK48T02 12 V DTBT A907 78536 V DTBT A908 VICO068 V DTBT B914 NCR53C710 V DTBT A934 ILACC AM79C900 V DTBT A925 Hardware BAB Graphics Module V BAB A410 ADAP to adapt signals on P2 to V ADAP A200 SCSI 8 bit and I O signals ADAP to connect AT keyboard to V ADAP A210 PS 2 compatible connector CONV Cheapernet 10BaseT MAU V CONV A500 RS 232 SILC V SILC E200 RS 422 SILC V SILC B300 RS 485 SILC V SILC A400 Cable V 24 for terminal V CABL A144 The last letter of the order numbers refers to the hardware revision and is subject to changes Please contact ELTEC for information about valid order numbers Example V E16 B105 t Revision number subject to change XII Hardware Manual ELTEC 40 60 Conventions ELTEC Conventions If not otherwise specified addresses
43. ACC and its on chip DMA channel is the flexibility and speed of communication The internal Manchester Encoder Decoder of the ILACC is compatible with the IEEE 802 3 specification Via the AUI connector on the front panel the BAB 40 60 is attached to Ethernet Cheapernet 10BaseT networks Hardware Manual ELTEC 40 60 1 3 7 SCSI Interface 1 3 8 Serial 1 3 9 CIO Counters Timers 1 3 10 Parameter RAM and Real Time Clock 1 3 11 Revision EEPROM ELTEC 1 Specification Single ended 8 bit SCSI 2 signals are fed into row A and C of the VMEbus P2 connector X102 An ADAP 200 is plugged onto the rear side of the backplane to interface to standard 8 bit SCSI connectors The NCR53C710 SCSI controller uses its own code fetching and SCSI data transfer from the DRAM The processor executes SCSI SCRIPTS to control the actions on the SCSI and the CPU bus SCRIPTS is a specially designed language for easy SCSI protocol handling It dramatically reduces the CPU activities The SCRIPTS processor starts SCSI I O operations in approximately 500 ns where traditional intelligent host adapters require 2 8 ms The BAB 40 60 offers two serial I O lines implemented by one Z8530 SCC CHAN 1 is a RS 232 two wire handshake interface CHAN 2 uses a removable serial interface level converters SILC As shipped a RS 232 level converter SILC is installed featuring hardware handshake as well as the XON XOFF protocol Additional level con
44. C3 0003 Control Register CIO The peripheral clock of the CIO is connected to a 5 MHz source The interrupt request outputs of CIO is connected to the LIRQ6 input of the VIC Local interrupt control register 6 LIRQ6 of the VIC has to be programmed for an active low level sensitive input The vector is supplied by the CIO The VIC has to be programmed to generate interrupts on level 6 to the CPU Only CPU IACK level 6 cycles are routed to the CIO device ELTEC Hardware Manual 53 3 Programmers Reference BAB 40 60 3 8 Watchdog Timer The watchdog timer installed on the BAB 40 60 monitors the activity of the microprocessor If the microprocessor does not write location FEC5 0000 within a certain time out period a reset pulse is generated After reset the watchdog timer is disabled The watchdog becomes active after writing the desired time out period to the watchdog configuration register at SFEC5 2000 Also the watchdog has a lock feature When locked the watchdog configuration register cannot be changed anymore to prevent unintentionally altering the watchdog period Only reset is able to unlock the watchdog After reset the software can read port A bit 7 of the system CIO to distinguish between a watchdog reset 0 and a reset generated by other sources 1 This watchdog indicator is cleared by power up reset the reset switch a VMEbus SYSRESET a VIC remote reset or by a write access to address
45. C40 0000 FC7F FFFF PCMCIA2 local N N 16 8 FC80 0000 FCBF FFFF PCMCIAO local N N 16 8 FCCO0 0000 FCFF FFFF Reserved FD00 0000 FDFF FFFF BEBO local N N 32 16 8 FE00 0000 FE7F FFFF BEB1 local N N 32 16 8 FE80 0000 FEBF FFFF EPROM local Y N 8 FECO 0000 FECF FFFF Local I O local N N 32 16 8 FEDO 0000 FEFF FFFF Reserved FFO0 0000 FFFE FFFF VMEbus Standard I O A24 N N 32 16 8 FFFF 0000 FFFF FFFF VMEbus Short I O A16 N N 16 8 1 Y 2 TCI driven high N TCI driven low 2 Y TBI driven high N TBI driven low 3 Caching may be enabled via system control register ELTEC Hardware Manual 37 3 Programmers Reference 38 BAB 40 60 Table 24 Local I O Address Assignment for BAB 40 60 Address Device Size Access FECO 0000 FECO 7FFF VIC DO 7 byte read write FECO 8000 FECO FFFF VMEbus Decoder 00 31 write see Section 3 2 2 RAM Access from the VMEbus FEC1 0000 FEC1 FFFF Reserved S FEC2 0000 2 NVRAM RTC byte read write FEC3 0000 FEC3 FFFF System CIO byte read write FEC4 0000 FEC4 FFFF Reserved gt FEC5 0000 FEC5 3FFF Watchdog byte read write FEC5 4000 FEC5 7FFF Revision EEPROM byte read FEC5 8000 FEC5 BFFF Reserved FEC5 C000 FEC5 DFFF Enable slave select ESR byte write see Section 3 2 2 RAM Access from the VMEbus FEC5 E000 FEC
46. Environmental Conditions 2 0 23 1 4 8 Power 23 27 Installation 25 2 1 Introduction Rp Pk ae NE 25 2 1 1 SIMM 2 22 2 2 25 2 22 Installat on eret etes ede t Wee Mp RR ERU ARR 27 2 1 3 Board Installation e RR EUER M ee ot 28 2 L3 L acum odas E RIA WA XIV apr se oio ada 28 2 1 3 2 Graphie i oboe ee e pasen der etos dei ein 28 2 1 4 Serial Interface Level Converter 28 2 1 5 EthemetInstallation lt sarees were eae Med 29 2 1 6 SCST Installations eoe e er der eH E edu t RR M een 29 2 2 Default Board Setting Ie Xe de tc e 31 II Hardware Manual ELTEC 40 60 Table of Contents Continued Page 2 3 Jumpers and Switches c ete x em RR REX LAUR UNCERT ENIRO PRODR bad 33 2 3 1 System Controller J301 33 2 3 2 Serial Interface CHAN 2 33 2 3 3 Reset t ERR MER DEN ERR tesa AG at 35 2 3 4 Pin 1 Connection of EPROM 1605 35 2 3 5 EEPROM Write Enable 11702
47. FF Hardware Manual ELTEC 40 60 Appendix Appendix ELTEC Hardware Manual 95 Mnemonics Chart A 1 Mnemonics Chart A 1 1 Addressing Capabilities A 1 2 Data Transfer Capabilities 96 BAB 40 60 This is the same mnemonics chart that can be found in the VMEbus Specification When the following mnemonic is applied to a board It includes the following addressing capabilities A16 A24 A32 ADO MASTER MA16 MADO16 MA24 MADO24 2 MADO32 lt x KKK SLAVE SADO16 SADO24 SADO32 LOCATION MONITORS LMA16 LMA24 LMA32 Master Data Transfer When the following It means that the MASTER has the following mnemonic is applied data transfer capabilities to a board DO8 EO D16 D32 UAT BLT RMW MD8 X MBLT8 X X MRMW8 X X MALL8 X X X MD16 X X BMBLT16 X X X MRMW16 X X X MALL16 X X X X MD32 X X X MBLT32 X X X X MRMW32 X X X X MALL32 X X X X X MD32 UAT X X X X MRMW32 UAT X X X X X Hardware Manual ELTEC 40 60 Mnemonics Chart Slave Data Transfer When the following It means that the SLAVE has the following mnemonic is applied toa data transfer capabilities board 008 0 08 0 016 032 UAT BLT RMW SD8 O X SRMW O X X SD8 X SBLT8 X X SRMW8 X X SALL8 X X X SD16 X X SBLT16 X X X SRMW16 X X X SA
48. Hardware Manual 69 3 Programmers Reference 3 18 System Control Register SCR BAB 40 60 The BAB 40 60 features several status and control bits to monitor and change the system control signals These are implemented using port lines of the system CIO Reset initializes all ports as input The default values are set during the RMon initialization routine Table 46 System Control Register Layout System CIO Bit No Type Name Description PA7 Input WDS Watchdog Status 0 Watchdog Reset 1 2 Normal Reset PA6 Input SCSITRM SCSI Termination 0 enable termination 1 disable termination PA5 Output RESCYC Reset Cycle 0 Address Decoder normal operation default 1 Address Decoder reset operation reset condition 4 Output DSCTRLO VMEbus A32 Data Size Control 0 normal longword operation for A32 default 1 breaks longword cycles into two word cycles Output DSCTRL1 VMEbus A24 Data Size Control 0 normal longword operation for A24 1 breaks longword cycles into two word cycles default PA2 Output ASCTRL VMEbus Address Modifier Source Control 0 normal operation FCO 2 gt 5 12 VMEbus Address Modifier from VICs Address Modifier Source Register PA1 Output CACTRL VMEbus Cache Control 0 disables caching of VMEbus data default 1 enables caching of VMEbus data PAO Output INIT Initialization Indicator D1401 0 green 12 red PB7 0 Input HEXSW Read Hex Switc
49. LL16 X X X X SD32 X X X X SBLT32 X X X X SRMW32 X X X X X SALL32 X X X X X Location Monitor Data Transfer When the following It means that its LOCATION MONITOR has the following mnemonic is applied capabilities to a board D08 O D16 D32 UAT BLT RMW LMBLT32 X X X X LMRMW32 X X X X X LMALL32 UAT X X X X X A 1 3 Glossary ADO Address Only UAT Unaligned Transfer BLT Block Transfer RMW Read Modify Write EO Both Even and Odd Addresses Odd Addresses Only ELTEC Hardware Manual 97 A 2 Address Modifiers on VMEbus A 2 Address Modifiers on VMEbus BAB 40 60 Hex Code Address Modifier Access Note 5 43 2 1 0 3F H H H H H Standard Supervisory Ascending 1 3E H H H H HL Standard Supervisory Program 1 3D H H H H L H Standard Supervisory Data 1 3C H H HHLL Undefined 2 3B H H H L HH Standard Non Privileged Ascend 1 3A H H H L HL Standard Non Privileged Program 1 39 H H H L L H Standard Non Privileged Data 1 38 H HHL LL Undefined 2 30 37 H HL x x x Undefined 2 2F H L H H HH Undefined 2 2E H L HHHL Undefined 2 2D H L H H L H Short Supervisory I O 1 2 HL H HLL Undefined 2 2B H L H L HH Undefined 2 2A H LHL HEL Undefined 2 29 H L HL L H Short Non Privileged 1 28 HL HL LL Undefined 2 20 27 H L L x x x Undefined 2 10 1F L Hx x x x Undefined 3 L L H HHH Extended Supervi
50. M 9 51 VIC TONER 4 11 44 PCMCIA 45 VIC Timer 10 50 Power On Initialization 12 21 PODE neat mer re 13 access 29 S A SIN na 3 25 VMEbus Interface 11 p tehar ele Meet eet 13 VMEbus Interrupt Sources 73 R VMEbus Master Interface 11 RAMI ses test 7 39 41 VMEbus Slave Interface 11 RAM UEM 41 e 47 RDY sch Melia ts Shes OE ds 48 E 45 Real Time Clock 51 Watchdog 54 REG edes e E pod 50 4 Relative Address 45 e eI e gt 50 Reset uui eiu dave 10 68 us reuse Wed e ede 4 NE PSG Nerei 55 gives Oba ee al ad aD 6 X RMOI REC UC s 12 XON XOBE dau e rS bes 9 ROMed application 13 101 Hardware Manual ELTEC 40 60 A 4 References ELTEC A 4 References For more information we recommend the following additional literature MC68 EC LC 040 M68040UM AD Microprocessors User s Manual MC68 EC LC 060 M68060UM AD Microprocessors User s Ma
51. ROM eed bales 9 1 3 12 VIC Timers crank ea als ote etr SER ERU LR RU cR ADEL ER SORS 10 1 3 15 Watchdog Time tii oou v eme od ede e eee 10 1 3214 Status DISPLAY 10 ELTEC Hardware Manual I Table of Contents Continued BAB 40 60 Page 1 3 15 JReSet sete one xe UR RD Bien Lee aes Oe 10 1316 VMEbus Interface do Rete e te era dee Re 11 1 3 16 1 System 1 11 1 3 16 2 VMEbus Master 11 1 3 16 3 VMEbus Slave 11 1 37 15 5 Interrupt SOULCES E AO ET AR t a EDT Rb NEUE RE 11 1 3 18 BAB Extension Bus 11 1 3 19 Softwares Ae deus THREE ES VES 12 1 3 20 up Nee ees 14 14 Definition of Board 21 Lab VMEBUS eso sc tate ee ete e t ar 21 14 27 S ue erected oon b dr Mee tonno dun iet tob ied 22 k43 Bthermet 22 L44 SCSLilossizcsugeixcea Seon 22 I EV EMEN SILIO Cx E 22 1 426 MITBE Vales 5 ots o sure pe x Sea SAP URDU S 22 147
52. Register Address 31 8 7 5 4 3 2 0 ICR FEC7 00A8 used for IOC 2 000 ELTEC initial version 0 0 25 2 used for IOC 2 internal internal purposes 00 1 EUROCOM 17 1xx 2xx 0 1 33 MHz purposes 100 BAB 40 60 xxx 1 0 40MHz other reserved 1 1 reserved If bits 5 7 of the ICR are 90100 extended revision information is available at the serial EEPROM The serial EEPROM is a 512 B FRAM which is used to store ELTEC specific board revision information For the user the upper 256 B of the FRAM are reserved to store additional information The lower 256 B of the FRAM contain the extended board revision information These factory settings must never be modified by the user to guarantee system consistency Because the FRAM can only be handled via an PC bus protocol data should only be modified using the implemented RMon utilities For this see RMon Documentation The FRAM is controlled in detail by the signals SDIO and SCLK These signals can be set via a register at address 5 4000 Table 34 Control Register Layout Register Address 7 2 1 0 2 Control FEC5 4000 unused SCLK SDIO 56 Hardware Manual ELTEC 40 60 ELTEC Table 35 Address Map of the Serial EEPROM 3 Programmers Reference Offset Size Usage Address Byte 000 8 Initialization 008 2 Revision code of structure 00A 2 Size of CRC calculation 00C 4 CRC 010 16 Board revision information 020 16 Opti
53. Size of VMEbus slave extended address range in 16 MB RAM Address 0000 0 7 Default Data 04 64 MB A32 slave window size Definition unsigned char vme enable Description VMEbus slave access enable flags bit 2 ICF1 bit 0 extended other bits are reserved RAM Address 0000 0 8 Default Data 05 enables ICF1 and extended Definition unsigned long user hook 6 Description Pointer list to user hooks hook 0 init hook 1 entry hook 2 reserved reserved reserved reserved reserved company name board name portation RAM Address 0000 0B48 0000 0B6F Default Data FFFF FFFF SFFFF FFFF S FFFF FFFF SFFFF FFFF FFFF FFFF SFFFF FFFF SFFFF FFFF SFFFF FFFF FFFF FFFF FFFF FFFF Hardware Manual 81 3 Programmers Reference BAB 40 60 3 21 4 Group D Boot Parameters 0000 0B70 0000 0C57 3 21 4 1 Autoboot Flag Definition unsigned char autoboot Description Autoboot flags Bit 7 Not autoboot Bit 1 debug output Bit 0 OS 9 debug enable This value is configurable by means of the setup utility 1 RAM Address 0000 0B70 Default Data 82 3 21 4 2 Operating Definition unsigned char os System Description Operating system FF OS 9 FE LynxOS bootloader not implemented This value is configurable by means of the setup utility RAM Address 0000 0B71 Default Data SFF 3 21 4 3 SCSI Def
54. U are automatically converted into two word or four byte accesses on the PCMCIA card depending on the address space and the IOCS16 signal Pin 16 of the card interface is routed to the IRQ3 pin of the VIC This pin can be used as interrupt request IREQ for I O cards or to support RDY BSY handshake in memory applications The RESET signal is generated depending on the CPU reset signal and bit 3 of the control register Status change battery voltage detect card detect and other features are supported by using control registers The standard address window for one PCMCIA socket on ELTEC s CPU boards offers 4 MB The PCMCIA uses the following relative address space Figure 6 Relative Address Space Relative Address Access to 40 0000 Socket config y o 30 0000 PCMCIA I O y o 20 0000 common or MEMORY attribute 00 0000 Hardware Manual 45 3 Programmers Reference BAB 40 60 The PCMCIA interface offers four configuration registers Figure 7 PCMCIA Interface Configuration Registers Relative Address Access to 30 0001 Card Control Register CCR 34 0001 Card Status Register CSR 38 0001 Interrupt Vector Register IVR 3C 0000 Window Register WIR 3 4 3 Control This register is used to select the PCMCIA command timing V pp voltage Register CCR and to control the state of the RESET Figure 8 Card Control Register CCR 7 6 5 4 3 2 1 0
55. YSCLK SYSRESET bus time out IACK daisy chain driver and a four level arbitration circuit System controller capabilities are enabled by inserting jumper J301 SYSCLK The SYSCLK is always driven if the system controller is enabled SYSRESET A low level on this signal resets the internal logic and asserts the local reset for a minimum of 200 ms If the VIC is configured as system controller the reset switch on the front panel S4 asserts the SYSRESET for a minimum of 200 ms Writing a SFO to the system reset register of the VIC at address FECO 10E3 resets all registers of the VIC and asserts the SYSRESET output for a minimum of 200 ms BTO The VIC includes two independent bus time out modules BTO for local cycles and for VMEbus cycles The VMEbus time out is only enabled when the VIC is configured as system controller On VIC reset the VMEbus time out period is set to 64 is and the local bus time out period to 32 us This can be altered by programming the transfer time out register of the VIC at address FECO 10A3 Use the RMon setup menu to change this value Four Level Arbiter If the VIC is configured as system controller the four level arbiter is enabled and programmed by writing into the arbiter requester configuration register at address FECO 10B3 Use the RMon setup menu to change this value 42 Hardware Manual ELTEC 40 60 3 3 2 VMEbus Master Interface 3 3 2 1 Longword Access to Wordwide Slaves
56. al BAB 40 60 ELTEC BAB 40 60 List of Tables List of Tables Page Table 1 CAS2 Operations on the Various Busses 6 Table 2 Usable Bandwidth of the 7 Table 3 6 Pin Telephone Jack Connector CHAN 1 MOUSE RS 232 PORT 701 14 Table4 15 AUI Connector ETHERNET X801 14 Table 5 9 Min D Connector male CHAN 2 702 15 Table 6 Pin Assignment of VMEbus Connector 101 16 Table 7 Assignment of Connector 102 17 Table 8 Pin Assignment of Power Connector 103 18 Table 9 Assignment of BGB 201 18 Table 10 Pin Assignment of BEB 222 1 19 Table 11 SCSI Connector 8 bit X103 on 200 20 Table 12 Recommended 8 68 26 Table 13 Default Settings eer eur DET UE ALPE UD eee e 31 Table 14 1301 System 33 Table 15 J701 CHAN 2 DCD DSR Select 33 Table 16 J702 CHAN 2 DCD Receive Clock
57. are handshake 9 b rst mode uc IY ues 7 I H BW 48 ICET d coder 25245 m La deeds 40 IG RU cider Tout 66 C Interrupt Sources 11 6 43 05 255 2 IM 65 OC PEE 46 I2 due 65 CD ende rur en cicada tag Reeth detest he 48 1065 16 eRe Beds 45 eee 9 53 ust dente dente es dedu 65 Configuration 12 IODCRE cR ce 65 Configuration Registers 46 IODCR2 BEE EL 65 C OnDBEeCtOES Dive IRR 14 IODGR3 4 Gd sent t eet qe 65 EP Scr Ness te a Nc de a t 6 4 2 mater 65 48 IODGR5 ren ur EA s 65 OE morus sten dome a Aas os eek HEC Ss 46 3 o etr hdd ob eter 65 rs issn NN eU SE 46 IODGCRT 2 dine Rn ies D st 65 D IODGRS 65 5 eMe 65 Deadlock Resolution 74 donde HAs DAN 3 11 IODCRIO v 65 IODGCRIT 1 ires 66 E bo hee 66 iier ge eR 66 Bea ce EU DG 45 25 estie ex 66 IIR EEG he
58. are written in hexadecimal notation and identified by a leading dollar sign Signal names preceded by a slash indicate that this signal is either active low or that this signal becomes active with the trailing edge bit byte kilo means the factor 400 in hex 1024 decimal mega the multiplication with 100 000 in hex 1 048576 decimal MHz 1 000 000 Hertz Board specific abbreviations ASR Address Substitution Register AUI Attachment Unit Interface BEB BAB Extension Bus BGB BAB Graphic Bus BLT Block Transfer BTO Bus Time out CAS Column Address Strobe CAS2 Compare and Swap 2 Instruction CLUT Color Look up Table CPU Central Processing Unit CSR Control Status Register CTS Clear to Send DAC Digital to Analog Converter DMA Direct Memory Access DTE Data Terminal Equipment EEPROM Electrically Erasable Programmable Read Only Memory EPROM Erasable Programmable Read Only Memory ESR Enable Slave Register FIFO First In First Out FPU Floating Point Unit IACK Interrupt Acknowledge ICF Interprocessor Communication Facility ICGS Interprocessor Communication Global Switches ICMS Interprocessor Communication Module Switches ILACC Integrated Local Area Communications Controller 2 Controller Asic Hardware Manual XIII Conventions Continued XIV LAN LIRQ MAU MBAR MMU NVRAM PCB PCMCIA PLD PLL RAM RAS RMC RTC RTS SBR SCSI SCR SILC SRAM SMR TTL VIC VRAM UAT BAB 40 60
59. ault Parameters of RMon 2 8 located on BAB 40 60 Beginning End Description Group A I O Initialization 0800 087F VIC parameter 0880 088F reserved 0890 08AF SCC port A parameters 08BO 08CF SCC port B parameters 0800 090 reserved 0910 092F CIO parameters 0930 094F reserved 0950 0951 SCSI chip parameter 0952 reserved Group B Address Information 0AF1 ICF1 address 0AF2 reserved reserved 4 5 A32 slave address 0AF6 reserved 0AF7 VME A32 slave size 0AF8 VME enable bits 9 50847 reserved Group C Hooks 50848 4 User hooks 0B50 0B63 reserved 0B64 0B67 Company name 50868 6 0B6C 0B6F Portation ELTEC Hardware Manual 75 3 Programmers Reference BAB 40 60 Table 49 Default Parameters of RMon 2 8 located on BAB 40 60 Beginning End Description Group D Boot Parameters 0B70 Autoboot flags 0B71 Operating system 0B72 SCSI controller ID 0B73 SCSI controller Hardware 0B74 SCSI logical unit number 0B75 Special boot flag 0B76 Sector size unused 0B78 Base address for RAM ROM boot 0B7C Own SCSI ID 0B7D Retry counter for NetBoot 0B7E Delay
60. ctions The longword accesses have to be split by software into two word accesses which slows down the performance Instead of this the IOC 2 hardware generates the needed bus cycles if the addressed device acknowledges a smaller data size than the CPU requested One of the main design goals of the BAB 40 60 is efficient use of the CPU s high speed bus Thus the following design rules are established Use of intelligent peripheral devices which are able to perform tasks independent from the main CPU NCR 53C710 ILACC Independent 68020 like bus for VMEbus Ethernet or BEB with separate arbitration Minimum interference between CPU bus 020 bus and I O bus Decoupling of VMEbus and CPU bus via FIFO for BLT On traditional designs there could only be one bus master on the whole board at a time For example if a BLT was in progress the CPU was blocked for the duration of the BLT At the BAB 40 60 the FIFO in the IOC 2 collects the data while the CPU still accesses the DRAM Hardware Manual 3 1 Specification BAB 40 60 In order to enhance system security the BAB 40 60 incorporates a watchdog timer It must be retriggered periodically otherwise the watchdog generates a reset Two serial ports are located on the BAB 40 60 One using a 6 pin shielded RJ11 jack on the front panel is intended for connection of a terminal or a mouse The other uses a 9 pin Min D male connector on the front panel It can be configured
61. d in 1962 and has been widely used throughout in industry RS 232 was developed for single ended data transmission at relatively slow data rates 20 Kbit s over short distances lt 15 SILC 300 for RS 422 V11 RS 422 was defined for differential data transmissions at high data rates over long distances and through noisy environment RS 422 allows data rates up to 10 Mbit s 12 m and line lengths up to 1200 m 100 Kbit s The SILC 300 driver is designed to drive a party line with ten receivers RS 422 devices cannot be used to construct a truly multipoint bus with multiple driver and receiver It is V11 compatible Cable termination is necessary for longer distances SILC 400 for RS 485 RS 485 was defined for truly multipoint communication RS 485 meets all the requirements of RS 422 but in addition this new standard allows up to 32 drivers and 32 receivers to be connected to a single bus thus allowing atruly multipoint bus to be constructed Cable termination is necessary for longer distances Hardware Manual 61 3 Programmers Reference 3 11 2 1 SILC Installation 62 BAB 40 60 The mechanical part of the installation is very easy First switch off the VMEbus system and pull the board on which the SILC module shall be installed or changed out of the rack If a SILC module is already placed in the connector remove it carefully Now plug the new SILC module into the corresponding connector on the CPU or I O board Conside
62. e PCMCIA Interface EPROM Graphics Keyboard Interface optional Ethernet Interface SCSI Interface Serial 1 0 CIO Counters Timers Parameter RAM and Real Time Clock Revision EEPROM VIC Timer Watchdog Timer Status Display Reset VMEbus Interface Interrupt Sources BAB Extension Bus Software Connectors Hardware Manual 1 Specification 1 Specification BAB 40 60 13 1 CPU The BAB 40 60 is equipped with Motorola s 68040 060 CPU clocked with 50 or 66 MHz internal bus operations are synchronous to this clock The CPU uses burst mode to access the main memory The BAB 60 uses the 68040 bus mode of the 68060 The CPU handles all interrupts generated by the VIC Non interruptable read modify write cycles TAS command supported between VMEbus and the CPU RMC cycles from the VMEbus to the local RAM are only indivisible when they are byte size CAS2 instructions have limited support Table 1 CAS2 Operations on the Various Busses 1st op 2nd op indivisible local RAM local RAM yes 020 bus BEB local RAM yes VMEbus local RAM yes local RAM 020 bus BEB no 020 bus BEB 020 bus BEB yes VMEbus 020 bus BEB yes local RAM VMEbus no 020 bus BEB VMEbus no VMEbus VMEbus yes Hardware Manual ELTEC 40 60 1 3 2 RAM Module ELTEC 1 Specification The DRAM is accessed by the following sources CPU SCSI Controller Ethernet Con
63. eaning Bit Position Mnemonic Meaning 0x0000 HPOS Horiz sync is positive 0x0002 VPOS Vert sync is positive 0x0004 GSYNC Sync on Green 0x0008 CSYNC Composite Sync 0x0010 TSYNC Tessellated Sync 0x0080 DBLANKP Disable blank pedestal RAM Address 50000 0 0 0000 0CFF Default Data 2575000 640 800 96 48 480 525 2 33 0 0000 0 0 0 0 0 0 It depends on the installed graphic module if changes at the video timing parameter also effect the hardware Hardware Manual 93 3 Programmers Reference 3 21 6 11 Keyboard Typamatic Rate 4 3 21 6 12 Keyboard Language 3 21 7 Checksum E 94 BAB 40 60 Definition unsigned char kbrate Description If this location is set to a value other than FF it is sent to the keyboard after the set typamatic rate delay command code F3 RAM Address 0000 0DA0 Default Data 00 30 codes per second after 250 ms delay Definition unsigned char kblang Description Keyboard language setting Valid values FF American keyboard vt100 FE German keyboard vt100 EF American keyboard mgr SEE German keyboard mgr RAM Address 0000 0 Default Data SFF Definition unsigned long checksum Description NVRAM checksum This value is read only and is set or compared by the RMon commands re or we respectively RAM Address 0000 0 0000 0BFF Default Data SFFFF FF
64. ence 3 21 5 2 Watchdog Enable Flag 3 21 5 3 Watchdog Time Out Period 3 21 5 4 Internal Board Information 88 40 60 Definition unsigned char wdog enable Description Enable watchdog timer Bit 0 0 watchdog disabled Bit 0 1 watchdog enabled RAM Address 0000 0 5 Default Data 00 Definition unsigned long Wdog time Description Watchdog time out period in milliseconds RAM Address 0000 0C5E Default Data 0082 130 ms time out Definition unsigned char board info 0x20 Description ELTEC internal board information for service purposes These values should not be modified RAM Address 50000 0 68 0000 0C87 Default Data 30 41 41 31 31 31 30 30 30 30 30 30 30 30 SFF SFF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Hardware Manual ELTEC 40 60 3 21 5 5 Ethernet Node Address 3 21 5 6 CPU Board Identification 3 21 5 7 Base Address ELTEC d 3 Programmers Reference Definition unsigned char ethernet addr 6 Description Copy of the boards Ethernet node address Read from the EEPROM during startup RAM Address 0000 0 88 Default Data SFF FF FF FF FF FF Definition unsigned char board id Description Unique number for each hardware platform Valid values 13 E16 14 IBAM 30 15 17
65. ents in life support devices or systems intended for surgical implant into the body or intended to support or sustain life Buyer agrees to notify ELTEC of any such intended end use whereupon ELTEC shall determine availability and suitability of its product or products for the use intended ELTEC points out that there is no legal obligation to document internal relationships between any functional modules realized in either hardware or software of a delivered entity This document contains copyrighted information All rights including those of translation reprint broadcasting photomechanical or similar reproduction and storage or processing in computer systems in whole or in part are reserved EUROCOM is a trademark of ELTEC Elektronik AG Other brands and their products are trademarks of their respective holders and should be noted as such 1995 ELTEC Elektronik AG Mainz E N ELTEC Elektronik AG Galileo Galilei Str 11 Postfach 42 13 63 D 55129 Mainz D 55071 Mainz Telephone 49 6131 9 18 0 Telefax 49 6131 9 18 199 ES A BAB 40 60 Table of Contents Table of Contents Page T ble of Contents UR se RU bue ide ot RR I ListotXT bles e Nee Ne Eae ERR He RP E Beh esee SUR EDS VII List Of uoa onn RIA due RAP Lares Bele RENE n LI M SE IX Scope or Delivery zz cioe der xeu eee AUR de UR PREDA XI dun
66. er Dynamic bus sizing for VMEbus and BEB Translation of BLT into bursts on 040 bus to allow snooping of BLT cycles Separate arbitration on 040 and 020 bus I O bus interface Support for VMEbus UATS to allow snooping Interface for a single bytewide EPROM Three 16 bit timer counter Two serial ports RS 232 RS 422 RS 485 Smart SCSI 2 NCR 53C710 interface with burst capability max transfer capacity 10 MB s and single ended 8 bit SCSI data bus Two rotary switches for selection of operation modes and base address Status display on front panel Watchdog timer 130 ms 17 min BEB for interfacing to various mezzanine busses BGB for graphic and keyboard module ELTEC Hardware Manual 1 1 Specification 1 2 General Description Figure 1 Block Diagram CPU Memory NCR53C710 8 bit SCSI 2 68040 060 Module SCSI 50 66 MHz 1 32 MB Controller Front 040 Bus Panel S remm 8536 10C 2 Watchdog Slave Operation 1M x 8 VMEbus Mode EPROM Controller 32KB 2KB x 8 NVRAM VMEbus 0 RTC Buffer Count o p SILC L Decoder 2 Revision Controller EEPROM Serial Line A Ethernet 020 Bus U pees Controller 1 Graphic Module 512 1 G Mu VRAM A Video Contr Keyboard Controller Keyboard PCMCIA2 mm
67. essing from the BEB In this case only parts of the DRAM can be reached by VMEbus A32 addressing or the ILACC To avoid problems ELTEC recommends that DMA BEB boards should deliver at least AO to A26 for operation with the default configuration 40 Hardware Manual ELTEC 40 60 3 24 RAM Mirror 3 2 5 Access from the BEB 3 2 6 RAM Access from ILACC ELTEC 3 Programmers Reference In some cases it may be desirable to prevent caching of data that are shared with other devices BEB VMEbus ILACC In these cases the cache inhibited RAM mirror can be used Access from the BAB Extension Bus BEB is done by using a standard 68k like requester with three line handshake BR BG BGACK During master transfers from the BEB a minimum of 24 address lines A23 have to be driven For operation with the default configuration 64 MB slave window at least AO to A26 have to be driven see Section 3 2 3 Address Translation The AM79C900 Ethernet Controller uses DMA transfer cycles to transfer commands data and status information to and from the DRAM Hardware Manual 41 3 Programmers Reference BAB 40 60 3 3 VMEbus Interface Each BAB 40 60 has a VMEbus master and a VMEbus slave interface Additionally VMEbus system controller functions are available via the VMEbus gate array VIC used on the BAB 40 60 board 3 3 1 System The BAB 40 60 features a full slot one system controller including Controller S
68. ff Oxff Oxff Oxff Oxff Oxff BAB 40 60 0x57 Ox7 0x13 0x53 Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff ELTEC 40 60 3 21 1 2 SCC Port A Parameter 3 Programmers Reference Definition struct io data sccla 0x10 Description Initialization values for SCC port A First member is value second member is SCC register number Register number 1 marks end 3 21 1 3 SCC Port B Parameter 3 21 1 4 CIO Parameter ELTEC RAM Address 0000 0890 0000 08AF Default Data 0x80 0x09 0x46 0x04 0 1 0x03 0x05 0x56 Ox0b 0x00 OxOdj 0x03 0 0 0x00 OxOf Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Definition struct io data scclb 0x10 Description Initialization values for SCC port B First member is value second member is SCC register number Register number 1 marks end RAM Address 0000 08 0 0000 08CF Default Data 0x40 0x09 0x46 0x04 0 1 0x03 0x05 0x56 0x00 OxOdj 0x03 0 0 0x00 0 0 Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Definition struct io data ciol 0x10 Description Initialization values for CIO First member is value second member is CIO re
69. gister number Register number 1 marks end RAM Address 0000 0910 0000 092F Default Data 0x88 0x40 Oxff 0x41 Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Hardware Manual 79 3 Programmers Reference BAB 40 60 3 21 2 Group B Address Information 0000 0AF0 0000 0B47 3 21 2 1 ICF1 Address Definition unsigned short icfl_addr Description Slave address of ICMS in VMEbus short I O range Only bits 15 6 are used for A15 A6 of slave address By default RMon enables this slave access RAM Address 0000 0AFO0 0000 0AF1 Default Data 8000 This value may be overwritten depending on the setting of hex switch 5901 3 21 2 VMEbus A32 Definition unsigned short ext addr Slave Address Description Slave address of VMEbus extended I O range Only bits 15 4 are used for A31 A20 of slave address By default RMon enables this slave access RAM Address 0000 0AF4 Default Data 8000 This value may be overwritten depending on the setting of hex switch 5901 80 Hardware Manual ELTEC 40 60 3 21 2 3 VMEbus A32 Slave Size 3 21 2 4 VMEbus Enable Bits 3 21 3 Group C Hooks 0000 0B48 0000 0B6F ELTEC 3 Programmers Reference Definition unsigned char ext size Description
70. h PC3 0 Output DISPLAY Write LEDs on Front Panel All outputs of the CIO are pulled high to ensure a valid logic level after reset 70 Hardware Manual ELTEC 40 60 3 Programmers Reference 3 19 Interrupt Sources All seven priority levels of the VMEbus are implemented The local modules are served by interrupts without restricting the VMEbus interrupt capacity The interrupt handler is a part of the VIC gate array This device contains seven registers to handle seven VMEbus interrupt sources Each IRQ line on the VMEbus is enabled and disabled separately Additionally the level passed to the CPU is changed for each of these lines through the control registers of the VIC The VIC also supports seven local interrupt request inputs called LIRQ1 to LIRQ7 These lines are connected to several local devices generating an IRQ referenced by Table 47 VIC Interrupt Priority Scheme Additionally the VIC generate local interrupts from eight interprocessor communication registers ACFAIL SYSFAIL arbitration time out posted write cycles and DMA completion To change the IRQ values in the VIC registers use the RMon setup menu Refer to the VICO68 data sheet for more information ELTEC Hardware Manual 71 3 Programmers Reference 72 Table 47 VIC Interrupt Priority Scheme BAB 40 60 IRQ Source Generated Vector CPU Level s
71. has only limited support see Table 1 CAS2 Operations on the Various Busses The easiest way to ensure that CAS2 instructions are indivisible is to have both operands of the CASA instruction within the same memory area local RAM VMEbus BEB Hardware Manual 43 3 Programmers Reference 3 3 2 4 A16 Slave 44 Interface ICMS BAB 40 60 A very useful feature of the VIC is a set of registers and switches for message passing or event signaling There are eight bytewide general purpose interprocessor communication registers accessible from the VMEbus or the local bus CPU Registers 0 to 4 are general purpose dual port registers Register 5 is a dual port read only ID register to identify the VIC and its revision level Register 6 is a module status register which is read only from the VMEbus Register 7 provides semaphores for registers 0 4 and several system control functions like a remote reset function Four Interprocessor Communication Module Switches ICMS are provided by the VIC These are bytewide mailbox switches to signal events by generating an interrupt to the local CPU if accessed from the VMEbus To signal dedicated events messages the ICMS locate a unique set of addresses The intercommunication registers within the VIC chip are accessible in A16 VMEbus address space only For programming the ICF decoder registers see the description of the slave base address register slave mask regi
72. he BAB 40 60 Although the BAB 40 60 RAM design has been optimized for compatibility layout of the SIMM s PCB and the type of the RAM chips may affect reliability Therefore ELTEC can t guarantee operation with all available SIMM modules It is recommended to use SIMMs of well known manufacturers Fujitsu Hitachi Toshiba Samsung TI Hardware Manual ELTEC 40 60 212 PCMCIA Installation gt ELTEC 2 Installation The PC Cards can easily be plugged into one of the three sockets when they have the right orientation To avoid unintended removal of the PC Cards on the front they can be locked with a metal plate and two screws M3x6 The internal PC Card can also be fixed to withstand shock and vibration For correct distance of the PC Card and the PCB a washer 15 necessary between the PCB and the holder Figure 2 PCMCIA Installation Holder PC Card Washer PCB Screw M2 5 x 6 Live insertion and removal of PC Cards is possible while none of the PC Cards is accessed by the CPU Since it is not easy to satisfy this condition it is recommended to avoid live insertion and removal When type III PC Card is installed in the internal socket the VMEbus specification of the adjacent VMEbus slot is violated so that it must stay free Not all type III PC Cards fit into the internal socket Only 5 V supply voltage cards are supported For a detailed list of cards and
73. he character window is placed in the center of the display window 01 The following two values specify the position of the character window within the display window RAM Address 50000 0 3 Default Data 0 Definition unsigned short rto wdworgx rto wdworgy Description Position of the left upper pixel of the character window within the display window RAM Address 0000 0 0000 0CB7 Default Data 0 0 Hardware Manual ELTEC 40 60 3 21 6 10 Video Timing Parameter ELTEC 3 Programmers Reference 1 Definition unsigned long rto param 0x38 Description Video Timing description The values within this array have the meaning RAM Address Mnemonic Meaning Unit 0000 0CCO pfreq Pixel Frequency Hz 0000 0CC4 hres Horiz Resolution pixel 0000 0CC8 hperiod Horiz Period pixel 0000 0CCC hsync Horiz Sync width pixel 0000 0CDO hbporch Horiz Back Porch pixel 0000 0CD4 vres Vert Resolution lines 0000 0CD8 vperiod Vert Period lines 0000 0CDC vsync Vert Sync width lines 0000 0CEO vbporch Vert Back Porch lines 0000 0CE4 syncmode Sync Mode 0000 0CE8 eqlen Equalization width pixel 0000 0CEC serlen Serration width pixel 0000 0CFO eqstart Equalization start lines 0000 0CF4 eqserin Equ Ser interval lines 0000 0CF8 vres 2 reserved The bits of the syncmode 0000 0CE4 have the following m
74. he oe hu e bc S a hes 45 341 Interface Description casy sies nex mne RR as 45 34 2 Address RAN E o pee ER a aed MR RISE de 45 3 4 3 Card Control Register 46 3 4 4 Status Register 1 48 ELTEC Hardware Manual Ill Table of Contents Continued 3 5 3 6 3 7 3 8 3 9 3 10 3 12 3 14 3 16 3 17 3 19 3 4 5 Interrupt Vector Register IVR 3 4 6 Window Register VIG TAM c PC PPP Battery Backed Parameter RAM and Real Time Clock 3 6 1 Parameter RAM NVRAM 3 6 2 Real Time Glock CIO Counter Timer 2 oc ke eee ey Watchdog Timer LER SMOD SEA DIR P Ie Revision Cache Coherency and Snooping Serial DO nist i TI 3 11 1 Serial Communication Controller SCC 3 11 2 Serial Interface Level Converter 51 3 11 2 1 SILC Installation System Control Register 5 Interrupt Sources e e Rs ER 3 19 1 Local Interrupt 3 19 2 VMEbus Interrupt Sources Hardware Manual BAB 40
75. ice Control Register 2 0000 0000 70010 IODCR3 Device Control Register 3 0000 0000 70014 IODCR4 Device Control Register 4 0000 0000 70018 IODCR5 Device Control Register 5 0000 0000 7001C IODCR6 Device Control Register 6 0000 0000 70020 IODCR7 Device Control Register 7 0000 0000 70024 IODCR8 Device Control Register 8 0000 0000 70028 IODCR9 Device Control Register 9 0000 0000 7002C IODCR10 Device Control Register 10 0000 0000 1 Default register value FECO 0000 ELTEC Hardware Manual 65 3 Programmers Reference 66 BAB 40 60 Table 44 Register Map Continued Offset Addr Symbol Name Reset Value 70030 IODCR 1 1 Device Control Register 11 0000 0000 70034 IODCR12 Device Control Register 12 0000 0000 70038 IOIACR IACK Control Register 0000 0000 7003C reserved 70040 EBARO EPROM Begin Address Register 0 0000 0000 70044 EMARO EPROM Mask Register 0 0000 0000 70048 EDCRO EPROM Device Control Register 0 0000 020F 0000 0A0F 7004C reserved 70050 EBARO1 EPROM Begin Address Register 1 0000 0000 70054 1 Mask Register 1 0000 0000 70058 EDCR1 EPROM Device Control Register 1 0000 020F 0000 0A0F 7005C zs reserved 7009C Address Bus Interface Registers 700A0 MBAR Memory Base Address Register 0000 0000 700A4 ASR Address Substitution Register FF80 0
76. inition unsigned char conid Controller ID Description Controller ID This value is configurable by means of the setup utility RAM Address 0000 0 72 Default Data 06 82 Hardware Manual ELTEC 40 60 3 21 4 4 SCSI Controller Hardware 3 21 4 5 SCSI Logical Unit Number 3 21 4 6 Special Boot Flag ELTEC 3 Programmers Reference Definition unsigned char conhard Description Controller hardware 00 Omti 01 SCSI Harddisk 02 SCFL 03 TEAC SCSI Floppy This value is configurable by means of the setup utility RAM Address 0000 0 73 Default Data 01 Definition unsigned char lun Description Logical unit number Valid values 00 20 40 60 This value is configurable by means of the setup utility RAM Address 0000 0B74 Default Data 00 Definition unsigned char specboot Description Special bootstraps FF None FD Streamer tape FE Ramdisk FC Ethernet ROM boot wait for NMJ FA Direct ROM boot F0 PCMCIA interface This value is configurable by means of the setup utility RAM Address 0000 0B75 Default Data SFF Hardware Manual 83 3 Programmers Reference 3 21 4 7 Sector Size 3 21 4 8 Base Address of RAM ROM PCMCIA Boot 3 21 4 9 Retry Counter for Network Boot 3 21 4 10 Delay until Auto Starts 84 BAB 40 60 Definition unsigned short sec
77. inued 3 21 5 5 Ethernet Node Address 3 21 5 6 CPU Board Identification 3 21 57 RMon Base Address 3 21 5 8 Size of Local 3 21 6 Group F Video 3 21 6 1 Graphic 3 21 6 2 Graphic Bit Mode 3 21 6 3 Display Start Address 3 21 6 4 Size of Graphic Plane 3 21 6 5 Size of Display Window 3 21 6 6 Number of Fore Background Color 3 21 6 7 Number of Columns and Lines 3 21 6 8 Video Descriptor Format 3 21 6 9 Position of Character Window 3 21 6 10 Video Timing Parameter 3 21 6 11 Keyboard Typamatic 3 21 6 12 Keyboard 3 21 7 Checkstim Ak SERRA ERR MR Appendix Mnemonics Chart Addressing A 1 2 Data Transfer ACE Glossatysso os Lorie doa repens debe eta 2 Address Modifiers on VMEbus nde ome eub AA References eus Ves sve REG oae dp De tea Technical Action Request Form Sheet Reader Comments Form Sheet VI Hardware Manu
78. ive clock of SCC Hardware Manual 33 2 Installation BAB 40 60 Table 17 Y703 DTR Transmit Clock Select Jumper J703 Function 1 2 DTR of SCC is connected to SILC 2 3 Transmit clock of SCC is connected to SILC Figure 5 Serial Interface CHAN 2 Configuration SCC SILC 9 pin Sub D 5 MHz PCLK TxD gt gt DU xD RxD RxD a lt 2 RxD RT RTS gt ee 7 RTS CTS CTS H 8 CTS J703 lt DTR gt O 1 gt gt 4 DTR 2 J701 DSR DCD 4 rm 310 6 nc Q3 J702 lt 2 SYNC 1y 1 DCD 2 1 RI TRxC gt 3 9 RTxC x 4 5 GND W REQ 40 60 with SILC 200 7 3728 MHz 34 Hardware Manual ELTEC 40 60 2 3 3 2 3 4 2 3 5 2 3 6 Reset 11401 Pin 1 Connection of EPROM J1605 EEPROM Write Enable J1702 Switches 2 3 6 1 VMEbus Slave Address S901 ELTEC 2 Installation When J1401 is closed or an external switch is connected to J1401 reset can be generated Table 18 11401 Reset Jumper J1401 Function open Normal operation closed Reset This jumper allows to select between EPROMs up to 4 Mbit and 8 Mbit Table 19 11605 Pin 1 Connection
79. llows the changeability of the different SILC modules on the BAB 40 60 SILC 200 for RS 232 SILC 300 for RS 422 SILC 400 for RS 485 The mechanical part of the installation is very easy First switch off the VMEbus system and pull the board out of the rack If a SILC module is already placed in the connector remove it carefully Now plug the new SILC module into the corresponding connector on the CPU or I O board Consider the polarization of the SILC module To avoid damage check that the pin 1 marked on the back of the SILC fits to pin 1 marked on the board Hardware Manual ELTEC 40 60 2 1 55 Ethernet Installation 2 1 6 SCSI Installation ELTEC 2 Installation A standard Ethernet Cheapernet MAU or a CONV 500 Cheapernet 10BaseT MAU can be connected via AUI cable to the 15 pin AUI connector on the front panel of the BAB 40 60 The length of the AUI cable is limited to 50 m For connections up to about 2 m flat cable can also be used In order to avoid HF radiation this cable should be shielded A 8 bit SCSI bus can be connected to X103 of ADAP 200 If the BAB 40 60 is located at either end of the SCSI bus the termination must be enabled in the RMon setup menu otherwise it must be disabled Hardware Manual 29 2 Installation BAB 40 60 Figure 3 Installation Diagram S902 S901 U903 X702
80. nditions Reset Source Affected Device Voltage Drop 4 75 V CPU SCC CIO Keyboard and Video Controller or Power up SCSI Controller or Reset Switch J1401 ILACC VMEbus SYSRESET if system controller Watchdog Indicator VMEbus Slave Decoder BEB VIC Remote Control Reset CPU SCC CIO Keyboard and Video Controller or SYSRESET SCSI Controller ILACC Watchdog Indicator BEB Watchdog Reset CPU SCC CIO Keyboard and Video Controller SCSI Controller ILACC BEB CPU SCSI Controller ILACC Hardware Manual ELTEC 40 60 3 Programmers Reference 3 17 Bus Time Out The BAB 40 60 features two independent software programmable bus time out modules one for the local time out and one for the VMEbus time out Both time out modules are located in the VIC and are programmed by writing the transfer time out register SFECO 10A3 The time out period is programmable from 4 us to 480 us Local time out is not generated when waiting for VMEbus mastership This is programmable within the VIC chip Local time out is set to 32 us and the VMEbus time out is set to 16 us by RMon Use the RMon setup menu to change these values The VMEbus time out is generated by the system controller and therefore is only used if the VIC is being used as the system controller Jumper J301 is used to enable disable the board s system controller Access to the BEB BGB triggers the local BTO generator ELTEC
81. nual Motorola Ltd European Literature Centre 88Tanners Drive Blakelands Milton Keynes MK14 5BP England Further specifications and extracts of data sheets are available with the Service Manual For ordering information refer to Related Products page XII Hardware Manual 102
82. of EPROM Jumper J1605 Function 1 2 Pin 1 connected to 5 V lt 8 Mbit 2 3 Pin 1 connected to A19 8 Mbit J1702 enables disables the hardware write protection for the serial EEPROM Only the upper 256 B of the EEPROM can be write protected Table 20 J1702 EEPROM Write Enable Jumper J1702 Function open Write protection enabled closed Write protection disabled Both hex switches 5901 5902 are used by RMon for the configuration setup see RMon manual They are connected to port B of the CIO The hex switch 5901 selects the BAB 40 60 slave window address The size of the A32 slave window is normally 256 MB This can be changed by the RMon setup menu The size of the A16 slave window used for VIC access is 256 bytes Hardware Manual 35 2 Installation 2 3 6 2 Hardware Configuration S902 36 BAB 40 60 Table 21 Hex Switch S901 VMEbus Slave Address Hex Switch VMEbus Base Address S901 A32 A16 F F000 0000 F000 E000 0000 E000 D D000 0000 D000 1 1000 0000 1000 0 Use configuration value Switch S902 defines the configuration source and the operation mode For switch position 0 1 RMon enters an interactive mode If switch S902 is in position 8 to F the user program located in the RMon EPROM is called Table 22 Hex Switch S902 Hardware Configuration Hex Switch Function 5902 0
83. on revision information 030 16 Option revision information 040 16 Option revision information 050 16 Option revision information 060 8 Serial number 068 8 Reserved 070 14 Revision codes 07E 2 Category codes 080 64 Text 0 0 64 Reserved 100 256 User data The user data can be stored at address offset 100 1FF To store the user data see RMon documentation for more information Hardware Manual 57 3 Programmers Reference 3 10 Cache Coherency and Snooping BAB 40 60 To maintain cache coherency in a multi master system the 040 060 has the capability of snooping Snooping can be enabled via snoop control register at SFECS5 E000 write only Bit 7 5 of the Snoop Control Register are used to select the size of the onboard SIMM module see Table 39 RAM Size Table 36 Snoop Control Register Layout for BAB 40 60 Register Address 7 5 4 3 2 E SNCR FEC5 E000 RAM Size unused unused 5 1 SCO Table 37 Snoop Control Encoding for BAB 40 Requested Snoop Operation SCO Alternate Bus Master Read Access Alternate Bus Master Write Access 0 0 Inhibit Snooping Inhibit Snooping 0 1 Supply Dirty Data and Leave Dirty Sink Byte Word Longword 1 0 Supply Dirty Data and Mark Line Invalid Invalidate Line 1 1 Reserved Snoop Inhibited Reserved Snoop Inhibited Table 38 Snoop Control Encoding for BAB 60
84. r the polarization of the SILC module To avoid damage check that the pin 1 marked on the back of the SILC fits to pin 1 which is marked on the board The following table provides information about the functionality of the pins on the SILC modules Table 42 Pin Assignment for SILCs Pin SILC 200 SILC 300 SILC 400 Signal Description Signal Description Signal Description d GND1 R B not connected 2 RxD R A not connected 3 T A A 4 GND2 T B not connected 5 not connected not connected 6 RTS C A not connected 7 CTS B 8 not connected C B not connected 9 CTS CTS pulled low 10 RxD RxD RxD 11 Voc Voc Voc 12 GND GND GND 13 not connected pulled low pulled low 14 not connected not connected not connected 15 TxD TxD TxD 16 RTS RTS pulled low Hardware Manual ELTEC 40 60 3 Programmers Reference 3 12 Ethernet Interface 802 3 10base5 The ILACC s internal registers are selected by writing the corresponding register number to address FEC6 8006 and accessed at address FEC6 8002 Both addresses must be accessed with word size instructions After initialization and starting the ILACC operates without any CPU interaction It transfers prepared data receives incoming packets and stores them into reserved memory locations To signal service requests the ILACC interrupt signal is connected to the VIC s LIRQ7 input The VIC has to
85. rated After reset the watchdog timer is disabled The time out period becomes effective after the first access to the watchdog configuration register After reset the software can read 7 of the CIO to distinguish between a watchdog reset and a reset generated by other sources This watchdog indicator is only cleared by power up reset the reset switch a VMEbus SYSRESET a VIC remote reset or by a write access to the watchdog The time out period is derived from a quartz oscillator so that tolerances can be neglected The BAB 40 60 features a four LED display on the front panel and displays values from 0 F This status display FEC3 0000 is designed as a read write register and uses the least significant nibble of the byte Reset may be initiated by six sources supply voltage drop below 4 75 V or power up reset jumper J1401 VMEbus SYSRESET VIC remote control reset register Watchdog CPU RESET instruction Hardware Manual ELTEC 40 60 1 316 VMEbus Interface 1 3 16 1 System Controller 1 3 16 2 VMEbus Master Interface 1 3 16 3 VMEbus Slave Interface 1 3 17 Interrupt Sources 1 3 18 BAB Extension Bus BEB ELTEC 1 Specification Each BAB 40 60 board offers VMEbus master and slave interfaces Additionally VMEbus system controller functions are available via the VMEbus gate array VIC The BAB 40 60 features a full slot one system controller including SYSCLK SYSRESET bu
86. ration VIC Programming Hardware Manual ELTEC 40 60 ELTEC 1 Specification Various Bootstraps OS 9 from SCSI Floppy OS 9 from SCSI Harddisk OS 9 from SCSI Tape OS 9 from ROM RAM Disk OS 9 from PCMCIA Lynx from Tape Lynx from Harddisk Lynx from Floppy tftp bootstrap from Ethernet including ARP and RARP protocols ROMed application bootstrap suitable as well for VMEbus downloaded applications under control of a VMEbus host External Callable I O Functions Enable Disable IRQs Get Device Status Set Device Mode Character Raw I O C like functions getchar putchar printf Application Hooks Application programs may freely use the externally callable I O functions and other information provided in the RMon Fixed Public Location Furthermore a ROMed application can very easily be started interactively or automatically after RESET or power on from RMon The application autostart mechanism can be installed simply by setting the respective bootstrap configuration parameters Hardware Manual 13 1 Specification 1 3 20 Connectors 14 BAB 40 60 Table 3 6 Pin Telephone Jack Connector CHAN 1 MOUSE RS 232 PORT X701 Pin Signal Description 1 RTS Request to Send 2 TxD Transmit Data 1 3 GND Signal Ground 1 4 GND Signal Ground
87. s time out IACK daisy chain driver and a four level arbitration circuit System controller capabilities are enabled when J301 is closed The master interface of the BAB 40 60 board supports 8 16 and 32 bit data transfer cycles in A32 A24 and A16 addressing modes A special feature is provided to support longword accesses from the local CPU to D16 VMEbus boards dynamic bus sizing Two control lines of the SCR enable longword breaking for the A32 and A24 area The VIC chip supplies the VMEbus address modifier signals This is done by either routing 2 line to AMO 2 or by driving these signals by internal address modifier source register of the VIC FECO 10B7 The AM3 5 lines are driven depending on the actual data size or by the address modifier source register One output signal of the system control register is used to control this option The BAB 40 60 supports slave block transfer cycles The BAB 40 60 supports A32 slave access to the DRAM and an A16 slave interface to access the interprocessor communication registers The addresses for all of the slave interfaces are separately programmable The BAB 40 60 allows full utilization of both the powerful VMEbus interrupt structure and the 68040 060 CPU design The BEB port of the BAB 40 60 can carry slave only master only or master slave boards The IRQ line of the BEB is connected to VIC s LIRQS input The VIC has to be programmed to generate interrupts on level 2
88. size Description OS 9 sector size RMon does not use this value RAM Address 0000 0 76 Default Data SFFFF Definition unsigned long romkerneladdr Description Base address of ROM kernel RAM disk or PCMCIA interface This value is used for special bootstraps SFA and FO It is configurable by means of the setup utility RAM Address 0000 0 78 Default Data 0000 0000 Definition unsigned char Description Retry counter for network boot This value is used as counter to call the network bootstrap port until the RMon is called again RAM Address 0000 0B7D Default Data 00 Definition unsigned short autob Description This value specifies the delay seconds before the autoboot sequence starts RAM Address 0000 0B7E Default Data 0009 Hardware Manual ELTEC 40 60 3 21 4 11 3 21 4 12 3 21 4 13 Own Internet ELTEC Logical Sector Offset Device Command Address L D 3 Programmers Reference Definition unsigned long lsnoffset Description Logical Sector Offset RAM Address 50000 0 80 Default Data 0000 0000 Definition unsigned char drive cmd 0x40 Description Drive commands The command list for configurated drive will be copied here by the setup utility RAM Address 0000 0B88 0000 0BC7 Default Data 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
89. sory Ascending 1 0E L L H HHL Extended Supervisory Program 1 00 L L HHL H Extended Supervisory Data 1 0 L L H HL L Undefined 2 0B L L H L H H Extended Non Privileged Ascend 1 L LHL HEL Extended Non Privileged Program 1 09 L L H L L H Extended Non Privileged Data 1 08 LE Ho E Eb Undefined 2 00 07 L x x x Undefined 2 1 Defined by VMEbus Specification 2 Definition reserved 98 Hardware Manual ELTEC 40 60 A 2 Address Modifiers on VMEbus 3 Defined by user ELTEC Hardware Manual 99 BAB 40 60 Index A 3 Index Symbols E Continued ISRDYABSY 2241 gx FEY YS 45 re s bet 66 IRESE Ata Nee 45 47 EDERT eee e E 66 EEPROM 5 9 Address Map 37 ion eui ducet pape address modifier 11 37 96 PA EPROM IRE 8 address modifier source 11 43 Lin dde 39 Address Translation 40 eter in Rhode oe 21 BADGE aise d Ethernet Interface 8 esce 40 66 qute ales 8 B Four Level Arbiter 42 Bandwidth of the RAM 7 G Board Installation 28 getchar Da Dad petias 13 Bootstrap aceite ttes 12 13 H oO udo idis 42 hardw
90. ster and enable slave select register in Section 3 2 2 RAM Access from the VMEbus Use the RMon setup menu to change the register values Within the 256 byte space the VIC chip locates several intercommunication registers Table 27 Intercommunication Register Location on VMEbus Register Type A07 06 05 04 03 02 01 5 0 Interprocessor Communication X X 0 0 2D Registers Interprocessor Communication X X 0 1 0 2D Global Switches Interprocessor Communication X X 1 0 0 2D Module Switches 29 X don t care selects register switch number For further information refer to the VICO68 data sheet Hardware Manual ELTEC 40 60 3 Programmers Reference 3 4 PCMCIA Interface 3 4 1 Interface Description 3 4 2 Address Range ELTEC The PCMCIA was designed for extension cards on laptop computers It offers 64 MB of attribute memory common memory and I O The PCMCIA interface converts CPU signals to PCMCIA signals via PLD Memory I O and mixed cards can be used The address and data lines are connected via buffers to the card connector 10 pull ups are connected to the data lines to define a FF on the data bus if no device on the card is selected The access time to the card is at least 200 ns and can be extended to up to 12 us by using the WAIT signal The interface supports the dynamic data bus sizing Longword transfers of the CP
91. t be closed and R1602 must be removed The Dallas timekeeper RAMs do not offer the feature to check the battery The SGS Thomson devices allow to check an internal battery OK flag Hardware Manual 51 3 Programmers Reference 3 6 2 Real Time Clock 52 BAB 40 60 The clock features BCD coded year month day hours minutes and seconds as well as a software controlled calibration For lifetime calculations of the battery please refer to the data sheet Access to the clock is as simple as conventional bytewide RAM access because the RAM and the clock are combined in the same chip Table 29 Address Assignment of the Real Time Clock MK48T12 Address Description FEC2 7FF8 RTC Control Register FEC2 7FF9 Seconds FEC2 7FFA Minutes FEC2 7FFB Hour FEC2 7FFC Day FEC2 7FFD Date FEC2 7FFE Month FEC2 7FFF Year For further details see the MK48T12 MK48T18 resp DS 1644 data sheet The SRAM RTC can only be accessed with byte instructions Hardware Manual ELTEC 40 60 3 Programmers Reference 3 7 CIO Counter Timer The BAB 40 60 offers three independent programmable 16 bit counter timers integrated in the CIO Table 30 Address Assignment of the System CIO Address Description FEC3 0000 Port C Data Register CIO Status Display FEC3 0001 Port B Data Register CIO Hex Switches FEC3 0002 Port A Data Register CIO System Control Register FE
92. the SBR register The 32 decoder compares A31 to A24 of the VMEbus with the SBR bits 32 to 24 for VMEbus extended access Hardware Manual 39 3 Programmers Reference BAB 40 60 The decoder compares A15 to A8 of the VMEbus with the SBR bits 15 to 8 The ESR register allows separate enabling of the two comparators Table 26 Enable Slave Register Layout Reg Address 2 1 0 ESR 5 000 unused ICF1 A16 unused VEXT A32 1 Decoder enabled 0 Decoder disabled 32 3 Address The address presented by the VMEbus the BEB or the ILACC is Translation translated from the 020 bus 020 to the 040 bus with the help of the MBAR memory base address register and ASR address substitution register of the IOC 2 The address on the 040 bus is calculated using the following formula amp logical AND operation logical OR operation logical complement The translation is necessary for snooping of the CPU to keep its caches consistent with the memory The translated address must always be in the DRAM If not the computer crashes in most cases For all address lines not driven by the source the corresponding bit position in the ASR must be 1 so that the invalid bits are substituted Unfortunately the address translation exists only once for the three address sources VMEbus BEB ILACC This leads to some restrictions when the DRAM is accessed by A24 addr
93. troller BEB VMEbus Burst mode is supported for accesses of CPU SCSI Controller VMEbus BLT The base address of the DRAM seen from the CPUs is fixed to 0000 0000 To avoid programming of the MMU the DRAM is mirrored as non cacheable RAM The base address for accessing the RAM from the VMEbus as well as the window size is programmable The on board firmware uses hex switch S901 to program the VMEbus address decoder and mask registers When using A24 addressing from the BEB to access the BAB 40 60 RAM the address translation logic has to be programmed to supply the local addresses A 24 to A 26 The following table summarizes the usable bandwidth of the RAM including precharge and refresh Table 2 Usable Bandwidth of the RAM Bus Clock 33 MHz MB s 25 MHz MB s DRAM read 44 40 DRAM write 44 40 Hardware Manual 7 1 Specification 1 3 3 1 3 4 1 3 5 1 3 6 PCMCIA Interface EPROM Graphics Keyboard Interface Optional Ethernet Interface BAB 40 60 The three socket PCMCIA interface uses a MACH445 PLD It incorporates several control registers and translates the signals from the BAB s 020 bus to the three PCMCIA sockets The data and address lines of the sockets are isolated from the 020 bus via buffers This allows live insertion and removal of PC Cards under certain circumstances when none of the PC Cards is accessed by the CPU To ensure that un
94. until autoboot starts 0B80 0B83 Logical Sector Offset 0B84 0B87 reserved 0B88 0BC7 Drive command 0BC8 0BD7 Own internet address 0BD8 0C17 Internet bootfile name incl host internet address 0C18 0C1B Slave board address 0C1C 0C1D BootP flag 0C1E 0C1F Network boot time out value 0C20 0C4F Server name 0C50 0C57 reserved Group E Board Information 0C58 reserved 0C59 Character I O port number 0C5A 0C5B reserved 0C5C Watchdog enable flag 0C5D reserved 0C5E 0C61 Watchdog time out period 0C62 C067 reserved 0C68 0C87 Internal board information 0C88 0C8D Ethernet Node ID 0C8E Board ID 0C90 0C93 RMon base address 0C96 0C97 Local memory size in MB 0C98 0CAO reserved 76 Hardware Manual ELTEC 40 60 ELTEC 3 Programmers Reference Table 49 Default Parameters of RMon 2 8 located on BAB 40 60 Beginning End Description Group F Video Descriptor 0 1 Graphic Bit Mode 0CA2 Display Start Address 0CA6 0CA9 Size of Graphic Plane 0CAA 0CAD Size of Display Window 0CAF 0CBO Fore and Background color 0CB1 0CB2 Number of Columns and Lines 0CB3 Video Descriptor Format 0CB4 0CB7 Position of Character Window 0CCO OCFF Video Timing Parameter 0D00 0DBF reserved 0DAO Keyboard typamatic rate delay 0DA1 Keyboard language 0DA2 00FB reser
95. upplied by LIRQ7 ILACC 3 VIC Error Group IRQ ACFAIL from VMEbus 7 VIC Write Post Fail 7 VIC Arbitration Time out 7 VIC SYSFAIL from VMEbus 7 VIC LIRQ6 System CIO e System CIO LIRQ5 BEB 21 LIRQ4 Serial 51 SCC LIRQ3 PCMCIA Controller 31 PCMCIA LIRQ2 Clock Tick Timer of VIC 6 VIC LIRQ1 SCSI Controller 2 VIC Keyboard Controller ICGS Group IRQ Interprocessor Communication 6 VIC Global Switches of VIC ICMS Group IRQ Interprocessor Communication 7 VIC Module Switches of VIC IRQ7 VMEbus 7 VMEbus IRQ6 VMEbus 6 VMEbus IRQ5 VMEbus 5 VMEbus IRQ4 VMEbus 4 VMEbus IRQ3 VMEbus 3 VMEbus IRQ2 VMEbus 2 VMEbus IRQ1 VMEbus 1 VMEbus DMA Status IRQ VIC DMA Controller 1 VIC VMEbus Interrupt VIC Interrupter 1 VIC Acknowledged 1 The IRQ levels inside the VIC have to be programmed with the level mentioned in the column All other IRQ levels are example values of the operating system s initialization they may be changed by the user Hardware Manual ELTEC 40 60 3 19 1 Local Interrupt Sources 3 19 2 VMEbus Interrupt Sources ELTEC 3 Programmers Reference The BAB 40 60 has eight local interrupt sources connected to six VIC inputs LIRQ1 LIRQ3 to LIRQ7 Table 48 Local Interrupt Sources Device VIC Input Level Vector Supplied by ILACC LIRQ7 3 47 VIC System CIO LIRQ6 e xx CIO BEB LIRQ5 2 xx BEB board Serial LIRQ4 5 xx SCC PCMCIA LIRQ3 3
96. used areas of a PC Card are read as 1 the data lines of each slot are pulled high To allow programming of FLASH devices 12 V can be applied to the sockets via optocoupler devices The pin assignment of the 32 pin socket corresponds with the JEDEC standard The socket is designed for use with 32 pin EPROMs only These EPROM types range from 1 Mb up to 8 Mb 27C010 to 27C080 The EPROM access time is programmable via IOC 2 register from 4 to 36 wait states 60 ns to 810 ns maximum access time After reset the EPROM is mapped to 0000 0000 so the initial stack pointer and reset vector can be read During initialization it is mapped to its normal address FE80 0000 and the DRAM is located at address 0000 0000 The EPROM is accessed with six wait states 120 ns access time per byte at 33 MHz The software in the basic EPROM RMon initializes all hardware according to the parameters in the basic EPROM or the NVRAM FEC2 0000 Various graphics keyboard modules can be installed on the BAB 40 60 via the BGB connector All modules support a PS 2 compatible keyboard The standard module has 1MB and displays up to 1024x768 pixels with 4 8 bit per pixel and 60 MHz refresh rate Up to 800x600 72 Hz refresh rate is possible The monitor is connected to the module via a standard 15 pin VGA connector The Ethernet interface is based on the Integrated Local Area Communications Controller ILACC AM79C900 A main feature of the IL
97. ved 0DFC 0DFF Checksum Hardware Manual 77 3 Programmers Reference Type declarations for the following definitions struct io data unsigned char value unsigned char registerno 1 2 3 4 5 HH 3 21 1 Group A I O Initialization 0000 0800 0000 0A EF 3 21 1 VIC Definition Parameter Description 78 struct io data vic 0x40 Initialization values for VIC registers First member is value second member is VIC register number Register number 1 marks end 0x00 0x10 0x82 0x00 0x81 0x85 0x77 Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff RAM Address Default Data Oxab Oxc7 7 0 07 0 17 0x47 Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff 0000 0800 0000 087F 10 40 0 46 0 16 0 00 0 82 0 86 Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxaf Oxcb Oxdb 0x0b Oxlb Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Hardware Manual 0x60 0x00 0x82 0x00 0x83 0x87 Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxb3 Oxb7 Oxcf Ox0f Ox1f Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff Oxff 0x40 0x12 0x00 0x80 0x84 0 1 Oxff Oxff Oxff Oxff Ox
98. verter plug ins for RS 422 and RS 485 are available The baud rate generator is driven by 5 MHz allowing baud rates from 50 b s to 38 4 kb s The BAB 40 60 offers three independent programmable 16 bit counters timers integrated in the CIO The real time clock is designed with the MK48T12 timekeeper RAM It combines a 2KBx8 CMOS SRAM parameter RAM NVRAM a bytewide accessible real time clock a crystal and a long life lithium battery all in one package Alternatively a MK48T18 device can be used which offers 8 KB SRAM or a DS1644 device which offers 32Kx8 KB SRAM The revision EEPROM is realized by a 512x8B serial EEPROM which offers special board revision information The lower half size of the EEPROM is programmed by ELTEC and should not be modified by the user to guarantee board revision consistency The upper 256 B can be used by the user to store additional information Hardware Manual 9 1 Specification 1 3 12 VIC Timer 1 3 13 Watchdog Timer 1 3 14 Status Display 1 3 15 Reset 10 BAB 40 60 The VIC contains a timer which can be programmed to output a periodic wave form on LIRQ2 The available frequencies are 50 Hz 100 Hz and 1000 Hz The VIC timer is typically used as a tick timer for multi tasking operating systems The watchdog timer monitors the activity of the microprocessor If the microprocessor does not access the watchdog timer within the time out period of 130 ms to 17 min a reset pulse is gene
99. vices Since upgrading the BAB 40 to BAB 60 requires some additional components it is not recommended that this is done by the user Please contact ELTEC Generally all PS 2 SIMMs from 1 MB to 32MB with symmetric RAS CAS addresses and better than 70 ns access time are suitable for the BAB 40 60 Since the BAB 40 60 does not use parity checking SIMMs with or without parity can be used but SIMMs without parity should be preferred because they are usually cheaper and smaller It is mandatory that the length of the SIMM board does not exceed 35 mm to fit on the BAB 40 60 Hardware Manual 25 2 Installation 26 BAB 40 60 Table 12 Recommended SIMMs SIMM Size Chip Size No of Chips Chip No of Banks Organization RAS 1MB 1M 8 256Kx4 single 1 MB 4M 2 256Kx16 single 1 MB 4M 2 256Kx18 single 2 MB 1M 16 256Kx4 double 2MB 4M 4 256Kx16 double 2MB 4M 4 256Kx18 double 4 MB 4M 8 1Mx4 single 4 MB 16M 2 1Mx16 single 8 MB 4M 16 1Mx4 double 8 MB 16M 4 1Mx16 double 16 MB 16M 8 4Mx4 single 32 MB 16M 16 4Mx4 double Before removing or installing the SIMM module switch power off The SIMM is simply plugged into the connector it fits only in one orientation and is automatically recognized by the RMon please check the power on message of the RMon If RMon hangs with 5 in the LED display or reports the wrong size installation was not correct or the SIMM is not suitable for t
100. wide accessible real time clock a crystal and a long life lithium battery all in one package The MK48Txx devices have a battery lifetime of approximately 3 7 years when the clock oscillator is running To extend battery lifetime the clock oscillator can be stopped Alternatively a Dallas 051642 1643 device can be used which offers a lifetime of 10 years even if the oscillator is running The address area of this SRAM is divided into two main parts system dependent parameter data structure defined by ELTEC to store setup parameters for hardware initialization and boot informations for operating systems eight bytes of the SRAM for the registers of the real time clock Table 28 Address Assignment of SRAM RTC Address Description FEC2 0000 FEC2 07F7 Reserved for system configuration values The structure of the system configuration values is defined in the RMon manual FEC2 07F8 FEC2 7FF7 Free for user data if DS1644 is installed FEC2 7FF8 FEC2 7FFF Real time clock registers See Section 3 6 2 Real Time Clock for more information The S902 hex switch position 0 uses the configuration values stored in the basic EPROM rather than values defined in the SRAM For more details see also the RMon description If a MK48T18 is installed J1602 must be changed from position 1 2 to 2 3 If a DS1644 is installed J1602 must be changed from position 1 2 to 2 3 Additionally J1606 J1607 mus
101. y sending a retry acknowledge to the CPU On locked cycles this does not work because the arbiter does not grant the bus from the current bus master as long as LOCK is active Such deadlocks are resolved by sending a error acknowledge to the CPU Then there must be a bus error trap handler that inspects the stack frame whether there was a locked cycle or not If not normal bus error handling is continued Else the locked cycle is retried by simply performing a RTE instruction The trap handler also should inspect the VIC s bus error status register whether there was a bus error If so also normal bus error handling should be done to prevent that the trap handler retries the locked cycle infinitely If a semaphore resides in a region that can be cached in the 040 in copyback mode TAS violation can occur via the following sequence the semaphore resides in a dirty cache line in the cache of the 040 and the semaphore is set an alternate master performs the read of a TAS the 040 snoops the read and supplies that the semaphore is set the 040 clears the semaphore in the cache the alternate master performs the write of the TAS the 040 snoops the write so that the semaphore is set again As a result of this the clearing of the semaphore is lost This can be avoided by using the CAS instruction to clear the semaphore Hardware Manual ELTEC 40 60 3 Programmers Reference 3 21 Default Parameters for RMon Table 49 Def
102. y jumpers and switches For details refer to the appropriate descriptions identified in parentheses settings on a dark grey background indicate default settings The BAB 40 60 operates as single board computer in this configuration There are only very few jumpers on the BAB 40 60 which typically need no changes after shipping All other parameters are software programmable Since the jumper connections are not changed easily it is strongly recommended that these changes are performed by qualified personal only The user should refer to the silkscreen print on the component side of the BAB 40 60 for the following guidance on jumper area pin identification Pin 1 of every jumper area is marked by a beveled corner on the silkscreen outline of the jumper If you see this corner at the left upper side of the jumper area then pin 2 is on the right hand side of pin 1 Pin 3 can be found on the right of pin 2 and so on Table 14 J301 System Controller Jumper J301 Function open System controller disabled closed System controller enabled Table 15 1701 CHAN 2 DCD DSR Select Jumper J701 Function 1 2 DCD of X702 connected to SILC 2 3 DSR of X702 connected to SILC Table 16 J702 CHAN 2 DCD Receive Clock Select Jumper J702 Function 1 2 DCD DSR from SILC connected to DCD of SCC 2 3 DCD DSR from SILC connected to receive clock of SCC 3 4 7 37 MHz connected to rece

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