HP E2443B Intel Pentium CPU Preprocessor Interface User`s Guide
Contents
1. amp POD 1 POD 2 POD 3 16550 17 POD 4 POD 5 POD 6 Figure 1 2 Logic Analyzer Card Locations relative locations actual slots used can vary 9 Power Up When powering up the logic analyzer must be powered up first and Down Seq uence then the target system The logic analyzer provides the power to the active circuits on the preprocessor interface unpowered circuits may cause improper operation of the target system When powering down power down the target system first and then the logic analyzer HP E2443B Setting Up the HP E2443B Pentium CPU Preprocessor Interface 1 9 Table 1 3 Connections and Configuration Files HP 16540 16541A D 16550 1660 E2443B Logic Analyzer Logic Analyzer Logic Analyzer Into Pod Pod Pod Connector Master Card Pod 1 Master Card Pod 3 1 5 CIk1 Exp 3 Pod3 Master Card Pod 4 P2 STAT Exp Card 3 Pod 1 Master Card Pod 5 P3 ADDR Exp Card 3 Pod2 Master Card Pod 6 P4 ADDR Exp Card 2 Pod 1 Expander Pod 1 P5 DATA Exp Card 2 Pod2 Expander Card Pod 2 P6 DATA 1 Pod 1 Expander Pod 3 P7 DATA B Exp Card 1 Pod2 Expander Card Pod 4 P8 DATA B Exp 2 Pod3 Expander Pod 5 P9 additional status Exp Card 1 Pod3 Expander Card Pod 6 P10 additional st2. Figure 2 1 Format Specification HP E2443B Analyzing the Intel Pentium CPU Pentium CPU Preprocessor Interface 2 1 ClU Symbols The configuration files set up symbol tables in the logic analyzer The tables contain alphanumeric values which identify data patterns or ranges Table 2 1 lists the bits in the STAT label Table 2 2 lists the additional status bits which are available on pods 9 and 10 Table 2 3 lists the additional status bits which are available on the HP 1660A and HP 16550A Logic Analyzers Table 2 4 lists the signals which are available on the 2 x 4 header Table 2 5 lists the symbols for the Cycle label Table 2 6 lists the symbols for the Excptn label and table 2 7 lists the symbols for the Xfer label Table 2 8 lists the symbols for There are also symbols for many of the status signals listed below table 2 8 The patterns for each symbol listed in the tables are shown in the binary base In the actual software these patterns may be listed in the hexadecimal base to conserve display space Table 2 1 STAT Label Bits Pod Bit Status Signals Description BE7 BEO Byte Enable signals for the data bus IBT A high indicates a branch was taken A low this signal indicates that the current cycle is cacheable and will therefore be a burst CACHE A low on this signal indicates internal cacheability of the cycle for reads or a burst writeback
3. Figure 2 6 State Waveforms HP E2443B Analyzing the Intel Pentium CPU Pentium CPU Preprocessor Interface 2 23 3 General Information Introduction This chapter contains additional reference information including the characteristics and signal mapping for the HP E2443B Preprocessor Interface Characteristics Microprocessor Compatibility Microprocessor Package Accessories Required Maximum Clock Speed Target Signal Timing Signal Line Loading Power Requirements Logic Analyzer Required Number of Probes Used HP E2443B The following operating characteristics are not specifications but are typical operating characteristics for the HP E2443B Preprocessor Interface These characteristics are included as additional information for the user Intel Pentium CPU 273 pin PGA None 66 MHz CLK A minimum 3 5 ns setup 1 5 ns hold is required on the data bus A minimum 4 5 ns setup 1 5 ns hold is required on all other signals 7 pf in series with 85 ohms on CLK 14 pf in series with 35 ohms on the following signals ADS BRDY BRDYC HLDA KEN W R 14 pf on the following signals TU IBT INIT TDO SMIACT R S and RESET 10 pf on all other signals 1 5 A at 5 Vdc maximum from the logic analyzer HP 1660A HP 16540A D with three HP 16541A D Expansion Cards or HP 16550 two cards Ten 16 channel pods are available a 17th channel is available for the
4. No Activity on Activity Indicators HP E2443B Verify that the appropriate module has been selected from the Load module from File filename in the HP 16500A B disk operation menu Selecting Load All will cause incorrect operation when loading most preprocessor interface configuration files The logic analyzer displays this message if you try to load a configuration file for the wrong module Ensure that you are loading the appropriate configuration file for your logic analyzer This error occurs if you rename or delete the inverse assembler file that is attached to the configuration file Ensure that the inverse assembler file is not renamed or deleted Verify that the inverse assembler has been synchronized by placing an opcode at the top of the display not at the input cursor and pressing the Invasm key see Inverse Assembler in Chapter 2 This problem is usually caused by a hardware problem in the target system A locked status line will often cause incorrect or incomplete inverse assembly Check the activity indicators for status lines locked in a high or low state e Verify that the STAT DATA DATA B and ADDR format labels have not been modified from their default values These labels must remain as they are configured by the configuration file Verify that all microprocessor caches and memory managers have been disabled In most cases if the microprocessor caches and memory managers remain enabled you shou
5. amp IBRDYC St Pr Clk ADSsel amp IADS EADSsel amp EADS or HLDAsel amp or BOFFsel amp BOFF In State Per Transfer and Debugger modes the preprocessor generated signal Valid is part of ClkQual One additional signal EADS can be used as input to the clock qualifier by closing the switch In addition in Debugger mode data is captured whenever IU IV or IBT are asserted Whenever BOFF or HLDA is asserted the preprocessor interface automatically switches to State Per Clock mode and the State Per Clock ClkQual becomes relevant There are five additional signals which can be used in the State Per Clock ClkQual If none of the switches are closed no information will be clocked into the logic analyzer as long as BOFF or HLDA is asserted This allows maximum flexibility of logic analyzer storage and filtering when the Pentium CPU is tri stated Note that information is not inverse assembled while the preprocessor interface is in State Per Clock mode When BOFF or HLDA is deasserted the preprocessor interface switches back to State Per Transfer or Debugger mode The equations for the State Per Transfer and Debugger clock qualifiers are Valid I BRDY amp BRDYC amp Pentium CPU in T2 T12 states ClkQual St Pr Tr Valid or EADSsel amp EADS ClkQual Debugger Valid or EADSsel amp IEADS or IU or IV or IBT HP E2443B Analyzing the Intel Pe
6. Analyzers it is the K clock In State Per Transfer and Debugger modes ClkQual is asserted when valid data is on the bus or when the EADS qualification signal has been selected and is asserted in Debugger mode ClkQual is also asserted whenever IU or IBT are asserted In State Per Clock mode ClkQual is asserted when one more of the six qualification signals has been selected and is asserted EE amp Pentium CPU Signal to HP E2443B Connector Mapping Note HP E2443B The following table describes the electrical interconnections implemented with the HP E2443B Preprocessor Interface Since the pods on the logic analyzers are numbered differently than the pods on the preprocessor interface refer to table 1 3 to correlate the pod numbers The interconnections implemented with the HP E2443B are not direct interconnections The HP E2443B Preprocessor Interface places digital circuitry between the microprocessor pin and the logic analyzer input General Information Pentium CPU Preprocessor Interface 3 5 Preprocessor Pod Pin Table 3 1 Pentium CPU Signal List Logic Analyzer Probe Pentium CPU Pin Mnemonic Label s ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR These si
7. Divide Error 1 Debug Excptn 2 NMI Interrupt 3 Breakpoint 4 INTO Overflow 5 BOUND Rng Exc 6 Invalid Opcode 7 Dev Not Avail 8 Double Fault 10 Inv Task SSeg 11 Seg N Present 12 Stack Fault 13 Gen Protectn 4 Page Fault 16 Flt Point Err 17 Alignment Chk HP E2443B Analyzing the Intel Pentium CPU Pentium CPU Preprocessor Interface 2 9 The Xfer symbols consist of the following signals HLDA BOFF W R CACHE KEN Table 2 7 Xfer Symbols Pattern Xfer Rd Xfer Rd 4 Xfer Rd Xfer Wr 4 Xfer Wr Analyzing the Intel Pentium CPU HP E2443B 2 10 Pentium CPU Preprocessor Interface Table 2 6 Symbols Pattern Additional There are also symbols for the following signals Symbols W R D C M IO SCYC IBT IV IU WB WT PWT PCD BUSCK FLUSH IERR INTR NMI SMI SMIAC A20M AP APCHK ADS AHOLD BOFF BRDY BRDYC EADS EWBE HIT HITM HLDA HOLD INV NA BREQ RESET INIT PENH PCHK FERR IGNNE PRDY and R S HP E2443B Analyzing the Intel Pentium CPU Pentium CPU Preprocessor Interface 2 11 gt 0 0 0 2 Listing Menu Captured data is displayed as shown in figure 2 2 with the IAPENT inverse assembler or figure 2 3 with the IAPENTE inverse assembler The inverse assemblers are constructed so the mnemonic output closely resembles the
8. amp BRDYC amp Pentium CPU in T2 T12 states During State Per Transfer and Debugger modes when HLDA or is asserted the preprocessor interface automatically switches to State Per Clock mode regardless of the switch 7 and 8 settings The State Per Clock clock qualifier inputs become relevant The HLDA or data is not disassembled When HLDA or BOFF is deasserted the preprocessor interface switches back to State Per Transfer or Debugger mode therefore all other data is still aligned and disassembled For State Per Transfer and Debugger modes pipelined addresses are realigned The address captured with EAD S is the address of the current bus cycle it is not the inquire address However cache writebacks which are triggered bya snoop will be captured and displayed To fully capture inquire cycle activity use State Per Clock mode Clock Version The 1 x 3 header serves as a single pole double throw switch It allows Timing Only you to select the version of the clock which is sent to the logic analyzer in Timing mode One version of the clock PLL is routed through a phase locked loop while the other version CLK is only buffered The rising edges of CLK and PLL line up within 0 6 1 ns with PLL leading CLK The factory setting for the jumper is with PLL selected For more precise timing analysis of the clock signal the jumper can be moved to the CLK position so that the buffered version of the
9. apply to defects resulting from improper or inadequate maintenance by the Buyer Buyer supplied software or interfacing unauthorized modification or misuse operation outside of the environmental specifications for the product or improper site preparation or maintenance NO OTHER WARRANTY IS EXPRESSED OR IMPLIED HEWLETT PACKARD SPECIFICALLY DISCLAIMS THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE THE REMEDIES PROVIDED HEREIN ARE BUYER S SOLE AND EXCLUSIVE REMEDIES HEWLETT PACKARD SHALL NOT BE LIABLE FOR ANY DIRECT INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES WHETHER BASED ON CONTRACT TORT OR ANY OTHER LEGAL THEORY Product maintenance agreements and other customer assistance agreements are available for Hewlett Packard products For assistance contact your nearest Hewlett Packard Sales and Service Office Hewlett Packard Company certifies that this product met its published specifications at the time of shipment from the factory Hewlett Packard further certifies that its calibration measurements are traceable to the United States National Bureau of Standards to the extent allowed by the Bureau s calibration facility and to the calibration facilities of other International Standards Organization members This product has been designed and tested according to International Safety Requirements To ensure safe operation and to keep the product safe the information cautions and wa
10. cycle for writes W R A low indicates read and a high indicates write D C A low indicates a code special cycle and a high indicates a data cycle M IO A low indicates an I O cycle and a high indicates a memory cycle LOCK A low indicates that the current bus cycle is locked A20M A low indicates an Address bit 20 mask for internal cache lookups or memory cycles Analyzing the Intel Pentium CPU HP E2443B 2 2 Pentium CPU Preprocessor Interface Table 2 1 STAT Label Bits continued Pod Bit Status Signals Description This signal is generated by the preprocessor interface A high indicates that a data transfer is valid A low indicates that a new valid bus cycle is being driven by the Pentium CPU A low indicates that the external memory is ready to accept a new bus cycle although all data transfers for the current cycle are not completed BRDY A lowindicates valid data on the data pins BRDYC A low indicates valid data on the data pins for cacheable data PRDY A high indicates that the Pentium CPU is ready to accept a Probe Mode instruction AHOLD A high indicates an address hold request EADS A low indicates a valid external address has been driven onto the Pentium CPU address pins to be used for an inquiry cycle HIT This signal indicates the outcome of the most recent inquire cycle HITM A low indicates during inquire
11. sets up the format specification menu of the logic analyzer for compatibility with the Pentium microprocessor It also loads the inverse assembler for obtaining displays of Pentium CPU data in Pentium CPU assembly language mnemonics Log ic Analyzer The HP E2443B Preprocessor Interface requires HP 16500A system Software and module software version V05 03 or higher HP 16540 16541A D and HP 16550A Logic Analyzers For the HP 165008 mainframe Requirement system and module software version V01 00 or higher is required For the HP 1660A Logic Analyzer software version V01 00 or higher is required To use the enhanced inverse assembler with the HP 1660A Logic Analyzer software version V02 00 or higher is required If your software version is older than those listed above load new system software with the above version numbers or higher before loading the HP E2443B software Pentium M is a trademark of Intel Corporation Introduction 1 Logic Analyzers Supported The following logic analyzers are supported by the HP E2443B HP 1660A The HP 1660A Logic Analyzer provides 4 of memory depth with 136 channels of 100 MHz state analysis or 250 MHz timing analysis This logic analyzer also supports various combinations of mixed state timing analysis HP 16540A D with three HP 16541A D Expansion Cards This logic analyzer combination provides 4 k of memory depth 16k with the D version with 160 channels of 100 MHz state or tim
12. will clock information into the logic analyzer Therefore qualified clocking allows you to filter information since ClkQual must be asserted before the logic analyzer is clocked by 7 The logic analyzer must use qualified clocking for State Per Transfer and Debugger modes it can be clocked as qualified or non qualified for State Per Clock mode With non qualified clocking every state is captured regardless of the settings for the switches The configuration file sets up the logic analyzer for qualified clocking To change to non qualified clocking use the Format menu to remove the clock qualifier The clock qualifier is the M Clock on the HP 16550A and the Clock on the HP 16540 16541A D and HP 1660A Logic Analyzers Figure 2 5 shows the Format specification with the clock qualifier removed Only the L Clock is shown in the Master Clock field Clk1 is the L clock in the HP 16550A it is the J clock in the HP 1660A and HP 16540 16541A D Analyzing the Intel Pentium CPU HP E2443B 2 20 Pentium CPU Preprocessor Interface ClkQual In State Per Clock mode six signals can be used as inputs to the clock qualifier see Chapter 1 The inputs are selected by closing the appropriate switches The only states which will be captured are those in which the signal for a selected closed switch is asserted The equation for the clock qualifier in State Per Clock mode is ClkQual BRDYsel amp BRDY or BRDYCsel
13. 2 4 The following sections describe these functions If the X or pattern markers are turned on and the designated pattern is found in a state that has been Suppressed with display filtering the following message will appear on the logic analyzer display X or O pattern found but state is suppressed Pentium Inverse Assembly Options Code Reads Code Synchronization Unexecuted Prefetches Suppress Start From Show Show Default Size Show Show Show Mode Show Show Show Show Done Byte 0 6 Jumps Calls and Returns 16 Bits Other Instructions Align Memory Reads Memory Writes Protected I O Reads IDT Start 00000000 1 0 Writes 5128 Special Cycles Int Ack Cycles Figure 2 4 IAPENTE Inverse Assembly Options HP E2443B Pentium CPU Preprocessor Interface Show Suppress The Suppress Show settings determine whether the various microprocessor operations are shown or suppressed on the logic analyzer display Figure 2 4 shows the microprocessor operations which have this option The settings for the various operations do not affect the data which is stored by the logic analyzer they only affect whether that data is displayed or not The same data can be examined with different settings for different analysis requirements This function allows faster analysis in two ways First unneeded information can be filtered out of the
14. 3 CIKk1 IGNNE IGNNE P6 3 1 1 7 3 CIKk1 P8 3 CIk1 AP AP P9 3 1 1 10 3 1 1 These signals are generated by the preprocessor interface 16540 16541A D only HP 1660A and HP 16550A only General Information HP E2443B 3 12 Pentium CPU Preprocessor Interface 29200 2 Se rvicing The repair strategy for the HP E2443B is board replacement However table 3 2 lists some mechanical parts that may be replaced if they are damaged or lost Contact your nearest Hewlett Packard Sales Service Office for further information on servicing the board Exchange assemblies are available when a repairable assembly is returned to Hewlett Packard These assemblies have been set up on the Exchange Assembly program This allows you to exchange a faulty assembly with one that has been repaired calibrated and performance verified by the factory The cost is significantly less than that of a new assembly Table 3 2 Replaceable Parts HP Part Number Description 2443 69502 Exchange Board Cable Assembly E2443 66502 Circuit Board Cable Assembly E2443 68703 Software Disk Pouch 1200 1753 Pin Protector 1252 3743 Jumper ee Dimensions Figure 3 2 lists the dimensions for the HP E2443B circuit board The dimensions are listed in inches and millimeters HP E2443B General Information Pen
15. About this Manual We ve added this manual to the Agilent website in an effort to help you support your product This manual is the best copy we could find it may be incomplete or contain dated information If we find a more recent copy in the future we will add it to the Agilent website Support for Your Product Agilent no longer sells or supports this product Our service centers may be able to perform calibration if no repair parts are needed but no other support from Agilent is available You will find any other available product information on the Agilent Test amp Measurement website www tm agilent com HP References in this Manual This manual may contain references to HP or Hewlett Packard Please note that Hewlett Packard s former test and measurement semiconductor products and chemical analysis businesses are now part of Agilent Technologies We have made no changes to this manual copy In other documentation to reduce potential confusion the only change to product numbers and names has been in the company name prefix where a product number name was HP XXXX the current name number is now Agilent XXXX For example model number HP8648A is now model number Agilent 8648A HP E2443B Intel Pentium CPU Preprocessor Interface User s Guide for the HP 1660A HP 16540 16541A D and HP 16550 Logic Analyzers HEWLETT PACKARD Copyright Hewlett Packard Company 1993 Manual Part Number E2443 90903 Microfiche Part N
16. HP 1660A and HP 16550A Logic Analyzers Eight pods are required for inverse assembly General Information Pentium CPU Preprocessor Interface 3 1 Microprocessor Operations Displayed Additional Capabilities Environmental Temperature Altitude Humidity General Information 3 2 Interrupt Acknowledge Special Cycles including Branch Trace Messages I O Reads Writes Code Reads Data Reads Writes Normal Reads Pipelined Loads Page Directory Reads Writes Page Table Reads Writes Write Throughs Store Misses Write Backs Interrupt Acknowledge Cycles The logic analyzer captures all bus cycles including prefetches Unexecuted prefetches are marked with a dash The State Per Clock mode offers filtering for valid data BRD Y valid address ADS inquire address EADS HLDA and bus arbitration BOFF Operating Oto 55 C 32to 131 F Nonoperating 40 to 75 C 40 to 167 F Operating 4 600 m 15 000 ft Nonoperating 15 300 m 50 000 ft Up to 90 noncondensing Avoid sudden extreme temperature changes which could cause condensation within the instrument HP E2443B Pentium CPU Preprocessor Interface Interface The primary function of a preprocessor interface is to connect the Description target microprocessor to the logic analyzer through the probe interface and to perform any functions unique to that particular microprocessor The HP E2443B Preproce
17. Menu es aa Us itch sald Nl aie antes aan 2 12 Burst and Cacheable 2 13 The Pentium CPU Inverse Assemblers 2 14 Address s Sa een Se as 2 14 Prefetched 2 15 Synchronizing the Inverse Assembler 2 16 Operand SIZe ehe 2 17 Byte Enable 2 17 Incomplete 2 17 Opcode Data Numeric 2 17 Branch Trace 2 17 Contents 1 Illegal Instructions 2 17 The IAPENTE Inverse 2 18 Show Suppress tea dee pe en ss 2 19 Code Synchronization 2 19 IDT Description eini seni ml D RR 2 19 Modest Operation eorr ua ree ea 2 20 Qualified Non qualified 1 2 20 en a ee ER 2 21 State Waveforms Using State Per Clock Mode 2 23 Chapter 3 General Information Tntroduction tenn ses bus ee es en 3 1 Ch r cteristics b TEES 3 1 Interface Description eo ee e en 3 3 ClOCKIN 8594 Le een t dee teet Cbar eie ees 3 5 Pentium CPU Signal to HP E2443B Conn
18. T ADS NA STAT NA BRDY STAT BRD Y BRDYC STAT BRDYC PRDY STAT PRDY AHOLD STAT AHOLD EADS STAT EADS This signal is generated by the preprocessor interface Valid BRDY amp BRDYC amp Pentium CPU in T2 T12 states General Information HP E2443B 3 10 Pentium CPU Preprocessor Interface Table 3 1 Pentium CPU Signal List Continued Preprocessor Logic Analyzer Pentium CPU Pin Label s Pod Pin Probe Pin Mnemonic HIT STAT HIT HITM STAT HITM BTO STAT BT BT1 STAT BT BT2 STAT BT BT3 STAT BT BOFF STAT BOFF HLDA STAT HLDA R S R S ADSC ADSC HOLD HOLD BREQ BREQ INTR INTR NMI NMI SCYC SCYC BUSCHK BUSCHK FLUSH FLUSH INV INV EWBE EWBE WB WT WB WT PWT PWT PCD PCD RESET RESET INIT INIT HP E2443B General Information Pentium CPU Preprocessor Interface 3 11 Table 3 1 Pentium CPU Signal List Continued Preprocessor Logic Analyzer Pentium CPU Pin Label s Pod Pin Probe Pin Mnemonic P10 37 DPO DP P10 35 DPI DP 10 33 DP2 DP P10 31 DP3 DP P10 29 DP4 DP P10 27 DP5 DP P10 25 DP6 DP P10 23 DP7 DP P10 21 IU IU P10 19 IV IV P10 17 1 SMI SMI P10 15 11 SMIACT SMIACT P10 13 12 10 11 13 PM1 BP1 PM1 BP1 P10 9 14 BP2 BP2 P10 7 15 BP3 BP3 1 5 CIK2 ClkQual Qual P1 3 CIK1 CLK CLK P2 3 CIk1 ClkQual Qual P3 3 CIKk1 FERR FERR P4 3 CIK1 IERR IERR p5
19. ace information will be lost The cache can be disabled with software by setting CRO CD 12 CI or the PCD bits in the page table entries to 1 It can be disabled in hardware by deasserting KEN If the execution tracing enable bit bit 1 in TR12 C1 is set to 1 the Note branch trace message cycles will be captured and decoded by the logic analyzer This will allow the trace to indicate that branches have Occurred even with the cache enabled 5 If possible you may want to disable page translation so that the physical addresses that the preprocessor interface monitors are effectively the logical addresses Page translation can be disabled by setting CRO PG to zero Setting Up the HP E2443B HP E2443B 1 8 Pentium CPU Preprocessor Interface Connecting to Connect the logic analyzer probes to the cable connectors of the the HP E2443B preprocessor interface board as listed in table 1 3 Figure 1 2 shows the relative locations of the logic analyzer cards HP 16540 16541A D Expansion Cord 1 Bk 40799 8 HP 16540 16541A 0 Master Cord g HP 16540 16541A D Expansion Card 2 I 2 16540 16541A D Exponsion Cord 3 LEE off E m t ga po 5 BR lt gt HP 16550A Expansion Card HP 16550A Master Card zs SES hs a E f PODS gt po P N mo mo LI
20. actual assembly source code In figure 2 3 the unexecuted prefetches have been suppressed The logic analyzers always probe the full 64 bit data bus of the Pentium CPU When fewer than the full 64 bits of the data bus are used by a memory cycle the inverse assembler marks the bytes not used by the microprocessor with xx 100 500HH2 LA D Listing 1 Print Markers off Label Pentium Inverse Assembly Base Mnemonics Hex AL 6F 70 AL OOOF OO AL 71 AL 04 OOOFOOEE 000700 AL 0E OOOF OOF 1 OOOF 30D3 000700 000700 Figure 2 2 State Listing IAPENT Inverse Assembler Analyzing the Intel Pentium CPU HP E2443B 2 12 Pentium CPU Preprocessor Interface 100 500 2 LA D Listing 1 Invasm Options Print Markers Off Label ADDR_ Pentium Inverse Assembly Base Hex Mnemonics Hex AL r 70 AL 000500 71 Code Rea AL 04 OOOFOOEE 000500 AL 0E Code Rea OOOF OOF 1 000 3003 000000 1 0 write I O Writ 000000 1 0 read 1 0 Read 000 30 0 EAX Code Rea 0 000530 SHL Code Rea Figure 2 3 State Listing IAPENTE Inverse Assembler Unexecuted Prefetches Suppressed Burst and The logic analyzer can track burst 4 transfer and non burst Cacheable Data 1 transfer cycles During burst transfers the mic
21. ad the file into the logic analyzer There are three inverse assemblers in the HP E2443B software Table 1 4 shows the default inverse assembler which is automatically loaded by the configuration files It also shows the different logic analyzer configurations which are supported by each inverse assembler Pages 2 14 and 2 18 contain additional information on the different inverse assemblers To load a different inverse assembler after the configuration file has been loaded repeat steps 1 6 above except that for step 5 select the desired inverse assembler Setting Up the HP E2443B Pentium CPU Preprocessor Interface 1 11 Table 2 4 Inverse Assembler Compatibility Logic Analyzer Mainframe HP 16500A Mainframe default HP 16500B Mainframe yes default HP 1660A Logic Analyzer software 01 default HP 1660A Logic Analyzer software V02 00 or higher yes default Although this inverse assembler supports these logic analyzers it does not provide all the features available with IAPENTE 9 Timing Analysis The configuration loaded for state analysis may also be used for timing analysis In Timing mode the signals are buffered by a 74FCT646AT with a maximum buffer delay of 6 3 ns minimum 2 0 ns and a typical 1 0 ns skew To configure the logic analyzer for timing analysis 1 Set the switches for timing see page 1 3 2 Load the appropriate configuratio
22. atus Configuration Files CPENT 1 CPENT 2 CPENT 3 Forthe HP 16541A D cards expansion card 1 is the physically highest HP 16541A D card expansion card 2 is the second physically highest HP 16541A D card and expansion card 3 is the third highest HP 16541A D card see fig 1 2 For the HP 16550A cards the Master Card is the lower card and the expansion card is the higher card Note that the two HP 16550A cards must be configured as a single logic analyzer Setting Up the HP E2443B HP E2443B 1 10 Pentium CPU Preprocessor Interface 7 7 6 Setting Up the Analyzer from the Disk HP E2443B The logic analyzer can be configured for Pentium CPU analysis by loading the appropriate configuration file Loading this file will also load a default inverse assembler file or IAPENTE To load the configuration and inverse assembler 1 Install the flexible disk in the front disk drive of the logic analyzer The HP 16500B mainframe has a hard disk drive You can create a directory on the hard drive and copy the files from the flexible disk into the directory For step two select Hard Disk 2 Select the System Front Disk menu 3 Configure the menu to Load the analyzer configuration from disk 4 Select the appropriate module such as 100 500 MHz LA or Analyzer for the load 5 Use the knob to select the appropriate configuration file see table 1 3 6 Execute the load operation to lo
23. c serial output Test logic control signal Test logic reset signal These signals are located on the 2 x 4 header see figure 1 1 HP E2443B Analyzing the Intel Pentium CPU Pentium CPU Preprocessor Interface 2 7 The Cycle symbols consist of the following signals in the designated groupings BOFF LOCK D C W R BE7 4 BES 0st Table 2 5 Cycle Symbols Pattern HLDA amp BOFF Hold Ack Bus Backoff Int Ack Ist Int Ack 2nd I O Read I O Write Lckd Read Lckd Write Code Read Lckd Code Rd Reserved Mem Read Mem Write Lckd Mem Rd Lckd Mem Wr HB mp x xxx mM KM mM KM mM mM mM Mm mM KM xxx Shutdown Flush Halt Writeback Flush Ack Brch Trg Msg Undf Special mM SOs OC OO CO CO MOS ONO OO NON OX MK X XX OX ON OX X XX XX ON xx xX OX xxx xx OX KX ON M OM xX XX OM Xxx xXx KX KX KM Analyzing the Intel Pentium CPU HP E2443B 2 8 Pentium CPU Preprocessor Interface The Excptn symbols consist of the following signals in the designated groupings BOFF 07 0 D C W R 7 08 Table 2 6 Excptn Symbols Pattern Int Ack 1st Cycl 0
24. cates that the current cache line is write through and a high indicates write back PWT Indicates cache writeback on a page by page basis PCD Indicates cacheability on a page by page basis RESET A high indicates that the Pentium CPU will begin execution from a known reset state INIT A high indicates that the Pentium CPU will begin execution from a known reset state except the internal caches and some register values are left unchanged Analyzing the Intel Pentium CPU HP E2443B 2 4 Pentium CPU Preprocessor Interface Pod Bit P10 7 0 Table 2 2 Additional Status Bits continued Status Signals Description Data parity pins P10 8 IU A high indicates that an instruction in the u pipeline has complete execution P10 9 IV A high indicates that an instruction in the v pipeline has complete execution P10 10 SMI A low indicates a System Power Management interrupt P10 11 SMIACT A low indicates that the Pentium CPU is operating in System Management mode P10 12 P10 13 1 P10 14 2 P10 15 2443 BP are the breakpoint pins that indicate a breakpoint match with the debug registers DR3 0 when they are programmed as such the PM are the performance monitoring pins Analyzing the Intel Pentium CPU Pentium CPU Preprocessor Interface 2 5 Table 2 3 Additional Statu
25. cessor is a prefetching microprocessor It may prefetch up to 64 bytes eight 64 bit code fetches before the current opcode When a program executes an instruction that causes a branch the prefetched code is not used and will be discarded by the microprocessor The inverse assembler marks unused prefetches with a hyphen in the third column of the display The logic analyzer captures prefetches even if they are not executed Therefore care must be taken when you are specifying a trigger condition or a storage qualification and the instruction of interest follows an instruction that may cause branching An unused prefetch may generate an unwanted trigger The Pentium CPU has a prefetch queue of essentially 64 bytes This means that by the time a branching instruction is fully decoded up to 64 other instruction bytes may have already been prefetched across the data bus and stored in the logic analyzer Both exceptions and instructions can cause the prefetch queue to be flushed and subsequently refilled Branches jumps calls returns and system control instructions are the most common causes of prefetch queue flushes but there are many others Refer to your Pentium CPU user s manual for more information Analyzing the Intel Pentium CPU Pentium CPU Preprocessor Interface 2 15 Synchronizing the In some cases the prefetch marking algorithm in the inverse assembler Inverse Assembler may lose synchronization and unused prefetches or exe
26. ch markers are not displayed Setting Up the HP E2443B HP E2443B 1 2 Pentium CPU Preprocessor Interface tea Setting the Switches and Jumpers Mode of Operation HP E2443B The HP E2443B can capture Pentium CPU data in four modes Timing State Per Clock State Per Transfer and Debugger modes Switches 1 and 2 allow you to select the mode of operation For State Per Clock mode you can also have qualified or non qualified clocking selected through the Format menu State Per Transfer and Debugger modes only work in qualified clocking Switches 3 to 8 select the clock qualifier inputs for qualified clocking In the Timing mode you can select a buffered version of the microprocessor clock or a phase locked loop version The clock version is determined by the location of the jumper on the 1 x 3 header In Timing mode the signals are buffered but otherwise passed straight through to the logic analyzer In State Per Clock mode all signals are latched by CLK and clocked into the logic analyzer each CLK cycle see Chapter 2 for additional information on State Per Clock In State Per Transfer mode address pipelining is realigned and only valid transfers are clocked into the logic analyzer Debugger mode is identical to State Per Transfer mode with the exception that whenever IU IV or IBT are asserted data is captured regardless of whether or not it is valid Switches 1 and 2 determine the mode of operation see table 1 1 T
27. clock is captured The position of this jumper 1 only relevant for Timing mode The load on the clock signal is increased by one 74 646 input Note when the jumper is in the CLK position HP E2443B Setting Up the HP E2443B Pentium CPU Preprocessor Interface 1 5 PLL lt a n oj GND oj TCK n GND TRST n n TMS E2443E04 Co SYCLK Timing CO BRDY L BRDYC co ADS co EADS o HLDA BOFFs Figure 1 1 Preprocessor Interface Assembly HP E2443B Pentium CPU Preprocessor Interface Setting Up the HP E2443B 1 6 Connecting to the Target System Caution Caution 2443 The following steps explain how to connect the HP E2443B Preprocessor Interface to your target system To prevent equipment damage be sure to remove power from the target system whenever the preprocessor interface or microprocessor is being connected or disconnected Remove the Pentium microprocessor from its socket on the target system and store it in a protected environment Serious damage to the target system or preprocessor interface can result from incorrect connection Note the position of pin A1 figure 1 1 on the preprocessor interface connector and the target system socket prior to inserting the connector in the socket Also take care to align the preprocessor interface c
28. cuted instructions may be incorrectly marked If you suspect that the inverse assembler has lost synchronization re synchronize the inverse assembler by pointing to an executed instruction Once synchronized the inverse assembler will disassemble from this state through the end of the screen To point to an executed instruction 1 Selecta line on the display that you know contains the first byte of an executed instruction 2 Roll this line to the top of the listing 13 The cursor location is not the top of the listing In figure 2 2 the Note instruction DA HLT is the top of the listing 3 For the IAPENT or IAPENTD inverse assemblers select the Invasm field at the top of the display A pop up appears with the following choices Size 16 Byte 0 8 Size 32 Byte 0 8 Size 16 Byte 1 9 Size 32 Byte 1 9 Size 16 Byte 2 A Size 32 Byte 2 A Size 16 Byte 3 B Size 32 Byte 3 B Size 16 Byte 4 C Size 32 Byte 4 Size 16 Byte 5 D Size 32 Byte 5 D Size 16 Byte 6 E Size 32 Byte 6 E Size 16 Byte 7 F Size 32 Byte 7 F For the IAPENTE inverse assembler select the Invasm Options button and use the Code Synchronization portion of the submenu Size as used here refers to the default operand size for this code 16 or 32 bits 4 Select the choice that identifies which byte of the captured state contains the first byte of the code fetch and what the default operand size is for this code 16 or 32 bits With the inverse a
29. cycles that a hit toa modified line in the data cache has occurred BT3 BTO Branch target address bits BOFF A low indicates that the Pentium CPU should abort all outstanding bus cycles and float its bus on the next cycle HLDA HP E2443B A high indicates that the Pentium CPU has acknowledged a hold request and given up the bus Analyzing the Intel Pentium CPU Pentium CPU Preprocessor Interface 2 3 Table 2 2 Additional Status Bits Pod Bit Status Signals Description A low indicates that the normal execution of the CPU has been stopped and placed into an idle state possibly for execution of Boundary Scan Probe Mode instructions ADSC Address strobe used in chip set mode HOLD A high indicates a system bus hold request BREQ A high indicates that the Pentium CPU has internally generated a bus request INTR A high indicates an external interrupt NMI A high indicates a non maskable external interrupt SCYC A high indicates a split cycle more than two cycles will be locked together BUSCHK A low indicates that the system has unsuccessfully completed a bus cycle FLUSH A low indicates that the Pentium CPU will writeback all modified lines and invalidate its cache INV Indicates the final cache line state for an inquire cycle hit EWBE A high inactive indicates that a write through cycle is pending in the external system WB WT A low indi
30. d by incorrect signallevels Adjust the threshold level of the data pod Use an oscilloscope to check the signal integrity of the data lines as needed The state timing analyzers have a counter to keep track of the time from when an analyzer is armed to when it triggers The width and clock rate of this counter allow it to count for up to 41 93 ms before it overflows Once the counter has overflowed the system does not have the data it needs to calculate the time between module triggers The system must know this time to be able to display data from multiple modules on a single screen The HP 16540 16541A D Logic Analyzer cards are not calibrated Refer to your logic analyzer reference manual for procedures to calibrate the cards The default calibration file for the logic analyzer was loaded The logic analyzer must be calibrated when using HP 16540A D and HP 16541A D cards Refer to your logic analyzer manual for procedures to calibrate the master clocking system and ensure that the cal factors file is saved HP E2443B Pentium CPU Preprocessor Interface Herstellerbescheinigung Hiermit wird bescheinigt da das Ger t System HP 1650A B and HP 1651 A B in bereinstimmung mit den Bestimmungen von Postverf gung 1046 84 funkentst rt ist Der Deutschen Bundespost wurde das Inverkehrbringen dieses Ger tes Systems angezeigt und die Berechtigung zur berpr fung der Serie auf Einhaltung der Bestimmungen einger umt Zusa
31. display Figure 2 4 shows the settings to suppress unexecuted prefetches Figure 2 3 page 2 13 shows a listing with the unexecuted prefetches suppressed so that only executed instructions are displayed A comparison of figures 2 2 and 2 3 shows the difference in the listing display Second particular operations can be isolated by suppressing all other operations For example I O accesses can be shown with all other operations suppressed allowing quick analysis of I O accesses Code The Code Synchronization enables the inverse assembler to Synchronization resynchronize with the microprocessor code In some cases the prefetch marking algorithm in the inverse assembler may lose synchronization and unused prefetches or executed instructions may be incorrectly marked If any of the Code Reads are suppressed this could cause some executed instructions to be missing from the display To resynchronize the inverse assembler use the procedure on page 2 16 IDT Description The IDT Description settings include Mode IDT Start and IDT Size Mode can be Protected Real or Virtual IDT Start refers to the starting address of the Interrupt Descriptor Table and IDT Size refers to the size ofthe table Set these functions to match the target system settings In most cases the inverse assembler can automatically determine the target system settings and will operate properly regardless of the settings entered The inverse assembler uses the informa
32. ector Mapping 3 5 Nager 3 13 Dimensionsz iude guo ppp 3 13 Appendix Contents 2 Troubleshooting Target Board Will Not 1 Bent Pins 1 Slow or Missing 1 SlOW Clock nee ee ei ra ee es A 2 No Configuration File A 3 Selected File is A 3 Inverse Assembler Not 3 No Inverse 3 Incorrect Inverse 3 No Activity on Activity Indicators A 3 Capacitiye Loading idR A 4 Unwanted A 4 Waiting for A 4 Intermittent Data A 4 Time from Arm Greater Than 41 93 A 4 No Setup Hold Field on Format Screen A 4 Default Calibration Factors Loaded 16540 16541A D A 4 Introduction The HP E2443B Preprocessor Interface provides a complete interface for state or timing analysis of a Pentium CPU target system by an HP 1660A HP 16540 16541A D or HP 16550A Logic Analyzer The Pentium CPU configuration software on the flexible disk
33. essor code and disassemble it into Pentium CPU mnemonics which are displayed on the logic analyzer screen Unexecuted prefetches are marked with a hyphen The data mode inverse assembler IAPENTD functions like the default inverse assemblers except that it does not decode instructions or mark unused prefetches IAPENTD is useful for examining data flow while IAPENT or IAPENTE are useful for examining instruction flow You can also store data and re examine it later using a different inverse assembler The inverse assemblers only work in State Per Transfer and Debugger modes They do not work in State Per Clock or Timing modes Two different address labels are provided ADDR and ADDR_ ADDR provides the full 32 address bits A31 0 while _ provides the upper 24 address bits A31 8 When using the inverse assembler use ADDR_ in the listing ADDR_ gives you the upper 24 bits of the address while the inverse assembler display gives you the lower eight address bits A7 0 in its first two columns Using these two fields together gives you the entire 32 address bits The ADDR label displays the actual acquired 32 bit address with 2 0 000 binary When the inverse assembler is turned off the ADDR field can be used to display the full address in hexadecimal format Analyzing the Intel Pentium CPU HP E2443B 2 14 Pentium CPU Preprocessor Interface Prefetched Instructions HP E2443B The Pentium CPU micropro
34. g properly Ensure that the target system is on and operating properly If the error message persists check the that the logic analyzer pods connected to the proper connectors as listed in table 1 3 Troubleshooting Pentium CPU Preprocessor Interface 1 Slow Clock Troubleshooting A 2 If you have the preprocessor interface hooked up and running and observe slow clock or no activity from the interface board the 5 V supply coming from the analyzer may not be getting to the interface board To check the 5 V supply coming from the analyzer disconnect one of the logic analyzer cables from the HP E2443B and measure across pins 1 and 2 or pins 39 and 40 see figure 1 e If 5 V isn t observed across these pins check the internal preprocessor fuse or current limiting circuit on the logic analyzer For information on checking this fuse or circuit refer to the service manual for your logic analyzer If 5 15 observed across these pins and you feel confident that the 5 V is getting to the preprocessor interface contact your nearest Hewlett Packard Sales Service Office for information on servicing the board 2 GND 40 GND 39 5V 01650 67 Figure 1 Pinout of the Logic Analyzer Cable HP E2443B Pentium CPU Preprocessor Interface No Configuration File Loaded Selected File is Incompatible Inverse Assembler Not Found No Inverse Assembly Incorrect Inverse Assembly
35. gnals are generated by the preprocessor interface General Information HP E2443B 3 6 Pentium CPU Preprocessor Interface Table 3 1 Pentium CPU Signal List Continued Preprocessor Logic Analyzer Pod Pin Probe Pentium CPU Pin Pin Mnemonic Label s ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR HP E2443B Pentium CPU Preprocessor Interface DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA General Information 3 7 Table 3 1 Pentium CPU Signal List Continued Preprocessor Logic Analyzer Pentium CPU Pin Label s Pod Pin Probe i Mnemonic General Information HP E2443B 3 8 Pentium CPU Preprocessor Interface Table 3 1 Pentium CPU Signal List Continued Preprocessor Logic Analyzer Pentium CPU Pin Label s Pod Pin Probe Pin Mnemonic HP E2443B General Information Pentium CPU Preprocessor Interface 3 9 Table 3 1 Pentium CPU Signal List Continued Preprocessor Logic Analyzer Pentium CPU Pin Label s Pod Pin Probe Pin Mnemonic BEO STAT BE BEI STAT BE BE2 STAT BE BE3 STAT BE 4 STAT BE 5 STAT BE 6 STAT BE STAT BE 5 KEN STAT KEN CACHE STAT CACHE W R STAT W R D C STAT D C M IO STAT M IO LOCK STAT LOCK A20M STAT A20M Valid STAT Valid ADS STA
36. he LED on the HP E2443B indicates the selected mode of operation Table 1 1 Switch 1 and 2 Settings Mode of Operation Switch 2 Switch 1 Mode of Operation LED Color State Per Transfer State Per Clock Timing Debugger Setting Up the HP E2443B Pentium CPU Preprocessor Interface 1 3 Clock Qualifier In qualified clocking the level of a clock qualifier ClkQual is ANDed Inputs with the edge of the clock on the HP E2443B pod and the resultant rising edge clocks information into the logic analyzer The clock qualifier equations are listed in Chapter 2 The logic analyzer must be clocked as qualified for State Per Transfer and Debugger modes it can be clocked as qualified or non qualified for State Per Clock mode Note that for State Per Clock mode qualified clocking decreases the number of invalid data code states which are clocked into the logic analyzer since only CIK1 edges that occur when ClkQual is asserted will be clocked into the logic analyzer The configuration files set up the logic analyzers for qualified clocking Use the Format menu to configure the logic analyzer for non qualified clocking see Chapter 2 Switches 3 8 select the inputs to the clock qualifier These switches allow you to select particular cycles or operations to be clocked into the logic analyzer The inputs to the clock qualifier are selected by closing the appropriate switches For all switches which a
37. ing analysis HP 16550A two cards This logic analyzer provides 4 k of memory depth with 102 channels per card of 100 MHz state analysis or 250 MHz timing analysis This logic analyzer also supports various combinations of mixed state timing analysis C M How to Use This Manual Introduction 2 This manual is organized into three chapters and one appendix e Chapter 1 explains how to install and configure the HP E2443B Preprocessor Interface for state or timing analysis with the supported logic analyzers Chapter 2 provides reference information on the format specification and symbols configured by the HP E2443B software It also provides information about the inverse assemblers and status encoding Chapter 3 contains additional reference information including the characteristics and signal mapping for the HP E2443B Preprocessor Interface It also contains information on servicing Appendix A contains information on troubleshooting problems or difficulties which may occur with the preprocessor interface Setting Up the HP E2443B Introduction This chapter explains how to install and configure the HP E2443B Preprocessor Interface for state or timing analysis with the HP 1660A HP 16540 16541A D or HP 16550A Logic Analyzers Duplicating the Master Disk Before you use the HP E2443B software use the Duplicate Disk operation in the disk menu of your logic analyzer to make a duplicate copy of the HP E2443B master dis
38. k Store the master disk in a safe place and use the back up copy to configure your logic analyzer This will help prevent the possibility of losing or destroying the original files in the event the disk wears out is damaged or a file is accidentally deleted Equipment Supplied Note 2443 The HP E2443B Preprocessor Interface consists of the following equipment The preprocessor interface hard ware which includes the preprocessor interface circuit card and cables The configuration and inverse assembly software on a 3 5 inch disk Two additional jumpers HP part number 1252 3743 e This user s guide The preprocessor interface socket assembly pins are covered at the time of shipment with either a conductive foam wafer or a conductive plastic pin protector This is done to protect the delicate gold plated pins of the assembly from damage due to impact When you re not using the preprocessor interface protect the socket assembly pins from damage by covering them with the foam or plastic pin protector Setting Up the HP E2443B Pentium CPU Preprocessor Interface 1 1 Minimum The minimum equipment required for analysis of a Pentium CPU Equipme nt target system consists of the following Required 1660A HP 16540A D with three 16541A D Expansion Cards or an HP 16550A two cards The HP E2443B Preprocessor Interface which includes the configuration files and inverse asse
39. ld still get inverse assembly but it may be incorrect since some of the execution trace was not visible to the logic analyzer Verify that storage qualification has not excluded storage of all the needed opcodes and operands One of the cables board connections or preprocessor interface connections is probably loose Check all connections Troubleshooting Pentium CPU Preprocessor Interface A 3 Capacitive Loading Unwanted Triggers Waiting for Trigger Intermittent Data Errors Time from Arm Greater Than 41 93 ms No Setup Hold Field on Format Screen Default Calibration Factors Loaded 16540 16541A D Troubleshooting A 4 Excessive capacitive loading can cause signals to degrade resulting in incorrect capture by the preprocessor interface or system lockup in the microprocessor All preprocessor interfaces add additional capacitive loading The following techniques will reduce the capacitive loading Remove as many pin protectors extenders and adapters as possible e If multiple preprocessor interface solutions are available try using one with lower capacitive loading Unwanted triggers can be caused by unexecuted prefetches Add the prefetch queue depth to the trigger address to avoid this problem If a trigger pattern is specified this message indicates that the specified trigger pattern did not occur Verify that the triggering pattern is correctly set This problem is usually cause
40. legal instruction the message Illegal Opcode is displayed along with the byte s which caused the decoded illegal opcode This message is often an indication that the inverse assembler has lost synchronization see page 2 16 uj Do not modify the ADDR DATA DATA STAT labels in the Note format specification if you want inverse assembly Changes may cause incorrect results Also note that if the trace specification is modified to store only selected bus cycles incorrect or incomplete inverse assembly may result HP E2443B Analyzing the Intel Pentium CPU Pentium CPU Preprocessor Interface 2 17 IAPENTE Inverse Assembler Note Analyzing the Intel Pentium CPU 2 18 The IAPENTE inverse assembler contains additional features which use the increased capabilities of some of the logic analyzers It supports the HP 16540 16541A D and HP 16550A Logic Analyzers in the HP 16500B mainframe and the HP 1660A Logic Analyzer with software version V02 00 or higher For those logic analyzer systems the IAPENTE inverse assembler is automatically loaded when the appropriate configuration file is loaded Note that all the features in the IAPENT inverse assembler are also included in the IAPENTE inverse assembler see previous section The IAPENTE Inverse Assembly Options menu contains three functions display filtering with Show Suppress selections Code Synchronization and IDT description entry see figure
41. mblers Installation The following procedure describes the major steps required to perform Quick measurements with the HP E2443B Preprocessor Interface The page numbers listed in the various steps refer you to sections in this manual Reference that offer more detailed information prevent equipment damage be sure to remove power from the Caution target system whenever the preprocessor interface or microprocessor is being connected or disconnected 1 Set the switches and jumpers according to your measurement requirements see page 1 3 2 Install the preprocessor interface in the target system page 1 7 3 Connect the logic analyzer probes to the cable connectors of the preprocessor interface as listed in table 1 3 see page 1 10 4 Load the appropriate logic analyzer configuration file This also loads the appropriate default inverse assembler file page 1 11 5 If you want to fully capture the execution trace disable the cache If possible you may also want to disable page translation so the physical addresses the preprocessor interface monitors are effectively the logical addresses see page 1 8 ui Do not disable the cache memory if burst transfers are to be Note monitored Enabling the cache memory will allow you to view the data coming across the bus but the code may not be properly disassembled Also when the cache is enabled unexecuted prefetches are not inferred and the unexecuted prefet
42. modes the Pipeline Register Mux routes the output from the Registered Transceivers directly to the logic analyzer HP E2443B General Information Pentium CPU Preprocessor Interface 3 3 CLK DPO 7 DO 63 Status A3 31 Status gt CLK1 PLL Clock gt Cp Buffer 8 64 x gt A gt DATA DATA_B 64 8 A 3 nn gt 9 R Transceivers 0 gt STAT 3 29 r7 gt ADDR 73 gt 5 3 gt Pipeline 29 Register 23 ADDR 2 gt STAT 29 gt 29 Stage 2 22 Mux 23 gt 4 23 s Flip Flops 22 3 gt 5 2 Control DIP 8 Clocking x i Switch PALS E2443B01 Figure 3 1 HP E2443B Block Diagram General Information HP E2443B 3 4 Pentium CPU Preprocessor Interface 2777777 Clocking The CLK signal is buffered and sent to the logic analyzer on pin 3 of pod 1 For the HP 16550A Logic Analyzer this is L 7 for the 1660A and HP 16540 16541A D Logic Analyzers this is J 7 If there is no qualification to this clock edge data is captured on every rising edge of CLK This method is used in non qualified State Per Clock mode The Control Clocking PALs assert ClkQual to enable the clock qualifier for qualified clocking For the HP 16550A Logic Analyzer ClkQual is the M clock for the HP 1660A and HP 16540 16541A D Logic
43. n file from the disk 3 Select the Configuration menu of the logic analyzer 4 Select the Type field and select Timing Setting Up the HP E2443B 1 12 HP E2443B Pentium CPU Preprocessor Interface Analyzing the Intel Pentium CPU Introduction This chapter provides reference information on the format specification and symbols configured by the HP E2443B software It also provides information about the inverse assemblers and status encoding Format When you use the HP E2443B Preprocessor Interface the format Specification specification set up by the software will look similar to that shown in figure 2 1 There are some slight differences in the displays according to which logic analyzer you are using Table 3 1 in chapter 3 lists the Pentium CPU signals for the HP E2443B Preprocessor Interface and their corresponding lines to the logic analyzer uj The Setup Hold time must remain in the current setting 4 ns setup O s Note hold for the HP 16540 16541A D 3 5 ns setup O s hold for the HP 1660A and HP 16550 for proper operation with the HP E2443B 100 500 2 LA D Format 1 State Acquisition Mode Master Clock Full Channel 4K Memory 100NHz L CL f2 Cr 021 Pod D6 TTL Pod DS TTL Master Clock Master Clock Labels ADDR ADDR_ DATA DATA_B STAT Cycle Excptn xfer
44. ng warranty period Hewlett Packard Company will at its option either repair or replace products that prove to be defective For warranty service or repair this product must be returned to a service facility designated by Hewlett Packard However warranty service for products installed by Hewlett Packard and certain other products designated by Hewlett Packard will be performed at Buyer s facility at no charge within the Hewlett Packard service travel area Outside Hewlett Packard service travel areas warranty service will be performed at Buyer s facility only upon Hewlett Packard s prior agreement and Buyer shall pay Hewlett Packard s round trip travel expenses For products returned to Hewlett Packard for warranty service the Buyer shall prepay shipping charges to Hewlett Packard and Hewlett Packard shall pay shipping charges to return the product to the Buyer However the Buyer shall pay all shipping charges duties and taxes for products returned to Hewlett Packard from another country Hewlett Packard warrants that its software and firmware designated by Hewlett Packard for use with an instrument will execute its programming instructions when properly installed on that instrument Hewlett Packard does not warrant that the operation of the instrument software or firmware will be uninterrupted or error free Limitation of Warranty Exclusive Remedies Assistance Certification Safety The foregoing warranty shall not
45. ntium CPU Pentium CPU Preprocessor Interface 2 21 100 500 2 LA D Format 1 State Acquisition Mode Master Clock Full Channel 4K Memory 100NHz JL Lt Pods r 15 87_ Pod DS TTL Master Clock 1111111111111 15 87 0 06 0 ADDR ADDR_ DATA DATA_ Cycle Excptn xfer E Figure 2 5 Clock Qualifier Removed From Master Clock Analyzing the Intel Pentium CPU 2 22 HP E2443B Pentium CPU Preprocessor Interface The State Per Clock mode can be used with the State Waveforms Waveforms function of the logic analyzer to produce state timing diagrams The E horizontal axis displays state transitions rather than absolute time Using State Per Clock Mode 100 500 2 LA D Waveform 1 Control Print Accumulate off states Div Delay Markers 1 200 Off ADDR all 000 8560 68568 8570 8578 8580 0608 8588 8590 8538 FOE267FF C301 78BA 987 0582 8530 1 78BA 601 0 3010 5251 0003 20 E9F 1 8530 840F 908 0706 Code Read Read Code Read IFECOO 2 00 4 00 4 00 AEFC 2000 4 00 2000 1 Rd 43966600 43966600
46. onnector with the socket on the target system so that all microprocessor pins are making contact 2 Plug the preprocessor interface connector into the microprocessor socket on the target system If the preprocessor interface connector interferes with components of the target system or if a higher profile is required additional plastic pin guards can be added Plastic pin guards can be ordered from Hewlett Packard using the part number 1200 1753 However any 273 IC socket with a Pentium CPU footprint and gold plated pins can be used 3 Plug the Pentium microprocessor into the socket of the preprocessor interface board The socket on the preprocessor interface board is designed with low insertion force pins to allow you to install or remove the microprocessor with a minimum amount of force Setting Up the HP E2443B Pentium CPU Preprocessor Interface 1 7 U Care must be used when removing a microprocessor or socket from the Caution preprocessor interface board to prevent damaging the traces on the board 4 If you want to fully capture the execution trace disable the cache memory If you leave the cache enabled all data will still be captured and decoded but you may lose unexecuted prefetch flagging or synchronization with the execution trace To capture four cycle burst transfers you must leave the cache enabled This will allow you to view all data coming across the bus although some of the execution tr
47. re closed the signals are ORed together to create ClkQual therefore closing additional switches increases the variety of states which are clocked into the logic analyzer The different clock qualifier inputs are relevant only for certain modes of operation see table 1 2 For the modes marked no the switch position has no effect Note that for State Per Transfer and Debugger modes when HLDA BOFF is asserted the preprocessor interface automatically switches to State Per Clock mode regardless of the switch 7 and 8 settings The State Per Clock ClkQual signal becomes relevant If none of the clock qualifier inputs are selected then no information will be clocked into the logic analyzer When HLDA or BOFF is deasserted the preprocessor interface automatically switches back to State Per Transfer or Debugger mode Setting Up the HP E2443B HP E2443B 1 4 Pentium CPU Preprocessor Interface Table 1 2 Switch 3 8 Settings Clock Qualifier Inputs Relevant for Mode of Switch 3 Switch 4 Switch 5 Switch 6 Switch 7 Switch 8 Operation BRDY BRDYC ADS EADS HLDA BOFF Timing State Per Clock State Per Transfer Debugger n In State Per Transfer and Debugger modes the preprocessor generated signal Valid is also ORed into ClkQual therefore valid data transfer states are always captured In Debugger mode all states in which IU IV or IBT are asserted are also captured Valid BRDY
48. rnings in this user s guide must be heeded Contents Introduction Logic Analyzer Software Requirement Logic Analyzers Supported How to Use This Manual NENNEN Chapter 1 Setting Up the HP E2443B Introduction nenn ago ea ege Und 1 1 Duplicating the Master Disk 1 1 Equipment 1 1 Minimum Equipment Required 1 2 Installation Quick 1 2 Setting the Switches and 1 3 Mode 1 3 Clock Qualifier 1 4 Clock Version Timing 1 5 Connecting to the Target 1 7 Connecting to the HP 2443 1 9 Power Up Down Sequence 1 9 Setting Up the Analyzer from the 1 11 Timing Analysis hats 1 12 2 Analyzing the Intel Pentium CPU Introduction RR eee ir and 2 1 Format 2 1 RR 2 2 Additional Symbols 2 11 Lasting
49. roprocessor holds the address constant during the entire burst The inverse assembler listing displays the two least significant hexadecimal digits of the actual address derived by the inverse assembler at the left side of the column Up to eight instructions may be displayed for a single analyzer state because the Pentium CPU fetches eight instruction bytes from program memory If the first byte of these eight bytes contains a single byte instruction the next sequential instruction begins in the next higher byte This process continues from the least significant byte to the most significant byte until all of the fetched bytes are used When a single state contains more than one instruction each instruction is displayed on a separate line HP E2443B Analyzing the Intel Pentium CPU Pentium CPU Preprocessor Interface 2 13 20 The Pentium CPU Inverse Assemblers Address Labels The HP E2443B Preprocessor Interface software contains three inverse assemblers There are two default inverse assemblers IAPENT and IAPENTE and a data mode inverse assembler IAPENTD IAPENTE contains additional features which use the increased capabilities of some of the logic analyzers only available with the HP 16500B mainframe and the HP 1660A Logic Analyzer with software version V02 00 or higher For more information on the IAPENTE features see The IAPENTE Inverse Assembler in this chapter The default inverse assemblers analyze the microproc
50. s Bits 1660A and HP 16550 only Pod Bit Signals Description FERR A low indicates that an unmasked floating point error has occurred IERR A low indicates either an internal parity error or a functional redundancy error 5 IGNNE A low partially indicates that the Pentium CPU will ignore any pending unmasked numeric exception and continue executing floating point instructions for the entire duration that the signal is asserted This signal partially determines whether a machine check exception will be taken as a result of a parity error on a read cycle P7 This signal indicates the result of a parity check on a read cycle P8 CIK1 AP Address Parity for the address bus P9 CIK1 A low indicates a parity error on the address bus P10 CIKI FRCMC A low indicates that the Pentium CPU has been configured in checker mode while a high indicates that the Pentium CPU has been configured in master mode These signals are not available on the 1660 Logic Analyzer H These signals are only available on the HP 1660A and HP 16550A Note Logic Analyzers Each signal has its own label in the display Analyzing the Intel Pentium CPU HP E2443B 2 6 Pentium CPU Preprocessor Interface Table 2 4 2 4 Header Pins JTAG Description Test logic clock signal Test logic serial input Test logi
51. s while making measurements use this section to guide you through some possible solutions Each heading lists a problem you may encounter along with some possible solutions Error messages which may appear on the logic analyzer are listed below in quotes Symptoms are listed without quotes If you are still having difficulties after trying the suggestions below please contact your local Hewlett Packard service center for assistance If the target board will not bootup after connecting the preprocessor interface the microprocessor or the preprocessor interface may not be installed properly or they may not be making electrical contact Verify that the microprocessor and the preprocessor interface are properly rotated and aligned Verify that the microprocessor and the preprocessor interface are securely inserted into their respective sockets Verify that the logic analyzer cables are in the proper sockets of the preprocessor interface and firmly inserted Reduce the number of extender sockets see also Capacitive Loading Bent pins on the preprocessor interface pin protectors or adapters can cause system errors or inverse assembly errors Ensure all pins are properly aligned and making contact This error message might occur if the logic analyzer cards are not firmly seated in the HP 16500A B or HP 16501A frame Ensure that the cards are firmly seated This error might also occur if the target system is not runnin
52. ssembler also select Align Analyzing the Intel Pentium CPU HP E2443B 2 16 Pentium CPU Preprocessor Interface Rolling the screen up will inverse assemble the lines as they appear the bottom of the screen If you jump to another area of the acquisition buffer by entering a new line number you may have to re synchronize the inverse assembler by repeating steps 1 through 4 Operand Size symbol is displayed in the fourth column of the inverse assembly display for 32 bit operands The symbol will appear for default 32 bit operand operations as well as for operations when the operand size prefix is encountered and decoded Byte Enable The Byte Enables are not valid during cache accesses bursts Since Validity all cache reads and writes must be 64 bits all data lines are valid during these cycles Incomplete If a complete opcode is not present the inverse assembler will not be Decoding able to decode it A pair of asterisks will be listed on the display Opcode Data Most data is displayed in hexadecimal format An exceptions is the Numeric Bases operand for the INT value which is displayed in decimal Decimal numbers are indicated by a d suffix Branch Trace The Pentium CPU inverse assemblers decode branch trace messages Messaging which gives you branch target addresses This is especially useful for tracing execution while operating out of cache Illegal Instructions When the inverse assembler decodes an il
53. ssor Interface performs this primary function in the following ways Bylatching and buffering the addresses data and status of the Pentium microprocessor so that address status and data can be sent to the logic analyzer at the same time e By generating the logic analyzer clocks and clock qualifiers from the appropriate Pentium microprocessor signals and bus conditions All Pentium CPU signals are buffered latched by the Registered Transceivers see figure 3 1 One method of capture is used for State Per Transfer mode while a different method is used for State Per Clock and Debugger modes The Pipeline Register Mux controls the method of capture In State Per Transfer and Debugger modes KEN WB WT and all signals which follow address timing are also routed through the Stage 2 flip flops The Pipeline Register Mux selects either Stage 1 Registered Transceivers or Stage 2 data depending on the current depth of the pipeline The parent address is stored by the preprocessor interface until all of its associated data has crossed the bus When the Control Clocking PALs determine that the data is valid they assert ClkQual and the properly aligned data and address are captured by the logic analyzer The preprocessor interface will align all possible permutations of pipeline depth and burst transfers In State Per Clock mode the Registered Transceivers are configured as flip flops in Timing mode they serve as buffers For both
54. tion from these settings only in cases of uncertainty If you suspect that the inverse assembler is disassembling improperly check that these settings match your target system HP E2443B Analyzing the Intel Pentium CPU Pentium CPU Preprocessor Interface 2 19 7 Modes of Operation Qualified Non qualified Clocking The HP E2443B can capture Pentium CPU data in four modes Timing State Per Clock State Per Transfer and Debugger In Timing mode the signals are buffered but otherwise passed straight through to the logic analyzer in State Per Clock mode all signals are latched by CLK and clocked into the logic analyzer each CLK cycle This allows the logic analyzer to capture wait states and idle states in addition to valid data states In State Per Transfer and Debugger modes address pipelining is realigned and only valid data transfers are clocked into the logic analyzer Debugger mode is identical to State Per Transfer mode with the exception that whenever IU IV IBT are asserted data is captured regardless of whether or not it is valid Timing mode also allows a choice of buffered or phase locked loop clocks see Chapter 1 Chapter 1 shows the switch settings for selecting the different modes of operation In non qualified clocking 7 on the HP E2443B pod P1 is used to clock information into the logic analyzer In qualified clocking only those edges of 1 1 that occur when ClkQual is asserted
55. tium CPU Preprocessor Interface 3 13 4 0 in 101 6 177 in 45 09 mm Bee J 8 20 89 mm 000000000000000000000 D 000000000000000000000 0 34 in mr 8636 m 0000 6222 x 0200 5 9999 5222 0000 oooo 30 in 0000 B 5000 EX 762 m 2 oooo Bee 35 5580 M eg 2 3 50 in 8252 Hi 12 76 mm 0060060000006000000000 2 909000000090000909099 r 06000000000000000000 o lt 14 u H H 9950655 O 1 40 5 in 257 mm 12 89 mm 46 in 1168 mm 4 67 in LI 16 93 tr T PEO 039 in 1 mm 374 95 mm 167 in 425 mm _ 467 m 4 25 F 2443 5 Figure 3 2 HP E2443B Dimensions inches mm General Information HP E2443B 3 14 Pentium CPU Preprocessor Interface Troubleshooting Target Board Will Not Bootup Bent Pins Slow or Missing Clock HP E2443B If you encounter difficultie
56. tzinformation f r Me und Testger te Werden Me und Testger te mit ungeschirmten Kabeln und oder in offenen Me aufbauten verwendet so ist vom Betreiber sicherzustellen da die Funk Entst rbestimmungen unter Betriebsbedingungen an seiner Grundst cksgrenze eingehalten werden Manufacturer s declaration This is to certify that this product HP 1650A B and HP 1651 meets the radio frequency interference requirements of directive Vfg 1046 84 The German Bundespost has been notified that this equipment was put into circulation and was granted the right to check the product type for compliance with these requirements Additional Information for Test and Measurement Equipment Note Iftest and measurement equipment is operated with unshielded cables and or used for measurements on open set ups the user must insure that under these operating conditions the radio frequency interference limits are met at the border of his premises Note This declaration indicates compliance of this product with the German RFI specifications stated in the German Vfg 1046 84 directive
57. umber E2443 90803 Printed in U S A April 1993 Printing History New editions are complete revisions of manual Update packages which are issued between editions contain additional and replacement pages to be merged into the manual by the customer The dates on the title page change only when a new edition is published A software code may be printed before the date this indicates the version of the software product at the time the manual or update was issued Many product updates and fixes do not require manual changes and conversely manual corrections may be done without accompanying product changes Therefore do not expect a one to one correspondence between product updates and manual updates Edition 1 April 1993 E2443 90903 List of Effective Pages The List of Effective Pages gives the date of the current edition and of any pages changed in updates to that edition Within the manual any page changed since the last edition is indicated by printing the date the changes were made on the bottom of the page If an update is incorporated when a new edition of the manual is printed the change dates are removed from the bottom of the pages and the new edition date is listed in the Printing History and on the title page Pages Effective Date 327 Product This Hewlett Packard product has a warranty against defects in Warra nty material and workmanship for a period of 1 year from date of shipment Duri
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