Home

Mitac 8060B Service Manual - Laptop Schematics, Notebook

Contents

1. 5 lt Rete 25 22K 0603 0603 cens E Sbata 14 16 PCLINTG 1 ivre 8 WIRELED lt P m Rett 0 DFS OZ165 ibo si 15 5000 181 50015 me cows 080018 Spa 1 EAE 0515 case ces caso case coms 13 13 CSDD12 4 DTC144TKA 22U 010 010 0 10 010 0 10 0 1U HDD TeV 4 GOV 4 SOV 4 OV 4 OV 4 E HDD 10 ST 77 00 8 777 4 conje 8 HDDIS HDDI la HDDI3 SHORT SMT3 23 HDDj2 8 HDDj1 1 ed CSDA2 16 pes 15 SDA2 15 SDAT coal LL SDA CSDAI 16 14 17 18 CBE O 3 15 5040 HDA D coo Ta 16 15 5 53 Hs cesti Ed CSCS3 16 14 17 18 AD 0 31 15 3681 Hesioj cesio o 8051 16 1
2. CPU CORE PROCESSOR CORE POWER SUPPLY 1 468 0 748V 1 05V Banias VCCA ISOLATE POWER FOR INTERNAL PLL 1 8 1 5 VS 2 CPU CORE VCCP PROCESSOR I O POWER SUPPLY 1 05V vie Ute m 0 vss 146 HOLK CPU VSs 0 vss 73 H2 QUIET POWER SUPPLY FOR ON DIE COMP CKT 1 05V VSS 47 CPU 815 T Borko vss vss 74 24 VCCP 2 VSS 48 7 HCLK CPU BCLKI voci vss vss_75 VCCP 3 58 149 HBPMO E vec 2 vss 3 76 Hc VCCP 4 VSS 150 88 4 vss_77 6 HAG 31 lt gt 3 6 VCCP 5 55 151 00503 2 RTE SONIA vss s vss 7s HDO 6 VSS 152 Berit VSS 6 vss 78 As Dor VCCP 7 vss 153 BPM 5 7 13 p Du VCCP B VSS 164 E HTCLK vec vSS VSS ss p As close as possible vece S VSS 155 SI 90 ata vece ves vss 2 Dar
3. ADINP 2 O ADINP_1 O ARA 22 LUMT lt 1 prai m rat 100 10V Pesi 71 PR3B PR22 osu a os os os te gt ATI ps2 Hi 0603 777 PR55 i E PC68 PL26 PL27 A D Sv BEAD BEAD NA T 0805 T 0805 PH ATI pm E PR550 PRIS 71 PCe0 2 i poses A Posse osos A Tu som bm ES E PRSt PRSO qU 16V 1 fox S fore T dis aos Gr TOV si 5 Q 4 57 oe A m m A puzi Sasssov ra i Mur Sos ER PCI 0070 00 CSSP 56 PC553 1 mE 2 cts essa i REF ser 28 puss eni 1 H oa PS 1 8 Pw24 1 2 Pw26 er ili 15 ODBATT 1 1 L tod su 3 ibo CHE m EA a enor pono 20 E S lor Be 4 4 es cse Hg Sov poa 0 poss T poser 222425 ADEN lt 32 acok 27 805 rcioosos 10 190 a 109 jou 18 18 bei ai 1210 1210 0603 1210 1
4. BEAD BEAD oman pws ALWAYS o 1 2 PRSSI me 47 we Dre S leer 1 1210 0603 1812 0603 25V 50V 25V 50V x XSR PRS 0 1 2 pcre 47 1 2 1 sov PRI 0 A 15 ho 1206 1206 1 508 4 Pras 22 28 PWRON 2 sers 28 a na 2 6000 27 ENT 1 2 mg 4 2 O43V 7 3 26 PUI6 BEAD 0805C 1 pras Q Prat ona 100P 1 1 PRS6 4 25 508 CDRH127 100MC 0603 1 ONS 1003 2655 Pose 10 4 2 5 uis 24 220U 2200 PC54 Riza 53 7 p Pa TRE 6 GND BEAD 0805C EA 1 2 1 2 is Mi ours 2 SHORT SMT1 PR564 SI PR562 8 21 PC94 0 NA REF OUTS 1 470P 1 0608 p 9 FB5 PR30 777 1 95 10 19 2 4 PRO nis 10v n 18 100 HAITELI2UA PLsoS E 9 PLU 77 Reo 1 sep veo Li BATSSA a p eli egli 1 2 da 1 18 T raso
5. fen MDO MD1 MODE Description gt Install keyboard 80V 1 Remove keyboard AC 98V 0 MODE1 Expended mode with On Chip ROM disable E 0603 1 0 Expended mode with On Chip ROM enable iden E LUMT 28 500 750 uA ET 1 Single Chip mode R659 4 A R6SI ais 5514 1 2 2140 E 1 2 1 1529 i 2 nSwosc VALE 21 44 a DE 3 5VA VDDS 4 RLS4148 NA Close to H8 3437S 5 asv 1 S60UH NA 508 UNA GAUNA ACES 85203 04 02 1202 100M 20 0603 71 cass 1 1608 case D516 50 E 640 oaess 0 R290 GIU 010 128 0603 0603 0603 0 0603 0603 9 i vun 50V 50V 50 507 50V Rese 97 40K 4 777 0608 77 RP531 34 Pa Come From Battery 21 SCROLL 24 44 BATV 24 5 Abo asi lira Aes i are BAC 64 1K 1K TOKINA O10 0603 25 0603 0603
6. Riga AUDIO CODEC g mapa ne prt 3230806 R200 JUNE IN 20 E avs 24 1 2 60 INR 0603 d 9 7 m 0603 C203 TA 1 8 il lg 1208 1008 8230 R222 1202M100M 1530 bu 100 1608 AVDDAD 1202 100M 9230408 0603 In 0603 0603 ACBITCLK 1508 14 ino E 1 2 ini FE _ C840 10 Cddec __ NR ERR I GND 50 in 0603 C247 C248 ADP3301AR 5 gs Be ge TD ee du ne 10V 50V 50 0603 1206 R216 2 4 iu SK 0607 Close to ADP3307 Coke to Codec 15 18 20 ACRST MORSI AGND AGND 1 51 MODEM SPK 1820 viz TOKINA 0603 151820 ACSDOUT em R265 C EE C218 1 220 0805 80 20 1K 58 s ACSDIN BED BE 15 RR 88 98 24 Gan 1 220 0805 80 20 sl per vici lai C228 1 10 10V 1548 20 ACSYNC I SDATAIN 24 1 AU dave 0808 AGND ACBITCLK SYNC H 15 18 20 ACBITCLK 4 N 20 C834 10 10V 0603 8238 y 0603 RARA BITICLK i JCDROM RIGHT 16 ES 0839 AU 0603 R252 1 ost dla con 1 TAK
7. DVMAIN 08050 2657 pesos Pesos 504 Pesos Posos 0010 150 180 150 0603 0603 0603 0603 7288 7243 Ap 7243 PASO 6 50V 50V 50V 50V 2 e 14 15 DPRSLPVR 4 2 285 9 M 777 1 100 PRE 0603 1 M 1206 PRSOS 50v 10V 10 10K 10K 0603 4 eta 1 Posti X o 1 2 ou 508 GND 508 GND 7 CLK ENABLE 1 Y 4 p PR506 20501 1 PCI POSESPCSSSPCSO 0502 503 PC2 4 o PR507 2 8200 200 8200 2200 2200 220U 0010 010 100 100 PRI 4V 7843 7348 7343 0803 0803 1210 1210 i Pu 002 200 50 50 10 10 1 1 SISSA BATS4A 85285592854 Pug Put id SI7B86DP SI7886DP 3 522 woo 30 508 GND 508 Pbi x cp le le cl 3 1 1 2 8 o H2 4 EC310804 B2 PGND so 506 27 PRA si 255 1 2 XE DI 24 o 7 SHON 02 REF H2 10K 10 UM 04 21 TOT 0603 vec 05 TD 77 2 2 PRS T pos p peste 29885 Ms 10 10 0 470 Dorze 0608 0608
8. 5VS J6 3VS 0501 ECIHFS2 5VS DDC2B 9 S F503 c723 FASOI mircoSMDC110 R66 R67 5VS R583 R581 10 Po 10K 10K 2 2K 2 2K 7 SDA 5 D SZ 12 10 0502 2N7002 0513 o HSYNC 12 HSYNC_CON 13 AB NC7S08 y vec HS 0514 m VSYNC 12 ci 4 VSYNC_CON 14 AB NC7S08 Y U4 5 PI SCL 5 15 e 7 9 lt Q503 Q 2N7002 gt 5 RED 1518 1207 100 Controller e 5 GREEN L519 1207 100 gt lee e e 2 BLUE L520 1207 100 NV18M fro fo fe 6 7 8 10 C79 18P il RP503 CP502 CP503 22p 4 cl R579 R143 xi alle e e Hm e e e i Leo eee 1 100 8060B N B Maintenance 8 5 Memory Test Error Extend DDRAM is failure or system hangs up Memory Test Error 1 If your system installed with expansion SO DIMM module then check them for proper installation One of the following components or signals on the motherboard may be defective Use an oscilloscope to check the signals or replace the parts one at A time and test after each replacement 2 M
9. Layout Note TXOUT0 1 2 3 0 1 2 3 OAS PT ERE S W W S 12 5 5 12 mis savs i as shortas possible LCD VCC 1A Sl4800DY sos savs 1503 m 4 A E TU 5 1 LCD ID Select Table RP 4 184 oun 5 5 Pouto ouio T PEET si Display LCD ID3 LCD ID2 LCD 101 10 TXoum TXOUTO 10 4 E 4 19 C561 C25 2012 C570 C563 C572 fa per TXOUTZ E TX er m 0603 LEONE ogos 4 E H i 1 16 xus na X38 5 0 TOUTE 10 Close to LCD Connector can 10 LCD Ibo TERR 1 Re 21 m pes 10 LCD 01 em ICD 102 2 6 25 26 2 10 LCD I2 1500 i z d 21 Q Z DTC144TKA 98 ___ LENPVDD 10 ACES 77 87216 3003 207 58 2596 F503 mircoSMDC110 DFS savs 45V8 T T 1 1 DI Dig Di D9 07 EU E qe e E A 4 4 4 5 5 z 2 5 5 onem DDC2B 1 40mil G0mil 8011892 8 8 g g g 3 g W S 16 12 12 12 16 mil 22 5 22K nU E 2 2 2 s 226 a Close to VGA Connector k d A rei 1 L5181202 100M 1608 x os i i 5 4 10 i 5 L Elos i d lt VGA 4 55 13 O suyin Qnis osoz 6 gt 732254567 soa s SD E 119 10 SDA 1 usta e 15 5 FASOT I
10. SERIAL RESISTOR DIMM 1 DIMM 0 DDR 25V DDR 25V DDR 25V DDR 25V 1 a MDD2 9 9 7 REF 125V HDD 5 3 6 MDDS 104 1 16 e 3 100887 E m WDD MDT 1 B REF DIM 1 2 REF DIM 3 147 568 6 NDU RPS NESS 4 MOOSAD RPXB 6 Moo MD 1 KDDS 104 MDOT 31 vss VSS17 Ha nova 5 12 MODI mor 4 1208 m y Pa mo Leica Wbbis 1100 Dos Pig i 1 02 NUT MODI most voor 017 i 2 Wb MDOSAT ms Mode tg 0080 12 100 1 16 MODIE diis 4 1 x M 6 0137 5 12 MODIS RPX amp mor AB vss2 vssi 18 por 3 14 MDOSAT 56 8 Mois WDi2 amp 11 MDT 003 oo moo 3 MDDI 7 10 MODE 215 0012 22 5 ja MODIS mg 24 MOOT me 1 Rc 3 2 MDOSRY d wona MOTE 15 MODIS a WDD3 us 3 14 _MDOSAZ RPS moon 883 vesto Hi 0010 1 16 MDDET T n fa MODI mr a 3a mos MDDTE RP510 6 Mo20 12 ma Don 095 Ege be DORT 35 CDDRU MDDT RPXB 6 6 11 6 DDR3 6 CLK DDRO 6 MDIS IL 6 CLK_DDRS TRAE 37 6
11. o 24 C 24P worse 331040050016 CONHDREMSP 03MM ILLAD 291000021101 CONHDR MA LIPHLL2SRIADEL 201000020304 CONHDR MA GP L2SMM D SMM VA 331130004014 CONOR SIR MA P1423 AUS 291000142406 N FPC FFC 24P 0 5MM H 2 R A SM ON ON ON ON ON ON ON ON ON ON 122 8060B N B Maintenance 9 Spare Parts List 4 __ fasuosrommi mao o i poum caorann mew fasono assoni propane ses 331810006044 CON PHONE JACK 6P2C H11 5 RJ11 T 331910002006 JACK 2P 20VDC 5A DIP 331840010008 CON STEREO JACK 10P W SPDIF R A 331000008062 CON USB FM H15 54 R A 4P 2 SUYIN 345673100028 NDUCTIVE_TAPE TP COVER 8060 cowpuemne marea co O wem owacrmamwsumn mas woes o Lumen owucrmamwsemmam o wee O O TT MS 20673100002 COVER ASSERINGE 060 EE 340673100007 COVER ASSY LCD 8060 331840005007 CON STEREO JACK 5P R A W9 1 LGY2 J501 J502 2673100024 NTACT PLATE W5L6
12. 20 16 PDREQ PDDREQ SDDREQ SDREQ 20 16 PDIOR PDIOR SDIOR SDIOR 20 16 PIORDY PIORDY SIORDY SIORDY 20 kb sow acar SD spe pu zd 8 19 pesi Posi sposi 5005 20 16 AB140 Pposs Spcsss pAC22 SCS3 20 ms lt nose 16 IRQ15 IRQ15 20 Boaso 25 36 MITAC 2 ICH4 M 2 2 stom Document 414676300001 vo Thursday June 12 2003 Presi 35 o 28 PDF created with FinePrint pdfFactory trial version http www fineprint com 14 PCLREQA 427820 TRDY 14171820 STOP 1417 18 20 FRAME 14 17 PCLINTF 143721 SERIRO 1420 REOS 14 17 1820 ARDY 14 PCI INTH 14 17 PCI REQO 9 14 PCLINTA 14 20 PCLINTB 21 22 AGP BUS PULL UP DOWN ST 1 has an internal pull up straps on BPSB for 100Mhz ET 9 asea 0 Res 2 9568 TKNA B2KINA osos 0603 Age sre 69 AGP STi EAE a 69 AGP STO Reo Q R570 KINA 0603 lt 0603 ODEM MCH STRAP SETTING 512 x i lt x Test I x 00 lt PCI BUS PULL UP DOWN savs Rp526 PCI bue 21 r PCI REQ2 1418 i POL PCI REOB 14 41 17 PCI_REQS 14 L 14 s 208 RI POLINTE m d
13. 6 56 482 nnna 10 6 voso pad paas 8 rover 1 16 6 MD55 155 0012 VDD30 H i por s 6 RES 157 vppia 188 na DDR4 6 DDR1 6 3 34 MDOSNT pu MDOS6 p je DDR4 6 ICLK DDR1 6 2 m 184 48514 vsssi HS me 6 aos 168 Do4s 0052 182 053 5 aes pass posa 166 2075 1 10 168 1 a Mose jeg Yoo 190 1 16 pesta NOOO 7 Hz MODE 6 ee paso H TEP 6 MDS7 Hs sr 8615 vasa H4 3 E um 6 062 oss 1 Dass 178 15 Most E H 0056 OD 381 00015 VOD32 MODET 10 ia 8 9 ee 0057 DM7 185 186 1 16 r 5526 5554 na move E 338 RP514 moor 185 ER 1459 3 14 56 ore em ar 8 2 I 7 14 SMBDATA 82 sao 194 SHEDATA 5 12 6 VDDSPD E A a Riso V V 0603 2188 voni bus 20 lt 16 0037 OGMM200P IS 2 MODIS RP517 137640871 QUASAR 3 14 15035 su CA0123 200N01 3 10082 6 MATT nit bs MAAS Lae ADDRESS 001 ADDRESS 000 5 12 SWEA 4 2 MSWEA 10 53 6 SWEA rief hs 1 5 MAT 1 2 Ke MAT rds ads DDR 25V R629 499 Close To DIMM 0 Close To DIMM 1 Max VREF load
14. L1 L10 L11 L12 L2 L3 L4 L5 L6 332673100003 FFC TP 8060 332673100004 MB 8060 a cms gt 273000130001 FERRITE CHIP 1200HM 100MHZ 1608 273000130019 FERRITE CHIP 1200HM 100MHZ 1608 273000130019 FERRITE CHIP 1200HM 100MHZ 1608 273000130019 CHIP 1200HM 100MHZ 1608 273000150013 CHIP 1200HM 100MHZ 2012 273000150013 FERRITE CHIP 1200HM 100MHZ 2012 FERRITE CHIP 2200HM 100MHZ 1608 FERRITE CHIP 2200HM 100MHZ 2012 FERRITE CHIP 6000HM 100MHZ 2A 1 FFC AUDIO 8060 C 213000130015 273000150001 273000130006 332673100002 _523467310004 272601227501 312278206152 _227673100001 _227672300004 81676300002_ 81676300001 _273000610025__ _273000610025 _273000130001 _273000130019 _273000130019 273000130019 273090150013 _ 273000150013 2730110015 _273000150001 273000130006 332673100002 _332673100003 _332673100004 _345673100080 _345673100015__ 124 8060B N B Maintenance 9 Spare Parts List 6 art Number 282574164002 284501032001 Description ____ Location 8 IC 74VHC164 SIPO REGIST ER T SSOP U501 IC ADM1032 TEMPERATURE MTR S08 U501 U6 28600204000 28346657000 28346754000 1CBQ2040 GAS GAUGE S0 6P IC EEPROM 9346 64 16 BITS SO8 SM U508 ICEEPROM M24O02 WMNGT 2K 908 SM 283410310002 IC FLASH 512K 8 90
15. 5 SUSB 1 2 RTCCLK Low gt High WAKE Press Power Button DC DC PWM Controller 4 VRMPWRGD DC DC Circuitry MAX1907 Power On Turn On 1 5VS 1 8VS 3 SUSB Suspend Sequence VDDR_MEM2 5V 3VS 5VS CPU_CORE 8060B N B Maintenance 1 3 6 Suspend to Disk Sequence CPU Banias Produce Stop Grant Cycle 2 CPUSLP 1 STPCLK ICH4M 4 PCIRST 82801DBM 3 SUS_STAT 1 STPCLK High gt Low 2 Produce CPUSLP 3 SUS STAT 2 4 RTCCLK High gt Low 4 PCIRST 9 15 RTCCLK High gt Low PCI Device MCH M 5 SUSB 1 2 RTCCLK High Low PCI4510 TRL8101 Odem 6 SUSC 1 2 RTCCLK High gt Low PC87393F 7 VRMPWRGD and PWRGD High gt Low 5 SUSB 8 505 6 PWROK D D Board Embeded Controller 1 Received SUSB turn off 5VS 3VS Hitachi H8 3437S 1 5VS CPU Core 1 H8 Received SUSC 2 Received ON High gt Low turn off 2 Send ON High gt Low 1 8V VDD 2 5 3V 5V 12V 7 PWR_ON 5V Graphics NVIDIA NV18 PRO Turn Off PWM MAX1907 1 Received 5V 2 Send VRMPWRGD A 23 8060B N B Maintenance 1 3 7 ICH4 M 82801DBM GPI O Pin Define Plane Type PCIRST after PCIRST suum fans ______ fm fans oe tm ow 00 1 1 uz mes ume oe
16. PUI9A LMV393M i L 77 777 LMV393M ADINP o PR52 PD6 10 310504 3V gt 1 5V 3VS gt 2 8VS DCIN PR21 10 PUS02 ADINP 1 o e CSSP P28 PL26 3V AMES8801LEEV 1 5V 3VS AME8801LEEV 2 8VS 1 3 VIN X 4 13 VIN 4 10 e Ps 9 ey P our ADINP_2 e CSSN PC58 PC60 L PC43 44 L 519 522 i5 po T 15 CF de Ii lt P PU21 77 77 77 77 PD503 BATS4A 1 ki e REFIN pst 25 4 L PCo3 PRA ayy 100K L PC553 Fa Olu PUI4 PUI7 e 24 A SI4800DY SIA835DY SIA835DY PR29 PL25 PRI7 8 8 49 9K SS 4 7UH 05 7 EN 7 3 77 ux 2 itt PR42 COSE gt 141 5 2 a 3 44 0 DION gt PR23 PR24 P22 e ICTL PUI3 1 1 PC83 21 c A 2 PC567 PC85 PC6 DLO r e 10 l 10u 0 1u S IM Eme 77 20 PCI PC72 e V PR31 19 O lp O lp U18 40 LLIMIT 0 CSIP 4 4 e IINP 18 CSIN pcso Ls PESI PR38 paar Li 10p 12 1K Micro Controller 5VAS DVMAIN 5VAS DBATT 5VAS PR25 o PR549 100K IM 8 3437 PR32 PR548 m 47_ BATT_DEAD m 475K 4 7K 121K 402K si PROA y 5 PQ3 0512 Ri BATIL DEAD 1 i 1 LLOVP E 2N7002 DTCIA4TKA w 6 PQI SCK431LCSK 5 PUI9B 8060B N B Maintenance 8 1 No Power When the power button is pressed nothing happens no fan ac
17. 5 CD 9 mt 9 ona eni La SCROLL 470 A oa 52 Se NUM Ae 4 0603 HDDACTP 5 Ed 6 POWERBTNLED1 CL 190G 10 AC POWER 470 for R02 Put No BATT LED R2 1 0603 Z7 k WIRE LED pai la gt baia R Pesi PRI o VREF H8 RESET 9 91 BATT G cL 1906 DDR 25V 1 qe VSENSE 14 GND vcc 25 1 sl REF 125V 1 pi 1 AVIN TT o GND M POWERSW ea 985 Jepe poso Peso e t E 010 12996 ou AS 220 FIT 5 1206 0603 SOB 2 0603 7343 J tov 50V PR2 50 av TSVIZOMA 470K 8 5 05 0603 201 4 pesta cs 7 77 0010 0 10 010 0608 50 0603 50 0603 50V ENPBLTI L501 1 BEAD Ji 06030 11 as uoa 2012 21 1202 1000 313 BLADJ 1502 4 BEAD 113 06020 AC POWER Se 87 gt 1208 FATTE 4186 PL1 BATTR 41 9 1 pp 11 414 S14800DY 1212 1202 100 1200HM 100MHZ PL2 2012 5VAS 1 006 PR5OB dea Lie DF13A 12P 1 25H 1 FTS 7243 1000P 1503 C504 1202 100M 1875 0603 25V 1202 100M 010 2012 47 50V 20 50 2012 0603 lu 0805 ii 50 5 J 1 26522 554 4 100 0010 PRB 1206 0603 PWR_ON 77 pd vm tov 50v 1000P 1K 0603 PR7 50V 470K 0808 a PUA nh PUSOI 5148000 hi v 1 IL 4 i Ww PcsiUl 512
18. A VDDAD P19 D28 5 18 gt 3V_LAN gt AVDD LAN P24 PUI2 P25 P24 PUS06 45V 9 S VS UIS VCCA PU6 PL2 PL3 PR7 PUS PU7 PL4 PL6 a gt P27 1 2VS P27 si P4 VCCP VCCQ PU4 PL503 PUS02 PUS03 PL502 PR508 PUS04 PL2 PU2 18 VS PUSOL Main Voltage Map 0501 3VS SPD Audio Board P7 L524 gt 3VCLK66 P7 1 523 gt 3VCLKCPU L12 E 3VCLKANA P7 L525 gt 3VCLKPCI L9 P9 ILS P23 VCC3 IR P25 R186 me VHI ICH 1 5VS PL4 PU3 VGA 2 5 5 6 PRI PUI DDR 2 5V REF 1 25V D D Board 90 8 1 No Power When the power button is pressed nothing happens no fan activity is heard and power indicator is not light up 8060B N B Maintenance 2 0 ALWAYS PD506 Mother Board ADINP BAVTOLTI JL502 2 gt lt ADINP_1 5 va gt lt O ADINP 2 ini J23 6 5A 32VDC du d E 1 501 zen POWER IN le eee o Y Hr dt 5 t gt do DVMAIN odi PR37 A 2 549
19. AVDDAD 3208 5V CD 3VS R210 o 47K 10K R199 J505 U14 12VS 0 A j v O 12VS L30 R211 1 D 3 c207 L Internal 12VS ADP3301AR 4 1202 100M 47K EN MIC C203 99 eun 2 Microphone 0 01p lo 7r 2 8 7 5 0 1 D 5 77 8 1 2 7K Jd sp a NR 1 C247 C248 VCC WE 19 0 1p R214 T D ERR 90 1930 AVDDAD Li 4 7K R219 J506 51230405 120Z 100M 19 U13 1IN 68K a 9 LM MIC 3 15 77 25 38 2 3 R216 330K AVDDII 2 DVDD 1 2 nie n MC33078D 5 iria MIC 2 14 P20 C827 C830 C828 C225 2IN e 11 en T 21 3 6 3 20UT 2IN 8220 R215 100K 6 8K C188 ACRST ii C200 T 220P F 10 5 ACSDIN R673 22 8 Pi R217 22K sla ACSYNC R656 2 10 le ACSDOUT R655 2 5 48 SPDIFOUT 18 U507 ACBITCLK R672 22 6 4 23 C215 22 R227 IK LINE IN L 17 3VS 24 C211 22u R224 IK LINE IN R 16 216 L C218 R230 R222 Controller SPK_OFF MUTE_IN U17 100P 100P 100K 100K To next page 35 AOUT_L Hub Q507 rr DTCIA4TKA si NOUR Midian 1 ICH4 M J507 R305 aa hala 47 0 MINIPCI_SPKR MINIPCI J3 82801DBM 2 20 C834 lp R238 1K CDROM_RIGHT 2 m LC202 Pio ist R270 18 C839 lu R252 IK CDROM LEFT 1 SBS 4TK AVDDAD AVDDAD 19 C837 lu R247 IK CDROM COMM 3 C261 R283 L 253 9 23 25 2 10K gos C843 ione CDROM 47K 22P Connector 2 12 p
20. oad 040 610 010 010 040 osos 0603 osos osos 50V 50V 507 50V 50V 50V 507 50V 50V 50V 507 50V 507 Tie DDR SO DIMM Memory X 2 ize ev Bron Document 411676800001 fino Date Thursday June 12 2003 Bheet sE PDF created with FinePrint pdfFactory trial version http www fineprint com Place under the GPU 6 AGP_AD 0 31 lt EDS 2 PCIADO AGPVDDO 0 04 58 1 PCIADY AGPVDDO 1 2 5 PCIAD2 AGPVDDO 2 PCIADS AGPVDDO_3 4 4 ol AGPVDDG 4 cesa IL ceza 1 ome i VGA MENOS PCIADS AGPVDDO 5 osoa 1206 MEMA_MD 63 0 12 MEMB MD o3 0 5 PCIADS AGPVDDQ 6 10 10 al 11 MEMA MD 63 0 Td GND_77 PCIAD7 AGPVDDO_7
21. Bos Ci MEMANUN Gt MAE 7 bar DI 21 con Mio DAI COSTIERE ASAP 2597 MEMA_OSO rm pose AL ggg BAO 8 40 Bat 42 Pe bos Di Das ii 9 MEMA lt gt ATO H 2 eas ned DO 0012 2 renames i ai E venes pors Ela FER TS HER son ER 9 MEMA CAS MEMA Cj LH RAS 0081 051 0951 arr ass MENA MENR WE CAS ix 8 MENA eso TEMA We boss boss MEMA 9 MEMA CLKO VENA Lio FE 0603 MEMA 0017 9 MEMA K 0018 9 MEMA_CLK1 x pais 2 057 1 2 tts bore 1 MERI CRE Luh ee ba 9 Mi Mii H2 MEMA MD52 oe 0020 Fd DE 0020 jH WEMA MOSS Li VREF 0022 VREF poze sti MENA MeL pon Tiz MOL pce x mi pose SIE gt E nase ri ss AS NG2 2 S RE isso 1 Ms pas aia MEA pom 04U C38 8545 0025 12 NIE 0603 C610 EDO bs 0608 ou 10K NGS 0025 QU 100 NGS paas Ce 2 E 1206 0608 NOS 0027 0808 1206 NCS 0027 812 MEMA WDS ov baer V 50 WV PAS
22. JP BEAD 50 50 0603D_DFS via GND dr T 8888 335225 ICH4M HAS INTERNAL PULL UP E i i promo es a 2 To 28 39 AWRETN k 3 Ae 7 piane prziane 40 17206 5 KOF 28 PI9AS Praians 41 KIT n KO PNM 050 v KOE 28 Pisas PISIANS 42 CHET DTCIAATKA n E PIG AS preransiDAO 4 IU CHG 28 Siml Hi iow 11010 S 3 KOE 12 E PIZIANTIDAI 45 BLAD 28 ignal 1 S Hir Hd 57 20a Micro SA 21 7 CLASE 1 12 TUN Pole Controll DELGADO ros H amp LID Normal Suspend ICHABTN a sor zm DRE calet ontroller En Giorno i IRQ4 RXD1 T k Do 5 18 ROT 51 passata 1 8 2 Ha SOS R293 Lm P27 A15 P9O ROZESC2 mad Sat E 32 00 Pav IRQvEIOW 24 TOWEHEYY 2 i KOs sge 53 28 i POWERSW 28 E P32HDB2 D2 2 WOL TOWN 4 Koz Toz a ge 8 L gt AVOLDOWN 19 du P34 HDB4 D4 Posas 18 E 4 A 9 X 4 P35 HDB5 D5 Pesio Aol 1 024 a 88 pag HDBSIDE PSTIWAIT SDA H Erw Las ee Es H8 MODET 1 2 ADJ BTN 500 7 19 AVOL_UP PAO TMCIO Me TIN LT
23. Mou HSYNC 1200HM 100MHZ dala MBA Connecto 4 Aa NG7S08 RP502 CPso1 cP503 cpso2 100 8070 ro VSYNC Z2PAINA ies 2254 1208 58 1 rm 1206 1206 5 1206 1206 tov o usta Li T pinne 1 iie vsvne ila s lo x R579 0805 10 A 4 eiaha R606 2N7002 TOKINA R143 0805 0603 LIT 724 dul cuo id dud denis R607 14 1 10 0603 0603 MITAC Aris LCD amp CRT Interface Eustom 411676300001 1 10 Number Thursday Jane 200 13 or 28 PDF created with FinePrint pdfFactory trial version http www fineprint com savs u507A 3 vss D22 VCC3 3 vss ME Ves acta 3 VSS ats a vss VCC3 3 vss VCC3 3 vss vss AGP BUSY VCC3 3 VSS POLINTA bE LEL apa
24. vee cese l cer 1 45 18 5 FBADM NIE 470P 470P 2200P 2200P 2200P NV34M i E onn 6 CBE 0 3 VDD 3 ae ae 2209 11 0V NV31M 6A FBAD25 FBCD26 T GND 9 PCICBEO_ e iy 1 0v 26 FB DLLVOD FBCD27 10 XT Vor 151 2V NV34M 7 8A FBAD27 MS PCICBEZ VDD 6 1 T pax sii 2 FBCD29 T GND 12 VDD 7 1 FBAD29 FB_VREF FBCD30 T_GND_13 e VD 258 Que oom 5 FBADSO TOND 14 e EMA o POIRST PCICLK 9 0603 0608 0608 1 1 FBCD32 T_GND_15 MIS 6 14 17 18 2021 PCIRST PCIRST_ voD io FBAD32 786033 T GND 16 0711 FBAD3S FBCD34 T GND 17 ROC 6 AGP_GNT LR AE PCIGNT_ 12 FBAD34 GND 0 FBCD3S T GND 18 E14 6 AGP REO PCIREQ_ VDD 13 C671 C668 Mi 1 FBAD35 1 FBCD36 T_GND_19 JOP FANE 00220 FLX 9660 DU Lond ge 01 FBAD3S GND 2 2 FBCDI7 T GND 20 B18 6 AGP_FRAME AGP IRDY PCIFRAME VDD 15 0608 0603 an En 10 22 i FBAD37 Ata 21 EIZ 6 AGP_IRDY m PCIIRDY VDD 16 25 25 80 20 10V 10V FBAD38 GND 4 1 FBCD39 T GND 22 E18 6 AGP_TRDY AGP DEVSEL ALH PCITRDY_ VDD 17 Ans FBAD39 GND 5 FBCD40 23 RIS 6 AGP_DEVSEL PCIDEVSEL_ VDD 18 FEAD4O 6 FBCD41 2
25. 5 Wu 1 1 1 Li 902 100MNA R275 0805 poen t b 3 1 1894 GND c24 4 4 cma cone R240 _c230 0608 270P 0608 20 R2880 0603 4 1 j Sy 10 EET 1 TEM ae TE POMCIA 1394 Controller amp Socket ize Document vd posamen 411676300001 m Date Thursday June 12 200 nest 17 57 z z z z PDF created with FinePrint pdfFactory trial version http www fineprint com 3 AAA 2 0 31 R203 0805 144720 lt gt C
26. gt MOSFET 1 5 6 SUSB Device Regulator 4 97 v 10 VR PWRGD DC DC PWN 8 MCH PG DC DC PWN 4 Controller Controller MAX1907 MAX1858 9 CLK_ENABLE 7 VCCP 7 12VS 2 PWR_ON DC DC PWN gt Controller Clock MAX1858 at 9 CPU_CORE Provide to DDR_2 5V 12 PcIRSE PCI AGP OE system i 4 i Device CPU NB 12VS LDO MOSFET 4 FEES IE 5 ve 45VS 43VS 12VS REF 1 25 lt N Un 19 8060B N B Maintenance 1 3 2 Power On Suspend Sequence 1 Press LID 2 Select Windows Standby 3 Time Out ICH4M 82801DBM 1 STPCLK High gt Low 2 After CPU Stop Grant Cycle the ICH4M will output CPUSLP High gt Low 60 63 PCICLK 1 3 3 Resume from Power On Suspend Sequence 1 Ring In 2 Press Keyboard Mouse 1 WAKE_UP ICH4M 82801DBM 1 STPCLK 3 CPUSLP 2 PCI Stop Grant gt CPU Banias Process Stop Grant Cycle STPCLK Low gt High SUS STAT Low gt High 10mS PCI AGP Device 3 STPCLK s Co 2 CPUSLP Banias 1 2 3 CPUSLP Low gt High 2 4 PCICLK 4 STPCLK Low gt High 204 237uS Process Stop Grant Cycle 20 8060B N B Maintenance 1 3 4 Suspend To RAM Sequence 1 Press LID Button 2 Select Windows Standby Function 3 Press Internal Keyboard Fn F12 v
27. 0 30 weis nave HOUSING 80608 i HH iis crecen 4 51 6 76300001501 MITAC C jeans sese echnology Corp E E G H SHEET 1 of 1 model nameRNANR file nameRN6NR po MODEL 8060B Contexts Revision R01 PCB PCBA ROA 0 1 ROB 0 2 ROC 0 3 RO1 Title Page Cover Sheet 1 System Block Diagram 2 Power Block Diagram 3 Banias 4 Odem 1 2 5 Odem 2 2 6 Clock Generator Screw holes 7 DDR SO DIMM Socket 2 8 NV34M 1 9 NV34M 2 10 NV34M 3 11 NV34M 4 12 LCD amp CRT Interface 13 ICH4 M 1 2 14 ICH4 M 2 2 15 HDD CDROM Connector amp PULL UP RESISTER 16 PCMCIA 4510 17 LAN RTL8101L MDC 18 Audio Codec amp Amplifier 19 Audio DJ amp MINI PCI 20 BIOS SUPER IO 21 Micro Controller H8 22 LPT amp TV OUT port amp USB port 23 DC POWER 24 SYSTEM POWER 25 VCORE MAX1907 26 5V_CD 1 35VS VCCP 1 2VS 27 CHARGER amp D D CONNECTOR 28 History 29 DRAW DESIGN CHECK ISSUED POWER STATES IDSEL IDSEL CHIP AD11 AD17 MINIPCI AD18 LAN RTL8101L AD19 PCMCIA IEEE1394 STATE Sica VOTAGE so S1 S3 S4 S5
28. 005 CRUS _ Cho vesto e I 6 pore CUR DORE 1 w eS MT EI 2 MAT 12 6 6 0085 21 E 8 CLK DDR2 0516 rsa SCASA 1 T maz 6 1 ir oer 2 9 CUR 2 e bn 3 TRET TRE 3 4 6 SRASA b 6 35 88 6 1 6 4 me 6 851 RPXS Xog 0 BAGIDU our 5 MERAEA MARS 00 ioe MARE MENA BST 12 15 02 7 10 MENA i E a CEST 10 MART 105 559 106 1 16 WDDAO Mas or AS ioa MARE ND RP518 8 109 5 M o 3 14 MDD44 568 mio 5 A 0 NODS RS 6 MD36 6 04 Her Li vos voo27 04 4 5 12 Woo 6 MD32 HH Bat 118 MSRASA 11 6 mwen HZ BAD mass 38 Stat 2 1 057 9 wes HA 121 122 1 16 6 MD44 4 6 cs2 50 css 6 6 cso 51 6 6 Mose ka x32 pue 2124 lt 2 25 no 6 trot 128 vss vssze 328 4 6 MD35 EL vase 128 18 8 ME 0037 Ha MDOS4 181 0010 VDD28 5 33 134 7 10 H 6 MD52 83 0054 134 6 MEUM asino 5188 98888 E n 1 ui 6 Fra Move 88 0035 H40 3 14 EX ES See i TIDDIT 0011 0029 TOUR LEM 145 Dod Doss 146 5 32 EL pass DMs 148
29. 0608 1 susezov 0603 7 poss Poses 20524 2525 1 E 200 2200 oou _ 2200 yu 4 2200 PC4B 7343 7343 0603 7343 PCS28 100P DE Mt 2 2 100 PAT ie 2 50V 2 0508 1210 475K T 12 compa s Ec100s04 LU 8 aa 777 2 2 1 n 2 23 4 E 1 i 3 22 Ws 30 PRES POSES OU 1 i 2 sil oec FEET i 5 20 47 1 16 0470 Ve ne 1 ille tlas ala 7 Pann 18 7 7 8 17 TL posee _ Pose PRESE Si UU 8000 odu 100 1 wee 1 CD 9 16 i 2 11 2 508 0603 1812 5 OK PREST ov BY 120211000 471 PRI 2012 1 E 10 ii HS SPC 10039P 41 2K 20535 PRE38 m 5 30 0603 0 0870 ft 499K 1 FRI oH d 1 18 a 2 12 13 Posi Pos 10 I EOS IS Perel 1500 PC45 PC39 1500 PCS36 100P FS 7243 010 100 FN 743 Pusos MAX1858 63V 0603 1210 63V QSOP24A 50V 777 5 PRIS P2FBI 2 30K s 508 0608 all 1 th MITAC 2 System Block Diagram E iz er 2 Bison Document 411676800001 p Number Date Thursday June 12 2003 Presi 7 o a PDF created with FinePrint pdfFactory trial version http www fineprint com ADINP
30. to tbe GPU 59 T GND 42 U4 aGPSTOP VDD33 8 FBAD59 25 HES 6 T GND HHS VREF VDD33 9 FBAD6O GND 26 S3_ 061 T_GND_44 AGP VREF VDD33 10 1 FBAD61 GND 27 Hit FBCD62 T_GND_45 Fig AGP VDD33 11 tii leid FBADE2 GND 28 PHIL FBCD63 T GND 46 U18 6 AGP_PIPE A 1 AGP BILO AGPDBIHI VDD33 12 See FBADE3 29 20 12 MEMB MA 11 0 47 HIS AGPDBILO VDD33 13 11 mema mapio TA GND_30 FECAO T_GND_48 MCH M integrated pull down 4 5k NvieM Sov TEMO Guo mM 49 BGAGO2_64_35_1MM 32 ian GND oo HA veli 04 5 FBAAZ GND 48 GND FBOAS 52 FEAM GND 35 FBCAS T GND IZ FEAAS GND 36 FBCAG 54 IS FBAAG GND 37 Fig 7 T_GND_55 Wiz FEAA7 GND_38 T GND 56 GND_39 9 Tonn 57 Ma FBAAS 40 T GND 58 FBAAIO GND 41 MIS 1 FEAATI GND 42 2 T GND GND 43 12 MEMB_DOM7 0 MIZ 202 160 11 MEMA DOM7 0 TG GND 4a T GND W18 si FBADOMO GND 45 FBODOMI T GND M FEADOMI GND_46 FBCDOM2 FBADOM2 GND 47 FBCDOMS FEADOMI GND_48 FECDOMA GND 49 FBCDOMS FBADOMS GND 50 FacbaMs E FBADOME GND 51 FEADOM7 GND_52 4 MEMA RAS ES GND 53
31. BROR HREF a 4 HVREF Ens HVREF 4 HBPRI BPRIe 4 nbasv DESYE ASTE HRSpo 2 CPURSTE HCPURST Se LI oi m S BGAS68 25 As close as possible pin a MiTAC 1 2 ap Document Document 41676300001 m Dates Thursday June 12 2003 5 r 1 PDF created with FinePrint pdfFactory trial version http www fineprint com 9 AGP_AD 0 31 lt gt AD 0 31 0 12 Loa AL MA 12 8 G ADD smo GLADI SMM G_AD2 2 ADS SMAS Sum G_ADS SMAS G ADS Smas SMA7 5 G_ADI 5 581 58 72 Y vss 2 vss 73 FB 8017 SUA 553 VSS 74 E14 SMATI 274 G_ADI2 5 12 MDI0 63 384 5875 G_ADIZ E lt gt 63 8 823 vss 5 vss_76 114 G_ADI4 000 gt 33 6 58 77 015 spat 22 557 55 78 016 5002 a E26 VSS8 55 79 G_ADI7 spas 528 vss 9 VSS_80 Y e 55 10 55 81 5004 BN Ali 019 spas G27 55 11 VSS 82 6 AD20 5096 55 12 VSS 83 G AD21 5007 828 58 13 VSS 84 5008 Mee ves 4 VSS ABIT G_AD23 spas S2
32. DDRO BUS ROBO 5 12 MDD 20 6 i 5521 0 31 E 1 16 MDOSAS 7 10 5 8 15025 MDDT 1 E TRO 12 40029 Re moore nazo 42 5 3 WDOSAT 8 iux 4 1 voat wa asti La RP51 16 mag Res 45 007 en Die toes 5 ga MDDIS 4 3 MDDS RPX 6 MDZS 7 10 25 0082 5 12 24 TORI mus pn mm a Ln 4 16 MCBA2 52 VS95 VSS2 Fi 10 MDD23 base NEI 1 Tones ss 2019 0023 moD 2 MDD22 3 14 MCBAT 0024 0028 5g 1 18 MCBAZ 6 3 1 10 Bi 4008 VDD22 mopar MOOSE Pg cer E ip Heer ig a 5 14 Wein 5 MOST 117 MDD3T 3 MCBAO RPXB 030 7 10 MODSO oe Wes eg moan 5 12 mo a mor e moos 6 Moss a Dmm 57 baer li tions CERT WEERT I oe a me 1 16 cas tt 76 WAR RP515 MEM 50 850 Hasa 181 vss7 vss24 MIRATO 8 rem n i d s API tiene 1 base MOEA i 4 ee coe 0 tore v 6 MAT Dn Uses 9007 voD24 82 can 5 12 La _ 6 6 TRI 82 cas HA 5 im 6 MAS pui RESET DU x 2 MA ans cocoons 84 8525 10 MAAS 6
33. DTC144TKA 5VA 5VA E RPSOS _ Mul 5VA Twa BATT_DEAD_ Eo 41 POWERSW 470K 4 SET 8 For H8 3437S Reset leso R26 ai 1206 30K 51230108 RPI8 _ 0603 55 R285 j Kit 21 Ta 1 0608 Er u23 KT aces H ae RESET gg cova 25205 0800 MN RESET Ha RESET 28 cg a 4 1 L TL case BAT R277 1 2 IMP811 BAT ue __ 0603 507143 DATA R292 1 2 S Threshold 4 38V VY WU E 77 RP530 1 T DATA 2 7 05 AAA 1206 wig 30 u25 0608 0603 14 EXTSMI SOR 181 DE 14 17 PWROK A RONTE D 182 14 ICH A20GATE Dm l us amp ies 21 ROMCS Tr 4 hay Ue do i a MCCS 10K 10K 1621 McCS RUN iz cm di HEREIN 0608 0603 14 RCIN 22 D 282 EAD 4 THRM ROB 3 4 He THRNCBATA Py 5 pos 5VS SUSB H8 SUSC WAKE UP 7 14 UP ATO H8 MAKE qH O5H 2084 GND mA susB 1424 DTCIASSKA SUSC 14 SNTACETDSSBA 24 74CRTD3384DBQ 0287 Te 610 Micro Controller 0603 ize Document tov ustom 411676300001 ito Number ale Thursday June 2003 28 PDF created with FinePrint pdfFactory trial version http www fineprint com Place two
34. Homo j 188 verax H4 nii ls 13 HSYNC DACA_HSYNC BUFRST REN as short as possible ROMA14 E LCD 1 2 13 VSYNG DACA VSYNC ROMAIS vieHaDo 100 02 19 E THERMDA 2 10 mil trace 5 Rida 5 2 145 22 100108 13 AKIO DACA_RED THERMDC 0603 2 10KNA 5 DVOVSYNC mud GREEN DACA GREEN JomWepang EX oats Layout Note venon 95 13 BLUE BLUE stero 1510 p 77 W 12mil VIPHCLK v ls ve Law LCD BUE De 5 1 TBCCSDA ENOCLKN 10 1 07101 13 aay AGIO ipu STRAPO 1 SONA ei DVOCLKOUT eps M THMCTL STRAPO Gi 2200P Em Le E DVOCLKOUT DAC G2 ERT 4 1512 DACA STRAP G2 0803 DACAVDD STRAR2 pa VGA_THERMDG DVODO VIPDS i 24 AGI DACA_VDD STRAPS ADMIUSZ ROC DVOD1 VIPDS 1 gs 77 508 pope VIPD7 1608 1 ces mi DVOD4 PD Place 9009 18011 Monet ASS pace sync 00008 VIPCAL GND LI AES DACB_VSYNC DVODE il close 10 10 5 ppm vivono o 48 together DACB RED props Dvoba VIPVDDQ 1 losa 23 TV_CRMA 502 DACB_GRUE A pope ViPVDDO 2 pesto ciale ta dev 23 TV eom 401 pace BLUE O i TBv
35. csi 0024 012 WEME MDS7 Law 2 HEME pes F ou 100 Nos 0025 C1 neve MDS 8665 en Reo Noa 212 ___ 1K 0603 1206 5 0026 GH 1206 10K NCS 0026 0603 50V 10V NCB 0027 Ale MENE 0603 10 0603 NC6 0027 1 Doze MA Em 1 0028 28 Mees ST Nog 88 WEME MDSS Neg paso 0931 Fair oser 1 5 2 MEMB 057 Das 1 7 MEMB QS3 SEIT 5953 R49 0603 bass VSS TH2 0603 VSS TH3 marru ex VSSTH3 VSSTH BAZRFU2 MO x PI VSS TH4 BA2 RFU2 VSS THS VSSITHS VSSITH7 vSSTH7 VSSTHE VSSTHTO VSSTHIO VSSTHI2 vSSTHIS VSSTHIA VSSTHIS VSS TH15 VSS TH16 VGA_MEM2 5 VSSITH16 MEM2 5 9 vss o vss 0 vss 1 0 ce 55 1 vob 8 ves VoD 1 07 4 c ce 1 ves J 4 2 voD 2 Sozu gozu G77 MS VOD S pte vSS 4 vbD 3 210 GARE 100 vss 5 VDD 4 25V 25V 1206 vss 5 VDD 4 25V 25V 1206 vss 6 VDD 5 40 do 108 10 vss 6 00 5 k i 105 y 10 10 VSS_7 VDD 6 Ki A ee 005 ud 20 5 Fito VGA 25 vss 8 10 VGA_MEM2 5 vss 9 9 vss s vssO vona o yea VODA vaso La iaia aa vssa 1 i d J 4 j E VbbO 2 vssQ 2 VDDQ 2 C683 C704 C700 C708 C709 vsso 3 VDDO_3 220P
36. n 45446 16V 10 Pusot Wa HVOFN40 10V J posta posis 270P 0608 10 3 J 4 77 29516 2 PRSIS 2 PRSi4 PRSIS PR511 1K 750 200 200 TT 1K 1 1 1 0603 1 Pes 5 4 PR518 100K 1 savs TR 7 Posie 2 1 5K PRSIO 10 1 10K 0603 PR512 7 14 ste i o MiTAC System Block Diagram iz er stony Document 411676200001 110 Number Date Thursday June 12 2003 Pret 76 o PDF created with FinePrint pdfFactory trial version http www fineprint com PLS DVMAIN 1 2 Pw13 1202 100 2012 J Po2s 100 1210 50V 25 PR E 1 777 47 0805 1 F pt i 02 5 PR527 PL3 5 5 1 2 7 2 Pwis 1
37. 271071301812 271071301011 271071301311 271071303101 271071303101 271071330302 271071331301 129 8060B N B Maintenance 9 Spare Parts List 11 art Number Description 271071475311 RES475K 1 16W 1 0603 SMT 271071473101 RES 47K 1 16W 1 0603 SMT 271071473301 RES47K 1 16W 5 0603 SMT 271071487211 RES 48 7K 1 16W 1 0603 SMT 271071499811 RES 49 9 1 16W 1 0603 SMT R141 R142 R201 R202 R510 R511 271071499211 RES 49 9K 1 16W 1 0603 SMT 27107151210 6W 1 0603 SMT 5 1K 1 16W 1 0603 SMT RES 5 1M 1 8W 5 0805 SMT 1 16W 5 0603 SMT R101 R106 R108 R135 R35 R614 27107156230 6W 5 0603 SMT 27107151030 1 16W 5 0603 SMT 271071513301 RES 51K 1 16W 5 0603 SMT 271071549811 RES 54 9 1 16W 1 0603 SMT 271071560301 8 56 1 16W 5 0603 SMT 271071562811 RES 56 2 1 16W 1 0603 SMT 271071561101 8 8560 1 16W 1 0603 SMT 271071634111 RES 6 34K 1 16W 1 0603 SMT 271071682301 RES 6 8K 1 16W 5 0603 SMT 271071698101 RES 6 98K 1 16W 1 0603 SMT 271071623101 RES62K 1 16W 1 0603 SMT 27107163110 RES 63 4 1 16W 1 0603 SMT 27107168010 RES 68 1 16W 1 0603 SMT at Number 271071698311 _ RESGOBK neos su 271071750502 RESIS 5 nos su n 2 27107151210 271002515302 27107156230 271071822301 RES 8 2K 1 16W 5 0603 SMT R161 R638 271071823102 RES82K 1 16W 196 0603 SMT PR512 271071887211 RES 88 7K 1 16W 1 0603
38. 5 1 PCIRST 1K C571 C576 6565 F8 i 3 68 Lose vss vss 100 Dat 50 50V 610 ves VSS CES NGISSENA 0603 E18 BATS4C vss vss S0170 50V 2 q Ves VSREF VSREF_SUS vss WSS ER 777 0505 E10 vss vss i lion nt mi D cit cias TL cuo vee N88 10 iu 01U Dig vss vss 81 5 Su vss vss Bis vss vss 01 vss VSS D4 vss vss 1 n E vss 1 E i vss PWROK ROC a i i 7 8 SMEDATA 1 60 25 36 99 EN 25 1 7 8 SMBCLK OK eos TN 77 CRT IN p SLP_S5 5 22 ERU esi apioza A BAWSS EXTSML i or v es WAKE UP EY EY SMLINKI pz US an 9 9 a gm eR us cie 1 019 SMBALERT OAUINA 1 nis OK 2 0603 S BATLOW 2 ee E EM 1 ene RESET T ga PCIRST_MSK 2 1 R632 0603 pes PNE E 1 at 803 3 LI LN aiu 227 RAR 1 2 RTC_RST Ri70 WNA _ 0503 POIRST Ci56 ciae 132 795 1 142 ciad 1 C135 m 220 610 610 010 010 GIU 3A 010 n sue 18 ele le le le TS SETE 2 0047 08608 0603 2b2 0603 50V pm 777 777 DFIS 2P 1 25H 777 RTC_VBIAS E R628 1519 SPK OFF SIRO E VHLICH
39. 1 SPKLOUT 2 J502 10K 5VS 3VS 0 R506 502 RI DECT_HP OPT va C206 L C190 5V_AMP A Fiw 2201 7T 2208 p DTCIA4TKA Kl R661 6 R663 R501 L7 3 100K 47K J506 J1 4 7K 600Z 100M 2 5V_CD 1503 Q5 Ri DEVICE_DECT DEVICE WW 5 DTCI4ATKA Kl 110 16 600Z 100M 4 LINE_OUT_L LINE_OUT_L e 3 COLTO Nn 2 14 LINE_OUT_R LINE_OUT_R 19 3 Ls R669 R703 R702 600Z 100M 1 0 IK IK 19 600Z 100M 7 LINE OUT LH 600Z 100M 8 LED SE BTL HP LINE DEVICE DECT Input Output SPDIFOUT 7 Drive v IC Low Low High L RLine BTL 2 High High Low L RHP SE 600Z 100M 4 VOL_UP 6 La J502 VOL_DOWN LINE_IN_L SION 5 g n L8 4 i3 600Z 100M DINER 600Z 100M Y YN 5 16 3 y RI 100K 77 7 5 CD CAGND sws01 R2 x J501 100K VOL_UP MIC_3 6 15 5 ELI MIC_2 2 VOLDN 14 o o e 5 LI 1 600Z 100M 116 600Z 100M SW507 CAGND 115 8060B N B Maintenance 8 12 LAN Test Error An error occurs when a LAN device is installed 1 Check if the driver is installed properly 2 Check if the notebook connect with the LAN properly Check the following parts for cold solder or one of the following parts on the mother board may be defective use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement Board level Troubleshooting Parts
40. 16171820 STOP STOP ADI 1722 PWROK 2 99 AB6 PWROK SMLINKO ET 4 VOCHO vss 17 18 PAR ADO CBE O 3 Aig RSMRST SMILINK PACE vss 0 91748 PERR PERRY na CBE o 3 171820 VCC_RTC 370 ABL R177 0805 Pia VSS Pas cera 0 SER e eus Svenata AE SMe Veera vss M 2 2 AG 15 2 16471820 SERR SERRE 1 m SMBCLK AC SMEALERT vss 171820 Pes pA Place near pin RIO SMGALERTHGPIO 11 EU vss Mi 6 9 17 18 20 21 PCIRST PCIRST H7 DPRSLPVR SPKR SBSPKR 19 6 VCCLAN1_S VCCSUS1_5 vss 7 PCICLK ICH PCICLK 1526 DPRSLPVR _ DPRSLPVR CLKi4 34M ICH 7 VCCLANI SIVCCSUSI 5 vss M 4 6 HOPSLP U23 pPSLPA E12 8 vss 121 BGA360_25_36 cid cid ciu T 488 BGAGEO_25 36 TOUTE 010 7 04 0 18 1 010 Necsus vee ee 1206 0603 0603 0603 0603 Gis 111 Val 50 50 5074 50 Eig 51_5 vss Fia vccsusi s vss 77 VCCSUS1 5 vss VCCSUSI_5 vss 20 ES VSS Fio 7 Tr gt 5 ms vss R624 9 9 9 VSREF SUS vss 10 7532 OR MESH 0603 Riso G21 Supply Voltage Vas 2 0V to 6 04 47KINA Riz2 t 0 vss Fat n 4 4 ES ves us 0603 R196 D27 V_CPU_IO
41. APICCLK APIC Clock This clock operates up to 33 33 MHz APICD 1 0 I OD APIC Data These bi directional open drain signals are used to send and receive data over the APIC bus As inputs the data is valid on the rising edge of APICCLK As outputs new data is driven from the rising edge of the APICCLK Signal Name Type Description USBPOP Universal Serial Bus Port 1 0 Differential These differential USBPON pairs are used to transmit data address command signals for ports 0 USBPIP and 1 These ports can be routed to USB UHCI Controller 1 or the USBPIN USB EHCI Controller NOTE No external resistors are required on these signals The ICH4 integrates 15 k pull downs and provides an output driver impedance of 45 which requires no external series resistor USBP2P VO Universal Serial Bus Port 3 2 Differential These differential USBP2N pairs are used to transmit data address command signals for ports 2 USBP3P and 3 These ports can be routed to USB UHCI Controller 2 or the USBP3N USB EHCI Controller NOTE No external resistors are required on these signals The ICH4 integrates 15 k pull downs and provides an output driver impedance of 45 which requires no external series resistor USBP4P Io Universal Serial Bus Port 5 4 Differential These differential USBPAN pairs are used to transmit data address command signals for ports 4 USBPSP and 5 These ports can be routed to USB UHCI Controller 3 or the USB
42. Request Command must connect appropriate pins of both processor system bus agents They are asserted by the current bus owner to define the currently active transaction type These signals are source synchronous to ADSTB 0 65 8060B N B Maintenance 5 1 Intel Pentium M Processor Signal Name Type Description INIT I INIT Initialization when asserted resets integer registers inside the processor without affecting its internal caches or floating point registers The processor then begins execution at the power on Reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous signal However to ensure recognition of this signal following an Input Output Write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction INIT must connect the appropriate pins of both processor system bus agents If INIT is sampled active on the active to inactive transition of RESET then the processor executes its Built in Self Test BIST Signal Name Type Description LINT 1 0 LINT 1 0 Local APIC Interrupt must connect the appropriate pins of all APIC Bus agents When the APIC is disabled the LINTO signal becomes INTR a maskable interrupt request signal and LINTI becomes NMI a nonmaskable interrupt INTR and NMI are backward compatible
43. This document describes the system hardware engineer specification for 8060B portable notebook computer system The 8060B notebook computer is a new mainstream high performance thin and light notebook in the MiTAC notebook family 1 1 2 System Overview CPU Mobile Intel Banias 1 3 1 7GHz or above L2 Cache Core logic Intel 855PM Odem Intel 82801DMB ICH4 M System BIOS Insyde 512KB Flash EPROM Include System BIOS VGA BIOS Memory OMB Memory onboard Expandable to 1 0GB 200 pin DDR Memory Slot x2 DDR 200 266 specifications USER Upgradeable Discrete 64MB DDR VRAM reserve for 128MB 8060B N B Maintenance Continued to previous page Audio Built in AC97 V2 2 Codec Sound Blaster Pro compatible 3D stereo enhancement Built in mono microphone Built in 22W 3ohm stereo speakers Audio DJ 4 player buttons Play Pause Next Track Previous Track Stop Eject support System Power off play 1 push button and 1 LED for Audio DJ function On Off Push 1 second for turn on toggle for turn off Automatically turn off for CD player idle more than 5 minutes Digital volume Up Down control PCMCIA Type II x1 or Type I x1 CardBus support Non support Zoom Video Audio Function Ports Bi directional Parallel port EPP ECP x 1 USB support USB 1 1 and USB 2 0 port x 3 RJ 11 port x 1 RJ 45 port x 1 DC input x 1 Battery Connector x1 VGA monitor port x 1 Line out SPDIF
44. osos 0508 0603 50V SOV o 50 ol 80 20 FIF TH SERI TH 44 200 6 0280050 10280050 0300080 0300080 0300080 10300080 12 4 12 4 12 12 d 0503 FDSO4 Pe rad 10 rad J 2 10 10 FIDUCIAL MARK _ FIDUCIAL MARK _ FIDUCIALMARK FIDUCIALMARK 777 1394 GND MrGi4 MIgID1 210036 10340060 E D502 FIDUCIAL MARK _ FIDUCIAL MARK _ FIDUCIALMARK FIDUCIALMARK J 4 4 a La 0300080 0300080 0300080 2 2 2 4 12 4 12 4 12 AGND 2 10 rad 10 5 10 MTG27 pe 10300080 10390080 GND 45 y 44 del 0300080 0300080 0300080 4 12 4 12 4 12 ChE rad 10 AAA rad 10 MITAC Clock Generator Screw holes ize Document neh posamen 444676900001 lotto Thursday Jung 12 200 Eher TE PDF created with FinePrint pdfFactory trial version http www fineprint com
45. 0603 SMT 6W 5 0603 SMT 1 16W 5 0603 5 510 1 16W 5 0603 5 510 1 16W 5 0603 5 x zm gt d PRS17 R53 R54 PR30 R276 R303 R537 R643 R37 PR507 PR511 R16 R17 R38 R44 R48 R6 271071154102 RES 15 4K 1 16W 1 0603 SMT 271071154102 RES 15 4K 1 16W 1 0603 SMT 271071151101 150 1 16W 1 0603 SMT 271071154101 RESLSOK 1 16W 1 0603 SMT RES S RES 180K 1 16W 5 0603 SMT 271002102301 RESIK 1 10W 5 0805 9MT 271071102102 RESIK 1 16W 1 0603 SMT 271071102102 RESIK 1 16W 1 0603 SMT 271071105101 RESIM 1 16W 1 0603 SMT 271071105101 RESIM 1 16W 1 0603 SMT 271071105301 RESIM 1 16W 5 0603 5 RES 2 2K 1 16W 1 0603 SMT RES 2 2K 1 16W 5 0603 SMT RES 2 2M 1 16W 5 0603 SMT PR560 PRI0 R187 R188 R23 R48 R51 R521 R5 R42 128 8060B N B Maintenance 9 Spare Parts List 10 art Number Description Location S 271034278301 RES27 12W S 20008MT 1869 271071272101 RES2 7K 1 16W 1 0603 SMT 271071272301 _ RES 2 7K 1 16W 5 0603 SMT 271071201101 1888200 1 16W 1 0603 SMT 271071201301 RES 200 1 16 5 0603 SMT 271071204101 RES 200K 1 16W 1 0603 SMT 271071203101 RES20K 1 16W 1 0603 SMT 271071221302 RES22 1 16W 5 0603 SMT 271071223300 RES22K 1 16W 5 0603 MT R
46. 1 5VS 0805 100 25V 1206 PL503 I 26513 10 50V 0 2 1 003 x 5 J i 0010 PRS10 5 1K 77 4 MMBT3906L e 4 7UH 82K PRA PC520 100P See 1 onm Eus PR502 FB2 1 J 1K PC503 PR511 100K 1 Dre PC509 19 v m 100 0010 1 UMS 2200 820 PC508 1 1206 0603 PR50447 PCSIS 010 1 FB2 lt lt 7343 10V 50 1 4 1 1 i T i av 0603 T PRS0830K 1 osc 4 50V for R02 SCK431LCSK 5 c4 SOT23N 0470 PR3 0 220 PC518 ME DE Hh PR505 0603 De PGND 10K 46V rer nio 0 0 TA Bati 1 BAT54A 0805 Sex GND PGND H8 PC13 T 1 20502 peg 150 Pott PRSU347 PCSIO 010 ji 64 7243 oar 9 16 1 1 0603 0603 T EC sync ww 364 Sw 1 5 DDR 25V rr DI re 1 Da PGND PLS PUS gi 11 14 i 0 0010 PRO 5 1K FRI 77 2 5V 0805 ae 1 i PL502 Rer Ha oa i 1 100P 2504 MAX1858 PL4 VGA_MEM25 QSOP24A 0 3j puso d 127 0805 Ly FBI 5143620 l i 508 PD501 PRIO 15 4K 4 E Ec100504 0608 T poste Pesos 1 1 ME 4 0 010 100 0 010 5 PCI 4 Pelo E ce ace EST T 0603 1210 0603 FB1 4 2200 PC506 PC517 2200 PRS PC521 50V 1
47. 17 1820 SE 28 T apiocux ECT AGP BUSY 9 vss 9 16 PCI INTA 7 PIRQAR 0 GPIO7 B3 SC 1 27 avec VCC3 3 vss PIROB AD30 sci 22 3 vss 17 POLI 02 HSTPCLK VCC3 a VSS 1618 PCL INTD PIROD AD28 4 HSTPCLK rem aio sTPCLK Pio 12 V ERT 22 VCC3 vss 1620 PCI INTE PIRQE GPIO 2 027 HA20M 2 GPIO 13 IN 19 3 vss 16 17 PCLINTF PIROF GPIO 3 026 4 HSLP Malo CPUSLP Yay STP PC ROC 82K vss 1620 PCIINTG PIRQGHGPIO 4 AD26 4 HPWRGD TR CPUPWRGD STP_PCI GPIO 18 STP POI 7 0603 vss 16 PCLINTH PIRQH IGPIO 5 R50 4 HINTR ER INTR SLP_Si GPIO 19 DES tro SUSA 7 vss AD23 56 4 HNMI NMI STP_CPU GPIO 20 STP_CPU 7 26 VCCLANS 3 vss 16 4 REO 4 AD22 p C3 STAT GPIO 21 mix vwd A STOP 8 VCCLAN3 3 VCCSUSS 3 vss PAZ 16 20 REQ 021 4 HIGNNE IGNNE CPUPERF GPIO 22 3 VSS 1618 2 REQ 2 AD20 22 ICH_AZOGATE Sor 22 AZOGATE SSMUNSELIGPIO 23 L TP523 VCCSUS3 3 vss Hac 16 REO REOR 1 019 RINE CLKRUN amp GPIO 24 PA TA PCLKRUN 17 18 2021 VCCSUSS 3 vss 16 17 R
48. 281307085001 IC NC7SZ08P5 2 INPUT amp GATE SC70 284500034002 IC NV34M GPU VGA CTRL BGA701 284500593001 MCH M mFCBGA 593p PWR 284500165001 IC 0Z165 AUDIO DI TQFP 100P 286300965001 IC 0Z965R CCFL CTRL TSSOP16 02 284587393002 IC PC87393F TQFP 100P 284504510001 IC PCI4510GHK PC CARD 1394A CONT 286309701001 IC RT9701 POWER DIST RI SW SOT23 284500810002 IGRTL8101L LAN CONT ROLLER LQFP IC S 812C DECECT OR SOT 89 PRC 1C SC43 1 LCSK 5 5 ADJ REG SOT 2 1C SC43 1 LCSK 5 5 ADJ REG SOT 2 IC SPREAD MODULATING CLOCK GEN I 286100252001 IC TPA0252 AUDIO AMP 2W T SSOP 24 286302211004 IC TPS2211A POWER INTERFACE SW S 273000990117 INDUCT OR 4 7UH CDRH127 MULTI SMT 273000990117 INDUCTOR 4 7UH CDRH127 MULTI SMT 273000990142 INDUCTOR 4 7UH CDRH127B SMT 46503100005 5 ASSY 7521Li INSULATOR B BATT 8060 INSULATOR BATT ASSY L22R9 2 8175 INSULATOR BATT ASSY L91 6W14MID8 INSULATOR BATT ASSY ONE ROUND BL INSULATOR BATT ASSY POLY W30L52 INSULATOR BATT ASSY W13L20 BLAC 286300812002 286300431014 286300431014 284591720001 46673100008 46503400502 46673100025 46503200202 46673100026 4 46613100027 Location S 10 U513 U514 55 gt CA N 5 zd n gt UIS PL24 PL30 PL502 125 8060B N B Maintenance 9 Spare Parts List 7 Part Number sissi fama mao __ Decem fassa T_T
49. 3 Definition amp Location of Connectors Switches 3 1 Main Board Side B 15024 1501 J501 J502 J504 J505 J506 J507 J509 MDC Jump Wire Connector Left Internal Speaker Connector DDR SO DIMM Module Socket Internal Microphone Connector Audio DJ Board Connector Mini PCI Socket Right Internal Speaker Connector 59 8060B N B Maintenance 3 Definition amp Location of Connectors Switches 3 2 Audio DJ Board SW501 SW504 SW506 Side B SW502 SW503 SW505 SWS507 Volume Up Switch STOP EJECT Switch PLAY PAUSE Switch FF Switch RW Switch ADJ Button Volume Down J501 External Microphone Jack J502 Line In Jack J503 Line Out Jack Audio DJ Board Connector 60 8060B N B Maintenance 3 Definition amp Location of Connectors Switches 3 3 DC to DC Board Side A J501 DC to DC Board Connector PUS04 LTC3707 DDR 2 5V DC to DC Converter Side B Inverter Board Connector pu pull SW1 Power Switch SWI PU1 LP2996 REF 1 25V DC to DC Converter 61 8060B N B Maintenance 4 Definition amp Location of Major Components 4 1 Main Board Side A 6 J1 Intel Pentium M Processor J3 Intel 82855GM Memory Controller Hub Odem J8 NVIDIA NV18M VGA Controller J9 RTL8101L LAN Controller J12 Flash ROM BIOS J17 ALC202 Audio COD
50. 56 2 56 2 56 2 56 2 vu TPBIAS e ee R275 css C229 C228 R240 0 ob 270P 270P 1394 XI 2 1 d 1394_GND x6 24 576MHZ 1394_XO e C257 12P 119 8060B N B Maintenance 9 Spare Parts List 1 441999900211 ASSY OPTION 80608 CESSA facar sso Lemos suem cesaroni TS sso wmworwem rumvouy MS em isso SD Lumen par asrormosuset __ S saro Passes ST sommo pezzo ST pene eee oo Emma TT assi pucenemwrem S sam pico name Less mms pmeawrvonaes art Number 272075103403 272075103403 272075103702 272075103401 272075103401 272073223401 272072473402 272072473401 272003683401 272073104703 272075104701 272075104701 272075104703 272075104703 272072104402 272072104402 272072224701 272072334701 272072474501 272072474501 272072474701 272072474701 272002474401 272075102701 272075102701 272075103403 _272075103403 272075108702_ _272075103401 272075103401 _ 272073223401 _272072473402 272072473401 272003683401 _272073104703 ams ams 272075108703 272075104703 27
51. CSDD amp 15 20 CSDREQ 20 20 19 CSDIOR 20 CSDA2 20 T Lom MITAC ize Document 11676300001 wid ustom Number 41167630000 PDF created with FinePrint pdfFactory trial version http www fineprint com eod LAN cos 05V R229 rare Gis eod ik 77 Place clase to_PCI4510 i csrscua 1 CSERH AUDIO 122060 TIK m 0608 TINT 1 t CRE ba s7emiHz 5 veca C
52. FBADO FEvDDO 0 FBCDI GND 78 AGPVDDO 8 FEADI FBVDDO 1 FBCD2 GND 79 PCIADS AGPVDDO 9 FBAD2 FBVDDO 2 GND 80 PCIADIO E FEVDDO FBCD4 GND 1 PCIADI AGPSBAD FBAD4 FEVDDO 4 FBCDS GND 82 CPlAb12 AGPSBAI FBADS FEVDDO 5 FBCDS GND 83 PCIADI3 AGPSBAZ ETT m 6 FEVDDO 6 FBCD7 PCIADIA AGPSBA3 M FBAD7 FBVDDO 7 ROC FBCD8 GND 85 PCIADIS AGPSBA4 FEVDDO FBCD9 PCIADIS AGPSBAS FBADS FEVDDO 9 FBCDIO GND 87 PCIADI7 AGPSBAG FEADIO FBVDDO 10 11 PCIADIE AGPSBAT FEADII FBVDDO 11 FBCDi2 GND 2028 PCIADIS SBAD 7 6 FBADI2 FBVDDQ 12 VAIO FBCDIS GND 90 PCIADZO AGPSBSTBF SBSTB 6 FBADIS FEVDDO 13 014 GND i PCIAD21 AGPSBSTBS AGP SBSTB 6 Wi FBAD14 FBVDDQ_14 FBCD15 PCIAD22 FBADIS FBVDDO 15 FBCDIG PCIAD23 puvpp _ FBADIG FBVDDQ 16 FBCDI7 o Mi2 H PCIAD24 FBADI7 FBVDDO 17 FBCD18 T_GND_1 PCIAD2S AGPCALPD ROC Already modifyed FBADIS FBVDDQ 18 19 4 PCIAD26 AGPCALPU GND 14 y FBAD19 FBVDDO_19 1 FBCD20 3 PGIAD27 Place on solder side under the BGA from 1 35V to 1 3 FBAD20 tare FBCD21 T GND 4 Mt PCIAD28 CC gt FBAD2I FBCAL PD 0 3 FBCD22 5 HET vob o Was 2V NViBSM i 5 FBAD22 FBCAL PU GNO Feces
53. SUSA HIGH LOW LOW LOW LOW SUSB HIGH HIGH LOW LOW LOW SUSC HIGH HIGH HIGH LOW LOW DNHRIN 19V DBATT 12 6 RTC_VCC 3 3V o CPU CORE sev x x x 1 35VS 1 35V X x 1 8VS 1 8V x x DDR_2 5V 2 5 x VGA MEM2 5 2 5V x x 3VS 3 3V x x 3V 3 3V x 5VS 5V x x 5V 5V o x 5VA 5V 12VS 12V x x 12V 12V x 5V_CD 5V 0 O X byADJ BTN 5VAS 5V x 1 5V 1 5 x 1 5VS 1 5 o x x REF 1 25V 1 25V x x VCCP 1 05V x x x 1 2VS 1 2V x x 2 8 5 2 8V 9 x AD21 PCIINT PCIINT CHIP INTA NV18M PRO INTB MINIPCI INTC PCI4510 INTD LAN 181011 INTE MINIPCI INTF 4510 INTG OZ165 INTH PULL HI BUS MASTER REQ GNT CHIP REQO GNTO PCMCIA 4510 REQI GNT1 PULL HI REQ2 GNI2 RTL8101L REQ3 GNT3 MINIPCI REQ4 GNT4 PULL HI OPTION NO LINK ICH3M 1 275 REF 1 257 1 35VS 1 3V5 1 5VS 1 5V CPU CORE BANIAS 1 8VS BANIAS ODEM ICH4 DDR 2 5V DDR 2 5 NV18 M PRO 3V ICHAM LCD RIL8101L PCMCIA CARD CLOCK NV18 M PRO SIO USB PCM MIN IDE ALC200 MODEM H8
54. X501 SW506 SDIOR R611 SDACK D12 Audio DJ Board CDROM RST D14 SIORDY D502 IRQ15 D503 SDREQ PCI_INTG Replace Motherboard M B 107 8060B N B Maintenance 8 8 CD ROM Drive Test Error An error message is shown when reading data from CD ROM drive 5V_CD na Mode PAV_EN ISCDROM PCSYSTEM_OFF 9 47K ISCDROM go EO UE CDPlayer System 1 1 1 vec 9584 5V_CD J3 is R137 56 no CD ROM 1 0 1 29 51 PWR_CTL gt e e Power off 0 x 1 R138 C30 C586 C585 4 Q3 47K 5V_CD 0 1p DTCI44WK 28 PAVEN o 7 77 3VS 0 9 77 R33 R34 R79 R89 10K 4 7K 10K CSDD 0 15 SDD 0 15 gt P20 gt ii 69 71 67 0 2 33 33 34 SDA 0 2 68 70 66 gt 6 gt 64 62 CSCS 1 3 35 36 S SCS 1 3 63 61 gt 0507 5 CSDIOW 25 SDIOW 6 gt lt gt 100 CSDIOR 24 tri SDIOR 99 VO gt 89 CSDACK Pi SDACK 88 gt O U505 23 CCDROM_RST R32 33 BRSTDRV2 5 Controller CDROM_RST 94 CSIORDY 2 o Hub SIORDY 9 e e e 75 CIRQ15 29 8 le IRQ15 e 74 e 13 CSDREQ 2 82801DBM sonia EN dd 4 PCLINTG R611
55. 1 2 reus 2 poset POSSO 15 4K 14 15 552 555 11 52 100 0 10 100 0603 PR561 PC96 PR567 BSTS 156 pi 0 10 150 DC2010 1210 50V 1210 1 10K so 278 25V 0603 25V o 5 Puzz MAXt999 s 25V XR XR 1 050 2 1 PR28 ha PC554 1 2 M 0608 Sov Puzo KT PR554 47 1 J 7 D J Pws i 1 2 PRG 100K BEAD P 08050 10 Poss PCS 1 2 1800 1 1500 TT 7248 odU L503 mes s 0608 BEAD Sov 08050 508 4 H FIT 1 2 PRSSG 5 100P 0608 Sov ES ET E ET E PE 9 E Puso2 E RE PR47 951230105 5 Ter VN our 2 Hes Fiano EN ove E des AMESBOTLEEV sores ADEN 222428 J 50125 21 522 Il peas Pots 0010 10 BAVZOLTI u 0010 TU 0603 0603 E We ay En 4 10V Sov POY 2N7002 50 VE 777 MITAC DC POWER stor Document 411676300001 Number _ Thursday June 12 200 25 sr PDF created with FinePrint pdfFactory trial version http www fineprint com PL502
56. 16 _ciobe to testor 9 55 80 BB ace ze AD ogos 0603 5 Coit n 8 S 182 88 858 8 asnesgosss 58 BOV o BOV al 50V 4 50 capo 885 9999998958 222 4 58 55 99 999 8389989988 56 garg ul AZUNA p Amu NA 888 8888888888 999 88 55 88 222 2 9999999999 89 8555 me xS 2807 3 ADo 31 5 P Si LE gt anjo 31 14 18 20 4 1 55 5 1202 100 SHORT SMT4 S veca 1202100 i c22 com 010 E Place nearta conector _ 9 LI EL du R294 1 1 J 3 3 3 1 0223 como caso cass c27 como 010 010 010 0603 0603 0603 0603 0603 0603 1 SOV aj 50 SOV cg 50 4 SOV af 50V Place near to PCI4510 ai st car c222 care coe coms cos co 3 OU 10008 100 OU 010 040 010 me 1 1208 aus SOZITOONINA T 2 1 50V 10V 50V 50V 50V 50V Te I 1 ds 1 2 ma ma 1 t R2810 0603 Sr Alda IEEE1394 4P TM _ LINKTEK 4 d 4 pod J d T AVR20 0000X mos R257 2 mass Rese R260 gt R261 ostsosdiostioss 562 562 562 562 562 562 562 562 7 3 0502 gos
57. 2 S Pa Place Hear to RTL8101L _ ROB L 4 EE HIGH LOW FET A xc PIN 16 AUDIO CODEC ONMOTHER BD AUDIO CODEC ON DAUGHTER i ROB E 4 4 MDC SCREW HOLE i RIS 4 75 2039 i dala GNDI PARATE SHORT SMT3 Sons FOR EMI 0280050 4028 AS GND2 1 2 Eo Mraz SHORT SMT3 19 0280050 10 J11 77 2501 st vi R226 0805 GND_45 Henne 4 Protector 1 2 1 1 25 1 8 1808A g 75 77 vilrosozozot NOI cup cs 1900 L2 F501 1 C10101 10204 1 2 12021004 R512 0805 2012 mircoSMDC110 ize Document lev Document 441676300001 E Thursday June 12 200 Brest 18 o 5 i PDF created with FinePrint pdfFactory trial version http www fineprint com E 48V CD
58. 274011431408 XTAL 14 318M S0PPM 32PF 7 5 4P S 274011600408 XTAL 16MHZ 16PF 50PPM 8 4 5 2P 2457406 XTAL 24 576MHZ 16PF S0PPM 8 4 5 2500401 XTAL 25MHZ 30PPM 18PF AP SMT 2700401 XTAL 27MHZ 20PPM 16PF 7 5 4P SMT 274013276114 IXTAL 32 768KHZ 10PPM 12 5PF X 3 422613100007 422613100001 332110020111 X2 274 274 274 gt 132 F G H ITEM PART NO DESCRIPTION TYPE REMARK 1 1332673100002 FFCjAUDID 8060 PART 1332673100004 FFC TP MB 8060 1 4 340673100021 COVER ASSY DDR 8060 1 assEMBLY 1 5 340673100002 COVER ASSY MINIPCI 8060 1 6 _ 940673100034 SHIELDING ASSY 1 10 8060 1 ASSEMBLY 7 1340673100036 ASSY CPU 8060 1 ASSEMBLY 8 1340676300001 COVER ASSY 8060B 1 ASSEMBLY 9 _ 340676300000 PLATE ASSY CPU 8060B 1 AssEMBLY 10 340676300003 HOUSING ASSY 8060B 1 ASSEMBLY 11 340676300005 5 ASSY L 2W 8060B 1 ASSEMBLY 12 1340676300006 SPEAKER ASSY R 2W 8060B 1 ASSEMBLY 13 341673100011 SPRING SCREW CPU HEATSINK 8060 4 ASSEMBLY ______ 14 342665500008 CFM SUYIN S STANDOFF 4 15 342673100026 HEATSINK VGA 8060 1 4 e 16 343674900001 HEATSINK NORTH BRIDGE ENI7 a pat Io 55 17 3446723000205 DUMMY CARD PCMCIA MANGUSTA 1 PART 18 1344673100050 CIIVER
59. 97 2 pcs7 L pcs PC79 562 1 505 s 06 pesas PR545 gt 546 gt 540 PC542 eo T 018 lu 0 1u 0 1u 01 T RLZ24B POS T 01 4 7K 4 7K 0 1u 1000P TPC8107 e e e e e e e Tassa 475K PR557 475K PR565 OMS ALWAYS PR551 Po 12 LEARNING E 2N7002 47 7 n Div py gt 43V U18 Pe PC560 PC556 10 PU22 gt 5V 77 77 Micro MAX1999 gt 12V Controller pj ons gt 3VA H8 F3437 soe a gt gt 5VA DVMAIN PI P26 12V gt 12VS 1 501 1 502 PUS01 n PUBL gt PUSO6 PUI2 MAX1907 412V O e 5 12VS SI4800DY SI4800DY PRIMI 1 3 7 3 dell IM 45V amp 45VS 24 0 43VS 47 ED EN 1 4 amp WL Ve SG gt 1 3VS o o SUSB Puo c PUS05 PR539 PR6I PRESSO MAX1858 From U507 ICH4 M PRS40 a T FTN IK oA gt 5V_CD 1M 1000P T EN gt wo 91 8 1 No Power When the power button is pressed nothing happens no fan activity is heard and power indicator is not light up 8060B N B Maintenance DBATT
60. Audio DJ board ize Document ate Wednesday February 26 200 preet To z z z z 1 PDF created with FinePrint pdfFactory trial version http www fineprint com Reference Material Intel Mobile Pentium M Processor Intel 82855 Memory Controller Hub Intel 82801DBM I O Controller Hub 4 Mobile ICH4 M 8060B Hardware Engineering Specification Intel INC Intel INC Intel INC Technology Corp MiTAC SERVICE MANUAL FOR 8060 Sponsoring Editor Jesse Jan Author Sissel Diao Assistant Editor Janne Liu Publisher MITAC International Corp Address 1 R amp D Road 2 Hsinchu Science Based Industrial Hsinchu Taiwan R O C Tel 886 3 5779250 Fax 886 3 5781245 First Edition Jun 2003 E mail Willy Chen mic com tw Web http www mitac com http www mitacservice com
61. HITM vO AGTL Hit Modified Indicates that a caching agent holds a modified version of the requested line and that this agent assumes responsibility for providing the line Also driven in conjunction with HIT to extend the snoop window Signal Name Type Description ADS Address Strobe The system bus owner asserts ADS to indicate AGTL the first of two cycles of a request phase The GMCH can assert this signal for snoop cycles and interrupt messages BNR Block Next Request Used to block the current request bus owner AGTL from issuing a new request This signal is used to dynamically control the CPU bus pipeline depth BPRI Bus Priority Request The GMCH is the Priority Agent on the AGTL system bus It asserts this signal to obtain the ownership of the address bus This signal has priority over symmetric bus requests and will cause the current symmetric owner to stop issuing new transactions unless the HLOCK signal was asserted BREQ0 VO Bus Request 0 The GMCH pulls the processor bus BREQ0 AGTL signal low during CPURST The signal is sampled by the processor on the active to inactive transition of CPURST The minimum setup time for this signal 15 4 BCLKs The minimum hold time is 2 clocks and the maximum hold time is 20 BCLKs BREQO should be tristated after the hold time requirement has been satisfied During regular operation the GMCH will use BREQO as an early indication for PSB Addres
62. atomic i e no Hub Interface snoopable access to System Memory is allowed when HLOCK is asserted by the CPU 68 8060B N B Maintenance 5 2 Intel 82855GM Memory Controller Hub Odem Host Interface Signals Continued DDR SDRAM Interface Signals Continune Signal Name Type Description SWE SSTL_2 Write Enable Used with SCAS and SRAS along with SCS to define the DDR SDRAM commands SWE is asserted during writes to DDR SDRAM SWE may be heavily loaded and requires two clock cycles for setup time to the DDR SDRAMs SDQI71 0 IO SSTL 2 Data Lines These signals are used to interface to the DDR SDRAM data bus NOTE ECC error detection is supported by the SDQ 71 64 signals Signal Name Type Description HREQ 4 0 yo Host Request Command Defines the attributes of the request AGTL HREQ 4 0 are transferred at 2x rate Asserted by the requesting agent during both halves of the Request Phase In the first half the signals define the transaction type to a level of detail that is sufficient to begin a snoop request In the second half the signals carry additional information to define the complete transaction type HTRDY Host Target Ready Indicates that the target of the processor AGTL transaction is able to enter the data transfer phase RS 2 0 Response Status Indicates type of response according to the AGTL following the table RS 2 0 Response type
63. low voltage within the corresponding 16 bit group never exceeds 8 DINV DNIV 3 DNIV 2 Data Bits HD 63 48 HD 47 32 DINV 1 HD 31 16 DINVI 0 HD 15 0 HA 31 0 Io AGTL Host Address Bus HA 31 3 connects to the CPU address bus During processor cycles the HA 31 3 are inputs The GMCH drives HA 31 3 during snoop cycles on behalf of Hub Interface HA 31 3 are transferred at 2x rate Note that the address is inverted on the CPU bus HADSB 1 0 vo AGTL Host Address Strobe HA 31 3 connects to the CPU address bus During CPU cycles the source synchronous strobes are used to transfer HA 31 3 and HREQ 4 0 at the 2x transfer rate Strobe Address Bits HADSTB 0 HA 16 3 HREQ 4 0 HADSTB 1 HA 31 17 DRDY vo AGTL Data Ready Asserted for each cycle that data is transferred HDSTBP 3 0 HDSTBN 3 0 Io AGTL Differential Host Data Strobes The differential source synchronous strobes are used to transfer HD 63 0 and DINV 3 0 at the 4 transfer rate Strobe HDSTBP 3 HDSTBN 3 HDSTBP 2 HDSTBN 2 HDSTBP 1 HDSTBN 1 HD 31 16 DINV 1 HDSTBP 0 HDSTBN 0 HD 15 0 DINV 0 Data Bits HD 63 48 DINV 3 HD 47 32 DINV 2 HIT vO AGTL Hit Indicates that a caching agent holds an unmodified version of the requested line Also driven in conjunction with HITM by the target to extend the snoop window
64. x 1 Mic in x 1 Line in IEEE1394 x 1 FIR SIR x 1 TV Out x 1 7Pin S Video connector NTSC PAL 8060B N B Maintenance 1 2 System Architecture 1 2 2 Function Description 1 2 2 1 CPU Mobile Intel Banias processor with 400MT s BPSB 100MHz Capable of 478 pin Micro FCPGA processor package On die 32KB instruction cache and 32KB write back data cache On die IMB L2 cache Assisted Gunning Transceiver Logic AGTL bus driver technology 1 2 2 2 Core Logic Intel 82855PM Memory Control Hub Support AGP2 0 4X AGP Support 200 and 266 MHz DDR devices Maximum of 1GB of system memory by using 512MB technology devices Hub Interface to ICH4 M Intel ICH4 M I O Controller Hub PCI 2 2 Interface Bus Master IDE controller supports Ultra ATA 100 66 33 8060B N B Maintenance AC 97 2 2 Interface USB 1 1 and USB 2 0 Host Controllers 1 2 2 3 Memory Support 200 266MHZ SO DIMMs DDR Memory expandable to 1024MB 2 SO DIMM DDR slot 64MB 128MB 192MB 320MB 576MB 128MB 256MB 384MB 640MB 256MB 512MB 768MB 512MB 1024MB Table 1 Memory Expansion Capacity 8060B N B Maintenance 1 2 2 4 I O Ports CRT Port Standard VGA compatible port DDCI and DDC2B compliant m sem RED Red analog video output GREEN Green analog video output BLUE Blue analog video output Monitor Sense Monitor Sense Ground Ground Ground Ground 151413
65. 0 25 OZ165 Audio DJ Board 20 CONN_STOPEJECT DI4 STOPEJECT 37 J506 J1 K e SWs02 2 CONN FF lt D502 e FF CNN Pr 8 CONN_STOPEJECT SR 9 49 CONN_RW DI2 RW 34 U18 K e 51 505 s 31 CONN_PLAYPUSE D503 PLAYPUSE 36 10 CONN_FF Pa gt oo SW504 Micro R135 5 6K CONN_STOPEJECT 8 9 CONN_RW Controll 5V_CD e 7er ontroter R106 5 6K CONN FF 10 R101 5 6K CONN RW gt SW503 5 9 CONN_PLAYPUSE 11 H8 F3437 R614 5 6K 5 CONN PLAYPUSE ny e SW506 11 R675 IK ADJ_BTN 4 3 ADJ_BTN e 108 8060B N B Maintenance 8 9 USB Test Error An error occurs when a USB I O device is installed USB Test Error l if the USB device is installed l Including charge board Check the following parts for cold solder or one of the following parts on the mother board may be defective use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement Board level Troubleshooting Ei Parts Signals 0507 45V Replace another good charge board or good USB device Re test Yes af No USBOCO USBOC2 USBP0 USBPO USBP2 USBP2 USBP4 USBP4 Replace Motherboard 109 8060B N B Maintenance 8 9 USB Test Error An error occurs when a USB I O device is install
66. 000 Idle state 001 Retry response 010 Deferred response 011 Reserved not driven by MCH M 100 Hard Failure not driven by MCH M 101 No data response 110 Implicit Write back 111 Normal data response DDR SDRAM Interface Signals SDQS 8 0 IO SSTL 2 Data Strobes Data strobes are used for capturing data During writes SDQS is centered on data During reads SDQS is edge aligned with data The following list matches the data strobe with the data bytes There is an associated data strobe DQS for each data signal DQ and check bit CB group SDQS 7 gt SDQ 63 56 SDQS 6 gt SDQ 55 48 SDQS 5 gt SDQ 47 40 SDQS 4 gt SDQ 39 32 SDQS 3 gt SDQ 31 24 SDQS 2 gt SDQ 23 16 SDQS 1 gt SDQ 15 8 SDQS 0 gt SDQ 7 0 NOTE ECC error detection is supported by the SDQS 8 signal SCKE 3 0 SSTL 2 Clock Enable These pins are used to signal a self refresh or power down command to the DDR SDRAM array when entering system suspend SCKE is also used to dynamically power down inactive DDR SDRAM rows There is one SCKE per DDR SDRAM row These signals can be toggled on every rising SCK edge SMABI 5 4 2 1 SSTL_2 Memory Address Copies These signals are identical to SMA 5 4 2 1 and are used to reduce loading for selective CPC clock per command These copies are not inverted SDM 8 0 SSTL_2 Data Mask When activated during writes the corresponding data g
67. 0029 i NCB Daze A8 MGT ne Daso 8 0030 EE 0031 Dos LAZ VSSITHI pasa ENS vssiTHi OSA 057 VSS TH2 46 0603 VSSTH2 PBST 0603 VSS TH3 KB VSS TH3 Mereu VSS TH4 BAgRFU2 8 VSS TH4 BA2 RFU2 lt VSSITHS vSSITHS VSSITHE VSSITH vss VSSITH7 VSSITHIO vSSTHII VSSTHII 2 VSSITHT2 VSSITHIA VSSITHTA VSSITHIA VSSITHIS VSSITHIS VSSITHIG 25 VSSTH16 Mewes vss vss 1 o G amp vss 1 0 vss 1 SZ od VDD 1 mm P vss 3 vDD 2 4 cm ce 55 3 2 d cem 55 4 D 0 95220 582 VSSa 010 Siu I yss Voo T o T is ves 00 56 A VSS 6 vo s ri ov 1886 0 5 s av 107 557 VDD 6 7 VDD 6 VS8 8 _7 10 VGA _MEM2 5 vss 7 10 VGA_MEM2 5 vss 9 x 79 vss 9 vssa o voDa 0 550 0 0 visa 8092 esse ose 7 4 ysa 1 7 csse 1 gt vba 2 o ce cos 0595 E x 0587 cse css vssa 3 voDa 3 47008 47008 220P Een vssa 3 VDDQ 3 220P 220P 47002 47008 010 55074 4 0603 0603 0603 4 vssQ 4 VDDO 4 9608 0603 0603 0603 0603 VSSO_5 5 10 10 50V vssa 5 5 Ld 10 50V D E vssa 0007 Place i 7 ace memo i x E ace in memory secti 88
68. 1 0 YO Address strobes are used to latch A 31 3 and REQ 4 0 on their rising and falling edges Strobes are associated with signals as shown below Signals Associated Strobe REQ 4 0 A 16 3 ADSTB 0 A 31 17 ADSTB 1 BCLK 1 0 The differential pair BCLK Bus Clock determines the system bus frequency All processor system bus agents must receive these signals to drive their outputs and latch their inputs BNR vO BNR Block Next Request is used to assert a bus stall by any bus agent that is unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions BPM 2 0 BPM 3 BPM 3 0 Breakpoint Monitor are breakpoint and performance monitor signals They are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance BPM 3 0 should connect the appropriate pins of all Intel Pentium M processor system bus agents This includes debug D 63 0 D 63 0 Data are data signals These signals provide a 64 bit data path between the processor system bus agents and must connect the appropriate pins on both agents The data driver asserts DRDY to indicate a valid data transfer D 63 0 are quad pumped signals and will thus be driven four times in a common clock period D 63 0 are latched off the falling edge of both DSTBP 3 0 and DST
69. 2 1 to 2 2 6 Disassembly 2 Remove the mother board ASSY See the step 1 to 7of section 2 2 1 Disassembly 3 Remove two screws fastening the audio board and release the cable Figure 2 30 2 31 Figure 2 30 Remove the audio board Figure 2 31 Disconnect the cable Reassembly 1 Reconnect the cables to the audio board 2 Replace the audio board and secure with two screws 3 Assemble the notebook See previous sections Reassembly 54 8060B N B Maintenance 2 2 15 Touch Pad Board Disassembly 1 Remove the battery pack keyboard HDD module CD DVD ROM drive and LCD assembly See sections 2 2 1 to 2 2 6 Disassembly 2 Remove the mother board ASSY See the step 1 to 7of section 2 2 1 Disassembly 3 Remove the audio board See section 2 2 13 Disassembly 4 Remove the three screws to lift up the touch pad board Figure 2 32 5 Disconnect the TP amp MB and the touch pad cables Figure 2 33 Figure 2 32 Remove the touch pad board Figure 2 33 Disconnect two cables Reassembly 1 Reconnect the TP amp MB and the touch pad cables to the board 2 Replace the touch pad board and secure with three screws 3 Assemble the notebook See previous sections Reassembly 8060B N B Maintenance 2 2 16 Touch Pad Module Disassembly 1 Remove the battery pack keyboard HDD module CD DVD ROM drive and LCD assembly See sections 2 2 1 to 2 2 6 Disassembly 2 Remove the mother board ASSY See the st
70. 5 4 a sso provetti E ansniosor 11658160554 271611103301 RP 10K 4 8P 1 16W 5 0612 SMT eares 82 06125 n c x 2 1271601820502 206 sso 271071475311 271071473101 271071473301 271071487211 271071499211 271071512101 271071512101 271002515302_ 271071562301 271071562301 271071510301 271071513301 27107156981 _271071560301_ 27107156281 271071682301 271071698101 271071623101 271071631101 271071680101 271071681101 _271071681301 130 8060B N B Maintenance 9 Spare Parts List 12 370 0 0 0 0 0 7 7 7 7 7 3 370102020301 SPC SCREW M2L3 NIW K HEAD 370102020301 SPC SCREW M2L3 NIW K HEAD Description SPC SCREW M2LA K HD NIB SPC SCREW M2LA NIW K HD NYLOK SPC SCREW M3LA NIW K HD T0 3 SPEAKER ASSY L 2W 8060B SPEAKER ASSY R 2W 8060B SPONGE DDB SWITCH 8060B SPONGE KB L COVER 8060 SPONGE KB R COVER 8060 4 4 4 4 SPONGE T HERMAL MB CPU 8060B 4 4 4 4 Location S 3 3 SPONGE T HERMAL MB HDD 8060B SPONGE3 THERMAL MB 8060 SPRING SCREW CPU HEATSINK 8060 STAND OFF M2L8 3 CASHI 8060 STAND OFF MDC 8060 337040100005 SW PUSI BUTTON SPST LAROMA RAT SW PUSH BUTTON SPST 4P 1
71. 78 07 E PDF created with FinePrint pdfFactory trial version http www fineprint com WIRE LED BLADJ LED INDICATOR 5V 95 LED DATA 9 5 8 9 9 d LED CLK H8 RESET RIO R9 RI CDROMACTP CDROM HDD NUM CAP SCROLL 470 470 470 470 HBDACTP 0603 0608 0603 0603 POWERSW VAS SCROLL CL 190G ofi E DDR 2 5V CL 190G 05 ni x VGA 25 bj REF 125V 315 5 1 1906 DIO ve 4 15 2 2 54 5 PINREX 4 4 4 R502 PS1850 215GN185 Some TUNA Soa 1 POWERBTNLED2 97 47 777 9 470 58 0603 R501 1 cDROMACTP
72. 84 8060B N B Maintenance 7 2 Error Codes Following is a list of error codes in sequent display on the PIO debug board m 85 8060B N B Maintenance 7 2 Error Codes Following is a list of error codes in sequent display on the PIO debug board 8060B N B Maintenance 7 3 Maintenance Diagnostics 7 3 1 Diagnostic Tool for PIO Port P N 411904800001 Description PWA PWA 378 Port Debug BD Note Order it from MIC TSSC P N 411906900001 Description PWA PWA 378 Port Debug BD Note Order it from MIC TSSC 87 8060B N B Maintenance 8 Trouble Shooting D D D D D D D LU 8 1 No Power 8 2 No Display 8 3 VGA Controller Failure LCD No Display 8 4 External Monitor No Display 8 5 Memory Test Error 8 6 Keyboard K B Touch Pad T P Test Error 8 7 Hard Driver Test Error 8 8 CD ROM Driver Test Error 8 9 PIO Port Test Error 8 10 USB Port Test Error 8 11 Audio Failure 8 12 LAN Test Error 8 13 PC Card Socket and IEEE1394 Failure 88 8060B N B Maintenance 8 1 No Power When the power button is pressed nothing happens no fan activity is heard and power indicator is not light up Is the notebook connected power either AC adapto or battery Try another known good battery or AC adapter No Connect adaptor Check following parts and signals Parts Signals J23 ADINP ALWAYS Where from Board level PL28 DVM
73. CIA CARD PCI AUDIO AMP ROM 01 1 0 PDF created with FinePrint pdfFactory trial version http www fineprint com 8060B System Block Diagram RJ45 RTL8101L PQFP 100 Control IR Module HP 3602 PC87393F Super I O TQFP 100PIN S 9 Parallel Port Flash ROM 512KB PLCC 32 USB2 Controller 1 TPA0252 Amplifier M D C 30 pin Intel 82801DBM PD 0 15 5 Control ICH4 M BGA 421 AGI Realtek ALC202 o SD 0 15 16 Audio Codec pc 9 48 m 8 Be 38 RS 5 86 m 5 m H8 3437S Keyboard Controller PQFP 100 FAN1 For CPU FAN2 For CPU Cover Switch Internal Keyboard External Keyboard Touch PAD Banais Clock C P U Generator Micro FCPGA 478 pin ADM1032 1CS950810 Thermal Sensor Power Switch 9 3 Socket SSOP 16 5 o CRT NVIDIA 200 Pin DDR SO DIMM Socket 2 D SUB 15 NV34M Odem PCI 4510 VGA AGP BUS 4 MD 0 63 o P ONTROLLER gt i Vedio ME 3 BGAG02 pin l UBGA 209 TFT LCD LVDS DATA Micro FCBGA 593 Pin o 15 2 o d PCI BUS 13 HUB LINK MINI 5 d s 3 USBO External PCI wireless 8 amp Jj Line in 9 4 8 USBI E 3 External Microphone Internal Microphone Internal Speaker SPDIF JACK RJ 11 JACK PDF created with FinePrint pdfFacto
74. Dec mes espe Mp pep mo e o DTT e e CT eme es T_T _ GPIO11 SMBALERT SMB_ALERT 3 3V_ICH o d IET ok e mw T_T CS E GPIO12 EXTSMI 3 3V_ICH za 8060B N B Maintenance Continued to the previous table Pin Name Signal Name Power Type Original During Immediately S1 53 S4 S5 Description Plane Plan Type PCIRST after e PCIRST T_T TO ssa eem To Emm LL enon ans fo fe GPIO34 3 3VS High High High Off Off ENABKL MS K p usi CE TT me om on oe oe oe en GPIO36 CDROM RST 3 3VS GPIO37 SPK_OFF 3 3VS GPIO38 N 3 3VS CT T_T TTT pretese E ES GPIO40 3 3VS 765 1 anoa aws o _____ vettogiemen 2 eo GPIO42 3 3VS YO YO VO VO YO YO YO Uo Uo VO YO Lo Uo GPIO43 3 3VS GPIO 44 47 8060B N B Maintenance 1 3 8 Keyboard Controller Pin Define ee poe CC E meee xem emi KORS 0 memi Es ne come cose H8_SMI EJ ICH3M Connect to chipset ICH3M to system management interrupt Non ACPI mode E m pem pese Es e e seo re re o mo eee re m 0 m emm tnis re
75. HI_STB HI_STBS mius Sies US ig i GPIOTO I MAIN POWER WELL PCI ey USC D cm Te er 4 Ried ls WAIN POWER WELL PEI_REOE mE id oces FIRE win GPIOIZI I MAIN POWER WELL Men MS a er I GPIG 3 T_T WAN POWER WELL H cat en t d SEIS I WAIN POWER WELL PCT_INTS 420 GDROM AST PROFF GPIO 38 LANTXDO i 5 T HAIN POWER WELL _ ta rd 1o Tress NOT implemented AGP BUSY tar SEIS MAIN POWER WELL x ES one pin one 0 01uF as as close GPIO S RESUME POWER SCI gt 8800008 otas SE EE pese STOTT T RESUME POWER WELI EMEALERT a E ANO 26 cemc ABIES im E E GPIOTIZ I RESUME POWER WELL EXTSMI than 500 miie I MET 1 I RESUME POWER WELI L USEREIAS reson Ln 18 1820 ISTE E i E AGSDIN 818 1820 O MAIN WELL x as close pin as zm JL Implemented STOR PCI V gestire TORAS 0 STRAPPING 91 5 NOT Implemented SUSA di B 1 GPIO 20 NOT Implemented STOP CPU FH Integrate
76. IEEE1394 Failure An error occurs when a PC card device or 1394 device is installed 0507 Hub ICH4 M 82801DBM PCICLK_CARD From U506 Clock Generator CBE 0 3 FRAME IRDY TRDY DEVSEL STOP PERR SERR PME PCLKRUN PAR SUSB PCIRST PCILGNTO VvvvvvVVVVVVV Y PCI INTF PCI INTC AD 0 31 A R276 ADI9 100 U22 PCMCIA IEEE1394 Controller PCI4510GHK IDSEL 3V 9 12 0 4 9 45V J16 3 VCCENI all 1 34 gt o VCCDi VCCA VPPA VCCENO 1 svAB 2 Y 3 vcro 1015 um VPPENO 15 5 e e VDDPO VPPENI ii TPS2211 Avr 10 e VDDPI C237 czs 239 C240 C218 2 T Olp 0 1 e o o ee 77 a CAD 0 31 CCBE 0 3 CIRDY CTRDY CDEVSEL CPERR CSERR 2 CSTOP CREQ CGNT CINT CRST CBLOCK CAUDIO CCLKRUN CCD 1 2 CCLK CPAR CVS 1 2 CSTCHG R2_D2 R2_D14 R2_A16 R288 Alc R281 T TPB R294 1 f les TPB R289 e 2 RS R258 R259 260 R261 GNDI2
77. NL TRENTA ai Sav 19 UNE INC 15 0603 9 MC 3 Mic 19 2 x Feit wane E f 11 PCSYSTEM OFF DN Riot 4 FF 106 4 DONN STOPEJECT 0503 DIO CONT CDPlayer system off 1 1 i ian Bru E juni v 1 22 VOL DN SOLL DN 5 Direct system on x x rs 22 ADJ BIN lt P is pass through system on x x sve 1 ROM ACES no CD 1 S wn HDRMA24 Power off x MITAC Audio DJ amp Audio con MET 411676800001 Number Thursday June 200 Pret 0 or 2E 1 PDF created with FinePrint pdfFactory trial version http www fineprint com ET 1202 100M_DFS 4 1608 1 TOUCH 4 2202100 1608 TOUCH 2 22 T_DATA 113 120271 00M_DFS 1608 TOUCH BIOS ROM 22 i TOUCH GRD A SAI ea AGES 85202006 13 DT pjo 1 1 502 1501 cui 71 DI 1702 47 AT
78. O Print Acknowledge J gt 2 2 1 1 1 1 1 SLCT AUTOFDXT Auto Line Feed Printer Error A e 1 A H E ERROR NIT Reset Printer DUN N Printer Busy Paper Out 1 a 4 2 Ground Figure 6 Parallel Port Connector Z Ground Z Ground Z Ground Ground Z Ground Z Ground 0999989889 Z Ground Z Ground Ground Table 9 Parallel Port 8060B N B Maintenance 1 2 2 5 PC Card Slot One Type IVI slot supporting the 1997 PC Card standard and including full R2 16 bit and 32 bit Cardbus data transfer TI PCI4510 PCMCIA Controller amp TI TPS2211A Power Switch 1 2 2 6 Graphical Subsystem x 2 x nVIDIA NV34M graphical controller AGP4X including power management pins 256 bit 3D and 2D graphics accelerator Dual channel LVDS TV out support for NTSC and PAL Microsoft DirectX and OpenGL Optimizations and support 1 2 2 7 Display 15 2 TFT display 15 10 wide screen Resolution 1280x854 WXGA External Video refresh rate of up to 100Hz supported Vertical refresh frequencies to meet VESA requirements Simultaneous video in specified video modes switchable with hot key 8060B N B Maintenance 1 2 2 8 IDE Interface Support Dual Independent IDE Channels One is Hard Disk The other one is
79. PLL B Core VCC Power Power supply for the core VSS Power Ground supply for the chip 73 8060B N B Maintenance 5 3 Intel 82801DBM I O Controller Hub 4 Mobile ICH4 M Firmware Hub Interface Signals Hub Interface Signals Signal Name Type Description HI 11 0 YO Hub Interface Signals HI_STB HI_STBS IO Hub Interface Strobe Hub Interface Strobe Second One of two differential strobe signals used to transmit and receive data through the hub interface Hub Interface 1 5 mode this signal is not differential and is the second of the two strobe signals HI_STB IO Hub Interface Strobe Complement Hub Interface Strobe First HI STBF One of two differential strobe signals used to transmit and receive data through the hub interface Hub Interface 1 5 mode this signal is not differential and is the first of the two strobe signals HICOMP VO Hub Interface Compensation Used for hub interface buffer compensation HI VSWING I Hub Interface Voltage Swing Analog input used to control the voltage swing and impedance strength of hub interface pins LAN Connect Interface Signals Signal Name Type Description LAN CLK I LAN IF Clock Driven by the LAN Connect component Frequency range is 5 MHz to 50 MHz LAN RXD 2 0 I Received Data The LAN Connect component uses these signals to transfer data and control information to the integrated LAN Controlle
80. SERIRO 1 19 SERIRO PEMDATA AL BUSY 23 10 1 1 swiniaPiogs BUSY_WAITE MTR14 49 29 ACKEDRIA 7 SIO 14 smg p SOn ______ 20 CLKIN SLIN amp _ASTRB STEP SN P SLIN 23 FOR EXTERNAL SERIAL PORT DEBUGGER USE deo xL AFD _OSTRBWDENSEL 83 P ARD 23 IS HDSEL STB _WRITE P STB 23 fi Des nm usos 25 55 COMIDCD 10KNA Eme DODHE COMIDSR osos 0603 T EL WDATA sni 3 E COMTATS COMITXD 3 LA IL ons souriixenro S Lp 5 20 phos 0 on AI umos LL 11 221 Rie 22381 pense Fasi E 315 SLI pnATEOIRSL2 sao IRRX 23 SAT 351 IG IRSE FIRSEL ej FEC EROINA 38 XAZIGPIO22 IRSLa PWUREG 86 XAS GPIO2I 300 7 22 iz enr LL XA4 GPIO2A XSTBOR i EE VASNSTBIANCNF2 XDO GPIOO0IJOYABTN1 3 S Alpo x 1622 87 XAEIGPIOZEIPRIQAXST82 xDI GPIOOTLIOYBBTNI 2 Te DI 4j aq e 1622 18012 XAT GPIO27 PIROB Xp2 GPIOG2UOYAY H te 02 028 Xowarlosopinoc XosGPloosoYoY 198 ES alo asf M oR XASIGPIOS1 MTRI PIROD XD4 GP 004 JOYBX 2 Be 5 Sios X 1622 2 58 XA0IGPIOS2MIORD MDAX XD5IGPIOOS JOVAX 38 E m ips as HS Dar 1622 XA11 GPIOS4XIOWR MDTX XDSG
81. SERIRO 21 iE DEVSEL 14 17 18 20 x PERR 14417 18 4 t 7 LOCK LOCK 14 E SERR 14171820 BAKE 1206 Rp528 POLINTH Le n 21 1 9 14 20 x PCLINTG 14 20 at 7 POLINTE HPCLINTD 14 18 x PCLINTG 14 17 BARE 1206 ISA BUS PULL UP DOWN 38 o 21 22 IRQ12 21 MEMR 005 MCCS 2122 MENR 2122 2722 PIORDY ENHANCED IDE 15 PDD 0 7 15 15 PDIOW 15 PDIOR 15 PIORDY 15 PDACK 15 18014 15 PDA 15 PDAO 28 HDDACTP 20 CSDD 0 7 20 CSDIOW 20 CSIORDY 20 CIRO15 20 20 CSDAO 20 CSCS1 28 CDROMACTP 20 cscs3 PDDI0 7 7 Primary EIDE Connector 1 R595 0603 2 22 SUYIN 20038A 44G2 021 Ds 100504 151 1 2 SHORT SMT4 c29 Close to IDE 0603 0603 1206 Connector 50V 50V 16V BRSTDRV2 45V_CD 45V CD R34 47k 0603 CSDIOW Secondary EIDE Connector CABLE SEL SUYIN 80091AR 050G1T B 2 PDDIS 15 2008 15 i5 PDA 15 15 Pesi 15 HDD_RST 15 R32 0603 W S 16 12 12 16 mils CDROM COMM 53008 15 CCDROM_RST COMM CDROMLEFT 19 CDROM RIGHT 19
82. Signals 3V PCI GNT2 3 LAN PCI REQ2 AVDD LAN PCI INTD PCICLK LAN TXD AD 0 31 TXD CBE 0 3 RXIN FRAME RXIN IRDY TRDY DEVSEL STOP PERR SERR PME PCLKRUN PCIRST Correct it Check if BIOS setup is ok Replace Motherboard Re test Correct it 8060B N B Maintenance 8 12 LAN Test Error An error occurs when a LAN device is installed 3V_LAN AVDD_LAN Di 120Z 100M WY 59 70 75 R640 TA 0 From U506 Clock Generator ae D gt CBE 0 3 4 gt FRAME 18 Pu gt IRDY 19 4 gt P TRDY 20 gt 2 DEVSEL 2 0507 STOP M PERR 255 Io P SERR 26 Controller TUE PCLKRUN Hub 4 EN PCIRST RI84 0 81 ICH4 M PCI_GNT2 82 PCI REQ2 855 828010 PCLINTD 80 AD 0 31 4 gt R643 ADIS Es LN VDDIO 5 AVDDJ0 2 Controller RTL8101L IDSEL 3V 3V 3V gt 3V_LAN 3 AVDD_LAN R652 5 6K 55 1 8 cs vee 3V 3V_LAN 1s LAN 54 2 120Z 100M 1207 100 0508 7 4 U i 3 sei 9346 52 4 po GND 1 C189 0 1 R202 R201 49 9 49 9 R701 6 TXD 0 1 4 Pi
83. Sleep state and transition to the Deep Sleep state 66 8060B N B Maintenance 5 1 Intel Pentium M Processor Signal Name Type Description Signal Name Type Description SMI I SMI System Management Interrupt is asserted asynchronously by system logic On accepting a System Management Interrupt the processor saves the current state and enter System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler If SMI is asserted during the deassertion of RESET the processor will tristate its outputs Processor core power supply VCCA 3 0 VCCA provides isolated power for the internal processor core PLL s VCCP Processor I O Power Supply 0 Quiet power supply for die COMP circuitry These pins should be connected to VCCP on the motherboard However these connections should enable addition of decoupling on the VCCQ lines if necessary STPCLK I STPCLK Stop Clock when asserted causes the processor to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals to all processor core units except the system bus and APIC units The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is deasserted the processor restarts its intern
84. a2 0608 JODROM LEFT 16 19 1U 10V 0603 p247 1 CD GND 1 TAK a 20808 SONM JCDROM COMM 16 e veio C236 1 10 10V POLBEEP 1 C833 1 10 10V 0603 R237 R251 R246 AVDDAD C235 10 10V 0603 100K 100K 100K 2 aux H4 1 0603 0603 0603 0603 10 10 24 1 T A 1U 10V 0603 0603 10V 1U 4 C823 FLTaD LINE OUTIL Lou si 15 mils AGND GND AGNO AGNO 0603 286 AR as short as possible 50V 5 40736 7060377 3 ME 1 M rro PHONE C243 10 10V 0603 cast 1U 10V ig 40 OUT 3 MONO OUT MONO_OUT 18 ine a cms 2 1000 sov ons NC3 ALT LINE OUT L 1 3 AVODAD 4 ibis Meca p ld cesa 1 2 1000P sov 0803 Mis ROB SPDIFOUT 48 ED CUT meu C826 1 2 1000P sov 0603 INTERNAL MICROPHONE F 4 1508 T C261 l4 80 C825 1 2 1000P sov 0602 516302 4 Line Out NoAmp T 58 58 REFFLT 20mil C260 20 SPDIFOUT 22 3 28 Head Phone With Amp l MA 1 25MM H1 8 55 22 VREFOUT FLS2P HF U21 0603 777 ALC202 caes 4 71 ks 14 saspKR gt SBSPKR_ 0603 POFP4S_0 5MM xi 6362 6305 1000 97 Q7 0603 R27850V 0603 0603 0603 AND 7 17 CARDSPK MMBT3904L HOA 0603 50V 50V 30V AGND amon ICH4 has Int
85. device is interfaced to the DVO port Note Bit 7 needs to be strapped low when an on board DVO device is present The other pins should be left as NC DVODETECT I DVODETECT This strapping signal indicates to the GMCH DVO whether DVO device is present not When a DVO device is connected then DVODETECT 0 8060B N B Maintenance 5 2 Intel 82855GM Memory Controller Hub Odem Analog CRT Display Signals GPIO Signals Continue Signal Name Type Description VSYNC CRT Vertical Synchronization This signal is used as the vertical CMOS _ sync signal HSYNC CRT Horizontal Synchronization This signal is used as the CMOS _ horizontal sync signal RED Red Analog Video Output This signal is CRT Analog video Analog from the internal color palette DAC The DAC is designed for a 37 5 ohm equivalent load on each pin e g 75 ohm resistor on the board in parallel with the 75 ohm CRT load RED Red Analog Output Tied to ground Analog GREEN Green Analog Video Output This signal is CRT analog video Analog from the internal color palette DAC The DAC is designed for a 37 5 ohm equivalent load on each pin e g 75 ohm resistor on the board in parallel with the 75 ohm CRT load GREEN Green Analog Output Tied to ground Analog BLUE Blue Analog Video Output Th
86. emma awe sranmuanccommox Lema ST Faron fans ST aio famosa ca O aan fame Sl semen sommes asus www fama amine ST amc __ 441673100031 LCD ASSY AU WXGA 15 2 8060 451673100051 _ LCD ME 8060 ee Fi Lumens ficos osa 346673100023 INSULATOR FOR 4 CELLS 8060 346503200003 INSULATOR FOR 5 CELLS GRAMPUS 346673100047 INSULATOR INVERTER 8060 ori in E Li 71 _________ Oo osrs100077fINsuLATORKBL Downso 346673100074 _ INSULATORKBL SIDE8060 RIDE _________ _ _ ____ NENNEN 346673100076 INSULATOR KB R DOWN 8060 346673100073 INSULATOR KB R SIDE 8060 346673100075 INSULATOR KB UP 8060 KBD ASSY UI 8060 orzo sos __ sem passio naso ST Pern Perrone fascette 346676300009 INSULATOR KB COVER 8060B 126 art Number 294011200161 294011200069 294011200070 416267630901 416267630001 526267630015 346673100084 242676300002 375102010002 461504100001 461673100003 224670830002 221673150001 221503250001 221600050113 221673150004 221503250002 4 4 3 3 3 3 8060B N B Maintenance 9
87. fuses on same location 21 ERR 21 1 1 21 PINT 21 P_LPD2 21 P SUN 21 P_LPD3 21 P_LPD4 21 P LPDS 21 P_LPD6 21 P_LPD7 21 P_ACK 21 P_BUSY 21 P_PE SLOT power Trace50 60 mil 1 UST 1 3 1 vino vouro 2 RT9701 CBL SOT25 USB VOUTO VOUT1 pin is power source from IC to connect on 500mA Trace 40 only use one fuse EM 1 7 2012 ww ZE ZL NE cl sov GND 102 Bavsona Bavsona BAVSSNA 1505 120Z 100M 1608 i S VIDEO 4 TV_COMP JTv_cOMP 10 i place C573 0603 sov 2 2 1504 12024100M 1808 i 1 3 TV LUMA 10 5 1 2 TVLORMA TV CRMA 10 1506 120Z 100M 1608 Close to S VIDEO 1 dala NE css C574 css C597 0603 50 1008 100 1206 i DINTEIST 270P 270P 270P 0603 e SUVIN 0603 0603 0603 10 of 10 sisi 10 1
88. iei Gpl ia cana 83 T2 Error CdS PETI Ed Utd Uds 84 7 3 Maintenance Diagnostics c 87 8 Trouble Shooting 88 Bi No cora i ila ali 89 8 2 INO Display et 94 8 3 VGA Controller Failure LCD No Display I I ee re hr rre rrr 97 8 4 External Monitor No Display toes b Ox boa eeu ERI 99 5 5 Memory Test ETTOT ioo Uo Gr ERI IE BS pA RAE IER AGO See 101 8 6 Keyboard K B Touch Pad T P Test Error 103 8 7 Hard Driver Test Error siii EE Lata aoa cac E pens ili co li ie 105 8 8 CD ROM Driver Test Error lina 107 8 9 PIO Port Test eb ne ee xp vectes Coe pel 109 8 10 USB Port Test EETOE oe TRAZIONE TCR CRY 111 OLD Addio ARRE RIENZO ASIA III 113 012 LAN enn ei evi iex dau e RR IR Aaa 116 8 13 Card Socket Failure oen eret ene ________ ______ 118 8060B N B Maintenance Contents 9 Spare Parts Lists alal 120 10 System Exploded Views wedi coREP er eritrea 133 1i Circuit Diagram iss lella 134 12 Reference Material 164 8060B N B Maintenance 1 Hardware Engineering Specification 1 1 Introduction 1 1 1 General Description
89. internal pull up resistor CLKRUN VO PCI Clock Run Used to support PCI Clock Run protocol Connects to PCI devices that need to request clock re start or prevention of clock stopping NOTE An external pull up to the core power plane is required REQIA I PC PCI DMA Request A B This request serializes ISA like GPIO 0 DMA Requests for the purpose of running ISA compatible DMA REQ B cycles over the PCI bus This is used by devices such as PCI based REQ S Super I O or audio codecs which need to perform legacy 8237 DMA GPIO 1 but have no ISA bus When not used for PC PCI requests these signals can be used as General Purpose Inputs REQ B can instead be used as the 6th PCI bus request GNT A PC PCI DMA Acknowledges A B This grant serializes an GPIO 16 ISA like DACKZ for the purpose of running DMA ISA Master GNT B cycles over the PCI bus This is used by devices such as PCI based GNT 5 Super IO or audio codecs which need to perform legacy 8237 DMA GPIO 17 but have no ISA bus When not used for PC PCI these signals can be used as General Purpose Outputs GNTB can also be used as the 6th PCI bus master grant output These signal have internal pull up resistors IDE Interface Signals Signal Name Type Description PDCS1 SDCS1 Primary and Secondary IDE Device Chip Selects for 100 Range For ATA command register block This output signal is connected to the corresponding signal on the primary or second
90. m o m emer meis COTTE SLR dee LEARNING DD DDBord Control DD board Control DD board voltage negative logie negative logic o fe 32 35 P64 P67 5 7 Internal AN o E Matrix RESET d amp mESET RESET Reset H8 F3437 F3437 See _ i mm a em few s ras eme 26 8060B N B Maintenance Continued to the previous table CONN_PLAYPAUSE OZ165 Audio DJ Play and Pause FANI SPD Power Circuitry Indicated the battery capacity is not enough to power on system LAN CARD BUS If system on suspend mode then received this signal amp system have to wake up Touch PAD Connect to Touch Pad DATA OZ165 Control OZ165 Power Audio DJ Scan FF Charge Circuitry Indicated charge circuitry to work FANI Return FANI CPU FAN Speed FAN2 SPD FAN2 Return FAN2 System FAN Speed 74164 Bit 0 7 SCROLL NUM CAP AC POWER BATT POWER BATTR _ LN m x eal Hec m 8 E rad De pes CE LM ae a ICH3M Requesting the system to enter power management mode clock throttling H8_THRM 2 5 5 A 48 27 8060B N B Maintenance Continued to the previous table ECO CI ECCO H8_KBCS I Super
91. of 1mA DDR 25V DDR 25V 1 Place capacitors between and near DDR connector if possible fee pet ROC ni 4 4 J J 4 J B 4 4 dl 4 A 4 Read cue crea C662 C144 C758 C754 C755 C758 C757 C104 C103 C756 C124 C101 C100 C102 C775 C121 cag C98 C120 C97 499 0 10 0 010 0 01U 0 1U 100 610 010 GIU 010 010 GIU 010 610 GIU 040 040 0608 0608 0803 003 0603 1206 1206 0603 osos osos osos osos osos osos osos 1 50 E 50V 50V 50V 507 50V 50V 50V 50V 50V 50V 50V 50V 50V 50V 50V 50V 50V REF_1 25V REF_1 25V 77 T Y Place one cap close to every 2 pullup resistors terminated to V1 25 ROC C761 C792 i 71 c791 777 71 71 774 71 cree REF 1 25V 100 DAY 04U 04U 010 oy GU GIU 010 010 0603 osos osos osos osos osos osos osos 0603 0603 50V 50V 50V 50V 50V 50V 50V 50V 50V 50V 50V 50V 50V 50V 50V T DDR 25V ez Tl oro ZL 1 Cl cree creo cres 7 1 21 cre 9 77
92. pin P23 and W4 10 88 156 VCC vss_10 VSS ATE Da j 58 157 vecio 55 11 vss HM ABE 054 VERE 1501 VECP_12 VSS 158 8514 a VECCHI VSS 12 vss as H4 Ae T voor 13 vss 159 ree taste vecia vss i vss HMS VSS 160 ters 18 VSS Vss_87 E ato M24 ATE Det ed E 15 55 161 PROVE 58 15 33 0108 TU T dus voor 17 VSS 163 16 55717 vss oo 48 Mat 0114 i VCCP 18 VSS 164 9 5 GTLREFO VCC 17 88 18 vss et n Hos VCCP VSS 165 lt 0 5 length TES HEA vss 19 vss 2 23 VCCP 20 VSS 168 tae Tesori GTLREF2 VSS 20 vss HN AT D14 VCCP 21 VSS 167 esha OACLI GTLREF3 20 vss 21 vss 94 52 ATBR Diss VCCP22 VSS 168 Be HcOMPO vec 21 VSS 22 vss es HE ne 019 pue vece 23 vss 169 220P 59490 e25 compo Voc 22 5528 ri A20 0178 VCCP 24 VSS 170 Ds Roomz 226 vec 23 VSS 24 vss sr pon Disk Es 55 171 RHOOMPs ATEI compe VCC 24 VSS 25 vss HBL Disk vecao 88 172 TETTE cones VCC 25 VSS 26 vss os A238 D20 VSS 173 177 VCC 26 55 27 VSS 100 R22 Deis VSS NCC 27 VSS 25 vss 101 nose 120ma 26 vocan VSS 178 TP Q 1887
93. runs during DAC Clocking DREFCLK I Display Clock Input This pin is used to provide a 48 MHz input LVTTL clock to the Display PLL that is used for 2D Video and DAC LVDS LCK Flat Panel Clocking DREFSSCLK I Display SSC Clock Input This pin provides a 48 MHz or 66 MHz LVTTL input clock SSC or non SSC to the Display PLL B Dedicated LVDS LCD Flat Panel Interface Signals HI_ 10 0 VO Packet Data Data signals used for HI read and write operations Hub HI_STB IO Packet Strobe One of two differential strobe signals used to Hub transmit or receive packet data over HI STB Uo Packet Strobe Complement One of two differential strobe signals Hub used to transmit or receive packet data over HI Clock Signals Signal Name Type Description Host Processor Clocking BC LK I Differential Host Clock In These pins receive a buffered host BCLK CMOS clock from the external clock synthesizer This clock is used by all of the GMCH logic that are in the Host clock domain Host Hub and System Memory The clock is also the reference clock for the graphics core PLL This is a low voltage differential input System Memory Clocking SCK 5 0 Differential DDR SDRAM Clock SCK and SCK pairs SSTL 2 differential clock outputs The crossing of the positive edge of SCK and the negative edge of SCK is used to sample the address and control signals on the DDR SDRAM There are 3 pairs to each SO DIM
94. tov tov HTRST 1206 1206 i206 1206 1206 I mro 10V TOV o 10V R25 R24 97 f 27 680 0608 CPU CORE 5 5 CPU CORE Leg Ler osas 1 1 Addr 98h i 010 GI 64U 010 e 0603 osos osos 0603 LI fou 460 fou 10U ou 50V SOV of ej SOV 5 SV s 50V 1206 1206 1206 1206 1206 Layout Note gave a 10v 10V 10V 10V 10V n SG BAM 9 CPU CORE as short as possible S d 1 4 1 J 1 10 mil trace css Css cse ossi cse css 7 0538 a J J A 3 1 1 ow 259 Note tou 100 100 100 100 100 10 osso 0524 1 cs23 csi sas 10 mil spacing 0603 10K ayou ote 1206 1206 1206 1206 1206 1206 1208 010 010 010 010 010 010 010 ni ninna 50v 0603 W 12mil 10 10V 10V 10V 10 10V 10V 0603 0603 0603 0603 0603 0603 0603 77 88 W l2mi SNV 4 SOV ej SOV 4 SV o SOV 9501 CPU THERMDA THRM E 2 sax Le Ci 22 vai sec m Fl Ew D SDATA THRM DATA 22 c 2200P 1 sola sjeo TERM 4 cpu ea 1 ole cai GPU TEREG B 1 C529 C15 C10 521 C527 C522 C539 C553 C509 C510 C511 ADMIOSE HIGNNE 100 100 100 100 100 GI 010 610 e een 508 1206 120
95. with the signals of those names on the Pentium processor Both signals are asynchronous Both of these signals must be software configured using BIOS programming of the APIC register space and used either as NMI INTR or LINT 1 0 Because the APIC is enabled by default after Reset operation of these pins as LINT 1 0 is the default configuration PWRGOOD PWRGOOD Power Good is a processor input The processor requires this signal as a clean indication that the clocks and power supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state PVRGOOD can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD The PWRGOOD signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout the boundary scan operation ITP CLK 1 0 CLK 1 0 are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board ITP CLK 1 0 are used as BCLK 1 0 references for a debug port implemented on an interposer If a debug port is implemented in the system ITP CLK 1 0 are no connects These are not processor si
96. 0 50V 7343 0 1U 10U 7343 330K 10U 4 0603 1210 av 1 GIU 1206 50V 5502 10V PR506 XR 10K 7 1 77 Pen rM MITAC DID Board WIGS MTGIID3 0 006 0 v Document Bate Tuesday Apri 29 2003 1 oi 7 AUDIO DJ BOARD 77 48V V Y V V V V sof Jof LINE_OUT_L R Trace width Space Isolate must 15 15 15 i J J d uum 2503 DEVICE 1 0 600Z 100M 1608 1 2 18 S007 100M 1608 4 CD UNE DUTT LINE OUT 3 DECTHEOPT 7 59021008 1608 1 0603 500 R506 1 47K 1 Li2 _ 6002100 1608 a TU NA 25 8 0603 7 D 0663 SPDIFOU in 77 CANN 1608 GPIFDSIOTP i ba 6002 100M SHARP swso3 52 soa AUDIO COM 1 CONN PLAYPAUSE 515 315 O0P 00 114 3 4 603 603 peos PLP3216S_NA nO CHOKE PLP32
97. 0 define the bus command During the data phase C BE 3 0 define the Byte Enables C BE 3 0 Command Type 0000 Interrupt Acknowledge 0001 Special Cycle 0010 I O Read 0011 I O Write 0110 Memory Read 0111 Memory Write 1010 Configuration Read 1011 Configuration Write 1100 Memory Read Multiple 1110 Memory Read Line 1111 Memory Write and Invalidate All command encodings not shown are reserved The ICH4 does not decode reserved values and therefore will not respond if a PCI master generates a cycle using one of the reserved values DEVSEL vO Device Select The ICH4 asserts DEVSEL to claim a PCI transaction As an output the ICH4 asserts DEVSEL when a PCI master peripheral attempts an access to an internal ICH4 address or an address destined for the hub interface main memory or AGP As an input DEVSEL indicates the response to an ICH4 initiated transaction on the PCI bus DEVSEL is tri stated from the leading edge of PCIRST DEVSEL remains tri stated by the ICH4 until driven by a Target device 74 8060B N B Maintenance 5 3 Intel 82801DBM I O Controller Hub 4 Mobile ICH4 M PCI Interface Signals Continued PCI Interface Signals Continued Signal Name Type Description Signal Name Type Description FRAME Io Cycle Frame The current Initiator drives FRAME to indicate the beginning and duration of a PCI transaction While the Initiator asserts FRAME data trans
98. 0 10 5 6 Paro d JP BEAD DFS 21 P LPDO as close as paraller port connect 358 D504 BAS32L 7323 25P FM SUYIN Parallel Port Connector 5 2502 Layout note i Lay Same legth dp i USBP place as close as paraller port connect di E alli ab Gon mm 38 USB power pin to connect 0608 5 on 500mA Trace 40 mil 4 15 UsBPo Dre 15 lt lt 3299 R683 a Sa s 47K 4 1 0608 WA 1535 i uio 4 R554 i 6mi 33K pin GND_USB USBP GND_USB1 GND_USB1 15 USBPO 1 7mi 1 i 1 15 USBP4 i USBP 15 ussoca lt 1058004 3 i R682 R685 Ret 1 EA 15KNA C286 C284 1 20m 47K 1 0603 0603 gi 1 0603 1509 eos SE 50 50 i ni GND_USB1 i 111 15 USBP4 i 2 313 i 1 4s 4 ese gt capi 15 C655 cers 777 d rca GND2 0603 1 coat T E GNI 50 sov H 4705
99. 00K Ko poso PR569 10005 0608 uas mee S xm 1 0603 777 5VAS 77 DVMAIN Li owman 9 4 Pues 8107 1 508 475K 0608 1 DBATT DYMAIN 2 DBATT BATT_DEAD 22 gt PUISA 4 SSOPB 4 PET 2835 TK 010 0603 0608 1 50V pads AD ADEN a 2N7002 21509 i 2 120Z 100M 2002 2 510 PF502 1202 100 2012 6 5N32VDC di 1 2 i 2 E 5VAS 71 6 5A 32VDC 1202 100 2012 if 9 28555 possi 2 301K 0 1U 1 3 0603 0603 4 1 PR20 514 E 5 22 BAT V BAT V 56 4 da 7 12 1 4 MA7P DIP 4 0603 PRO C10319 10705 1 Posso PRSSO 22 BAT C BTC 4 2 1006 5VAS A i 0608 0008 LLOVP 28 PUTSB A 6542 PR40 4 99K 402K LMV393M 0603 N Pai 0603 PR26 71 77 580 8 1 PRIB LSN 1 432K QU 2 T PC547 PC546 1 50 4 0010 10002 PR543 POSI 20543 0603 0608 5 TE 1 50V 50V 7 o_DBATT DBATT POWER Bison Document 411675500001 b Number Thursday June T2 200 24 a 5 PDF created with FinePrint pdfFactory trial version http www fineprint com SYSTEM POWER 12V
100. 03 voc NCCSM 9 OU 03U 010 010 REQS 020 989 25v voca 10 osos osos 0603 HI id 10 vcC 9 VCCSM 11 16V 16V 16V 16V 16 16V 16V pase od HADSTEO 1 HADSTBOF Hbase NT VCCSM 13 4 HADSTBI HADSTB1 HD378 777 eco VCCSM 15 4 4 4 4 28 piau BS er TERES atatatesta o 7 HCLK A JS HD41 VCCSM 17 0603 0603 0603 0603 0608 0603 74 1 J 1 VCCSM 38 TOV eV ej eV of TOV of TOV of HRCOMP HD42 R534 0603 HSWNGT AD13 VCCSM_19 HsWNGt ERA Biss 2 REV SANG AAT inte 777 4 HDSTBPO HDSTBPO 2 HDSTBPO HD48 VCCSM 24 ROSTENO VECSM 25 ENT _ HDSTBNO Hbaos 26 BETS oe HDSTEPI HDSIA 28 s ea mogli 28 DEE HDSTEP2 Hpsas 5 2 x HOSTAN O 9 VCCSM 32 3 E Versus HDSTBP3 5 5 HDSTENS Hpsee E VCCSM 36 4 HDINV 3 avccP 37 aose ODEN HTRDY HTRDVA BGASGE_25 HDRDY DRDY soa HH 4 HDEFER DEFER pn 5 tem Eu une o Ma po 4 Hyper 48 i EE 4 EGR ivar o EE Max length is 0 5
101. 078 Ey section 8 Y en vsso 9 9 50 9 9 VSSQ_10 vDDQ 10 777 VSSQ_10 VDDQ_10 777 11 11 VSSO_11 VDDQ_11 080 12 55012 0012 Vsso 3 88013 VDDQ 13 VSSO_14 VDDO_14 VSSO_14 VDDO_14 VSSO_15 VDDO_15 VSSO_15 VDDO_15 VSSQ_16 VSSO_16 vSSO_17 vSSO_17 550 18 550 18 vSSO_19 vsso 19 KAD2GG238A 5025 402532384 6545 BGA144F 08MM 1 08MM 1 c i 2 R516 TNA i 0608 1502 2 1608 Uso 1 MEMA_CLK1 tine vec 4 i LAMA o tese NCTAVACIGOANA 56705 MITAC i ie i NV34M 3 2 e Documen Ev 1 ustom Document 411676300001 2 i Number 5 ate Thursday June 12 200 Beata PDF created with FinePrint pdfFactory trial version http www fineprint com NV18M NV31 MEMB CLKi MEMB_CLKO 4 R566 R560 88 0603 0608 MEMB MEMB CLKO 9 MA 11 0 MEMB MD 63 0 9 04 di MEMB_MAO MEMB x A0 Doo AE gi MEME WAT 0 Dao MEM E
102. 12 MEMB RAS bedenin 214 FBORAS_ 11 MEMA RAS a GND 54 12 CAS SENESE FBCCAS_ 1 MEMA GAS Bf _ GND 55 12 H memcs GH FBCWE During AGP 3 0 operation the AGP_VREF input 0 35v 1 MEMA OSO MEMA CST ESAME anes ma 050 MEME CST aen in AGP 2 0 operation is 0 75V 18 Fel FBACSI_ GND 58 12 MEMB CKE FBCCKE 25 1 1 22 1 1 11 MEMA FBACKE GND 59 MEMB_CLKO Ls i 1 12621 0 1 MEMA GND_60 12 MEMB CLKO rene vir 8 FBCCLKO os 212 4 11 MEMA_CLKO men cto GND 61 12 MEMB CLKO KIH Feccuko L 11 CLKO REOR FBACLKO_ GND 62 12 MEMB 3 FBCCLKt 11 MEMA WEN Gt 63 12 MEMB CLK1 14 _ 80 20 i 11 FBACLK1_ 050 basi H FEADOSO GND_66 FECDOSI FBADOSI GND 67 FBCDQSA FEADOS2 GND 68 FBCDOS3 FEADOSS GND 69 FBCDOS4 AGP_VREF FEADOS4 GND 70 7860085 VREF FEADOSS GND 71 FBCDOSE 11 QS 7 0 lt 3 FBADOSS GND 72 FBCDOS 1 FBADOS7 GND 73 x m 0 P GND 74 i Soi ARS 11 FBABAO B26 GND 75 262 12 FBCBAT 0603 17 7 EM 10 EG
103. 1211 Ground 1 2 3 4 5 6 7 8 9 10 11 Monitor Sense Monitor Sense CRT DATA Data from DDC monitor Figure 1 CRT Connector HSYNC Horizontal Sync control VSYNC Vertical Sync control CRT CLK Clock to DDC monitor I pa N Table 2 CRT Connector 8060B N B Maintenance 7 Pins S Video port for TV Out Support up 1024 768 resolution Support PAL and NTSC system Support Composite Output by a transfer cable Input Active Resolution Active TV Lines Over Under Scan 320 x 320 480 400 Signal Name 640 x 480 480 400 720 x 480 480 400 720 x 400 480 400 800 x 600 480 420 1024 x 768 Input Active Resolution Active TV Lines Over Under Scan 320 x 320 540 500 640 x 480 540 500 720 x 480 540 500 Table 3 S Video Port 720 x 400 576 m 510 800 x 600 600 510 1024 x 768 520 Table 4 TV Out Support Modes 8060B N B Maintenance IEEE 1394 Port Supports serial bus data rates of 100 200 and 400Mbits second The Asynchronous and Isochronous data transfers are supported One IEEE1394 port supported 1 2 3 4 Fin 1 Table 5 IEEE1394 Port Figure 2 1394 Connector Audio Ports SPDIF Microphone In amp Line In Built In 2 high quality internal speaker 1W 8 ohm with Box Built in 1 mono microphone AC97 V2 2 compliance Internal Speaker Internal Microphone LED of SPDIF Plug Ear Phone In Mute Active Plug SPDI
104. 168 BLM 15 1932168 NA 0501 CHOKE 2165 BLM W505 ona 0 3230105 SPD 4 1 GONN lt 0603 LI n BAVSSINA 1 TCOOEPSTIAAAPIT al a ECT e ud C501 C502 C503 for 02100 m swso4 i DI 1 donn RW solution i 2 R507 503 1 1 BAVS9 NA 004 11 1 1 3478 2 0 NA 777 3 sws02 0608 0608 NR 1 doNN sTOPEJECT UNEN L 02 3 4 DECT_HP OPT UT DTC144TKA LINE QUT R TCOOEPETIAAAPIT 4 H7 DEVICE CAGND 1 UP DEVICE DECT ot 3 4 RI TCOOEPETIAAAPIT 2 1 La uni a BAV99INA 5 CD acis 100K 87152 2405 swso7 0603 HDRIMA 24 DN la RO TCOOEPETIAAAPIT Dn 100K De R510 i 202 4 UNENL 4 1608 17 1 470 4 77 0 2 6002 100M UNE NA 2 608 lt JACK 5P RIAWS 1 J d LGY2313 0200 n ios DE ADJ 1 3 627 4 1202 100 1608 5 1 1 1 FIT 77 CAGND MIGS MTGD1 2 003 8 lai External Micro Phone Jack CONN PLAYPAUSE 4501 1 CONN FF MCI 2 va CONN_RW 1 i MAGND 4 i CONN STOPEJECT JACK SP RIA WO 1 LI VOL UP LGY2313 0200 o DN 1 2 ADJ BTN 0603 120Z 100M MAGND CAGND 1202 ota Vois Yon oto Vos Vote Isolate CD_ROM noise CAGND MAGND 77 MITAC
105. 2 LINE OUT L R667 RIN LOUT i LINE OUT L 20 AOUT p 0603 Lou IAE i T OUT I 1 Wi2SMMHIB i 0603 r 20 LLINE IN passed LHP IN 8 E m 1 2 040 VAUX 4 0503 C190 2200 10 EW63 0603 1 0470 7 10 Lote si BYPASS L 77 m 3 SEBTLE PVDDI AGND 14 HP LINE 22 AVOL_UP 4 ues 5V_AMP 22 AVOL DOWN DOWN ITI AGND MUTE The Digital Volume 1 4 eis SE BTL HP LINE INPUT OUTPUT 20 cete 1000 28 control have 32 0518 31 66 0470 0470 5 Low L R L BTL S mesi 1 1 1 Ga SR Duo 0603 0603 10 RI G x ROB A wu L R HP SE 25 AGND Resa 86701 2 ona i 1 2 0603 T HI 777 AGND AUNA 0603 Lui AGND p 2 DEVICE DECT RN AUDIO CODEC 50V ize Document ey 4 NL 5 Date Thursday June 12 200 38 ot E PDF created with FinePrint pdfFactory trial version http www fineprint com
106. 2 1245 Pois 1202 100 10K 00470 i 2012 PR529 16v Peste PCI7 4 SPC 10039P 8622 1M 10 100 G2 30 2 2K 0608 PRE SK 1206 0603 0608 10V 50v 52 1 PC20 J 514816DY 2200 Poz 14 100P 508 PiFB2 7843 010 14 11 i pro PaE 1206 ph PiFB2 2 2 1 TOOK PRESE Fee Hai 4 2 22 10 TI SOR 25 PRIO Poe 0603 1 1 2 4 osc Ht 1 12 H 5 20 47 1 18 0470 PCI nS 1 12 5 REF He 4 3 Fem Z Pann 18 777 PL4 77 PWIT E 8 oui HZ m 4 2 1 2 16 1 2 1112 1202 1004 IK SYNG sen poze AU 2012 1 2 10 15 47 1 100 4 28519 va 9 T mo 30 m Posi PRS24 m 44 00470 ASK 1 Fai DA XR 1 18 Asa 2 n lis Pott 100P 24 2200 2523 MAX1858 7343 QSOP24A PRS28 7 16 av 0603 24 777 PRS20 50V 300 10K 1206 0608 tov 4 4 1 508 497 28 PG 777 120Z 100M 2012 DVMAIN DVMAIN 1 2 7 possi 150 hu as 0603 25V Sov 20 i 2 T 1 posse dios T ds n 1 25V Pug savs savs 777 508 28530 4 1K Puto 1 22 ADJ ON 1 PL30 508 2 PW20 2530 PCS 2 29531 PCS27 0 0470 100 1 M 270P 16V PRSS2 1208 0603 PRI a al sov 10 4995 10V 50V 5 20503
107. 2 55715 VSS VSS_16 VSS_87 H rar Y VSS 18 55 89 50012 E a G_AD27 30013 222 55719 VSS 90 9 Y VSS_20 VSS_91 G_AD28 50014 6 029 50015 2 VSS 21 vss 92 ADI Y VSS_22 vss os AEA G_AD30 50016 F Aa 6 031 50017 E23 VSS 23 VSS 94 HA E d 58 24 58 95 9 AGP_CBE 0 3 50018 ESI VERDE Fa 50520 24 vss 26 788 97 G 50020 125 G_CBE2 50021 823 VSS_27 VSS_98 G_CBE3 30922 A v22 VSS 28 VSS_99 GRCOMP 50023 B21 vss 29 VSS 100 i i 30 55 101 EE should be 10 mils wide T SON 0024 AB22 55 50 VSS 102 and less then 0 5 9 AGP_DEVSEL G_DEVSEL 50026 LIS VSS 22 VSS 103 from Od 8 AGP_IRDY G IRDYA 50027 B18 A VSS 33 SSH 18 TRY TRDYE 002 C20 65 4 WSS 105 AZ 8 AGP STOP 6 Spaes E12 vss 106 PA 9 AGP PAR G_PAR 5 vss 36 107 HPS 9 AGP_REQ G_REO 50031 EE 9 AGP GNT 50032 109 hg AGPREF 50034 c VSS 40 VSS 111 pg EA 50035 C10 VSS_41 55 112 9 AGP_ADSTBO AD STBO 50036 cp As i 9 AGP_ADSTBO AD_STBO 50037 VSS 43 x 9 ADSTE AD STEI 30038 Sit me wes 9 AGP_ADSTB1 AD_STBI 0 B19 mis veste E Sposi ce ME i SBA2 50043 HES vss 40 vss 120 43 NEN LIA ER ace ee Ee PLACE CLOSE TO MCH SBAS 50045 B2 VSS51 55 122 F SBAS Spass EZ ves ve
108. 2 AK 1202100 C715 6701 Close GPU SUS ETAT R60 060 R84 19 0603 4 TUINA 1608 420 4700 V IFPABRSET Pet 22 2 AK 1 0805 COND GPIO7 amp THVCTL 2 16 IFPAIOGND GPlos IFPAIOVDD GPIO9 TVMODEO R100 2 AK 1 0603 me Close ta_GPU ROC R109 7 0603 TVMODE1 j Xen OKINATOK 8 BUT AK 4 1202 100 1606 1 i Wa J j 603 0603 di pue Ls ano 4 t Mans IFPBTXDS 0805 close 0805 0603 _ _ 9608 SAB IFPBTXDS IFPABVPROBE 9 DVOD8 880 2 1 1 0608 80 20 together 39720 2 18 1 IFPCVPROBE 6 NE _ 77 eS IFPBTXD7 7 FPBTXD7_ JTAG 2 10 moo 2 170602 7 AMA 2 US NAME meer DA ROB ROB _ PEOD va Dh is ip mee NVxxM DEVID x FE ione zc 11 v NViBM xe pome R3 5 gt lt BR SWAPRDY A NV31 NV34 po unm 2 MEA 1 E 2 _ SWAPRDY B i 12 E 2 1 0603 4 2 1 NV18M Pro 0x7 Default ge X U2 IFPCTXD1 VIPDS 7 LA _ 13 1803 ROC NV31M OxA x X U3 IFPCTXD2 TESTCTLA Ri 10608 Ai IFPCPLLGND TESTMODE 20 p DVOHSYNC R115 0603 i PCI_DEVID_3I muan 31M Pfo N10 R116 2 AK 1 0603 115 2 1 1 1 MIELE H IF
109. 206 osos osos mus e WV cf WV 4 Ov of TV of 0054 ma EET omu 501 0010 HAZE Hose veci se vite 0608 0608 0603 0603 Hala pet voci 87 m 1 d J 1 2 1 J J J J 4 is Hata Hone cse Tl Ser Can L 6575 i cses coi 1 osso HSWNGO HSWNG Horat Siu 610 PI 010 010 80 vi io oos 0608 oos oS oss 1 080 5 11 VIT 11 16V 16V 16V 16V 16V 16V HATTE HD14 TV el IV ej TeV 167 o dev vecia m m m a e 150 150 VCC1 5 1 14 BEES Hort E 77 VOCI 8 15 EH An 1 1 prr i vg 1 HAZE vCC1_8 0 VIT 17 DDR 2 5V 2 Hebe 4 8 1 VIT 18 HA24 HD21 ce22 ceri cera T VOR ME HA2S HD22 100 010 010 010 Voci o 108 0608 oos 0603 ocio HSWNGO HSWNG1 HA27 HD24 10V 16V 16V 16V VCCSM 1 0679 cer A E SE Lon 18 mil trace 10 mil space Hd voco VCCSM 2 220 220 a 1 07 00 i voci VECSM ma T ee Tos Jos jan ToN Tos A D ee ui VCCSM 4 10V 107 16V 16V 16V 16V 16V 4RE0 0 4 HAST 5 Moog vous 4 4 HREO 0 4 HD29 vec4 6 HREGOH 192 4 E E i lasts VCCSM 7 Tu 1 HREQI HDsze Sau 90220 Sou voce voosM ce cese ceso cera HREQ2 pase osos oo 9608 06
110. 2072104402 272072104402 272072224701 272072334701 272072474501 _272072474501 272072474701 _272002474401 272075102701 272075102701 U U 80 CAP 1U CR 16V 10 0603 X7R SM YSV 50 80 20 0603 5 5 C24 C26 C4 C6 PIU 470 16V 20 0603 Y5 V SMT 470 16V 80 20 0603 Y5V S 470 16V 80 20 0603 Y5V S 470 CR 16V 10 0805 X7R S CAP 1000P 50V 20 0603 X7R S CAP 1000P 50V 20 0603 X7R S CAP 1U 25V 80 20 0603 X7R S C1 C4 CAP 1U 50V 80 20 0603 Y5V S C100 C101 C102 C103 C104 C11 C 50V 480 2096 0603 Y5 V S C501 C502 C503 C504 PC12 PC1 120 8060B N B Maintenance 9 Spare Parts List 2 Part Number Description Location S 627207510241 CAP 1000P 50V 10 0603 X7R SMT C25 212030 272075 272075 272075 272075 272075 272431 272075 272021 272021 272011 272011 272043 272993 272011 272075 272431 272433 272433 272075 272073 272071 272002 272003 02402 0170 0140 0140 0140 0590 0070 0650 0650 0670 06407 0640 0600 06404 2030 5650 56502 56502 81301 80401 05701 05403 05701 C CAP CAP C 100P 50V 10 0603 COG SMT 000P CR 50V 10 0603 X7R IN 00 50 10 0603 NPO S 00 50V 10 0603 COG SMT 00 50V 10 0603 COG SMT AP 02405 CAP 1000P CR 3KV 10 1808 X7R TU C11 C196 C5 AP C635 PC19 C213 C216 C33 C34 C
111. 210 3VA 14 REFIN CELLS Gg zl 25V 25 50V 25V 25V 4 FON pros XSR XBR PR544 H E E posse 060s A 0603 50V 10U T E E prao p pros se E T 4 Ty PR552 100K PC72 E BEAD 09050 SU i 5 DU wow 1 2 Lii PISO BEAD osos es oi LPRA pra Beos 1 lt gt pass 4 4 PRESS We TW CHARGING 22 poss Took E dae T ms E 3 puis BEAD ososo WIRE LED BLADJ PLIS 20 WIRE LED AI tf 2B 1 JBLADJ 22 a 2225 PWR ON al LEDOUAD O45VS m 7 Hs sf TED EIK LED DATA 22 BEAD 0805C 977 8 Mia HB RESET 22 BEAD 10 8 CORTE H8_RESET 22 0805C DVMAIN o Hino gen pom CDROMACTP 16 BEAD 0805C 13 14 H4 HDDACTP 16 i ENPBLT1 17115 16 POWER ENPBLTE ie a POWERSW 5 E sdi pm EM Wa TES DORSO p i PLI BEAD x H esi var venas o 2 1 215 BEAD 08056 REF 1 26 2 o 15VS m 2 censo BEAD SaMM BEAD 4 2150875 puo peas T scm oso scm 4 BEAD sou 010 oa 090 so pesos 7 pose as e T ds LEE NES SQ WW as Tes Tes T ms qq 4 77 77 i MiTAC DC DG CONNECTOR CHARGER Custom Document 411676300001 1 1 0 Number vate Thursday June 12 200 Brest
112. 220P 4700P 4700F 0 1U MD 47008 47008 220P 220P 010 VSSQ 4 ogos J ogos osos 0603 359 4 VDDO 4 0603 0603 0603 0603 0603 vsso 5 5 Li 50V vsso 5 000 5 10 10 50V 50 6 VDDO 6 E vsso 6 VDDQ 7 VDDO 7 Place in memory section 7 VDDQ 7 Place in memory section VDDQ 8 vsso 9 vsso VODQ S 5070 0000 77 5010 50 11 vSSO tI vssa12 5012 VbbQ i2 vsso 18 VDDQ 1 VSSQ 13 VDDQ 13 797 VSSO_14 VDDQ 14 VSSQ 14 VDDQ 14 vssQ 15 15 15 VDDQ 15 vssa 16 VSSQ 16 vssa 17 H vssa 17 VSsQ 18 VSsQ 16 vssa vssa 045 6645 BGATAAF 8 1 BGATAAF 1 MITAC 2 ize Document ev stor Document 411675300001 n Thursday June 12 200 Pheer T ar 1 PDF created with FinePrint pdfFactory trial version http www fineprint com LCD amp CRT INTERFACE
113. 28 ves ves 102 E2 A 35 VOCAT vSS176 VCC 29 VSS 30 VSS 103 0248 1587 Option to 1 59 s dii veom 177 40 104 nsvo 2 30 vss vss_104 HB Alb 0258 for future support VCCAS VSS 178 O11 Rss 31 VSS 32 VSS 105 M A294 D26 VDO VSS 179 32 VSS 33 vss 106 HA HREO 0 4 ASOR 0278 55 180 CPU TESTI VCC 33 VSS 88 107 5 HREO 0 4 ABI 0288 2 1 VSS 181 I TESTI 34 VSS 35 vss 108 He VSS 182 a VCC 35 VSS VSS 109 UE REOO 0308 93 vss 183 TESTA VCC 36 88 37 88 110 122 0318 VSS B4 VCCS VSS 88 88 111 REO2 0328 v10 0 5 vos vSS_185 5 HDINVO 38 vss vss_112 REOS D33 26 VID 0 5 VSS_186 DINVO VCC 39 VSS_40 VSS_113 REGS Dade vss187 226 VCC 40 88 114 HE 0358 33 18 DINV2 41 VSS a2 3815 6 HADS lt 086 VCCSENSE 58 189 DINV VCC 42 43 vss 116 HA HADSTEO 0378 vSS_190 VCC 43 VSS d 88 117 5 HADSTBO ADSTBO D38 VSSENSE VSS_191 44 VSS 45 VSS 118 5 HADSTB1 ADSTB1 039 BANIAS VCC 45 55 46 VSS 119 HBRO 0408 VCC_46 VSS 47 vss 120 HA 5 HBRO Brow Date BGM SKIS CPULGORE VSS_48 vss_121 126 5 HBPRI E 18 een s VCC 48 VSS 49 vss 122 Hi2 8 SIENA 3 BNR 0438 49 VSS_50 VSS_123 044 3 1 VCC 61
114. 2T0 13 1 3T 8 ON ON JP ON 10P ON ON 2 340673100022 COVER ASSY MINIPCI 8060 272615181401 CP 180P 4 8P 50V 10 0612 NPO 272605220401 2 330v 08 206 123 9 Spare Parts List 5 art Number 523467310004 27260122750 312278206152 22767310000 227672300004 481676300002 48167630000 273000610025 Description DVD ROM ASSY 8X SDR 083 QSI 8060 EC 220U 10 6 3 7 7 15 105 EC 820U 4V 20 10X10 5 FPCAP tri z gt d D tri d 2 ro gt J ree gt Zils c 4 gt D E gt 3 F W ASSY SYS VGA BIOS 8060B FERRITE ARRAY 1200HM 100MHZ ONL Y y 273000610025 FERRITE ARRAY 1200HM 100MHZ ONLY Location S C190 C206 C279 C285 C296 PC1 PC5 PC6 501 art Number 2456000 2456000 2950000 2950000 2950000 0 0 0 0 0 8060B N B Maintenance Description 335152000062 F SE LR4 730 POLY SWITCH PRC MEE 2950000 0 016 FUSE NORMAL 6 5A 32VDC 3216 SMT PFI PF501 PF502 345673100027 GASKET AUDIO PCB 6060 pae 343673100024 _ GASKET PCHCIA Ma 000 E Lumen fossero T_T Csin some firms ST rese ui fine ieri soin fuovancassi ssi T_T serio
115. 3 4018 0728 777 52 CPUCLKT2 45 0603 3 2 R123 1 0603 499 10P NA 10P NA 1 NT SUSA don 0803 19 0503383 0608 0603 muon 14 STP Poi 34 Pci Hl IA 10 Ae ik 1K 1426 STP CPU CPU_STOP CPUCLKC1 42 0603 3 CREA 0603 0603 Reog 2 0603 GPUGLKG2 0603 33 s TRENRBLE 9g VULTSELO 2 Rido PCICLK CARD 26 cLK ENABLE 9 VIT PcicLko H9 WOT i48 PECI LAN GARD LAN 18 a SVCLKANA SVCLKANA 1 PCICLK2 12 0805 EJ 2 R147 PCICLK LPC 21 2 25 VODA ROIGLKS 16 4 2 8151 PCICLK RAM 43VCLK66 VDDA PCICLKA E 20 305 Pcicus 23 em ICH cum si Sessio VDD3V66 1 PCICLKG 18 ooo ICH 14 0 1U 010 0 10 220 3SNCLKGPU 46 oo osos osos 0605 Sa eee Fo e Sor 9007 5 1 0 aVCLKPCI POIL 0603 0603 0603 0503 c wore Polak F2 Ex i PA m 3 js 4 auo aves 2 eg dy 2 Ruso ee 6 66 3 so 15 15 GND2 aveo 4 23 0503 83 2 9180 5 85M AGP 9 201 s GNDA avee 8 4 24 cns SE gros 5 SPINA SONA 195 1524 47 to IREF 1202 105950810 4 4 4 4 TSSOPSS cmo cra RIDI 010 010 220 4 0608
116. 3 57 0603 4 481820 019 QU 10 AZT O x TRST Ld SEHR E sem Lj Es to PCIGNTO 14 77 CADI 27 6 61 ISEE PCIRST 69142820421 ADOS 3 z AUDIO SUSPEND i ADEE 2 O CSISCHG TPBIASO PME 141820 0603 GRDZE CARDSPK 19 En CADIT pe IPWROK 1422 DAMM CADET PCICLK CARD l CUD TPeoP Hir E CARD pes EJ TPADP 4 E HB CON POLKRUN 14182021 I TPBIN Meuncs EL Test anne T TRAIN NENG Les 18 ens TPBON Mens E2 SEE SERIRO 41621 TPAON MFUNC2 CARD 22 777 MFUNGI 98 SIG inte 1410 FMGAXOPIHT T CAD31 D10 MFUNCO ES T PCLINTC 14 16 62598 22 0 0 09 1 CAD2S D1 030 28 08 029 27 00 028 26 0 027 28 1 026 2 025 GAD23 A3 AD24 CAD22 A4 023 CAD21 AS 022 CAD20 AG 021 777 GAD19 A25 020 CADIB AT GADIZIAZA 018 16 7 017 GADISIIOWA 016 CADi4 AS 015 CADISITORD ADIA vis CADIZIATI Apia GADI1 0E 012 ee He ES vera OE 1 10056 CADIO CEZ ADI VCCDi CADSIIATO ADIO Ww 3 VDDPi a _ 8 018 a I ud 2 i CADS DG 106 PS2211 7 GND HO DADUDIS 58 D cass cese 240 454 HAN CAD3 DS 58 B8 22 o 550
117. 35 C735 C87 C88 C94 R 18 520 C501 C502 C503 50V 10 0603 NPO SM C105 C107 C108 C109 C116 C16 C C C 10 20 1210 X7R SMT U 10V 80 20 1206 Y5V S 10V 10 1206 XSR SMT AP CAP 100U 10V 20 7343 SMT C173 AP PC2 PC39 PC4 PC48 PC53 PC538 10U AP 10U 10V 20 1210 X7R SMT PC516 PC517 AP 10 504 511 521 522 52 C151 C165 C188 C197 C212 C56 C C AP AP C 25V 10 1812 XSR SMT T 00 0U 25V 2 2mm X5R KYOCERA SM 49 59 PC25 PC28 PC539 PC545 PC560 C1 C10 C12 C122 C13 C14 C144 2 50 5 0603 NPO S C118 C119 C257 C263 C CAP CAP CAP CAP CAP iU CR25V 80 20 0805 0U 6 3V 10 1206 X7R SMT AP CAP CAP 150U 6 3V TPE 20 7343 SMT C871 PC37 PC41 PC65 PC67 AP 5U 10 25 20 1 9 7343 5U 10 25 20 1 9 7343 80P 50V 5 0603 NPO SMT 8P_ CR 25V 10 0603 NPO S U CR 10V 80 20 0603 Y5 0 CR 16V 10 0805 X7R SM PC504 PC505 PC506 PC531 PC55 PC13 PC14 C166 C277 C278 C737 C744 C75 C79 C141 C161 C164 C170 C204 C224 C6 PC13 PC532 PC68 PC69 PC88 P C Part Number Description 8 272003105701 CAP 1U CR 25V 80 20 0805 519 2200 2 35 10 1 9 55 CAP 220U 2V 35 10 H1 9 5 5P C CAP 220U TPE 4V 20 7343 SMT CAP 220U TPE 4V 20 7343 SMT 272075472701 CAP 4700P 50V 20 0603 X7R S C42 C48 C51 C58
118. 4 6 STOP Re voD_19 Place close to the BGA H3 FBADAT 7 St FBCD42 25 Ala 6 AGP PAR PCLINTA AKIR PCIPAR VOD 20 FBAD42 GND 8 FBCD43 26 14 16 _ VDD 21 FBAD43 GND 9 POS FBCD44 27 RIS me a VDD 22 FBAD44 GND 10 786045 28 6 AGP_RBF AGP WEF 4814 AGPRBF_ 2 o FBADAS GND_11 FBCD46 RIZ 6 AGP_WBF AGPWBF_ FBADAS GND 12 FBCD47 B18 18 AGPMBDET_ VDSOCLAMPO X FBADA7 GND 13 FBCD48 T_GND s RIS 6 16 STO x AGPSTO VOSOCLAMPI EE 4 GND i4 HH FBCD49 T GND 32 616 ST AGPSTI Place on solder VGA i FBAD49 GND 15 FBCDSO Tono FHS 616 AGP ST2 AGPST2 eg FBADSO GND 16 051 34 VDD33 0 lt lt M FBADS1 GND 17 FBCD52 T GND 35 8 ADsTaD AGP RDSTET A4 AGPADSTBFO VOD33 1 1 ELLE FBADS2 EM FBCDSS T GND HHE AGP_ADSTBI 2 4 FEADSI i FBODS4 37 6 AGE ADSTDO AGE ADSTED ARS E T ocne cam i i E GND 20 18 6 AGP ADSTBI AGPADSTESI VDD33 4 EC e um FBADSS 21 2 FBCD5G LS VDD33 5 FBADSS GND 22 FBCDS7 T GND 40 VDD33 6 FBADS7 GND 23 rex Ecc FBCD58 T GND 41 SE acpausy VDD33 7 FBADSS GND 24 LES Pisce
119. 4 PCIRST PCI AGP Device MCH M EIDE Device Odem ICHAM 82801DBM 1 STPCLK High gt Low 2 After CPU Stop Grant the ICHAM Output CPUSLP 3 SUS STAT 2 4 RTCCLK High gt Low 4 PCIRST 9 15 RTCCLK High gt Low 5 SUSB 1 2 RTCCLK High gt Low 1 STPCLK gt CPU Banias Process Stop Grant Cycle 2 CPUSLP Graphics NVIDIA NV18 PRO Turn Off 3 SUS_STAT p DC DC Turn Off 1 5VS 1 8VS VDDR_MEM2 5V 3VS 5VS CPU_CORE 5 SUSB y Embeded Controller H8 3437S Detect SUSB Status 21 8060B N B Maintenance 1 3 5 Resume from Suspend To RAM Sequence CPU Banias Process Stop Grant Cycle 4 STPCLK gt 1 Press LID Button 2 Select Windows Standby Function Graphics 3 Press Internal Keyboard Fn F12 4 CPUSLP NVIDIA NV18 PRO Turn On v ICH4M DC DC Circuitry 2 SUSB Tum On 1 5VS 1 8VS VDDR_MEM2 5V 3VS 5VS CPU_CORE 7 PCIRST 82801DBM 1 STPCLK Low gt High 2 After CPU Stop Grant the ICH3M Output CPUSLP troll 3 SUS STAT 2 4 RTCCLK Low gt High mbeded Controller PCI AGP Device MCH M i eo H8 3437S EIDE Device Odem SECIROT QUI High 5 PWROK Detect SUSB Status
120. 41 271071244301 RES 240K 1 16W 5 0603 5 271071244102 RES 240K 1 16W 1 0603 SMT PR537 271071270301 RES27 1 16W 5 0603 SMT 27107127481 RES27 4 1 16W 1 0603 SMT R31 R38 R505 R534 271071202102 RES2K 1 16 1 0603 SMT 271071205101 RES2M 1 16W 1 0603 5 R 27107134811 RES 3 48K 1 16W 1 0603 SMT PRI2 271071301812 RES 30 1 1 16W 1 0603 SMT R56 27107130101 RES 301 1 16W 1 0603 SMT R525 R536 27107130131 RES 301K 1 16W 1 0603 SMT PRS55 27107130310 RES 30K 1 16W 1 0603 SMT 27107130310 RES 30K 1 16W 1 0603 SMT art Number RES39 1 16 5 0603 SMT 271002478301 RES4 7 1 10W 5 0805 SMT 271002478301 RES4 7 1 10W 5 0805 SMT 1 16W 5 0603 SMT RES 4 99K 1 16W 1 0603 SMT RES 402K 1 16W 1 0603 SMT RES 41 2K 1 16W 1 0603 SMT 271071432211 RES43 2K 1 16W 1 0603 SMT RES 43K 1 16W 5 0603 SMT 271071471302 RES470 1 16W 5 0603 SMT 271071471302 RES470 1 16W 5 0603 SMT 271071471302 RES470 1 16W 5 0603 SMT 271071471302 RES470 1 16W 5 0603 5 RESATOK 1 16W 5 0603 SMT 271071475011 RES475 1 16W 1 0603 SMT 5 5 5 5 5 5 S aes 271071272101 271071272301 271071201101 271071201301 271071204101 271071203101 ELM 271071221302 271071221301 271071225302 271071244301 271071248102 271071270301 27107127481 271071202102 271071205101
121. 507 15 18015 HINTRO CINTRO CinQis 16 15 SIORDY HIORDY CIORDY 3 ICSIORDY 16 5 1 TPURKY RING Ex i TP544 22 ACTIVITY ACTIVITY TOUCHDOWN PI AST TPS4CO L TEJRX RX Tx FH TPIT O H 15 CDROM RST HRESET cresets 22 CCDROM RST 16 TP5472 3 3 TH 1 0 15 SDIOW HDIOW CDIOWi Poor CSDIOW 16 t PUT f 15 SDIOR HDIOR PI Cep CSDIOR 16 apa H2 15 SDACK HDMACK CDMACK CSDACK 16 21 1801 one LED2 vELP 12x HDASP PAL Gsonca 1445 PD 35 1 01 veta dx 15 c HDMARQ CDMARO cspREQ 16 ua oec PCLINTE 4 E 218 cHseno RESERVED4 6 x E 16 PCL PCI INTE b pr 19 1 3 30 INTA 20 1 2 gt POLINTE 14 16 MS gt BL RESERveDO nesenveps 22 2 GROUNDO PCIRST m 7 PCICLK MINI po JPOIRST 6 9 14 17 18 21 45 P 1 2 crounot x507 SEG x na erouns 32 osco dx Aum PMER PME 14 17 18 Lhe TED Gas SEG s ex 4 35 AD 29 RESERVED 3 AD30 ow Sog dg m 38 Hz Sx 10 39 40127 3 38 inni m Riz SS 41 ADOS 028 42 foe FH 248 RESERVED pias Hi spazi ai m como 52 ar Ko Raos 1 2 0608 ADT See 0608 ISCOROM 4 com 52 5 GROUNDS GROUND
122. 510 R511 40 FS2 R612 IK Ries 499 1 49 9 1 IK J12 J504 DDR SO DIMM Ps U3 45 R123 33 HCLK_MCH i CLK_DDR 0 5 gt 44 R122 33 HCLK_MCH Memory CLK DDR 0 5 21 R150 33 66M_MCH66IN Controller Hub R551 R548 Odem 49 9 1 499 1 3V_ICH SMBDATA SMBCLK R60 lt R164 10K 10K 29 SMBDATA gt 30 SMBCLK 4 5 25 SUSA 34 STP_PCI U507 _ 53 STP_CPU vo 39 R608 33 USBCLK_ICH gt Controller 22 R146 33 66M_ICH Hub 5 R616 33 PCICLK_ICH gt 82801DBM 56 R124 33 14M_ICH gt R125 33 SIO_14 318MHZ 20 a gt Par 0515 12 R147 33 PCICLK_LPC 1 gt Super I O Po 23 R140 33 66M AGP U4 NV18M 8 2 No Display 8060B N B Maintenance EEE Power Good amp Reset Circuit Check U3 Pe HCPURST P 3VS MCH M PCIRST VCCP Odem Ul Pas e PR502 R502 CPU 501 47 100K VR_PWRGD HPWRGD i Banias MAX1907 3V da lex P PCIRST Pos PU22 c RSMSRT BEEN D D Board S I 9 MAX1999 Sei POWERSW Ne ls 81 9 26 rod U507 Po U4 Pis U9 Pa US15 1507 LI NV18M LAN PHY Super Mini PCI BA R676 Po 423 POWERBTN IK 9 vo 110 018 18__ H
123. 55GM Memory Controller Hub Hub Interface Signals Signal Name Type Description Clock Signals Continue Signal Name Type Description DVOCC LK Differential DVO Clock Output These pins provide a differential DVOCCLK DVO reference clock that can run up to 165 MHz DVOCCLK corresponds to the primary clock out DVOCCLK corresponds to the primary complementary clock out DVOCCLK and DVOCCLK should be left as NC Not Connected if the DVO C port is not implemented DVOBCCLKINT I DVOBC Pixel Clock Input Interrupt This signal may be selected DVO the reference input to either dot clock PLL DPLL or may be configured as an interrupt input A TV out device can provide the clock reference The maximum input frequency for this signal is 85 MHz DVOBC Pixel Clock Input When selected as the dot clock PLL DPLL reference input this clock reference input supports SSC clocking for DVO LVDS devices DVOBC Interrupt When configured as an interrupt input this interrupt can support either DVOB or DVOC DVOBCCLKINT needs to be pulled down if the signal is NOT used DPMS I Display Power Management Signaling This signal is used only in DVO mobile systems to act as the DREFCLK in certain power management states i e Display Power Down Mode DPMS Clock is used to refresh video during S1 M Clock Chip is powered down in S1 M DPMS should come from a clock source that
124. 5V 20mA SW1 SW2 SW PUSH BUTTON SPST 4P 15V 20mA SWI TAPE 1 2 2 ADHESIVE FACE 20YARD wecwowiswammaw __ ums THERMIST OR 10K 1 RA DISK 103AT ovormoworuerwaeansmae 131 8060B N B Maintenance 9 Spare Parts List 13 Part Number Description Location S 288200144003 TRANSDTCI44TKA N MOSFET SOT 23 Q2 03 04 05 0504 0507 0510 0 288204425002 TRANS SI4425DY PMOS 8 5A 30V 0 0 02 02 03 03 TRANS SI4532DY N amp P MOSFET SO8 PR 02 TRANS SI4800DY N MOS 01850HM S0 PU11 PU12 PU14 PU15 PU20 P TRANS SI4800DY N MOS 01850HM SO PU2 PUS01 TRANS SI4892DY N MOSFET S08 PUO TRANS SI4892DY 508 PUSO2 TRANSSI7886DP N MOSFET 508 PULPU TRANS SI7888DP N MOSFET 808 PU3 PU4 Location S art Number 373101712351 270140000003 421666200009 422673100004 422676300001 Description T SCREW B M1 7 L2 35 K HD 2 NIB VARISTOR 280V 5 6X3 8MM TVB280 0 WIRE ASSY BATTERY BIOSNV WIRE ASSY INVERT OR LCD 8060 WIRE ASSY MDC 8060B WIRE ASSY MIC 8060 WIRE LCD ASSY LCD 8060 WIRE 20 UL1007 120MM RED YIYL P 332110020109 WIRE 20 UL1007 65MM BLACK 332110020094 WIRE 20 UL1007 65MM RED YIYI PW 332110026130 WIRE 26 UL1007 45MM BLACK 332110026128 WIRE 26 UL1007 65MM YELLOW 332110026125 WIRE 26 UL1007 81MM WHITE YIYI 273001050118 XSFORMER CI8 5 SIT16260 0839B 16
125. 6 1206 1206 1206 osos 30v 30V o 10V 10V 10V 50V 50V 50V 4 50 50V 4 50 50V M 418VS 1 5VS HSTPCLK 9 HOPSLP ursi _ J A dud J mi 1 1 1 24 2 502 C501 5 C504 i 1 14 1202 100 1608 100 100 100 0 0107 100 0 010 f 112 11206 E RU 212 10803 i 30V tov CALA One 0 01uF 10uF cap for each VCCA pin Don t overlay by CHOKE or vibrating signals As close as possible to pin Banias ize Document Pustom DOCUMENT 411676300001 Date Thursday June 12 2003 Bheet oF 1 PDF created with FinePrint pdfFactory trial version http www fineprint com GEE usc lt gt H0p0 63 4 Maze 400 n Hbi ipn J m n a a Jj 4 veci si 3 1 e tas Logo Lon 7 ew Les ue se Loe dus veci 53 1206 1206 12 tios toe 1206 1208 083 voci 53 08 1 1
126. 7 C589 C59 C59 272075471401 CAP 470P 50V 10 0603 X7R SMT C291 C293 C41 C53 C62 C630 C6 121 9 Spare Parts List 3 Part Number 272075471401 272072471301 272075470701 272431476502 272030680402 272431826501 221673150002 221673150003 221600020128 221503220001 221673120003 431676300001 335152000044 342665500008 324180786564 412676300001 242676300001 273000500095 273000500096 273000500096 273000500015 273000150313 361200001018 361200001018 331000007021 escription CAP 470P 50V 10 0603 X7R SMT CAP 470P CR 16V 5 0603 NPO P CAP 47P 50V 10 0603 NPO S 6 3 20 5 7343 5 CAP 68P_ 3KV 5 1808 NPO SMT PR CAP 82U 2 5V 20 SP CON 7343 S CARD BOARD FRAME PALLET 8060 CARD BOARD TOP BTM PALLET 8060 CARTON 380MM 320MM 320MM BC FLUT CARTON BATTERY GRAMPUS CARTON N B 8060 CASE KIT 8060B CFM BAT FUSE THERMAL 98 C CFM SUYIN S ST ANDOFF 4 40H4 8 N CFM TCL IC CPU PENTIUM M 3G uF CFM TCL INTEL Clexico 802 11b PR CFM TCL LABEL AGENCY GLOBAL 8060 CHOCK COIL 0 5UH 1 0mOHM 25 30A CHOCK COIL 4 7UH 20mOHM 25 4 5A CHOCK COIL 4 7UH 20mOHM 25 4 5A CHOKE COIL 50UH REF D 4 2 5 5T CHOKE COIL 900HM 100MHZ 20 2012 CLEANNER YC 336 LIQUID ST ENCIL P CLEANNER YC 336 LIQUID ST ENCIL P CON BAT 7P 2 5mm SUYIN Location S PC2 c12 C110 C111 15 19 Es P PL18 PL25 PL3 PL6 PL503 L3 L509 L532 L535 21 80608 N B Maintenance Part Number
127. 8_ICH4BTN E PWRBTN Controller U25 Hub 25 11 H8_PWRC i 1 er Level Shift 322 MDC P y17 Micro SN74CBTD3384 ICH4 M ALC201 Controller HDD_RST 35 i gt 7 Pie Primary EIDE Connector H8 F3437 _ s RESET il 023 vee 82801DBM Poo R32 IMP811 CDROM_RST 9505 33 CCDROM_RST 33 ON E3 a B Audio DJ Secondary EIDE Connector 96 8060B N B Maintenance 8 3 VGA Controller Failure LCD No Display There is no display or picture abnormal on LCD although power on self test is passed VGA Controller Failure LCD No Display 1 Confirm LCD panel or monitor is good Check if and check the cable are connected Ud Hare cold properly 2 Try another known good monitor or LCD module Re soldering solder Board level Troubleshooting Display OK Yes lp Replace faulty One of the following parts on the mother board may be LCD or monitor defective use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement Replace Parts Signals Motherboard Remove all the I O device amp cable from motherboard except LCD panel or extended monitor J501 3VS L501 LCDVCC L502 ENPVDD L503 LCD_ID 0 3 LI TXOUT 0 3 TXOUT 0 3 TXCLK D D Board TXCLK ENABKL MSK ENPBLT BLADJ Connect the I O device amp cable to the M B one at a time to find out which part is ca
128. 9 Vss 142 14 HIGNNE 5 A3 IGNNE HDSTBN 3 i Vss_70 vSS_149 14 HDSTBN O 3 5 i 88 71 88 144 14 HPWAGD PWRGOOD DSTBNO i vss 72 VSS 145 HPROCHOT DSTENI svecp o RP 1 ne B17 PROCHOTE DSTBN2 EXT DSTBN3 HDSTBP O 3 ziii HOSTBPIO 3 5 5 14 HSTPCLK 8 DSTBPO 6 14 HOPSLP DPSLP DSTBP1 gim om B DSTBPS CPU Voce 10u 100 wu 100 tou tou 100 1 3 1 1 FAO prew ig 210 i i 6 HCPURST RESET CPU THERMDA 4 4 777 mer THERMDA aig CFU THERMDU RI gt 0 R23 2 R20 2 TP2 51 51 54 9 N 39 150 54 9 N 330 1 i i o Les dle Core power decoupling Tes GL SEIS mre Gua THERMTRIPY O17 CPO TPRMTRIP OUT __ gt THRMTRIP OUT 14 60790680 CORE BANAS CPU CORE BGA479_SKTS 9 1 4 4 cse I cia osso 4 3 100 100 tou 100 tou 10U cia osso 1206 1208 12 1206 1208 1206 1206 Tou fou 10U 10U 10V 30V 10V 10V f 1206 1206 i206 1206 1206 4 TOV 30V ROPORST HEN csss csse T c21 STETETE i cesa osas 0552 7 0505 D 0 100 100 100 100 100 10V 1 tov
129. ADI BTN 20 ET 608 FPG FFCHMMI24P feti 800 7 3 51 TMOO PBONDBO S Tep para f LED CLK 28 R675 ACTIVITY 100 B52092402 Hs sor PB1 XDB1 LED_DATA 28 miss TK x 5 PAS TMCIV HIRQY PBoxpe2 81x 4 621 DI 55 e_N 0808 R249 1 2 PWR EL 1621 9012 FAN 24 PASITMRI HIRO1 PBA XDB4 88 gt CHARGING 28 777 C232 E PAG PWO PBNXDBS ADI ON 50V 0603 PWR ON T 56 PB6 XDB6 X ADI ON 27 SERI 25 From PB7 XDB7 SZ A T DATA 21 2 CARD RI HEU 18 peo paokeving ETTI 17 24 LEARNING 12 PS2 SCKO PA1 KEYIN9 Tess RIT 26 PEOKEYINO FTCI Pagikevinio imen 20 CONN PLAYPAUSE n 27 PEIMEVINIFTOA 242528 E CHAIN 2021 E 28 PEZIKEVINZIETIA PAAKEYINI2 ETA VOL UP 20 20 21 CONN RW E PeSKEVINSIFTIB VOLON 20 LAN WAKE 20 CONN STOPEJECT 32 peaevinaenio PABIREVINS I Tong LAN WAKE 18 3 PESIKEVINSIFTID PATKEYINIS H lt gt 21 DEAD 24 E 34 pesikEVINE IROS ISTBY FVPP Meum PE7KEYIN7IRO7 20 21 SCROLL_DOWN RES Hi 4 20 21 SCROLL UP Xr 2 R291 EXTAL IRESO 100 10K 437 00 0 5MM Reg 1 0603 50V 4 501 Sa p External Pull Up Down TP 0603 CPU FAN Control ROG 5 ROC
130. AGO2_64_35_1MM caso case 5 1 470P 470 470P 805 0603 10 ej 80 20 10 2 4 ceos 7 4700F 0 0470 0 047U 0608 0603 cese a TETE 80 20 80 20 47 stor Document 117590001 m Pare Thursday June 12 200 preet st E 5 z z z 1 PDF created with FinePrint pdfFactory trial version http www fineprint com NV18M NV31 Layout Note avs
131. AIN Troubleshooting Power source PL29 first use AC to PQS Replace the faulty AC adaptor or Battery power it PR36 PR37 PD506 PD507 Is the M B and charger BD connected properly 1 511 Yes Connect AC adaptor Check following parts and signals Parts Signals Battery J21 DBATT Power Replace PL509 ADEN OK Motherboard PL510 BAT V Yes 501 502 Replace the faulty PU24 Charger BD 89 8 1 No Power 8060B N B Maintenance When the power button is pressed nothing happens no fan activity is heard and power indicator is not light up P28 PQS JLSO2 ADINP 1 P28 PQS PR36JL501 ADINP 2 gt PQS ADINP PFI PL28 PL29 PQS PR37 PD4 PDO POWER IN gt J23 PD506 Charge PR52 PU21 PU13 PU14 PL25 PR17 PU17 PU18 PRI4 PUS05 P28 PU24 Discharge 1501 1502 0501 PU11 PU504 PL18 PL13 P27 1 3VS PU9 PUS03 PL30 PU10 P27 P26 PUI PUA PLI PRI PR2 DVMAIN _li P24 PUIS PU16 PL24 PL21 PR30 PD507 Discharge 5 ALWAYS PRS51 PU22 NOTE P28 Page 28 on M B Board circuit diagram Through by part PFI PU20 PU23 PT1 PR556 PL504 P25 P24 PQ502 12V mmm 12VS PU20 PU23 PT1 PD8 PU507 PL505 P25 P22 PR27 L31 P25 PQ2 S VAS P14 PR547 25 DI9 3V VCC_RTC CPU CORE P25 PUR P25 3V m pu 1 54 P18 P19 Q9 L530 5V_CD
132. BEjo 9 CBEo 3 141720 E 43V LAN ae PT 4 T 123 120Z 100M 1608 9 1 R204 0805 9 VS i s C145 71 4 ee 120 1202100 160 Sol 220 Siu 610 00 POE 22 1206 1206 0603 0603 0603 PME 14 17 20 16V 16 50V 50V 50V PN 1827 1 2 0603 dnb 388932454882 844 us 85883885882r 7f55c99RASEIESRESESZ 3985 LAN lt lt lt lt lt Buse x sa 558555522802280120012001209 BEBE 2 14172021 POLKRUN S855 2 14 16 17 20 FRAME FRAMEB EER 14 16 17 20 DEVSEL DEVSELB 1 1 71 71 Te SERR Deva 18 010 GIU 010 ADIB 14 16 17 PERR PERRB 0603 0603 0603 0603 0603 0603 141720 PAR IDSEL RN XING 50V 50 oj 50 50V 50V 50V PAR 7 PCIGLK LAN PCICLK XIN 14 16 PCLINTD RXIN d A 12 5 14 16 17 20 IRDY 14 PCLGNT2 1 3V_LAN AVDD LAN 1416 PCI_REQ2 9 Porst n gt FORSEN mies 1 2 0808 RE 1 ead PCIRST R184 0603 ini 6 9 14 17 20 21 PCIRST 1 2 060 50 C167 i 4 x cu eur vm ew em ROMCS OEB 0603 91 0 10 ISOLATER us 1206 0608 osoa 0608 s AIV LAN 50V aj 50 af 50V 0508 1 0608 n j EECS 1 w al flex ver ne jb Caos 1 So 8 88 5
133. BN 3 0 Each group of 16 data signals correspond to a pair of one DSTBP and one DSTBN The following table shows the grouping of data signals to data strobes and DINV Quad Pumped Signal Groups Data Group DSTBN DSTBP DINV D 15 0 0 0 D 31 16 1 1 D 47 32 2 2 D 63 48 3 3 Furthermore the DINV pins determine the polarity of the data signals Each group of 16 data signals corresponds to one DINV signal When the DINV signal is active the corresponding data group is inverted and therefore sampled active high DBR DBR Data Bus Reset is used only in processor systems where no debug port is implemented on the system board DBR is used by a debug port interposer so that an in target probe can drive system reset a debug port is implemented in the system DBR is a no connect DBR is not a processor signal or performance monitoring tools 64 8060B N B Maintenance 5 1 Intel Pentium M Processor Signal Name Type Description Signal Name Type Description DBSY DBSY Data Bus Busy is asserted by the agent responsible for driving data on the processor system bus to indicate that the data bus is in use The data bus is released after DBSY is deasserted This signal must connect the appropriate pins on both processor system bus agents DPWR 1 DPWR is a control signal from the Intel 855PM and Intel 855 chipsets used to re
134. C96 126 L 760 L C764 e e e 49 9 00 T OOlp T Controller e e 4 PE 77 Hub Ps Odem A 33 PI 5 0506 gt 3 R122 29 HCLK_MCH 33 d p l 3 44 Clock gt R150 Generator lt 30 gt 66M_MCH66IN 33 168950810 gt 2 3 CS 2 3 gt CLK_DDR 0 5 CLK_DDR 0 5 3 5 CLK_DDR 3 5 e 102 8060B N B Maintenance 8 6 Keyboard K B Touch Pad T P Test Error Error message of keyboard or touch pad failure is shown or any key does not work Keyboard or Touch Pad Test Error Check U18 J17 J10 for cold solder Yes Re soldering Is K B or T P cable connected to notebook properly Board level Troubleshooting No Sa No One of the following parts or signals on the motherboard may be defective use an oscilloscope to check the signals or replace the parts one at a time and test after each Try another known good Keyboard replacement or Touch pad Parts Signals Replace 0511 5VA Motherboard 018 H8_VDD5 J17 3VS Replace the faulty J10 45V Keyboard or U25 ROMCS Touch Pad L13 115 MCCS KI 0 7 KO 0 15 T CLK T DATA 103 8060B N B Maintenance 8 6 Keyboard K B To
135. E l Dat bat 15 a2 baz A2 S 003 bas MEME VAS M 004 pos BI Mah per 5 Dos E lt lt gt OS 7 0 9 a 6 096 S 096 pi ene ap 0007 at oser 35 2 MEMB 054 a 2007 FAT USED 1 MEMB 050 9 FBCBAO Fdo Nota ere RSI 0603 8 L4 Doe pt bos NEVE 8 Das Hitt HAS MENE NDI ATO PE neve Dar 9 0 lt gt AI Dallo Cri i EE 0012 0013 HE neve 096 DOMI EH z VGA_MEM2 5 LE mena VGA 25 pave ER D 0018 ai oses 7 2_ MEMB oss RAS pavs 0018 p ves ost posi Ris ala 8 MEMB CAS CAS bast R572 0603 MEMB_MD48 0 MEMB_WE Gis MEMB nes x E meme mo neri B E Dale MENE MD on 9 MEMB CERT Li 5017 Ei meme b 8 MEMB cs 2 0603 A CERT EER 0603 8 MEMB CLKO cK 2018 dl 1 8 MEMB_CLK1 Lilo cee LEL x 1 9 EMG CERE Lit oh ek Bate CRI M MIL 0020 2 x pazo FH REFS ui Dax HL WDSS REF2 0021 245 VREF VREF 0622 ME MD Na Daes x MEMB 056 Nes 0022 De l EE 1 22 paso 81 9851 936 _ 0052 Tes VA TE MEMB_MD56 Nez MEMB
136. E 1520 MINI PD MPCIACT hi 4 sl cii cim 1 E 3 4 iu 010 1 ef ee fe oe ef VR PWRGD 10 Reza 0603 10M H7 7 92 768KHZ Ried PCLKRUN 10 0603 Number aie Thursday June 12 2003 14 sr ig 5 z E z 1 PDF created with FinePrint pdfFactory trial version http www fineprint com O CONTROLLER HUB uso7E 29 usero USER cen usar o Ho HL 23 Usbpo 088 08 Hs 9 Teo gian He Route signals with 5 10 trace apscd pouting Bignale must atum de uo i E HUB_ i TE aa uee 88 a Bru eet cce BS E VREF signal TP5349 1 8170 0 58 E GPIO CHARACTERISTIC LIST 23 USBOCO U55000 8189 20 HUB STB 6 H i i NAME TYPE POWER PLANE CURRENT DEFINE 23 USBOC2 2058002 Als
137. E ow oo 358888 8 888 8 sasgagss 58582 85 1 Wes 77 50V 685855 SS 222 2 55555555 923999 66 os To d 943 NO P N A2 5V_LAN 2 5V_LAN PQFP100 0 5MM Ca o n 1808 Bee Reso 1 6 0603 A 4 1 2 1 C800 inn GIN Select 43 or 45V for 81011 124 1202100 1608 e detect Standby power for 1 2 7 i eno AVDD_LAN 121 120Z 100M 1608 1 Must close to RTL8180L RJ45 1 2 3 H si 5 m 43S 25 8 T 19 MONO OUT MONO UT 1 2 R307 Place near to transformer 8 4 i MODEM SPK r pai Er 5 LSPK MODEM SPK 19 20 GND a 8 tS J Le Ns n 1 5 GND 45 ALLTOP 5j g mex cus os sos 90071020 i 5 e 18 SE TO MDC Layout Note zl 8 2 pro iod cem euer nn el B4EFFXRSR 15 19 20 ACRST 25 3 E R692 1 2 0603 1 15 20 gt TERR 3 i FARA 2 00 29 30 R691 ACBITCI EX GND SHIELDING 1 2 08 LK gt 15 1920 1 FMIO BMMIH2 4 S WIWIS 12 6 6 12 mils i B 0603 1 H as short as possible D 57 un GND 45 amp 0603 a 4 i PIRX TXD 1 1 16 UTX 777 voi AVDD LAN o 0808 ol 1 5 I n MDC HARDWARE STRAP
138. EC J18 H8 F3437 Micro Controller J22 PCI4510 PCMCIA amp 1394 Controller 62 8060B N B Maintenance 4 Definition amp Location of Major Components 4 1 Main Board Side B 505 U506 0507 0515 02165 Audio DJ Controller ICS950810 Clock Generator Intel 82801DBM Controller Hub 4 Mobile ICH4 M PC87393 Super I O Controller 63 8060B N B Maintenance 5 Pin Descriptions of Major Components 5 1 Intel Pentium M Processor Signal Name Type Description A 31 3 Io A 31 3 Address define a 2 32 byte physical memory address space In sub phase 1 of the address phase these pins transmit the address of a transaction In sub phase 2 these pins transmit transaction type information These signals must connect the appropriate pins of both agents on the Intel Pentium M processor system bus A 31 3 are source synchronous signals and are latched into the receiving buffers by ADSTB 1 0 Address signals are used as straps which are sampled before RESET is deasserted Signal Name Type Description BPRI BPRI Bus Priority Request is used to arbitrate for ownership of the processor system bus It must connect the appropriate pins of both processor system bus agents Observing BPRI active as asserted by the priority agent causes the other agent to stop issuing new requests unless such requests are part of an ongoing locked operation The priority a
139. EO 0 ADI 4 HFERR misi a a 4220 FERRE 97025 FORSI_NSE SUSPEND 17 vecsussa vss HS 4 4 GPS x 16 PONI REQB REQS GPIO 1 016 pidas SS vss 16 U B59 REQA GPIO 0 015 ie 16 1721 serra lt gt ERO 122 serio vee VCCSUSS 3 vss POLENTA SUSB 9 3 vss oa 2 9 a ie mo rm sum eran SE PELA PETE 824 ADi2 1 4 1068008 SLP_S4 srp ss VCCSUS3 3 vss 522 18 PCL GNT2 see I CNTA 2 011 1 2 Usd DROITE SEP RE er rc s vss D mmc s Tac yor pines RS 2 cla TE voci s Es 1 GNTB GNTS GPIO 17 ADB LADI0 3 RH LADU EWHI SYS_RESET PS tan RST 0603 v voc s vss 3 O GNTA GPIO 16 07 RTC 21 LAD O 3 LAD2 FWH2 TANRST DYS 77 VCCI S vss p E EN kae vss 06171820 FRAME FRAME ADS SUSCLK SUS STATPAPCPD SUS STAT 9 1021 veci 5 vss 6171820 IRDY IRDY ADA 522 AM SUSCLK VGATENRMPWRGD Mi PWRGD 05 vocis vas 1617 18 20 TRDY TRDY amp ADS INTRUDER THERMTRIP THRMTRIP OUT 4 1_5 vss 16 17 1820 DEVSEL DEVSEL AD2 7 RTCRSTE PI 02 a gt 1 5 vss
140. ERT GPIO 10 9 I Not implemented GPIO 8 I Fixed as Input only Resume power well Unmuxed GPIO 7 I Fixed as Input only Main power well Unmuxed GPIO 6 I Not Implemented in Mobile Assign to Native Functionality GPIO 5 2 I Fixed as Input only Main power well Can be used instead as PIRQ E H GPIO 1 0 I Fixed as Input only Main power well Can be used instead as PC PCI REQ A B GPIO 1 can also alternatively be used for PCI 5 V_CPU_IO Powered by the same supply as the processor I O voltage This supply is used to drive the processor interface outputs VSS Grounds NOTE Main power well GPIO are 5V tolerant except for GPIO 43 32 Resume power well GPIO are not SV tolerant 81 8060B N B Maintenance 6 System Block Diagram Ur U501 Intel Pentium M Processor Thermal Sensor ADM1032 Micro FCPGA CRT D SUB 15 U4 AGP Bus 4X TV S Video NVIDIA U3 NV18M 1507 LCD Panel Odem 200 pin DDR SO DIMM Socket 2 MINI PCI North Bridge wireless PCI Bus Hub Link External Microphone U22 Internal Microphone PCMCIA 1394 USB 3 U507 017 Sui AC Link Uli Usio Controller amp Socket Aud
141. ESI 11 3 060 at Number 271071150501 RESIS_ 116W 5 0603 0IT art Number 271071000002 271071000002 271071010301 271071 271071 271071 271071 271071 271071 271071 271071 271071 271071 271071 271071 271071 271071 271071 271071 271071 271071 271071 271071 271071 271071 52101 52101 00302 00302 0221 0110 0130 0410 0410 0410 0410 04302 04302 04302 04302 03101 03101 03101 03302 03302 03302 06301 _27107100000 _27107100000 271071010301 271071152101 271071182101 momoo aere 271071101301 271071104101 271071104101 271071104101 271071106302 aeneo anne 271071108302 271071103101 annone 271071103101 271071105302 271071103302 271071105302 271071106301 RES 1 5K 1 16W 1 0603 5 RES 1 5K 1 16W 1 0603 SMT 510 1 16W 5 0603 SMT 510 1 16W 5 0603 SMT 1 0603 SMT 196 0603 SMT 27 5 E pen gt gt 0603 5 RES 100K 1 16W 1 0603 SMT 6W 1 0603 SMT 6W 1 0603 SMT 6W 1 0603 SMT E gt gt em ALA gt 5 gt 1 16W 5 0603 5 RES 100K 1 16W 5 SMT 510 1 n 6W 5 0603 1 16W 1 0603 SMT 6W 1 0603 SMT 6W 1
142. F Device In Mute Active Plug External Microphone Mute Mute 8060B N B Maintenance RJ 11 Connection to Modem Daughter Board Connector Support 56Kbps V 90 1 2 3 4 No Connect Phone Line Positive Phone Line Negative No Connect Table 6 Modem Port Figure 3 Modem Connector RJ 45 Support full duplex 10 Base T 100 Base T Ethernet 1233452850788 Transmit Data Ring NS Transmit Data Tip Receive Data Ring Internal termination resistor Internal termination resistor Receive Data Tip Internal termination resistor 1 2 3 4 d 6 7 8 Internal termination resistor Table 7 LAN Port Figure 4 LAN Connector 8060B N B Maintenance Infrared interface supporting IRDA format FIR IrDA 1 1 compliant HP SIR supported USB Ports Three industry standard USB 2 0 ports Support MAX Power Current 500mA each port USB Device Power 5VDC Balanced Data Negative Balanced Data Positive Ground Table 8 USB Port Parallel Port Configurable as logical ports LPT1 LPT2 or LPT3 EPP rev 1 7 amp 1 9 compatible ECP IEEE 1284 compatible Industry standard 25 Pins connector Figure 5 USB Connector 8060B N B Maintenance STROBE Data Strobe PDO PP Data bit 0 PDI PP Data bit 1 PD2 PP Data bit 2 PD3 PP Data bit 3 PD4 PP Data bit 4 PDS PP Data bit 5 1111 4 3210987654321 nn Printer Acknowledge C O O C C O O C Q
143. GND2 T eos ms 1518 19 ACSYNC 108 AC SYNC 104 x SDOUT GND IN 3 BATS4 SOV of SWV 4 SOV 1516 MSDIN LE 1 aba 3 ATA OUT 108 ACSDOUT 15 18 19 38 PAVMODE 82 MT 15 18 19 ACBITCLK AC BIT AC CODEC 196 AC97_RST 109 AC_CODEC_IDI AC_RESET 15 18 19 MINIPCISPKR 1 2 8305 0 0603 11 112 19 MINIPCLSPKR lt 1 MOD AUDIO MON RESERVED 112 02165 77 113 AUDIO GNDO GROUNDIS tit 31 POFP100 05MM x115 SYS AUDIO OUT SYS AUDIO IN 16 iov E MODEM SPK 18 19 an SYS AUDIO OUT GND SYS AUDIO GND ET 1008 1008 1008 100P 119 120 0608 0603 0603 0603 0603 AUDIO_GNDI AUDIO GND2 1 MPCIACT 10 10 10 Liv 121 RESERVEDS 122 MPCIACT 1445 VCCSVA 33VAUXIT GND1 77 GND2 GND R301 fe D 470 2 2uf 100ms SIZE 45V 2 UM 4 827 101 0038 R144 ATK ATK 0608 0608 IF 1 ID is B4h 777 IF 0 is 34h Ri36 ATKINA 0603 1206 16 cess ITT 12VS 3506 OGIUNA usi2 4 0608 1 45V x ilo DEVICE DECT 2 NB ERR 2 1 19 DEVICE DECT pE 1 GND 55 19 LINE OUT L TNE OUTA 19 casa cass ADPSSDTAR SNA cas 19 LINE OUT PDIFDUT 010 10UNA 508 UNE NL 17 0608 1206 0503 co 19 UNE
144. I O Port 62h 66h chip select oim CS ERE CE fe fe fe fee a m CSS SI SS 1 3 9 Power Consumption of Suspend Mode Suspend to RAM 90mA Suspend to Disk Soft off Mechanical off TBDmA 28 8060B N B Maintenance 2 System View and Disassembly 2 1 System View 2 1 1 Front View Turn J Down Button Turn I Up Button Stop Eject Button Play Pause Button gt i Button Button CD DVD ROM Power Button External Microphone Jack Line Out Phone Jack Line Out Phone Jack Top Cover Latch Hard Disk Drive eeeococeceoococoQ 2 1 2 Left side View CD DVD Disk Drive 29 8060B N B Maintenance 2 1 3 Right side View PCMCIA Card Socket IR Sensor 2 1 4 Rear View Power Connector USB Ports 1394 Jack RJ 45 Connector Parallel Port VGA Port System Fan S Video Output Connector Kensington Lock RJ 11 Connector Ventilation Openings ae Le is enin _ 30 2 1 5 Bottom View Q Wireless Card O Battery Pack Extend SO DIMM Hard Disk Drive 2 1 6 Top open View Battery Charge Indicator Battery Power Indicator AC Power Indicator Microphone Keyboard Touch Pad LCD Screen Device Indicators oocoeooccoceQ Power Button 8060B N B Maintenance 31 8060B N B Maintenance 2 2 System Disassembly The section discusses at length each major component for disas
145. I8M e a J1 P28 LI 23 J9 J501 5VS SNY e L503 11 m 5VAS E BLADJ ZEN 2 M Pu 1502 4 E 5 0507 ES coe 5 4 5VS 5VS From 018 H8 ENPBLTI S U10 17 1501 y 1 ENPBLT 5 C504 C502 38 Controller un Hub 15 ENPBLTI 7 DC Power Board ENABKL_MSK Qa ICH4 M DTC144TKA 1 000 CIT Inverter Board 98 8060B N B Maintenance 8 4 External Monitor No Display There is no display or picture abnormal on CRT monitor but it is OK for LCD External Monitor No Display 1 Confirm monitor is good and check Check if the cable are connected properly U4 J6 are cold solder Yes Board level Troubleshooting 5 Re soldering 2 Try another known good monitor Display OK Replace faulty monitor One of the following parts on the mother board may be defective use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement Parts Signals Remove all the I O device amp cable from i V motherboard except monitor Motherboard 2 SDA HSYNC VSYN Connect the I O device amp cable SCL Display to the M B one at a time to find RED OK out which part is causing the GREEN problem L518 L520 BLUE 99 8060B N B Maintenance 8 4 External Monitor No Display There is no display or picture abnormal on CRT monitor but it is OK for LCD
146. IO PCSYSTEM 28 ISCOROM he SRO LU UNDO Tee a 018 0120 38 GROUND n Pan i PAR 141710 ds T 82 ues iA savs 5 40 BEE 16 oj voL noy 51 trove gt anouno PE FRAME 48 ua PCLKRUN 55 3342 aoe FRAME 14 16 17 18 Ss ince 14173821 PCLKRUN 05 881 KRUNE Trove 88 um TRDY 34164748 X H RI29 14 16 17 18 SERR SERRE stops 58 STOP 14 16 17 18 0608 OK Ress 1 2 4 7K 0603 1 28 GROUNDS 33e H DEVSEL Rise H PERRE DEVSEL DEVSEL 141617418 m A 0608 57 woDE 1 PWR Abs 78 4 GROUNDS 2 R139 R Rist 010 GROUNDS 4 83 GROUND ADIS 47KINA 0608 is 96080 Hn 30 pesera pont 87 Aola z sain 88 Apis 20 4 28 pay veco 1202 00M ADIS ADIs iaia dined veci 0502 BATS4 Di2 vece 1 15 35 ADI ADIO 8 0 MPCI PD 22 CONN_STOPEJECT a t 3 BATET RW 31 STOP_EJECT 16 r3 pu RESERVED MPa Lino 0605 21 22 CONN_RW PREV_TRK SCAN_RWONDO 4 i 21 22 CONN amp NEXT_TRK SCAN_FWwaND1 H em on LI GROUNDE GROUND14 192 W S 6 12 mil 3 PLAYPAUSE 36 F 65 0 10 0 10 0 10 103 104 22 CONN_PLAYPAUSE 1 PLAY PAUSE
147. L HDD 8060 1 PART 10 345673100028 CONDUCTIVE_TAPE TP COVER 8060 1 PART 345673100036 CONDUCTIVE TAPE KB COVER 8060 11 PART 21 1346673100054 THERMAL PAD NB 8060 1 PART 22 346673100068 _ SPONGE3 THERMAL MB 8060 1 PART 23 346676300007 SPUNGE THERMAL MB CPU 8060B 1 __ 24 346676300008 SPUNGE THERMAL MB HDD 8060B 1 25 1346676300009 INSULATOR KB COVER 8060B 1 JASSEMBLY o 26 370100010853 SPC SCREV MeL2 5 NIW NV 4 27 370102010405 SPC SCREV MeLANIWK HDCO NLK PART 28 1370102020301 SPC SCREW MeL3 NIW K HD 5 PART 29 1370102610405 5 5 M26L4 K HDNIWNLK 5 PART _____ 30 1370102631202 SPC SCREW M2 6L6 K HD NIW NLK 21 PART MeL3 K HEAD NIW 12 PART 1 fASSemBLY 1 I 8 1 ASSEMBLY 1 ASSEMBLY 1 ASSEMBLY i 1 sem iTM41P 311 SYNAP 1 PART 1 assemBy 1 ASSEMBLY j30G FUJITSU MHR2030AT 8 1 ASSEMBLY 43 1531067310008 KBD ASSY GR 8060 1 ASSEMBLY 44 340673100000 ASSY HINGE 8060 1 ASSEMBLY ___ 45 840673100004 _ BRACKET ASSY TP 8060 1 ASSEMBLY ___ 46 346673100086 SPONGE KB L COVER 8060 346673100087 _ SPONGE KB R COVER 8060 1 6 created with FinePrint pdfFactory trial version htt EENT Hay
148. M NOTE ECC error detection is supported by the SCK 2 and SCK 5 signals SCK 5 0 Complementary Differential DDR SDRAM Clock These are the SSTL_2 complimentary differential DDR SDRAM clock signals NOTE ECC error detection is supported by the SCK 2 and SCK 5 signals DVO Hub Input Clocking GCLKIN I Input Clock 66 MHz 3 3 V input clock from external buffer CMOS DVO Hub Interface DVO Clocking DVOBC LK Differential DVO Clock Output These pins provide differential DVOBCLK DVO pair reference clock that can run up to 165 MHz DVOBCLK corresponds to the primary clock out DVOBCLK corresponds to the primary complementary clock out DVOBCLK and DVOBCLK should be left as NC Not Connected if the DVO B port is not implemented Signal Name Type Voltage Description ICLKAP 1 25 V Channel A differential clock pair output true 245 800 MHz LVDS 225 mV ICLKAM 1 25 V Channel differential clock pair output compliment LVDS 225 mV 245 800 MHz IYAP 3 0 1 25 V Channel A differential data pair 3 0 output true 245 800 LVDS 225 mV MHz TYAM 3 0 1 25 V Channel A differential data pair 3 0 output compliment LVDS 225 mV 245 800 MHz 70 8060B N B Maintenance 5 2 Intel 82855GM Memory Controller Hub Odem Dedicated LVDS LCD Flat Panel Interface Signals Continued Digital Video Output C DVOC Port Signals Signal Nam
149. M Power Power supply for System Memory clock buffers VCCASM Power Power supply for System Memory logic running at the core voltage isolated supply not connected to the core Signal Name Type Description Hub Interface HLRCOMP Analog Hub Interface RCOMP This signal is connected to a reference resistor in order to calibrate the buffers PSWING Ref Input buffer VREF Input buffer differential amplifier to determine Analog a high versus low input voltage VCCHL Power Power supply for Hub Interface buffers DVO DVORCOMP Analog Compensation for DVO This signal is used to calibrate the DVO buffers GVREF Ref Input buffer VREF Input buffer differential amplifier to determine Analog a high versus low input voltage VCCDVO Power Power supply for DVO GPIO VCCGPIO Power Power supply for GPIO buffers DAC REFSET Ref Resistor Set Set point resistor for the internal color palette DAC Analog VCCADAC Power Power supply for the DAC VSSADAC Power Ground supply for the DAC LVDS LIBG Analog LVDS reference current signal connected to reference resistor VCCDLVDS Power Digital power supply VCCTXLVDS Power Data Clk Tx power supply VCCALVDS Power Analog power supply VSSALVDS Power Ground supply for LVDS Clocks VCCAHPLL Power Power supply for the Host PLL VCCAGPLL Power Power supply for the Hub DVO PLL VCCADPLLA Power Power supply for the display PLL A VCCADPLLB Power Power supply for the display
150. ONT EDIE T ges 9 ODEVSEL E I RIA 1 RED TROY ur ss 129 0603 TRST 5 4 03 cus our K 010 010 03 n 0603 0603 SOV 507 b I TIT aga U22 BGA GHK 209 alal pa 3 cvsa 1394 ADT CADE onmsesE 2 Fe lt 50 5510058 855885555 xoa 4 38 DOLI 5 36 5 3 3385553 Vik m 5 2 Eu 19 copa 58455525525 soose gt 22 SOS 80200202 22202002017 x 2 4 10 cen 00020002 229253 cc BBE 90660660 SCK ADS TROT 8601601 550660 55 225 8889998 290009999 gt i CADI a ADT 858795 67988 E i OBE O 3 141820 ADU 2 8 CRDTS ce BH cone a 1 an 1 coset is SO BEZIATe d 1 2 con S A o a HZOATE Sit ROB d E CELUCK Lud RIO CONT 5 wg CSTOF 150 TESTO PAR 14 820 DINT B 2 SOREL i eek 4 SERR 14 16 1820 rese gt EOGFIETERO AH FILTERI PERR 141618 H o x 18 FILTERO 14 16 18 20 7 DA CFHAME ROY 146 1620 00887 a a or dun o JRDY 04161820 ADTE ta 22 TADTI e Ro FRAME 14 16 18 20 VCCA cie 0603 CAD20 2
151. Optical Device Supports PIO mode 0 1 2 3 4 and Ultra DMA 33 66 100 1 2 2 9 Read Only Memory BIOS Flash Fully compatible with industry standard software including Windows 2000 amp Windows XP 4Mb Flash BIOS Fully supports APM V1 2 and latest ACPI specification Insyde BIOS core 1 2 2 10 Power Management Features Local standby mode Individual devices such as HDD graphics controller LCD etc CPU Idle mode Including ACPI modes C1 and C2 Suspend mode Including S1 and S3 ACPI modes Fully APM V1 2 compliant Fully ACPI V1 1 compliant Hibernate for Windows 2000 and Windows XP 8060B N B Maintenance Thermal management Fully US EPA Energy Start compliant 1 2 2 11 Keyboard Controller Hitachi H8 3437S 1 2 2 12 Super I O NS PC87393F LPC interface Ultra I O 1 2 2 13 LEDs Indicator HDD amp CDROM amp NUM amp CAP amp SCROLL amp Wireless LAN amp Audio DJ POWER 1 2 2 14 Buttons One Power Button 7 Audio Control Buttons 8060B N B Maintenance 1 2 2 15 Touch Pad Module Synaptics TM41P 350 with two Buttons 1 2 2 16 Audio DJ Seven Audio Control Buttons PLAY_PAUSE NEXT_TRK SCAN_FW PREV_TRK SCAN_RW STOP_EJECT Volume up Digital Volume Control Volume Down Digital Volume Control Power on off Audio DJ Allowing CD play while the notebook is OFF Low power consumption Automatically turn off for CD player idle mo
152. P 1010 S08 18 03 0603 0603 D 18 sov 05 505 20 D 118 o SAB 1 vep 277 5VS A S PAS M E C202 Me Sov SCROLL UP 4202 100M_DFS 1608 1 18 1 02029 SCROLL DOWN CROLL DOWN 1197 2 20Z00M DFS T608 vss WE SCROLL CHULL COM 22021008 DFS 1808 3 28F020 PLCC TOUCH PWR 41 Part Number Have To Change TOUCH DATA 5 aces TOUCA_GND 87151 0707 7 127 47PINAA7PINA A 0603 777 STRAP OPTION XCNF2 XCNFi FUNCTIONALITY x 0 NOBIOS nis cass T je x 1 NORMAL MODE XRDY DISABLE 2 010 010 0 1 0 LATCH MODE XA12 19 XRDY ENABLE ay SOV 1 1 0 LATCH MODE GPIO 10 17 XRDY ENABLE osos osos __ 06030 0 1 1 LATCH MODE XA12 19 XRDY DISABLE 0515 TT T 777 ee 1 1 1 LATCH MODE GPIO 10 17 XRDY DISABLE 14 00 3 8585 P_LPDID 7 23 LADO delusa EEEEI 2 BASE ADDRESS SELECT ar P LPDZ R643 INDEX REGISTER DATA REGISTER LADS PDSIRDATA 48 TES POICLK Lec FeDe MOUNTED POSMSENO LPS 14171820 4 LRESET PDSDRATEO 0608 4 AERE LFRAME PD7MSEN OPEN 2FH d 4j 4 LoRas 810 14 SUS STAT Aos 1 2 LPcPDA PNEXRDY 38 1417820 PCLKRUN CLKRUN GPIO36 SLCT WGATER PORE SLCT 23 14 167
153. P4N USB EHCI Controller NOTE No external resistors are required on these signals The ICH4 integrates 15 pull downs and provides an output driver impedance of 45 which requires no external series resistor 5 0 VO Overcurrent Indicators These signals set corresponding bits in the USB controllers to indicate that an overcurrent condition has occurred USBRBIAS USB Resistor Bias Analog connection point for an external resistor to ground USBRBIAS should be connected to USBRBIAS as close to the resistor as possible USBRBIAS I USB Resistor Bias Complement Analog connection point for an external resistor to ground USBRBIAS should be connected to USBRBIAS as close to the resistor as possible 77 8060B N B Maintenance 5 3 Intel 82801DBM I O Controller Hub 4 Mobile ICH4 M Power Management Interface Signals Signal Name Type Description Power Management Interface Signals Continue THRM I Thermal Alarm This is an active low signal generated by external hardware to start the hardware clock throttling mode The signal can also generate an SMI or an SCI Signal Name Type Description THRMTRIP Thermal Trip When low THRMTRIP indicates that a thermal trip from the processor occurred the ICH4 will immediately transition to a S5 state The ICH4 will not wait for the processor stop grant cycle since the processor has overheated LAN_RST I LAN Reset This signal mus
154. PCPLLGND omi FPCPLLVDD P10 TESTMEMCLK 21 NV31GLM IFPCRSET NV31GLM Pro OxE VIPHOTL R112 2 1 0608 BUS TYPE 0 IFPCIOGND 14 IFPETOVDD FPCIOVDD 7 NV18M 104 2 O 1 0603 ROMA14 qu BE 6a 35 m 29 58074 60 i 0 1 AT03 2 1 1 0603 0603 T ROM 777 ston Document Number 411676300001 ais Thursday June 12 200 oF heat E PDF created with FinePrint pdfFactory trial version http www fineprint com NV18M NV31 MEMA_CLKO R544 68 0603 R44 68 0603 9 MEMA_MA 11 0 0503 w vas 48 lt T MEMA 0 9 MEMA 001 BS mem E Dai Ae nevada ra 092 Me 2 002 45 WEMI NDSS 558 Bas At pos HO HA Da4 bos lt _ gt 0807 0 9 MER MA
155. PIOOGUOYBBTNO 215 cell 5 1 XA12 GPIO1ONOVABTNI RI24 XD7 GPIO07 JOYABTNO 98 1807 079 i XA1IGPIOT JOYBBTN1 DTR2 _BOUT2 id Si 18 XA14IGPIO121JOYAY OTS2 xWREXCNF1 4 DR dens dejoc veo 20 osavs BRE xaisiarioiauovey soure Nous lt G GND os HH 16 6 1400 2 XIOWR XCS14 MTR1 DRATEO Li 16 22 Lam XATTIGPIO18OYAX SIN2 XIORD GPIO37 IRSL2 DR1 Lx Tutor cs 6 XCSO DR1 XDRY GPIO25 I _ Tt_____ gt RoMcs 22 4 pom XA19 DCD2 JOYABTNO GPIO17 p sov 8598 10K 9 8988 0608 2687393 Mitac POFP100_0 5MM MITAC INTERNATIONAL CORP BIOS SUPER I0 TOUCHPAD Document Number e ston 411676300001 Date Thursday June 12 2008 Breet E PDF created with FinePrint pdfFactory trial version http www fineprint com H8 Mode Select Table
156. PLCC32 W29C04 e 284582801044 IC FW82801DBM ICH4 M BGA 421P U507 284583437003 IC H8 F3437S KBD CTRL TQFP 100P a 28631781200 283767630002 28459508100 28630081100 286100393004 28450299600 28630177200 28630185800 28630185800 28630190700 28630199900 28613307800 28630141400 282574164002_ 284501032001 286303301001 _284500202005 286308801006 286308801009 _283466570001 283467540001 _ 28310110002 23456250104 _284563437003 286317812001 _ 289767610002 _284595081001 _286300811001_ _286100393004 236301772001 _286301907001 286301995001 286122078001 _286301414001 IC HA178L12UA VOLT REGULAT OR SC PUS07 IC HYB25D128323CL3 6 DDR SDRAM 4 U2 U5 U503 U504 IC 1CS950810 CK408 CLOCK GEN T IC IM811 MICROPWR VOL SOT 23 4 U23 IC LMV393 DUAL COMPARTOR SSOP 8P IC LP2996 DDR NS PSOP8 SMT C MAX1772 PWM QSOP 28P PU21 CMAXISSS PWM QOP 24P C MAX1858 PWM QSOP 24P C MAX1907A PWM CONTROLLER 40 QF C MAX1999 PWM QSOP 28P C MC33078D LOW NOISE OP AMP SO C MM1414 PROTECTION T SOP 20A PR lo _ 281307085001 _284500034002 2500393001 _284500165001 _286300965001 _ 284567393002 _284504510001 _286309701001 _284500810002 _286300812002 286300831014 ESHTE _286100252001 _286302211004 _273000590117_ _273000590117_ 273000590142 art Number
157. S STAT 9 14 21 1 LK VDU AEN Ba 7 PU Dynamic NVVDD voltage control 4 4 SDATA 4 TL ons Longe lom 8 Thermal monitor 47 010 4 4 0608 0805 alla ae 9 PU TBD 1 380209 50V oj 10 CLKOUT FS D M A STRAP BIT LOGIC 0 LOGIC 1 XTALSSIN a R68 03 4 NO P N 0 STRAPO R92 2 1 0608 Rise 1 1 10P NA E 1 Te 1 R107 2 19 0608 STRAPI i ROC 1 STRAP2 NA 0603 9 NV18M Cra 1101 4Nx32 DDR SDRAM DOS 2 bits dli on low to 2 Teo i m aas SCL 1 2 0608 NV31M T23 1 sot sx 25004 ice ICA SDA Q SSA 13 d I2CBSCL R72 i 2 2K 0603 Pu STRAPS TK Tac ieparxc sci Ag Gesta Rd 2 22k 00s 18 g OA 13 TXOUTU Wi 0 3 um wu 13 TXOUTO TROUTO IERATXDO Age _ 20080 R585 2 22K 0603 NV31M ERE 9 FPAPOT taco Soa Busi ROB TOUTT x cibi RAI 13 TXOUTI a IFPATXDI verno 40K 1 0603 lace RTAS PA 4 1 a di 1 lose FRO le er ior Rg 5 seme 2 AK Lem 13 TOUTS IFPATXD3 Et to ENPBLT B VEPASPELVDD 10 IFPABPLLGND FHS PO zm mem ose ko seul 1 U10 IFPABPLLVDD Gpiog Hi PIO 6
158. SERVICE MANUAL FOR 8060B BY Sissel Diao Repair Technology Research Department EDVD Jun 2003 MITAC gt 8060B N B Maintenance Contents 1 Hardware Engineering Specification cccsccscssccsssccccccccccscccssccccccscosscsccsscccesscccsccess 4 Ld Introduction lei ORIO IAA 4 1 2 System ATchiteclure roper dolore 6 1 3 Electrical Charatte ela ROIO 19 2 System View and Disassenibly RR RR a 29 PN A TER 29 DISassembDE once e DM teak 32 3 Definition amp Location of Connectors Switches 57 Mother Board REM T 57 3 2 Audio DJ Board SEINE QU E NEATIS 60 33 DC to DC Board c ro 61 4 Definition amp Location of Major Components 62 Mother Boar o cp Ea LT 62 5 Pin Description of Major Component 64 5 1 Intel Pentium M Processor 64 5 2 Intel 82855GM Memory Controller Hub 0 004 68 5 3 Intel 82801DBM I O Controller Hub 4 Mobile 4 0 004 74 8060B N B Maintenance Contents 6 System Block Diagramma 82 7 Mamtenance Diagnostics ila 83 7 1
159. Spare Parts List 8 O foe fd emummames O MS LR Partono LT PF OPTION WXGA 15 2 8060B LT PEAU WXGA 15 2 8060B 6504100002 PCB PWA 8060 BATT GAUGE BD ERE 316676300003 PCRPWA 8060 B AUDIO BD 516676300002 PCBPWA 8060 B DD BD Number Description Location S 316676300001 222670820003 222503220001 34 4 4 Pemaosan Lanes sei Lanes pwarwaswormarr prorecriovsy __ pwemweswmamom pwemeswmopms ine fwarwaswonnmmay ST 11167630000 _ PWA PWA 8060B MOTHER BD ee 311676300003 PWAPWA 8060B MOTHER BD ST 4 676300002 PWA PWA 8060B MOT HER BD T U 411673100028 PWA PWA INVERTER BD MSL FOR 8060 MEE 411673100029 PWA PWA INVERTER BD MSL FOR 8060 332810000158 PWR CORD 250VI0A 2P BLK CHINA 15 222400001 271044027101 RES 002 2W 1 2512 SMT PRI PR2 271046257101 RES 025 2W 1 2512 SMT PRC R18 RI8A 271045507101 RES 05 1 2512 SMT PRI7 271044061101 RES 06 2W 1 2512 SMT ae 271002000301 RESO 1 10W 5 0805 SMT 271002000301 RESO 1 10W 5 0805 SMT 271071000002 RESO 1 16W 5 0603 SMT 127 8060B N B Maintenance 9 Spare Parts List 9 R
160. TEST3 must be left unconnected but should have a stuffing option connection to V SS separately using 1 k pull down resisitors THERMDA Other Thermal Diode Anode THERMDC Other Thermal Diode Cathode THERMTRIP The processor protects itself from catastrophic overheating by use of an internal thermal sensor This sensor is set well above the normal operating temperature to ensure that there are no false trips The processor will stop all execution when the junction temperature exceeds approximately 125 C This is signalled to the system by the THERMTRIP Thermal Trip pin TMS I TMS Test Mode Select is a JTAG specification support signal used by debug tools TRDY I TRDY Target Ready is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer TRDY must connect the appropriate pins of both system bus agents TRST I TRST Test Reset resets the Test Access Port TAP logic TRST must be driven low during power on Reset 67 8060B N B Maintenance 5 2 Intel 82855GM Memory Controller Hub Odem Host Interface Signals Host Interface Signals Continue Signal Name Type Description DINV 3 0 VO AGTL Dynamic Bus Inversion Driven along with the HD 63 0 signals Indicates if the associated signals are inverted or not DINV 3 0 are asserted such that the number of data bits driven electrically low
161. VCC 50 VSS 51 VSS 124 DE base HCOMPO amp HCOMP2 should be 5 voc 62 1 56 52 VSS 125 1 Ra 4 ERRE 0468 route with 18 mil width Normal operation VCC 63 vec 52 VSS VSS 126 9 Hue Diss ecu E vec si ves 55 488 5 54 LI 5 128 5 HDEFER 14 DEFER 0498 eliak ee DOSSiBIe 1 HCOMP3 should be not be stuffed VCC_66 vec 55 VSS 56 VSS 128 i5 HTRDY TRDY 050 route with 5 mil width i 67 vec 56 88 57 5 180 0518 VCC 68 VCC 57 VSS 58 VSS 131 HRS 0 2 HIH 0528 i E VCC 69 VCC 58 VSS 59 VSS 132 ASIA 05 A ICPU TESTI 70 Vcc 59 vss_60 55 133 RS2 a BBL 1 S 2 0608 Base vec 60 vss 61 VSS 194 m 0566 recommend pullup TEST vss_62 VSS135 14 Da some 0566 1 ISONA 2 3 3 always RR RA 2 088 IENA perenne 5 138 4 HFERR FERRE 0578 asosa gA gt oeoa S MNA 2 osoacPU TESTS BGA 79_SKTS 8517 6 a 28 0588 VSS 65 VSS 138 Rete bene 050 i VSS 66 VSS 139 Tri DAL sir 0608 0009 67 VSS 140 50 PSI 0814 VSS 88 141 HIGNNE 0628 VSS 6
162. ake sure that your SO DIMM sockets are OK Board level Troubleshooting 3 Then try another known good SO DIMM modules Parts Signals U3 DDR_2 5V Yes U506 0 63 Replace the faulty 1504 MA 0 12 DDRAM module 12 MDQS 0 8 RP3 RP16 R154 0 7 R183 SERA R633 CS 0 3 If your system host bus clock running at ze an 266MHZ then make sure that SO DIMM Replace R150 SCASA module meet require of PC 266 Motherboard RP508 RP521 SWEA HCLK_MCH HCLK_MCH 66M MCH66IN CLK DDR 0 5 CLK_DDR 0 5 Replace the faulty DDRAM module SMBDATA SMBCLK 101 8060B N B Maintenance 8 5 Memory Test Error Extend DDRAM is failure or system hangs up DDR_2 5V e RPSO8 RP521 56 8 J504 CKE 0 3 CS 0 3 CKE 0 1 CS 0 1 MDOSI0 8 MDOSA 0 8 Ps 4 gt _ MD 0 63 MDD 0 63 4 MEM BS 0 1 MEMA BS 0 1 BS 0 1 0 1 gt MA 0 12 MCB 0 7 MAA 0 12 MCBA 0 7 gt SRASA SCASA SWEA MSRAS MSCASA MSWEA Pe gt RP3 RP16 104 CLK_DDR 0 2 CLK DDR 0 2 5 R154 R183 R633 10 gt gt 5 3V U3 9 DDR_2 5V DDR_2 5V i gt gt PE R620 RI64 150 DDR_REF 10K 10K R629 e 1 From 0507 ICH4 M 49 9 BERDM Memory L cess R549 _ SHBDATA e e T 1000P 150 R634
163. al clock to all units and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input VCCSENSE VCCSENSE is an isolated low impedance connection to processor core power VCC It can be used to sense or measure power near the silicon with little noise VID 5 0 VID 5 0 Voltage ID pins are used to support automatic selection of power supply voltages Vcc Unlike some previous generations of processors these are CMOS signals that are driven by the Intel Pentium M processor The voltage supply for these pins must be valid before the VR can supply Vcc to the processor Conversely the VR output must be disabled until the voltage supply for the VID pins becomes valid The VID pins are needed to support the processor voltage specification variations TCK I TCK Test Clock provides the clock input for the processor Test Bus also known as the Test Access Port TDI I TDI Test Data In transfers serial test data into the processor TDI provides the serial input needed for JTAG specification support VSSSENSE VSSSENSE is an isolated low impedance connection to processor core VSS It can be used to sense or measure ground near the silicon with little noise TDO TDO Test Data transfers serial test data out of the processor provides the serial output needed for JTAG specification support TESTI I TEST2 TEST3 TESTI TEST2 and
164. ary IDE connector PDCS3 SDCS3 Primary and Secondary IDE Device Chip Select for 300 Range For ATA control register block This output signal is connected to the corresponding signal on the primary or secondary IDE connector PDA 2 0 Primary and Secondary IDE Device Address These output SDA 2 0 signals are connected to the corresponding signals on the primary or secondary IDE connectors They are used to indicate which byte in either the ATA command block or control block is being addressed Signal Name Type Description PDD 15 0 Primary and Secondary Device Data These signals directly SDD 15 0 drive the corresponding signals on the primary or secondary IDE connector There is a weak internal pull down resistor on PDD 7 and SDD 7 PDDREQ I Primary and Secondary IDE Device DMA Request These input SDDREQ signals are directly driven from the DRQ signals on the primary or secondary IDE connector It is asserted by the IDE device to request a data transfer and used in conjunction with the PCI bus master IDE function and are not associated with any AT compatible DMA channel There is a weak internal pull down resistor on these signals PDDACK Primary and Secondary IDE Device Acknowledge These SDDACK signals directly drive the DAK signals on the primary and secondary IDE connectors Each is asserted by the ICH4 to indicate to IDE DMA slave devices that a given data transfer cycle assertion
165. as NC Not Connected if the signal is NOT used when using internal graphics device DVOBBLANK Flicker Blank or Border Period Indication DVOBBLANK is DVO programmable output pin driven by the GMCH When programmed as a blank period indication this pin indicates active pixels excluding the border When programmed as a border period indication this pin indicates active pixel including the border pixels DVOBBLANK should be left as left as NC Not Connected if not used DVOBFLDSTL I TV Field and Flat Panel Stall Signal This input can be DVO programmed to be either a TV Field input from the TV encoder or Stall input from the flat panel DVOB TV Field Signal When used as a Field input it synchronizes the overlay field with the TV encoder field when the overlay is displaying an interleaved source DVOB Flat Panel Stall Signal When used as the Stall input it indicates that the pixel pipeline should stall one horizontal line The signal changes during horizontal blanking The panel fitting logic when expanding the image vertically uses this DVOBFLDSTL needs to be pulled down if not used DVOB and DVOC Port Common Signals Signal Name Type Description DVOBCINTR I DVOBC Interrupt This pin is used to signal an interrupt typically DVO used to indicate a hot plug or unplug of a digital display ADDID 7 0 I ADDID 7 0 These pins are used to communicate to the Video DVO BIOS when an external
166. border When programmed as a border period indication this pin indicates active pixel including the border pixels DVOCBLANK should be left as left as NC Not Connected if not used DVOCFLDSTL I TV Field and Flat Panel Stall Signal This input can be DVO programmedto be either a TV Field input from the TV encoder or Stall input from the flat panel DVOC TV Field Signal When used as a Field input it synchronizes the overlay field with the TV encoder field when the overlay is displaying an interleaved source DVOC Flat Panel Stall Signal When used as the Stall input it indicates that the pixel pipeline should stall one horizontal line The signal changes during horizontal blanking The panel fitting logic when expanding the image vertically uses this DVOCFLDSTL needs to be pulled down if not used Signal Name Type Description DVOBDI 11 0 DVOB Data This data bus is used to drive 12 bit RGB data on DVO edge of the differential clock signals DVOBCLK and DVOBCLK This provides 24 bits of data per clock period In dual channel mode this provides the lower 12 bits of pixel data DVOBD 11 0 should be left as left as NC Connected if not used DVOBHSYNC Horizontal Sync HSYNC signal for the DVOB interface DVO DVOBHSYNC should be left as left as NC Not Connected if not used DVOBVSYNC Vertical Sync VSYNC signal for DVOB interface DVOBVSYNC should be left as left
167. c 2 e 5 1 P17 Q7 22 2 U22 CARDSPK 2 MMBT3904L gt 225 12 __1202100 24576MHZ 129 1202 100M 3 PCI4510GHK RS 10K bu AGND 22P 3 114 8 11 Audio Failure Audio OUT No sound from speaker after audio driver is installed 5V CD 5V_AMP o D28 EC10QS04 18 3 8 7 gt 4 2205 199 C173 C816 C808 T 0 14 1001 0471 T 0 47 77 5 _ y 5VA q BAT54C 3 9 1 DI L C818 T 0 471 77 MUTE_IN 5V_AMP ra R662 From previous page 100K 2 EAPD 0518 DTCIA4TKA From previous page 77 AOUT_L C821 0 47 R667 SIK 20 AOUT_R C822 0 47 R668 SIK 16 From previous page C195 m 0 47u 19 C815 0 471 7 R669 0 14 VDD PVDDI0 1 6 SE BTL VAUX 0510 HP LINE SHUTDOWN Amplifier TPA0252 LLINE IN RLINE IN LHP IN RHP IN HP LINE 8060B N B Maintenance 13 SPKROUT 1 3VS 3 5 SPD Audio DJ Board e J509 R508 SI2301DS 11 SPKROUT gt 0 5 i Ww 25 _ SPKLOUT i Internal Speaker Connector 2 112 3 8507 600Z 100M L 3
168. ce 31 Function 0 Offset DO bit 13 If FERR is active indicating a coprocessor error a write to the Coprocessor Error Register FOh causes the IGNNE to be asserted IGNNE remains asserted until FERR is negated If FERR is not asserted when the Coprocessor Error Register is written the IGNNE signal is not asserted Speed Strap During the reset sequence ICH4 drives IGNNE high if the corresponding bit is set in the FREQ_STRP register Processor Interface Signals INIT Initialization INIT is asserted by the ICH4 for 16 PCI clocks to reset the processor ICH4 can be configured to support CPU BIST In that case INIT will be active when PCIRST is active Signal Name Type Description A20M Mask 20 A20M will go active based on either setting the appropriate bit in the Port 92h register or based on the A20GATE input being active Speed Strap During the reset sequence ICH4 drives A20M high if the corresponding bit is set in the FREQ_STRP register CPUSLP CPU Sleep This signal puts the processor into a state that saves substantial power compared to Stop Grant state However during that time no snoops occur The ICH4 can optionally assert the CPUSLP signal when going to the S1 M state NMI Non Maskable Interrupt NMI is used to force a non Maskable interrupt to the processor The ICH4 can generate an NMI when either SERR or IOCHK is asserted The processor detects an NMI whe
169. d Pull Down 348 GPIOIZI o NOT Implemented x i GP10122 OD NOT Implemented CPUPERF ES i 204 2 SEIGIZ3 NOT Implemented x i GPIO 24 1 O NOT Implemented PCLKRUN n 9653 0603 f GPIO 25 1 0 RESUME POWER WELI SUSPEND ENABKL ENPBHLT OUTPUT Integrated Pull Up OT 170 RESUME BOWER WELI PCIRST_MSK i GPIO 28 170 RESUME POWER WELI PULL HI 1 0 0 GPIO 32 175 MAIN POWER WELL CMPCIACT I 1 0 5 1 1 GPIO 33 1 0 MAIN POWER WELL MINI_PD Qo ae DTOMATIA 9 2 0 1428 DPRELPVR i 170 MAIN POWER WELL ENREKL MSK 5VS 9 1 GPIO 35 170 MAIN POWER WELL HDD RST i GPIO 36 170 MAIN POWER WELL RST 1 re ls GPIO 37 170 MAIN POWER WELL SPK OFF 00 ENPELT ENPBLT en 170 MAIN POWER WELL x H7 GPIO 39 1 0 MAIN POWER WELL x GPIO 40 1 0 MAIN POWER WELL x GPIO 41 1 0 MAIN POWER WELL x GPIO 42 I O MAIN POWER WELL x GPIO 43 1 0 MAIN POWER WELL x 16 PDD o 15 PODIO 15 3000 19 5000 15 20 STRAPPING AT RISING EDGE OF PWROK PDD 15 50015 PDD 14 80014 STRAPPING PINS FUNCTIONS PDD 12 500 12 RESDOUT SAFE MODE PDD 10 Sop 19 EEDOUT RESERVED 5008 TENTA OP BLOCK SWAP OVERRIDE poDE 5008 DPRSLPVK INTERFACE TERMINATION SCHEME 2004 5004 HUB_LICH_COMP HUB INTERFACE SCHENE I 0 OR 1 5 Li En 3002 NO REBOOT 2000 5000 16 PDIOW PDIOW SDIOW SDIOW 20 16 PDACK PDDACK
170. d as a GPO NOTE This signal will be asserted in S1 M on the ICH4 M SLP_S5 S5 Sleep Control SLP_S5 is for power plane control The signal is used to shut power off to all non critical systems when in the S5 Soft Off states SUSCLK Suspend Clock Output of the RTC generator circuit to use by other chips for refresh clock PWROK Power OK When asserted PWROK is an indication to the ICH4 that core power and PCICLK have been stable for at least 1 ms PWROK can be driven asynchronously When PWROK is negated the ICH4 asserts PCIRST NOTE PWROK must deassert for a minimum of 3 RTC clock periods for the ICH4 to fully reset the power and properly generate the PCIRST output AGPBUSY AGP Bus Busy To support the C3 state This signal is an indication that the AGP device is busy When this signal is asserted the BM_STS bit will be set If this functionality is not needed this signal may be configured as a GPI STP_PCI Stop PCI Clock This signal is an output to the external clock generator for it to turn off the PCI clock Used to support PCI CLKRUN protocol If this functionality is not needed This signal can be configured as a GPO PWRBTN Power Button The Power Button causes SMI or SCI to indicate a system request to go to a sleep state If the system is already in a sleep state this signal causes a wake event If PWRBTN is pressed for more than 4 seconds this causes an unconditional t
171. d on the board However it is recommended that routing channels to these pins on the board be kept open for possible future use Please refer to the platform design guides for more details PREQ Probe Request signal used by debug tools to request debug operation of the processor PROCHOT PROCHOT Processor Hot will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit has been activated if enabled This signal may require voltage translation on the motherboard PSH Processor Power Status Indicator signal This signal is asserted when the processor is in a lower state Deep Sleep and Deeper Sleep SLP SLP Sleep when asserted in Stop Grant state causes the processor to enter the Sleep state During Sleep state the processor stops providing internal clock signals to all units leaving only the Phase Locked Loop PLL still operating Processors in this state will not recognize snoops or interrupts The processor will recognize only assertion of the RESET signal deassertion of SLP and removal of the BCLK input while in Sleep state If SLP is deasserted the processor exits Sleep state and returns to Stop Grant state restarting its internal clock signals to the bus and processor core units If DPSLP is asserted while in the Sleep state the processor will exit the
172. duce power on the Intel Pentium M data bus input buffers DEFER DEFER is asserted by an agent to indicate that a transaction cannot be guaranteed in order completion Assertion of DEFER is normally the responsibility of the addressed memory or Input Output agent This signal must connect the appropriate pins of both processor system bus agents DINV 3 0 IO DINV 3 0 Data Bus Inversion are source synchronous and indicate the polarity of the D 63 0 signals The DINV 3 0 signals are activated when the data on the data bus is inverted The bus agent will invert the data bus signals if more than half the bits within the covered group would change level in the next cycle DINV 3 0 Assignment Data Bus Bus Signal Data Bus Signals DINV 3 D 63 48 it DINV 2 D 47 32 DINV 1 D 31 16 DINV 0 D 15 0 DPSLP FERR PBE FERR Floating point Error PBE Pending Break Event is multiplexed signal and its meaning is qualified by STPCLK When STPCLK is not asserted FERR PBE indicates a floating point when the processor detects an unmasked floating point error FERR is similar to the ERROR signal on the Intel 80387 coprocessor and is included for compatibility with systems using MS DOS type floating point error reporting When STPCLK is asserted an assertion of FERR PBE indicates that the processor has a pending break event waiting for service The assertio
173. e Type Voltage Description ICLKBP 1 25 differential clock pair output true 245 800 MHz LVDS 225 mV ICLKBM 1 25 Channel differential clock pair output compliment 245 LVDS 225 mV 800 MHz IYBP 3 0 1 25 Channel B differential data pair 3 0 output true 245 800 LVDS 225 mV MHz 01 1 25 Channel B differential data pair 3 0 output compliment LVDS 225 mV 245 800 MHz Digital Video Output B DVOB Port Signals Signal Name Type Description DVOCDI11 0 DVOC Data This data bus is used to drive 12 bit RGB data on DVO edge of the differential clock signals DVOCCLK and DVOCCLK This provides 24 bits of data per clock period In dual channel mode this provides the upper 12 bits of pixel data DVOCD 11 0 should be left as left as NC Not Connected if not used DVOCHSYNC Horizontal Sync HSYNC signal for the DVOC interface DVO DVOCHSYNC should be left as left as NC Not Connected if not used DVOCVSYNC Vertical Sync VSYNC signal for DVOC interface DVOCVSYNC should be left as left as NC Not Connected if the signal is NOT used when using internal graphics device DVOCBLANK Flicker Blank or Border Period Indication DVOCBLANK is DVO programmable output pin driven by the GMCH When programmed as a blank period indication this pin indicates active pixels excluding the
174. e section 2 2 1 Disassembly 2 Open the top cover 3 Loosen the four latches locking the keyboard Figure 2 2 Figure 2 2 Loosen the four latches Figure 2 3 Disconnect the cable 4 Slightly lift up the keyboard and disconnect the cable from the mother board then separate the keyboard Figure 2 3 Reassembly 1 Reconnect the keyboard cable and fit the keyboard back into place with four latches 2 Replace the battery pack See section 2 2 1 Reassembly 35 8060B N B Maintenance 2 2 3 HDD Module Disassembly 1 Carefully put the notebook upside down 2 Remove the battery pack See section 2 2 1 Disassembly 3 Remove one screw and slide out the HDD compartment cover Figure 2 4 4 Slide HDD module out from the compartment carefully Figure 2 5 Figure 2 4 Remove HDD module Figure 2 5 Disassemble the hard disk Reassembly 1 Slide the HDD module into the compartment then replace the HDD compartment cover 2 Replace the battery pack See section 2 2 1 Reassembly 36 8060B N B Maintenance 2 2 4 CD DVD ROM Drive Disassembly 1 Carefully put the notebook upside down Remove the battery pack See section 2 2 1 Disassembly 2 Remove the HDD module See section 2 2 3 Disassembly 3 Remove one screw fastening the CD DVD ROM drive Figure 2 6 4 Then insert a small rod such as a straightened paper clip into the drive s manual eject hole and push firmly to release the tray Pull the tray o
175. ed 5V 0511 1538 120Z 100M 3 VOUTO vino vouro SY e L C95 C293 C285 T VOUTI R684 293 L 2 33K 470P 2201 T J20 USBOCO 3 L C846 R683 T 1000 47K Pss 1535 A USBPO 90Z 100M Pas 2 3 L537 120Z 100M VOUTI SYY e c U507 2 R679 291 1 0279 220 gt 33K 470P 2201 6 USBOC2 2 5 L css R678 5 T 1000P 47K 3 Controller Hub USBP2 902 100 IVA AA 4 d 2N Y Ys ICH4 M F502 L507 mircoSMDC110 120Z 100M 5V O A Y Y e 4 R554 cass 82801DBM 33K 470P 2208 16 USBOC4 3 L R61 P23 T 1000P 47K L509 USBP4 90Z 100M gt AAA USBP4 110 8060B N B Maintenance 8 10 PIO Port Test Error When a print command is issued printer prints nothing or garbage PIO Port Test Error 1 Check if PIO device is installed properly J13 Board level 2 Check CMOS LPT port setting properly Troubleshooting One of following parts signals on the motherboard may be defective use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement Parts Signals Correct it 0515 5VS J13 P_LPDO PR504 SUOEBD RP506 Replace the Replace RP522 P LPD2 fault
176. ep 1 to 7of section 2 2 1 Disassembly 3 Remove the audio board and touch pad board See sections 2 2 13 and 2 2 14 Disassembly 4 Remove four screws fastening the touch pad module and disconnect the touch pad s cable to lift up the touch pad module Figure 2 33 Figure 2 34 Remove the top mother board Reassembly 1 Replace the touch pad module and bracket and secure with four screws 2 Reconnect the cables to the board 3 Assemble the notebook See previous sections Reassembly 56 8060B N B Maintenance 3 Definition amp Location of Connectors Switches 3 1 Main Board Side A 1 JA J2 43 JA 5 J6 J7 8 J9 FAN Connector RJ11 Connector Secondary EIDE Connector LCD Connector S Video Connector USB Port Connector Primary EIDE Connector External VGA Connector DC to DC Board Connector J10 Touch pad Connector J12 DDR SO DIMM Module Socket J13 Parallel Port Connector 57 8060B N B Maintenance 3 Definition amp Location of Connectors Switches 3 1 Main Board Side A 2 6 6 6 J14 J15 J16 J18 J19 J20 J21 J22 J23 U26 RTC Battery Connector Internal Keyboard Connector PCMCIA Card Bus Socket LAN RJ45 Connector IEEE1394 Connector USB Port Connector Battery Connector Modem Daughter Board MDC Connector AC Power Jack FIR Module 58 8060B N B Maintenance
177. equired that represents a logical AND of the ICH4 s PWROK and VGATE VRMPWRGD signals DPSLP Deeper Sleep This signal is asserted by the ICH4 to the processor When the signal is low the processor enters the Deeper Sleep state by gating off the processor Core clock inside the processor When the signal is high default the processor is not in the Deeper Sleep state This signal behaves identically to the STP_CPU signal but at the processor voltage level SMBus Interface Signals Signal Name Type Description SMBDATA VOD SMBus Data External pull up is required SMBCLK VOD SMBus Clock External pull up is required SMBALERT I SMBus Alert This signal is used to wake the system or generate GPIO 11 If not used for SMBALERT it can be used as a GPI System Management Interface Signals Signal Name Type Description INTRUDER I Intruder Detect Can be set to disable system if box detected open This signal s status is readable so it can be used like a GPI if the Intruder Detection is not needed SMLINK 1 0 VOD System Management Link SMBus link to optional external system management ASIC or LAN controller External pull ups are required Note that SMLINK 0 corresponds to an SMBus Clock signal and SMLINK 1 corresponds to an SMBus Data signal Signal Name Type Description RTCX1 Special Crystal Input 1 This signal
178. er known good CPU module DIMM module and BIOS 2 Remove all of I O device FDD HDD CD ROM from motherboard except LCD or monitor Check system clock and reset circuit 1 Replace faulty part Yes 2 Connect the I O device to the M B one at a time to find out To be continued which part is causing the problem Clock and reset checking Display OK 8 2 No Display 8060B N B Maintenance System Clock Check Pre PR506 501 38 0 CLK_ENABLE 28 MAX1907 3VCLKPCI 3VCLK66 3VS 3VCLKCPU 3VCLKANA R609 5 10K 23 e 1523 Y Y 120Z 100M 46 50 1525 1702 10 e 8 14 e L12 IX 120Z 100M e 1 26 37 L524 1207 100 19 32 R148 PCICLK_LAN B 11 R149 PCICLK_CARD 10 RISI piu 1507 PCICLK_MINI gt 16 P21 MiniPCI Connector Pn 022 PCMCIA 1394 SE Controller 3 Pig 09 97 2 TE p m 2 LAN Controller 7 VTT_PWRGD Pr U506 Clock Generator ICS950810 43VS FS2 FS1 80 CPUCLK o o 1 100 2 54 FSO R126 IK F o 1 2 52 R610 33 HCLK_CPU gt U1 51 R613 33 f HCLK_CPU gt CPU gt EE R
179. er planes are on 80 8060B N B Maintenance 5 3 Intel 82801DBM I O Controller Hub 4 Mobile ICH4 M Power and Ground Signals Signal Name Description VCC3_3 3 3 V supply for core well I O buffers This power may be shut off in S3 S4 S5 or G3 states AC 97 Link Signals Signal Name Type Description AC_RST AC 97 Reset This signal is a master hardware reset to external Codec s AC SYNC AC 97 Sync This signal is a 48 kHz fixed rate sample sync to the Codec s AC_BIT_CLK I AC97 Bit Clock This signal is a 12 288 MHz serial data clock generated by the external Codec s This signal has an integrated pull down resistor 5 1 5 V supply for core well logic This power may be shut off in S3 S4 55 or G3 states AC SDOUT AC97 Serial Data Out Serial TDM data output to the Codec s NOTE AC_SDOUT is sampled at the rising edge of PWROK as a functional strap VCCHI 1 5 V supply for Hub Interface 1 5 logic 1 8 V supply for Hub Interface 1 0 logic This power may be shut off in S3 S4 S5 or G3 states VSREF Reference for 5 V tolerance on core well inputs This power may be shut off in S3 S4 S5 or G3 states AC SDIN 1 0 I AC97 Serial Data In 2 0 These signals are Serial TDM data inputs from the three Codecs NOTE An integrated pull down resistor on is enabled when either The ACLINK Shutoff bit in the AC 97 Global C
180. ernal 1 777 ME AGND AGND 4 Pull Down 20k AGND R212 40 2KNA 0608 E On Use 14 318MHz external clock R221 27K 0603 AVDDAD R211 47K 0603 R210 47K 0603 5v_0D 1 d R270 cass 4 10V 5 122 028 Ar A E 20 SPKR 1 1 1 K 0603 0 R220NA 0603 Paz 0608 777 120Z 100M 77 1 C205 100504 C199 1 2 50V avs 2012 GND 2012 fond Eun se 0 SOV SOV AGND M ie TE 0009 External Micro Phone Jack SSVLAMP 0515 gt 1 1007 11N H2 ons 1 193 200680 an 1 2 2 2 60 Layout Note 1 ven 1 MUTE_IN 3 c 1445 SPK 0818 4 nA NCS30780 R215 HSETITEESR us mum O47U BATS4C VAUX 3 5 5V 0 7 Bais 0 me Weiss 148 TKA 0608 camo wem AGND 0608 0608 Lose 7 1 220PINA 220PINA as short as possible 777 0603 9603 R217 2 0603 2200 11 1 For 2W speaker AGND AGNI AGNI Rees Internal Speaker Connector zi D B ij AOUT 1 047U 1 Wi i 0603 Amplifier HE EFTERSR W 15 mils 1 9510 gt 6087 H H short as possible i i 0815 0470 16 ALINE IN 13 L 1 LINE OUT R Line OUT R 20 0603 T 1L RHP iN Ht La vo P 1 0470 16 1 5
181. ers are installed properly 1 Try another known good speaker CD ROM 2 Exchange another known good charger board Correct it Correct it Board level Troubleshooting Replace Motherboard Check the following parts for cold solder or one of the following parts on the motherboard may be defective use an oscilloscope to check the following signal or replace parts one at a time and test after each replacement 1 If no sound cause of line out check the following parts amp signals Parts Signals U17 AOUT_R U510 AOUT L J506 DEVICE DECT SPDIFOUT 3VS 5V_AMP 3VS_SPD LINE_OUT_L LINE_OUT_R Audio DJ Board 2 If no sound cause of MIC check the following parts amp signals Parts Signals U17 MIC U13 MIC 2 J505 MIC 3 J506 Audio DJ Board 3 If no sound cause of CD ROM check the following parts amp signals Parts U17 R238 R252 R247 J3 Signals CDROM LEFT RIGHT CDROM COMM 8060B N B Maintenance 8 11 Audio Failure Audio IN No sound from speaker after audio driver is installed
182. fFactory trial version http www fineprint com PD506 a ALWAYS 2 BAVIOLTI ADINP 3 502 i 2 ADNP 1 SH RT SMTI EE 1 2 ADINP_2 SHORT SMTI 06 5 4 1 2 DVMAIN o DVMAIN Pos 06 TPC8107 d J dis sos Posse 28545 2 PR546 Posso PC542 4 7K 80310504 ou 10008 20507 1 0603 0805 0805 PD 0608 0608 50V 50V 50v PR565 LEARNING 1 475K 80310904 NA 22 LEARNING Hm 0 1 PRS66 20503 1M N7002 0603 0723 FET PF2 amp 5AG2VDC PL28 1202 00M 2012 io N 2 777 1 2 23 2DC S107B200 PFI 6 5A 82VDC 12128 pwi 1 2 pw2 1 2 pws 20502 4 4 4 4 1230305 Posso 2697 Posa posa pcg 2012 10 010 9 PUSO6 0603 osos osos 0603 Posez 0505 ESE 50 25 50V 50 sov 50 03U RLZ24B HA S sbelo 88 sov Al 8 o ET 2 E 6 2 1M 1 1 0603 Lvl lwl PR539 PR61 1 1 1 100K Pcs37 1
183. fers continue When the Initiator negates the transaction is in the final data phase 15 an input to the ICH4 when the ICH4 is the Target and is an output from the ICH4 when is the Initiator remains tri stated by the ICH4 until driven by an Initiator STOP Stop STOP indicates that ICH4 as a Target is requesting Initiator to stop the current transaction STOP causes the ICH4 as an Initiator to stop the current transaction STOP is an output when the ICH4 is a Target and an input when the ICH4 is an Initiator STOP is tri stated from the leading edge of PCIRST STOP remains tri stated until driven by the ICH4 IRDY Initiator Ready IRDY indicates the ICH4 s ability as an Initiator to complete the current data phase of the transaction It is used in conjunction with TRDY A data phase is completed on any clock that both IRDY and TRDY are sampled asserted During a write IRDY indicates the ICH4 has valid data present on AD 31 0 During a read it indicates the ICH4 is prepared to latch data IRDY is an input to the ICH4 when the ICH4 is the Target and an output from the ICH4 when the is an Initiator IRDY remains tri stated by the ICH4 until driven by an Initiator PERR VO Parity Error An external PCI device drives PERR when it receives data that has a parity error The ICH4 drives PERR when it detects a parit
184. g parts or signals on the motherboard may be defective use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement U507 5VS R595 HDD_RST RP532 PIORDY PDAI0 2 Motherboard PDCS1 PDIOR PDIOW PDDACK PDDREQ IRQ14 105 8060B N B Maintenance 8 7 Hard Drive Test Error Either an error message is shown or the drive motor spins non stop while reading data from or writing data to hard disk 5VS J7 181 43VS gan e e e 41 42 ES C36 C31 C29 4 7K 8 77 77 77 P15 J PDD 0 15 3 18 R595 HDD_RST 24 BRSTDRVI 1 0507 PIORDY 27 55 d 3 vO PDA 0 2 33 35 36 8 tn Controller PCSI PCS3 3738 Hub PDIOR 25 9 a PDIOW 23 2 ICH4 M PDACK 29 PDDEQ 21 82801DBM IRQ14 e 31 8060B N B Maintenance 8 8 CD ROM Drive Test Error An error message is shown when reading data from CD ROM drive CD ROM Driver Test Error 1 Try another known good compact disk 2 Check install for correctly Board level Troubleshooting One of the following parts or signals on the motherboard may be defective use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement Parts Signals U507 5V_CD U18 SW502 SDD 0 15 U505 SW503 SDA 0 2 J3 SWS504 SCS 1 3 J506 SW505 SDIOW
185. gent keeps BPRI asserted until all of its requests are completed then releases the bus by deasserting BPRI A20M If A20M Address 20 Mask is asserted the processor masks physical address bit 20 A20 before looking up a line in any internal cache and before driving a read write transaction on the bus Asserting A20M emulates the 8086 processor s address wrap around at the 1 Mbyte boundary Assertion of 20 is only supported in real mode 20 is an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction BRO I O BRO is used by the processor to request the bus The arbitration is done between the Intel Pentium M processor Symmetric Agent and the MCH M High Priority Agent of the Intel 855PM or Intel 855GM chipset COMPP3 0 Analog COMP 3 0 must be terminated on the system board using precision 1 tolerance resistors Refer to the platform design guides for more implementation details ADS vO ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 31 3 and REQ 4 0 pins All bus agents observe the ADS activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction ADSTB
186. gnals LOCK Io LOCK indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins of both processor system bus agents For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction to the end of the last transaction When the priority agent asserts BPRI to arbitrate for ownership of the processor system bus it will wait until it observes LOCK deasserted This enables symmetric agents to retain ownership of the processor system bus throughout the bus locked operation and ensure the atomicity of lock RESET Asserting the RESET signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents For a power on Reset RESET must stay active for at least two milliseconds after VCC and BCLK have reached their proper specifications On observing active RESET both system bus agents will deassert their outputs within two clocks All processor straps must be valid within the specified setup time before RESET is deasserted RS 2 0 RS 2 0 Response Status are driven by the response agent the agent responsible for completion of the current transaction and must connect the appropriate pins of both processor system bus agents PRDY Probe Ready signal used by debug tools to determine processor debug readiness RSVD These pins are RESERVED and must be left unconnecte
187. ines or the IDE DMA acknowledge PDDAK or SDDAK Primary and Secondary Disk Stop Ultra DMA ICH4 asserts this signal to terminate a burst 76 8060B N B Maintenance 5 3 Intel 82801DBM I O Controller Hub 4 Mobile ICH4 M IDE Interface Signals Continued Signal Name Type Description PIORDY PDRSTB PWDMA RDY SIORDY SDRSTB SWDMA RDY I Primary and Secondary I O Channel Ready PIO This signal will keep the strobe active PDIOR or SDIOR on reads PDIOW or SDIOW on writes longer than the minimum width It adds wait states to PIO transfers Primary and Secondary Disk Read Strobe Ultra DMA Reads from Disk When reading from disk the ICH4 latches data on rising and falling edges of this signal from the disk Primary and Secondary Disk DMA Ready Ultra DMA Writes to Disk When writing to disk this is de asserted by the disk to pause burst data transfers LPC Interface Signals Signal Name Type Description LAD 3 0 VO LPC Multiplexed Command Address Data For the LAD 3 0 FWH 3 0 signals internal pull ups are provided LFRAME O LPC Frame LFRAMEXZ indicates the start of an LPC cycle or an FWH 4 abort LDRQ 1 0 I LPC Serial DMA Master Request Inputs LDRQ 1 0 are used to request DMA or bus master access These signals are typically connected to an external Super I O device An internal pull up resistor is provided on these signals Inter
188. io Codec TA Internal Speaker PCI4510 HDD ICH4 M ar Amplifier SPDIF JACK 2 E Intel 82801DBM 5 RIAM Jack 015 09 S 5 M D C e Power LAN PHY 9 RTL8101L 5 Switch FAN ISA Bus IR Module 515 U18 Power Button Super I O i PCMCIA MINI CRETESE Micro CARDBUS 1394 RJ 45 Jack Aene PC87393 U12 Controller Touch Pad Socket Flash ROM H8 3437S dM Keyboard 8060B N B Maintenance 7 Maintenance Diagnostics 7 1 Introduction Each time the computer is turned on the system bios runs a series of internal checks on the hardware This power on self test post allows the computer to detect problems as early as the power on stage Error messages of post can alert you to the problems of your computer If an error is detected during these tests you will see an error message displayed on the screen If the error occurs before the display is initialized then the screen cannot display the error message Error codes or system beeps are used to identify a post error that occurs when the screen is not available The value for the diagnostic port 378H is written at the beginning of the test Therefore if the test failed the user can determine where the problem occurred by reading the last value written to port 378H by the 378H port debug board plug at PIO Port or Mini PCI Slot 83 8060B N B Maintenance 7 2 Error Codes Following is a list of error codes in sequent display on the PIO debug board m n
189. is connected to the 32 768 kHz crystal RTCX2 Special Crystal Input 2 This signal is connected to the 32 768 kHz crystal Other Clock Signals Signal Name Type Description CLK14 I Oscillator Clock Used for 8254 timers It runs at 14 31818 MHz This clock is permitted to stop during S1 M or lower states CLK48 I 48 MHz Clock This clock is used to run the USB controller It runs at 48 MHz This clock is permitted to stop during S1 M or lower States CLK66 I 66 MHz Clock This is used to run the hub interface It runs at 66 MHz This clock is permitted to stop during S1 M or lower states Miscellaneous Signals Signal Name Type Description SPKR Speaker The SPKR signal is the output of counter 2 and is internally ANDed with Port 61h bit 1 to provide Speaker Data Enable This signal drives an external speaker driver device which in turn drives the system speaker Upon PCIRST its output state is 0 NOTE SPKR is sampled at the rising edge of PWROK as functional strap RTCRST I RTC Reset When asserted this signal resets register bits in the RTC well and sets the RTC_PWR_STS bit bit 2 in register NOTES 1 Clearing CMOS in an ICH4 based platform can be done by using a jumper on RTCRST or GPI or using SAFEMODE strap Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low 2 Unless entering the XOR Chain Test Mode the RTCRST input must always be high when all other RTC pow
190. is signal is CRT Analog video Analog from the internal color palette DAC The DAC is designed for a 37 5 ohm equivalent load on each pin e g 75 ohm resistor on the board in parallel with the 75 ohm CRT load BLUE Blue Analog Output Tied to ground Analog GPIO Signals GPIO I F Total Type Comments RSTIN I Reset Primary Reset Connected to PCIRST of ICH4 M CMOS PWROK I Power OK Indicates that power to GMCH is stable CMOS AGPBUSY AGPBUSY Output of the GMCH IGD to the ICH4 M which CMOS indicates that certain graphics activity is taking place It will indicate to the ACPI software not to enter the C3 state It will also cause a C3 C4 exit if C3 C4 was being entered or was already entered when AGPBUSY went active Not active when IGD is in any ACPI state other than DO EXTTS 0 I External Thermal Sensor Input This signal is an active low input CMOS to the GMCH and is used to monitor the thermal condition around the System Memory and is used for triggering a read throttle The GMCH can be optionally programmed to send a SERR SCI or SMI message to the ICH4 M upon the triggering of this signal GPIO I F Total Type Comments LCLKCTLA SSC Chip Clock Control be used to control an external clock CMOS chip with SSC control LCLKCTLB SSC Chip Data Control Can be used to control an external clock CMOS chip for SSC control PANELVDDEN LVDS LCD Flat Panel Power Control This signal is
191. mbly 1 Reconnect the cable to the modem card and secure the modem card with two screw 2 Assemble the notebook See previous sections Reassembly SI 8060B N B Maintenance 2 2 12 D D Board Disassembly 1 Remove the battery pack keyboard HDD module CD DVD ROM drive and LCD assembly See sections 2 2 1 to 2 2 6 Disassembly 2 Remove the mother board ASSY See the step 1 to 7of section 2 2 1 Disassembly 3 Rock the D D board to detach from the mother board Figure 2 28 Figure 2 28 Detach the D D Board Reassembly 1 Insert the D D board s pins into the connector Then push it down and ensure every pin insert well 2 Assemble the notebook See previous sections Reassembly 52 8060B N B Maintenance 2 2 13 Mother Board Disassembly 1 Remove the battery pack keyboard HDD module CD DVD ROM drive and LCD assembly See sections 2 2 1 to 2 2 6 Disassembly 2 Remove the heatsink CPU SO DIMM modem card D D board See section 2 2 9 to 2 2 12 Disassembly 3 Rock the D D board to detach from the mother board Figure 2 29 Figure 2 29 Detach the mother Board Reassembly 1 Replace the D D Board modem card CPU heatsink See section 2 2 12 to 2 2 9 Reassembly 2 Assemble the notebook See previous sections Reassembly 53 8060B N B Maintenance 2 2 14 Audio Board Disassembly 1 Remove the battery pack keyboard HDD module CD DVD ROM drive and LCD assembly See sections 2
192. mom CLK T DDRS PES TEK DDR 8 3 4 i ibl 8 CLK_DDRS TEK DORT K23 scs sck 2 pE24 CLK DDR2 8 DDR SMRCOMP as wide a trace as possible M CU DOR TER DOR dis soks pay Gu Dore e CLK DDRS ri Minimum of 12 mils wide and isolated from X DDR5 vera Let 4 8 DDR2 9A soke Sckes plas 1 E 1 CLK_DDRS 8 other signals with a minimum of 10 mils spacing 8 188 8 DDRO SCKo surcome a DOR SMRCOMP 3 x SRASA CERES 1 DDR 25V PES smse ACVENING PSI ga probatori taro BI 8 SCASA 880 soas RCVENOUT Ai atea 8 SWEA a DDR REF gi PAPAE T x T HUB MCH VREF signal less 3 Testa 181 m RSVD1 MDQSO 0603 Tests 30080 eag moast SMVREF input is 10mA 1 1 RSVD3 50051 MD MDOS1 8 pi REEE ss es c RSVDS 00 182 Rsvos Spasa DI 0054 8 pe 9 Tes O 1 822 Rsvo7 Spass 2 DUE 0055 8 ret 150 tes C 27 30056 DOSE 0 0608 0608 0603 0608 18027 spas LES 0057 8 507 507 1 m 50058 MDOSB 8 4 HOPWR DPWRE 4 14 HOPSLP DPSLP ODEM BGA568_25 MITAC Odem 2 2 ize Document ev Pustom DOCUMENT 411676300001 011 0 Thursday June 12 2003 presi of 1 PDF created with FinePri
193. n it detects a rising edge on NMI NMI is reset by setting the corresponding NMI source enable disable bit in the NMI Status and Control Register Speed Strap During the reset sequence ICH4 drives NMI high if the corresponding bit is set in the FREQ_STRP register SMI System Management Interrupt SMI is an active low output synchronous to PCICLK It is asserted by the ICH4 in response to one of many enabled hardware or software events FERR I Numeric Coprocessor Error This signal is tied to the coprocessor error signal on the processor FERR is only used if the ICH4 coprocessor error reporting function is enabled in the General Control Register Device 31 Function 0 Offset DO bit 13 If FERR is asserted the ICH4 generates an internal IRQ13 to its interrupt controller unit It is also used to gate the IGNNE signal to ensure that IGNNE is not asserted to the processor unless FERR is active FERR requires an external weak pull up to ensure a high level when the coprocessor error function is disabled NOTE FERR can be used in some states for notification by the processor of pending interrupt events This functionality is independent of the General Control Register bit setting STPCLK Stop Clock Request STPCLK is an active low output synchronous to PCICLK It is asserted by the ICH4 in response to one of many hardware or software events When the processor samples STPCLK asserted it responds by stopping its in
194. n of FERR PBE indicates that the processor should be returned to the Normal state When FERR PBE is asserted indicating a break event it will remain asserted until STPCLK is deasserted Assertion of PREQ when STPCLK is active will also cause an FERR break event GTLREF I GTLREF determines the signal reference level for AGTL input pins GTLREF should be set at 2 3 vcce GTLREF is used by the AGTL receivers to determine if a signal is a logical 0 or logical 1 DPSLP when asserted on the platform causes the processor to transition from the Sleep state to the Deep Sleep state In order to return to the Sleep state DPSLP must be deasserted DPSLP is driven by the ICH4 M component and also connects to the MCH M component of the Intel 855PM or Intel 855GM chipset HIT HITM HIT Snoop and HITM Modified convey transaction snoop operation results Either system bus agent may assert both HIT and HITM together to indicate that it requires a snoop stall which be continued by reasserting HIT and HITM together DRDY vo DRDY Data Ready is asserted by the data driver on each data transfer indicating valid data on the data bus In a multi common clock data transfer DRDY may be deasserted to insert idle clocks This signal must connect the appropriate pins of both processor system bus agents IERR Internal Error is asserted by processor as the result
195. ne logic VGATE VRMPWRGD VGATE VRM Power Good VGATE VRMPWRGD is used for Intel SpeedStep technology support This is an output from the processor s voltage regulator to indicate that the voltage is stable This signal may go inactive during an Intel SpeedStep transition 78 8060B N B Maintenance 5 3 Intel 82801DBM I O Controller Hub 4 Mobile ICH4 M Power Management Interface Signals Continued Processor Interface Signals Continue Signal Name Type Description Signal Name Type Description DPRSLPVR Deeper Sleep Voltage Regulator This signal is used to lower the voltage of VRM during C4 and S1 M states When the signal is high the voltage regulator outputs the lower Deeper Sleep voltage When the signal is low default the voltage regulator outputs the higher Normal voltage During PCIRST the output driver is disabled and an internal pull down is enabled This is needed for implementing a strap on the pin When PCIRST deasserts the output driver is enabled To guarantee no glitches on the DPRSLPVR pin the pull down is disabled after the output driver is fully enabled NOTE DPRSLPVR is sampled at the rising edge of PWROK as a functional strap IGNNE O Ignore Numeric Error This signal is connected to the ignore error pin on the processor IGNNE is only used if the ICH4 coprocessor error reporting function is enabled in the General Control Register Devi
196. near on USB 4PX2 DIP 1 disce 1 USB pini 071 1 Ewen T Lep i Js ere Tr P ick LI SHORT SMT4 zd i 33K ND t ag E 0608 SNE GUE See same power 777 777 242 4 pin 30 mil 05 GND USB 414 a 15 USBP2 15 useoce C 5806 HANDI 1 2038036 0371038 ba E SNES TL oes m 3 3 a useapxi From 3VS to VCC3_IR cede power plane to GND 0603 0603 Jos oso T J 4 Module 014 015 play two grain MUR MI i BE 77 1B Made Select 2 same power GND_USB GND_USB IRMODEO IRMODE1 FIRSEL RX Function TX Function 1 pin 30 15 USBP2 T 2 im 4 T R01 Low x Shutdown Shutdown 9 7 21 IRRX IRRX 4 Low Low Low Full Distance Power 41508 Res 27 21 RTX Tx 9 1 lt gt 1 10 Reso 2 C275 cara i Reso e Resi ar care Low LOW SIR 2 3 Distance Power NOEL amp 0603 4 HI LOW SIR 1 3 Distance Power Caso TSQUINA Sov Sov 100 01U 7243 501 3602 1206 0603 63V m Low Low HI MIR FIR Full Distance Power 1504 3 16 oy 1 i We Low HI MIR FIR 2 3 Distance Power Fortuna 77 Hi MIR FIR 1 3 Distance Power GND AR Bison Document 411676800001 IR Mode Select vate Thursday June 12 200 Brest DI E 5 z E z PDF created with FinePrint pd
197. nput for Analog address signals of the Host AGTL Interface This signal is connected to the input buffer differential amplifier to determine a high versus low input voltage HCCVREF Ref Host Common Clock Command input buffer VREF Reference Analog voltage input for the common clock signals of the Host AGTL Interface This signal is connected to the input buffer differential amplifier to determine a high versus low input voltage VTTLF Power PSB Power Supply VTTLF is the low frequency connection from the board This signal is the primary connection of power for GMCH VTTHF Power PSB Power Supply VTTHF is the high frequency supply It is for direct connection from an internal package plane to a capacitor placed immediately adjacent to the GMCH NOTE Not to be connected to power rail System Memory SMRCOMP Analog System Memory RCOMP This signal is used to calibrate the memory I O buffers SMVREF 0 Ref Memory Reference Voltage Input buffer VREF Reference Analog voltage input for Memory Interface Input buffer differential amplifier to determine a high versus low input voltage SMVSWINGH Ref RCOMP reference voltage This is connected to the RCOMP Analog buffer differential amplifier and is used to calibrate the I O buffers SMVSWINGL Ref RCOMP reference voltage This is connected to the RCOMP Analog buffer differential amplifier and is used to calibrate the I O buffers VCCSM Power Power supply for Memory I O VCCQS
198. nt pdfFactory trial version http www fineprint com says E aVOLKCPU 4 2 FS2 FS1 FSO CPUCLK AAA 2012 J J J C733 C732 C728 0 0 i 100MHZ 010 010 220 osos 080 1 2 uN Tere 0 1 1 133MHZ 4 JP ROB 1 USO acti 2 34M ICH SEO Lum mum en Layout note Place crystal within 9506 060 m A 1525 500 mils of CLK Gen 2 y 4eMHz use 9 I 2 6 NTwo 49 9 PULL LOW AS CLOSE 5 al DOT 88 7AS PISSOBLE TO AAA RI27 0 mus 2012 TKINAS io baa MEDATR Aes 3ves cH Bux eno DL eue TL cras 0608 814 SMBCLK OLR 88 CPU 4 NTwo 49 9 PULL LOW AS CLOSE 0608 0808 so HOKCPU 4 7AS PISSOBLE TO CPU 50V 50V 50V 480 2096 250 FSO R610 i 55 Egi CPUCLKTO 52 1 2 2 3 _ 1605 RI34 160
199. nted GPIO 25 yo Can be input or output Resume power well Unmuxed GPIO 24 18 vO Not Implemented in Mobile Assign to native Functionality GPIO 17 16 Fixed as Output only Main power well Can be used instead as PC PCI GNT A B GPIO 17 can also alternatively be used for PCI GNT 5 Integrated pull up resistor VCCLANI_5 1 5 V supply for LAN Controller logic This is a separate power plane that may or may not be powered in S3 S5 states depending upon the presence or absence of AC power and network connectivity This plane must be on in S0 and S1 M VCCRTC 3 3 V can drop to 2 0 V min in G3 state supply for the RTC well This power is not expected to be shut off unless the RTC battery is removed or completely drained NOTE Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low Clearing CMOS in an ICH4 based platform can be done by using a jumper on RTCRST or GPI or using SAFEMODE strap VCCPLL 1 5 V supply for core well logic This signal is used for the USB PLL This power may be shut off in S3 S4 S5 or G3 states VBIAS RTC well bias voltage The DC reference voltage applied to this pin sets a current that is mirrored throughout the oscillator and buffer circuitry GPIO 15 14 I Not implemented GPIO 13 12 I Fixed as Input only Resume power well Unmuxed GPIO 11 I Fixed as Input only Resume power well Can be used instead as SMBAL
200. of DIOR or DIOW is a DMA data transfer cycle This signal is used in conjunction with the PCI bus master IDE function and are not associated with any AT compatible DMA channel PDIOR Primary and Secondary Disk I O Read and Non Ultra PDWSTB PRDMA DMA This is the command to the IDE device that it may drive RDY data onto the PDD or SDD lines Data is latched by the ICH4 on the deassertion edge of PDIOR or SDIOR The IDE device is SDIOR selected either by the ATA register file chip selects PDCS Hf or SDWSTB SRDMA SDCS1 PDCS3 or SDCS3 and the PDA or SDA lines or the RDY IDE DMA acknowledge PDDAK or SDDAK Primary and Secondary Disk Write Strobe Ultra DMA Writes to Disk This is the data write strobe for writes to disk When writing to disk ICH4 drives valid data on rising and falling edges of PDWSTB or SDWSTB Primary and Secondary Disk DMA Ready Ultra DMA Reads from Disk This is the DMA ready for reads from disk When reading from disk ICH4 deasserts PRDMARDY or SRDMARDY to pause burst data transfers PDIOW Primary and Secondary Disk I O Write Non Ultra PDSTOP DMA This is the command to the IDE device that it may latch data from the PDD or SDD lines Data is latched by the IDE device SDIOW on the deassertion edge of PDIOW or SDIOW The IDE device is SDSTOP selected either by the ATA register file chip selects PDCS1 or SDCS1 PDCS3 or SDCS3 and the PDA or SDA l
201. of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the processor system bus This transaction may optionally be converted to an external error signal e g NMI by system core logic The processor will keep IERR asserted until the assertion of RESET BINIT or INIT DSTBN 3 0 TO Data strobe used to latch in D 63 0 Signals Associated Strobe D 15 0 DINV O DSTBN 0 D 31 16 DINV 1 DSTBN I D 47 32 DINV 2 DSTBN 2 D 63 48 DINV 3 DSTBN 3 Fe te HE DSTBP 3 0 Io Data strobe used to latch in D 63 0 Signals Associated Strobe D 15 0 DINV 0 DSTBP 0 D 31 16 DINV 1 DSTBP 1 D 47 32 DINV 2 DSTBP 2 D 63 48 DINV 3 DSTBP 3 IGNNE I IGNNE Ignore Numeric Error is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating point instructions If IGNNE is deasserted the processor generates an exception on a noncontrol floating point instruction if a previous floating point instruction caused an error IGNNE has no effect when the NE bit in control register 0 CRO is set is an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction REQ 4 0 REQ 4 0
202. ontrol Register is set to 1 or Both Function 5 and Function 6 of Device 31 are disabled Otherwise the integrated pull down resistor is disabled General Purpose I O Signals HIREF Analog Input Expected voltages are 0 9 V for HI 1 0 Normal Hub Interface Series Termination 350 mV for HI 1 5 Enhanced Hub Interface Parallel Termination This power is shut off in S3 S4 S5 and G3 states VCCSUS3 3 3 3 V supply for resume well I O buffers This power is not expected to be shut off unless the main battery is removed or completely drained and AC power is not available VCCSUSI 5 1 5 V supply for resume well logic This power is not expected to be shut off unless the main battery is removed or completely drained and AC power is not available VSREF_SUS Reference for 5 V tolerance on resume well inputs This power is not expected to be shut off unless the main battery is removed or completely drained and AC power is not available VCCLAN3_3 3 3 V supply for LAN Connect interface buffers This is a separate power plane that may or may not be powered in S3 S5 states depending upon the presence or absence of AC power and network connectivity This plane must be on in S0 and S1 M Signal Name Type Description GPIO 43 32 yo Can be input or output Main power well GPIO 31 29 Not implemented GPIO 28 27 yo Can be input or output Resume power well Unmuxed GPIO 26 VO Not impleme
203. ovrr DYODII T ze 470P 77 5 x x des eines GL NOU ass puoi PN m ME DACB RSET 27MHZL m DIL 10 ovovoDa te aca uve vuoi oan NUI piovono o Ness DRE ea 15 veg iss DACEMREF ABE vnEF d 2 XTALSOUTEUFF PE s DvoVDDQ gt NET D DACBVDD XTALOUTBUFF 976 Ilem 1558 ace 4 DACB 15 0603 1 VREF 1202 100 se 25V 10 1 VREF 20 AG sigur XTALSSIN 06030 x 1608 Qm ossi 07210 pu op xtatssin AIZ n E ovoon NEUE 4 H RA DVOCAL_PU_GNI 23 21556 i 0603 0603 0603 77 i NR BER close BGA602 64 35 1MM NC 25 5 2X 64 28 5 ine NO P N Hg T 022 777 5 G20 NG_29 HEX Lio lor X D3 Ned NG_90 Mex PLLVDD 1K De 4 NC 3i 720210011 1608 XB NC 6 NC32 124 Clos ceul 2228 NC 7 NC 38 Ge Ga GPIO DEFAULT USAGE 7 Noose E19 NC A osos oS 008 1 STATE NOt 9603 77 Nc 10 80 209 g 0 PD Spread spectrum control 88 2 SMS wc 2 neg FBZ d PD Hot plug unplug NGS Nes LIZ x 2 PD Panel backlight enable NOB a an BGASO2_64_35_1 4 3 PD Panel power enable 4 PD TBD 3VS 0603 5 Spread spectrum control E 6 PU HW suspend 8153 XTALSOUTBUFF 1 i 8 SUS_STAT SU
204. r These signals have integrated weak pull up resistors LAN TXD 2 0 Transmit Data The integrated LAN Controller uses these signals to transfer data and control information to the LAN Connect component LAN_RSTSYNC LAN Reset Sync The LAN Connect component s Reset and Sync signals are multiplexed onto this pin EEPROM Interface Signals Signal Name Type Description EE_SHCLK O EEPROM Shift Clock Serial shift clock output to the EEPROM EE_DIN I EEPROM Data In Transfers data from the EEPROM to the ICH3 This signal has an integrated pull up resistor EE_DOUT EEPROM Data Out Transfers data from the ICH3 to the EEPROM EE_CS Chip Select Chip select signal to the EEPROM Signal Name Type Description FWH 3 0 Io Firmware Hub Signals Muxed with LPC address signals LAD 3 0 FWH 4 LFRAME Firmware Hub Signals Muxed with LPC LFRAME LFRAME signal PCI Interface Signals Signal Name Type Description AD 31 0 IO PCI Address Data AD 31 0 is a multiplexed address and data bus During the first clock of a transaction AD 31 0 contain a physical address 32 bits During subsequent clocks AD 31 0 contain data The ICH4 drives all 0s on AD 31 0 during the address phase of all PCI Special Cycles C BE 3 0 vO Bus Command and Byte Enables The command and byte enable signals are multiplexed on the same PCI pins During the address phase of a transaction C BE 3
205. ransition power button override to the S5 state with only the PWRBTN available as a wake event Override occurs even if the system is in the S1 M S4 states This signal has an internal pull up resistor STP_CPU Stop CPU Clock Output to the external clock generator for it to turn off the processor clock Used to support the C3 state If this functionality is not needed this signal can be configured as a GPO BATLOW Battery Low This signal is an input from the battery to indicate that there is insufficient power to boot the system Assertion will prevent wake from S1 M S5 state Can also be enabled to cause an SMI when asserted Ring Indicate This signal is an input from the modem interface It can be enabled as a wake event and this is preserved across power failures CPUPERF OD CPU Performance is used for Intel SpeedStep technology support The signal selects which power state to put the processor in SYS_RESET System Reset This pin forces an internal reset after being debounced The ICH4 will reset immediately if the SMBus is idle otherwise it will wait up to 25 ms 2 ms for the SMBus to idle before forcing a reset on the system SSMUXSEL SpeedStep Mux Select SSMUXSEL is used for Intel SpeedStep technology support The signal selects the voltage level for the processor RSMRST Resume Well Reset This signal is used for resetting the resume power pla
206. re than 5 minutes 8060B N B Maintenance 1 2 2 17 MODEM MDC Option Pin Signal Name Pn Signal Name NC MONO_OUT NC MODEM_SPK NC NC NC GND NC 5V NC NC NC NC GND Pull Up to 3V 3V 5V GND GND 3V ACSYNC ACSDOUT MSDIN ACRST MSDIN GND GND GND ACBITCLK Table 10 Modem Daughter Board Connector 1 2 2 18 Mini PCI MiniPCI Specification V1 0 802 11b wireless LAN optional with built in Antenna 8060B N B Maintenance 1 3 Electrical Characteristic 1 3 1 Power On Sequence Plug in AC Adapter or Main Battery CPU 11 H_PWRGD 4 4 Banias VDMAIN H8_RESET 13 HCPURST IMP811 4 DC DC PWN 3VA Controller RTC lt 12 PCIRST Press Power Button MARTI gt 5V 3V Odem i v 1 POWERBTN MOSFET 6 SUSB gt MOSFET vibe 12VS 5VS 43VS 4 5 PWRBTN Embeded Controller 6 SUSC 5VA 12 PCIRS H8 3437S eg PWN 6 6 SUSB ADI ON Controller ICHAM P MAX1858 PI 2 PWR_ON 5 82801DBM 4 RSMRST Si leg it Audio
207. resistors are not required on these signals If pull ups are used they should be tied to the 3 3 power rail GNT B GNT 5 GPIO 17 has internal pull up PAR Io Calculated Checked Parity PAR uses even parity calculated on 36 bits AD 31 0 plus C BE 3 0 Even parity means that the ICH4 counts the number of 1s within the 36 bits plus PAR and the sum is always even The ICH4 always calculates PAR on 36 bits regardless of the valid byte enables The ICH4 generates PAR for address and data phases and only guarantees PAR to be valid one PCI clock after the corresponding address or data phase The ICH4 drives and tri states PAR identically to the AD 31 0 lines except that the ICH4 delays PAR by exactly one PCI clock PAR is an output during the address phase delayed one clock for all ICH4 initiated transactions PAR is an output during the data phase delayed one clock when the ICH4 is the Initiator of a PCI write transaction and when it is the Target of a read transaction ICH4 checks parity when it is the Target of a PCI write transaction If a parity error is detected the ICH4 will set the appropriate internal status bits and has the option to generate an NMI or SMI PCICLK PCI Clock This is a 33 MHz clock PCICLK provides timing for all transactions on the PCI Bus NOTE This clock does not stop based STP_PCI signal PCICLK only stops based on SLP_S1 or SLP_S3 PCIRST PCI Reset ICH4 a
208. roups in the DDR SDRAM are masked There is one SDM for every eight data lines SDM can be sampled on both edges of the data strobes NOTE ECC error detection is supported by the SDM 8 signal RCVENOUT SSTL_2 Clock Output Reserved NC Signal Name Type Description SCS 3 0 Chip Select These pins select the particular DDR SDRAM SSTL_2 components during the active state Note There is one SCS per DDR SDRAM Physical SO DIMM device row These signals can be toggled on every rising System Memory Clock edge SMA 12 0 Multiplexed Memory Address These signals are used to provide SSTL 2 the multiplexed row and column address to DDR SDRAM SBA 1 0 Bank Select Memory Bank Address These signals define which SSTL 2 banks are selected within each DDR SDRAM row SMA and SBA signals combine to address every possible location within a DDR SDRAM device SRAS DDR Row Address Strobe SRAS may be heavily loaded and SSTL 2 twO DDR SDRAM clock cycles for setup time to the DDR SDRAMs Used with SCAS and SWE along with SCS to define the System Memory commands SCAS DDR Column Address Strobe SCAS may be heavily loaded SSTL 2 two clock cycles for setup time to the DDR SDRAMs Used with SRAS and SWE along with SCS to define the System Memory commands RCVENIN SSTL_2 Clock Input Reserved NC 69 8060B N B Maintenance 5 2 Intel 828
209. rupt Signals USB Interface Signals Signal Name Type Description SERIRQ vO Serial Interrupt Request This pin implements the serial interrupt protocol VOD PCI Interrupt Requests In Non APIC Mode the PIRQx signals can be routed to interrupts 3 4 5 6 7 9 10 11 12 14 or 15 as described in the Interrupt Steering section Each PIRQx line has a separate Route Control Register In APIC mode these signals are connected to the internal I O APIC in the following fashion PIRQ A is connected to IRQ16 PIRQ B to IRQ17 PIRQ C to IRQ18 and PIRQ D to IRQ19 This frees the legacy interrupts PIRQ H E GPIO 5 2 VOD PCI Interrupt Requests In Non APIC Mode the PIRQx signals can be routed to interrupts 3 4 5 6 7 9 10 11 12 14 or 15 as described in the Interrupt Steering section Each PIRQx line has a separate Route Control Register In APIC mode these signals are connected to the internal I O APIC in the following fashion PIRQ E is connected to IRQ20 PIRQ F to IRQ21 PIRQ G to IRQ22 and PIRQ H to IRQ23 This frees the legacy interrupts If not needed for interrupts these signals can be used as GPIO IRQ 14 15 Interrupt Request 14 15 These interrupt inputs are connected to the IDE drives IRQ14 is used by the drives connected to the Primary controller and IRQ15 is used by the drives connected to the Secondary controller
210. ry trial version http www fineprint com BLOCK DIAGRAM OF THE 8060B PWR_ON CHARGING I_LIMIT PWM DDR_2 5V v Diode D VMAIN ADAPTOR Protector learning Discharge Battery Switch SUSB Charge IC MAX1772 SWITCH v ds 514800 1 5VS DDR DC to DC Converter Requlator 1858 0 4 514800 5 431 SWITCH AGP_MEM2 5 gt 100 LP2996 514800 e 125V 3VS Ec max1999 ay susB T T Shut Down 3 3V DC to DC Convertor 5VS 45V e 1 LSV DC to DC Convertor MOSFET 12VS Shut Down CPU_CORE Vcc Core DC to DC Convertor MAX1907 5V_CD 1 35VS DDR DC to DC Converter SWITCH 1858 VCCP 514800 DDR to DC Converter n MAX1858 E CHARGE SWITCH MUST BE MEET ICH2 POWER ON SEQUENCE 3V O 1 5V Regulator AME8801LEEV 3VS 2 8VS Regulator AME8801CEEV Li ovp PDF created with FinePrint pdfFactory trial version http www fineprint com
211. s TXD Pig 9 PJRX 3 71 3 e 16 PJTX 8 R700 x 0 14 PJTX 7 7 R699 U11 R708 R245 c 0 75 75 gt 68 RXIN e 6 15 e 7 1 2 5 PH163112 Q 67 RXIN e 8 R707 R250 75 75 R698 10 PM 45 8 R605 R599 0 S 49 9 49 9 rum L m 1000P L co26 7 77 L_AGND GND 45 ZT L AGND 61 R203 R204 22 60 3 R226 e 1 gt L527 0 4 172 xi T P T 10 si L_AGND GND 45 E YA 77 117 8060B N B Maintenance 8 13 PC Card Socket and IEEE1394 Failure An error occurs when a PC card device or 1394 device is installed PC Card Socket and IEEE1394 Failure 1 Check if the PC CARD or 1394 device Check the following parts for cold solder or one of the following is installed properly Board level parts on the mother board may be defective use an oscilloscope 2 Confirm PC card or 1394 driver is Troubleshooting to check the following signal or replace the parts one at a time and installed ok test after each replacement Parts Signals U22 VCCENI SUSB 015 SUPDBN PCIRST No J16 PCI GNTO 719 VEEBNT PCI REQO Try another known good PC card or Replace AD 0 31 INTE 1394 device Motherboard X6 CBE 0 3 IRDY TPA TRDY TPB TPB DEVSEL Re test Change the faulty TPBIAS h d STOP VCCA OK part then end PERR VPPA No SERR PCLKRUN 8060B N B Maintenance 8 13 PC Card Socket and
212. s 123 BE dp sha sposa Vs 125 i 9 AGP SBSTB SBSTB 50049 VSS 55 VSS 126 9 AGP_SBSTB SBSTB 50050 gs 36 hed I 50051 __ 5 PI 9 AGP_RBF GP WEF 230 RBF 50052 gr SS AUS 9 AGP_WBF GE PIPE Wer 50053 x 55 13 9 PIPE 22229 pipes 30054 24 8899 xem E 9 16 AGP_STO G25 STO 50055 61 182 ie AGP eri E Api Spose 816 AGP_ST2 sta 30057 03 we Spasa ES VSS 108 E VSS_66 VSS_137 AAT H2 50061 S2 VSS_67 VSS_138 Y VSS 68 VSS 139 Phi n ipa HE External Thermal Sensor E Sas ua eat For SO DIMM thermal 50065 50067 25 1 2 HI O 10 LE DDR25V EDS ELS 16 L Hifo 10 Wee 50068 15 HUB N28 Hi STB 50070 i 15 HUB STB 40 HI STB 50071 ni FOS te ver BAL an MUN 1 30K i 4 7KINA 2 RET oe 5 PCIRST REZ 058 81427182021 PCIRST 2270 RSTIN 2 H28 CRE CKE2 8 TEST O haed RSVD SOKES 30 1 RESISTOR and 1 CS0 4 INTEGRATED PULL UP soseo DE 8 0 14 CAP within 1 0 erst Pre DSS A of the CA z scs 2 Pet 4 PLACE CLOSE TO ETS PIN 8 MEM_BSO 0605 1 250 er Siz 5850 scs 3 __ CSS 53 8 e scio pK Foe om CLK DDRO 8 PER o
213. s and Ctl input buffer and sense amp activation CPURST CPU Reset The CPURST pin is an output from the GMCH The AGTL GMCH asserts CPURST while RESET PCIRST from ICH4 M is asserted and for approximately 1 ms after RESET is deasserted The CPURST allows the processor to begin execution in a known state Note that the ICH4 M must provide CPU strap set up and hold times around CPURST This requires strict synchronization between GMCH CPURST deassertion and ICH4 M driving the straps DBSY VO Data Bus Busy Used by the data bus owner to hold the data bus for AGTL transfers requiring more than one cycle DEFER Defer GMCH will generate a deferred response as defined by the AGTL rules of the GMCH s Dynamic Defer policy GMCH will also use the DEFER signal to indicate a CPU retry response DPSLP I Deep Sleep This signal comes from the ICH4 M device CMOS an indication of and C4 state control to the CPU Deassertion of this signal is used as an early indication for C3 and C4 wake up to active HPLL Note that this is a low voltage CMOS buffer operating on the PSB VTT power plane HD 63 0 VO Host Data These signals are connected to the CPU data bus AGTL HD 63 0 are transferred at 4x rate Note that the data signals are inverted on the CPU bus HLOCK vO AGTL Host Lock All CPU bus cycles sampled with the assertion of HLOCK and ADS until the negation of HLOCK must be
214. sembly 1 To install the SO DIMM match the SO DIMM s notched part with the socket s projected part and firmly insert the OS DIMM into the socket at 20 degree angle Then push down until the retaining clips lock the SO DIMM into socket Then replace the extend SO DIMM compartment cover and secure with two screws 2 Replace the battery pack See section 2 2 1 Reassembly 49 8060B N B Maintenance 2 2 10 SO DIMM 2 2 10 2 Extend SO DIMM Disassembly 1 Remove the mother board ASSY See the step 1 to 7of section 2 2 1 Disassembly 2 Full the retaining clips outwards and remove the SO DIMM 6 Figure 2 25 Figure 2 25 Remove the SO DIMM Figure 2 25 Remove the SO DIMM Reassembly 1 To install the SO DIMM match the SO DIMM s notched part with the socket s projected part and firmly insert the OS DIMM into the socket at 20 degree angle Then push down until the retaining clips lock the SO DIMM into cover 2 Assemble the notebook 50 8060B N B Maintenance 2 2 11 Modem Card Disassembly 1 Remove the battery pack keyboard HDD module CD DVD ROM drive and LCD assembly See sections 2 2 1 to 2 2 6 Disassembly 2 Remove the mother board ASSY See the step 1 to 7of section 2 2 1 Disassembly 3 Remove two screw fastening the modem card Figure 2 26 4 Then disconnect the cable from the modem card Figure 2 27 Figure 2 26 Remove two screws Figure 2 27 Disconnect the MDC cable Reasse
215. sembly reassembly and show corresponding illustrations Use the chart below to determine the disassembly sequence for removing components from the notebook NOTE 1 Before you start to install replace these modules disconnect all peripheral devices and make sure the notebook is not turned on or connected to AC power 2 During disassembly 1 Label each cable as you disconnect it noting its position and routing 2 Keep all the screws 32 NOTEBOOK Modular Components LCD Assembly Components Base Unit Components 8060B N B Maintenance 2 2 1 Battery Pack 2 2 2 Keyboard 2 2 3 HDD Module 2 2 4 CD ROM Drive 2 2 5 Wireless Card 2 2 6 LCD Assembly 2 2 7 Inverter Board 2 2 8 LCD Panel 2 2 9 CPU 2 2 10 SO DIMM 2 2 11 Modem Card 2 2 12 D D Board 2 2 13 System Board 2 2 14 Audio Board 2 2 15 Touch Pad Board 2 2 16 Touch Pad Module 33 8060B N B Maintenance 2 2 1 Battery Pack Disassembly 1 Carefully put the notebook upside down ee 2 Slide the release lever to the Figure 2 1 Figure 2 1 Remove the battery pack Reassembly 1 Replace the battery pack into the compartment The battery pack should be correctly connected when you hear a clicking sound 2 Slide the release lever to the lock position unlock position 9 while take the battery pack out of the compartment 34 8060B N B Maintenance 2 2 2 Keyboard Disassembly 1 Remove the battery pack Se
216. sserts PCIRST to reset devices that reside on the PCI bus The ICH4 asserts PCIRST during power up and when S W initiates a hard reset sequence through the RC CF9h register The ICH4 drives PCIRST inactive a minimum of 1 ms after PWROK is driven active The ICH4 drives PCIRST active a minimum of 1 ms when initiated through the RC register PLOCK VO PCI Lock This signal indicates an exclusive bus operation and may require multiple transactions to complete ICH4 asserts PLOCK when it performs non exclusive transactions on the PCI bus Devices on the PCI bus other than the ICH4 are not permitted to assert the PLOCK signal SERR VOD System Error SERR can be pulsed active by any PCI device that detects a system error condition Upon sampling SERR active the ICH4 has the ability to generate an NMI SMI or interrupt 75 8060B N B Maintenance 5 3 Intel 82801DBM I O Controller Hub 4 Mobile ICH4 M PCI Interface Signals Continued IDE Interface Signals Continue Signal Name Type Description PME VOD PCI Power Management Event PCI peripherals drive PME to wake the system from low power states 51 55 PME assertion can also be enabled to generate an SCI from the SO state In some cases the ICH4 may drive PME active due to an internal wake event The ICH4 will not drive PME high but it will be pulled up to VecSus3_3 by an
217. t be asserted at least 10 ms after the resume well power VecLAN3_3 and VecLANI_5 is valid When deasserted this signal is an indication that the resume well power is stable SLP_S1 S1 Sleep Control SLP_S1 provides Clock Synthesizer or Power plane control Optional use is to shut off power to non critical systems when in the S1 M Powered On Suspend S3 Suspend To RAM S4 Suspend to Disk or S5 Soft Off states SUS STAT LPCPD Suspend Status This signal is asserted by the ICH4 to indicate that the system will be entering a low power state soon This can be monitored by devices with memory that need to switch from normal refresh to suspend refresh mode It can also be used by other peripherals as an indication that they should isolate their outputs that may be going to powered off planes This signal is called LPCPD on the LPC I F SLP_S3 S3 Sleep Control SLP_S3 is for power plane control It shuts off power to all non critical systems when in S3 Suspend To RAM S4 Suspend to Disk or S5 Soft Off states SLP_S4 S4 Sleep Control SLP_S4 is for power plane control It shuts power to all non critical systems when in the S4 Suspend to Disk or S5 Soft Off state C3_STAT C3_STAT This signal will typically be configured as C3_STAT It is used for indicating to an AGP device that a C3 state transition is beginning or ending If C3_STAT functionality is not required this signal may be use
218. ternal clock RCIN Keyboard Controller Reset CPU The keyboard controller can generate INIT to the processor This saves the external OR gate with the ICH4 s other sources of INIT When the ICH4 detects the assertion of this signal INIT is generated for 16 PCI clocks NOTE The ICH4 ignores RCIN assertion during transitions to the S1 M S3 S4 and S5 states INTR CPU Interrupt INTR is asserted by the ICH4 to signal the processor that an interrupt request is pending and needs to be serviced It is an asynchronous output and normally driven low Speed Strap During the reset sequence ICH4 drives INTR high if the corresponding bit is set in the FREQ_STRP register A20GATE A20 Gate A20GATE is from the keyboard controller The signal acts as an alternative method to force the A20M signal active It saves the external OR gate needed with various other PCIsets 79 8060B N B Maintenance 5 3 Intel 82801DBM I O Controller Hub 4 Mobile ICH4 M Processor Interface Signals Continued Signal Name Type Description Real Time Clock Interface Signals CPUPWRGD OD CPU Power Good This signal should be connected to the processor 5 PWRGOOD input To allow for Intel 9 SpeedStep technology support this signal is kept high during an Intel SpeedStep technology state transition to prevent loss of processor context This is an open drain output signal external pull up resistor r
219. tivity is heard and power indicator is not light up PU24 5VA ua 5VAS 51230105 5 1 DBATT DVMAIN PR47 PDIO 100K 12 3 D PQ4 DTC144WK 1 3V PL509 2 30 ADEN 257002 PF501 120Z 100M P22 6 5A 32VDC PLS10 77 120Z 100M PF502 breit J21 6 5A 32VDC 35077100 12 5 S 1 5 5 U18 um ri T 1000 T ERI 5VAS 301K Jr D516 RP531 A BAVTOLTI ali PR542 PR20 4 99K 0 38 1 39 BAT_VOLT BAT_V T w Micro e PR543 PC544 543 20K 1000P T O lp c245 L C246 T 0 n L PC559 PR559 2 5 T 100K Q 2 ar B d 5 H8 F3437 R292 R277 PRI9 5 10K 10K 99 BAT CLK BAT C 4 16 BAT_DATA BAT D 5 PRI8 0 93 8060B N B Maintenance 8 2 No Display There is no display on both LCD and VGA monitor after power on although the LCD and monitor is known good No Display Monitor or LCD module Replace monitor Board level or LCD Troubleshooting Make sure that CPU module DIMM memory are installed Properly Refer to port 378H Yes error code description System BIOS writes error code to port 378H section to find out which part is causing the problem Motherboard No 1 Try anoth
220. tri stated during a hard reset MDDCDATA vO DVI DDC Clock The signal is used as the DDC data for a digital DVO display connector i e secondary digital monitor This signal is tri stated during a hard reset MDDCCLK DVI DDC Data The signal is used as the clock for a digital DVO display connector i e secondary digital monitor This signal is tri stated during a hard reset 72 8060B N B Maintenance 5 2 Intel 82855GM Memory Controller Hub Odem Voltage Reference PLL Power Signals Signal Name Description Voltage Reference PLL Power Signals Continue Host Processor HXRCOMP Analog Host RCOMP Used to calibrate the Host AGTL I O buffers HYRCOMP Analog Host RCOMP Used to calibrate the Host AGTL I O buffers HXSWING Analog Host Voltage Swing RCOMP reference voltage These signals provide a reference voltage used by the PSB RCOMP circuit HYSWING Analog Host Voltage Swing RCOMP reference voltage These signals provide a reference voltage used by the PSB RCOMP circuit HDVREF 2 0 Ref Host Data input buffer VREF Reference voltage input for the Analog data signals of the Host AGTL Interface Input buffer differential amplifier to determine a high versus low input voltage HAVREF Ref Host Address input buffer VREF Reference voltage i
221. ttery pack See section 2 2 6 2 2 2 and 2 2 1 Reassembly 43 8060B N B Maintenance 2 2 9 CPU Disassembly 1 Remove the battery pack keyboard HDD module CD DVD ROM drive and LCD assembly See sections 2 2 1 to 2 2 6 Disassembly 2 Turn the four hex nuts to left to unscrew it completely Figure 2 17 3 Carefully put the notebook upside down Remove seventeen screws on the bottom of the notebook Then detach the housing Figure 2 18 I Figure 2 17 Remove the four hex nuts Figure 2 18 Remove the seventeen screws 44 8060B N B Maintenance 4 Remove three screws fastening the mother board ASSY Figure 2 19 5 Disconnect the two speaker cables 0 MDC wire cover switch cable MIC wire 0 Audio cable 6 Figure 2 20 Figure 2 19 Remove the three screws Figure 2 20 Disconnect all the cables and wires 45 8060B N B Maintenance 7 Disconnect the TP amp MB cable Now you can separate the system board ASSY Figure 2 21 8 To remove the heatsink ASSY remove four spring screws fastening the heatsink ASSY and disconnect the fan s power cord Figure 2 22 Figure 2 21 Remove the system board Figure 2 22 Remove the heatsink ASSY 46 8060B N B Maintenance 7 Using a flat screwdriver rotate the lock of the CPU socket until the arrow points to the O position for removing the CPU Figure 2 23 Figure 2 23 Remove the CPU Reassembl
222. uch Pad T P Test Error Error message of keyboard or touch pad failure is shown or any key does not work 3VS 5VA H8_VDD5 L31 120Z 100M 1 C862 C866 C255 C867 C262 C259 C256 R290 C249 C252 RT 0 lp T 0 9 59 4 37 36 9 e 5V VDDIO 3 VCCI1 2 B AVCC J17 AVREF RP18 47K 8 8 KI 0 7 E 3VS 5VA 4 D P22 KO 0 15 RP532 1 16 gt 47T s 1025 R297 R298 10K 10K ROMCS H8 KBCS 72 8 9 95 cm 68P 3 Internal Keyboard Connector 0515 1 5 U18 R287 7 73 MCCS 14 3 15 H8 MCCS e 98 M levare n 68P LPC Micro r Supe 3VS 5V Controller 5V J10 RP532 114 4 7K 8 120Z 100M RP530 a 5 115 P 1 Poy 93 SA2 93 4 7K 4 21 PC87393 4 gt 8 3437 xia 120Z 100M 87 IRQI 53 e 4 e 10 T 3 86 IRQI2 54 4 113 ok 120Z 100M L cui 112 4 4 83 e 96 47P 47P 0 1p 82 97 gt Touch pad 104 8060B N B Maintenance 8 7 Hard Drive Test Error Either an error message is shown or the drive motor spins non stop while reading data from or writing data to hard disk Hard Driver Test Error 1 Check if BIOS setup is OK Board level 2 Try another working drive and cable Troubleshooting Re boot OK Parts Signals One of the followin
223. used enable CMOS _ power to the panel interface PANELBKLTEN LVDS LCD Flat Panel Backlight Enable This signal is used to CMOS enable the backlight inverter BLD PANELBKLTCTL LVDS LCD Flat Panel Backlight Brightness Control This signal CMOS is used as the Pulse Width Modulated PWM control signal to control the backlight inverter DDCACLK TO CRT DDC Clock This signal is used as the DDC clock signal CMOS between the CRT monitor and the GMCH DDCADATA vO CRT DDC Data This signal is used as the DDC data signal CMOS between the CRT monitor and the GMCH DDCPCLK vO Panel DDC Clock This signal is used as the DDC clock signal CMOS between the and the GMCH DDCPADATA Panel DDC Data This signal is used as the DDC data signal CMOS between the and the GMCH MI2CCLK vO DVO Clock This signal is used as the DC for a digital DVO display i e TV Out Encoder TMDS transmitter This signal is tri stated during a hard reset MI2CDATA vO DVO Data This signal is used as the 2C_DATA for a digital DVO display i e TV Out Encoder TMDS transmitter This signal is tri stated during a hard reset MDVICLK vO DVI DDC Clock This signal is used as the DDC clock for a digital DVO display connector i e primary digital monitor This signal is tri stated during a hard reset MDVIDATA vO DVI DDC Data The signal is used as the DDC data for a digital DVO display connector i e primary digital monitor This signal is
224. using the problem 97 8060B N B Maintenance 8 3 VGA Controller Failure LCD No Display There is no display or picture abnormal on LCD although power on self test is passed J4 0501 3VS 514800 8 L503 7 3 120Z 100M LCDVCC 12 5 2 e IVY e e C590 D 5 572 C563 C570 C25 C561 12VS 8 10u 1000P 1000 1 4 77 7 splay 3 2 43VS Display LCD ID3 LCD_ID LED_IDI LCD DIES LTN152W3 66M_AGP From 0506 Clock Generator ENPVDD amp 0 0 0 1 m 152 01 R109 ie 10K 10K 4 RP2 IK 4 AGP AD 0 31 LCD 100 21 e i CBE 0 3 LCD 23 e AGP FRAME LCD ID2 25 D gt U4 U3 AGP_IRDY AGP_TRDY MT LCD ID3 2 95 4 gt e AGP DEVSEL STOP TXOUT 0 3 8 5 11 20 8 0 11 TXOUT 0 3 6 7 13 18 Memory AGP_ADSTB 0 1 N TXCLK 3 TXCLK Controller 4 SR VGA AGP_RBF AGP_WBF Hub E Controller o AGP PIPE 18 gt AGP_REQ N lt AGP_GNT xp Odem gt 27MH C75 ST 0 2 18 gt NV
225. ut until fully extended then carefully pull harder to remove the CD DVD ROM drive Figure 2 7 Figure 2 6 Remove one screw Figure 2 7 Remove the CD DVD ROM drive Reassembly Push the CD DVD ROM drive into the compartment and secure with one screw 2 Replace the HDD module See section 2 2 3 Reassembly 3 Replace the battery pack See section 2 2 1 Reassembly 37 8060B N B Maintenance 2 2 5 Wireless Card Disassembly Complete the steps in Section 2 2 to prepare the system for disassembly 1 Remove the battery pack See section 2 2 1 Disassembly 2 Remove two screws fastening the mini PCI cover Figure 2 8 3 Disconnect the antenna connecting the wireless card Figure 2 9 step 1 Figure 2 8 Remove the mini PCI cover Figure 2 9 Remove the antenna 4 Pull the retaining clips outwards 0 and remove the wireless card Figure 2 9 step 2 38 8060B N B Maintenance Reassembly 1 To install the wireless card match the wireless card s notched part with the socket projected part and firmly insert the card into the socket Then push down until the retaining clips lock the card into the socket 2 Attach the antenna Then replace the cover and secure with two screws 3 Replace the battery pack See section 2 2 1Reassembly 39 8060B N B Maintenance 2 2 6 LCD ASSY Disassembly 1 Remove the battery pack and keyboard See sections 2 2 1 and 2 2 2 Disassembly 2 Carefully upside do
226. wn the notebook then remove two screws on the bottom of the notebook Figure 2 10 3 Disconnect the antenna from the wireless card See the step 1 2 of section 2 2 5 Disassembly 4 Turnover the notebook and remove two screws on the rear side of the notebook Figure 2 11 Figure 2 10 Remove two screws on the Figure 2 11 Remove two screws on the bottom side of notebook rear side of notebook 40 8060B N B Maintenance 5 To remove the hinge cover unscrew three screws Figure 2 12 6 Disconnect the LCD cables from the mother board 9 and Pull out the antenna from the KB cable s compartment 0 Then unscrew the four screws 6 Now you can separate the LCD ASSY Figure 2 13 Figure 2 12 Remove the hinge cover Figure 2 13 Remove the LCD ASSY Reassembly 1 Attach the LCD assembly to the base unit and secure with four screws on the hinges 2 Reconnect the two cables to the mother board 3 Reconnect the antenna to the wireless card See section 2 2 5 Reassembly 4 Replace the hinge cover and secure with three screws 5 Replace the keyboard and battery pack See sections 2 2 2 and 2 2 1 Reassembly 41 8060B N B Maintenance 2 2 7 Inverter Board Disassembly 1 Remove the battery pack keyboard and LCD assembly See sections 2 2 1 2 2 2 and 2 2 6 Disassembly 2 Remove six rubber pads and six screws fastening the LCD cover Figure 2 14 3 Insert a flat screwdriver to the lower part of the LCD cover and gentl
227. y 1 Align the arrowhead corner of the CPU with the beveled corner of the socket and insert the CPU pins into holes 2 Use a flat screwdriver to rotate the lock of the CPU socket until the arrow points to the L position for securing the CPU in place 3 Reconnect the fan s power cord to the system board and fit the heatsink onto the top of the CPU and secure with four screws 4 Replace the heatsink and secure with four spring screws Then reconnect the fan s power cord 5 Reconnect the TP amp MB cable and then fit the mother board into place 47 8060B N B Maintenance 6 Reconnect the two speaker cables 0 MDC wire cover switch cable MIC wire 0 Audio cable 6 7 Fasten the mother board by three screws 8 Replace the housing and secure seventeen screws on the bottom of the notebook and four hex nuts on the rear side of notebook 9 Fasten the housing by four hex nuts on the rear of the notebook 10 Replace the LCD ASSY CD DVD ROM HDD keyboard and battery pack See section 2 2 6 to 2 2 1 Reassembly 48 8060B N B Maintenance 2 2 10 SO DIMM 2 2 10 1 Extend SO DIMM Disassembly Remove the battery pack See section 2 2 1 Disassembly 2 Remove two screws locking the extend SO DIMM compartment cover Figure 2 24 3 Full the retaining clips outwards and remove the SO DIMM 6 Figure 2 24 Figure 2 24 Remove the extend SO DIMM cover Figure 2 24 Remove the extend SO DIMM Reas
228. y error The ICH4 can either generate an NMI or SMI upon detecting a parity error either detected internally or reported via the PERR signal TRDY Target Ready TRDY indicates the ICH4 s ability as a Target to complete the current data phase of the transaction TRDY is used in conjunction with IRDY A data phase is completed when both TRDY and IRDY are sampled asserted During a read TRDY indicates that the ICH4 as a Target has placed valid data on AD 31 0 During a write TRDY indicates that the ICH4 as a Target is prepared to latch data TRDY is an input to the ICH4 when the ICH4 is the Initiator and an output from the ICH4 when the ICH4 is a Target TRDY is tri stated from the leading edge of PCIRST TRDY remains tri stated by the ICH4 until driven by a target REQI4 0 REQ 5 REQ B GPIO 1 PCI Requests The ICH4 supports up to 6 masters on the PCI bus 5 15 muxed with PC PCI REQ B must choose one or the other but not both If not used for PCI or PC PCI REQ 5 REQ B can instead be used as GPIO 1 NOTE REQ 0 is programmable to have improved arbitration latency for for supporting PCI based 1394 controllers GNT 4 0 GNT 5 E GNTI B GPIO 17 PCI Grants The ICH4 supports up to 6 masters on the PCI bus GNT 5 is muxed with PC PCI GNT B must choose one or the other but not both If not needed for PCI or PC PCI GNT 5 can instead be used as a GPIO Pull up
229. y parts Motherboard RP524 P_LPD3 R647 P_LPD4 Li P_LPDS RP525 P_LPD6 RP523 P_LPD7 RP507 RP505 111 8060B N B Maintenance 8 10 PIO Port Test Error E U515 LPC Super I O PC87393 When a print command is issued printer prints nothing or garbage D504 BAS32L 5VS DI e oo o o o o 9 9 9 9 R644 RP525 RP523 RP507 RP505 22K 22K 4 2 2K 4 2 2K 4 2 2K 4 RP504 33 4 54 P STB STB 1 53 P_AFD AFD 14 42 P_LPDO LPDO 2 51 ERR ERR 15 RP506 50 P_LPDI 33 4 LPDI 3 e 49 P INIT INIT 16 9 48 P LPD2 LPD2 4 e 4 P_SLIN SLIN 7 RP522 46 P_LPD3 33 4 LPD3 5 45 P_LPD4 LPD4 6 44 P LPD5 LPDS 7 43 P_LPD6 LPD6 8 524 42 P_LPD7 33 4 LPD7 9 41 P_ACK ACK 10 40 P_BUSY BUSY 11 37 P_PE PE 12 35 P_SLCT SLCT 13 R647 33 L C166 CP507 dO LO LO Lul CP506 CP505 CP504 T 180P 180P 4 TOT T T 180P 4 180P 4 180P 4 18 25 o o e e o o 77 GND 102 10 2 109 PIREA 112 8060B N B Maintenance 8 11 Audio Failure No sound from speaker after audio driver is installed Audio Failure 1 Check if speaker cables are connected properly 2 Make sure all the driv
230. y pry the cover out Repeat the process until the cover is completely separated from the housing 4 To remove the inverter board on the lower part of the LCD housing remove two screws and disconnect two cables Figure 2 15 e 1 1 0 a L l d 24 3 Figure 2 14 Remove LCD cover Figure 2 15 Remove the inverter board Reassembly 1 Reconnect the cables Fit the inverter board back into place and secure with two screw 2 Replace the LCD cover and secure with six screws and rubber pads 3 Replace the LCD assembly keyboard and battery pack See section 2 2 6 2 2 2 and 2 2 1 Reassembly Pa 8060B N B Maintenance 2 2 8 LCD Panel Disassembly 1 Remove the battery pack keyboard and LCD assembly See sections 2 2 1 to 2 2 2 and 2 2 6 Disassembly 2 Remove the LCD cover See the step 1 to 3 of section 2 2 7 Disassembly 3 Disconnect one cable from the inverter board on the lower part of the panel Figure 2 16 4 Remove the four screws on two sides of the panel and four screws on the lower part of the LCD panel Figure 2 16 Figure 2 16 Remove LCD panel Reassembly 1 Fit the LCD panel back into place and secure with eight screws and reconnect the cable to the inverter board 2 Fit the LCD cover back into the housing and ensure inosculated well Then replace the six screws and six rubber pads 3 Replace the LCD assembly keyboard ba

Download Pdf Manuals

Related Search

Related Contents

Dahle 40026 scissor  Epson TM-S1000 User's Manual  • MODO/P • MODO/V Membrane d`étanchéité bitume  Chief UNS-1 rack accessory  IPG Commercial OV2 High End Mono Laserjet datasheet 4P_P4015  Fiche d`instructions  Istruzioni per l`uso LION 5000 LION 6000  User Guide - XMFan.com  ING2100M User Manual  Kawai CA1200 Musical Instrument User Manual  

Copyright © All rights reserved. Failed to retrieve file