Wavetek -
Contents
1. s 15VA R213 286 287 C216 S VENDRE asf 257 ssp 5 SYNC 158 22 22 1 228 oe 22N aan 2 6 NP1280 1 15208 78L 05 88 M L266 TES C221 145170 282 lt FB205 xls SYNC ETS pee C208 BVA ee 1K IC202 B 8214 REFCLK 1 R235 3 OSCIN VDD NE527 13 158 PJ208 2 2 15K 15VA C228 11 6 2 ll DSCOUT PHy 1 M ZEROX av e R224 3 REFDUT PHA FA av E 18M 4 8 288 8 282 BVCPU FIN PD av M2 5 Pa 358 a 98 809 5 lor vas PLLCTL 7 4 8 1 av TANK PLLLD 8 p 3 85 3 3 14 LD 8281 EDNT GND C322 PLLC Gk EY 15a 288 15203 czat 4 IC282 D 4 R216 128N Mc12149 DOUT 8288 15202 282 og 158 15 R312 BVA 0236 22 EZ 11 VEE 228 2Y av 35v R203 2 av 5 47K R217 BVCGA 15265 R235 EZ 231 12K R221 FB206 10K m 22U vR208 c317 ADB561 av 2k2 ER ARBCL2. BVCPU 388 c3a1 5VX CE 5VCPU C382 WOE WCEL WOE CEH taan 5 C303 22 20 BVCPU Lo c3a BYCPU 2 BVCPU 385 2 TPI p C386 28 caos 28 C397 I 18 37 B4 73 88 108 128 144 14 14 15VA av av ae av BVX 51 vc 94 uv 1a WAG 1a I m ee Ha LADDR ab WAT 5 Ww a i EXTCLK WWD1 a D LADDR WAZ 21 m 2115198 13 11 WWOZ LADDR2 WAS 78 85 12 IC22 D REFCLK WWD3 S923 LADDR3 WAA 7 WWD4 2 LADDR4 WAB 23 av 74 8 WWOS D5 LADDRS WAS 5 WWDG 188 LADDRG WAT 24 wo7 5 LADDR7 WAB a 4 LADDRB 5VCPU R38 SKG 25 WAS 25 100K LADDRS wara 2 CLKCAL 155 LADDR1a WATT s FPGADIN 777 sWeTRG DIN LADDR1 1 WA12 3 PJff 1 1 2 3 4 HOLD 38 LADDR12 WA 13 2 HOLD IN R33 1C21 A IC21 B R36 BWR LADDR 3 HCT14 HCT14 478 SAD P411 2 O4 AS E BAD ag 19 LADDR1 4 Woo cia W cnn av 834 R37 119 EL wor _ 478 L ADDR1 5NOT WO2 18 Ie 1 19 a 8 5VcPU SEL 28 wo2 18 PJi2 1 co TRIGGER FPGASELNOT 75 woo TRIG IN 1C21 E 1021 D CTL TRGOSEL RAMD 17 WA 17 R35 HCT14 HCT14 48 78 wot WD4 RRS Bl esa oz 77 v2 os 13 e 5 CTLTRGISEL LDC RAMD2 ww 16 53 78 wo3 wos 16 BVCPU 45 CTLTRGOSEL1 INIT RAMD3 79 wor 15 W7 15 av BVA ce TRGPRY RAMD4 w fa 88 5 8383 FA av TRGNXT RAMD5 WAI 4 1 27 ATK 857 48 RAMOS
3. REDLSEL B I 87 818 9 2 7 2 4 GPIB INTERFACE DISPLAY INTERFACE BVCPU av 1 KEYBOARD INTERFACE av zMoD BVEPH Bra A cir PJ7 2 w Pi4 34 O Pi2 ia O 22 qp ZMoD 5VCPU BiA 33 O 4 2 18 og EC PJB 4 PJ4 32 OF 7 5 DI ces av 16 PJ6 2 6MHZ 844 38 OFF 8 D2 HC32 18 3 9 1 PJ6 3 MRST PJ4 28 OH PJ2 a gt D3 2BVEBU 4084 PJ6 80 GPIBINT PJ4 26 PJ2 3s 2 PIE 7 C RB PJ4 24 Oc PJ2 2 13 PJS BO PJ4 22 OA PJ2 As 5 Ds PIB 50 GPIBSEL PJ4 20 O PJ2 4 114 15 pz 1 LE OE PJ2 23 REMLED PJB 11 A2 PJ4 18 PJ2 CH3ED PJS Aa PJ4 14 OH av PJ2 z 8 REDESER 1 PJ4 OA B x 8 558 28 550 87 44 12 PJ2 1 O CONTRAST PJE 17 PJ4 18 Oc PJ2 15 O kNOBA 1512 PIG 28 c BB PJ4 8 PJ2 17 O kNOBB EDIO SHDAT 1C13 PJS 18 D4 PJ4 8 OF 34 f GND O o BVCPU PJ6 160 03 PJ4 4 OFF 8 cars M ra Pig 14 m2 PJ4 2 OF BVCPU PJ6 120 D PJ4 1 Oo PJ2 2 18 na e PJG 18 00 PJ4 31 O BACKLIGHT g 5g EEPROM BVCPU ass PJS 6 PJ4 5 CONTRAST PJ2 8 ia gt 14 ay az Li PJB PJ4 28 Q BACKLIGHT 5 2 4 9 pa ce vec esr 15 16 06 PJ2 27 CHION DISPO PJ4 21 O PJ2 3 IC16 8 2 1 14 pcz LEDLDAD i 65 ps4 23 O DISP PJ2 6 3 FPEACELK PSK ee IC15 28 STR o PJ2 25 SYNCION DISP2 1 GND GND PJ4 25 O PJ2 7 R26 83546 FPGACCLK 3 5 PJ2 28 SUMIN E j 0 pja 27 O B SP3
4. B QO iw YU YU YU YU YU 5 3 im IN s s sk ub Nw s O PJ1 17 KNOBB 55 55 55 55 gt 8 55 d RE O P31 12 DE RE bud dy O Put 11 5VCPU PJ1 PJ1 PJ1 PJ1 LD12 REMOTE PJ1 PJ1 SYNC1ON R12 680 FO Keyboard Pcb 23 28 38 23 27 25 5VCPU XTL 4 BEEP ES 12 MHz 22P R25 C15 ARC RS232 INTERFACE 4 18 fu 2 3 C16 23 238 5VCPU 5 T av CPU AND MEMORY BUZZ PJ 63 PERA E RUS 3 ycc 064189 av 1 3 av av Psi 18 GND 228 m PILING GND 58 AD 64 ROMSEL VBAT Put 2 ict A GND TRANSMIT OUT 6 14C88 GND 5VCPU 24 de 24 29 29 24 29 29 24 29 F 4 C5 SHD2 3 TENDO O O O Q Q Q Q RI DRE QG 35V 65 DE WE pE WE SHD1 44 SANEPID BR 4588 TEND IC4 5 1C6 1C7 Ice 1c3 5408 45 32 ROM a PAM 32 Ll yec RAM 32 L yer RAM 32 L yec RAM 32 yer RAM SHEN
5. Part Number 23105 2300 23105 2470 23105 2510 23105 2560 23105 3100 23105 3120 23105 3150 23105 3200 23105 3270 23105 3330 23105 3470 23105 3510 23105 4100 23105 4200 23105 5100 23105 6100 23202 0039 23202 0100 23202 0102 23202 1240 23202 1750 23202 2220 23206 0412 23206 1200 23222 0047 23301 0443 23377 2220 23424 0443 23427 0268 23427 0331 23427 0593 23427 9205 23427 9209 23427 9218 23428 0082 23428 0390 Description RES SM0805 3KOOF W1 RES SM0805 4K70F W1 RES SM0805 5K10F W1 RES SM0805 5K60F W1 RES SM0805 10KOF W1 RES SM0805 12KOF W1 RES SM0805 15KOF W1 RES SM0805 20KOF W1 RES SM0805 27KOF W1 RES SM0805 33K0F W1 RES SM0805 47 W1 RES SM0805 51KOF W1 RES SM0805 100KF W1 RES SM0805 200 W1 RES SM0805 1MOOF W1 RES SM0805 10MOF W1 RES 3R90F W25 MF 50PPM RES 10ROF W25 MF 50PPM RES 10R2F W25 MF 50PPM RES 240RF W25 MF 50PPM RES 750RF W25 MF 50PPM RES 2K20F W25 MF 50PPM RES 41R2F W60 MF 50PPM RES 200RF W60 MF 50PPM RES 4R70J W33 MF FUSIBLE RES NETWK SIL 22K X 8 RES PS H 2K2 CF 10MM CAP10NZ 1KV CER D10 P5 CAP22PJ 100V CER NPO P2 5 CAP1NOK 63V CER HI K P5 CAP82PG 100V CER NPO P2 5 CAP47PJ 100V CER NPO P2 5 CAP33PJ 100V CER NPO P2 5 CAP 330PK 100V CER MED K P2 5 CAP8P2C 100V CER NPO P2 5 CAP39PG 100V CER N150 P2 5 Position R30 310 R23 282 288 289 290 295 296 298 R233 242 306 R240 270 R1 2 4 6 11 14 32 35 55 205 207 209 211 235 R217 R221 236 241 279
6. 10V and its input approximately 3 6V Relays RL201 and RL202 select 20dB output attenuators and IC217 selects an intermediate 10dB attenuator Zero Crossing Detector IC201 is a comparator with positive feedback via R203 M is the signal selected by IC211 and M2 is the signals dc mid point which is buffered by IC200 B This circuit is used to detect zero crossing of high frequency DDS waveforms of sine ramp or triangle and sent to the FPGA Control DACs IC27 is a 12 bit voltage output DAC with internal 2V reference IC115 provides a bi polar output of 3 3V 28 multiplexes the DAC output voltage onto the appropriate hold capacitor FET input amplifiers C29 buffer the voltages on the hold capacitors IC208 is a quad 8 bit DAC IC209D provides a 3 3V reference to give 0 to 3 3V DAC output IC209 A B and C give gain and or offset VR200 gives coarse adjustment of the multiplier offset and is only adjusted at initial calibration with the default calibration values present The voltage at each DAC output is controlled by the MPU which calculates each value from a combination of the instrument set up and the calibration constants stored in EEPROM Reference Clock IC105 is an integrated 10MHz voltage controlled crystal oscillator If an external clock is applied C48 is charged up via D5 blocking the internal clock Phase Locked Loop and VCO IC203 is a VCO tuned by varicap diodes D209 212 The range is 20MHz to 40MHz for square a
7. Gate Start Stop Phase Sweep All standard and arbitrary The smaller of 1MHz or the maximum for the selected waveform 40Msamples s for ARB and Sequence 0 005Hz to 100kHz internal dc to 1MHz external Internal from keyboard previous channel next channel or trigger generator External from TRIG IN or remote interface 360 settable with 0 1 resolution subject to waveform frequency and type Frequency sweep capability is provided for both standard and arbitrary waveforms Arbitrary waveforms are expanded or condensed to exactly 4096 points and DDS techniques are used to perform the sweep Carrier Waveforms Sweep Mode Sweep Direction Sweep Range Sweep Time Marker Sweep Trigger Source Sweep Hold Multi channel sweep All standard and arbitrary except pulse pulse train and sequence Linear or logarithmic triggered or continuous Up down up down or down up From 1mHz to 16 MHz in one range Phase continuous Independent setting of the start and stop frequency 30ms to 999s 3 digit resolution Variable during sweep The sweep may be free run or triggered from the following sources Manually from keyboard Externally from TRIG IN input or remote interface Sweep can be held and restarted by the HOLD key Any number of channels may be swept simultaneously but the sweep parameters will be the same for all channels Amplitude Offset and Waveform can be set independently for each channel
8. Tone Switching Capability provided for both standard and arbitrary waveforms Arbitrary waveforms are expanded or condensed to exactly 4096 points and DDS techniques are used to allow instantaneous frequency switching Carrier Waveforms Frequency List Trigger Repetition Rate Source Tone Switching Modes Gated Triggered FSK All waveforms except pulse pulse train and sequence Up to 16 frequencies from 1mHz to 10MHz 0 005Hz to 100kHz internal dc to 1MHz external Usable repetition rate and waveform frequency depend on the tone switching mode Internal from keyboard previous channel next channel or trigger generator External from TRIG IN or remote interface The tone is output while the trigger signal is true and stopped at the end of the current waveform cycle while the trigger signal is false The next tone is output when the trigger signal is true again The tone is output when the trigger signal goes true and the next tone is output at the end of the current waveform cycle when the trigger signal goes true again The tone is output when the trigger signal goes true and the next tone is output immediately when the trigger signal goes true again Using 2 channels with their outputs summed together it is possible to generate DTMF test signals Trigger Generator Internal source 0 005 Hz to 100kHz square wave adjustable in 10us steps 3 digit resolution Available for external use from any S
9. 93 ae WWR i TRIGGER 7 1K IC25 A TRIGGER RAMD7 08858 858 ARBCLK 47 RAMDB 84 We WOE WEL WOE WER PJ13 1 Z a IBBUT 85 wos 22 28 BYCPU 22 28 1 EXTSUM RAMDS 5 6 EXT SUM IN m313 INCEN __49 INCEN wie m av x 43 87 11 P3132 TOAN R59 6 TIMER RAMD11 BB a 220 BVCPU 45 MODE RAMD12 89 4012 H MANTRIG 2 MANTRG RAMD13 wots 1 5 25808 32 92 wor B mE 5 2888 RAMD1 4 s 475 AMD wots 7 RAMD15 128 w2 2 1 21 RAMOENOT Wo 868 8 IC25 B EPGAPRGE DONE MOEN 2 WA3 8 1k A PROG RAMWRNOT Praa LI FPGACCLK 187 TE 3 57 145 za R61 AMEXT DACDAT WAG 5 ExT MOD 58 pat L 5 6 PJ13 4 FILT P22 10221 DACDAT2 DA2 ME z 5 Z pgi 10144 DACDAT3 ne WAS 25 av OPON 8 ie xCS1a BACHATA 61 DA4 je 5 TGA1244 52 DAS ws 4 3 Pa3 DACDAT5 83 Wn 26 1 25 DACLD 7 pg4 DACDATG pa WATZ 3 x 118 ret AT2 7 pAcpAr 55 DA7 P25 WA13 2 P3 1 66 REFCLK LI 7 att 143 loa BACDATB DAB B CLK ta 67 DAS DACD 87 DACDATS 4 PJ3 2 PLLD 19 68 18 4 P1a DACDAT1B 848 8 15 88 pat vW ts 118 EXTCLK INTSUM gt p DACDATI 1 sae x SUMOFF 13 1 2 N C Ja T WB12 12 BYCPU AMON 5 ZMODOUT z Mora 18 132 lois N C ud 4 1 wore 1 11 2 3 OPEN 15 SPR1 DOUT CLKIN c54 1023 61717 Esa 1524 S
10. Any channel can be triggered by the previous or next channel The previous next connections can be used to daisy chain a trigger signal from a start channel through a number of channels in the chain to an end channel Each channel receives the trigger out signal from the previous or next channel and drives its selected trigger out to the next or previous channel The end channel trigger out can be set up to drive the start channel closing the loop In this way complex and versatile inter channel trigger schemes may be set up Each channel can have its trigger out and its output waveform set up independently Trigger out may be selected from Waveform End Position Markers Sequence Sync or Burst Done Using the scheme above it is possible to create a sequence of up to 64 waveform segments each channel producing up to 16 segments and all channels being summed to produce the complete waveform at the output of channel 4 INTERFACES Full remote control facilities are available through the RS232 or GPIB interfaces RS232 Variable Baud rate 9600 Baud maximum 9 pin D connector IEEE 488 Conforms with IEEE488 1 and IEEE488 2 GENERAL Display Data Entry Stored Settings Size Weight Power Operating Range Storage Range Environmental Options Safety EMC 20 character x 4 row alphanumeric LCD Keyboard selection of mode waveform etc value entry direct by numeric keys or
11. 28 2 O niat MSD 3 18 29 O B2 D2 4 62 O 17 38 O 83 03 0103 o 5 LS 5 15 32 85 D5 O05 7 14 33 BE 06 nins B 13 34 87 87 3 8 7 3 12 35 Be De Onos LSD NPJ5 28 MISHELL 75160 Gpib Interface Pcb 11 13 15 19 17 28 18 16 14 12 18 38 48 K12 K11 18 kg B k49 B k37 RO RO Od RO RO RO RO FB F7 FE F5 LOCAL g MOD g SUM status Pst 14 COL BO 36 B OKA B KIB B Bio B B Bu B k47 B ARB wa AMPL SEQUENCE gg STD gg REO E MODE gg UTILITY gt PJI 18 E E E E E coL B B Bk44 B Bxk32 Bi k33 B 26 BO 27 23 E k22 EXP B ENTER q amp p 5 pe a 5 a 7 4 4 4 4 4 mPJ1 18 COL KB 7 F4 F2 F1 F3 ry PJ1 20 COL 3 B k41 BKIG BK46 Ba Bi k42 8 2 B 38 me CREATE OFFSET MODIFY MAN sa FILTER MAN HOLD g TRIG IN E gt PJI 13 COL 4 Es MAIN QUT CHI K20 K21 B k43 B k39 ROTOR ROTOR lt gt A a SYNC OUT ry Puts 21 5VCPU K31 B 4 HO Od L SWEEP RECALL NPJt 18 3 COL 6 Bs CONTRAST 4K7 1 B 15 B Bk13 B k34 B k35 EJ k28 B k29 B B K25 E k24 PJ1 34 B da ESCAPE 4g L CE L 3 B TUE L 2 E B L 0 m BVCPU PJ1 22 COL 7 swi 2 PJ1 15 KNOBA
12. PJ2 B 2 7 F 4 PJ2 38 TRIGIN 14 6 01585 ery e EDIO SHDAT 2 Pij 2H MODIN 8148 O DISPRW PJ2 12 ne PYP av cia DISPRS PJ4 7 Q 4084 Mt NOT 5VCPU KE E ZMOD DOUT SHD2 zMa 51 SHDG zM2 SHEN ZMOD1 SHDACDAT zMOD2 SHDACCLK 3 SHDACLOAD 2 604 D8 DIN Di RAM NOT D2 ROMNOT LDC D3 RAMI NOT D4 RAM2NOT D5 RAM3NOT D6 icta RAM4NOT D7 xCS 5 CHISEL A4 vo1aa CH2SEL AB CH3SEL AB CH4SEL A7 17 npa A18 ppt A18 DD2 DD3 6MHz DWR WRNOT DE RDNOT DRS IORONOT MREONOT FPGAPROG FPGACCLK SHCLK FPGADIN SWPTRG TDI MODE WEMIOD1 WFMIOD2 HOLDHI WFMI0D3 INCEN WFM1004 WEMIOD5 INTTRIG HDC WFM10D6 MANTRIG CPULOCK WFMIOD7 LEDLOAD N C CEKIN DONE PROG ECS CCLK EDIO SHDAT INIT KROWSELNOT KCOLSELNOT KNOBA GPIBSELNOT KNOBB GND b fs la ss ES av 73 64 ZMoD zMa 85 a zMi ZM2 ZMOD1 6 7 8 ay 28 RAMOSEL 30 ROMSEL 32 RAMZSEL eg 33 RAM3SEL 34_RAM4SEL av 3 SEL ta 13 14 83 DISPO 32 DISP gt DISP2 80 DISP3 94 DISPRW 85 DISPE 86 DISPRS 2 3 FPGAPROG 2 FPGACCLK FPGADIN 24 97 HOL DHI 88 INCEN 28 INTTRIG 99 MANTRIG 26 BVCPU 22 R29 47K 58 52 FRSTZ 74 WR 76 78 KNOBA 78 Main Pcb Sheet 1 of 4 MPU and Interfaces
13. _ 42 TRANSMIT IN 3 DRERI av 15 stzxx8 ev te 128kxa fav te t2exxe fav 16 128KXB av 6 128kx8 8 8 MEL Koy B GND GND GND GND GND GND SHDACDAT A AB AB AB AB AB IZB TXAB LR 12 1 8 210 2110 2 Jaa 2 Iho 210 SHDACCLK 48 PJ1 3 49 15 At 11 31 A Al 31 N 31 31 31 m sa RECEIVE IN O 4 6 47 16 A2 A 4 1 A2 4 2 4 Az 4 A 4 je SRDACLOAD 464700 17 A3 s A3 28 A3 28 A3 28 A3 28 a Aa 28 na 72 OC crsa faj A4 3 A4 27 3 A4 27 3 A4 27 A3 A4 27 3 4 27 3 oi 71 48498 _ 45 O prso 2 5 4 4 A4 A4 A4 A4 7a 514 8 za AB 7 AB 26 AB 26 AB 26 5 25 A5 25 D2 RECEIVE OUT 21 as AB 48 AB z 1 AB z AS AB z A5 AB zg 145 pa 59 sa 1 22 A7 ES A7 12 A7 12 A7 12 A7 12 As A7 12 4 58 ss 23 AB 27 A8 11 A8 11 7 AB 11 N AB 55 87 8 8 5VCPU 3 gz 175 24 AS 28 8 A8 23 AB 23 e A8 23 gt AS z3 A3 25 M 55 56 8 55 1 2 25 Ata 23 ATB ATB 1g 1a Aia 19 1a uA 87 85 TXS 28 Aii 25 Aii Aii 9 Mt g Allg a 1 9 4 52 Att 2 8 27 A12 rn az a 2 g A az a A12 a i A12 Re As 81 av QRESET A13 28 Ata 7 ata 7 Ata 7 A3 7 2 A13 7 6 58 EMERD 5 Cusack 28 A13 A13 A13 A13 A13 A13 59 7 H 29 A14 28 14 6 A14 6 A14 6 A14 6 A14 6 I A7 ji C Busro BATE z A14 AE AE p ANA AE NE ANA MIB
14. by rotary control Up to 9 complete instrument set ups may be stored and recalled from battery backed memory Up to 100 arbitrary waveforms can also be stored independent of the instrument settings 3U 130mm height 350mm width 2 and 4 channels 212mm 2 rack single channel 335mm long 7 2 kg 16 Ib 2 and 4 channels 4 1kg 9lb 1 channel 230V 115V or 100V nominal 50 60Hz adjustable internally operating range 14 of nominal 100VA max for 4 channels 75VA max for 2 channel 40VA max for 1 channel Installation Category Il 5 C to 40 C 20 80 RH 20 C to 60 C Indoor use at altitudes up to 2000m Pollution Degree 2 19 inch rack mounting kit Complies with EN61010 1 Complies with EN50081 1 and EN50082 1 10 Safety This generator is a Safety Class instrument according to IEC classification and has been designed to meet the requirements of EN61010 1 Safety Requirements for Electrical Equipment for Measurement Control and Laboratory Use It is an Installation Category II instrument intended for operation from a normal single phase supply This instrument has been tested in accordance with EN61010 1 and has been supplied in a safe condition This instruction manual contains some information and warnings which have to be followed by the user to ensure safe operation and to retain the instrument in a safe condition This instrument has been designed for indoor use in a Pollution Degree 2 environ
15. code which is passed to the software Multiple keys down are ignored IC10 provides the port decode signals for access to IC12 and IC13 The knob is connected directly to the FPGA IC10 This decodes the 4 states of the switches and increments decrements a counter The counter is read and cleared every 10ms and the value and sign passed to the software The 6 LEDs are driven directly from the outputs of IC18 and IC19 which are shift registers loaded under CPU control by IC10 The LCD is accessed via a bi directional 4 bit port in IC10 FPGA Waveform Generation The FPGA IC221 provides the complete waveform generation system including a 38 bit phase accumulator for DDS operation a programmable divide by n register for arbitrary waveform playback a 16 segment waveform sequencer trigger gate control logic 20 bit re loadable burst counter multi instrument phase synchronisation logic and an 8 bit 16 port bi directional MPU interface Access is provided to the waveform RAM to allow the patterns to be written and the Sync and Cursor Marker output signals are generated All internal operations of the FPGA are clocked by the signal ARBCLK Note that if this signal is interrupted it is possible for the FPGA to become non functional requiring the FPGA be completely reset The clock could be interrupted by a fault condition or by setting the CLOCK BNC to INPUT and then providing an unacceptable clock An unacceptable clock is any signal which
16. for two seconds and then revert to the UTILITY menu If any keys other than 0 9 are pressed while entering the password the message ILLEGAL PASSWORD will be shown Using the Password to Access Calibration or Change the Password With the password set pressing calibration onthe UTILITY screen will now show ENTER PASSWORD 18 When the correct password has been entered from the keyboard the display changes to the opening screen of the calibration routine and calibration can proceed as described in the Calibration Routine section If an incorrect password is entered the message INCORRECT PASSWORD is shown for two seconds before the display reverts to the UTILITY menu With the opening screen of the calibration routine displayed after correctly entering the password the password can be changed by pressing password soft key and following the procedure described in Setting the Password If the password is set to 0000 again password protection is removed The password is held in EEPROM and will not be lost when the memory battery back up is lost In the event of the password being forgotten contact the manufacturer for help in resetting the instrument Calibration Routine The calibration procedure proper is entered by pressing continue on the opening Calibration screen pressing exit returns the display to the UTILITY menu Pressing tests calls a menu of basic hardware checks used at production test which are self explanatory At
17. overrides the internal clock but produces a replacement which is less than 9MHz or greater than 10 5MHz This would happen if for example a DC voltage gt 2V was connected to the clock input 15 Trigger Generator This is created by a counter timer in IC10 The counter timer produces a squarewave in the range 100kHz to 0 005Hz The FPGA IC221 may be set to use this as the internal trigger Power Supply The transformer has two separate secondaries one provides 15V by IC30 and IC31 the other provides 5V by low drop out regulator IC32 and 5V by IC33 The display backlight is driven by a current source made up of Q22 and associated components and is approximately 150mA IC34 provides local regulation for the analogue IC204 provides local regulation for the VCO IC226 provides local regulation for the PLL PJS is a test point for the supply rails Four PCB mounted fuses protect the transformer secondaries under fault conditions Required values measured PJ5 pin 1 5VCPU 0 2V pin 2 OV pin 3 5V 0 2V pin 4 15V 0 6V pin 5 5VA 0 2V pin 6 15V 0 6V Waveform DAC and Filters IC210 is a high speed 12 bit DAC whose data is latched on the rising edge of DACCLK The output current is 20mA fullscale giving 1Vp p into 50Q from OV to 1V The DAC has an internal 1 23V 1 27V to 1 17V reference R218 sets the full scale output current An internal control amplifier mirrors this with respect to the 5
18. the start The Hold input may be enabled independently for each channel Input Impedance Ref Clock In Out Set to Input Set to Output Set to Phase Lock 10kQ Input for an external 10MHz reference clock TTL CMOS threshold level Buffered version of the internal 10MHz clock Output levels nominally 1V and 4V from 50Q Used together with SYNC OUT on a master and TRIG IN on a slave to synchronise phase lock two separate generators INTER CHANNEL OPERATION Inter channel Modulation The waveform from any channel may be used to Amplitude Modulate AM or Suppressed Carrier Modulate SCM the next channel Alternatively any number of channels may be Modulated AM or SCM with the signal at the MODULATION input socket Carrier frequency Carrier waveforms Modulation Types AM SCM Modulation source Frequency Range Internal AM Depth Resolution Carrier Suppression SCM External Modulation Signal Range SCM Entire range for selected waveform All standard and arbitrary waveforms Double sideband with carrier Double sideband suppressed carrier Internal from the previous channel External from Modulation input socket The external modulation signal may be applied to any number of channels simultaneously DC to gt 100 kHz 0 to 105 1 gt 40dB VCA Approximately 1V pk pk for 100 level change at maximum output Approximately 1Vpk for maximum output Inte
19. 100 23105 2130 23105 2150 23105 2180 23105 2200 23105 2220 23105 2240 23105 2270 22 Description HEADER 4WAY STR SIL STD HEADER 2 WAY STRAIGHT 156P HEADER 4 WAY STRAIGHT 156P HEADER 6 WAY STRAIGHT 156P SKT 9W R A D TYPE CLIP IN HEADER 6WAY STR SIL STD HEADER 20 WAY 2X10 STR SKEL HEADER 34 WAY 2X17 STR SKEL RES SM0805 1ROOF W1 RES SM0805 2R20F W1 RES SM0805 6R80F W1 RES SM0805 10ROF W1 RES SM0805 21R5F W1 RES SM0805 51ROF W1 RES SM0805 62ROF W1 RES SM0805 68ROF W1 RES SM0805 82ROF W1 RES SM0805 100RF W1 RES SM0805 110RF W1 RES SM0805 130RF W1 RES SM0805 150RF W1 RES SM0805 180RF W1 RES SM0805 215RF W1 RES SM0805 220RF W1 RES SM0805 470RF W1 RES SM0805 510RF W1 RES SM0805 620RF W1 RES SM0805 680RF W1 RES SM0805 1KOOF W1 RES SM0805 1K30F W1 RES SM0805 1K50F W1 RES SM0805 1K80F W1 RES SM0805 2KOOF W1 RES SM0805 2K20F W1 RES SM0805 2K40F W1 RES SM0805 2K70F W1 Position TP200 PJ3 7 200 PJ11 12 PJ13 PJ8 PJ1 PJS PJ6 PJ2 4 R276 R275 R274 R25 R204 273 R200 237 238 239 244 253 278 300 R219 R247 250 272 277 R269 R7 225 227 229 230 249 R48 51 251 266 R58 62 R201 213 216 R220 294 309 R248 271 R3 59 223 312 R36 37 252 281 293 R226 297 R24 307 R311 R5 10 27 33 34 56 57 60 61 202 218 228 304 305 R268 R292 R267 291 R222 231 287 R280 R19 28 243 R18 22 26 232 299 PCB ASSY MAIN 44912 0720 continued
20. 101 20213 0040 20234 0012 20234 0027 20234 0029 20612 0011 20661 0219 20662 0201 20662 0520 22315 0232 22315 0233 Description CABLE COAX 50Q 2 6MM RG316 U WASHER M4 ZPST WASHER M3 SHK PROOF I T ZPST WASHER M3 SPRING SCREW NO 6 X 3 8 RFLNGPZ ST AB SCREW NO6 X 3 8 NIB HDPZ ST AB NUT M3 ZPST CAPTIVE NUT SPIRE NO 6 SCREW M3 X 8 PNHDPZ ZPST SCREW M3 X 6 PNHDPZ ZPST SCREW M4 X 12 PNHDPZ ZPST WASHER FIBRE M3 SPACER HEX M3 x 15 NPBR BRACKET PLAS FOOT 3786 7001 FOOT PVC PV2629 BLACK FUSE 250MA TL HRC S F FUSE 500MA TL HRC S F Position EARTH TRANSFORMER MAINS INLET EARTH EARTH EARTH TRANSFORMER PJ1 3 11 MAIN Position BNC TO PCB MAIN PJ202 RUBBER FEET CHASSIS F PANEL CHASSIS SPACERS PCB SPACERS FRONT PANEL CHASSIS REAR PANEL CASE UPPER FRONT PANEL CHASSIS CHASSIS CHASSIS SPACERS PCB SPACERS FEET PCB SPACERS 230V VERSIONS 115V VERSIONS 27 CASING AND OTHER ITEMS continued Part Number 22491 0120 22491 0270 22491 0040 22469 0203 22575 0202 22575 0204 22575 0206 33171 0130 33537 0900 33537 0910 43171 1430 43171 2250 48584 0221 28 Description MAINS LD 2M ST IEC UK PLUG 5A MAINS LD 2M ST IEC EURO PLUG MAINS LD 2M ST IEC USA PL SOLDER TERMINAL PIN 18 0223K SKT2W 156 20AWG YELLOW IDT SKT4W 156 20AWG YELLOW IDT SKT6W 156 20AWG YELLOW IDT SPRING FOOT CASE UPPER CASE LOWER CONN ASSY GPIB MAIN 20W CONN ASSY DIS MAIN 34W CONN ASSY RS232 PC SCRND
21. 22 C75 TIP3Q 2288 1 4882 16V BACKL IGHT PJB 3 OH E FS1 1 BAT ps p BW 15V 33 i SK5 LM337 5 10 BVCPU Main Pcb Sheet 4 of 4 Power Supplies
22. 285 av PT rd ADB35 3 3 R256 RL281 A RL2801 B RL202 A RL202 B 11 2 n sig 5 2808 5 2808 Ss aja ara Ba R260 BA 8283 R264 27 9 2821 5vA 5 B t E MAIN FB203 1a ATI 41RZ 4182 4182 293 5377 as awe 47P EB RES PJ202 2 EXTSUM 283 882 Dy 10212 1BaN l BVA 1295 R271 8 ZW ABN av s T inia 2 62 um our avo 5 m 18 43 1 1C214 C ay 1C218 B 285 av 14 Rg EA 155 R287 NE5532 4R7 14 av ES Hara R278 12 3 z DCOFFSET FUSIBLE 58 51 Y 5 4 m 298 ev 83 av 9 1aN R273 82 L3 2185 5 Jai NS 8 ay BVA Joo SUMAT5 SUMOFF av 5 C313 16 3 a 1aaN vDD 51 SUMAT SUM 8 56 58 9 SUMAT2 ER 7 6 MUL TOFSET VEE EP 80288 203 RL205 80281 80282 80284 UNREG R275 ay 2 2 sa av 1C213 B C288 3 1C213 C TaaN 13 B 1 eS 14 5 FILT ay 12 7 ILT 6 AP Main Pcb Sheet 2 of 4 S SUMAT4 IC216 B 8 549 j ain ee O av 0201 278 0202 C278 0283 0284 8299 0285 BC549 1 88 8C549 1 88 8 549 8C549 2 7 8 549 Analogue Section WAVEFORM GENERATION AND MEMORY
23. 2M Position UK VERSIONS EURO VERSIONS USA VERSIONS DISPLAY CABLE PJ3 7 11 12 200 ON MAIN PJ13 ON MAIN PJ8 ON MAIN Component Layouts Main Pcb 15222 15223 1 12 15225 15224 IC221 508 R2 m CETTE 13 64 P ces 28 29 F8200 un TP202 1c27 ello 10115 El R53 R54 R154 o e Y Y N 3066 PJ2 5 S 5 26283 RP1 g u X a PJ4 a gt IC7 BATT LK2 Keyboard Pcb aie K36 18 K18 9 c Ka J K17 K14 i K16 K44 K13 K45K38 K15 K26 K32 22 i K2 K23 GP
24. 315 0453 22573 0041 22573 0048 Description ADHESIVE MTG PADS 25 x 12MM WASHER SIL PAD TO220 WASHER SIL PAD TO220 PLAIN CLIP GP02 FOR PCB MTG H SINKS HEATSINK PCB MTG 38MM PLAIN HEATSINK PCB MTG 50MM PLAIN HEATSINK TO220 CLIP ON 29DEG W BATTERY 3V LITH 20MM BUTTON BEAD FERRITE LEADED INDUCTOR 2 7UH INDUCTOR 2 07UH BLK INDUCTOR 2 0UH WHT INDUCTOR 1 78UH GRN INDUCTOR 1 545UH RED INDUCTOR 1 2UH INDUCTOR 1 322UH YEL INDUCTOR 1 157UH RED INDUCTOR 1 06UH BLUE INDUCTOR 0 47UH RELAY TYPE 53 5 24V RELAY TYPE 47 24VDC FUSE 500mAT SUBMIN PCB MNT FUSE 1 5AT SUBMIN PCB MTG HEADER 2WAY STR SIL STD GOLD HEADER 3WAY STR SIL STD GOLD Parts List Position SW1 K5 12 20 21 30 31 48 K1 2 4 13 19 22 29 32 47 49 R1 3 5 11 12 VR3 LD1 5 11 Position FOR BATTERY FOR SK200 FOR SK2 FOR SK2 5 200 SK200 FOR IC220 SK2 3 4 5 SK8 BATT FB1 200 206 L208 L205 L206 L207 L209 L204 L201 L202 L203 L200 RL201 202 RL200 203 204 205 FS3 4 FS1 2 LK1 2 TP1 TP201 202 PJ202 CENTRE PIN REMOVED 21 PCB ASSY MAIN 44912 0720 continued Part Number 22573 0070 22573 0202 22573 0204 22573 0206 22574 0450 22575 0038 22575 0065 22575 0100 23105 0010 23105 0022 23105 0068 23105 0100 23105 0215 23105 0510 23105 0620 23105 0680 23105 0820 23105 1100 23105 1110 23105 1130 23105 1150 23105 1180 23105 1215 23105 1220 23105 1470 23105 1510 23105 1620 23105 1680 23105 2
25. CB DAC IC SM MC145170D IC SM MC12148D IC V REG 78L05 TO92 IC V REG 7815 TO220 IC V REG 7915 T0220 IC V REG LM337 TO220 IC V REG L4941BV IC SM 4051 IC SM 4094 IC SM 74HC4052 IC SM 74HC4053 IC SM 74HCTOO IC SM 74HCT 14 IC SM 74HC00 IC SM 74HC32 IC SM 74HC240 IC SM 74HC373 IC SM 64180 IC SM 14C88 IC SM 14C89 IC 2704001 512Kx8 EPROM IC SM 93C46 1K 64x16 EEPR IC SM 32KX8 RAM 15ns IC SM XCS10 4TQ144C IC SM XCS05 3VQ100C IC SM 128Kx8 RAM 70ns Position IC220 IC16 200 IC209 IC219 IC25 216 IC29 115 IC207 IC215 IC27 IC208 IC210 IC206 IC203 IC108 204 226 IC30 IC31 IC33 IC32 34 IC28 IC18 19 IC211 212 217 IC213 214 IC202 IC11 21 IC22 IC14 15 20 IC23 IC12 13 IC3 IC1 IC2 IC4 IC17 IC222 225 IC221 IC10 IC5 9 25 PCB ASSY MAIN 44912 0720 continued Part Number 28151 0010 28502 0020 28515 0070 31331 9030 35555 3210 Description BUZZER RESONATOR CERAMIC 12MHZ OSC MODULE 10MHz VCXO SCREEN PCB MOUNT PCB MAIN FRONT PANEL ASSY Part Number 20030 0263 20030 9201 20030 9202 20038 9501 20065 0090 20210 0104 20234 0027 20234 0040 20612 0011 20620 0010 22219 0090 22573 0056 22575 0202 22575 0204 22588 0004 26100 0160 31711 0180 33331 7210 33331 7290 37113 2030 37151 0430 43171 1400 43171 1401 43171 2210 26 Description WASHER M3 ZPST WASHER 6BA x 1 32in FIBRE WASHER 6BA x 1 16in FIBRE WASHER M3 SPRING SCREW K22 X 5 PT L
26. IB Pcb m 8 mace L 30 Circuit Diagrams 31 PJ5 17 PJ5 8 PJ5 8 PJ5 7 PJ5 6 PJ5 5 PJ5 11 PJ5 18 PJ5 12 PJ5 18 PIS 19 PJ5 20 PJ5 21 PJ5 22 PJ5 23 PJ5 24 PJ5 1 PJ5 2 PJS 3 PJ5 4 PJ5 13 PJ5 14 PJ5 15 PJ5 16 PJ5 26 SHELL or CY N CY SJ Oy M CY SJ Oy V CY VY LS161 GPIBINT 5VCPU 4 MN PJ4 U ry PJ4 RZ 6MHZ OPA MERIT MN PJ4 U PJ4 MN PJ4 vcPU 0 BSF Fls 55 PI B S BSL AP gt AR PRA 22 Let m 87 4 18 6 Hr D5 APA D4 4 pis 53 p14 D a ry PJ4 P 25AC CSD GPIB INTERFACE PCB 1531 SN75162 1033 5 18 44812 0258 eee 2 3 20119 25 REN 3 4 19 18 24 SPC E BA 4 5 18 17 38 NDAC NDAC vi 171161 37 TAA NRF D 16 15 38 RST OKs 7 8 15 14 39 DAV DMAAK 8 EQI 3 epi 3 14 26 ATN 282 ATN DMARQ 8 3 27 SRO an iNT O 5VCPU SC TE DC LT BVCPU 20 22 20 s oO 1 12 2 31 0122 123 1 e 2 32 C52 54 2 ui 192N ner GND GND A gt i m z 15 1 852 A TR3 PE RS1 Q 1532 TE PE asa VCPU O 2 19
27. K he dies rra REF av RM 152998 og av 232 C240 C246 3 LM324 8 2 39P 33P BVPLL 11 1 SUMOFST E L201 1282 L203 R225 P A CS 1 322 8 1 157UH 1 BBUH 8287 18k BVCPU av i 1 mens 1 3 no n 3 nnn 1 3 nn n E av av 1 23V TEYA cesto DAC REF DACCLK RL20B A 6 Ls z Ls z Ls 7 37 DACC 4 RE 258 257 DACD as MUL TOFSET 212 8 av 510 5 33P NOT FITTED 1 aN D EUD 8 5628 0 47K C233 C235 C237 C241 C247 32 LOAD 2 150P 56 12 Jioc av E234 C248 n226 REF REF REF REF WAVOFST BP2 33P INA INB INC IND 1C218 1C211 DEED HI5735 4852 284 5 5VA M 1C289 D LM324 1 4 12 av C235 C238 C238 C243 C245 C248 354 5 Tau om ES 88 88 56P 88 47P feuP I aa Mi av ay 28 R228 C251 C252 33P 255 4 3 288 1 54BUH av RL203 A QQ FILT 8 8 7 mmm C253 REF3 3V 4 Y mmm 330P FILTH 5245 1C214 A aep 4853 IC214 B A 1 13 av Y1 14 v1 IC218 A z ES e z ES a 2 15V0PA Y w M NE5532 1 1a av 11 me 282 WAVOFST iau C283 5206 5 C262 ay ae 180N 5287 _ p aan 10217 T IC213 D F te av FUSIBLE 82 11 1C280 A ay 3238 248 R267 av av Bt 15 1K8 Ee C318 244 ta M2 7 47 51 14 lu 8388 T R268 51 1C219 0286 3 TP201 Mt 1 i xt x2 z A av 5285 5285 8 av L 1 218 R309 8655 av
28. Linearity Error Sine Cosine Haversine Havercosine 0 1mHz to 16 MHz 0 1mHz or 7 digits 10 ppm for 1 year Typically lt 1 ppm C 2 5mV to 10Vp p into 500 lt 0 1 THD to 100kHz lt 65dBc to 20kHz lt 50dBc to 1MHz lt 35dBc to 10MHz lt 30dBc to 16MHz lt 65dBc to 1MHz lt 65dBc 6dB octave 1MHz to 16MHz 1mHz to 16MHz 1mHz 4 digits 1 digit of setting 2 5mV to 10Vp p into 500 lt 25ns 0 1mHz to 100kHz 0 1mHz or 7 digits 10 ppm for 1 year 2 5mV to 10Vp p into 500 lt 0 1 to 30 kHz 0 1mHz to 100kHz 0 1mHz 7 digits 10 ppm for 1 year 2 5mV to 10Vp p into 500 lt 0 1 to 30 kHz Pulse and Pulse Train Output Level Rise and Fall Times Period Range Resolution Accuracy Delay Range Resolution Width Range Resolution 2 5mV to 10Vp p into 500 lt 25ns 100ns to 100s 4 digit 1 digit of setting 99 99s to 99 99s 0 002 of period or 25ns whichever is greater 25ns to 99 99s 0 002 of period or 25ns whichever is greater Note that the pulse width and absolute value of the delay may not exceed the pulse period at any time Pulse trains of up to 10 pulses may be specified each pulse having independently defined width delay and level The baseline voltage is separately defined and the sequence repetition rate is set by the pulse train period Arbitrary Up to 100 user defined waveforms may be stored in the 256K point non volatile RAM Waveforms can b
29. N1442 PNHDZ NUT M2 5 ZPST SCREW M3 X 6 PNHDPZ ZPST SCREW M2 5 X 12MML PNHDPZ ZPST WASHER FIBRE M3 CLIP ENCODER KNOB SWITCH ROCKER DPST GREY HEADER 16WAY STR SIL STD SKT 2W 156 20AWG YELLOW IDT SKT 4W 156 20AWG YELLOW IDT BNC SKT BKHD 50R STANDARD LCD 20 X 4 BACK LIT BEZEL FRONT PANEL OVERLAY FRONT PANEL KEYCAP 8X3MM LIGHT GREY KNOB ENCODER LIGHT GREY CONN ASSY 2 WAY 285MM CONN ASSY 2 WAY 195MM CONN ASSY CRIMPED Position BUZZ XTL1 IC105 S205 206 Position BEZEL LCD FIXING LCD FIXING KEYBOARD PCB FRONT PANEL BEZEL FIXING LCD FIXING KEYBOARD PCB FRONT PANEL BEZEL LCD FIXING KEYBOARD PCB FRONT PANEL FOR DISPLAY MAIN PCB PJ200A 8 PJ200B PJ7 INTERFACE 1 PJ6 PJ12 200 MAIN PJ13 MAIN REAR PANEL ASSY Part Number 20037 0401 20038 9502 20063 0010 20210 0102 20213 0040 20223 9001 20236 0010 22115 0340 22520 0170 20037 0401 20038 9502 20063 0010 22588 0004 33331 7430 43171 1401 Description SOLDER TAG SHAKEPROOF 4BA WASHER M4 SPRING EARTH SCREW NO6 X 3 8 NIB HDPZ ST AB NUT M4 ZPST EARTH CAPTIVE NUT SPIRE NO 6 SCREW M3 X 8 RAISED CKHDPZ SCREW M4 X 12 TAMPERPROOF TRANSFORMER FILTER IEC INLET FUSE 1A SOLDER TAG SHAKEPROOF 4BA WASHER M4 SPRING SCREW No 6 x 3 8 NIB HDPZ ST AB BNC SKT BKHD 50R STANDARD REAR PANEL PRINTED CONN ASSY 2 WAY 195MM CASING AND OTHER ITEMS Part Number 10144 0007 20030 0266 20037 0301 20038 9501 20062 0700 20063 0010 20210 0
30. NPN BC549C IC NE527N IC SM AD8561AR IC NE5532N Position C239 247 C12 235 241 249 C236 C238 243 C48 210 213 216 218 219 221 224 225 271 288 289 290 292 320 322 C3 6 9 11 16 41 52 57 60 63 66 67 81 141 155 200 201 203 204 205 208 209 211 214 215 217 220 229 230 255 256 257 261 262 263 265 267 269 272 275 277 279 281 283 291 294 295 300 310 312 317 321 C15 C2 5 13 14 42 43 76 77 79 212 264 266 280 282 285 286 C78 80 C75 C72 73 C7 202 231 C74 C227 C228 C64 65 C226 D1 3 5 9 200 207 213 214 LED1 LD200 D10 13 D208 D14 15 D16 18 D209 212 BR1 Q22 Q1 3 6 13 Q2 4 5 14 15 20 21 200 205 IC201 IC205 IC218 PCB ASSY MAIN 44912 0720 continued Part Number 27106 0633 27106 1110 27106 1160 27106 1170 27106 1180 27106 1210 27107 0071 27151 1010 27153 1050 27153 1060 27153 1070 27158 0020 27158 0030 27160 0011 27160 0013 27160 0020 27160 0210 27160 0460 27227 0510 27227 0940 27236 0520 27236 0530 27238 0000 27238 0140 27239 0000 27239 0320 27239 2400 27239 3730 27253 0020 27253 0050 27253 0060 27400 0140 27403 0010 27410 0460 27412 0080 27412 0090 27413 0430 Description IC EL2099CT IC SM LM358M DUAL OP AMP IC SM LM324M OP AMP IC SM AD8055AR OP AMP IC SM AD8056AR OP AMP IC SM LMC662CM IC SM TLO71 BIFET OP AMP IC AD835AN IC SMLTC1257CS8 IC SM TLC5620CD DAC IC SM HI5735K
31. R53 54 154 R206 212 R155 R29 203 208 234 301 302 303 R17 R8 16 20 21 38 R15 RQ R45 52 224 R72 R70 R262 265 R40 R39 R71 R260 261 263 264 R256 259 R254 255 RP 1 3 VR200 C70 71 C1 4 50 51 206 207 C311 C233 C245 276 293 318 C8 246 248 250 251 C253 C232 234 270 319 C240 242 244 252 254 23 PCB ASSY MAIN 44912 0720 continued Part Number 23428 0560 23428 1100 23428 1150 23428 1180 23461 0015 23461 0020 23557 0612 23557 0647 23557 0658 23557 0660 23557 0664 23557 0673 23557 9122 23620 0242 23620 0246 23620 0249 23620 0252 25021 0901 25061 0200 25115 0907 25130 9201 25131 0224 25131 0227 25174 0224 25211 9302 25334 0011 25336 5590 25377 5490 27103 0041 27103 1020 27106 0517 24 Description CAP56PG 100V CER N150 P2 5 CAP 100PG 100V CER NPO P2 5 CAP 150PG 100V CER N150 P2 5 CAP 180PG 100V CER N750 P2 5 CAP SM0805 10NK 50V CER X7R CAP SM0805 100NZ 50V CER Y5V CAP 1U0 100V ELEC RE2 P2 CAP 10U 35V ELEC RE2 P2 CAP 100U 25V ELEC RE2 P2 5 CAP 2200U 16V ELEC RE2 P5 CAP 1000U 35V ELEC RE2 P5 CAP 22U 35V ELEC RE2 P2 CAP 4700U 16V ELEC RE2 P7 5 CAP 22NJ 100V P E P5 CAP 100NK 63V P E P5 CAP 330NK 63V P E P5 CAP 2N2K 63V P E P5 DIO 1N4148 B R LED T1 ROUND 3mm RED DIO 1N4002 B R DIO ZEN 6V2 W5 DIO ZEN 18V 1W3 DIO ZEN 6V8 5W DIO SM VARICAP BB148 RECTIFIER BRIDGE W02G TRAN PNP TIP30 TRAN PNP BC559C TRAN
32. TE A atz 58 31 37415 A18 3215 Ai8 3 JA ME 3 Ale 8 Ais 3 ate __57 82 LI qw ai A16 AI6 A16 A16 A16 A16 A19 56 10K A17 IC11 E T 33 13 DA 13 DA 13 DA 13 Da 13 DA 13 INTA A18 Da Da Da Da Da Da 54 14 51 14 Di 14 D 14 D1 14 D1 14 BMHZ 1 2 TRIGGER inn 35 Atg Dt Dt Dt Dt pt 48 EETBTNT 12 15 D2 15 D2 15 D2 15 D2 15 D2 5 WA Q 2 17 192 Da 7 2 Bi 1 2 53 17 TEET NE x a 4 D3 5 3 fa D4 1g 103 D4 18 gt D4 18 5 D4 18 m D4 18 E Tomo 1c14 D sa 111 37 DO 13 88 18 65 55 D5 19 o ta lie meo E AGT 38 Df za 1 55 29 D6 2g DB 20 E DS 20 ns 24 om 55 61 ag D2 21 DE D7 21 pe D7 21 DB D7 21 D7 21 D7 21 8 D3 D7 D7 87 87 87 87 15 85 Cuin 48 VPP 17 18 cst NC 52 cs NC C52 cst NC 52 cst NC 52 cst NC C52 wwoa TORT ER g oe Q p Q 28 22 h 30 c se rm 38 PET 11 53 O me 42 D5 5 38 31 22 30 22 woz z wr 66 43 06 A17 L vBAT VBAT VBAT VBAT WWD3 O wa VBAT 13 RD 57 Q Ro 44 07 18 4 4 WWD4 a MESZ RAMBSEL 5 RAMZSEL boss y 8 12 wos 2 RAM4 RAMSAVE MN RAMSAVE RAMSAVE SEE 15 11 wis R Nae BEY BVCPU POWER FAIL RESET AND BATTERY CONTROL LOGIC SAVE ps RAMSAVE wwo7 fhe VBAT 1 ed BON 11 TI 13 12 FRETZ n5 1BVA LEDLOAD 5 R14 BC CLKIN 03 10K 549 815 200 BC zMa sk 559 9888 Eid 8 6 ECS 35 RAMSAVE zMi aK 6 EDIO SHDAT 38 m 549 BIK KRDWSEL 88
33. UMAT3 138 SYNEGUT SYNC 884 WEE VEE 134 20k p21 18 7 136 138 141 P22 INTLOKEN 131 P gt av SUMAT 23 CTLEXTLOKEN ey TEEN 55 153 aa H53 SUMAT4 148 129 HOLD nez 20K 142 P28 HOLD 18M 1C28 SUMAT2 112 1528 125 meer 8 1c29 A PY suMATS 138 CTLRDRAM 5VA BUT 123 av ae 3 1C115 A yz LMC662 PLLLD CTLRORAMA 4 MC662 55 AMPL PLLC P31 CTLRDRAML 4d 8 8 g 1722 HOLDHI HBEBHI EN C155 DACCLK _ DACCLK CPULOCK 5 i av 1 1 137 SHDACCLK 5 av 8 af 5 6 2 7 E 11 SHDACDAT DATA aise VOUT 13 17 AE 8 45 1 24 855 tak 27 135 45 55 64 71 81 lot taaltia SHDACLOAD SHDAEPOAD Dos A DCOFFSET GND gi ICZI F IC f5 B 11 GND HCT14 BV 662 So ep IB cs3 ces av SHEN BOE 1 29 8 q E LMC662 av c6a av 1 a p Nor FITTED Main Pcb Sheet 3 of 4 Waveform FPGA and Memory IC38 7815 SK2 15V 15VA 15VOPA 1 P 0 P 1888 35 L49331 yi 3 240V 0 P ia cap D18 5 1gau 6v8 25V 5W FS4 Po I P m v 120v 588m a SK3 1031 O 1318 1BVA 15VDPA me FS2 pia UNREGBV PIB 2 1 5AT asya LO PIB 6 5VCPU p A D16 R72 5VCPU 3R9 O PJ5 1 PJ5 3 C74 O FB L 3 4788 5V PJ5 4 16V pO ABV PJ5 2 0
34. V rail L201 L202 L203 and associated components form the 16MHz 7 stage elliptic filter The inductors are factory set before board assembly and must not be adjusted L204 provides sinx x correction and is adjusted at initial calibration L205 L206 L207 and associated components form the 10MHz 7 stage elliptic filter The inductors are factory set before board assembly and must not be adjusted L208 provides sinx x correction and is adjusted at initial calibration L209 C252 and C253 form a Bessel filter L209 is also factory preset Amplitude Control Sum and Modulation IC215 is a 4 quadrant multiplier driven differentially via IC211 The main signal is at M and is OV to 1V a dc reference M1 of half this is generated by IC200 A Amplitude is controlled by IC218 A with the output set to maximum the voltage at its output is approximately 1V External AM is selected by IC214 A and is summed with the amplitude control voltage at the input of IC218 A Sum is selected by IC214 C and the external signal is summed at the multiplier output via its Z input IC212 and IC213 form the sum input attenuator Amplifiers and Attenuators 16 With the amplitude at maximum the signal at the output of the multiplier is approximately 1Vp p IC219 gives a gain of 5 5 to give 5 5Vp p and IC220 gives a gain of 3 8 to give 20Vp p IC218 B provides DC offset for the main output when set to maximum i e 10V IC218 B s output will be approximately
35. WAVETEK MAINTENANCE MANUAL Model 39A 40MHz Arbitrary Waveform Generator October 2005 Issue 1 This document contains information proprietary to Wavetek and is provided solely for instrument operation and maintenance The information in this document may not be duplicated in any manner without the prior approval in writing from Wavetek Wavetek Datron Test and Measurement Division Hurricane Way Norwich Norfolk NR6 6JB U K CE Tel 44 1603 256600 Fax 44 1603 256688 Table of Contents Specifications Safety 10 Installation 11 General 12 Circuit Descriptions 13 Calibration 18 Parts List 21 Component Layouts 29 Circuit Diagrams 31 Specifications Note This specification covers the whole series which includes 2 and 4 channel instruments the interchannel specifications only apply to the multi channel instruments Specifications apply at 18 28 C after 30 minutes warm up at maximum output into 500 WAVEFORMS Standard Waveforms Sine square triangle DC positive ramp negative ramp sin x x pulse pulse train cosine haversine and havercosine Range Resolution Accuracy Temperature Stability Output Level Harmonic Distortion Non harmonic Spurii Square Range Resolution Accuracy Output Level Rise and Fall Times Triangle Range Resolution Accuracy Output Level Linearity Error Ramps and Sin x x Range Resolution Accuracy Output Level
36. YNC OUT socket OUTPUTS Main Output One for each channel Output Impedance Amplitude Amplitude Accuracy Amplitude Flatness DC Offset Range DC Offset Accuracy Resolution 50Q 5mV to 20Vp p open circuit 2 5mV to 10Vp p into 50Q Amplitude can be specified open circuit hi Z or into an assumed load of 50Q or 6000 in Vpk pk Vrms or dBm 2 1mV at 1kHz into 500 0 2dB to 200 kHz 1dB to 10 MHz 2 5dB to 16 MHz 10V DC offset plus signal peak limited to 10V from 500 Typically 3 10mV unattenuated 3 digits or 1mV for both Amplitude and DC Offset Sync Out One for each channel Multifunction output user definable or automatically selected to be any of the following Waveform Sync all waveforms square wave with 50 duty cycle at the main waveform frequency or a pulse coincident with the first few points of an arbitrary waveform Position Markers Arbitrary only Any point s on the waveform may have associated marker bit s set high or low Burst Done Produces a pulse coincident with the last cycle of a burst Sequence Sync Produces a pulse coincident with the end of a waveform sequence Trigger Selects the current trigger signal Useful for synchronizing burst or gated signals Sweep Sync Outputs a pulse at the start of sweep to synchronize an oscilloscope or recorder Phase Lock Out Used to phase lock two generators Produces a positive edge at the 0 phase point Output Sign
37. al Level TTL CMOS logic levels from typically 50Q Cursor Marker Out Adjustable output pulse for use as a marker in sweep mode or as a cursor in arbitrary waveform editing mode Can be used to modulate the Z axis of an oscilloscope or be displayed on a second scope channel Output Signal Level Adjustable from nominally 2V to 14V normal or inverted adjustable width as a cursor Output Impedance 6000 typical INPUTS Trig In Frequency Range DC 1MHz Signal Range Threshold nominally TTL level maximum input 10V Minimum Pulse Width 50ns for Trigger and Gate modes 50us for Sweep mode Polarity Selectable as high rising edge or low falling edge Input Impedance 10kQ Modulation In Frequency Range DC 100kHz Signal Range VCA Approximately 1V pk pk for 10096 level change at maximum output SCM Approximately x 1Vpk for maximum output Input Impedance Typically 1 KQ Sum In Frequency Range DC 8 MHz Signal Range Approximately 2 Vpk pk input for 20Vpk pk output Input Impedance Typically 1 Hold Holds an arbitrary waveform at its current position A TTL low level or switch closure causes the waveform to stop at the current position and wait until a TTL high level or switch opening which allows the waveform to continue The front panel MAN HOLD key or remote command may also be used to control the Hold function While held the front panel MAN TRIG key or remote command may be used to return the waveform to
38. alibration mode lt nrf gt represents the calibration password The password is only required with CALIBRATION START and then only if a non zero password has been set from the instrument s keyboard The password will be ignored and will give no errors at all other times It is not possible to set or change the password using remote commands CALADJ lt nrf gt Adjust the selected calibration value by lt nrf gt The value must be in the range 100 to 100 Once an adjustment has been completed and the new value is as required the CALSTEP command must be issued for the new value to be accepted CALSTEP Step to the next calibration point For general information on remote operation and remote command formats refer to the Instrument instruction manual remote operation sections 20 PCB ASSY KEYBOARD 44912 0710 Part Number 22224 0010 22226 0101 22226 0150 23202 1680 23382 2470 25061 0200 35555 3010 43171 2230 Description ENCODER ROT 36 POS W O DETENT KEYSWITCH ALPS SKHHBW KEYSWITCH LIGHT GREY RES 680RF W25 MF 50PPM RES PS H 5KO CERMET MIN LED T1 ROUND 3mm RED PCB KEYBOARD CONN ASSY KB MAIN 34W PCB ASSY MAIN 44912 0720 Part Number 10366 9701 20613 0006 20613 0007 20670 0135 20670 0310 20670 0320 20670 0340 22010 0610 22040 0920 22042 0260 22042 0261 22042 0262 22042 0263 22042 0271 22042 0290 22042 0291 22042 0292 22042 0293 22042 0300 22240 0020 22240 0050 22315 0450 22
39. clocked at 12MHz XTL1 The MPU provides 20 memory address lines which are used to provide access to a total of 1M bytes of memory this comprising a 512k byte EPROM 1048 and 5 128k byte rams IC5 9 The EPROM is located at address 00000h and extends to 07FFFFh The top 128k bytes are shared by IC5 and the selection of ram or EPROM is controlled by the FPGA 610 The other 4 rams are located at addresses 080000h to OFFFFFh IC9 is the system ram which contains all the essential variables and work areas including the software stack IC5 8 is the non volatile store for all the arbitrary waveforms and is not used for any other purpose The MPU selects between the memory devices via address decoders located in the FPGA at IC10 The RS232 interface is provided directly by the MPU and is buffered to the rear panel connector PJ1 by IC1 and IC2 One of the counter timers provides a constant 0 5ms tick to the MPU which is used to time all the housekeeping functions e g keyboard scan knob control as well as some generator functions e g frequency sweep The second counter timer is not used The FPGA IC10 provides the port select signals to the GPIB board Keyboard LCD and LEDs The keyboard is interrogated every 10ms This is done by reading the registers in IC12 and IC13 If a key is down then one of the transistors Q6 Q13 will be on and the corresponding bits read from 1C12 1C13 will be high The MPU decodes this to produce a key
40. d CAL 14 CH1 Not used CAL 15 CH1 Not used CAL 55 Clock calibrate Adjust for 10 00000 MHz at SYNC OUT Service Adjustments The following 3 sections contain information about adjustments which are normally done once only at the factory These may need to be repeated if a component in the relevant area is changed 19 VCO Adjustment This should not normally be necessary and L6 is sealed at the factory However if a problem is suspected or components in this circuit have been changed carry out the following test first Set the output to 10MHz squarewave and check that the voltage at TP200 3 is 9 5V to 10 5V Check LED 200 is off Only if the voltage is outside these limits should L200 be adjusted to 10 0 2V L6 core must then be resealed again to reduce phase noise caused by mechanical vibration Use only non corrosive silicon rubber VR200 Adjustment Not normally necessary Must only be adjusted with the default calibration values loaded or CALO7 set to 0128 At CALO7 adjust VR200 for OVdc 5mV Amplitude Flatness This should not normally be necessary Set to 20Vpk pk and use a 50Ohm terminator frequency to 100kHz sinewave Adjust oscilloscope to show exactly 6 divisions Frequency to 10 00000MHz and adjust L208 for exactly 6 divisions Frequency to 10 1MHz and adjust L204 for exactly 6 divisions These two adjustments should only be done using a high quality oscilloscope with a bandwidth of at least 100MHz Rem
41. e defined by front panel editing controls or by downloading of waveform data via RS232 or GPIB Waveform Memory Size Vertical Resolution Sample Clock Range Resolution Accuracy Sequence 64k points per channel Maximum waveform size is 64k points minimum waveform size is 4 points 12 bits 100mHz to 40MHz 4 digits 1 digit of setting Up to 16 waveforms may be linked Each waveform can have a loop count of up to 32 768 A sequence of waveforms can be looped up to 1 048 575 times or run continuously Output Filter Selectable between 16MHz Elliptic 10MHz Elliptic 1OMHz Bessel or none OPERATING MODES Triggered Burst Each active edge of the trigger signal will produce one burst of the waveform Carrier Waveforms Maximum Carrier Frequency Number of Cycles Trigger Repetition Rate Trigger Signal Source All standard and arbitrary The smaller of 1MHz or the maximum for the selected waveform 40Msamples s for ARB and Sequence 1 to 1 048 575 0 005Hz to 100kHz internal dc to 1MHz external Internal from keyboard previous channel next channel or trigger generator External from TRIG IN or remote interface Trigger Start Stop Phase Gated 360 settable with 0 1 resolution subject to waveform frequency and type Waveform will run while the Gate signal is true and stop while false Carrier Waveforms Maximum Carrier Frequency Trigger Repetition Rate Gate Signal Source
42. each step the display changes to prompt the user to adjust the rotary control or cursor keys until the reading on the specified instrument is at the value given The cursor keys provide coarse adjustment and the rotary control fine adjustment Pressing next increments the procedure to the next step pressing CE decrements back to the previous step Alternatively pressing exit returns the display to the last CAL screen at which the user can choose to either save new values recall old values or calibrate again The first two displays CAL 00 and CAL 01 specify the connections and adjustment method The next display CAL 02 allows the starting channel to be chosen in multi channel instruments ignore CALO2 in this instrument and step on to CALO3 The subsequent displays CAL 03 to CAL 55 permit all adjustable parameters to be calibrated The full procedure is as follows CAL 03 CH1 DC offset zero Adjust for OV 5mV CAL 04 CH1 DC offset at full scale Adjust for 10V 10mV CAL 05 CH1 DC offset at full scale Check for 10V 3 CAL 06 CH1 Multiplier zero Adjust for minimum Volts AC CAL 07 CH1 Multiplier offset Adjust for OV 5mV CAL 08 CH1 Waveform offset Adjust for OV 5mV CAL 09 CH1 Output level at full scale Adjust for 10V 10mV CAL 10 CH1 20dB attenuator Adjust for 1V 1mV CAL 11 CH1 40dB attenuator Adjust for 0 1V 1mV CAL 12 CH1 10dB attenuator Adjust for 2 236V AC 10mV CAL 13 CH1 Not use
43. f the phase accumulator drive the lower 12 RAM address lines the upper 4 RAM address lines are held low The output waveform frequency is now determined by the size of the phase increment at each clock If each increment is the same size then the output frequency is constant if it changes the output frequency changes as in sweep mode The generator uses a 38 bit accumulator and a clock frequency which is 2 x 10 27 4878 MHz this yields a frequency resolution of 0 1 mHz Only the 12 most significant bits of the phase accumulator are used to address the RAM At a waveform frequency of FcLk 4096 6 7MHz the natural frequency the RAM address increments at every clock At all frequencies below this i e at smaller phase increments one or more addresses are output for more than one clock period because the phase increment is not big enough to step the address at every clock Similarly at frequencies above the natural frequency the larger phase increment causes some addresses to be skipped giving the effect of the stored waveform being sampled different points will be sampled on successive cycles of the waveform MPU and Memory The majority of the digital hardware in the instrument is contained in 3 LSI devices these being a MicroProcessor Unit IC3 and 2 Field Programmable Gate Arrays IC10 and IC221 The Z80180 MPU contains an 8 bit Z80 core 2x16 bit counter timers 2x8 bit serial interfaces and 8 memory management unit The MPU is
44. ment in the temperature range 5 C to 40 C 20 80 RH non condensing It may occasionally be subjected to temperatures between 5 and 10 C without degradation of its safety Do not operate while condensation is present Use of this instrument in a manner not specified by these instructions may impair the safety protection provided Do not operate the instrument outside its rated supply voltages or environmental range WARNING THIS INSTRUMENT MUST BE EARTHED Any interruption of the mains earth conductor inside or outside the instrument will make the instrument dangerous Intentional interruption is prohibited The protective action must not be negated by the use of an extension cord without a protective conductor When the instrument is connected to its supply terminals may be live and opening the covers or removal of parts except those to which access can be gained by hand is likely to expose live parts The apparatus shall be disconnected from all voltage sources before it is opened for any adjustment replacement maintenance or repair Any adjustment maintenance and repair of the opened instrument under voltage shall be avoided as far as possible and if inevitable shall be carried out only by a skilled person who is aware of the hazard involved If the instrument is clearly defective has been subject to mechanical damage excessive moisture or chemical corrosion the safety protection may be impaired and the apparatus sho
45. nd arbitrary waveforms and fixed at 27 48779MHz in the DDS mode Comparator IC205 gives TTL output levels IC206 is a PLL IC and has internal dividers for both inputs which are set by the MPU Phase comparison is done at 3kHz in PLL mode and slightly higher in DDS mode IC15 is the loop filter which drives the VCO LED2 is out when the loop is in lock Inputs and Outputs IC21 is a hex Schmitt A B D and E are used for the Trig In and Hold In inputs The Sync output has four gates in parallel IC202 IC23 is an octal 3 state buffer When Clock In Out is an output the top four buffers are enabled and the bottom four disabled When Clock In Out is an input the top four buffers are disabled and the bottom four enabled The Zmod output high is set by the three digital signals at the input of IC16 A IC16 A provides gain to give a maximum output high of 14V When Q14 is on the output is low when turned off the output goes high until D2 conducts clamping output high to the required level 17 Calibration All parameters can be calibrated without opening the case i e the generator offers closed box calibration All adjustments are made digitally with calibration constants stored in EEPROM The calibration routine requires only a DVM and a frequency counter and takes no more than a few minutes The crystal in the timebase is pre aged but a further ageing of up to 5ppm can occur in the first year Since the ageing rate decreases ex
46. ng the diagram below 4 Refit the cover and the secure with the same screws 5 To comply with safety standard requirements the operating voltage marked on the rear panel must be changed to clearly show the new voltage setting 6 Change the fuse to one of the correct rating see below 230V 115V 15 14 13 12 11 for 230V operation connect the live brown wire to pin 15 for 115V operation connect the live brown wire to pin 14 for 100V operation connect the live brown wire to pin 13 Fuse Ensure that the correct mains fuse is fitted for the set operating voltage The correct mains fuse types are for 230V operation 250 mA T 250V HRC for 100V or 115V operation 500 mA T 250V HRC To replace the fuse disconnect the mains lead from the inlet socket and withdraw the fuse drawer below the socket pins Change the fuse and replace the drawer The use of makeshift fuses or the short circuiting of the fuse holder is prohibited Mains Lead When a three core mains lead with bare ends is provided it should be connected as follows Brown Mains Live Blue Mains Neutral Green Yellow Mains Earth WARNING THIS INSTRUMENT MUST BE EARTHED Any interruption of the mains earth conductor inside or outside the instrument will make the instrument dangerous Intentional interruption is prohibited The protective action must not be negated by the use of an extension cord without a protective conductor Mounting Thi
47. ote Calibration Calibration of the instrument may be performed over the RS232 or GPIB interface To completely automate the process the multimeter and frequency meter will also need to be remote controlled and the controller will need to run a calibration program unique to this instrument The remote calibration commands allow a simplified version of manual calibration to be performed by issuing commands from the controller The controller must send the CALADJ command repeatedly and read the dmm or frequency meter until the required result for the selected calibration step is achieved The CALSTEP command is then issued to accept the new value and move to the next step While in remote calibration mode very little error checking is performed and it is the controllers responsibility to ensure that everything progresses in an orderly way Only the following commands should be used during calibration WARNING Using any other commands while in calibration mode may give unpredictable results and could cause the instrument to lock up requiring the power to be cycled to regain control CALIBRATION lt cpd gt nrf The calibration control command lt cpd gt can be one of three sub commands START Enter calibration mode this command must be issued before any other SAVE calibration commands will be recognised Finish calibration save the new values and exit calibration mode ABORT Finish calibration do not save the new values and exit c
48. ponentially with time it is an advantage to recalibrate after the first 6 month s use Apart from this it is unlikely that any other parameters will need adjustment Calibration should be carried out only after the generator has been operating for at least 30 minutes in normal ambient conditions Equipment Required e 3 digit DVM with 0 25 DC accuracy and 0 5 AC accuracy at 1kHz e Frequency counter capable of measuring 10 00000MHz The DVM is connected to the MAIN OUT of each channel in turn and the counter to any SYNC OUT Frequency meter accuracy will determine the accuracy of the generator s clock setting and should ideally be 1ppm Calibration Procedure The calibration procedure is accessed by pressing the calibration soft key on the UTILITY screen CALIBRATION SELECTED Are you sure password tests exit continue The software provides for a 4 digit password in the range 0000 to 9999 to be used to access the calibration procedure If the password is left at the factory default of 0000 no messages are shown and calibration can proceed as described in the Calibration Routine section only if a non zero password has been set will the user be prompted to enter the password Setting the Password On opening the Calibration screen press the password soft key to show the password screen ENTER NEW PASSWORD Enter a 4 digit password from the keyboard the display will show the message NEW PASSWORD STORED
49. r channel Analog Summing Waveform Summing sums the waveform from any channel into the next channel Alternatively any number of channels may be summed with the signal at the SUM input socket Carrier frequency Entire range for selected waveform Carrier waveforms All standard and arbitrary waveforms Sum source Internal from the previous channel External from SUM IN socket Frequency Range DC to gt 8MHz External Signal Range Approximately 5Vpk pk input for 20Vpk pk output Inter channel Phase locking Two or more channels may be phase locked together Each locked channel may be assigned a phase angle relative to the other locked channels Arbitrary waveforms and waveform sequences may be phase locked but certain constraints apply to waveform lengths and clock frequency ratios With one channel assigned as the Master and other channels as Slaves a frequency change on the master will be repeated on each slave thus allowing multi phase waveforms at the same frequency to be easily generated DDS waveforms are those with 7 digits of frequency setting resolution while Non DDS waveforms have 4 digits Phase Resolution DDS waveforms 0 1 degree Non DDS waveforms 0 1 degree or 360 degrees number of points whichever is the greater Phase Error All waveforms lt 10ns The signals from the REF IN OUT socket and the SYNC OUT socket can be used to phase lock two instruments where more than 4 channels are required Inter channel Triggering
50. s instrument is suitable both for bench use and rack mounting It is delivered with feet for bench mounting The front feet include a tilt mechanism for optimal panel angle Arack kit for mounting in a 19 rack is available from the Manufacturers or their overseas agents 11 General Service Handling Precautions Service work or calibration should only be carried out by skilled engineers Please note the following points before commencing work Most of the integrated circuits are CMOS devices and care should be taken when handling to avoid damage by static discharge Also most devices are surface mounted miniature components with very fine leads on small pitches These components must be removed and replaced with great care to avoid damage to the PCB It is essential that only the proper tools and soldering equipment as recommended for surface mount components are used The decoupling capacitors associated with the integrated circuits are surface mounted on the solder side of the PCB Dismantling the Instrument 12 WARNING Disconnect the instrument from all voltage sources before it is opened for adjustment or repair If any adjustment or repair of the opened instrument is inevitable it shall be carried out only by a skilled person who is aware of the hazards involved 1 Remove the six screws retaining the top cover 2 The rear panel may be removed as follows Disconnect the grey ribbon cable from PJ6 on the GPIB PCB Invert
51. the instrument and remove the three screws securing the rear panel and the nuts securing the 9 way RS232 connector to the rear panel The panel may now be tilted back to allow access If the panel is to be completely removed the connectors must be removed from PJ3 PJ7 PJ8 and PJ11 the blue and brown wires disconnected from the mains inlet filter and the blue and brown wires unsoldered from the mains transformer Cut the ties holding the cable assembly to the side instrument chassis The panel is then completely free of the instrument 3 The front panel assembly may be removed as follows Remove the connectors from PJ2 PJ4 PJ12 PJ13 and PJ200 and desolder the screened cable from PJ202 Remove the two nuts and bolts in the sides and two screws in the bottom of the instrument securing the front panel assembly The panel may now be drawn clear of the instrument 4 Main pcb removal Remove all connectors from the pcb and desolder the screened cable from PJ10 Tilt the rear panel away as in 2 above Remove six screws and lift away the main pcb When re assembling the instrument ensure that all fixings use the correct fastenings General Circuit Descriptions The following sections should be read with reference to the block diagram and the circuit diagrams Trig Out From Previous Channel Trig Out From Next Channel Common Hold In 9 Common Cursor Marker Out Common CPU DC Offset Control DAC s Common E
52. to 0 1Hz The frequency of the waveform is clock frequency waveform length thus allowing short waveforms to be played out at higher repetition rates than long waveforms e g the maximum frequency of a 4 point waveform is 40e6 4 or 10MHz but a 1000 point waveform has a maximum frequency of40e6 1000 or 40kHz 16 Bits RAM ADDRESS CLOCK 0 1Hz to 30MHz Arbitrary waveforms have a user defined length of 4 to 65536 points Squarewaves use a fixed length of 2 points and pulse and pulse train have their length defined by the user selected period value DDS Mode 14 In DDS mode Direct Digital Synthesis all waveforms are stored in RAM as 4096 points The frequency of the output waveform is determined by the rate at which the RAM addresses are changed The address changes are generated as follows The RAM contains the amplitude values of all the individual points of one cycle 360 of the waveform each sequential address change corresponds to a phase increment of the waveform of 360 4096 Instead of using a counter to generate sequential RAM addresses a phase accumulator is used to increment the phase 38 Bit 12Bit 16 Bit RAM ADDRESS 4 Top Bits PHASE 38 Bit CLOCK sets to 0000 INCREMENT REGISTER PHASE ACCUMULATOR On each clock cycle the phase increment which has been loaded into the phase increment register by the CPU is added to the current result in the phase accumulator the 12 most significant bits o
53. uld be withdrawn from use and returned for checking and repair Make sure that only fuses with the required rated current and of the specified type are used for replacement The use of makeshift fuses and the short circuiting of fuse holders is prohibited This instrument uses a Lithium button cell for non volatile memory battery back up typical life is 5 years In the event of replacement becoming necessary replace only with a cell of the correct type i e 3V Li MnO 20mm button cell type 2032 Exhausted cells must be disposed of carefully in accordance with local regulations do not cut open incinerate expose to temperatures above 60 C or attempt to recharge Do not wet the instrument when cleaning it and in particular use only a soft dry cloth to clean the LCD window The following symbols are used on the instrument and in this manual Caution refer to the accompanying documentation incorrect operation may damage the instrument terminal connected to chassis ground mains supply OFF mains supply ON o alternating current Installation Mains Operating Voltage Check that the instrument operating voltage marked on the rear panel is suitable for the local supply Should it be necessary to change the operating voltage proceed as follows 1 Disconnect the instrument from all voltage sources 2 Remove the screws which retain the top cover and lift off the cover 3 Change the transformer connections followi
54. xt Trig Sync Out Q Trig Out Lock Clock In Out To Waveform Other Channels FPGA Waveform RAM PLL 10MHz CLK Common VCA In SUM Common Co CLK In Out Amplitude Control Common SUM fo 0 50dB In Attenuator SUM Out From Previous Channel 16MHz O Elliptic Filter O Bessel Filter 10MHz Elliptic Filter Zero Crossing Comparator Attenuators Sum Out L pe Simplified Block Diagram Principles of Operation The instrument operates in one of two different modes depending on the waveform selected DDS mode is used for sine cosine haversine triangle sinx x and ramp waveforms Clock Synthesis mode is used for square pulse pulse train arbitrary and sequence In both modes the waveform data is stored in RAM As the RAM address is incremented the values are output sequentially to a Digital to Analogue Converter DAC which reconstructs the waveform as a series of voltages steps which are subsequently filtered before being passed to the main output connector RAM ADDRESS Main Out Output Attenuators O in Co DC Offset MAIN O P The main difference between DDS and Clock Synthesis modes is the way in which the addresses are generated for the RAM and the length of the waveform data 13 Clock Synthesis Mode In Clock Synthesis mode the addresses are always sequential an increment of one and the clock rate is adjusted by the user in the range 40MHz
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