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1. the flip flop circuit 65 and a resistor 154 in turn con nected to the emitter 156a of a PNP transistor 156 of the test supply circuit 77 The base 1565 of transistor 156 is grounded and the collector 156c thereof is connected to the base 1585 of a NPN transistor 158 The emitter 158a of transistor 158 is connected to the 5 volt bus 142 and the collector 158c thereof is connected to the collector 162c of a PNP transistor 162 The base 162b of the tran sistor 162 is connected through the resistor 160 to the flip flop circuit output conductor 153 and through a 4 117 400 20 produce different current transitions unless collector and base drive circuits 36 and 38 act as constant current sources when the devices being tested are operating in their normal manner Accordingly the circuit impe dance provided by the collector and base drive circuits 36 and 38 are selected to be so much greater than the forward junction impedances of the test devices so that when the voltages applied thereto are of proper polarity the desired above preferred currents will flow With the specifications described unsymmetrical bi polar transistors having a current gain of about 20 to 30 or more located in a circuit with a shunt impedance of a modestly low value of at least about 1 000 2 000 ohms generally pass the gain test in only one of the six possi ble positions of the test switch 18 This same transistor under the high drive test will generally test
2. 22 2 4 117 400 Sheet 5 of 6 U S Patent Sept 26 1978 P os di p 6 69 aze azs 82 82 7d PZB ER 029 2841 d Y DELI 841 6 AS 28 477 75 39V L 10A 52 OL 952 LNALNO 24 2 9 YON OL 88 98 2 a qr8 S Sheet 6 of 6 4 117 400 Sept 26 1978 U S Patent 4 117 400 2 switch is preferably provided which can connect the load and control terminal energizing and drive voltage pulses to the three terminals of a transistor or FET under test in all the different possible connection combi nations thereof so that the operator does not have to identify the various terminals of the transistor or FET device to carry out the test The low control terminal drive level is selected so that with most non bipolar transistors a properly conducting transistor with a mod est forward conduction current gain for example as low or about 20 to 30 and shunted by a not unusually low impedance would test satisfactorily in only one of the six different possible test switch positions A very marginal transistor which would pass a high level test designed to test transistors in highly shunted circuits can therefore be detected and discarded if it is found defective Also since most transistors will pass the low level test in only one test switch position by color cod ing the leads extending from the test circuit to the
3. and P1 occurring during the first polarity transition of the base drive waveform W7 are of opposite polarity respectively for properly operating NPN and PNP transistors or their equivalent conductivity type FET devices nd that similarly the pulses P2 and P2 occurring respectively for properly operating NPN and PNP transistors or their equivalent conductivity type FET devices dur ing the second polarity transition of the waveform 7 are also of opposite polarity The circuits to be de scribed amplify and inverts the waveforms W11 and WIT and sense them only during the polarity transition periods of the waveform W7 to identify properly oper ating NPN or PNP devices or FET devices of equiva lent conductivity type While this detecting circuit can accomplish this result in a number of ways as illustrated in the prefered form of the invention of FIG 2 the output of differentiating network 54 is shown connected to a detector amplifier inverter 58 which may be an operational amplifier which inverts and amplifies waveforms W11 and W17 to produce the waveforms W11 and W17 in FIG 7 This amplified and inverted output is fed to the input 62a of a gate 62 and also to the input 66a of an inverter 66 The output 66b of the inverter 66 is fed to the input 62a of a gate 62 The timing circuit 40 produces output signals fed to one or more input terminals of the gates 62 and 62 such as the inputs 60c and 60c illustrated which
4. and would be switched to a highly conductive state during the second half of this interval The test switch 18 as shown in FIG 3 has three switch sections 18 1 18 2 and 18 3 with associated wipers 18 1 18 2 and 18 3 which make contact with six associated stationery contacts interconnected in such a way that the three inputs 18a 18b and 18c of the test switch 18 are connected in six different ways to output terminals 18d 18e and 18 thereof whereby the collector and base drive waveforms are applied in the six different possible ways to the output terminals 18d 18e and 18f The output terminals 18d 18e and 18 of the test switch 18 connect respectively to the connecting leads 4a 4b and 4c and to the associated terminals of socket 12 The conductive tips 6a 6b and 6c associated with the leads 4a 4b and 4c are respectively connected to any of the exposed terminals of the transistor or FET device under test without the operator knowing before hand which particular terminals are the load or control terminals of the device under test The waveforms W7 and WS are such that a transistor or FET device will not test good unless the input terminal 185 of the test switch 18 which input terminal is connected as previ ously described to the output of the base drive circuit 38 is connected to the base or gate control terminal of the transistor or FET device under test Also in case of an unsymmetrical bipolar transistor the input
5. claim 6 wherein said mini mum gain value of said non bipolar transistors is in the range of from about 20 to 30 8 The testing apparatus of claim 6 wherein said shunting impedance of said modestly low value is in the range of from about 1 000 to 2 000 ohms 9 The testing apparatus of claim 6 wherein said mini mum gain value is in the range of about 20 to 30 said shunting impedance of said modestly low value is in the range of about 1 000 to 2 000 ohms and said very low shunting impedance is in the range of from about 10 to 200 ohms 10 A circuit for testing transistor devices or the like said circuit comprising test device connection terminals to be connected at random if desired to the respective terminals of a transistor device or the like to be tested in circuit or out of circuit a periodic intermittently occurring control terminal driving constant current voltage source which voltage during first and second test intervals has an initial portion which renders non conductive a transistor device having a different con ductivity type assigned to the test interval involved and which then switches to a polarity and a value which render this transistor device substantially conductive when said load terminal energizing voltage source and said control terminal driving voltage source are con nected respectively to the proper load and control ter minals of the transistor device or the like being tested means for switching said vol
6. condition ef fects connection of the terminals of the transistor device or the like under test and the output of said test voltage supply means to said leakage testing circuit said func tion control switching means having a second condition which connects said voltage sources to the terminals of the transistor device under test to perform said gain test and manually operable means for operating said func tion control switch means between said first and second conditions 13 A circuit for testing transistor or FET devices said circuit comprising test device connection terminals to be connected at random if desired to the respective terminals of a transistor device or the like to be tested in circuit or out of circuit a periodic intermittently occurring control terminal driving constant current voltage source which voltage during first and second test intervals for testing transistor or FET devices of opposite conductivity type has during each interval an initial portion of a polarity which renders non conduc tive a transistor or FET device having the conductivity type assigned to the test interval involved and which voltage during each such interval switches to the oppo site polarity and a value which render this device sub stantially conductive when said load terminal energiz ing voltage source and said control terminal driving voltage source are connected respectively to the proper load and control terminals of the transistor o
7. drive voltage applied between the base and emitter terminal is zero of of a current flow opposing polarity whereas a FET device is rendered non conductive by 8 drive voltage substantially different from zero and of a current opposing polarity The testing apparatus of the invention now being described is preferably one where the operator does not have to know beforehand the identity of the various terminals of the transistor or FET device involved All that is necessary for the operator to perform a conduc tion test under low drive or high drive conditions is that after connection of the leads 4a 4b and 4c respec tively to different terminals of the transistor or FET device involved the operating arm 18 of a six position test switch 18 is moved successively to the different possible positions thereof until he hears a tone signal 10 30 35 40 45 50 55 65 3 or transistor devices which can be reliably detected These waveforms while initiating and terminating from and to zero volts vary between negative and positive polarities during the application of the positive and negative load terminal drive pulses Such a drive signal waveform is also operable with transistor devices which are rendered non conductive when only a zero voltage is applied to the base terminal thereof Thus the same drive signal waveform is operable with both FET and transistor devices When a transistor does not show satisfactory conduc tion
8. namely that shown by the waveform W10 in FIG 7 The waveform appearing at the output of the collector drive circuit 36 when a properly operating PNP transistor or P channel FET device is being tested is shown by the waveform W16 in FIG 7 The voltage changes shown by these waveforms W10 and W16 will not occur when an improperly operating transistor or FET device is being tested and any pulses generated by the differentiation of such voltages will not be of suffi cient amplitude to operate the detecting circuits in the manner now to be described when a properly operating transistor or FET device is being tested A conductor 52 extends from the collector drive output conductor 41 to the inp t portion of a detecting circuit which as illustrated includes a resistor 53 shunted by the section 155 of the drive control switch when this switch is in its HI position so that the detector circuit then operates with maximum sensitivity under these conditions to increase the signal to noise ratio therein Resistor 53 is connected to a differentiat ing network 54 which differentiates the waveform ap pearing on the collector drive output conductor 41 When the waveforms W10 and W16 are differentiated by the network 54 comprising a capacitor 54 in series with a grounded resistor 56a the voltage appearing across resistor 56a will be that shown respectively by the W11 and W17 waveforms shown only in FIG 2 It should be noted that the pulses P1
9. normal leakage currents and or silicon and germanium devices which for a low signal or power device have different normal leakage cur rents Indicia opposite the scale 26a indicates the actual leakage current flow If a transistor unlike a FET device does not test good under low drive conditions this may be due to a defective transistor or because the transistor is so highly shunted that the transistor cannot be tested under such drive conditions If the transistor tests good under such low drive conditions then the transistor is unquestion ably a good transistor A transistor testing bad under the low drive conditions may test good under high drive conditions but to be sure that the transistor is a satisfac tory transistor for ideal circuit operating conditions the operator may wish to determine whether the transistor failed a low drive condition test because of excessive leakage or because merely that it was in a circuit having very low shunting impedances If the transistor under test failed both the low and the high drive test or if the transistor failed the low drive test and passed the high drive test the transistor should generally be further tested out of circuit This applies also to FET devices which do not test good under the high drive condi tions The transistor or FET device to be further tested is then removed from the circuit involved and its termi 4 117 400 8 a waveform W8 appears which is positive only du
10. normally has a 4 5 volt input which momentarily drops to zero at the 10 Hertz rate These pulses are fed by a conductor 104 to the set input terminal S of the flip flop circuit F5 which causes the voltage on the Q output terminal thereof see waveform W3 in FIG 6 to drop from a positive to a zero voltage level which remains for the duration of the NPN and the PNP test intervals previously described The voltage on the Q output ter minal thereof see waveform W3 in FIGS 4 and 5 which is positive during the NPN and PNP test inter vals is fed by conductors 113 115 118 120 and 119 to the reset and enable terminals of toggle flip flop in cludes F1 F2 and F3 to prepare them for operation A conductor 105 extending from the Q output terminal of flip flop circuit F5 extends to the previously mentioned NOR gate 72 controlling the tone generator circuit 74 The negative or zero going pulse output from the slow clock pulse generator 43 is fed by conductors 106 and 108 to the reset input terminal R of the toggle flip flop circuit F1 to prevent this circuit from being set at that instant The same pulse is fed through a rectifier 110 to a terminal 42b of the fast clock pulse generator to synchronize the same In the particular circuit illus trated the terminal 426 is also the output terminal for the pulses generated by the pulse generator 42 These pulses are fed to toggle input terminal T of the toggle flip flop circuit F1 Accordingly a c
11. shunt resistance and capacitance referred to are the net resistance or capacitance measured between the control and reference load terminal of the test device in the circuit in which the device is located Since the test 65 circuit of the invention is utilized to test transistor de vices or the like of various power handling capabilities a given applied collector or base drive voltage could 4 117 400 22 gain only above a given acceptable value when the device is in a circuit having a shunting impedance of not much less than a given modestly low value but provid ing a load current transition below said given level when load current flow is in a reverse direction for most unsymmetrical bipolar transistors said high drive level providing a load current transition of at least said given level for most unsymmetrical bipolar transistor devices having a forward current gain of at least said given value when the transistor devices or the like are in a circuit providing a very low shunting impedance of only small fraction of said modestly low value and providing said load current transition of at least said given level in both directions of current flow when said unsymmetrical bipolar transistor devices are in a circuit providing a shunting impedance of said modestly low value and current gain detecting means for detecting and indicating the occurrence of a load current transi tion of at least said given level 7 The testing apparatus of
12. signals prepare the gate 62 for opening by a 4 117 400 12 leakage test one load terminal and the control terminal of the device under test are connected together and the leakage is measured between these terminals and the other load terminal thereof To this end the L contact of the function control switch sections 32a and 32b are respectively connected together by a conductor 91 and the conductor 91 is connected by conductor 93 to an input 87a of the leakage testing circuit 87 Thus when the function control switch is moved to the L position thereof the wipers 32a and 32 of the function control switch sections 32a and 326 will connect the conductor 93 to the control and one of the load termi nals of the device under test The other load terminal of the device under test is coupled by the test switch 18 to the wiper 32c of the function control switch section 32c in turn coupled through the L contact of the switch section a conductor 92 and resistor 98 of a voltage divider network including a grounded resistor 99 to the aforementioned conductor 78 extending to the output terminal 776 of the test voltage supply circuit 77 It is thus apparent that the output voltage of the test voltage supply circuit 77 is coupled in series with the two unconnected terminals of the device under test to the input of a leakage testing circuit 87 of conventional design which feeds a current through the meter move ment 89 in propo
13. terminal 18c associated with the collector drive circuit 36 must be connected by the test switch to the collector terminal of the transistor under test for the transistor to test satisfactory under low drive conditions except in the case of special transistors which have sufficient reverse gain to test satisfactory under such low drive condi tions The point in the circuit just described at which the voltage conditions are sensed to determine whether or not the device being tested has a satisfactory gain is the output of the collector drive circuit 36 which should be 20 25 30 35 40 45 50 55 60 65 7 of leakage tests with the conductivity type of the device involved since the selection of a proper polarity test voltage is done automatically by the test circuit de scribed Reference should now be to FIG 2 which shows a detailed block and partial circuit diagram of the most preferred form of the present invention FIG 2 shows a transistor 33 connected in circuit with a circuit impe dance 35 between the base terminal 335 of the transistor and one of the load terminals 33a which will be as sumed to be the emitter terminal of the transistor However it is assumed that the operator of the testing apparatus of the invention does not know what particu lar terminals of the transistor are the emitter base or collector terminals The test switch 18 which is shown in block form in FIG 2 has three switch secti
14. the collector circuit of this transistor has con tinuity Accordingly the collector 178c is coupled through the light emitting diode or lamp 28 to the conductor 180 extending to the resistor 182 in series with the collector of transistor 184 It can thus be seen that when the wiper 32e is advanced to the I or the L contact and an apparently satisfactorily operating transistor is being tested so that the base 1845 of transis tor 184 has a positive voltage applied thereto current flows through the lamp 28 through a circuit including the load terminals of the transistors 184 and 178 Since the voltage on conductor 180 is then near ground poten tial the lamp 28 to which the conductor 180 extends will have substantially no voltage applied to the oppo site terminals thereof and so it is in a de energized state While the specifications for the testing circuit just described may vary widely in its commercial form it has the following specifications 20 25 30 35 45 50 Applied test current base drive 250 mA high drive or 1 mA low drive at 4 duty cycle 125 mA at 4 duty cycle 10 per second collector drive test repitition rate reverse voltage for leakage test 2 0V Limiting in circuit shunt values for valid good bad test shunt resistance down to 10 ohms with high drive down to 1 5K ohms with low drive up to 15 mfd with high drive up to 3 mfd with low drive 55 capacitance 60 The
15. 144a When the waveforms W4 and W3 are applied to the inputs 102a and 102 of the gate 102 prior to the begin ning of the NPN test interval the voltage at the input 102a will be 5 volts and the voltage at the input termi nal 1025 will be zero volts so that its output terminal 102c will be at 4 5 volts and the adjacent transistor 135 will be non conductive However at the start of the NPN test interval and until the point where the wave form W4 reduces to zero both inputs to the gate 102 will be positive so that the gate output terminal 102c will drop to zero thereby causing the transistor 135 to become conductive This in turn drives the transistor 139 conductive to couple the 5 volt bus 142 to the collector circuit point 153 coupled by the resistor 155 and the previously mentioned resistor 39 to a base drive terminal 157 connected to the T contact of the func tion control switch section 32b As previously indicated when the waveform W4 drops to zero the NAND gate 102 will close and this portion of the waveform W4 coupled through the resis tor 147 to the base of transistor 144 will render this transistor conductive thereby coupling the 5 volt bus 140 to the point 153 coupled to the base drive terminal 157 The transistor 144 remains conductive until the waveform W4 once again rises to a 4 5 volt level when the aforementioned transistors 135 and 139 will become conductive for the second half of the PNP test inte
16. 4 117 400 Sep 26 1978 11 45 pying only a small portion of each cycle During each test interval a load terminal energizing pulse is gener ated to energize a transistor or FET device of a differ ent conductivity type and a control terminal drive volt age is penetrated which initially is of a polarity which would render a transistor or FET device of the associ ated conductivity type non conductive and then switches to a voltage of opposite polarity to render such device fully conductive There is provided means for selectively varying the control terminal driving current which flows in an operating device from a relatively high to a relatively low level Signals are derived show ing the transition in the conductive states of the devices under test during the polarity transition of the control terminal drive voltage waveform A first detecting and storage circuit is provided which detects and stores the occurrence of a current transition during the first test interval showing a possibly properly operating device of one conductivity type and a second detecting and storage circuit is provided which detects and stores the occurrences of a current transition during the second test interval showing a possibly properly operating device of the opposite conductivity type The storage circuit sets a leakage and material type test voltage producing circuit to produce a test voltage of proper polarity depending upon whether the possibly proper
17. 5 239 3 58a 54 15b Lo N 54g DET Us 2 wir AR 36 coLLECT DRIVE th TRANSISTOR TEST TERM U S Patent Sept 26 8 Sheet 1 of 6 4 117 400 FIG 2la BASE QUT OF CIRCUIT GOOD 2ib EI JO 4P LEAKAGE 2 6 POWER 14 Que GEN e foie TO LEAKAGE 2 ZS 0 gt CIR INPUT e TO LAMPS TO 1D CIR TO LOUDSPEAKER OBS 26 6 28 LIAINNOD 1 077 481 pM 22 8 4 ze ei ZIM ogg ogg Nge tie 4 eee Lio eee Hs _ T D 55 Lingala J 2 S9NIAS3 1 26 7 3 2 i Deg 4 02 M 9NI1S31 J39VXV31 68 82 4 924 HOLIMS Wil 1S31 YOLSISNV aL It Id Ob TT Pag 1M 1531 00 HOLSISNVYL Sheet 2 of 6 4 1 17 400 Sept 26 1978 U S Patent 29 8 29 9 229 80133130 OL pze YON OL 353500 OL 25 d 2 25 0011 Ibl suf ERR N39 ISTINA 432012 MOIS sol jn bl t 46 6 Oe 628 U 9 6 I acer eau id 25 1 MSENWHI34 3AIMG 4012371702 tbl Sp bbl T 0 opd PPI N eb qet N39 ISTMNd 2 3072 15 SE eb SI WHIL ES Reie N 32 110 35 P pp bb 9 V Ot ish 2 Ob ge Sheet 3 of 6 4 117 400 Sept 26 1978 U S Patent Sheet 4 of 6 4 1 17 400 RESCAN PE
18. 8 whose emitter 135a is connected to a 5 volt bus 140 The collector 135c of the transistor 135 is coupled through a resistor 137 to the base 139b of PNP transistor 139 The emitter 139a of the transistor 139 is connected to 5 volt bus 142 The collector 139c of the transistor 139 is coupled to the collector 144c of a PNP transistor 144 whose emitter 144a is connected to the 5 volt bus 140 and whose base 144b is connected by a conductor 145 and resistor 151 to the emitter 144a A conductor 145 and a resistor 147 connects the base 144b to the conductor 130 upon which the waveform W4 appears It should be apparent that when the waveform W4 which varies between 5 volts and zero is at 5 volts the voltage difference between the emitter and the base of the transistor 144 is zero since the emitter is con nected to the 5 volt bus 140 Zero volts applied to the 10 25 35 40 45 50 55 60 65 13 terminals R to which positive voltage must be fed to enable the flip flop circuit to be set and reset i e tog gled by successive pulses fed to toggle input terminals T thereof from the input of the fast clock pulse genera tor 42 The output thereof shown by waveform W9 in FIG 5 is a normally 5 volt output which drops mo mentarily to zero volts at a 1000 Hertz rate The reset input terminal R can also be used to reset the flip flop circuits to a reference reset condition when a zero or negative going voltage is appli
19. RIOD INTERVALS eer NPN 765 TEST Sept 26 1978 U S Patent FIG 5 5 HIGH FREQ CLOCK PLUSES y rw NE mm BN NE Lp SE EES wl 1 epes DEn 1 9 o TEST a did NPN fence Er TEST E 1 wia i o Il E Lus BINE NI CS S BN DN NI M NT Fw iT 9 66 FLIP FLOP Fi Q OUTPUT FLIP FLOP F5 Q OUTPUT FLIP FLOP F2 Q OUTPUT FLIP FLOP F3 Q OUTPUT FLIP FLOP F3 Q OUTPUT BASE DRIVE VOLTAGE COLLECTOR DRIVE VOLTAGE LOW FREQ CLOCK PULSES FIG 7 LATCH RESET PULSES Q V COLL E C TOR VOLTA GE F OR NPN DEVICE DIFF amp INVERTED WAVE FORM FOR NPN DEVICE AT OUTPUT OF OPER AMPL MAIN GATE SIGNAL FOR GATE MAIN GATE SIGNAL FOR GATE OUTPUT OF GATE 62 OUTPUT OF FLIP FLOP OF GOOD NPN TRANS COLLECTOR p GE F Of PNP DEV DIFF COLLECTOR WAVEFORM FOR PNP DEVICE AT OUTPUT OF OPER AMP 58 66 OUTPUT OF GATE 62 OUTPUT OF FLIP FLOP es IF GOOD PNP TRANS 99 DG EG IH 07 JAYA Ke D 62 Z l Zbl 69 SEI EZI 28702 35104 2 JO 42012 M2012 1NdiNO O WOH 1SVJ OI MOTS O4 Ov LINDY YIWIL WOHJ ITE 94 SIS Osp ga eg Re 24 GN 0 ZSI OL YON D qz pac S IVN9IS INILVO
20. age sources when applied to the proper load and control terminals of transistor devices or the like producing load current transistions indicative of the current gain thereof manually operable switching means for switching said voltage sources to said test device connecting terminals in the various different possible connecting combinations thereof current gain detecting means for detecting and indicating the occur rence of a load current transition of at least a given level indicating that the device has a satisfactory gain said detecting means including means for selectively deter mining whether the device being tested is of one or opposite conductivity type function control switching means having a gain test effecting condition for inter connecting said voltage sources device connecting terminals and detecting means for performing a current gain test a leakage test circuit a leakage test circuit voltage source supplying a DC voltage of a fixed value but a selectable polarity said function control switching means having a device leakage test effecting condition for connecting said leakage test circuit and test circuit voltage source to said device connecting terminals ex tending to the control and load terminals of the device being tested through which a leakage current is to be measured and said current gain detecting means includ ing means for determining the conductivity type of the transistor device or the like under test and for
21. al testing circuit 82 includes reverse con nected rectifiers 160 and 162 respectively connected between the input terminal 82a and the respective in verting and non inverting input terminals 164a and 164a of an operational amplifier 164 A feedback resis tor 170 is connected between the output terminal 164b and the inverting input terminal 164a For an NPN or N channel device the voltage drop between the control and load terminal is positive and for a PNP or P channel device this voltage drop is negative If the negative voltage drop is greater than 0 4 volts which is pres ent for a silicon device this voltage exceeds the thresh old of the rectifier 160 which is a silicon recitifier with a reverse threshold of 0 4 volts This negative voltage is applied to the input terminal 164a of the operational amplifier 164 to produce a 5 voltage at the output terminal 1645 thereof If the base to emitter voltage involved exceeds 0 4 volts which is indicative of a silicon device of opposite conductivity type to the de vice which produced a voltage in excess of 0 4 volts this voltage is coupled through the rectifier 162 which is also a silicon rectifier to the input terminal 164a of 17 72a and 72a of the NOR gate 72 NOR gate 72 as 20 illustrated is a circuit wherein the voltage at the output terminal 72b thereof is normally zero and will be posi tive if any one or more inputs thereof are at zero volts If no tran
22. and material identification test for such a transistor after the transistor device is removed from the circuit The above described and other features of the inven tion and the advantages thereof will become apparent upon making reference to the specification to follow and the claims DESCRIPTION OF DRAWINGS FIG 1 is a perspective view of the control panel side of the housing of the testing apparatus of the most pre ferred form of the invention FIG 2 is a basic block diagram of the basic compo nents of the testing apparatus of FIG 1 FIG 3 is a circuit diagram of that part of the test circuit including the transistor terminal switch means and the associated function switch associated therewith FIG 4 is a detailed block and partial circuit diagram of the collector and base drive circuits and the timing circuits shown in block form in FIG 2 FIG 5 shows various signal waveforms present in the circuit of FIG 4 FIG 6 is a detailed block diagram and partial circuit diagram of the detector amplifier gate flip flop and tone control and generating circuits shown in block form in FIG 2 FIG 7 shows various waveforms of signals present in the circuit of FIG 6 and FIG 8 is a circuit diagram of the material identifica tion circuit shown in block form in FIG 2 4 117 400 6 nals inserted within the sockets of the connector 12 at the bottom of the control panel 2a If the transistor or FET device involved did not
23. base grounded transistor 156 which in turn renders the transistor 158 conductive to couple the 5 volt bus 142 to the collector side of the transistor 158 and through the resistor 80 and 98 to the circuits which perform the material and leakage tests As previ ously indicated the state of flip flop circuit 65 is locked in when the function control switch 32 is moved from its center position to either the I or L positions thereof Reference should now be made to FIG 8 which shows a preferred but exemplary circuit for the material testing circuit 82 It will be recalled that the input termi nal 82a of this circuit is coupled through conductors 8 and 85 and resistor 80 to conductor 78 leading to the output terminal 77b of this test voltage supply 77 Also the function control switch section 32b when its wiper 32 engages the I contact connects one of the load terminals and the control terminal of the device under test between the input terminal 82a of the material testing circuit 82 and ground Moreover the polarity of the DC voltage fed to the input terminal 82a depends upon whether the device under test is of one conductiv ity type or another since the voltage drop which is measured in ge materials test to determine whether the material is a silicon or germanium material must be that produced by current flow in the low impedance direc tion of the control terminal to load terminal junction The materi
24. d control terminal driving voltage source means generate cyclically repeating pulsed waveforms said current gain detecting means is opera ble each cycle of said periodic waveforms and includes resettable memory means settable to a condition indicat ing a satisfactory gain of the transistor device or the like 40 45 50 55 60 65 under test and means for resetting said memory means each cycle of said periodic waveforms 4 The testing apparatus of claim 3 wherein the opera tion of said function control switching means to said leakage test effecting condition disables the operation of said resetting means 5 The testing apparatus of claim 1 wherein said inter mittently occurring voltages generated by said voltage sources have cyclically repeating waveforms compris ing current generating pulses which occur only a very minor portion of each test cycle 6 Apparatus for testing the current gain of transistors or the like said apparatus comprising test device con necting terminals to be connected to the respective terminals of a transistor device or the like to be tested in circuit or out of circuit an intermittently occurring load terminal energizing constant current voltage source and intermittently occurring control terminal driving constant current voltage source said voltage sources when applied to the proper load and control terminals of transistor devices or the like producing load current transitions ind
25. eans for detecting storing and indicating the occurrence of a load current transition in the transistor device being tested of the opposite conductivity type and properly connected to said load terminal energizing and control terminal driving voltage sources of at least said given level only during each second test interval 11 The testing circuit of claim 10 wherein there is provided connecting leads having distinguishing indicia thereon extending from said device connecting termi nals lead connection indicating means including means responsive to said switching means for identifying the terminals of the transistor device or the like to which said connecting leads extend when said switching means connect said sources of voltage to the proper load and control terminals which result in said detecting means detecting a transistor device or the like with a load current transition of at least said given level 12 The testing circuit of claim 10 wherein there is provided a leakage testing circuit test voltage supply means for said leakage testing circuit and which is oper able to produce an output DC voltage of a given refer ence value but of selectable opposite polarities polarity control means responsive to said circuit means for oper ating said test supply voltage means to produce a test voltage of a polarity corresponding to the conductivity type of the device passing the gain test function control switch switching means in which a first
26. ed thereto Each of these toggle flip flop circuits have Q and Q output terminals The voltage at each Q output terminal will be positive when the flip flop circuit involved is in a set condition and will be at zero voltage when the circuit is in a reset condition The voltage at each Q output terminal is opposite to that of the L output terminal i e it is zero when the other is positive and vice versa The timing circuit further has a flip flop circuit F5 having set and reset input terminals S and R respec tively and output terminals Q and Q and which will have the same voltages as the Q and Q terminals of the toggle flip flop circuits F1 F2 and F3 just described in the set and reset conditions states thereof The feeding of a zero or negative going pulse to the set input termi nal S will result in the setting of the flip flop circuit F5 and the feeding of a similar voltage to the reset terminal R of the flip flop circuit F5 will result in the resetting of the flip flop circuit F5 The timing circuit further in cludes inverting NAND gates 102 and 102 having pairs of input terminals 1020 1026 and 102a 102b The output voltage of each gate 102 or 102 will be normally 5 volts and will drop to zero volts when both input terminals thereof have 4 5 volts voltage fed thereto The slow clock pulse generator 43 generates negative going pulses at an exemplary rate of 10 per second As shown by waveform W1 in FIG 5 the generator 43
27. effecting a DC output of said test current voltage source of a polarity corresponding to the conductivity type of the transistor device or the like under test 16 The testing apparatus of claim 15 where said load terminal energizing and control terminal driving volt age sources generate cyclically repeating pulsed wave forms said current gain detecting means is operable each cycle of said periodic waveforms and includes resettable memory means settable to a condition indicat ing a satisfactory gain of the transistor device or the like under test and means for resetting said memory means each cycle of said periodic waveforms 17 The testing apparatus of claim 16 wherein the operation of said function control switching means to said leakage test effecting condition disables the opera tion of said resetting means 18 The testing apparatus of claim 15 wherein said intermittently occurring voltages generated by said voltage sources have cyclically repeating waveforms comprising current generating pulses which occur only 8 very minor portion of each test cycle 5 45 50 60 65 23 circuit means for detecting storing and indicating the occurrence of a load current transition in the transistor device or the like being tested of one conductivity type and properly connected to said load and control termi nal voltage sources of at least said given level only during said first test interval and second circuit m
28. ega tive to its positive polarity during the NPN test interval and a properly operating PNP transistor results in a positive pulse at the output of gate 62 during the polar ity transition of the base drive waveform W7 from its positive to its negative polarity during PNP test inter 5 10 15 20 25 35 40 45 50 val The pulse at the output of gates 62 and 62 are fed to the set input terminals 65c and 65c respectively of the flip flop circuits 65 and 65 The output terminals 655 and 65 of the flip flop circuits 65 and 65 are Q output terminals which have a 5 volt output when the flip flop circuit involved are reset and a zero voltage when the flip flop circuits are set At the beginning of each NPN test interval the reset input terminals 65a and 65a of these gates are respectively fed with a zero going pulse from the slow clock pulse generator 43 to minimize any continued false operation due to occasional transients The clock pulses are fed on conductor 69 The Q output terminals 65b and 65b of the flip flop circuits 65 and 65 are respectively coupled to the inputs 55 60 65 15 base of a PNP transistor results in termination of collec tor current Transistor 144 becomes conductive when the waveform W4 drops to zero which occurs during the second half of the NPN testing interval and the first half of PNP testing interval since then the base 1445 is negative with respect to the emitter
29. es switching means for switching said voltage source means to said test device connecting terminals in the various different possible connecting combinations thereof said means for detecting said current transitions including means for selectively determining whether the device being tested is of one or opposite conductiv ity type function control switching means having a gain test effecting condition for connecting said voltage source means to said device connecting terminals for performing said gain test a leakage test circuit a meter movement for said leakage test circuit leakage test circuit voltage source means for supplying a DC volt age of a fixed value but of selectable polarity said func tion control switch having a device leakage test effect ing condition for connecting said leakage test circuit and test circuit yoltage source to said device connecting terminals extending to the control and load terminals of the device being tested through which a leakage current is to be measured said current gain detecting means including means for determining the conductivity type of the transistor device or the like under test which shows a satisfactory gain and for effecting a DC output of said test current voltage source means of a polarity corresponding to the conductivity type of the transistor device or the like under test showing such a satisfactory gain 3 The testing apparatus of claim 2 wherein load ter mitial energizing an
30. flop circuit 65 is zero During the performance of a materials or leakage test it is imperative that the normal transistor test cycle be terminated and the set or reset condition of the flip flop circuit 65 or 65 be maintained so that the test voltage supply circuit 77 will have a steady output of proper polarity to carry out the materials and leakage tests Accordingly the slow clock pulse generator 43 which normally applically resets the flip flop circuits 65 and 65 is de energized during these materials and leakage tests To this end FIG 2 shows a function control switch section 32d having a grounded wiper 322 and a connection extending only from the T contact to the slow clock pulse generator 43 Accordingly the slow clock pulse generator 43 has no continuity to ground and therefore is decoupled from its supply source when the wiper 325 is connected to the L and I contacts The materials testing circuit identified by reference number 82 in FIG 2 has an enabling input terminal 82a connected by a conductor 83 to the output of NOR gate 72 so that the material testing circuit is prepared for operation only when either the flip flop circuits 65 or 65 is set indicating an apparently properly operating transistor or FET device A conductor 78 extending from the output 77b of the test voltage supply circuit 77 is shown coupled through a resistor 80 and a conductor 85 to the input terminal 82a of the material testing ci
31. he conduction of transistor 144 will thus cause 5 volts to appear at the collector drive terminal 157 adjacent to resistor 39 At the initiation of the PNP test interval when the waveform WS drops to zero the gate 102 will re close 10 render the transistor 144 non conductive and the waveform WS then dropping to zero is effective to render the transistor 135 conductive as this voltage is 4 117 400 18 resistor 164 connected to the emitter 162a of the transis tor 162 in turn connected to the 5 volt bus 140 Accordingly when the Q output of the flip flop circuit 65 is at zero volts indicating a satisfactorily operating NPN transistor under test this zero voltage coupled through resistor 160 to the NPN transistor 162 will render the transistor 162 conductive to couple the voltage of the 5 volt bus 140 to the collector side of the transistor 162 in turn connected through the resis tor 80 to the conductor 88 FIG 2 leading to the I contact of the sections 32b of the function control switch 32 The collector side of the transistor 162 is also connected through the resistor 98 to the L contact of 6 section 325 of the function control switch which forms part of the leakage test circuit as previously ex plained When the Q output terminal of the flip flop circuit 65 is positive indicating an apparently satisfactorily oper ating PNP transistor this positive voltage effects con duction of the
32. icative of the current gain thereof means for selectively providing relatively high and low constant current drive levels from the proper connection of said voltage sources to the load and con trol terminals of the transistor device or the like being tested said low drive level providing a load current transition of at least a given level for most unsymmetri cal bipolar transistor devices having a forward current 4 117 400 24 means for detecting storing and indicating the occur rence of a load current transition in the transistor of FET device being tested of opposite conductivity type and properly connected to said load terminal energizing and control terminal driving voltage sources of at least said given level only during each second test interval 14 The testing circuit of claim 13 wherein said first and second test intervals are contiguous and the wave form of the voltage generated by said control terminal driving voltage source is of a constant polarity and value after the initial portion of said first test interval and during said initial portion of said second test inter val 15 Apparatus for testing the current gain of transis tors or the like said apparatus comprising test device connecting terminals to be connected to the respective terminals of a transistor device or the like to be tested in circuit or out of circuit a load terminal energizing voltage source a control terminal driving voltage source said volt
33. ice being tested will be identified by a color coded chart which appears in a window 22 The chart has three different sections 20a 20b and 20c which indicate the color of the leads 4a 4b and 4c which extend to the indicated terminals of the device involved Visible through a window 24 on the front panel 2a of the housing 2 are the various scales 26a 26b 26c 26d and 26e over which a pointer 28 of a meter movement not shown is moved If a transistor does not test good under low drive conditions the control arm of the drive switch 15 is moved to the HI position where the amplitude of the control terminal drive signal is increased to make the test circuit more sensitive If the test of the transistor or the FET device under high drive conditions indicates that a further test of the device is desirable namely a leakage test then the transistor or FET device involved is removed from the circuit and connected into the test apparatus through the socket terminals 12 as previously explained If the operator does not know whether the device is a germanium or a silicon device he must de termine this before carrying out the leakage test Thus it will be noted that the leakage indicating scales 266 26c 26d and 26e have segments marked thereon of dif ferent lengths indicating the areas of the scales over which there is a satisfactorily low leakage condition for low signal and power transistors or FET devices which have different
34. itching the tog gle flip flop circuit F4 between its set and reset states while the enabling and reset terminals E and R thereof receive a positive voltage in the periods between the NPN and PNP test intervals The flip flop circuit F4 has a Q output which during the toggling of the circuit comprises positive pulses fed to the base 43b of a NPN transistor 143 by a conductor 142 The collector 143c of the transistor 143 is connected to the 5 volt bus 140 and the emitter 143a of the transistor 143 is connected through resistor 145 to the terminals of loudspeakers 76 in turn connected to ground The lamps 20 and 20 which are shown as light emit ting diodes are respectively connected between the Q output terminals of the gates 65 and 65 and a common terminal 150 connected through a resistor 152 to the 5 volt bus 140 It is apparent therefore that when either of the Q outputs of the flip flop circuit 65 or 65 is zero because of the set condition thereof the associated lamp 20 or 20 will become energized As previously indicated when either the lamp 20 or 20 is energized indicating to the operator that there is a properly operating transistor or FET device and the operator desires to carry out a leakage test the condi tion of the flip flop circuit 65 will indicate whether the transistor or FET device under test is a NPN or N channel or a PNP or P channel device Accordingly a conductor 153 extends between the Q output 65b of
35. ition where the nose portion 30 thereof is opposite a reference line 315 leading to the word LEAKAGE If the device is a power device the operator then examines a scale 26d or 26e associated with the particular type of semi conductor material out of which the device being tested is made namely a silicon or germanium semi conductor material Indicia not shown positioned on or opposite the scales in volved will identify the particular type of device in volved for which the scale is to give leakage informa tion If the device being tested is a low signal device then the scale 268 or 26c associated with the particular semi conductor material involved is examined to deter mine whether or not there is excessive leakage in the device under test If the pointer 28 moves beyond the usually dark colored segment of the scale involved indicating satisfactory leakage the operator knows that the transistor or FET device has excessive leakage The actual amount of leakage current flowing therein can be seen by noting the indicia not shown opposite the first scale 26a A transistor testing device operating in the manner described is a unique test instrument since heretofore there has never been a single test instrument which can test transistors or FET devices in circuit as well as out of circuit and where there is a selection of drive levels which during an in circuit low drive test with common levels of shunting impedances indicates a prope
36. ly operating device is of one or the other conductivity type 18 Claims 8 Drawing Figures a 2 62b f 65 65b 2O NPN 05 S 1 o 7 20 a PNP 32 4 LEAKAGE M TESTING CIRCUIT 82a T 28 bes MATERIAL SE 2 62 KS L 82 1 329 8 62 8b AMP 8 1 58 bic 5 4 Sab United States Patent 9 Feldman 54 CIRCUIT FOR TESTING TRANSISTORS OR THE LIKE 75 Inventor Harold Feldman Skokie Ill 73 Assignee Dynascan Corporation Chicago Ill 41 Appl No 681 487 22 Filed Apr 29 1976 IUE Co ER GOIR 31 26 52 U S CI 324 158 T 324 73 R 58 Field of Search 324 158 T 158 D 3 R 56 References Cited U S PATENT DOCUMENTS 3 458 814 7 1969 Ryan cerent 324 158 D 3 636 450 1 1972 Griffin 324 158 T 3 870 953 3 1975 Boatman et al 324 73 R OTHER PUBLICATIONS TF30 Super Cricket Service Manual Sencore 3200 Sencore Drive Sioux Falls S D 57107 2 21 75 Primary Examiner Rudolph V Rolinec Assistant Examiner Ernest F Karlsen Attorney Agent or Firm Wallenstein Spangenberg Hattis amp Strampel 57 ABSTRACT The circuit includes sources of periodic low duty cy cle load terminal energizing and control terminal driv ing pulse waveforms During each cycle the wave forms occur only during successive test intervals occu TRANSISTOR 33 UNDER TEST 3
37. ly during the second half of the NPN test interval and prepare the gate 62 for opening by a posi tive pulse fed to the input 62a thereof only during the second half of the PNP test interval While the gate 62 is prepared to be opened during the NPN test interval the polarity of a pulse developed at the output of the detector amplifier and inverter 58 due to a properly operating PNP transistor or equivalent FET device will not open the gate 62 Similarly during the time that the gate 62 is prepared for opening during the PNP test interval the polarity of the pulse fed to the input 62a thereof will be of the incorrect polarity to open the gate 62 when a properly operating NPN transistor or equiv alent FET device is being tested The output terminals 62b and 62 of the gates 62 and 62 are respectively connected to the input terminals 65a and 65a of flip flop circuits 65 and 65 which re spectively are set by a positive pulse passing through the open gates 62 and 62 The setting of either flip flop 65 or 65 will energize the associated indicating lamps 20 or 20 which are shown connected to ground Also the setting of either flip flop 65 or 65 will operate a tone Benerator circuit 64 in any suitable way As illustrated the output terminals 65b and 65b of the flip flop circuits 65 and 65 are respectively shown connected to a NOR gate 72 which will pass the voltage at the terminal 65b or 65b of a set flip flop 65 or 65 to e
38. n nected to the input 62a of the gate 62 which is also a NAND gate While in FIG 2 the gates 62 and 62 are shown with only a single gating input since this is a generalized or simplified circuit the gate 62 of FIG 6 has two gate signal input terminals 62c 1 and 62c 2 and the gate 62 has two gate signal input terminals 62c 1 and 62 2 The gate signal input terminals 62 2 and 62c 2 of the gate 62 and 62 are connected to the con ductor 123 previously described in connection with FIG 4 on which conductor the waveform W2 appears which goes positive only during the second half of the NPN test interval and the second half of the PNP test interval so that the gates 62 and 62 are prepared for opening during these periods However the gate 62 is prepared for opening only during NPN test interval by the connection of its gating signal input terminal 62c 1 to a conductor 136 upon which appears the waveform WS which is always positive except during the PNP test interval when it is zero The gate 62 is prepared for opening only during the PNP test interval by the con nection of its gate signal input terminal 62c 1 to the conductor 129 upon which waveform W5 appears which is only positive during the PNP test interval As previously indicated only a properly operating NPN transistor results in the presence of a positive pulse at the output of the gate 62 during the polarity transition of the base drive waveform W7 from its n
39. nergize a tone generator circuit 74 to which a loudspeaker 76 is con verted In the most preferred form of the invention the tone generator circuit 74 is in condition for operation only during the intervals between the NPN and PNP test intervals Accordingly a control conductor 75 is shown extending between an output of the timing cir cuit 40 and the tone generator circuit 74 to couple a signal which prevents operation of the tone generator circuit 74 during the test intervals Also in the particu lar circuit shown in FIG 2 a section 32 of the function control switch 32 is provided which prevents operation of the loudspeaker 76 when the function control switch 32 is in its I or L positions during the materials identification and leakage test operation of the testing circuit described Accordingly only the I and L contacts of this switch section are shown grounded The flip flop circuits 65 and 65 are reset once during each cycle of operation of the described testing circuit except where the function control switch is held in the LEAKAGE or IDENTIFY positions To this end connections are shown from the slow clock gener ator 43 to the rest inputs 65c and 65c of the flip flop circuits 65 and 65 It will be recalled that a material identification or leakage test is not carried out except where a transistor or FET device in an out of circuit test tests satisfactory but failed either or both the low or high dri
40. ntil the recent development of improved testing apparatus transistor devices could not be tested reliably and safely without disconnecting them from the circuits in which they are used When testing transistors in cir cuit with most prior art testing apparatus there was a significant risk of damaging the circuits involved par ticularly where the transistors were shunted with low impedences Thus if DC voltages or continuous square wave voltages are applied to a heavily shunted transis tor the resulting energy supplied to those circuits could be excessive and destroy associated circuit components In recent years there was developed a transistor test ing circuit using pulsed test voltage waveforms with a low duty cycle which permits transistors to be tested safely in circuit Such a testing circuit is disclosed and claimed in U S Pat No 3 870 953 to Boatman et al In this circuit square topped pulse waveforms are pro vided for both the emitter collector load terminals and the base control terminals of the transistor devices to be tested which automatically periodically establish the voltage conditions during successive testing intervals which test respectively NPN and PNP type transistors These emitter collector and base drive voltages are intermittently applied so that insufficient energy is ap plied to the transistors tested in circuit to damage the transistors or the associated circuit components even when low sh
41. onductor 111 ex tends from the terminal 42b to toggle input terminal T of the flip flop circuit F1 Thus the second pulse gener ated by the fast clock pulse generator 42 will toggle the flip flop circuit F1 as does each succeeding pulse thereof so long as the flip flop circuit F1 receives a 4 117 400 16 coupled through resistor 163 to the base 135b of the transistor 135 driving transistor 139 The transistor 135 is therefore conductive during this test interval during which the waveform W5 remains zero Refer now to FIG 6 which shows among other things exemplary circuits for the detector amplifier and inverter circuit 58 inverter 66 gates 62 and 62 flip flop circuits 65 and 65 NOR circuit 72 and the tone genera tor circuit 74 shown in block form in FIG 2 FIG 6 shows the detector amplifier and inverter 58 circuit as an operational amplifier with the negative inverting input terminal 58a thereof connected to the output ter minal 586 of the amplifier through a resistor 545 which also forms a part of the differentiating network includ ing the capacitor 54a The positive input terminal 58c of the operational amplifier is shown grounded As previ ously described the output of the operational amplifier 58b is coupled to the input 62a of the gate 62 which is a NAND gate Similarly the output 665 of the in verter 66 whose input 66a is connected to the output terminal 58b of the operational amplifier 58 is co
42. ons 18 1 18 2 and 18 3 as shown in FIG 3 with input terminals 18a 185 and 18c respectively extending through con ductors 29a 29b and 29c to the wipers 32a 32b and 32c of the sections 32a 32b and 32c of the function control switch 32 The wipers of each of these function control switch sections can selectively engage I T or L terminals respectively suggesting the words Identify Test and Leakage The I and T terminals of the function control switch section 32a are shown grounded and the T terminal of the function control switch section 326 is shown coupled through a resistor 39 to a conductor 37 extending to the output 38b of a base drive circuit 38 The resistor 39 is shunted by the section 15a of the drive control switch 15 when the switch is in its HI position The base drive circuit 38 has an input 38a controlled by a timing circuit 40 so that there appears at the output 38b a base terminal drive voltage waveform W7 which is negative during the first half of an NPN or N chan nel device test interval and is positive during the sec ond half of this test interval and which is positive dur ing the first half of the immediately successive PNP or P channel device test interval and is negative during the second half of this test interval These two succes sive test intervals are repeated each cycle of operation of the circuit shown which cycle repeats itself at a Biven ra
43. ply circuit 77 is also connected to a leakage testing circuit 87 which may be of conventional design The leakage testing circuit 87 controls the operation of a meter movement 89 In a 4 117 400 14 positive enabling voltage on its enable input terminal which lasts for the duration of the NPN and PNP test intervals There is thus produced at the Q output of the toggle flip flop circuit F1 a voltage waveform W2 see FIG 4 or FIG 5 which is coupled by a conductor 121 to the toggle input terminal T of the toggle flip flop circuit F3 and by a conductor 123 to the detector gates 62 and 62 The positive going portions of the wave forms W2 occur during the second halves respectively of the NPN and PNP test intervals during which the pulses resulting from the differentiation of the collector terminal voltage waveforms like W10 and W16 are to be detected to identify whether or not there is a satis factory operating transistor or FET device It will be recalled that only a zero or negative going voltage will effect a setting operation in any of the flip flop circuits just described and therefore a connec tion of the Q output of the toggle flip flop circuit F1 to the toggle input terminal T of the toggle flip flop circuit F3 will not result in a toggling of flip flop circuit F3 except during the zero going portions of the waveform W32 Accordingly the waveform appearing at the Q output terminal of the flip flop circuit F3 will have the o
44. position involved Both the particular block diagram circuits shown in FIG 2 and the particular details of any of the circuits shown in block form therein to be described can vary widely without deviating from the broad aspects of the invention However FIG 2 shows the most preferred logic circuit of the invention and the circuits now to be described show the most preferred forms of the cir cuitry for some of the circuits shown in block form in FIG 2 Accordingly reference should now be made to FIG 4 which among other things shows the preferred circuit for the timing circuit 40 and the collector and base drive circuit 36 and 38 The timing circuit 40 com prises a series of toggle flip flop circuits F1 F2 and F3 which have enabled input terminals E and reset input 11 lamps 20 or 20 is energized showing a properly operat ing transistor or FET device the output of the flip flop circuit 65 which will then be either a positive or a zero voltage will identify whether the device involved is an NPN or N channel device namely when the output thereof is positive or whether it is a PNP or P channel device namely when the output thereof is zero The DC test voltage supply circuit 77 will provide a DC output 77b of one polarity when the output of the flip flop circuit is positive and it will provide an output of 10 5 20 25 30 40 45 50 55 60 65 the opposite polarity when the output of the flip
45. r FET device being tested means for switching said voltage sources to said test device connecting terminals in the various different possible connecting combinations thereof first circuit means for detecting storing and indicating the occurrence of a load current transition in the transistor or FET device being tested of one con ductivity type and properly connected to said load and control terminal voltage sources of at least a given level only during said first test interval and second circuit
46. rcuit 82 The input terminal 82a of the material testing circuit is also shown connected by a conductor 88 to the I contact of the function control switch section 32b which contact when a properly operating transistor has been detected is connected through the wiper 32b and the test switch 18 to the control terminal of the transis tor or FET device being tested The I contact of the function control switch section 32a is grounded so that the control terminal and one of the load terminals of the device under test during a materials test are connected between the input terminal 82a of the material testing circuit 82 and ground The testing circuit 82 to be de scribed is one wherein the circuit is responsive to the different voltage drops which occur between the termi nals of the device under test when the devices are re spectively silicon and germanium semiconductor de vices The circuit 82 energizes either the lamp 28 or 28 depending upon the value of this voltage drop The lamps 28 and 28 are rendered inoperable except during the materials and leakage test by the connections thereof shown in FIG 2 to the wiper 32c of switch section 32e of the function control switch 32 Thus the I and L contacts of this switch section have no connections thereto and the T contact thereof is grounded so that these lamps are rendered inoperable except during a materials and leakage tests The output of the test voltage sup
47. ring the NPN test interval and is negative only during the PNP test interval Because of the voltage dropping effect of associated impedances not shown current flow in the device under test will modify the voltage appearing at output terminal 365 The output 36b of the collector drive circuit 36 is coupled by a conductor 41 to the T contact of section 32c of the function control switch 32 where wiper 32c is connected to the input 18c of the transistor terminal test switch 18 The T contact of the function control switch section 32a is grounded It should be apparent to those knowledgeable about the operation of transistors and FET devices that in the first half of the NPN test interval the polarities and timing of the waveforms W8 and W7 respectively gen erated by the collector drive and base drive circuits 36 and 38 are such that during the NPN test interval if they were respectively coupled to the collector and base terminals of the NPN transistor or the source or drain and gate terminals of a N channel FET device during the first half of this interval the device would be non conductive and during the second half of this inter val the device would be switched to a highly conduc tive state Similarly the collector drive and base drive waveforms W8 and W7 during the PNP test interval are such that a PNP transistor or a P channel FET device connected as described would be non conductive dur ing the first half of this interval
48. rive level control switch 15 having a LO and a HI position is set to its LO position which establishes an amplitude level for load and con trol terminal drive current to flow in the load and con trol terminals of a transistor which will normally be adequate to produce a good transistor indication for only one conducting direction of most satisfactorily operating unsymmetrical bipolar transistors As is well known 2 NPN transistor is normally oper ated from a source of DC voltage where the positive terminal thereof is generally coupled through a load circuit impedence to the collector terminal and the negative terminal thereof is connected directly or indi rectly to the emitter terminal of the transistor In a N channel FET device 8 source of DC voltage is con nected similarly to the drain and source terminals which are respectively equivalent to the collector and emitter terminals of a transistor A NPN transistor or N channel FET device is normally operated in a conductive state by coupling a signal pulse or other current producing drive voltage source so that conventional current flows into the base or gate terminals requiring generally that the signal sources be connected so that the positive terminal thereof is coupled to the base or gate electrode and the negative terminal thereof is connected to the emitter or source terminal of the transistor or FET device A transistor is rendered non conductive when the
49. rly operating transistor in only one of the six dif ferent possible connections of the load and control volt age terminal sources to the unknown terminals of the transistor involved and during an in circuit high drive test generally indicates a properly operating transistor or FET device for unusually low shunting impedance without any danger of damaging the circuit Most tran sistors will test good in two of the six test switch posi tions in the high drive test Moreover the test apparatus just described is unique in that the operator does not have to concern himself in the materials determination 5 20 25 35 40 45 50 55 60 65 5 generated within the housing 2 which indicates that the transistor or FET device involved has appreciable am plification which at least under low drive conditions indicates a good transistor or FET device When the operator hears such a tone signal he looks upon the front panel 2a to see if a lamp 20 or 20 is lighted which identifies whether the apparently good transistor or FET device being tested is 2 NPN or N channel device or 8 PNP or P channel device As indicated in some tests the transistor or FET device will test good in two different positions of the test switch 18 and in other tests it will test good in only one position of the test switch 18 Where the device tests good in only one position the base collector and emitter or gate drain or source terminals of the dev
50. rtion to the degree of leakage current involved The test voltage supply output must have a definite polarity relationship with respect to the uncon nected load and the base terminals of the device under test if the device is a non bipolar transistor FIG 2 shows a block 100 representing a DC power supply having an output 100a at which a 5 volt with respect to ground voltage appears and an output 100b at which a 5 volt with respect to ground voltage ap pears Also shown is the aforementioned power on off switch 14 and the power indicating lamp 16 connected in a conventional way to A C input conductors of a plug connector 103 thereshown FIG 2 also shows in block form a lead connection indicator 101 which is mechanically coupled to the test switch 18 The lead connection indicator may comprise a movable member not shown which responds to the movement of the test switch 18 to its six different posi tions In each of these different positions of the test switch 18 a different color coded chart having a differ ent section 21a 21b and 21c becomes visible in the window 22 of the control panel 2a The color of these three different sections visible in the window 22 corre sponds to the colors of the leads 4a 4b and 4c which would be extending respectively to the base collector and emitter of a non bipolar transistor under test where the test circuit indicates that the transistor is a properly operating one for the particular test switch
51. rval after which the dropping of the waveform W3 to zero will result in both transistors 144 and 139 being non conductive so that the voltage at the base drive termi nal 157 will be zero The collector drive waveform W8 FIG 5 is gener ated by the feeding of the waveforms W3 and W5 of the Q and Q outputs of the flip flop circuits F5 and F3 to the inputs 1025 and 102a of the NAND gate 102 through conductors 113 115 118 128 and 133 and 136 The output terminal 102c of this gate is coupled through a resistor 134 to the base 1440 of a PNP tran sistor 144 forming part of the collector drive circuit 36 which is a circuit similar to the base drive circuit 38 just described The corresponding components of the cir cuits 36 and 38 will be similarly numbered except that a prime has been added to the elements of the circuit 36 However the connections of the gate 102 and other associated portions of the circuit to the collector drive circuit 36 are different from those connections made from the gate 102 and associated portions of the base drive circuit 38 to the transistors of the base drive cir cuit 38 Accordingly the output terminal 102c of the gate 102 which is normally at 5 volts will normally render the transistor 144 non conductive until the gate 102 has opened by the transition of the waveform W3 from zero to 4 5 volts at the beginning of an NPN test interval when the waveform W5 is still positive T
52. satisfacto rily in two of the six possible positions of the test switch 18 when the transistor is heavily shunted with resis tances of the order of magnitude of about 10 to 200 ohms a transistor having a gain of at least about from 20 to 30 will pass the high drive test in only one position of the test switch As previously indicated by having a test apparatus which provides for low and high drive tests as de Scribed not only does this aid the serviceman in identi fying all of the terminals of the transistor when carrying out the low drive test for most satisfactorily operating transistors but more importantly it enables the service man to detect marginally operating transistors which would pass a high drive test designed to test transistors in very low shunting impedance circuits but which would fail a low drive test because of excessive leakage or other reasons Moreover the present invention greatly simplifies the carrying out of materials and leak age tests to determine whether a transistor which passes a high drive test but fails a low drive test is defective or marginal rather than being satisfactory but operating in a very low shunting impedance circuit It should be understood that numerous modification may be made in the most preferred forms of the inven tion described without deviating from the broader as pects of the invention I claim 1 Apparatus for testing the current gain of transistors or the like said appara
53. sistor is being tested or the transistor being tested does not pass the gain test the Q outputs of the flip flop circuits 65 and 65 will be positive When the NOR gate output is positive the positive voltage is fed by a conductor 139 to the reset input terminal R of a toggle flip flop circuit F4 like the other toggle flip flop circuits F1 F2 and F3 previously de scribed To permit the flip flop circuit F4 to toggle both the enabling input terminal E and the reset termi nal R must have a positive voltage thereon To this end the waveform W3 at the output of the flip flop circuit 5 FIG 4 is coupled by a conductor 137 to the en abling terminal E of the flip flop circuit F4 The wave form W3 is normally positive and goes zero only dur ing the very short period occupied by the NPN and PNP test intervals 0 004 second during each rescan period 0 1 second The length of time that the enabling terminal of the flip flop circuit receives this zero volt age from the line 137 is of very short duration and re 35 40 45 50 55 60 65 peats at a low rate of 10 cycles per second but it modi fies the sound generated by the loudspeaker 76 so that it is a more easily noticeable raspy sound The toggling input terminal T of the flip flop circuit F4 receives its input from the output of the fast clock pulse generator 42 on conductor 141 The zero going fast clock genera tor pulses are effective in repeatedly sw
54. tage sources to said test device connecting terminals in the various different possible connecting combinations thereof means for selectively providing relatively high and low constant current drive levels from the proper connection of said voltage sources to the load and control terminals of the transistor device or the like being tested said low drive level providing a load current transition of at least a given level for most non bipolar transistor devices hav ing a forward current gain only above a given minimum low value when the device is in a circuit having a shunt ing impedance not much less than a given value but providing a load current transition below said given level when a load current flow is in a reverse direction for most unsymmetrical bipolar transistors said high drive level providing a load current transistion of at least said given level for most unsymmetrical bipolar transistor devices having a forward current gain of at least about said low value when the transistor devices or the like are in a circuit providing a very low shunting impedance of only a fraction of said given value first 0 20 25 21 about said value when the transistor devices or the like are in a circuit providing said very low shunting impe dance and current gain detecting means for detecting and indicating the occurrence of a load current transi tion of at least said given level 2 The testing apparatus of claim 1 which includ
55. te where the period occupied by the two test intervals described is a small fraction of the total period referred to as a rescan period in FIGS 5 and 7 between the successive generation of waveform W7 This pro vides a low duty cycle and relatively low energy ap plied to the transistor or FET device under test to avoid damage to the circuit in which the transistor or FET device is located It is apparent that when the drive control switch 15 is respectively in its LO and HI positions the current resulting from the waveform W7 will have relatively high and relatively low values The timing circuit is synchronized by a slow clock pulse generator 43 which generates pulses at a relatively slow frequency for example 10 hertz Accordingly the output 435 of the slow clock pulse generator 43 is shown connected by a conductor 45 to a synchronizing input 40 of the timing circuit 40 The timing circuit 40 is also controlled by a fast clock pulse generator 42 which has an input 42a synchronized from the slow clock pulse generator 43 and an output 42b where pulses appear for example at a frequency of 1 000 hertz The pulses are fed to the synchronizing input 40a of the timing circuit 40 The timing circuit 40 also controls the voltage wave form generated by a collector drive circuit 36 having an output terminal 365 at which under no load conditions 4 117 400 10 proper polarity positive pulse fed to the input 62a thereof on
56. test good under the high drive in circuit test then the operator will determine whether the transistor or FET device has a satisfactory Bain under out of circuit conditions by moving the test switch 18 to its various positions to see if the lamp 20 or 20 will become energized If a lamp does not become energized the operator is fairly certain that the transis tor is defective and he can then dispose of the same However if the transistor or FET device under test out of circuit results in the energization of one of the lamps 20 or 20 then he will generally carry out further tests as indicated to see whether the device tested poorly in circuit because of very low shunting imped ances or because of excessive leakage after he has deter mined whether the device is a silicon or a germanium semiconductor device To this end knob 30 of a function control switch 32 spring urged into a center position is moved against the return spring pressure so that a projecting nose portion 30 thereof is moved opposite a reference line 31a lead ing to the word IDENTIFY If the device involved is a silicon device a lamp 28 will become energized and if it is a germanium device a lamp 28 will become ener gized Indicia Si and Ge opposite the lamps 28 and 28 indicate the type of semi conductor material which the energization of the adjacent lamps 28 and 28 are respectively to indicate Next the knob 30 is rotated to an opposite extreme pos
57. tested in either the low or high drive modes of operation of the present invention However only a FET device with an unusually high gain will test good under a low drive test Therefore to insure a valid test for all FET devices the high drive mode of operation of the present invention should be initially used when the device being tested is known to be a FET device In accordance with another aspect of the present invention the base drive waveforms utilized in the com mercial form of the Boatman circuit disclosed in said U S Pat No 3 870 953 are modified so that FET de vices can be reliably tested The base drive pulse wave forms of the Boatman et al circuit comprises a pulse of a given polarity which starts from zero at the beginning of the test interval for each transistor type and drops to z ro after termination thereof The zero level drive voltages cannot render FET devices non conductive and so the current transition produced in a FET device by these waveforms do not produce current transitions which can be reliably detected In accordance with the present invention the control terminal drive waveforms produce current transitions in properly operating FET 5 20 25 30 35 40 45 50 55 65 1 CIRCUIT FOR TESTING TRANSISTORS OR THE LIKE BACKGROUND OF INVENTION This invention relates to circuits for testing transis tors or FET devices for satisfactory gain both in circuit and out of circuit U
58. tput of the operational amplifier will be at zero volts This occurs when the 5 device under test is a germanium device which pro duces a control to load terminal voltage drop of less than 0 4 volts When the voltage at the output terminal 1645 is 5 volts this voltage is applied to one of the terminals of 10 the light emitting diode or lamp 28 in turn connected through resistor 182 and the collector 184c and emitter 184a of an NPN transistor 184 to the T and L termi nals of the section 32e of the function control switch 32 The switch section 32e has a wiper 32e which is grounded The transistor 184 is maintained in a non conductive state until the NOR gate 72 has a positive output indicating that the device being tested is an ap parently properly operating transistor or FET device Accordingly a conductor 188 connected to this NOR gate extends to a resistor 186 connected to the base 1845 of the transistor 184 The 5 volts at the output terminal 1645 of the oper ational amplifier 164 is connected through a resistor 176 to the base 178b of PNP transistor 178 whose emitter 178a is connected to the 5 volts bus 140 and also through resistor 179 to the base 178b Thus under the 5 volts output conditions of the amplifier 164 transis tor 178 is non conductive When the device under test is a germanium device and the output of the operational amplifier 164 is zero volts this will render the transistor 178 conductive provided
59. trans ducer under test and providing an indication to the operator correlating the lead colors with the test switch position all of the transistor terminals can be identified In some rare cases high frequency transistors or tran sistors with higher than usual gain levels may test out satisfactorily in two low level drive test switch posi tions where the transistor has sufficient gain in both possible directions of conduction thereof as in the case of symmetrical bipolar devices like FET devices The high control terminal drive level is selected so that maximum sensitivity is achieved for testing highly shunted in circuit transistors However under such con dition unsymmeterical bipolar transistors i e transistors having substantially different current gain in the two possible directions of current flow having a satisfac tory circuit gain will test good for two of the six possi ble connections of the test switch under modestly low shunting conditions because most transistors under these conditions will then have sufficient forward and reverse gain to test out satisfactorily for forward and reverse directions of current flow therethrough Since most good transistors will test satisfactory in only one test switch position during the low drive test lead iden tification can be obtained under most test conditions leaving the high amplitude level test for testing under the most severe in circuit shunting conditions FET devices can be
60. tus comprising test device con necting terminals to be connected to the respective terminals of a transistor device or the like to be tested in circuit or out of circuit an intermittently occurring load terminal energizing voltage source means an inter mittently occurring control terminal driving voltage source means said voltage sources when applied to the proper load and control terminals of transistor devices or the like producing load current transitions indicative of the current gain thereof means for selectively pro viding relatively high and low drive levels from the proper connection of said voltage source means to the load and control terminals of the transistor device or the like being tested said low drive level providing a load current transition of at least a given level for transistor devices having a forward current gain only above a given minimum value when the device is in a circuit having a shunting impedance of a given value but fails to provide a load current transition of said given level when said circuit has a very low shunting impedance of a fraction of said value said high drive level providing a load current transition of at least said given level for most transistor devices having a current gain of at least 19 the operational amplifier which then produces 4 5 volts at the output terminal 1645 thereof When neither of the input terminals 164a or 164a receives a voltage through the rectifier 160 or 162 the ou
61. under the low base drive mode of operation of the present invention or a FET device does not show suffi cient current gain under the high gate drive mode of operation of the present invention the device is re moved from the circuit and re tested under the appro priate signal level conditions to determine whether or not the device involved tested unsatisfactorily because of high shunting impedance conditions or because of the defective operation of the transistor or FET device A transistor which tests good under an out of circuit condition but failed the test under the in circuit condi tion can be further evaluated to determine whether the leakage thereof is excessive In accordance with an other aspect of the present invention leakage tests and also transistor material identification tests to determine whether the device is a germanium or silicon transistor which is necessary to perform a proper leakage test can be carried out without the operator concerning himself about the selection of test voltages of proper polarity In this aspect of the invention when a detection operation identifies under a high base drive condition a transistor of the PNP or NPN type having a satisfactory gain level but which did not test out properly under the low base drive test indicating a possibly leaky or heavily shunted transistor a test circuit voltage or proper polar ity is automatically set up to produce a test voltage of proper polarity for a leakage
62. unting impedances are present This transistor testing apparatus however did not provide for the testing of FET devices and in other respects did not give the operator maximum aid in car rying out leakage and material type tests or enable the operator to select different control terminal drive lev els as in the case of the present invention to be de scribed which has unexpected advantages to be de scribed The present invention therefore represents an im provement over the testing apparatus which is the sub ject of said U S Pat No 3 870 953 Accordingly one of the objects of the invention is to provide improved transistor testing apparatus operating on the principle of that disclosed in said US Pat No 3 870 953 and which further permits the use of Bach apparatus in the testing of FET devices Another object of the invention is to provide transis tor and FET testing apparatus as described which gives the operator greater flexibility in his testing of the de vices involved A related object of the invention is to provide transistor and FET testing apparatus which makes it simpler for the operator to carry out material type and leakage tests where the initial testing of the devices raises the question as to whether or not the devices have excessive leakage 2 SUMMARY OF THE INVENTION In accordance with one of the features of the present invention there is preferably provided a selection of at least two
63. utline of waveform W5 of FIGS 4 and 5 which is positive only during the PNP test interval Waveform WS is the waveform appearing at the Q output termi nal of the flip flop circuit F3 and it is zero during this test interval A conductor 125 extends from the Q output of the toggle flip flop circuit F1 at which terminal the wave form W2 of FIG 4 appears to the toggle input terminal T of flip flop circuit F2 Since the toggle flip flop cir cuit F2 is toggled only during a zero going pulse fed to the T input terminal thereof the waveform W4 appears at the Q output terminal thereof which waveform is positive except during the second half of the NPN test interval and the first half of the PNP test interval Thus the waveform W4 is a zero going pulse centered over the middle portion of the NPN and PNP test intervals The waveform W3 which is positive during the dura tion of these test intervals and the waveform W4 which is zero during a period centered within the test intervals are utilized to generate the base drive voltage wave form W7 shown in FIG 5 The waveform W3 generated by toggle flip flop cir cuit F5 is fed by conductors 118 and 128 to the input 1025 of a NAND gate 102 and the waveform W4 generated by toggle flip flop circuit F2 are fed by con ductors 130 and 132 to the input 120a of a NAND gate 102 The outputs 102c of NAND gate 102 is coupled through a resistor 134 to the base 1356 of a PNP transistor 3
64. ve tests indicating the possibility that the transistor or FET device involved has excessive leakage therein or that the transistor was located in a heavily shunted circuit Thus when such a transistor or FET device tests satis factory in an out of circuit test or at any other time when the transistor tests satisfactory a test voltage supply circuit 77 is automatically operated to provide at its output 77b a DC voltage of proper polarity to carry out a materials or leakage test for the NPN or N channel device or for the PNP or P channel device involved Accordingly the test voltage supply device 77 has an input 77a connected by conductor 81 to the output 65b of one of the flip flop circuits 65 If either one of the 20 25 30 35 40 45 50 55 60 65 9 coupled through the function control switch section 32c directly to one of the load terminals generally the col lector of an unsymmetrical bipolar transistor device under test to obtain a good gain indication When the output terminal 36b of the collector drive circuit is connected to the collector of satisfactorily operating NPN transistor or either load terminal of a satisfactorily operating N channel FET device as previously indi cated because of the voltage dropping effect of various impedances connected to the output terminal 362 of the collector drive circuit the voltage which appears thereat will be different from the collector drive wave form W8
65. widely different control terminal drive levels for the test circuit As in the case also with the commer cial form of the test apparatus disclosed in said U S Pat No 3 870 953 a manually operable six position test 4 117 400 4 DESCRIPTION OF EXEMPLARY EMBODIMENT OF THE INVENTION Referring now more particularly to FIG 1 the test ing apparatus shown therein includes a housing 2 in which all of the mechanical and electrical components to be described are housed and as seen from the side thereof which includes the front control panel 2a Ex tending from the bottom of the control panel are three differently colored connecting leads 4a 4b and 4c hav ing conductive tips 62 6b and 6c adapted respectively to contact the unknown terminals of a transistor or FET device while it is still connected into its normal circuit The leads have plug units 8a 8b and 8c which are insert able within jacks 10a 105 and 10c When the test of a transistor or FET device in circuit indicates the need for further testing such device is physically removed from its circuit and the leads extending from such de vice are then inserted within the three apertures of socket 12 The control panel 2a also has projejcting therefrom the movable control arm of power on off switch 14 and a lamp 16 which becomes lighted when the power on off switch 14 is operated to its on posi tion After power is turned on generally the movable control arm of a d

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