SHARP SERVICE MANUAL - The Sharp MZ
Contents
1. Tm 99699999 Perspective View Parts fitted face lt lt Opposite Side E wT P i d n lae a a 1 LI E el 12 i TTE 5 a laao 06 TUDOD 0000007 eS 040 4 oiCl per EF teo s L IIT XY um 5 2 a i A ie Y o Dk D iat op m Notes The printed wiring board and circuit diagram are subject to change without prior notice 09005920000 Printed Wiring Board 27 A B C _ D 2 F G K L M N P Circuit Diagram 6 5245 icis RMPTHOOOIPAZZ IEC CONNECTOR Diosa sn ii Da 7 Os a2 DIOS Di HG Da 6 m e zs ew fis NRFDIRI 37 Dit ZBOA P O NDAC R LHOOBLA 1 EOIR FAN As SPO 39 Aa AS GND 1 GND Enable x 43 n n E s rete be oe ex Jp 21 2 an Mi PARTS SIDE amp c3 068 1 WEE MR TM icin zcu 3 id R RESET te Cii IOyF tOv iyFzi2V IO wv2. X wii 28 PACKING METHOD 2 8 103 or 2 88104 7 Protected Seat SSAKHOO43PAZZ PWB Sleeve SPAKSO028PAZ2Z Packing Case 5 0185 22 for MZ BBIO3 187 22 for 2 88104 Instruction Manual TiNSE0036PAZZ English for MZ BBIO3 5 0037 22 English for 2 88104 Seal x 2 TSELFOO01PAZZ 30 NOTES Be sure to use regular parts for securing the safety and reliability of the set Be sure to replace these parts with specified REPLACEMENT PARTS LIST ones for maintaining the safety and performance of the set MODEL 2 88103 REF NO PART NO INTEGRATED CIRCUITS RH iX0297PAZZ 2 RH iX0305PAZZ IC3 RH iX0190PAZZ IC4 ICS 2 22 RH iXOOB5SPAZZ 9 RH iX0152PAZ2 iC13 DUNTKOOG4PAZZ DESCRIPTION MC14411 SN75189AN SN74LS266N Hybrid IC SN75188N TL497CN 12N10K1 TRANSISTORS AND DIODE Q1 VS2SA496 0 1 D1 VHO1S1586 1A RESISTORS R1 VRC MT2EG106K R2 SC2EF102J e VRD SC2EF102 R3 F103J i VRO SC2EF103 R4 VRD SC2EF272J RS VRD SC2EF472J R6 VRD SC2EF 101J i SC2EF10 R7 VRD RU2EE222J R8 VRD RU2EE561J R9 VRD RU2EE273J R11 VRO SC2EF221J R12 VRO SC2EF561J R13 VRN RT2HCIROF 816 VRD SC2EF104J RMPTCIOI9PAZZ CAPACITORS e VCTYPU18D1042 C2 oo 254496 0 151586 10M ohm 1 4W 1K ohm 1 4W 10K ohm 1 4W 2 7K ohm 1 4W 4 7
3. 1 210 6 45V ENE Cn DTR am 254496 7 1 2 5 75 694 9L 9 9 9 93 44 PY lt 100 1 u CHANNEL 8 9 THDA 0 0 9 3 CHANNEL A 75088 Sasa a 13 CSTA ier DTRA 3 6 7 si 4 8 DCOA f 5 9 C2 8 RH iX0305PAZZ 7 8 0085 22 SN75189A ROE OL SN75188N Vcc 4A 4 4Y 3 Vcc 4B 4A 4Y 3B PIN ASSIGNMENT PIN ASSIGNMENT Top View Top View 1A 1Y 2A 28 2Y GND Block 5 Block 6 Power Supply Circuit DUNTKO064PAZZ 12N10K1 Bus Interface Circuit The serial interface card consists of six blocks and if each block functions normally a faulty operation is caused by an external factor Ex program the counterpart machine etc Circuit Blocks and Check of Behavior 2 80510 is built in and test the function by the test program Port address Check if an address code set by SW 1 DIP switch is output selector If the output does not agree wired or output is a low level Check if MC14411 is outputting oscillation and setting Frequencies are as follows F1 153 6 KHz F8 9 600 Hz F3 76 8KHz F9 4 800 Hz Fb 384 KHz 211 2 400 Hz F6 28 8KHz F13 1 758 8 Hz F7 19 2KHz F14 1 200 Hz Be sure t
4. 8513 9519 109185 doo 2 I d uan Circuit Diagram ESI ACL EST UNI 128195 ssauppy 3203 Und A ddng J9MOd sng 103409 sng AG sng ssaippy Construction of Circuit The serial interface card consists of the following six blocks Block 1 Hybrid IC circuit Block Diagram of Hybrid IC D D Data Bus D Driver TxDA D RxDA 0 Channel RTSA D Channel A Data CTSA Di Read Write TRA Do Registers Control DCDA W RDYA RD Intetnal Bus 1 R T 5 TxDB RxDB Ao RTSB Channel B Channel 8 CTSB tai Read Write Date DTRB Logic Registers amp CDB ExINT 9 Control p IEI W RDYB IEO SYNCA BR1 BR2 Block 2 Port Address Select Circuit 1 5266 2 4 RH iX0190PAZZ SN74LS266N PIN ASSIGNMENT Top View Block 3 Baud Rate Oscillation and Setting Circuit IC w 2 w 5 MCI441I 1C1 RH iX0297PAZZ MC14411 PIN ASSIGNMENT BLOCK DIAGRAM Top View Rate Select 23 Rate Select g 22 O 210 Crystalas 200 Reset 100 Block 4 Driver Jumper Switch and Connector Circuit P o 2 8 ES o P 19 800 38496 0 75100 3 Rie 540 I 9 RTS Tice 0 R E o 2 L etm 1C 751894 5 5 2 cs 5 a 4
5. 5 W 4 IORQW RD IORQ A Ao SELECT 9 RH iX0303PAZZ SN74LS138N Pin Assignment Top View DATA OUTPUT The address decoding logic forms CE signal of PIO and R Wy and W signals of HIC from the signals Ag to RD WR and The decoded output of COH to C7H is used by the data buffer control logic 4 Data Buffer Contro Logic IEI IEO Mr RD Decoded output of to C7H No 1 of 6 1 5245 The data buffer control logic regulates the buffer connecting the CPU data bus line and the bus lines of PIO and CPU reads data when the No 1 pin of IC6 is in low level CPU reads data when the IO addresses of COH to 7 are input to CPU and CPU reads the interrupt vector from PIO in the mode 2 interrupt acknowledge cycle 5 Timing Circuit 22 HIC HIC The timing circuit forms pulses of about 500usec and about 5usec 500usec determines the time for receiving one command when the signal is received in the slave mode and determines the time from trans mitting data to the GP IB data bus to outputting DAV It is so designed that 500usec pulse is not generated until El becomes high level by considering the disposition of by interrupt MZ 8BIO4 TROUBLESHOOTING ra Y IPE function BASIC Commands other than GP iB does not work normally Does beco
6. 6 PWB circuit diagram Packing Method Rene rre hasse ote e a Se PUR S Fo ETE EA n ag Replacement parts 51 IP MZ 8BIO3 SPECIFICATIONS Communication method Asynchronous Standard compliance with EIA RS 232C Control LSI Z 80SIO O Number of channels 2 Channel A and Channel B 20mA current loop Changeover is allowed for one channel Channel B Baud rate Can be set independently for the two channels Manual setting using switch Number of baud rates 10 75 110 150 300 600 1200 1800 2400 4800 9600 baud Character length 5 6 7 or 8bits Selection by software Parity bit Odd none or even Stop bit 1 1 or2 Mode Either terminal mode or modem mode can be selected for each channel through the use of jumper chip 2 80 vector interrupt can be used Manual setting with switch 0 50 3 j 25 C 80 C Interrupt Port address Operating temperature Storage temperature MZ 8BIO3 GENERAL INFORMATION a introduction Ther are two methods of data communication between computer and external equipment 8 bit parallel and bit serial The serial interface card MZ 8BIO3 hereinafter referred to as interface tard permits data communication by the bit serial method This interface card is manufactured in accordance with
7. 8 1025 REM by BASIC interpreter 1030 REM 1040 REM HE E EF HF E E E HF E HE E E FF FF AE E FE OF HE FF FF AE HF HF HF HF E HF GA HF 4 1050 REM 1060 REM Parameter 1070 REM 1080 REM DEFB 18H 18 1090 REM DEFB 10H DATA 10 1100 REM DEFB 10H DATA 10 1110 REM WR4 DEFB 4 DATA 04 1120 REM DEFB 4FH DATA 1130 REM WRS DEFB 5 DATA 05 1140 REM DEFB EAH IDATA 1150 REM WR3 DEFB 3 DATA 03 1160 REM DEFB EOH 1 DATA EO 1170 REM 1180 REM MODE ENT adr 2 F009 J 1190 REM LD 1200 LD B19 DATA 06 09 1210 REM LD HL MR 21 00 F0 1220 REM OTIR DATA 1230 Ln C CHBCT DATA 1240 LO 9 06 09 1250 REM LD HL WR DATA 215 00 FO 1260 REM OTIR 1270 LD A13 DATA 03 1280 OUT DATA D3 B1 1290 REM LD HR3 1 08 1300 OR 1 F 6 01 1310 REM OUT DATA 03 81 1320 LD Ar3 DATA 3E 03 1330 REM QUT CHBCT A DATA D3 B3 1340 REM LE WR3 1 08 1350 REM OR 1 01 1360 OUT CHBCT A DATA 03 83 1370 REM RET DATA C9 1380 REM 1390 REM INPUT ROUTINE 1400 REM INER O NO ERROR 1410 REM bit4 j PARITY ERROR 1420 REM bitS 1 OVERRUN ERROR 1430 REM bit zl FRAMING ERROR 1440 REM 1450 INER ENT
8. DATA 57 1890 REM JR Z CHBOUT DATA 28 1900 LD CHAR DATA 34 33 0 1910 OUT CHBDT A DATA D3 B2 1920 REM RET DATA C9 1930 REM END DATA END 1940 REM 1950 DIM X 300 LIMIT 2000 15 4096 1960 FOR 0 TO 9 X J sJI INEXT FOR Js0 TO 5 17 10 1965 PRINT SIF SUBROUTIN LOADING 1970 READ X 1IF X 2 END THEN 3000 1980 16 9 1 1 48 CASC MID X 2012 48 1990 POKE P J P P 1 GOTO 1970 3000 REM 944494 4X4 X AER HF 3F 4F HF HF 3010 REM 3020 REM MAIN PROGRAM 3030 REM 3040 REM FE FE FF E EF HE JE E FF JE AE AE AH AE 3050 REM 3060 USR FOO9 mode set 3070 s4444 TEST PROGRAM Serial I F MZ 8BIOS3 3080 PRINT 3090 PRINT Channel A TEST 3100 FOR 1 0 TO 255 3110 POKE FO33 I USR F060 POKE F033 0 REM channel A output 3120 USR SFO34 033 2032 REM channel A input 3130 IF ERX 0 THEN PRINT COMMUNICATION ER STOP 3140 IF 1 lt gt THEN PRINT COMPARA ER STOP 3150 PRINT 3 NEXT 3160 PRINT OK 3170 PRINT 3180 PRINT Channel B TEST 3190 FOR 1 0 255 3200 POKE FOS3 I USR FOG6C SPOKE F033 0 REM channel B output 3210 USR FO4A FOSGS ERSPEEK FO32 REM channel B input 3220 IF lt gt 0 THEN PRINT COMMUNICATION ER s
9. data are the same at the time of transmission receiving Setting jumper blocks on the card For the self diagnosis as mentioned above set the jumper blocks on the card as follows J 1 i J 2 J 3 z Since port addresses BOH B1H B2H and B3H are used in the program set the switch SW 1 in the following factory setting OFF ON OFF OFF ON Switch position Set the switch for baud rate setting as desired After setting each mode install the card in MZ 80B On this occa sion signal cable needs not to be connected Flow Chart of Self diagnosis Program Start testing Channel A Stop the program when an error occurs If Channel is found normal test Channel B then _ Set Z80 SIO mode Start checking Start checking Channel A Channel 8 Output test data from Channel A input from Parity error framing error or Overrun error Output test data from Channel 8 Input from Channel B Parity error framing error or Overrun error Same as transmitted data Same as transmitted data Contents or error displayed Contents of error displayed Test completed Channel A is Channel B is normal normal 11 P m Program by BASIC language Now let us draw up the program described in the above mentione
10. error overrun error framing error etc Causes Wrong borate setting Abnormal borate oscillator Wrong jumper set ting 1 2 and J 3 Abnormal 12V or 12V line Faulty connector Faulty counterpart machine Other Signal is not input Control does not return from input routine in test program run Causes Wrong borate setting Abnormal borate oscillator Abnormal 12V or 12V line Wrong jumper setting J 1 J 2 and J 3 Faulty connector Faulty operation of hybrid IC Faulty counterpart machine Faulty driver 1 Other O shows a related circuit Circuit blocks Faulty symptoms and probable causes 12 or 12V line deviates over 1096 Causes Faulty TL497AC Faulty 12N10K 1 Short circuited load Short circuited electrolytic capacitor Other Borate oscillator does not output Causes Faulty MC14411 Faulty crystal Two or more dip switches SW 2 SW 3 turned on Faulty borate clock input circuit of hybrid IC O shows a related circuit Self diagnosis program Let ys consider a program for self diagnosis of this interface card and assume that data are transmitted from Channel A are received by Channel For channel B similar communication system shall be adopted Self diagnosis of the interface card can be made by examining whether the receive data and transmit
11. waiting logic and a data buffer control logic so that the mode 2 interrupt of Z 80A can be utilized by Z 80APIO Data bus 2 808 bus line RESET Buffer control logic Address decod ing logic Waiting logic lt p 4 line 2 8 104 Block Diagram 19 Management Data bus 3 Hand shake line 5 Management line Description of Hybrid RMPTHOOO1PAZZ for GP IB The hybrid IC mounted on the GP IB interface 2 88104 of MZ 80B integrates the hand shake logic bus driver receiver etc which are the proper circuits of GP IB circuit into one package By connecting this HIC hybrid to the I O ports of an ordinary microcomputer the functions of Tg L4 SH and AH and the inputting and outputting of the management line and data line are enabled DB 27 3 Data line E ar 0 5108 t 8 H0001PA 31 58 Internal register R1 19 107 it t 32 read write pulse w2 16 bias DAVIR 2 33 L DIOS NDACIR 4 34 0104 Input to hand EOIR 2 shake line and ATN R lt 6 35 0103 management line SRO R 7 m IFC R 3 0102 RENIR 9 37 EOI D 11 DIO Gp IB tine 12 38 Management 13 line output IFC D 4 39 ifo Enabling manage RENID 40 REN ment lines other ENABLE 10 than 41 ATN i TACS 49 Reporting of LACS 50 43 internal logic 51 DAV status SPAS 44 47 NRFD Reset signal CLR 45 Waiting time NBA 4
12. 3 2032 1 1460 REM DEFS 1 DATA 00 1470 REM CHAR ENT C adr z F033 J 1480 REM DEFS 1 DATA 00 1490 REM 1500 REM CHAIN ENT adr z F034 1 1510 REM IN CHACT DATA DB B1 1520 REM RRCA DATA OF 1530 REM JR NC CHAIN DATA 30 1540 REM LD 1 DATA SE 01 1550 REM DATA 03 81 1560 REM IN 1 1570 REM AND 70H E6 70 1580 Lo 32 32 F0 1590 REM IN CCHADT DATA BO 1600 REM L CHAR A DATA 32 33 20 1410 REM DATA 9 13 1630 REM CHBIN adr FO4A 2 1640 REM IN CCHBCT DATA 08 83 1650 REM RRCA DATA OF 1660 REM JR NC CHBIN DATA 30 FB 1670 REM Lo 1 IDATA 1 1680 QUT 03 83 1690 IN CHBCT DATA DB B3 1700 REM AND 70H 70 1710 REM Ln 1 DATA 32 32 20 1720 IN DATA 08 82 1730 REM Lo CHAR A 32 33 FO0 1740 REM RET DATA C9 1750 REM 1760 REM OUTPUT ROUTINE 1770 REM 1780 REM CHAOUT ENT C adr F060 J 1790 REM IN CHACT DATA DB Bi1 1800 REM BIT 214 DATA 57 1810 REM JR Z CHAOUT DATA 28 1820 REM LD CHAR IDATA 34 33 FO 1830 REM CHADT A DATA D3 BO 1840 REM RET DATA C9 1850 REM 1860 REM CHBOUT ENT adr FO6C J 1870 REM IN CHBCT DATA DB B3 1880 REM BIT 2 amp
13. 6 iC9 10 12 14 PART NO RH iX0078PAZZ RH iX0276PAZZ 0149 22 RH iX0102PAZZ RH iX0070PAZZ RH iX0124PAZZ RH iX0200PAZZ RH IX0303PAZZ RH iX0075PAZZ 0229 22 0227 22 RMPTHOOO1PAZZ Ontsisrons R1 R6 R2 R4 R3 R5 VRD SC2EF332J VRD SC2EF221J VRO SC2EF153J VRO SC2EF331J MODEL MZ 8BIO4 PARTS LIST MODEL 2 8 104 DESCRIPTION SN74LS32N SN74LS191N SN74LS27N SN74LS14N SN74LSOON SN74LS245N SN7407N SN74LS138N SN74LSOBN LHOO81A Z 80APIO SN74LS221N Hybrid IC 3 3K ohm 1 4W 220 ohm 1 4W 15K ohm 1 4W 330 ohm 1 4W CODE AF AL AF AM AE AR AG AG AE BD AN BY AA AA AA AA REF PART NO NO R7 VRD SG2EF123J RB VRD SC2EF822J R9 VRD SC2EF1 Ein ID SC2EF103J CAPACITORS VCKYPU2HB102K VCQYKU1HM683K C4 VCQSMU1HM102J C5 VCEAAU1AW107M C6 VCSACU1AE106M c12 VCTYPU1BD104Z C24 MISCELLANEOUS QPLGZO105PAZZ LANGKO297PAZZ TiNSEO037PAZZ 32 DESCRIPTION 12K ohm 1 4W 8 2K ohm 1 4W 10K ohm 1 4W 1 000PFD 500V Ceramic 0 068MFD 50V Film 1 000PFD 50V Film 100MFD 10V Aluminum 10MFD 10V Tantalum 6 1MFD 12V Ceramic 25 Pin Terminal Fixing Metal of 25 Pin Terminal Instruction Manual English CODE AA AA AA AA AB AC AB AD BC AG BR
14. 6 NDAC setting NBAW EO Weinert 2 53 32 SG Signal ground 1 17156 28 29 48 Vee GND Block Diagram of Hybrid IC NI Driver Receiver 20 Description of Each Circuit Each circuit will be described The logic diagrams used for description are simplified schemata of logic p 1 Reset Circuit RESET To M1 MI The circuit is intended to reset PIO by the RESET signal from 2 808 CPU board 2 is reset when MI terminal is active for 2 clock cycles or over providing that both RD and TORO signals are not active The RC circiut in the diagram is a low pass filter provided for preventing faulty operation due to noise 2 Waiting Circuit IOR QW EXWAIT Vcc The waiting circuit corrects the timing of the interrupt vector transmitting from PIO to CPU in the interrupt ac knowledge cycle Thus IORQW develops a signal of reversed TORO and EXWAIT doesn t develop pulse in other cycle than the interrupt acknowledge cycle This waiting circuit does not correct the timing of the daisy chain With the delay of the daisy chain IEO look ahead is carried out on the extension 1 interface of MZ 80B The timing chart in the interrupt acknowledge cycle is illustrated below 250nsec Last M cycie Wait line Interrupt Tw detection Interrupt vector detection Ti Tw S Tw input 21 3 Address Decoding Logic Decoded output of to to PIO COH C3H
15. EIA RS 232C the Electronic Industries Association RS 232C and used for data communication with other equipment having interface based on RS 232C Functions of this interface card The interface card has the following functions 1 One card has two channels each of which is capable of transmitting receiving data independently 2 Oneofthe ten baud rates can be selected by operating the switch on the card Baud rates can be set independently for the two channels 3 Output connector signals to external equipment can be in either terminal mode or modem mode through the operation of the jumper chip 4 This interface card can be used as 20mA current loop for one channel Applications Equipped with the above mentioned functions the interface card has a variety of applications Some applications of this very versatile serial interface card are shown below Data communication between computers on telephone line via acoustic couplers Printer Plotter Digitizer Color display Card reader Magnetic tape equipment 1 2 3 4 5 6 7 MS Gunes arey pneg g 5 UNO o 310 pneg Z MS 1125 pneg 2 515 10120uu02 322125 V 1 5 apow if 10128Uu0 12 5 8 jauueyd apoyw CIRCUIT 7518 4 MZ 8BIO3 DESCRIPTION OI PuqAH
16. K T soe 12 100 TA id CHANNEL B CHANNEL A ai m lt MZ 8BIO3 17 Interface standard accordance with IEC Standard TC66 Interface funcion Functions executable in 2 808 Version up BASIC language Basic talker Serial poll Cancellation of talker by MLA Interface message transmit Controller receive Controller pass Controll pass to itself Parallel poll Output connector Male type connector in compliance with IEC Standard Operating temperature 5 C 35 C Storage temperature 0 C 50 C Power source DC 5V supplied from MZ 808 Reference The following specifications are reference specifications since difference is caused by cable quality connector connection noise and other environmental conditions 1 Number of instruments per 15 max including MZ 80B system 2 Full length of cable per system 20m or less However length per instrument shall be about 2m 1f the number of instru ments exceed 11 in one system cables of 2m or less shall be used between instruments so that the full length wil be 20m or less Note The above mentioned specifications may be changed in the future for improvement of the product 18 Block Diagram This interface circuit consists of a hybrid IC for GP IB Z 80APIO and various logics to connect them to the extension 1 of MZ 80B Some of included logics are a
17. K ohm 1 4W 100 ohm 1 4W 2 2K ohm 1 4W 560 ohm 1 4W 27K ohm 1 4W 220 ohm 1 4W 560 ohm 1 4W 1 ohm 1 2W 100K ohm 1 4W Resistor Array 3 3K ohm x 6 O 1MFD 12V Ceramic CODE BA AM AF BU AM AU BF AF AB AA AA REF PART NO NO C3 ae VCTYPU1BD104Z ii 7 VCKZPR1HB221K C22 RI C24 C8 VCEAAUOJW107Y C9 c11 C12 VCKZPR1HF103P C18 C20 C10 VCSACU1AE336K C13 C15 Y cis VCEAAU1CW336 C21 C17 VCCSPR1H6151J MISCELLANEOUS L1 RCiLF7863VAZZ us RCiLF7862VAZZ L3 RCiLF7864VAZZ X TAL 5 0017 22 Sw1 QSW D0004PAZZ sw2 QSW DOOO6PAZZ Sw3 gt J 1 QPLGZ0103PAZZ J 2 P PAZ QPLGZ0102PAZZ QJUM 0004PAZZ CN1 22 ENS QPLGZ0104PA LANGKO296PAZZ 050 20010 22 TiNSEO036PAZZ 31 DESCRIPTION 0 1 12V Ceramic 220PFD 50V Ceramic 100MFD 6 3V Aluminum 0 01MFD 50V Ceramic 33MFD 10V Tantalum 33MFD 16V Aluminum 150PFD 50V Ceramic Coil CHO4 Coil CHO3 Coil 85651 Crystal 1 8432MHz Dip Switch 6 contacts Dip Switch 10 contacts 4 Pin Plug 3 Pin Plug Jumper for J 1 J 2 J 3 9 Pin Terminal Fixing Metal for two 9 Pin terminal 24 Pin IC Socket instruction Manual English CODE AB AB AD AB AA AG AG AK AP AR AR AD AC AF AY AF AF BP Cx INTEGRATED CIRCUITS IC1 c2 ICB 5
18. MZ 8BIO3 MZ 8BI04 SHARP SERVICE MANUAL PDSMX81013 MZ Qm am _ EI RS 232C Serial Interface Card M Z 8BIOS3 MZ FEATURES 2 8 103 serial interface card for 2 80 capable of converting parallel 8 bits data to serial data to transmit and receive Integrating two channels of interface conforming to RS 232C JIS C 6361 into one board e Employment of 2 80510 0 one of Z 80 family enabling to deal with various interrupts MZ 8BI04 s GP IB interface card for MZ 80B capable of freely controlling measuring instrument groups conforming to IEC standards 4PEE 488 and enabling low cost automatic measuring system Capable of programming by improved BASIC SHARP CORPORATION e M xa ox E a Contents M2 8BIO3 Specifications General information rsi sl DE aon UR RUE MEA RES Description of Circuit ue ERRARE RUNI Ba ele ws Keres Troubleshooting s vh Ee os ee ie AS oe Y Ie 8 Test program usos osa Rye a aie da PWB and circuit diagram 2 88104 Specifications NINE Description of circuit TEILE T ro bleshooting RR a Bee
19. STOF 3230 IF I lt gt A THEN PRINT COMPARA ER STOP 3240 FRINT 4 NEXT 3250 PRINT OF 3260 END 14 L i BITTY rr e 7 Lr ws a 4 1 sm a i i i E A Sia P fe ae 4 _ 5 gt 24 9 9 4 2 5103 PWB AND CIRCUIT DIAGRAM Notes The printed wiring board circuit diagram are subject to change without prior notice Printed Wiring Board 4 2 3 4 D 6 7 3 9 10 Parts fitted face et Opposite side Perspective View 15 11 10 11 A B D E S Circuit Diagram A PARTS SIDE A7 3V Sw i RA 5v GND LzCHOS IZNI DU CIO cis BS 07 cil 53 Qi 18 44 5 EX INT 5v t LJ LJ LJ Lj 8w 2 B Ics DCDB w RDYB SYNCB TxDA RxDA RTSA CSTA DTRA DCDA W RDYA SYNCA GND BRZ w 5 A 34 2 N C D N C D N C o N C DS e X E a u 0 RYK ICT 25A496 O 55 84 5 EAE n R REK 4 Rx 5 T 220P 5 DTR c 5 AT
20. d flow chart using languages The program list is shown later In the BASIC program the routine to control the interface card is composed of machine language The machine language data are written into the memory by POKE statement and the routine is called by USR statement The routine is made by programming statement Nos 1000 through 1990 or Statement Nos 1080 1160 Parameters Clock rate x16 Stop bit 2 bits Parity Present Odd even of parity Even Transmit receive character 8 bits Auto enable Set Statement Nos 1180 1370 Mode setting routine Statement Nos 1550 1610 Channel A input routine Input data are stored in Address CHAR Error flags are stored in Address Statement Nos 1630 1740 Channel B input routine Input data are stored in Address CAHR Error flags are stored in Address INER Statement Nos 1780 1840 Channel output routine Transmit data are stored in Address CHAR Statement Nos 1860 1930 Channel B output routine Transmit data are stored in Address CHAR Statement Nos 1950 1990 Writes machine language data in the memory TBASIC Version SB 6510 SB 5510 12 by BASIC language 1000 REM st kttitk tb ERE HE HE HE EEE dt dE EEE 1010 REM 1020 REM Serial I F Subroutine for MZ 8BIO3 on 7 80
21. ecoding circuit 1 11 1C10 and Check abnormal signal Yes Faulty 12 1 The REN line of GP IB becomes low level by the command REN and high tevel by the command LCL 2 Pin 9 outputs negative pulse by reading I O address 196 Pin outputs negative pulse by writing on to address CAH 196 Pin outputs negative pulse by writing on to I O address C5H 197 24 Methods of Interpreting Whether Normal or Abnormal Each terminal is normal if it is in the following status in the READY condition after run by BASIC Ics Positive pulse Turns level when XXCOH to XXC7H are transmitted address bus mmm TT e Constant H level Negative pulse Same as MI CPU bus Negative pulse Same as CPU bus Output terminals of address decoding circuit 1 11 Develops negative pulse when 1 address COH to C3H 192 to 195 are accessed ws 25 a a gt ee oe Input terminals of PIO M Same signal as CPU bus In BASIC ready status At transmission of data to GP IB At receiving data in slave mode d Constant L level Outputs positive pulse of Constant L level about Susec Constant H level Constant H level Outputs negative pulse of about 500 lt
22. hat two or more switches of SW 2 and SW 3 DIP switch are not turned on Tolerable deviations are 0 1 for each frequency in measurement consider that the waveform of MC14411 varies according to the load capacity because MC14411 is CMOS Drivers Check the status of input signal jumpers Output of 75188 High level 10V to 12V switches and Input of 75189 Low level 10V to 12V connectors input of 75188 OV to M Output of 75189 Low 2 5V to 5V f reset the output terminal of the hybrid IC is in the high level high level of TTL level Be sure that the voltage is 5 Be sure that the output of DC DC converter is 12V 10 12 10 Power supply 5V line 12V line e 12V line Since there is no circuit part examine if the signal is input to the board normally The hybrid IC is not actuated unless the clock signal is applied to the terminal of the hybrid Bus interface Faulty symptoms and connected circuit blocks Circuit blocks Faulty symptoms 12345 6 and probable causes 2 s 4 s e Transmission buffer is not empty Control does not return from the transmission routine in test program run Causes Hybrid IC doesn t function normally clock is inoperative Wrong port address selection Abnormal 5V power supply Other Error message is gener ated from Z 80SIO parity
23. me normal when GP IB interface is removed No Fault of other part than GP 1B interface Yes Is voltage across 3 Vcc and GND normal No Shorr par etween N Normal A Abnormal With the method of interpretation refer to page 25 26 Yes ea N Normal A Pin D of IC6 Pin of 1C7 Abnormal N Pin of 1C7 22 Faulty 12 Pin 9 of ICS A Abnormal signal b 78 Faulty 1C7 Pin of A Abnormal EXWATT signal Check if input line from CPU bus is short circuited with GND or Vcc A 1 connected to input N line is faulty A A Pin 3 of IC5 Pin of 1C3 D N N Pin 02 of ICS 1C12 each input 4 Pin Q of IC5 N 4 4 A Faulty IC10 IC3 Faulty 5 23 Abnormal signal Do REN 1 and tow level by Does pin 2 ot 1C12 become high level by REN commend Does 1 12 develop negstive pulse by commands T REN end LCL Are normal signais input to pins of 1C12 Abnormal EXWAIT signal N Faulty Faulty Pin of IC1 A commands work normal D Fauity IC9 11 C9 normal 2 Yes Faulty Yes HIC No LCL commend Faulty address d
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