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1. OA gt rwdev gt q OA gt OA gt OA gt OA gt OA gt OA gt OA gt OA gt OA gt OA gt ct one of the following functions 0 System Parameters ue Read Write device y2 Software Reset x3 NVRAM Management 4a Error Reporting 1g Analyze Error Logs 6 Power Off at Main Breaker Ee NVRAM SIMM tests XE Return to selftest Command gt 2 OA gt Initiating Software Reset 1 20 SPARCserver 1000 POST User s Guide May 1993 OA gt DEMON OA gt Select one of the following functions OA gt 0 System Parameters OA gt i Read Write device OA gt 2 Software Reset OA gt Bech NVRAM Management OA gt 4 Error Reporting OA gt x5r Analyze Error Logs OA gt Ge Power Off at Main Breaker OA gt VT NVRAM SIMM tests OA gt ict Return to selftest OA gt Command gt 3 OA gt Bootbus NVRAM Management OA gt Select one of the following functions OA gt woe Print Bad Group List 0a gt 4 Clear Bad Group List OA gt y2 Print Bad Page List 0a gt w37 Clear Bad Page List OA gt vie Return to Main menu OA gt Command gt 0 OA gt Bad Memory Groups on System OA gt No Bad groups found OA gt Hit any key to continue OA gt Bootbus NVRAM Management OA gt Select one of the following functions OA gt wor Print Bad Group List OA gt Lt Clear Bad Group List OA gt 2 Print Bad Page List OA gt 3 Clear Ba
2. Level 17 e Attributes Test Module SCSI DVMA control register write write read test Testdata 0x1 0x2 0x4 0x40000000 0x80000000 Write word testdata to ESC DMA Control register Write word inverse testdata to word 0 in Lance buffered memory Read word testdata from ESC DMA Control register Compare and print error message if miscompare Testdata 0x0 Write word testdata to ESC DMA Control register Write word inverse testdata to word 0 in Lance buffered memory Read word testdata from ESC DMA Control register Compare and print error message if miscompare SCSI DVMA address register write write read test Testdata 0x1 0x2 0x4 0x40000000 0x80000000 Write word testdata to ESC DMA Address register Write word inverse testdata to word 0 in Lance buffered memory Read word testdata from ESC DMA Address register Compare and print error message if miscompare Testdata Oxffffffff Write word testdata to ESC DMA Address register Write word inverse testdata to word 0 in Lance buffered memory Read word testdata from ESC DMA Address register Compare and print error message if miscompare SCSI DVMA count register write write read test Testdata 0x1 0x2 0x4 0x40000000 0x80000000 Write word testdata to ESC DMA Count register Write word inverse testdata to word 0 in Lance buffered memory Read word testdata from ESC DMA Count register Compare and print error message if miscompare
3. MXCC Registers ID 13 10 Level 8 e Attributes Test Module Initialization Module Test the read and write accessibility of the MXCC ASIC registers using all access sizes allowed The addresses of the MXCC registers are in ECSR space and Control Space ASI 2 To prevent XDBus transactions this test uses Control Space Access only If any access causes a data access exception or unexpected interrupt the test aborts with a FAIL status The Stream Source and Destination Address registers are not tested here because they generate XDBus transactions to the BWs but they are tested after the rest of the system is initialized and tested Also the Interrupt registers must be tested later because they generate XDBus transactions to the BW A write to the Status register has bad side effects it can cause the CPU to hang So it is not tested except to read it and insure that it does not cause a trap The Reset register is tested by clearing it and verifying that it clears A Software Reset can be tested from the DEMON Menu The Error register is read only The test clears all errors then checks to insure that all error bits are cleared Possible Error Messages 6s register value indicates XBus may be broken expected X X observed X X aA o While testing s register an unexpected trap occurred MFSR X MFAR X Trap Type 2x CC Error X X SPARCserver 1000 POST User s Guide May 1993 Subtest
4. Unexpected Component ID value address X expected X or X observed X 6s register failed to return correct data address X expected SX observed X 6s register failed to return correct data expected X X observed X X Floating a expected observed Floating a bit through s register failed A le X X bit through s register failed expected SX SX observed X X Init MXCC Regs ID Level e Attributes 13 11 8 Error is Fatal Clear the MXCC error register clear all pending interrupts clear the reference miss count register and enable Level 15 interrupts Possible Error Messages This module does not check or report errors Test Descriptions 2 17 2 18 OOOO 0000 Subtest Subtest Ecache 0x0E ID 14 0 e Attributes CO Useful Test Diagnosis PUA Module CPUB Module Test the external cache system Setting Cache Size e ID 14 1 Level 1 e Attributes Error is Fatal Set or clear the bits for the selected mode half or full cache Possible Error Messages This module does not check or report errors Ecache Tags ID 14 2 e Level 8 e Attributes Test Module Initialization Module Test address uniqueness and data reliability of the external cache MXCC tags e Do a write pass in ascending order e Do a read pass in ascending order e Do a write pass in descending order e Do a read pass in descending order e Do the data reli
5. Start timeout loop waiting for receive confirmation Verify the receive data transmit data Test Descriptions ero lll No Possible Error Messages WARNING Check Ethernet cable Lance chip initialization failed CSRO expected 4X CSRO observed 4X Error condition detected CSRO 4X o oS CSRO 4X Rx msg Descriptor 1 S4X Tx Msg Descriptor 1 4X Tx Msg Descriptor 3 4X Rx data error address X expected 2X observed 2X Subtest ESC Registers e ID 45 6 Level 17 e Attributes Test Module SCSI DVMA control register write write read test e Testdata 0x1 0x2 0x4 0x40000000 0x80000000 e Write word testdata to ESC DMA Control register e Write word inverse testdata to word 0 in Lance buffered memory e Read word testdata from ESC DMA Control register e Compare and print error message if miscompare e Testdata 0x0 e Write word testdata to ESC DMA Control register e Write word inverse testdata to word 0 in Lance buffered memory e Read word testdata from ESC DMA Control register e Compare and print error message if miscompare 2 74 SPARCserver 1000 POST User s Guide May 1993 SCSI DVMA address register write write read test Testdata 0x1 0x2 0x4 0x40000000 0x80000000 Write word testdata to ESC DMA Address register Write word inverse testdata to word 0 in Lance buffered memory Read word testdata from ESC DMA Address register Compare and
6. Write halfword testdata to Lance RAP register Write halfword inverse testdata to word 0 in Lance buffered memory Read halfword testdata from Lance RAP register Compare and print error message if miscompare Lance CSRO STOP bit test e Write 0 to RAP to point to CSRO register e Testdata CSRO_STOP e Write halfword testdata to Lance RDP register e Write halfword inverse testdata to word 0 in Lance buffered memory e Read halfword testdata from Lance RDP register e Compare and print error message if miscompare 2 100 SPARCserver 1000 POST User s Guide May 1993 No lll Lance CSR1 register write write read test Write 1 to RAP to point to CSR1 register Testdata 0x1 0x2 0x4 0x4000 0x8000 Write halfword testdata to Lance RDP register Write halfword inverse testdata to word 0 in Lance buffered memory Read halfword testdata from Lance RDP register Compare and print error message if miscompare Testdata Oxffff Write halfword testdata to Lance RDP register Write halfword inverse testdata to word 0 in Lance buffered memory Read halfword testdata from Lance RDP register Compare and print error message if miscompare Lance CSR2 register write write read test Write 2 to RAP to point to CSR2 register Testdata 0x1 0x2 0x4 0x4000 0x8000 Write halfword testdata to Lance RDP register Write halfword inverse testdata to word 0 in Lance buffered memory Read halfword testdata from Lance RD
7. BW MQH Cache Consistency e ID 37 1 Level 17 e Attributes Test Module Test consistency between the external cache subsystem and the memory CC BW MEM The IOC chip is frozen for this test Assign a test address for each board Each board has a cache line in virtual page 0 Set the line to valid and owned by this cache Fill the line with a test pattern Each subblock will have a different pattern Read and verify the first doubleword of each subblock Read hit external cache will return the data to CPU Victimize this line check the new tag Check main memory to verify that the Ecache flush occurred Verify that this new line will not have owner set Read miss fill from main memory Check data and tags SPARCserver 1000 POST User s Guide May 1993 Possible Error Messages Note This is a common group of error messages used by all the POST Consistency tests Block compare failed load address X data X X store address X data X X Block check error address X expected SX observed X Stream ready bit timed out Check tags failed cctag X X exp state x bwtag X exp state x Check Dcache tags failed address X expected valid bit x observed valid x DCache tag has inconsistent state ptag X X Read hit Ecache data error addr X expected SX SX observed X X Read miss Ecache data error address X expected SX SX observ
8. Block compare failed load address X data X X store address X data X X 2 46 SPARCserver 1000 POST User s Guide May 1993 No lll Block check error address X expected X observed X Stream ready bit timed out Check tags failed cctag X X exp state x bwtag X exp state x Check Dcache tags failed address X expected valid bit x observed valid x DCache tag has inconsistent state ptag X X Read hit Ecache data error addr X expected X X observed X X Read miss Ecache data error address X expected X X observed X X ol x lt Victimize error for address write invalidate failed for address X IO loopback read data error address X expected 5X 5X observed X X IO loopback read miss failed address X IO loopback read hit failed address X IO loopback write miss failed address X IO loopback write hit failed address X Test Descriptions 2 47 lll No Subtest 2 48 IO cache shared owner failed address X IOC check tags line dex X Xob X X TOC check data ex X ob X word d IO cache flush data error address X expected X X observed X X CPU read data address X expected X X observed X X Check RefMiss count xpected CRC X CMC X observed CRC X CMC X BW IOC Consistency ID 39 2 Level 17 e Attributes Test Module Test Co
9. Glossary A bus arbitration system determines which processor can control the system at any instant The arbitration system consists of circuits on the control board and the system boards Applications specific integrated circuits ASICs are integrated circuits which perform specialized tasks in the system If an ASIC BARB BBC BIC BW BX IOC or SBI fails the entire system board must be replaced The backplane subsystem consists of the control board and the card cage A bank of memory consists of eight SIMMs Each system board has space for two independent memory banks Board arbiter BARB ASICs are part of the bus arbitration system BARBs are located on the system boards See Arbitration System The BootBus Controller BBC ASIC is located on the control board The BBC works with BBC2 ASICs on system boards to control parts of the boot process BootBus Controller 2 BBC2 ASICs are located on system boards See BBC Glossary 1 BIC Every SPARCserver 1000 system board has four Bus Interface Chip BIC ASICs BICs connect the board to the backplane XDBuse Board The term board refers to the control board or to system boards The SPARCserver 1000 system has 1 control board and up to 4 system boards Board ID Board slot ID codes are hardwired on the card cage backplane A system board can be moved to any card cage slot without the need for jumper changes BootBus The BootBus connects the OpenBoot PROM set on a system
10. May 1993 No lll Subtest Lance memory compare address X expected xX observed X o9 X X o9 o9 Lance Registers error e JD 45 4 Level 17 e Attributes Test Module Lance RAP write read read test Testdata 0x1 0x2 0x4 0x4000 0x8000 Write halfword testdata to Lance RAP register Write halfword inverse testdata to word 0 in Lance buffered memory Read halfword testdata from Lance RAP register Compare and print error message if miscompare Testdata Oxffff Write halfword testdata to Lance RAP register Write halfword inverse testdata to word 0 in Lance buffered memory Read halfword testdata from Lance RAP register Compare and print error message if miscompare Lance CSRO STOP bit test Write 0 to RAP to point to CSRO register Testdata CSRO_STOP Write halfword testdata to Lance RDP register Write halfword inverse testdata to word 0 in Lance buffered memory Read halfword testdata from Lance RDP register Compare and print error message if miscompare Lance CSR1 register write write read test Write 1 to RAP to point to CSR1 register Testdata 0x1 0x2 0x4 0x4000 0x8000 Write halfword testdata to Lance RDP register Write halfword inverse testdata to word 0 in Lance buffered memory Read halfword testdata from Lance RDP register Compare and print error message if miscompare Testdata Oxffff Write halfword testdata to Lance RDP reg
11. Stress test using non cacheable stores e Make sure Store Buffer is off e Zero Store Buffer control and all tags e Clear the tags The Dptr and Fptr are set to 0 e Turn on Store Buffer e Issue 8 stores that should use each entry in the Store Buffer 0 7 e Turn off Store Buffer e Read the tags and data and verify SPARCserver 1000 POST User s Guide May 1993 2 Using EPROM address space float 1 through the address field of each tag e Issue the store e Read the tag and data e Float address bit and loop for all address bits Use a bus parity error to force a Store Buffer error and check the Store Buffer tags data and control for proper state e Establish the trap handler The first store will go to the Store Buffer The load will cause the Store Buffer to flush this store with odd parity The MXCC should complain about the bad parity The CPU should take a data store error trap e Check that the correct trap data store error occurs Dptr must point to the entry that incurred the data store error e Check the Store Buffer control and tags e Zero Store Buffer control and all tags Possible Error Messages Store Buffer tag error entry x expected X X observed X X Store Buffer data error entry x expected X X observed X X Store Buffer control error expected observed x lt A o X Data store error trap did not occur Test Descriptions 215 2 16 Subtest
12. e ID 91 0 Attributes General Purpose e Diagnosis XDBus0 Let each board align using system LEDs and run a backplane check The boards are staggered in time so that they will not interfere with each other Wait for Alt e ID 91 1 Level 1 e Attributes Error is Fatal Perform a synchronization function to insure both CPUs on this board are at a known state before continuing further Possible Error Messages This module does not check or report errors XDBus setup C_O e JD 91 1 Level 1 Attributes Error is Fatal Set up XDBus 0 configuration SPARCserver 1000 POST User s Guide May 1993 No lll Subtest O 0e 8008 Subtest Possible Error Messages This module does not check or report errors CO Backplane Check e ID 91 2 Level 1 e Attributes Test Module Each board has a pre assigned time to test its connection to the backplane Using JTAG take the BICs for the bus under test out of loopback Issue a series of reads and writes to the BW s DynaData register using several test patterns Using JTAG put the BICs back into loopback Possible Error Messages Read DDR at X caused Data Access Exception Data Compare Error address X expected X observed X CO Exit LB 0x5D ID 93 0 Attributes General Purpose e Diagnosis XDBus0 Let each board exit loopback so that it can now use the backplane Loopback Exit C_0O e ID 93 1 Level 1 e
13. e Initialize TLBs with unique tags and same ctx 0 e pag flush with different index3 and verify correct TLBs are invalidated after each flush Level4 entire e Initialize TLBs with unique tags and ctx e entire flush and verify all TLBs are invalidated This test needs to enable mmu demaps Possible Error Messages Wrong tlb after 10 flush Wrong tlb after 11 flush Wrong tlb after 12 flush Wrong tlb after 13 flush Wrong tlb after flush entire SPARCserver 1000 POST User s Guide May 1993 No lll Subtest Subtest MMU TLB Lock e ID 43 7 Level 17 e Attributes Test Module Error Terminates Sequencer Test the locking of TLB entries e Set lock bits for all entries except 1 e Initialize all TLBs with valid ptes otherwise they will be replaced e Initialize memory with unique 11 ptes e Do probe entire for all different index1 and verify the unlocked entry is used each time e Repeat for other 63 entries Possible Error Messages Wrong unlocked tlb entry MMU TLB Protection Error e ID 43 8 Level 17 Attributes Test Module Error Terminates Sequencer Test MMU protection access traps Map EPROM exit boot and do the following tests Invalid addr error test e Initialize invalid pte in memory Do access ld st user super data ld st user super instr e Verify that you got trap 0x9 and MMU sync error register is updated correctly in each case e Repeat for levell th
14. et Return OA gt BW Register Base E0000000 OA gt Comp Id 10D3907D OA gt DCSR 0001A000 0000DD00 OA gt DDR PRPEEEPRE PEPE REE OA gt CTL 00002000 OA gt ITBL OA gt 0000 OA gt 0000 OA gt 0000 OA gt 0000 OA gt 0000 OA gt 0000 OA gt 0000 OA gt 0000 dele SPARCserver 1000 POST User s Guide May 1993 OA gt Probing E0800000 OA gt BW Register Base E0800000 OA gt Comp Id 10D3907D OA gt DCSR 0001A000 8000DD00 OA gt DDR 00000000 00000000 OA gt CTL 00002020 OA gt ITBL OA gt 0000 OA gt 0000 OA gt 0000 OA gt 0000 OA gt 0000 OA gt 0000 OA gt 0000 OA gt 0000 OA gt Probing 01F00000 OA gt CC Register Base01F00000 OA gt StreamData OA gt Stream Data 0 01F00000 00000000 00000000 OA gt Stream Data 1 01F00008 00000000 00000000 OA gt Stream Data 2 01F00010 00000000 00000000 OA gt Stream Data 3 01F00018 00000000 00000000 OA gt Stream Data 4 01F00020 00000000 00000000 OA gt Stream Data 5 01F00028 00000000 00000000 OA gt Stream Data 6 01F00030 00000000 00000000 OA gt Stream Data 7 01F00038 00000000 00000000 OA gt StreamSrcAddr 01F00100 80000010 06000000 OA gt StreamDstAddr 01F00200 80000010 OEAABFCO OA gt RefMissCnt 01F00300 00000000 00000000 OA gt IntrptPend O1F00406 0 OA gt IntrptMask O1F00506 7FFE OA gt BIST O1F00804 23AA97E6 OA gt
15. or words to be emphasized Edit your login file Use 1s a to list all files system You have mail systems su Password To delete a file type rm filename Read Chapter 6 in User s Guide These are called class options You must be root to do this viii SPARCserver 1000 POST User s Guide May 1993 Related Manuals For more information on the SPARCserver 1000 system refer to the documents listed below Table P 2 Related Documentation Category Manual Title Part Number Installation Memory Module Installation Guide 801 2030 SPARCserver 1000 Installation Manual 800 2893 SPARCserver 1000 System Board Manual 800 2900 Diagnostics OpenBoot Command Reference 800 6076 Service SPARCserver 1000 Service Manual 801 2895 Safety Sun SPARCserver 1000 Cabinet and Data Center Expansion Cabinet 801 2892 Regulatory Compliance Manual Prefacee ix SPARCserver 1000 POST User s Guide May 1993 IiI Overview of POST The SPARCserver 1000 system s Power On Self Test POST software automatically tests the hardware resources of the system at power up or reset POST resides in the boot PROM programmable read only memory on each processor board in a SPARCserver 1000 system It runs as a stand alone diagnostic and multiprocessor control program 1 1 Features of POST The SPARCserver 1000 POST has a functionality far greater than any Sun system POST so far Based on test results a
16. Assumption Ecache is enabled No table walks are done in this test Make sure ASI 0x20 accesses are cacheable so that memory packets are generated instead of I O packets Possible Error Messages Wrong data on read with tlb hit Wrong data on read with tlb hit 2 54 SPARCserver 1000 POST User s Guide May 1993 No lll Subtest MMU Table Walk e ID 41 5 Level 17 e Attributes Test Module Error Terminates Sequencer Test MMU table walk operation Probe 10 test e Initialize memory with unique 10 ptps Do 10 probe using for the following cases ctpr 0x80000 0x40000 0x2000 0 ctx 0x8000 0x4000 1 Verify that you get expected 10 ptp Probe 11 test e Initialize memory with unique 11 ptes e Clear 10 ptp register e Do 11 probe with all different index1 and verify that you get correct 11 pte e Verify 10 ptp register gets updated Probe 12 test e Initialize memory with unique 12 ptes e Do l1 probe with all different index2 and verify that you get correct 12 pte Probe 13 test e Initialize memory with unique 13 ptes e Clear 12 ptp register e Do 13 probe with all different index3 and verify that you get correct 13 pte e Verify 12 ptp register gets updated Probe entire test e Initialize memory with unique 13 ptes e Do entire probe with all different index3 and verify that you get correct 13 pte e Verify ref bit is updated Test Descriptions 205 lll No Possible E
17. Control O1FOOA04 0000002C OA gt RC 0 DCB 0 WI 0 PF 1 MC 0 PE 1 CE 1 CS_HC 0 OA gt Status O1FO0BO0 0000000F FFFO0002 OA gt SXP 0 SM 0 NCSID 0 NCSPA FFFF00 NCSPC 0 SPC 0 BC 0 WP 0 RP 1 PP OA gt Reset 01F00C04 00000000 OA gt Error O1FOOEOO 00000000 00000000 OA gt ME 0 XP 0 CC 0 VP 0 AE 0 EV 0 CCOP 0 ERR 0 S 0 PA 0 00000000 OA gt CompId O1FO00F04 02000104 OA gt MID 2 MDEV 1 MREV 0 MVEND 4 0 Overview of POST 1 13 lll 0A gt Probing 09F00000 0A gt CC Register Base09F00000 OA gt CompId O9FOOFO4 00000104 0A gt MID 0 MDEV 1 MREV 0 MVEND 4 OA gt Probing E0100000 OA gt MQH Register Base E0100000 OA gt Comp ID 10D8607D OA gt DCSR 00048700 1000D000 OA gt DDR FPREFREFE FPRRREEERE OA gt GOADR 02400009 OA gt G1ADR 02000009 OA gt G2ADR 00000000 OA gt G3ADR 00000000 OA gt GOTYPE 08000800 08000800 OA gt G1TYPE 08000800 08000800 OA gt G2TYPE FREFREFE PRRFREEERE OA gt G3TYPE FEFFEPFEE EFEPEFEF OA gt CSR 00000000 00024101 OA gt CEADR 294C4000 00F90800 OA gt CEDR 00000000 00000000 OA gt UEADR 2940C000 00F90800 OA gt UEDR 00000000 00000000 OA gt ECCDCR 00000000 00000000 OA gt StreamData OA gt Stream Data 0 09F00000 00000000 00000000 OA gt Stream Data 1 09F00008 00000000 00000000 OA gt Stream
18. Memory data compare error 2 6 System Reconfiguration At this point POST performs the following tasks to boot the system Selects the System Master Configures and interleaves the memory Prints the system and memory display in verbose mode only Builds structures to pass to the OpenBoot firmware Copies the system IDPROM into NVRAM on each board Selects an MQH to do the demap replies Sets final LED values Scrubs the memory Initializes all CPUs and MXCCs for booting Finally POST completes execution by transferring control to the OpenBoot program Test Descriptions 2 111 lll No 2112 SPARCserver 1000 POST User s Guide May 1993 Sample POST Output This appendix shows the output that POST typically displays when it is run in diag mode on a SPARCserver 1000 system 1B gt BIST 1A gt BIST St 1B gt T Status 00000001 Signatures CPU 456E34F1 MXCC 1B gt mapl6 test atus 00000001 Signatures CPU 456E34F1 MXCC x x x SPARCserver_1000 MP POST Rev 7 1A gt mapl6 test 1B gt 1 1B gt 1A gt 1B gt 1A gt 1A gt 1A gt EPRO EPRO 1B gt LEDs 1B gt S Test EPROM path Test EPROM checksum Test EPROM path Test x x x SPARCserver_1000 MP POST Rev 7 EPROM checksum Test Ms Test Test WALK LED Test 1B gt Serial Ports Test 1B gt Port A Register Testj HESSEN 0123456789 lt gt
19. a all boards 0 OA gt DRAM NVRAM Size Speed Size Speed Manufacturer H 0 4Mbit 80ns 1Mbit 70ns E 1 16Mbit 100ns 4Mbit 85ns MS 2 64Mbit TI If NVSIMM NV 1 and B 1 if battery is good OA gt 0A gt SIMM Grp Data ECC Size Spd Mfg B NV SIMM Grp Data ECC Size Spd Mfg B NV OA gt H H 4 H OA gt 4100 3 31 16 3 2 4300 3 63 48 7 6 OA gt 3700 2 31 16 3 2 3900 2 63 48 7 6 OA gt 3300 1 31 16 3 2 0 0 2 0 0 3500 1 63 48 7 6 0 2 0 0 OA gt 2900 0 31 16 3 2 0 0 2 0 0 3100 0 63 48 7 6 0 2 0 0 OA gt 4000 3 15 00 1 0 4200 3 47 32 5 4 OA gt 3600 2 15 00 1 0 3800 2 47 32 5 4 OA gt 3200 1 15 00 1 0 0 0 2 0 0 3400 1 47 32 5 4 0 2 0 0 OA gt 2800 0 15 00 1 0 0 0 2 0 0 3000 O 47 32 5 4 0 2 0 0 OA gt Hit any key to continue OA gt 1 18 SPARCserver 1000 POST User s Guide May 1993 System Parameters OA gt Select one of the following functions OA gt o7 Set POST Level OA gt Paley Dump Device Table OA gt 2 Display System OA gt x3 Dump Board Registers OA gt 4a Dump Component IDs OA gt 5 Clear Error Logs OA gt 6 Display Simms OA gt 1g Scrub Main Memory 0a gt XE Return Command gt 7 0A gt Hit any key to continue OA gt System Parameters OA gt Select one of the following functions OA gt O7 Set POST Level OA gt ae Dump Devic
20. lll OOOO 0000 Subtest Subtest Keybd Mouse 0x0B e ID 11 0 e Attributes CO Useful Test e Diagnosis BootBus Test the BootBus Serial Communication Control keyboard and mouse ports Keyboard Loopback e ID 11 1 Level 8 Attributes Test Module Test the keyboard using loopback e Initialize the UART and enable loopback e Send characters 0x20 through 0x7f e Check RXRDY and verify that RXDATA TXDATA Possible Error Messages pa x local loopback error no txready pa X local loopback error no rxready pa X local loopback error exp 0x X obs 0x X Mouse Loopback e ID 11 2 Level 8 e Attributes Test Module Test the mouse using loopback e Initialize the UART and enable loopback e Send characters 0x20 through 0x7f e Check RXRDY and verify that RXDATA TXDATA Test Descriptions 2 7 2 8 OOOO 00 OOOO 0000 Subtest Possible Error Messages pa x local loopback error no txready pa X local loopback error no rxready pa X local loopback error exp 0x X obs 0x X NVRAM TOD 0x0C e ID 12 0 Attributes CO Useful Test e Diagnosis BootBus Test the BootBus NVRAM time of day clock function to insure that the clock is running Basic CPU 0x0D e ID 13 0 Attributes General Purpose Diagnosis CPUA Module CPUB Module Test the Basic CPU functions FPU Register JD 13 1 e Level 8 e Attributes Test Module Initialization Module Test float
21. CO XPT Test C_O BW IOC XPT Read Write Test C_0 BW MQH 1A gt CO BW MQH Consistency Test BW MQH Cache Consistency Test C_O BW IOC MQH SBus Loopback Test 1A gt CO IOC MQH Consistency Test Testing slot 0 on board 1 Testing slot 1 on board 1 Testing slot 2 on board 1 Testing slot 3 on board 1 IOC MQH Consistency Test 1A gt CO BW IOC Consistency Test 1A gt C_0 BW IOC MQH 1A gt Cache States Test 1A gt BW IOC Consistency Test 1A gt SPARC Module Board Master Test 1A gt C_0 BW MQH 1A gt CPU and Cache Test 1A gt U PTP Cache Invalidation Test 1A gt U Stuff TLB Hit Test 1A gt U Table Walk Test 1A gt U Flush Test 1A gt MMU TLB Lock Test 1A gt MMU TLB Protection Error Test 1A gt MMU Table Walk With Parity Error Test 1A gt MMU Table Walk With ECC Error Test 1B gt SPARC Module Board Slave Test 1B gt Read MOH State 1B gt C_0 BW MQH 1B gt CPU and Cache Test 1B gt U PTP Cache Invalidation Test 1B gt U Stuff TLB Hit Test 1B gt U Table Walk Test 1B gt U Flush Test 1B gt MMU TLB Lock Test 1B gt MMU TLB Protection Error Test 1B gt MMU Table Walk With Parity Error Test 1B gt MMU Table Walk With ECC Error Test 1A gt OnBoard IO Verification Test 1A gt C_0 BW IOC MQH 1A gt Check OnBoardIO Card0 Test 1A gt Lance Memory Test A 4 SPARCserver 1000 POST User s Guide May 1993 1A gt Lance R
22. Every system board has 10 LEDs on the back panel Two green LEDs top positions indicate the presence of one or two SPARC processor modules or none The remaining eight yellow LEDs lower positions are activated by software commands to the system s status registers and no particular meanings have been assigned to these 8 LEDs In normal operation the eight lower LEDs on the system master board will constantly turn on and off in a cyclical pattern while corresponding LEDs on the remaining system boards will be off The Memory Queue Handler MQH ASIC on the system board provides the interface between the system board SIMMs and the backplane buses The Module XBus Cache Controller MXCC ASIC is located on the SPARC module and controls the flow of data to and from the XDBus Non volatile random access memory The non volatile SIMM NVSIMM is a battery backed SIMM Battery current is shared in a group of NVSIMMs in the event that a single battery fails This is one of four positions of the front panel key switch When the key is in this position turning on AC power at the main AC breaker on the back of the server cabinet or pressing the reset switch on the inside of the front panel causes POST diagnostics to run followed by booting of the system This switch is located behind the front panel The SBus Interface SBI ASIC converts signals between the SBus and the higher speed XDBus There is one SBI on each system board SB
23. TLB Lock e ID 41 7 Level 17 Attributes Test Module Error Terminates Sequencer The the locking of TLB entries e Set lock bits for all entries except 1 e Initialize all TLBs with valid ptes otherwise they will be replaced e Initialize memory with unique 11 ptes e Do probe entire for all different index and verify the unlocked entry is used each time e Repeat for other 63 entries Possible Error Messages Wrong unlocked tlb entry Test Descriptions 2 07 lll No Subtest MMU TLB Protection Error e ID 41 8 Level 17 Attributes Test Module Error Terminates Sequencer Test MMU protection access traps Map EPROM exit boot and do the following tests Invalid addr error test Initialize invalid pte in memory e Do access ld st user super data ld st user super instr e Verify that you got trap 0x9 and that the MMU sync error register is updated correctly in each case e Repeat for levell through level3 ptes Protect error test e Initialize pte in memory with acc 2 0 0 through 7 e Do access ld st user super data ld st user super instr e If there is an access error verify that you got trap 0x9 and that the MMU sync error register is updated correctly If there is no access error verify that the MMU error register is not updated e Repeat for levell through level3 ptes Possible Error Messages No trap on illegal permissions access Wrong mmu fsr on twalk protect error Wron
24. all access sizes allowed The addresses of the BW registers are in CSR space and Local space the test uses both address spaces If any access causes a data access exception or unexpected interrupt the test aborts with a FAIL status Possible Error Messages While testing s register an unexpected trap occurred MFSR X MFAR Trap Type 2x CC Error X X Test Descriptions 2 21 2 22 Subtest Unexpected Component ID value o9 o9 address X expected X or X observed X register failed to return correct data address X expected observed X oA o x lt register failed to return correct data expected X X observed X o9 oA o o9 x lt Floating a bit through s register failed o9 expected X observed o9 x lt Floating a bit through s register failed Xa Xa X X expected observed oO o oO ol Timers and Interrupts ID 18 3 Level 8 Attributes Test Module Initialization Module Test timer in free running mode no interrupts e Make sure the prescaler is initialized for 1 microsecond e Configure Ptimer for non UT mode e First do the Ptimer then do the Ttimer e Clear all interrupt registers e Set timer to run free Stall for a few milliseconds e Make sure the counter did some counting Check the interrupt table should be 0 SPARCserver 1000 POST User s Guide May 1993 No lll Test both P and T timer in li
25. because its subtest Timers and Interrupts has failed The test ID is 38 3 and the LED pattern for the test is 0x26 2A gt TEST FAILED BWO Regs Timers and Interrupts ID 38 3 LED 0x26 2A gt Timer Error expected the Limit Bit to be set Address FFF02010 Data 00237800 The example below shows the failing test and subtest CO SBI and SBI Registers The test ID is 56 1 and the LED pattern for this test is 0x36 OA gt TEST FAILED CO SBI SBI Registers ID 56 1 LED 0x38 OA gt While testing Component ID register an unexpected trap occurred MFSR 00000936 MFAR 02800000 Trap Type 9 CC Error 00000000 F01E1D58 Overview of POST 15 lll 1 3 User Interface Commands In diag mode you can interact with POST in a limited way using the commands shown in Table 1 2 Table 1 2 User Interface Key Commands Key a Action Toggle Pause CPU A flag Press this key to stall selftest on CPU A Press any key to resume selftest Affects both CPUs POST freezes on current system board other system boards continue Toggle Pause CPU B flag Press this key to stall selftest on CPU B Press any key to resume selftest Affects both CPUs POST freezes on current system board other system boards continue Toggle Trace Test Case flag Set this flag to allow subtests to display trace messages on the console This is helpful for debugging or t
26. board to the SPARC processor modules on that same board BW The system board has two Bus Watcher BW ASICs two for each processor to convert XDBus signals to higher speed processor module bus signals C0 C1 and C2 Configurations Note The SPARCserver 1000 has only one XDBus system bus so CO is the only possible configuration that applies However this version of POST was also also designed to operate on the SPARCcenter 2000 which permits the C1 and C2 configurations In the CO configuration POST configures the system to operate with XDBus0 operational and XDBus1 disabled All devices connected to XDBus1 are disabled so that they cannot interact with or affect the operation of the enabled devices on XDBus0 In the C1 configuration POST configures the system to operate with XDBus1 operational and XDBus0 disabled All devices connected to XDBus0 are disabled so that they cannot interact with or affect the operation of the enabled devices on XDBus1 In C2 configuration POST configures the system to operate with both XDBus0 and XDBus 1 enabled All devices connected to both these buses are enabled and functional Cache Memory caches are located near various buses on the system board Glossary 2 SPARCserver 1000 POST User s Guide May 1993 CARB Card Cage Card Slot Clock Generation Control Board IOC Key Switch LED Indicators One Central Arbiter CARB ASICs on the control board are part of the m
27. check or report errors CO IOC 0x20 e ID 32 0 Attributes General Purpose e Diagnosis IOCO Set Configuration 0 and test the IOC C_0 BW IOC e ID 32 1 Level 1 Attributes Error Terminates Sequencer Error is Fatal Establish the board configuration for this test Possible Error Messages This module does not check or report errors SPARCserver 1000 POST User s Guide May 1993 No lll Subtest IOC Registers e ID 32 2 Level 8 Attributes Test Module Error Terminates Sequencer Test the read and write accessibility of all IOC ASIC registers using all access sizes allowed The addresses of the IOC registers are in CSR space If any access causes a data access exception or unexpected interrupt the test aborts with a FAIL status Possible Error Messages While testing s register an unexpected trap occurred MFSR X MFAR X Trap Type 2x CC Error X X Unexpected Component ID value address X expected X or X observed SX 6s register failed to return correct data address X expected SX observed X 6s register failed to return correct data expected X X observed X X Floating a bit through s register failed expected observed oA o X X Floating a bit through s register failed expected X X observed X X Test Descriptions 2 29 Subtest Subtest Subtest IOC XDBus Tags e ID 32 3 Level 8 e Attri
28. data X X store address X data X X Block check error address X expected X observed X Stream ready bit timed out Test Descriptions 2 43 2 44 Check tags failed cctag X SX exp state x bwtag X exp state x Check Dcache tags failed address X expected valid bit x observed valid x DCache tag has inconsistent state ptag X X Read hit Ecache data error addr X expected SX SX observed X X Read miss Ecache data error address X expected SX SX observed X X Victimize error for address X Write invalidate failed for address X IO loopback read data error address X expected SX SX observed X X IO loopback read miss failed address X IO loopback read hit failed address X IO loopback write miss failed address X IO loopback write hit failed address X IO cache shared owner failed address X IOC check tags line dex X Xob SX X IOC check data ex SX ob X word d SPARCserver 1000 POST User s Guide May 1993 No lll O0e O O0ee e Subtest IO cache flush data error address X expected X X observed X X CPU read data address X expected X X observed X X Check RefMiss count xpected CRC X CMC X observed CRC X CMC X CO BW IOC Consistency 0x27 e ID 39 0 Attributes General Purpose e Diagnosis IOCO Set Configuration 0 and test consistency betw
29. g2 g3 1A gt 1A gt 1 dh J 1 1 1 1A gt Sample POST Output A 6 SPARCserver 1000 POST User s Guide May 1993 POST Design Concepts B This appendix describes some principles on which the SPARCcenter 2000 and SPARCserver 1000 POST is designed These two systems use the same POST and the information in this appendix applies to both systems B 1 Tests and Subtests POST is a collection of diagnostics or Tests that examine system hardware and ensure that the system can boot successfully Tests perform the following types of tasks initializing and checking the hardware acquiring resources needed during testing and reconfiguring the hardware Usually each group of related components in a system has a test associated with it Each test can contain an ordered list of SubTests these subtests perform the individual tasks needed by the test Once a test is selected to run all the subtests associated with it execute unconditionally and in the specified order unless errors cause the test to be aborted A subtest can be called by several tests A test fails if any of its subtests fails and passes only if all of its subtests pass B 1 1 TestIDs and SubtestIDs A TestID uniquely identifies each test Similarly within a test a SubTestID uniquely identifies a subtest The TestID and SubTestID together uniquely identify a given subtest from all other subtests in POST B 1 B 1 2 TestLi
30. not tested To prevent losing refresh the Refresh Enable bit in the MCSR is never reset When it is appropriate the test restores the original value it found in the register Possible Error Messages While testing s register an unexpected trap occurred MFSR X MFAR X Trap Type 2x CC Error X X Unexpected Component ID value address X expected X or X observed X s register failed to return correct data address X expected X observed X SPARCserver 1000 POST User s Guide May 1993 No lll Subtest Subtest 6s register failed to return correct data expected observed Floating a bit through s register failed expected observed X ll o9 x lt Floating a bit through s register failed expected X X observed X X ae ol MOH Initialization e ID 119 4 Level 1 Attributes Error Terminates Sequencer Error is Fatal Set up the MOH timing registers and control register Timing values loaded depend on the types of SIMMs present Turn on Refresh Enable set Refresh Count Request Delay Possible Error Messages This module does not check or report errors Enable ECC e ID 119 5 Level 1 e Attributes Error is Fatal Enable ECC checking on the MQH Possible Error Messages This module does not check or report errors Test Descriptions 2 87 lll No Subtest Memory e ID 119 6 Level 8 e Attributes Test Module
31. of POST 1 23 lll Error Log Analysis for Board 1 OA gt BWO CPU A OA gt XDBus Parity Error XDBus Data 00000000 00002000 XDBus Parity OA gt MOQHO OA gt Multiple Errors ti 0A gt XDBus Parity Error XDBus Data 00000000 00002000 XDBus Parity OA gt IOCO OA gt Multiple Errors OA gt XDBus Parity Error XDBus Data OA gt XDBus 0 on BACKPLANE caused parity error OA gt History log bit 13 shows failed BICs BIC 0 Byte 1 OA gt Log Date Mar 17 0 16 12 GMT 1993 OA gt CPU A Function at time of error System Level Software OA gt SSSS Error Log Analysis for Non Processor Board 2 OA gt Parity error on XDBus 0 caused by BACKPLANE OA gt Parity error detected by BIC 2 byte 1 OA gt Log Date Mar 17 0 14 53 GMT 1993 OA gt 00000000 00002000 XDBus Parity System Memory Failure Analysis OA gt No Bad groups found OA gt Hit any key to continue OA gt DEMON OA gt Select one of the following functions OA gt NO System Parameters OA gt vie Read Write device OA gt v2 Software Reset OA gt Be NVRAM Management OA gt 4a Error Reporting OA gt ot Analyze Error Logs OA gt M6 Power Off at Main Breaker OA gt Sy NVRAM SIMM tests OA gt ie Return to selftest OA gt Command gt 7 OA gt 00 00 00 1 24 SPARCserver 1000 POST User s Guide May 1993 NVRAM SIMM Tests OA gt Select one of
32. option does not have a menu When you type 6 at the main menu prompt POST trips the main breaker this is for manufacturing tests only NVRAM SIMM Tests Option Type 7 at the main menu prompt to get to the NVRAM SIMM tests sub menu This option is provided for users to test the NVRAM SIMMs The operating system uses NVRAM SIMMs to store data POST never writes to NVRAM SIMMs it only checks the batteries Note Never run these tests on a system that is operational since vital operating system data might be erased Return To Selftest Option Type r to leave the DEMON menus You are taken back to the point where you interrupted POST execution when you called the DEMON and the test execution continues SPARCserver 1000 POST User s Guide May 1993 The following screens are an example of how you can use various options in the DEMON menus The example begins with the selection of option 0 System Parameters from the DEMON main menu OA gt DEMON OA gt Select one of the following functions OA gt 0 System Parameters OA gt Mae Read Write device OA gt x2r Software Reset OA gt sid NVRAM Management OA gt 4a Error Reporting OA gt Boks Analyze Error Logs OA gt 6 Power Off at Main Breaker OA gt ie NVRAM SIMM tests OA gt Mal Return to selftest OA gt Command gt 0 OA gt System Parameters OA gt Select one of the following functions OA gt g Set POST Le
33. the following functions OA gt 0 Read Write 6N Test OA gt vare Write Test no verify OA gt 2 Read Test verify single pattern OA gt Niel Return to Main menu OA gt Command gt 0 OA gt NVRAM 6N Read Write Test OA gt Couldn t find any NVRAM OA gt Hit any key to continue OA gt NVRAM SIMM Tests OA gt Select one of the following functions OA gt OF Read Write 6N Test OA gt St Write Test no verify OA gt y2 Read Test verify single pattern 0a gt Sach Return to Main menu OA gt Command gt r OA gt DEMON OA gt Select one of the following functions OA gt NO System Parameters OA gt vie Read Write device OA gt v2 Software Reset OA gt Be NVRAM Management OA gt 4a Error Reporting OA gt ot Analyze Error Logs OA gt M6 Power Off at Main Breaker OA gt Sy NVRAM SIMM tests OA gt ie Return to selftest OA gt Command gt r OA gt Overview of POST 1 25 1 26 SPARCserver 1000 POST User s Guide May 1993 No lil Test Descriptions This chapter contains the descriptions for the tests that make up the POST software Note This chapter lists the tests in the order in which they are executed when POST is invoked The general format for each test description is as follows Each test has an LED pattern shown as a set of eight lights associated with it The hexadecimal value of this LED pattern is also sh
34. useful to me Strongly Strongly Not Agree Agree Disagree Disagree Applicable C u C u C Comments Do you have additional comments about the SPARCserver 1000 POST User s Guide Name Title Company Address NECESSARY IF MAILED IN THE NO POSTAGE UNITED STATES BUSINESS REPLY MAIL FIRST CLASS MAIL PERMIT NO 1 MOUNTAIN VIEW CA POSTAGE WILL BE PAID BY ADDRESSEE SY ay RN E SUN MICROSYSTEMS INC Attn SMCC Technical Publications MS MTV15 42 2550 Garcia Avenue Mt View CA 94043
35. 0 00000000 OA gt 00000000 00000000 OA gt 00000000 00000000 OA gt Probing E0200000 OA gt IOC Register Base E0200000 OA gt Comp ID 1OADDO7D OA gt DCSR 0001A000 2000DD00 OA gt DDR FREFFFFPRFE FFFPFFFE OA gt CTL 0001E060 OA gt DBUS Tags SBUS Tags State Bits OA gt 00000000 00000000 00000000 OA gt 00000000 00000000 00000000 OA gt 00000000 00000000 00000000 OA gt 00000000 00000000 00000000 Overview of POST 1 15 lll 0A gt Probing 02800000 OA gt SBI Register Bas OA gt Comp ID OA gt CTL OA gt SR OA gt SOCR OA gt SICR OA gt S2CR OA gt S3CR OA gt SOSBCR OA gt S1SBCR OA gt S2SBCR OA gt S3SBCR OA gt ISR OA gt ITIDR OA gt System Parameters OA gt a0 OA gt Salt OA gt 2a OA gt x37 0a gt XAT 0a gt vg OA gt 6 OA gt IY 0a gt PE Command gt 4 e 0280 OO OGO G GO OTO Oa 1 w 00 OA gt Hit any key to continue Set PO Dump D Displa Dump B Dump C Clear Displa Scrub Return eo C O 16 o oS SS OOOO O O O G O fo 0000 ADEO7D 020000 00000 00021 00021 00021 00021 00000 00000 00000 00000 00000 00000 oO gt Sao O OA gt Select one of the following functions ST Level evice Table y System oard Registers omponent IDs Error Logs y Simms ain Memory 1 16 SPARCserver 1000 POST User s Guide May 1993 OA gt OA gt OA gt OA gt OA g
36. 00 Subtest Subtest Possible Error Messages Data Compare Error address X expected X observed X CO NPB SBI Ox7A e JD 122 0 e Attributes NonProcessor Board Test Diagnosis SBI Test the SBI on the non processor board SBI Initialization ID 122 1 Level 1 e Attributes Error Terminates Sequencer Error is Fatal Initialize all SBI registers to the default values Possible Error Messages This module does not check or report errors SBI Registers e ID 122 2 Level 8 Attributes Test Module Error Terminates Sequencer Test the read and write accessibility of all SBI ASIC registers using all access sizes allowed The addresses of the SBI registers are in ECSR space If any access causes a data access exception or unexpected interrupt the test aborts with a FAIL status The SBI Interrupt registers with the exception of the Interrupt Target ID are not tested here but are tested in the SBus Interrupts test Test Descriptions 2 93 2 94 Subtest Possible Error Messages While testing s register an unexpected trap occurred MFSR X MFAR X Trap Type 2x CC Error X X Unexpected Component ID value address X expected X or X observed X 6s register failed to return correct data address X expected SX observed X s register failed to return correct data expected X X observed X X Floating a bit through s register f
37. 6 Subtest FAS236 Registers e ID 126 7 Level 17 e Attributes Test Module FAS configuration register 1 write write read test For testdata 0x1 0x2 0x4 0x40 0x80 Write byte testdata to FAS configuration register 1 Write byte inverse testdata to byte 0 in Lance buffered memory Read byte testdata from FAS configuration register 1 Compare and print error message if miscompare testdata Oxff Write byte testdata to FAS configuration register 1 Write byte inverse testdata to byte 0 in Lance buffered memory Read byte testdata from FAS configuration register 1 Compare and print error message if miscompare FAS configuration register 2 write write read test For testdata 0x1 0x2 0x4 0x40 0x80 Write byte testdata to FAS configuration register 2 Write byte inverse testdata to byte 0 in Lance buffered memory Read byte testdata from FAS configuration register 2 Compare and print error message if miscompare testdata Oxff Write byte testdata to FAS configuration register 2 Write byte inverse testdata to byte 0 in Lance buffered memory Read byte testdata from FAS configuration register 2 Compare and print error message if miscompare FAS configuration register 3 write write read test For testdata 0x1 0x2 0x4 0x40 0x80 Write byte testdata to FAS configuration register 3 Write byte inverse testdata to byte 0 in Lance buffered memory Read byte testdata from
38. ABCDEFGHIJKLMNOPORSTUVWXYZ _ 1A gt Serial Ports Test 1B gt Serial Port B Loopback Testj 23AA97 Fi oO 23AA97 fl oD abcdefghijklmnopqrstuvwxyz A 1A gt Port A Register Test LESSE 0123456789 lt gt ABCDEFGHIJKLMNOPORSTUVWXYZ _ abcdefghijklmnopaqrstuvwxyz 1B gt Mouse Loopback Test 1A gt Serial Port B Loopback TestJ 1B gt NVRAM TOD Test 1A gt Keybd Mouse Test 1B gt Basic CPU Test 1A gt Keyboard Loopback Test 1B gt FPU Register Test 1A gt ouse Loopback Test 1B gt FPU Functional Test 1A gt NVRAM TOD Test 1A gt Basic CPU Test 1B gt MMU TLB Test 1A gt FPU Register Test 1B gt Instruction Cache Tags Test 1A gt FPU Functional Test 1A gt MMU TLB Test 1A gt Instruction Cache Tags Test 1B gt Instruction Cache Ram Test 1A gt Instruction Cache Ram Test 1B gt Data Cache Tags Test 1A gt Data Cache Tags Test 1B gt Data Cache Ram Test 1A gt Data Cache Ram Test 1B gt Store Buffer Tags Test 1B gt Store Buffer RAM Test 1B gt Store Buffer Functional Test 1A gt Store Buffer Tags Test 1B gt MXCC Registers Test 1A gt Store Buffer RAM Test 1A gt Store Buffer Functional Test 1A gt XCC Registers Test 1B gt Init MXCC Regs 1B gt Ecache Test 1B gt Setting Cache Size 1B gt Ecache Tags Test 1A gt Init MXCC Regs 1A gt Ecache Test 1A gt Setting Cache S
39. Attributes Test Module Using JTAG take the BICs out of loopback From this point on the BICs should not be in loopback Test Descriptions eno Possible Error Messages This module does not check or report errors 2 4 System Master Selection POST chooses a System Master from one of the Board Masters in the system The CPU that becomes the System Master is the CPU with a functional BootBus on the lowest numbered board After the System Master is selected all other CPUs become slaves and wait for assignments from the System Master The System Master tests non processor boards then performs final system configuration as described in the following sections 2 5 System Level Testing 2 84 O 0880 Subtest The Following series of tests run after Dyanbus Loopback Exit All System Board Components may now interact with each other This interactivity is exercised and checked for correct results CO NPB Loopback Exit 0x76 ID 118 0 e Attributes NonProcessor Board Test e Diagnosis XDBus0 Take this non processor board out of loopback Loopback Exit e ID 118 1 Level 1 e Attributes Test Module Using JTAG take the BICs out of loopback From this point on the BICs should not be in loopback Possible Error Messages This module does not check or report errors SPARCserver 1000 POST User s Guide May 1993 No lll Subtest O00 0eee Subtest Subtest Marking NPB e ID 118 2 Le
40. BootBus Test the BootBus Serial Communication Control serial ports Port A Register e ID 9 1 Level 17 e Attributes Test Module Perform a Walking 1s test on the UART SCC Z85C30 write read register 12 Possible Error Messages Data Compare Error address X expected X observed X Port B Register e ID 9 1 Level 17 e Attributes Test Module Perform a Walking 1s test on the UART SCC Z85C30 write read register 12 Possible Error Messages Data Compare Error address X expected X observed X Test Descriptions 2 5 2 6 Subtest Subtest Serial Port A Loopback e ID 9 2 Level 17 e Attributes Test Module Test Serial Port A using loopback e Initialize the UART and enable loopback e Send characters 0x20 through 0x7f e Check RXRDY and verify that RXDATA TXDATA Possible Error Messages pa x local loopback error no txready pa X local loopback error no rxready pa X local loopback error exp 0x X obs 0x X Serial Port B Loopback ID 9 3 Level 17 e Attributes Test Module Test Serial Port B using loopback e Initialize the UART and enable loopback e Send characters 0x20 through 0x7f e Check RXRDY and verify that RXDATA TXDATA Possible Error Messages pa x local loopback error no txready pa X local loopback error no rxready pa X local loopback error exp 0x X obs 0x X SPARCserver 1000 POST User s Guide May 1993 No
41. D 18 1 Level 8 e Attributes Test Module Initialization Module Test the Bus Watcher Tag RAMs with a 6N algorithm The test is meant to be called by the POST sequencer The code is meant to be run in diag mode only The test is executed from the CPU s Icache e Determine BW tag size and mode configured e Execute the 6N test on the tags e First pass write in ascending order e Second pass read then write in ascending order e Third pass read compare in descending order e Loop for all patterns Possible Error Messages Data Compare Error address X expected X observed X 2 24 SPARCserver 1000 POST User s Guide May 1993 No lll OOO0O 0000 Subtest Subtest CO M H Ox1E ID 30 0 Attributes General Purpose Diagnosis MQHO Set Configuration 0 and test the MQH C_O BW MQH e ID 30 1 Level 1 Attributes Error Terminates Sequencer Error is Fatal Establish the board configuration for this test Possible Error Messages This module does not check or report errors MQH Registers e ID 30 2 e Level 8 e Attributes Test Module Error Terminates Sequencer Test the read and write accessibility of the MQH ASIC registers using all access sizes allowed The addresses of the MQH registers are in CSR space If any access causes a data access exception or unexpected interrupt the test aborts with a FATL status The ECC Error registers are read only Testi
42. D are not tested here but are tested in the SBus Interrupts test Test Descriptions 23l 2 32 Subtest Possible Error Messages While testing s register an unexpected trap occurred MFSR X MFAR X Trap Type 2x CC Error X X Unexpected Component ID value address X expected X or X observed X 6s register failed to return correct data address X expected SX observed X s register failed to return correct data expected X X observed X X Floating a bit through s register failed expected observed oA le X X Floating a bit through s register failed expected X X observed X X s fields SEGA C S updated when WSA 0 expected observed SBI Initialization e ID 33 3 Level 1 Attributes Error Terminates Sequencer Error is Fatal Initialize all SBI registers to the default values SPARCserver 1000 POST User s Guide May 1993 No lll Subtest Possible Error Messages This module does not check or report errors SBus Interrupts ID 33 4 Level 8 e Attributes Test Module Test all levels of SBus interrupts for all SBus slots Verify that the correct interrupt state is recorded in the BW MXCC and SBI ASICs Insure that the correct SPARC interrrupt level is delivered to the CPU This test is executed on each board by the CPU on that board The system uses this test for SBus slots on non processor boards Mask a
43. DING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT THIS PUBLICATION COULD INCLUDE TECHNICAL INACCURACIES OR TYPOC vagen ERRORS THANGES ARE PERIODICALLY ADDED TO THE INFORMATION HEREI sH S BE INCORPOK N EDITIONS OF THE PUBLICATION SUN MICROSYSTEMS INC M OVE ENIS AND OR CHANGES IN THE PRODUCT S AND OR THE PROGRAM S DESCRIBED IN THIS PUBLICATION AT ANY TIME Contents Preface othe ee cease cee Pe ee oe eee nae eee ees Vii 1 Overview Of POST sscicccadnacetdevennntaciesddewiwces 1 1 1 1 Feat resof POST pic 0 5608 ghd einer ini kaa EREE 1 1 1 2 Invoking POST ree iaa a aeai E a 1 2 1 2 1 System and Board LEDS wc cveee ese ensyeves ves 1 3 1 2 2 ae Oi ot ee 1 4 1 3 User Interface Commands 4 3240 suunas 1 6 14 DEMON Menu Options 0 00 ereee cee w ewe sew neues 1 8 2 Test DescriptlOns 1 lt lt 415soe0 ke Cede we SOREN Enkie Hees 2 1 2L Early POST Tests nccsny menn E nain EEEE 2 2 2 2 Board Level Testing s20n che aleve nu Reertevenndeny 2 3 23 Loopback EMG ecient bihide e e e E 2 81 24 System Master Selection ui0cciis ek eecewcceu ee ien 2 84 2 5 System Level Testing 2103555455 0beseununeudinweien 2 84 2 6 System Reconfiguration bes sss sssr resser 2 111 iii A Sample POST Ontput 22601 siciiweriaivesasarend iaudu A 1 B POST Design Concepts ix cd5 iavese che siseevaweaois oa aes B 1 B 1 Tests and Subtests 2 0 e
44. Data 2 09F00010 00000000 00000000 OA gt Stream Data 3 09F00018 00000000 00000000 OA gt Stream Data 4 09F00020 00000000 00000000 OA gt Stream Data 5 09F00028 00000000 00000000 OA gt Stream Data 6 09F00030 00000000 00000000 OA gt Stream Data 7 09F00038 00000000 00000000 OA gt StreamSrcAddr 09F00100 80000000 00000000 OA gt StreamDstAddr 09F00200 80000010 1D555FC0 OA gt RefMissCnt 09F00300 00000000 00000000 OA gt IntrptPend O9F00406 0 OA gt IntrptMask 09F00506 FFFE OA gt BIST 09F00804 23AA97E6 OA gt Control O9FOOA04 0000002C OA gt RC 0 DCB 0 WI 0 PF 1 MC 0 PE 1 CE 1 CS_HC 0 OA gt Status O9FOOBOO 0000000F FFF00000 OA gt SXP 0 SM 0 NCSID 0 NCSPA FFFF00 NCSPC 0 SPC 0 BC 0 WP 0 RP 0 PP OA gt Reset 09F00C04 00000000 OA gt Error O9FOOEOO 00000000 00000000 OA gt ME 0 XP 0 CC 0 VP 0 AE 0 EV 0 CCOP 0 ERR 0 S 0 PA 0 00000000 0 1 14 SPARCserver 1000 POST User s Guide May 1993 OA gt Timing Registers OA gt 00000000 00000141 OA gt 00000000 00000021 OA gt 00000000 0000022D OA gt 00000000 000004AF OA gt 00000000 00000147 OA gt 00000000 00000117 OA gt 00000000 0000021B OA gt 00000000 0000008A OA gt 00000000 00000002 OA gt 00000000 00000012 OA gt 00000000 00000090 OA gt 00000000 00000040 OA gt 00000000 00000000 OA gt 00000000 00000000 OA gt 00000000 00000000 OA gt 00000000 00000000 OA gt 00000000 00000000 OA gt 0000000
45. Exit O00 Board N 1 Board Level Testing POST Design Concepts System Masters Selection System Level Testing ReConfig __ To OpenBoot B 3 B 4 Board Level Testing On reset the hardware automatically puts each board in loopback mode and the processors on the board coordinate to do board level testing before exiting loopback During this testing phase each board in the system is logically and electrically isolated from other boards This prevents failures on one board from corrupting other boards A processor that fails during this phase becomes inactive The types of tests executed during this phase include BootBus tests CPU module cache controller external RAM and Bus Watcher tests as well as tests that ensure the functionality of non processor components on the board Loopback Exit During loopback exit each processor verifies its connection to the backplane Processors that pass this test synchronize and enable their boards on to the backplane processors that fail remain inactive The purpose of this phase is to get working boards out of loopback so that they can be tested together System Master Selection In this phase the processors collectively elect system masters for each of the three configurations C0 only XDBus0 enabled e C1 only XDBbus1 enabled e C2 both buses enabled These system masters are called COSM C1SM and C2SM respectively Note The SPARCs
46. FAS configuration register 3 Compare and print error message if miscompare testdata Oxff Write byte testdata to FAS configuration register 3 Write byte inverse testdata to byte 0 in Lance buffered memory Read byte testdata from FAS configuration register 3 Compare and print error message if miscompare SPARCserver 1000 POST User s Guide May 1993 2 FAS configuration register 1 2 back to back write write read read test e For testdata 0x1 0x2 0x4 0x40 0x80 e Write byte inverse testdata to FAS configuration register 1 e Write byte testdata to FAS configuration register 2 e Write byte inverse testdata to byte 0 in Lance buffered memory e Read byte inverse testdata from FAS configuration register 1 e Read byte testdata from FAS configuration register 2 e Compare and print error message if miscompare e testdata Oxff e Write byte inverse testdata to FAS configuration register 1 e Write byte testdata to FAS configuration register 2 e Write byte inverse testdata to byte 0 in Lance buffered memory e Read byte inverse testdata from FAS configuration register 1 e Read byte testdata from FAS configuration register 2 e Compare and print error message if miscompare Possible Error Messages char fas_xfr_low_txt J Transfer count low register compare error char fas_xfr_hi_txt J Transfer count high register compare error char fas_configl_txt Config register 1 compare error char fas_
47. P register Compare and print error message if miscompare Testdata Oxffff Write halfword testdata to Lance RDP register Write halfword inverse testdata to word 0 in Lance buffered memory Read halfword testdata from Lance RDP register Compare and print error message if miscompare Lance CSR3 register write write read test Write 3 to RAP to point to CSR3 register Testdata 0x1 0x2 0x4 0x4000 0x8000 Write halfword testdata to Lance RDP register Write halfword inverse testdata to word 0 in Lance buffered memory Read halfword testdata from Lance RDP register Compare and print error message if miscompare Testdata Oxffff Write halfword testdata to Lance RDP register Write halfword inverse testdata to word 0 in Lance buffered memory Read halfword testdata from Lance RDP register Compare and print error message if miscompare Test Descriptions 2 101 lll No Possible Error Messages SS address X expected 4X observed 4X char lance_rap_wr_rd_txt RAP write write read miscompare char lance_csr0_not_cleared_txt CSRO register not cleared when STOP bit set char lance_csrl_stop_txt CSR1 write write read miscompare when CSRO STOP bit set char lance_csr2_stop_txt CSR2 write write read miscompare when CSRO STOP bit set char lance_csr3_stop_txt CSR3 write write read miscompare when CSRO STOP bit set char lance_rdp_rap_wr_rd_b2b_txt J RDP RAP back to back writ
48. Processor Board Test Diagnosis IOCO SBI Test the JTAG IO ring on non processor boards This test is run by the C_0 system master Verify IO Ring e ID 120 2 Level 1 e Attributes Test Module Scan in the ring containing the IOC and SBI ASICs verify that the JTAG data is correct Possible Error Messages JTAG TAP state machine not responding Incorrect arguments passed by caller JTAG component ID does not match JTAG ring continuity test failed State after initialization not expected Ring length does not match expected Test Descriptions 2 89 O 8008 Subtest Subtest CO NPB IO 0x79 e ID 121 0 e Attributes NonProcessor Board Test Diagnosis IOCO Test IOCOs on non processor boards This test is run by the C_0 system master Check BDA ID 121 1 Level 1 Attributes Error Terminates Sequencer Error is Fatal Insure that the part to be tested next has not already failed eariler in POST Possible Error Messages This module does not check or report errors C_0 NPB IOC e ID 121 2 e Level 1 Attributes Error Terminates Sequencer Error is Fatal Establish the board configuration for this test Possible Error Messages This module does not check or report errors SPARCserver 1000 POST User s Guide May 1993 No lll Subtest IOC Registers e ID 121 3 Level 8 Attributes Test Module Error Terminates Sequencer Test the read and write accessibi
49. RO Flush the SBI Write Buffers Now send the DRAIN command to the ESC Check that the ACTIVEO and ACTIVE bits in SCSI DVMA Control register are cleared indicating the data transfer is complete Check for timeout Test Descriptions 2 79 lll No e Verify the transfered bytes by reading main memory e Reset the FAS 236 to release the SCSI bus Possible Error Messages Data Compare Error address X expected X observed X char fas_dvma_xfr_timeout_err_txt Transfer timeout waiting on SCSI DVMA Control register char fas_dvma_read_fifo_err_txt FIFO data compare error char fas_dvma_write_mem_err_txt Memory data compare error Subtest SCSI DVMA Write Error e ID 45 10 Level 17 e Attributes Test Module Program the FAS and ESC chips to do a DVMA write to an invalid address and verify that the correct error condition occurs Reset the FAS 236 Send NOP command to FAS after doing reset Set bit 3 Chip Test Mode of the Configuration Register 1 Set bit 0 Target Test Mode of the Test Register Load the Transfer Count Register with the number of bytes to be transferred Load the ESC SCSI DVMA Count register with the byte count Store the INVALID virtual address in ESC SCSI DVMA Address register Store the test data bytes directly into the FIFO register Issue a RECEIVE DATA W DMA command 0xAA into command register Turn on DMA and set direction in ESC SCSI DVMA Control re
50. SPARCserver 1000 POST User s Guide Y amp sS 20 SUN Sun Microsystems Computer Corporation 2550 Garcia Avenue Mountain View CA 94043 Part No 801 2916 10 Revision A May 1993 BO Please Recycle 1993 Sun Microsystems Inc 2550 Garcia Avenue Mountain View California 94043 1100 U S A by copyright and distributed under licenses apa or nisi docume ion may be Alls reserved This prod and related documentation are protect n No part vritten authorization of C iver ty ili perenne ree and licensed from Sun s Font panera RESTRICTED RIGHTS LEGEND Use duplication or disclosure by the United States Government is subject to the restrictions set forth in DFARS 252 227 7013 c 1 ii and FAR 52 227 19 The product described in this manual may be protected by one or more U S patents foreign patents or pending applications TRADEMARKS Sun Sun Micros seca Sun Microsystems Computer Cc trademarks rporation the Sun logo the SMCC logo are trademarks or registered red trademarks of UNIX System Laboratories Inc names mentioned herein are the trademarks of their respective owners All other produ AN ADARE a a aia the SCD ppoe paa are or i orae mena of SPARC International ste SPARC to Sun X Window System is a trademark and product of the Massachusetts Institute of Technology THIS PUBLICATION IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND EITHER EXPRESS OR IMPLIED INCLU
51. Status 00000000 OA gt Analyzing BIC data J22 SPARCserver 1000 POST User s Guide May 1993 OA gt XDBus 0 on BOARD caused parity error OA gt History log bit 12 shows failed BICs BIC 0 Byte 1 OA gt Hit any key to continue OA gt Dump Error Reset Status OA gt 0 3 Select Board OA gt ict Return Command gt r OA gt DEMON OA gt Select one of the following functions OA gt OW System Parameters OA gt ae Read Write device OA gt ee Software Reset OA gt 3 NVRAM Management OA gt 4a Error Reporting OA gt 15 Analyze Error Logs OA gt 6 Power Off at Main Breaker OA gt wer NVRAM SIMM tests OA gt xe Return to selftest OA gt Command gt 5 OA gt Error Log Analysis for Board 0 OA gt BWO CPU A OA gt XDBus Parity Error XDBus Data 00000000 00002000 XDBus Parity OA gt MQHO OA gt Multiple Errors OA gt XDBus Parity Error XDBus Data OA gt IOCO OA gt Multiple Errors OA gt XDBus Parity Error XDBus Data 00000000 00002000 XDBus Parity OA gt XDBus 0 on BOARD caused parity error OA gt History log bit 12 shows failed BICs BIC 0 Byte 1 OA gt Log Date Mar 17 0 14 53 GMT 1993 OA gt CPU A Function at time of error System Level Software OA gt CPU B Function at time of error System Level Software OA gt ti 00000000 00002000 XDBus Parity ti 00 00 00 Overview
52. Test all memory on this MQH If a group with memory is not found return FAIL The purpose of the test is to test enough memory to allow the consistency tests to run The memory test functions are loaded into the Icache for speed The short memory test algorithm is e Clear the number of memory faults in the current test e Load the CC Stream Data register with alternate patterns e Loop through memory writing 64 bytes at a time e Check the memory Set up and load the alternate pattern Loop through memory writing 64 bytes at a time e Check the memory e The permanent ECC handler handles memory errors If the faults exceed 2 return FAIL The long memory test algorithm is e Clear the number of memory faults in the current test e Loop through a set of long long patterns e Load the stream data register with a pattern Fill memory with a pattern e Load the stream data register with pattern e Read then write pattern e Read pattern write pattern read Possible Error Messages Memory Compare Failure Addr X Expected X X Observed X X 2 88 SPARCserver 1000 POST User s Guide May 1993 No lll Subtest O 8000 Subtest Config Memory Available e ID 119 7 Level 1 e Attributes Error is Fatal Count the amount of memory available in the current configuration Possible Error Messages This module does not check or report errors CO NPB IO Ring 0x78 e ID 120 0 e Attributes Non
53. Testdata Oxffffffff Write word testdata to ESC DMA Count register Write word inverse testdata to word 0 in Lance buffered memory Read word testdata from ESC DMA Count register Compare and print error message if miscompare SPARCserver 1000 POST User s Guide May 1993 No lll ESC register back to back write write read read test e Testdata 0x1 0x2 0x4 0x40000000 0x80000000 e Write word inverse testdata to ESC DMA Address register e Write word testdata to ESC DMA Count register e Write word inverse testdata to word 0 in Lance buffered memory e Read word inverse testdata from ESC DMA Address register e Read word testdata from ESC DMA Count register e Compare and print error message if miscompare Testdata Oxffffffff e Write word inverse testdata to ESC DMA Address register e Write word testdata to ESC DMA Count register e Write word inverse testdata to word 0 in Lance buffered memory e Read word inverse testdata from ESC DMA Address register e Read word testdata from ESC DMA Count register e Compare and print error message if miscompare Possible Error Messages 6s Register data compare error address X expected X observed X char esc_d_ctl_err_txt ESC SCSI DVMA Control char esc_d_adr_err_txt ESC SCSI DVMA Address char esc_d_cnt_err_txt ESC SCSI DVMA Count char esc_reg_b2b_err_txt ESC back to back access Test Descriptions 2 105 lll No 2 10
54. X Stream ready bit timed out Check tags failed cctag X X exp state x bwtag X exp state x Check Dcache tags failed address X expected valid bit x observed valid x DCache tag has inconsistent state ptag X X Read hit Ecache data error addr X expected X X observed X X Test Descriptions 2 49 Read miss Ecache data error address X expected SX SX observed X X ole x lt Victimize error for address write invalidate failed for address X IO loopback read data error address X expected 5X 5X observed X X IO loopback read miss failed address X IO loopback read hit failed address X IO loopback write miss failed address X IO loopback write hit failed address X IO cache shared owner failed address X IOC check tags line dex X Xob SX X TOC check data ex X ob X word d IO cache flush data error address X expected SX SX observed X X CPU read data address X expected SX SX observed X X Check RefMiss count xpected CRC X CMC X observed CRC X CMC X SPARCserver 1000 POST User s Guide May 1993 No lll O0e O 0000 Subtest Subtest SPARC Module Board Master 0x29 e ID 41 0 Attributes General Purpose Diagnosis PUA Module CPUB Module Test all functional elements of the SPARC Module C_O BW MQH e ID 41 1 Level 8 Attributes Error Te
55. _mem_err_txt Memory data compare error SPARCserver 1000 POST User s Guide May 1993 No lll SCSI DVMA Write e ID 126 9 Level 17 e Attributes Test Module Program the FAS and ESC chips to do DVMA write and verify Reset the FAS 236 Send NOP command to FAS after doing reset Set bit 3 Chip Test Mode of the Configuration Register 1 Set bit 0 Target Test Mode of the test register Load the Transfer Count Register with the number of bytes to be transferred Load the ESC SCSI DVMA Count register with the byte count Store the virtual address in ESC SCSI DVMA Address register Store the test data bytes directly into the FIFO register Issue a RECEIVE DATA W DMA command 0xAA into command register Turn on DMA and set direction in ESC SCSI DVMA Control register Wait 1uS to allow for internal command synchronization Wait for the bytes to be transferred via DMA control TCZERO Flush the SBI Write Buffers Now send the DRAIN command to the ESC Check that the ACTIVEO and ACTIVE bits in SCSI DVMA Control register are cleared indicating the data transfer is complete Check for timeout Verify the transfered bytes by reading main memory Reset the FAS 236 to release the SCSI bus Possible Error Messages o9 S address X expected 2X observed 2X char fas_dvma_xfr_timeout_err_txt Transfer timeout waiting on SCSI DVMA Control register char fas_dvma_read_fifo_err_txt FIFO d
56. a to FAS configuration register 2 Write byte inverse testdata to byte 0 in Lance buffered memory Read byte inverse testdata from FAS configuration register 1 Read byte testdata from FAS configuration register 2 Compare and print error message if miscompare Test Descriptions 2 77 lll No Possible Error Messages char fas_xfr_low_txt Transfer count low register compare error char fas_xfr_hi_txt J Transfer count high register compare error char fas_configl_txt Config register 1 compare error char fas_config2_txt Config register 2 compare error char fas_config3_txt Config register 3 compare error char fas_config2_b2b_txt Config reg 1 2 back to back compare error Subtest SCSI DVMA Read e ID 45 8 Level 17 e Attributes Test Module Program the FAS and ESC chips to do a DVMA read and verify Reset the FAS 236 Send NOP command to FAS after doing reset Set bit 3 Chip Test Mode of the Configuration Register 1 Set bit 0 Target Test Mode of the Test Register Load the Transfer Count Register with the number of bytes to be transferred Load the ESC SCSI DVMA Count register with the byte count Store the virtual address in ESC SCSI DVMA Address register Make this an INVALID virtual address Store the test bytes into the FIFO register Issue a SEND DATA W DMA command 0xA2 into command register Turn on DMA and set direction in ESC SCSI DVMA Control
57. ability test case e Loop through all the patterns Possible Error Messages Data Compare Error address X expected X X observed X X SPARCserver 1000 POST User s Guide May 1993 No lll Subtest Ecache SRAM ID 14 3 Level 8 e Attributes Test Module Initialization Module Test access size addressing and SRAM data reliability This test is run with the external cache disabled Test CC SRAM access Write a pattern into an SRAM double word location Read it back a byte at a time and verify Read it back a half at a time and verify Read it back a word at a time and verify Write every byte in the cache line Read and verify Write every half in the cache line Read and verify Write every word in the cache line Read and verify Test CC SRAM addressing e Write pass address up e Read pass address up e Write pass address down e Read pass address down Test CC SRAM data reliability Only do the long test if POST LEVEL is high Loop through all the patterns Checking for stuck ats Test pattern and pattern Turn on CPU module Bus parity and watch for traps Set up trap to handle data access exception parity error Loop through all patterns Check for parity error Check for miscompares Do a short test for booting DIAG Switch OFF e Turn on CPU module Bus parity and watch for traps e Set up g5 and g6 to expect data access exception Test De
58. ailed expected observed oA le X X Floating a bit through s register failed expected X X observed X X s fields SEGA C S updated when WSA 0 expected observed SBI Initialization e ID 122 3 Level 1 Attributes Error Terminates Sequencer Error is Fatal Initialize all SBI registers to the default values SPARCserver 1000 POST User s Guide May 1993 No lll Subtest Possible Error Messages This module does not check or report errors SBus Interrupts ID 122 4 Level 8 e Attributes Test Module Test all levels of SBus interrupts for all SBus slots Verify that the correct interrupt state is recorded in the BWs MXCC and SBI chips Insure that the correct SPARC interrrupt level is delivered to the CPU This test is executed on eack board by the CPU on that board SBus slots on non processor boards will be tested using this test e Mask all interrupts except level 15s e Clear all existing interrupt states e Establish this board s BW as the target for this SBus s interrupts e Verify the CC transaction to the SBI interrupt target register e Loop for all levels SBus has levels 1 through 7 e Loop for all slots each board has 4 SBus slots e Use diagnostic register to generate SBus interrupt e Issue a TAKE and check the state register issue a GIVE and check the state register e Check the BW interrupt table e Check CC interrupt pending e Unmask
59. alidation e ID 41 3 Level 17 Attributes Test Module Error Terminates Sequencer Verify that the root and level 2 ptp caches are invalidated properly on context switches ctpr switches and so on e Initialize root ptp and 12 ptp caches with valid entries Do the following write to ctx register write ctpr register flush entire flush context flush region flush segment flush page e In each case verify root ptp and 12 ptp caches are invalidated or left alone according to specifications This test issues demap packets writes to TLB flush ASI BWs and MQHs need to be on and demap must be enabled in one MQH It does not need memory Test Descriptions Peek lll No Possible Error Messages Wrong root ptp cache valid state Wrong 12 ptp cache valid state Subtest MMU Stuff TLB Hit e ID 41 4 Level 17 Attributes Test Module Error Terminates Sequencer Test basic functionality of MMU TLB Context test e Initialize TLBs with unique contexts and ptes but same vaddr tag 0 e Initialize target memory locations with unique data e Read from vaddr 0 using different contexts and verify that you get the correct data each time vadadr test e Initialize TLBs with unique vaddr and ptes but same context 0 e Initialize target memory locations with unique data e Read from different vaddr Walking 1s pattern through bits 31 12 with ctx 0 and verify that you get the correct data each time
60. ata is the unformatted contents of all JTAG scannable ASIC registers Analyze Error Logs Option The Analyze Error Logs DEMON option does not have a menu When you type 5 at the main menu prompt POST begins analyzing and displaying the error logs POST always logs the last System Watchdog error in BootBus NVRAM The Analyze Error Logs option analyzes System Watchdog error logs If there are any error bits set POST formats and displays the relevant data Overview of POST 1 9 1 10 This function is also be invoked by e All board masters upon a System Watchdog Reset In this case each board can only see its own error log because the BICs are in loopback Note that the POST System Master maintains and analyzes the error log for all non processor boards The POST System Master after the loopback exit phase of testing only if there was a recent System Watchdog In this case the POST System Master analyzes the error log from each board in the system If no error bits are set you only see a banner for that board Note For troubleshooting purposes only it is possible to clear the error logs using the DEMON menus The timestamp for each error log is taken from the TOD on that board If the operating system has not initialized the TOD ignore the timestamp and use the Clear Error Logs option from the System Parameters menu for this task Power Off at Main Breaker Option The Power Off at Main Breaker DEMON
61. ata compare error Test Descriptions 2 109 lll No 2 110 Subtest char fas_dvma_write_mem_err_txt Memory data compare error SCSI DVMA Write Error e ID 126 10 Level 17 e Attributes Test Module Program the FAS and ESC chips to do a DVMA write to an invalid address and verify that the correct error condition occurs Reset the FAS 236 Send NOP command to FAS after doing reset Set bit 3 Chip Test Mode of the Configuration Register 1 Set bit 0 Target Test Mode of the Test Register Load the Transfer Count Register with the number of bytes to be transferred Load the ESC SCSI DVMA Count register with the byte count Store the INVALID virtual address in ESC SCSI DVMA Address register Store the test data bytes directly into the FIFO register Issue a RECEIVE DATA W DMA command 0xAA into command register Turn on DMA and set direction in ESC SCSI DVMA Control register Wait 1uS to allow for internal command synchronization Wait for error bit DMA_ERR to be set in SCSI DMA Control register Check for timeout Reset the FAS 236 to release the SCSI bus Possible Error Messages ae S address X expected 2X observed 2X char fas_dvma_xfr_timeout_err_txt Transfer timeout waiting on SCSI DVMA Control register char fas_dvma_read_fifo_err_txt FIFO data compare error SPARCserver 1000 POST User s Guide May 1993 No lll char fas_dvma_write_mem_err_txt
62. ata reliability e Write all the state bits and an incrementing pattern in the Paddr field e Flash clear the lock bits check thatthey get cleared and that Paddr is not changed e Flash clear the valid and mru bits check that all valid and mru bits are clear and that lock bits and Paddr field are unchanged Possible Error Messages Data Compare Error address X expected X X observed X X Instruction Cache Ram ID 13 2 Level 17 e Attributes Test Module Initialization Module Test the instruction cache RAM Address Ascending e Write each address with its address as the data e Read and verify each address Address Descending e Write each address with its address as the data e Read and verify each address SPARCserver 1000 POST User s Guide May 1993 No lll Subtest Cell Disturbance e Write the entire cache with a checkerboard bit pattern e Read and verify each address e Reverse the checkerboard pattern and repeat Data Reliability e Write the cache with standard test patterns e Read and verify the data Possible Error Messages Data Compare Error address X expected X X observed X X Data Cache Tags e ID 13 3 Level 8 e Attributes Test Module Initialization Module Test the CPU s data cache tags for address uniqueness and data reliability Address Ascending e Write each tag with its address as the data e Read and verify each add
63. basic functionality of MMU TLB Context test e Initialize TLBs with unique contexts and ptes but same vaddr tag 0 e Initialize target memory locations with unique data e Read from vaddr 0 using different contexts and verify that you get the correct data each time Test Descriptions 2 63 2 64 Subtest vaddr test e Initialize TLBs with unique vaddr and ptes but same context 0 e Initialize target memory locations with unique data e Read from different vaddr Walking 1s pattern through bits 31 12 with ctx 0 and verify that you get the correct data each time Assumption Ecache is enabled No table walks are done in this test Make sure ASI 0x20 accesses are cacheable so that memory packets are generated instead of I O packets Possible Error Messages Wrong data on read with tlb hit Wrong data on read with tlb hit MMU Table Walk e ID 43 5 Level 17 Attributes Test Module Error Terminates Sequencer Test MMU table walk operation Probe 10 test e Initialize memory with unique 10 ptps Do 10 probe using for the following cases ctpr 0x80000 0x40000 0x2000 0 ctx 0x8000 0x4000 1 and verify that you get expected 10 ptp Probe 11 test e Initialize memory with unique 11 ptes e Clear 10 ptp register e Do 11 probe with all different index1 and verify that you get correct 11 pte Verify 10 ptp register gets updated Probe 12 test e Initialize memory with uniqu
64. butes Test Module Read write and verify the IOC s XDBus tags Possible Error Messages Data Compare Error address X expected X observed X TOC Sbus Tags e ID 32 4 Level 8 e Attributes Test Module Read write and verify the IOC s SBus tags Possible Error Messages Data Compare Error address X expected X observed X IOC Cache RAM e ID 32 5 Level 8 e Attributes Test Module Read write and verify the IO Cache RAM SPARCserver 1000 POST User s Guide May 1993 No lll O0e O O000 Subtest Subtest Possible Error Messages Data Compare Error address X expected X observed X CO SBI 0x21 ID 33 0 Attributes General Purpose Diagnosis SBI Test the SBI ASIC SBI Initialization ID 33 1 Level 1 Attributes Error Terminates Sequencer Error is Fatal This function initializes all SBI Registers to the default values Possible Error Messages This module does not check or report errors SBI Registers e ID 33 2 Level 8 Attributes Test Module Error Terminates Sequencer Test the read and write accessibility of all SBI ASIC registers using all access sizes allowed The addresses of the SBI registers are in ECSR space If any access causes a data access exception or unexpected interrupt the test aborts with a FAIL status The SBI Interrupt registers with the exception of the Interrupt Target I
65. cache must be enabled Issue a load for subblock 0 read the CC tag and insure that subblock 0 and 1 are valid Then issue a load for subblock 1 and insure that subblock 2 gets prefetched Then issue a load for subblock 2 and insure subblock 3 gets prefetched Flush Line Verify that when a line is victimized the valid blocks in the line get flushed to memory SPARC Module Features Test all SPARC module features Fill a buffer with the feature off then enable the feature and fill a second buffer Compare the two buffers for equality Features tested are Store Buffer Prefetcher Cache Cache PSO Snoop Multi Instruction Multi Command Ecache Prefetch and Write Invalidate Possible Error Messages Store Buffer Memory Compare Error address X expected X X observed X X CC Prefetch failed address X fetch block 1x prefetch block 1x Flush Block did not update memory address X flush block 1x Flush Block disturbed wrong memory block address X flush block 1x SPARCserver 1000 POST User s Guide May 1993 No lll Subtest Block Compare Error Source Address X Destination X Byte Count X Cache Data and Memory Data don t agree doubleword 1X cache data X X memory data X X char sparc_enable_err_txt Data with features on not equal to data with features off buffer index x feature off data X X feature on data X X MMU PTP Cache Inv
66. config2_txt Config register 2 compare error char fas_config3_txt Config register 3 compare error char fas_config2_b2b_txt Config reg 1 2 back to back compare error Test Descriptions 2 107 lll No 2 108 SCSI DVMA Read e ID 126 8 Level 17 e Attributes Test Module Program the FAS and ESC chips to do a DVMA read and verify Reset the FAS 236 Send NOP command to FAS after doing reset Set bit 3 Chip Test Mode of the Configuration Register 1 Set bit 0 Target Test Mode of the Test Register Load the Transfer Count Register with the number of bytes to be transferred Load the ESC SCSI DVMA Count register with the byte count Store the virtual address in ESC SCSI DVMA Address register Make this an INVALID virtual address Store the test bytes into the FIFO register Issue a SEND DATA W DMA command 0xA2 into command register Turn on DMA and set direction in ESC SCSI DVMA Control register Wait 1uS to allow for internal command synchronization Wait for the bytes to be transferred via DMA control TCZERO Check for timeout Verify the transfered bytes by reading the FIFO register Reset the FAS 236 to release the SCSI bus Possible Error Messages ae S address X expected 2X observed 2X char fas_dvma_xfr_timeout_err_txt Transfer timeout waiting on SCSI DVMA Control register char fas_dvma_read_fifo_err_txt J FIFO data compare error char fas_dvma_write
67. d A o x lt Bypass Stream Read Failed Slot x expected observed oA o x lt x lt Bypass Consistent Write Failed Slot x expected X observed X ae ol Bypass Consistent Read Failed Slot x expected X observed X A le SBI Flush Write Buffers timed out Slot x Stream Buffer Control Register X SPARCserver 1000 POST User s Guide May 1993 No lll Subtest WARNING Test skipped no memory in configuration X IOC MQH Consistency ID 38 3 Level 17 e Attributes Test Module Test consistency between the IO Cache and main memory e Assign a test address for each board Each board has a cache line in virtual page 0 Put test data in memory Initialize the IO chips for loopback operation Verify that a read will miss and cause an IOC line fill Verify that a read to the same address will hit in the IOC Verify that a write miss will cause an IOC line fill Verify that a write will hit in the IOC and update the IOC data Verify that the IOC is the owner and will reply with a CPU read Verify that the data became shared Verify that the IOC will flush owned data to memory e A write miss must cause an IOC line fill This write will hit in the IOC and update the IOC data e Issue a read for address alias flush The IOC must flush the dirty line to memory e Check IOC flushed data Possible Error Messages Block compare failed load address X
68. d Page List OA gt Me Return to Main menu OA gt Command gt 2 OA gt Bad Memory Pages in System OA gt No Bad pages found OA gt Hit any key to continue Overview of POST 1 21 lll OA gt Bootbus NVRAM Management OA gt Select one of the following functions OA gt oe Print Bad Group List 0a gt Ev Clear Bad Group List OA gt x27 Print Bad Page List OA gt oy Clear Bad Page List OA gt it Return to Main menu OA gt Command gt r OA gt DEMON OA gt Select one of the following functions OA gt wor System Parameters OA gt yI Read Write device 0a gt ver Software Reset OA gt e NVRAM Management OA gt 4a Error Reporting OA gt x5r Analyze Error Logs OA gt Ge Power Off at Main Breaker OA gt Y7 NVRAM SIMM tests 0a gt xt Return to selftest OA gt Command gt 4 OA gt Dump Error Reset Status OA gt 0 3 Select Board OA gt vee Return Command gt 0 OA gt Dumping local board 0 OA gt Log Date Mar 17 0 14 53 GMT 1993 OA gt A CC Error Register 00000000 00000000 OA gt B CC Error Register 00000000 00000000 OA gt Processor A OA gt BWO DCSR 0001A000 0800DD10 DDR OA gt Processor B QOA gt BWO DCSR OOFFFOFF FFFFFFFF DDR FPREFFFFFE FFFFFFFE OA gt MQHO DCSR 00048700 1800D090 DDR 00000000 00002000 0 0 00000000 00002000 OA gt IOCO DCSR 0001A000 2800DD90 DDR 00000000 00002000 OA gt SBI Control 00020000
69. d better isolation of failing components on the system boards In diag mode you can communicate with POST You can control POST using keyboard commands and you can use its test control features POST is very verbose in this mode See Appendix A for a sample POST run 1 2 1 System and Board LEDs The SPARCserver 1000 system has three system LEDs and ten board LEDs Their function is described in this section System LEDs The left system LED is green the center LED is yellow and the right LED is green The left LED green is the power indicator Once the power to the system is turned on this LED always remains lit ON When the center LED yellow is ON it indicates that POST is running If the center LED yellow remains lit for more than 1 minute in normal mode and the right LED green never lights up it shows that the machine is unable to boot In diag mode this LED remains lit for longer than one minute If the center and right LEDs light up simultaneously it shows that the system has booted with failing components which POST has disabled You should be able to boot UNIX or other stand alone diagnostics If the right LED green is ON and the center LED yellow is OFF it indicates that the system has passed POST without any failures Overview of POST 1 3 Board LEDs The ten board LEDs work as follows e Two green board LEDs A and B indicate the presence of functional processors on a board a
70. e store load pairs to insure that the loads are stalled until the stores complete Store Buffer Access Issue stores of all sizes and on all boundaries and check the memory data CC Prefetch Verify the CC prefetch logic When prefetch is enabled a prefetch should occur under the following conditions when the next sequential subblock of the one just fetched is not valid and contained within the same line then prefetch Burst Read Miss Subblock n Prefetch Subblock n 1 Note that prefetch is only issued for burst reads the Dcache must be enabled Issue a load for subblock 0 read the CC tag and insure that subblock 0 and 1 are valid Then issue a load for subblock 1 and insure that subblock 2 gets prefetched Then issue a load for subblock 2 and insure subblock 3 gets prefetched Flush Line Verify that when a line is victimized the valid blocks in the line get flushed to memory Test Descriptions 2 61 lll No e SPARC Module Features Test all SPARC module features Fill a buffer with the feature off then enable the feature and fill a second buffer Compare the two buffers for equality Features tested are Store Buffer Prefetcher Cache Cache PSO Snoop Multi Instruction Multi Command Ecache Prefetch and Write Invalidate Possible Error Messages Store Buffer Memory Compare Error address X expected SX SX observed X X CC Prefetch failed address X fetch block 1x prefetch block 1x Flush Bl
71. e 12 ptes e Do 11 probe with all different index2 and verify that you get correct 12 pte SPARCserver 1000 POST User s Guide May 1993 No lll Subtest Probe 13 test e Initialize memory with unique 13 ptes e Clear 12 ptp register Do 13 probe with all different index3 and verify that you get correct 13 pte Verify 12 ptp register gets updated Probe entire test e Initialize memory with unique 13 ptes e Do entire probe with all different index3 and verify that you get correct 13 pte e Verify ref bit is updated Possible Error Messages Wrong root pointer on 10 probe Wrong 11 entry on 11 probe Wrong root ptp cache Wrong 12 entry on 12 probe Wrong 13 entry on 13 probe Wrong 12 ptp cache Wrong 12 vaddr cache Wrong 13 entry on 13 probe Ref bit is not set MMU Flush e ID 43 6 Level 17 Attributes Test Module Error Terminates Sequencer Test MMU TLB flush opeartion Test Descriptions 2 65 Level0 context e Initialize TLBs with unique ctx tags and same vaddr 0 e ctx flush with different ctxs and verify correct TLBs are invalidated after each flush Levell segment e Initialize TLBs with unique tags and same ctx 0 e seg flush with different index1 and verify correct TLBs are invalidated after each flush Level2 region e Initialize TLBs with unique tags and same ctx 0 e reg flush with different index2 and verify correct TLBs are invalidated after each flush Level3 page
72. e Table OA gt 2 Display System OA gt 3 Dump Board Registers OA gt 4a Dump Component IDs OA gt 5 Clear Error Logs OA gt So Display Simms OA gt Tg Scrub Main Memory OA gt saat Return Command gt r OA gt DEMON OA gt Select one of the following functions OA gt o System Parameters OA gt ling Read Write device OA gt w2 Software Reset 0a gt 3 NVRAM Management OA gt 4 Error Reporting OA gt x5r Analyze Error Logs OA gt MOS Power Off at Main Breaker OA gt ht NVRAM SIMM tests OA gt waa Return to selftest OA gt Command gt 1 Overview of POST 1 19 lll rwdev gt rwdev gt rwdev gt rwdev gt OA gt DEMON OA gt Sel OA gt rwdev gt OA gt General command format is op_size_space asi address data count increment op r or w or q read or write or quit size b h w ord space a or v alternate or virtual space asi 2 0x4c if alternate space address device or memory address data write data if write count optional range count increment optional address increment default is data type NOTE s are ignored and can be used as seperators Examples wba 2f f01e 0000 a5 4 writes 4 consecutive bytes into bootbus SRAM rdv 0 10 reads the frist 16 doublewords from cachable space rda 2 0180 0000 4 100 reads the first 4 MXCC tags rwa 2f fff0 3010 40 0 reads the BW tick timer 64 times
73. e eateries ceoeeeeieieeis B 1 B 1 1 TestIDs and SubtestIDs eee eeee B 1 B 1 2 TestLists and Sequencers cs ce bed kw ew eedwn B 2 B 1 3 Test Levels and Error Levels B 2 Boils Test Desig as cne cave eer ie tia eee ee eee et B 2 B 2 Phases of POST iecerei pueden ne eena ee eee B 3 B 3 Errof Handling 2h ca ee ee eee aor ewan ea ps B 5 B 4 R nning POST estee nee seek irinotecan eee E B 6 Glossa ie apinn orere nanamu ee E E e ee Glossary 1 INdEX epgactaneheceerwntansneene E EEEE Index 1 SPARCserver 1000 POST User s Guide May 1993 Tables Table P 1 Table P 2 Table 1 1 Table 1 2 Typographic Conventions 6c e cece eee eee viii Related Documentation sasssa 0c cece eee ix Error Message Fields 0 6 c cece ccc eee ee 1 4 User Interface Key Commands 6 600 c eee ee 1 6 vi SPARCserver 1000 POST User s Guide May 1993 Preface This manual SPARCserver 1000 POST User s Guide describes the Power On Self Test POST software that is part of the diagnostics that test the SPARCserver 1000 system POST resides in the boot PROM programmable read only memory on each SPARCserver 1000 system board The information in this manual is for manufacturing and test engineers repair depot and field service personnel and diagnostics engineers who test the SPARCserver 1000 system The manual does not describe the system architecture it assumes you ar
74. e familiar with such hardware concepts It provides some background information about the POST software explains how you can use it and contains detailed information about the tests that make up the software The manual is organized as follows Chapter 1 Overview of POST The first chapter introduces you to POST and tells you how to use the software Chapter 2 Test Descriptions The second chapter comprehensively describes the tests of the POST software For each test there is a test description an LED pattern the basic steps executed by the test and a summary of error messages Appendix A Sample POST Output This appendix shows the results of a sample run of the POST software vii Appendix B POST Design Concepts This appendix describes the design principles for POST Glossary The glossary enhances your understanding of POST by defining the SPARCserver 1000 system terminology Typographic Changes and Symbols The following table describes the font and symbol conventions used in this manual Table P 1 Typographic Conventions Typeface or Symbol Meaning Example AaBbCc123 AaBbCc123 AaBbCc123 AaBbCc123 The names of commands files and directories on screen computer output What you type contrasted with on screen computer output Also the POST test names will be shown with this typeface Command line placeholder replace with a real name or value Book titles new words or terms
75. e testdata from ESC DMA Address register Read word testdata from ESC DMA Count register Compare and print error message if miscompare Test Descriptions 2 75 lll No Possible Error Messages Register data compare error address X expected X observed X char esc_d_ctl_err_txt J ESC SCSI DVMA Control char esc_d_adr_err_txt J ESC SCSI DVMA Address char esc_d_cnt_err_txt ESC SCSI DVMA Count char esc_reg_b2b_err_txt ESC back to back access Subtest FAS236 Registers e ID 45 7 Level 17 e Attributes Test Module FAS configuration register 1 write write read test For testdata 0x1 0x2 0x4 0x40 0x80 e Write byte testdata to FAS configuration register 1 e Write byte inverse testdata to byte 0 in Lance buffered memory e Read byte testdata from FAS configuration register 1 e Compare and print error message if miscompare e testdata Oxff e Write byte testdata to FAS configuration register 1 e Write byte inverse testdata to byte 0 in Lance buffered memory e Read byte testdata from FAS configuration register 1 e Compare and print error message if miscompare 2 76 SPARCserver 1000 POST User s Guide May 1993 No lll FAS configuration register 2 write write read test For testdata 0x1 0x2 0x4 0x40 0x80 Write byte testdata to FAS configuration register 2 Write byte inverse testdata to byte 0 in Lance buffered memory Read byte
76. e write read read miscompare Subtest Lance Local Loopback e ID 126 5 Level 17 e Attributes Test Module Test Lance transmit and receive functions using internal loopback e Initialize the init block transmit receive pointers e Issue stop to Lance chip and verify it stopped e Set to internal loopback e Initialize the init block parameters e Initialize the receive block parameters e Initialize the transmit block parameters Load CSR1 2 with the base of the init structure Start timeout loop waiting for Lance chip to init e Set up transmit and receive buffer data 32 byte incrementing pattern e Load buffer for transmit and clear receive buffer 2 102 SPARCserver 1000 POST User s Guide May 1993 No lll Send transmit command e Start timeout loop waiting for transmit confirmation Start timeout loop waiting for receive confirmation Possible Error Messages WARNING Check Ethernet cable Lance chip initialization failed Set up destination address in transmit block Set up source address in transmit block Verify the receive data transmit data CSRO expected 4X CSRO observed 4X Error condition detected CSRO 4X oS CSRO 4X Rx msg Descriptor 1 4X Tx Msg Descriptor 1 4X x Msg Descriptor 3 4X Rx data error address X expected 2X observed 2X Test Descriptions 2 103 lll No 2 104 Subtest ESC Registers e ID 126 6
77. ed X X Victimize error for address X Write invalidate failed for address X Test Descriptions 2 39 2 40 O0e O O O IO loopback read data error address X expected SX SX observed X X IO loopback read miss failed address X IO loopback read hit failed address X IO loopback write miss failed address X IO loopback write hit failed address X TO cach shared owner failed address X IOC check tags line dex X Xob X X TOC check data ex X ob X word d IO cache flush data error address X expected SX SX observed X X CPU read data address X expected SX SX observed X X Check RefMiss count xpected CRC X CMC X observed CRC X CMC X CO IOC MQH Consistency 0x26 e ID 38 0 Attributes General Purpose Diagnosis IOCO MQHO Set Configuration 0 and test consistency between IOC and main memory SPARCserver 1000 POST User s Guide May 1993 No lll Subtest Subtest C_0 BW IOC MOH e ID 38 1 Level 17 Attributes Error Terminates Sequencer Error is Fatal Establish the board configuration for this test Possible Error Messages This module does not check or report errors SBus Loopback e ID 38 2 Level 17 e Attributes Test Module Use the SBus loopback feature of the SBI ASIC to test and exercise the paths between the CPU and SBus and the SBus and main memory IO cache and CPU cache tra
78. een BW and IOC C_0 BW IOC MOH e ID 39 1 e Level 17 Attributes Error Terminates Sequencer Error is Fatal Establish the board configuration for this test Possible Error Messages This module does not check or report errors Test Descriptions 2 45 lll No Subtest Cache States ID 39 1 Level 17 e Attributes Test Module Initialization Module Walk the MXCC state table through all state transistions except the ones that require Write Invalidate Mode and another CPU The IOC is used in loopback mode to effect foreign reads and writes The following transistions are tested Invalid to Valid not Shared Owner Invalid to Valid Shared not Owner Invalid to Valid not Shared not Owner Valid to Valid via CPU read Valid to Valid not Shared owner Valid to Valid Shared not Owner via foreign read Valid to Valid Shared not Owner via foreign write miss Owner to Owner via CPU write Owner to Owner via CPU read Owner to Shared Owner Shared to Shared Owner Shared to Shared via CPU read Shared to Shared via foreign read Shared to Shared via foreign write Shared to Shared via foreign write miss Shared and Owner to Owner Shared and Owner to Shared Shared and Owner to Shared Owner via CPU write Shared and Owner to Shared Owner via CPU read Shared and Owner to Shared Owner via foreign read Shared and Owner to Shared via foreign write miss Possible Error Messages
79. egisters Test 1A gt Lance Local Loopback Test 1A gt ESC Registers Test 1A gt FAS236 Registers Test 1A gt SCSI DVMA Read Test 1A gt SCSI DVMA Write Test 1A gt SCSI DVMA Write Error Test 1A gt Bus Ring Test 1A gt Verify Bus Ring Test 1A gt CO BP Check Test 1A gt Wait for Alt 1A gt XDBus setup C_0 1A gt CO Backplane Check Test 1A gt CO Exit LB Test 1A gt Loopback Exit C_0O Test 1A gt programming MOH group addr at E1101000 to 0180000C 1A gt programming MOH group addr at E1101008 to 0100000C 1A gt programming MOH group addr at E1101040 to 0080000C 1A gt programming MOH group addr at E1101048 to 0000000C 1A gt Reading Address Decoding Registers from Hardware 1A gt b1 d0 g0 IF 0 IV O ssize 3 1A gt b1 dO gl IF 0 IV 0 ssize 3 1A gt b1 d0 g2 IF 0 IV O ssize 3 1A gt b1 d0 g3 IF 0 IV 0 ssize 3 1A gt total pmem 0x00020000 pages 0x020000000 bytes in 1 chunks 1A gt DRAM chunk 0 base 0x00000000 size 0x00020000 1A gt 0 failed 1 passed blank untested unavailable sbus l card present 0 card not present x failed 1A gt 1A gt Slot copuA bw0 cpuB bw0 bb ioc0 sbi mqh0 mem sbus xd0 1A gt 1A gt 1 A e ah it 1 T 1 1 512 1001 1 1A gt 1A gt 1A gt Memory Group Status O failed 1 passed m simm missing c simm mismatch blank unpopulated unused 1A gt 1A gt Slot gO gl
80. equivalent You need this set up to see status and error information during POST execution You can invoke POST in one of these ways Turn on the power to your SPARCserver 1000 system Press the system reset switch which is located under the front panel Depending on the position of the key switch which is on the front of the system under the front panel POST will execute in normal mode key switch in the normal or SECURE position or diagnostic mode key switch in the DIAG position Diagnostic mode is hereafter called diag mode Normal Mode Normal mode is used for booting the operating system quickly In normal mode the actual operation of POST is transparent to the user POST initializes the SPARCserver 1000 hardware state and tests all system board components out to the SBus connectors If errors are detected POST attempts to recover by modifying the system configuration to exclude the faulty components When POST completes it transfers control to the OpenBoot firmware which then boots the operating system In normal mode POST should transfer control to OpenBoot firmware within one minute it does not display any status messages but it does display error messages as they occur SPARCserver 1000 POST User s Guide May 1993 lll Diag Mode Diag mode is used to test and troubleshoot the SPARCserver 1000 system boards In diag mode POST executes a larger set of diagnostics which provide additional coverage an
81. erver 1000 has only one XDBus system bus so the only possible configuration for this server is C0 C1 and C2 do not apply System Level Testing System level testing is divided into three sub phases one for the CO configuration one for C1 and one for C2 the only possible configuration for the SPARCserver 1000 is C0 Each sub phase is run by the corresponding system master Each system master puts all the boards into the configuration for which it is master then tests non processor boards and for the CO and C1 configurations the system s main memory Next it runs system level tests that SPARCserver 1000 POST User s Guide May 1993 B B 3 Error Handling include checking inter processor interrupts device to processor interrupts and cache coherency Finally each system master computes the value of its configuration as the weighted sum of available resources and stores this value in specific registers of all working Bus Watcher ASICs in the system These values are used in the reconfiguration phase of testing Reconfiguration In the reconfiguration phase the configuration with the highest value is the winner The system master of the winning configuration initializes the system to be in this configuration Memory is configured and interleaved and bad memory groups are excluded POST sends the OpenBoot firmware information on functioning system resources as well as The device table which includes data on the par
82. f the Lance chip and FAS 236 chip that are on the NPB System Board SPARCserver 1000 POST User s Guide May 1993 No lll Subtest Subtest Subtest C_0 NPB IOC MQH e ID 126 1 Level 1 Attributes Error Terminates Sequencer Error is Fatal Establish the board configuration for this test Possible Error Messages This module does not check or report errors Check OnBoardIO Cardo e ID 126 2 Level 1 Attributes Test Module Error Terminates Sequencer Check that Slot 0 did not trap when probed Possible Error Messages Board x Card0 not in this configuration Lance Memory e ID 126 3 Level 17 e Attributes Test Module Test the Lance memory buffer e Do 1 2 4 8 byte accesses to entire 32 byte at each address bit e Do marching a5 s forward and backward to entire 128Kbytes Test Descriptions 299 lll No Possible Error Messages Lance memory compare error address X expected X observed X Lance memory compare error address X expected X X observed X X Subtest Lance Registers e ID 126 4 Level 17 e Attributes Test Module Lance RAP write read read test Testdata 0x1 0x2 0x4 0x4000 0x8000 Write halfword testdata to Lance RAP register Write halfword inverse testdata to word 0 in Lance buffered memory Read halfword testdata from Lance RAP register Compare and print error message if miscompare Testdata Oxffff
83. g mmu far on twalk protect error Got unexpected trap Got mfsr fault valid 2 58 SPARCserver 1000 POST User s Guide May 1993 No lll Subtest Subtest MMU Table Walk With Parity Error e ID 41 9 Level 17 Attributes Test Module Error Terminates Sequencer Do table walk with parity error e Make pte cacheable in Ecache e Do table walk without parity error e Repeat for different access types e Repeat for level 1 3 ptes e Repeat with parity error Possible Error Messages No trap on twalk parity error Wrong mmu fsr on twalk parity error Wrong mmu far on twalk parity error MMU Table Walk With ECC Error e ID 41 10 e Level 17 Attributes Test Module Error Terminates Sequencer Do table walk with ECC error ptes not cacheable in Ecache e Do table walk with ce error e Repeat for different access types e Repeat for level 1 3 ptes e Repeat with ue error Possible Error Messages No trap on table walk w ue Wrong mmu fsr on table walk w ue Wrong mmu far on table walk w ue Test Descriptions 259 OO0O0O 8008 Subtest Subtest Wrong mqh ue error addr reg after table walk w ue Wrong mqh ue error data reg after table walk w ue No trap on table walk w ce Wrong mqh ce error addr reg after table walk w ce Wrong mqh ce error data reg ce after table walk w ce SPARC Module Board Slave 0x2B e ID 43 0 Attributes General Purpose D
84. gister Wait 1uS to allow for internal command synchronization Wait for error bit DMA_ERR to be set in SCSI DMA Control register Check for timeout Reset the FAS 236 to release the SCSI bus 2 80 SPARCserver 1000 POST User s Guide May 1993 No lll 2 3 Loopback Exit O 0e 8008 Subtest Possible Error Messages Data Compare Error address X expected X observed X char fas_dvma_xfr_timeout_err_txt Transfer timeout waiting on SCSI DVMA Control register char fas_dvma_read_fifo_err_txt FIFO data compare error char fas_dvma_write_mem_err_txt Memory data compare error Using JTAG take the BICs out of loopback From this point on the BICs should not be in loopback Bus Ring 0x59 e ID 89 0 Attributes General Purpose e Diagnosis XDBus0 Test continuity and length of the JTAG scan ring and the component IDs of all the chips on Bus Interface JTAG scan ring Verify Bus Ring ID 89 2 Level 1 e Attributes Test Module Initialization Module Scan in the ring containing the BIC and BARB ASICs verify that the JTAG data is correct Test Descriptions 2 81 2 82 O0O0 80080 Subtest Subtest Possible Error Messages JTAG TAP state machine not responding Incorrect arguments passed by caller JTAG component ID does not match JTAG ring continuity test failed State after initialization not expected Ring length does not match expected CO BP Check 0x5B
85. his flag to allow POST to display the name of each step as it goes through the system initialization sequence Reset the flag and POST displays only the major milestones and the spin loopbar N Skip to next test Set this flag to terminate the current test list and allow the sequencer to fetch the next test list spaceba Skip to next test case at Set this flag while a subtest is looping on error and the loop will exit and the subtest will continue by breaking out of the current loop Useful when looping on error Overview of POST 1 7 1 4 DEMON Menu Options 1 8 The DEMON options are useful when troubleshooting the system they are not required in a normal POST run To use the DEMON menus type m see Table 1 2 to interrupt POST while it is running in diag mode The DEMON main menu is shown below 1A gt DEMON 1A gt Select one of the following functions 1A gt 0 System Parameters 1A gt 1 Read Write device 1A gt 2 Software Reset 1A gt 3 NVRAM Management 1A gt 4 Error Reporting 1A gt 5 Analyze Error Logs 1A gt 6 Power Off at Main Breaker 1A gt 7 NVRAM SIMM tests 1A gt r Return to selftest 1A gt Command gt To go to another menu or to select a command from this menu type the number or letter that corresponds to the option all other keys are ignored System Parameters Option Type 0 at the main menu prompt to get
86. iagnosis CPUA Module CPUB Module Test all functional elements of the SPARC Module Read MQH State ID 43 1 Level 1 e Attributes Error is Fatal Read the alternate processor s MQH state array This is done so that the slave processor that calls this test does not rerun JTAG INIT on the board s MOH and cause possible refresh problems Possible Error Messages This module does not check or report errors C_O BW MQH e ID 43 2 e Level 8 Attributes Error Terminates Sequencer Error is Fatal Establish the board configuration for this test SPARCserver 1000 POST User s Guide May 1993 No lll Subtest Possible Error Messages This module does not check or report errors CPU and Cache e ID 43 3 e Level 8 Attributes Test Module Error Terminates Sequencer Test the functionality of the CPU and Ecache on the SPARC module Data Prefetcher Data Cache must be enabled Issue a series of LDDs STDs with Data Prefetcher off then with Data Prefetcher on and compare non prefetched buffers with prefetched buffers The data should be identical SB Stress Issue a series of stores with Store Buffer off then with Store Buffer on and compare the memory data The data should be identical Store Buffer Cacheable Issue 8 cacheable store doubles and check the Store Buffer tags as well as the data Read and check the memory data Store Buffer store load Stall CPU snooping Issue consecutiv
87. ing point unit registers e Read a data pattern into an FPU register e Write FPU register out to memory Compare data in memory to original data e Repeat for all FPU registers e Repeat for several data patterns SPARCserver 1000 POST User s Guide May 1993 No lll Subtest Subtest Possible Error Messages Unexpected trap occurred during FPU operation FPU Double Reg d exp X X obs X SX reg exp obs Single Precision exp X obs X FPU Functional ID 13 1 e Level 8 e Attributes Test Module Initialization Module Test the functionality of the floating point unit Perform the following operation using single precision 3 4 5 24 2 4 5 e Verify that the result is 3 0 e Repeat using double precision Possible Error Messages Unexpected trap occurred during FPU operation FPU Double Reg d exp X X obs X X reg exp obs Single Precision exp X obs X MMU TLB ID 13 1 e Level 17 e Attributes Test Module Subtest Disabled Initialization Module Write read verify all TLB entries using Walking 1s pattern Possible Error Messages unexptd_tlb_msg entry sel exp obs Test Descriptions 2 9 lll No Subtest Subtest 2 10 Instruction Cache Tags ID 13 1 Level 17 e Attributes Test Module Initialization Module Test that the Icache can be flash cleared and that the tags can be addressed uniquely Also check the tag array for d
88. ister Write halfword inverse testdata to word 0 in Lance buffered memory Test Descriptions 2 71 2 72 e Read halfword testdata from Lance RDP register e Compare and print error message if miscompare Lance CSR2 register write write read test e Write 2 to RAP to point to CSR2 register e Testdata 0x1 0x2 0x4 0x4000 0x8000 e Write halfword testdata to Lance RDP register e Write halfword inverse testdata to word 0 in Lance buffered memory e Read halfword testdata from Lance RDP register e Compare and print error message if miscompare e Testdata Oxffff e Write halfword testdata to Lance RDP register e Write halfword inverse testdata to word 0 in Lance buffered memory e Read halfword testdata from Lance RDP register e Compare and print error message if miscompare Lance CSR3 register write write read test e Write 3 to RAP to point to CSR3 register e Testdata 0x1 0x2 0x4 0x4000 0x8000 e Write halfword testdata to Lance RDP register e Write halfword inverse testdata to word 0 in Lance buffered memory e Read halfword testdata from Lance RDP register e Compare and print error message if miscompare e Testdata Oxffff e Write halfword testdata to Lance RDP register e Write halfword inverse testdata to word 0 in Lance buffered memory e Read halfword testdata from Lance RDP register e Compare and print error message if miscompare Possible Error Messages Data Compare Er
89. ith ue error Possible Error Messages No trap on table walk w ue Wrong mmu fsr on table walk w ue Wrong mmu far on table walk w ue Wrong mqh ue error addr reg after table walk w ue Wrong mqh ue error data reg after table walk w ue No trap on table walk w ce Wrong mqh ce error addr reg after table walk w ce Wrong mqh ce error data reg ce after table walk w ce OnBoard IO Verification 0x2D e ID 45 0 Attributes General Purpose e Diagnosis None Test the IO functions of the Lance chip and FAS 236 chip that are on the system board Test Descriptions 2 69 2 70 Subtest Subtest Subtest C_0 BW IOC MOH e ID 45 1 Level 1 Attributes Error Terminates Sequencer Error is Fatal Establish the board configuration for this test Possible Error Messages This module does not check or report errors Check OnBoardIO Cardo e ID 45 2 Level 1 Attributes Test Module Error Terminates Sequencer Check that Slot 0 did not trap when probed Possible Error Messages Board x Card0 not in this configuration Lance Memory e ID 45 3 Level 17 e Attributes Test Module Test the Lance memory buffer e Do 1 2 4 8 byte accesses to entire 32 byte at each address bit e Do marching a5 s forward and backward to entire 128Kbytes Possible Error Messages Lance memory compare error address X expected X observed X SPARCserver 1000 POST User s Guide
90. itialize TOD Delay e ID 124 1 e Level 1 e Attributes Error is Fatal Use the TOD for a timed delay allowing SBus devices to perform self initialization Possible Error Messages This module does not check or report errors TOD Delay e ID 124 1 e Level 1 e Attributes Error is Fatal Use the TOD for a timed delay allowing SBus devices to perform self initialization Possible Error Messages This module does not check or report errors Test Descriptions 2 97 O00 80080 Subtest O00 8000 CO NPB XPT 0x7D e ID 125 0 e Attributes NonProcessor Board Test Diagnosis SBI Test XPTs on non processor boards This test is run by the C_0 system master XPT Read Write e ID 125 1 Level 17 Attributes Test Module e For the first part of the test force parity Set up the SBI control register Do a 6N test Load a new pattern Test with the next pattern First pass write in ascending order Second pass read then write in ascending order Third pass read compare in descending order Move the pattern pointer along Loop for all patterns Restore original SBI control register Test with some even and odd parity patterns Clear the XPT so that there is good parity Possible Error Messages Data Compare Error address X expected X observed X NPB OnBoard IO Verification Ox7E JD 126 0 e Attributes NonProcessor Board Test e Diagnosis None Test the IO functions o
91. ize 1A gt Ecache Tags Test 1B gt Ecache SRAM Test 1A gt Ecache SRAM Test 1B gt Ecache Enable Bed SPARCserver 1000 POST User s Guide May 1993 1B gt Clear CC SRAM 1A gt Ecache Enable 1A gt Clear CC SRAM 1A gt BWO Regs Test 1A gt C_O BW 1A gt BW Registers Test 1A gt Timers and Interrupts Test 1A gt BW Tag RAM 6N Test 1B gt BWO Regs Test 1B gt C_O BW 1B gt BW Registers Test 1B gt Timers and Interrupts Test 1B gt BW Tag RAM 6N Test 1A gt CO MOH Test 1A gt C_O BW MQH 1A gt MOH Registers Test 1A gt MQH Initialization 1A gt Enable ECC 1A gt Memory Test 1A gt x Skip to Next Subtest 1A gt Config Memory Available 1A gt Config Board 512MB Config Total 512MB 1A gt CO IOC Test 1A gt C_O BW IOC 1A gt IOC Registers Test 1A gt IOC XDBus Tags Test 1A gt IOC Sbus Tags Test 1A gt IOC Cache RAM Test 1A gt CO SBI Test 1A gt SBI Initialization 1A gt SBI Registers Test 1A gt SBI Initialization 1A gt SBus Interrupts Test 1A gt CO SBUS Cards Test 1A gt SBI Initialization 1A gt Checking for SBUS cards 1A gt Board 1 Slot 0 occupied 1A gt Board 1 Slot 3 occupied 1A gt CO XDBus Timing Test 1A gt C_0 BW 1A gt Compute XDBus Frequency 1A gt Bus frequency 33 MHz 1A gt TOD Delay Sample POST Output A 3 p 1A gt 1A gt 1A gt 1A gt 1A gt 1A gt 1A gt 1A gt 1A gt 1A gt 1A gt 1A gt
92. l page tables C_0 BW IOC e ID 36 1 e Level 17 Attributes Error Terminates Sequencer Error is Fatal Establish the board configuration for this test Possible Error Messages This module does not check or report errors SPARCserver 1000 POST User s Guide May 1993 No lll Subtest O0e O O00090 XPT Read Write e ID 36 2 Level 17 e Attributes Test Module Test the functionality of the external page tables e For the first part of the test force parity Set up the SBI control register Do a 6N test Load a new pattern Test with the next pattern First pass write in ascending order Second pass read then write in ascending order Third pass read compare in descending order Move the pattern pointer along Loop for all patterns Restore original SBI control register Test with some even and odd parity patterns Clear the XPT so that there is good parity Possible Error Messages Data Compare Error address X expected X observed X CO BW MQOH Consistency 0x25 e ID 37 0 Attributes General Purpose Diagnosis MQHO Set Configuration 0 and test the consistency between BW and main memory Test Descriptions 237 Subtest Subtest C_O BW MQH e ID 37 1 Level 17 Attributes Error Terminates Sequencer Error is Fatal Establish the board configuration for this test Possible Error Messages This module does not check or report errors
93. le Verify Store Buffer tags for address uniqueness and data reliability The test is run with the Store Buffer off Store Buffer Addressing test e Write address ascending e Read and verify e Write address descending e Read and verify Store Buffer RAM data reliability e Write all tags with test pattern e Read each tag and verify data e Loop for all patterns Possible Error Messages Data Compare Error address X expected X X observed X X Store Buffer RAM ID 13 6 e Level 8 e Attributes Test Module Initialization Module Verify Store Buffer SRAMs for address uniqueness and data reliability This test is run with the Store Buffer off Test Descriptions elo 2 14 Subtest Store Buffer Addressing test e Write address ascending e Read and verify e Write address descending e Read and verify Store Buffer RAM data reliability e Write entire RAM with test pattern e Read RAM and verify the data e Loop for all patterns Possible Error Messages Data Compare Error address X expected X X observed X X Store Buffer Functional ID 13 9 Level 8 e Attributes Test Module Initialization Module Test the Store Buffer functions that can be tested while in boot mode with the Ecache turned off Implies only non cacheable space This test currently issues stores to EPROM address space The actual results are obtained from the Store Buffer
94. lity of all IOC ASIC registers using all access sizes allowed The addresses of the IOC registers are in CSR space If any access causes a data access exception or unexpected interrupt the test aborts with a FAIL status Possible Error Messages While testing s register an unexpected trap occurred MFSR X MFAR X Trap Type 2x CC Error X X Unexpected Component ID value address X expected X or X observed SX 6s register failed to return correct data address X expected SX observed X 6s register failed to return correct data expected X X observed X X Floating a bit through s register failed expected observed oA o X X Floating a bit through s register failed expected X X observed X X Test Descriptions 2 91 2292 Subtest Subtest Subtest IOC XDBus Tags e ID 121 4 Level 8 e Attributes Test Module Read write and verify the IOC s XDBus tags Possible Error Messages Data Compare Error address X expected X observed X TOC Sbus Tags e ID 121 5 Level 8 e Attributes Test Module Read write and verify the IOC s SBus tags Possible Error Messages Data Compare Error address X expected X observed X IOC Cache RAM e ID 121 6 Level 8 e Attributes Test Module Read write and verify the IO Cache RAM SPARCserver 1000 POST User s Guide May 1993 No lll O 80
95. ll interrupts except Level 15 Clear all existing interrupt states Establish this board s BW as the target for this SBus s interrupts Verify the CC transaction to the SBI interrupt target register Loop for all Levels SBus has levels 1 through 7 Loop for all slots each board has 4 SBus slots Use diagnostic register to generate SBus interrupt Issue a TAKE and check the state register Issue a GIVE and check the state register Check BW interrupt table Check CC interrupt pending Unmask the interrupt and insure the CPU gets the correct interrupt Do necessary housekeeping Clean up before exiting Possible Error Messages Failed to establish new targer id Board x Address X expected observed ae ol 2X 2X Incorrect Interrupt State Board x Address X expected observed X X ae ol 2 2 Test Descriptions 2 33 2 34 O0e O OO0 O Subtest Subtest Incorrect CC Interrupt Pending Board x Slot x Address X expected observed Incorrect BW Interrupt Table Board x Slot x Address X expected observed SBus Interrupt not delivered to CPU Board x Slot x Level x o Trap Type 2x CO SBUS Cards 0x22 e ID 34 0 Attributes General Purpose e Diagnosis None Probe all sbus slots to see if a sbus card responds SBI Initialization e ID 34 3 e Level 1 Attributes Error Terminates Sequencer Error is Fatal This function ini
96. mit mode with interrupts e First do the Ptimer then do the Ttimer e Set timer to run free e Clear all interrupt registers e Set limit to 100 and see if interrupt is generated e Stall for a few milliseconds e Check the limit bits e Check the interrupt table e Check the interrupt pending e Setup for tick timer e Set timer to free running mode turn off interrupts Test User Timer Mode e Configure the Ptimer for User Timer mode e Make sure it counts Test alarm clock interrupts e First do the Ptimer then do the Ttimer e Set timer to run free e Clear all interrupt registers e Set ND limit to 100 and see if interrupt is generated e Stall for a few milliseconds e Check the limit bits e Check the interrupt table e Check the interupt pending e Setup for tick timer e Set timer to free running mode turn off interrupts Clean up everything e Configure Ptimer for non UT mode e Set timer to run free e Clean up interrupt registers Possible Error Messages Timer Free Running Mode Error Address X start count X end count X Test Descriptions PA lll No Timer Error expected the Limit Bit to be set Address X Data X Interrupt table has incorrect value expected 4X observed 4X Interrupt Pending Register has incorrect value level d expected 4X observed 4X User Timer mode not counting start count X X end count X X Subtest BW Tag RAM 6N I
97. nd on customer defined resource preferences POST selects the optimal system configuration using as many working resources as possible It thus tries to provide a reliable machine configuration that can be used by the OpenBoot firmware POST has two goals Offer the customer a wide platform for applications even if there are hardware failures Facilitate field replacement and factory repair To these ends it records error history information about failed or marginally functional components and also provides field replaceable unit FRU level diagnostic information A detailed log containing information about which tests have passed and which have failed is available after each POST run The FRU level information is useful for both manufacturing and field service 1 1 1 2 Invoking POST 1 2 personnel to determine functional components The more detailed information which is recorded from relevant hardware error registers each time there is a failure helps fault diagnosis in the factory The most important new feature of POST which differentiates it from POST in earlier Sun machines is automatic reconfiguration When POST finds hardware failures it tries to reconfigure the system optimally using as many functional I O components as possible Before you begin running POST make sure you have a SPARCserver 1000 system with a serial cable running from the system board in the lowest numbered slot to a TTY terminal or
98. ng is limited to insuring that register access does not cause a trap and that all error bits are cleared The Group Type registers are read only they are not tested To prevent losing refresh the Refresh Enable bit in the MCSR is never reset When appropriate the test restores the original value it found in the register Test Descriptions 225 2 26 Subtest Possible Error Messages While testing s register an unexpected trap occurred MFSR X MFAR X Trap Type 2x CC Error X X Unexpected Component ID value address X expected X or X observed X 6S register failed to return correct data address X expected SX observed X s register failed to return correct data expected X X observed X ae ol x ae ol Floating a bit through s register failed expected X observed oA le x Floating a bit through s register failed expected X X observed X X Je ol ae o MOH Initialization e ID 30 3 Level 1 e Attributes Error is Fatal Set up the MQH timing registers and control register Timing values loaded depend on the types of SIMMs present Turn on Refresh Enable set Refresh Count Request Delay Possible Error Messages This module does not check or report errors SPARCserver 1000 POST User s Guide May 1993 No lll Subtest Subtest Enable ECC JD 30 4 Level 1 Attributes Error is Fatal Enable ECC checking
99. nsactions are also verified This test is not run unless main memory is accessible Stream Mode and XPT Bypass Insure tags are cleared Set slot configuration registers Clear all error bits SEGA 0 Slot Reset Stream Mode 64 Byte Burst Bypass XPT Clear some memory SBus loopback write data data offset Data should have looped to memory See if any SBI errors were set Verify the memory data Negate the data in memory SBus loopback read the memory a word at a time and check for errors Data should have looped from memory Verify the read data Test Descriptions 2 41 2 42 Consistent Mode and XPT Bypass use the same procedure as above except Consistent Mode is selected and the IOC tags tags are verified for the correct state e Insure tags are cleared e Set slot configuration registers e Clear all error bits e SEGA 0 Slot Reset Stream Mode 64 Byte Burst Bypass XPT e Clear some memory e SBus loopback write data data offset e Check IOC tags for correct state Data should have looped to memory e See if any SBI errors were set e Verify the memory data e Negate the data in memory e SBus loopback read the memory a word at a time and check for errors e Check IOC tags for correct state Data should have looped from memory Possible Error Messages SBI Detected Errors Board x Slot x Status X Slot Config X Bypass Stream Write Failed Slot x expected X observe
100. nsistency between the BW CC IO Cache and main memory e Assign a test address for each board Each board has a cache line in virtual page 0 e Put test data in memory e Initialize the IO chips for loopback operation e Verify that a read will miss and cause an IOC line fill e Check BW CC and IOC tags for correct state e Verify that a read to the same address will hit in the IOC e Check BW CC and IOC tags for correct state e Verify that a write miss will cause an IOC line fill e Check BW CC and IOC tags for correct state e Verify that a write will hit in the IOC and update the IOC data e Check BW CC and IOC tags for correct state e Verify that the IOC is the owner and will reply with a CPU read e Verify that the data became shared e Check BW CC and IOC tags for correct state SPARCserver 1000 POST User s Guide May 1993 No lll Verify that the IOC will flush owned data to memory e A write miss must cause an IOC line fill e Check BW CC and IOC tags for correct state This write will hit in the IOC and update the IOC data e Check BW CC and IOC tags for correct state e Issue a read for address alias flush The IOC must flush the dirty line to memory e Check BW CC and IOC tags for correct state Check IOC flushed data Possible Error Messages Block compare failed load address X data X X store address X data X X Block check error address X expected X observed
101. ock did not update memory address X flush block 1x Flush Block disturbed wrong memory block address X flush block 1x Block Compare Error Source Address X Destination X Byte Count X Cache Data and Memory Data don t agree doubleword 1X cache data X X memory data X X char sparc_enable_err_txt Data with features on not equal to data with features off buffer index x feature off data X X feature on data X X 2 62 SPARCserver 1000 POST User s Guide May 1993 No lll Subtest Subtest MMU PTP Cache Invalidation e ID 43 3 Level 17 e Attributes Test Module Error Terminates Sequencer Verify that the root and level 2 ptp caches are invalidated properly on context switches ctpr switches and so on e Initialize root ptp and 12 ptp caches with valid entries e Do the following write to ctx register write ctpr register flush entire flush context flush region flush segment flush page e In each case verify that the root ptp and 12 ptp caches are invalidated or left alone according to specifications This test issues demap packets writes to TLB flush ASI BWs and MQHs need to be on and demap must be enabled in one MQH It does not need memory Possible Error Messages Wrong root ptp cache valid state Wrong 12 ptp cache valid state MMU Stuff TLB Hit e ID 43 4 e Level 17 Attributes Test Module Error Terminates Sequencer Test
102. on B 4 D DEMON menus 1 8 diag mode 1 3 E early POST tests 2 2 Ecache test 2 18 EPROMS test 2 3 error message 1 4 ErrorLevel B 2 expected error B 5 K Keybd Mouse test 2 7 L LEDs test 2 4 loopback exit 2 81 Index 1 N normal mode 1 2 NPB OnBoard IO Verification test 2 98 NVRAM TOD test 2 8 O OnBoard IO Verification test 2 69 onion skin method B 2 P phases of POST B 3 R replay B 5 S Sequencer B 2 Serial Ports test 2 5 SPARC Module Board Master test 2 51 SPARC Module Board Slave test 2 60 SubTestID B 1 system LEDs 1 3 system reconfiguration 2 111 T TestID B 1 TestLevel B 2 TestLists B 2 TestStatesArray B 2 U unexpected error B 5 user interface commands 1 6 Index 2 SPARCserver 1000 POST User s Guide May 1993 Reader Comments We welcome your comments and suggestions to help improve the SPARCserver 1000 POST User s Guide part number 801 2916 10 Please take time to let us know what you think about this manual The information was well documented and easy to follow Strongly Strongly Not Agree Agree Disagree Disagree Applicable C C u u Comments The information provided in the manuals was complete Strongly Strongly Not Agree Agree Disagree Disagree Applicable C u C u Comments The information I needed was easy to find Strongly Strongly Not Agree Agree Disagree Disagree Applicable Q u C u C Comments The manuals were
103. on the MQH Possible Error Messages This module does not check or report errors Memory e ID 30 5 Level 8 e Attributes Test Module Test all memory on this MQH If a group with memory is not found return FAIL The purpose of the test is to test enough memory to allow the consistency tests to run The memory test functions are loaded into the Icache for speed Short memory test algorithm Clear number of memory faults in current test Load the CC Stream Data register with alternate patterns Now loop through memory writing 64 bytes at a time Check the memory Set up and load the alternate pattern Loop through memory writing 64 bytes at a time Check the memory The permanent ECC handler handles memory errors If the faults exceed 2 return fail Long memory test algorithm e Clear number of memory faults in current test Loop through a set of long patterns e Load stream data register with pattern Fill memory with pattern e Load stream data register with pattern e Read then write pattern e Read pattern write pattern read Test Descriptions 2 27 2 28 Subtest O0e O OOQOOQOQO Subtest Possible Error Messages Memory Compare Failure Addr X Expected X X Observed X X Config Memory Available e ID 30 6 Level 1 e Attributes Error is Fatal Count up the amount of memofy available in the current configuration Possible Error Messages This module does not
104. own alongside the test name A brief description of the test follows along with the test ID number attributes and a diagnosis field showing the possible cause of a problem should a test fail For test LED patterns in this manual white lights O indicate that the LED is OFF and black lights indicate that the LED is ON The description of the test is followed by descriptions for each of the subtests within a test Like tests subtests also show IDs attributes diagnoses and brief descriptions of the functions they perform In addition the algorithm in the form of pseudocode and the error messages for each subtest are also listed Subtests do not have hexadecimal values and their corresponding LED patterns associated with them 2 1 2 2 1 Early POST Tests 2 2 Shortly after power on and before transferring control to the test sequencers see Appendix B POST does a few preliminary tests These tests are basic checks to verify that the CPU and BootBus are working well enough so that POST can begin more comprehensive testing The following tests are very basic if they fail you may or may not see error messages depending on the extent of the failure The first check is to start BIST built in self test on the MXCC ASIC The BIST takes one second to execute If this operation hangs the CPU you see the value 0x01 in the board LED display The next check is to start BIST on the CPU module This BIST take
105. print error message if miscompare Testdata Oxffffffff Write word testdata to ESC DMA Address register Write word inverse testdata to word 0 in Lance buffered memory Read word testdata from ESC DMA Address register Compare and print error message if miscompare SCSI DVMA count register write write read test Testdata 0x1 0x2 0x4 0x40000000 0x80000000 Write word testdata to ESC DMA Count register Write word inverse testdata to word 0 in Lance buffered memory Read word testdata from ESC DMA Count register Compare and print error message if miscompare Testdata Oxffffffff Write word testdata to ESC DMA Count register Write word inverse testdata to word 0 in Lance buffered memory Read word testdata from ESC DMA Count register Compare and print error message if miscompare ESC register back to back write write read read test Testdata 0x1 0x2 0x4 0x40000000 0x80000000 Write word inverse testdata to ESC DMA Address register Write word testdata to ESC DMA Count register Write word inverse testdata to word 0 in Lance buffered memory Read word inverse testdata from ESC DMA Address register Read word testdata from ESC DMA Count register Compare and print error message if miscompare Testdata Oxffffffff Write word inverse testdata to ESC DMA Address register Write word testdata to ESC DMA Count register Write word inverse testdata to word 0 in Lance buffered memory Read word invers
106. register Wait 1uS to allow for internal command synchronization Wait for the bytes to be transferred via DMA control TCZERO Check for timeout Verify the transfered bytes by reading the FIFO register Reset the FAS 236 to release the SCSI bus 2 78 SPARCserver 1000 POST User s Guide May 1993 No lll Possible Error Messages Data Compare Error address X expected X observed X char fas_dvma_xfr_timeout_err_txt Transfer timeout waiting on SCSI DVMA Control register char fas_dvma_read_fifo_err_txt FIFO data compare error char fas_dvma_write_mem_err_txt Memory data compare error Subtest SCSI DVMA Write e ID 45 9 Level 17 e Attributes Test Module Program the FAS and ESC chips to do DVMA write and verify Reset the FAS 236 Send NOP command to FAS after doing reset Set bit 3 Chip Test Mode of the Configuration Register 1 Set bit 0 Target Test Mode of the test register Load the Transfer Count Register with the number of bytes to be transferred Load the ESC SCSI DVMA Count register with the byte count Store the virtual address in ESC SCSI DVMA Address register Store the test data bytes directly into the FIFO register Issue a RECEIVE DATA W DMA command 0xAA into command register Turn on DMA and set direction in ESC SCSI DVMA Control register Wait 1uS to allow for internal command synchronization Wait for the bytes to be transferred via DMA control TCZE
107. ress Address Descending e Write each address with its address as the data e Read and verify each address Cell Disturbance e Write the entire array with a checkerboard bit pattern e Read and verify each address e Reverse the checkerboard pattern and repeat Data Reliability e Write the tag array with standard test patterns e Read and verify the data Test Descriptions 2 11 lll No Subtest 2 12 Possible Error Messages Data Compare Error address X expected X X observed X X Data Cache Ram ID 13 4 Level 8 e Attributes Test Module Initialization Module Test address uniqueness and data reliability of the CPU internal data cache RAMs Address Ascending e Write each address with its address as the data e Read and verify each address Address Descending e Write each address with its address as the data e Read and verify each address Cell Disturbance e Write the entire cache with a checkerboard bit pattern e Read and verify each address e Reverse the checkerboard pattern and repeat Data Reliability e Write the cache with standard test patterns e Read and verify the data Possible Error Messages Data Compare Error address X expected X X observed X X SPARCserver 1000 POST User s Guide May 1993 No lll Subtest Subtest Store Buffer Tags ID 13 5 Level 8 e Attributes Test Module Initialization Modu
108. rminates Sequencer Error is Fatal Establish the board configuration for this test Possible Error Messages This module does not check or report errors CPU and Cache e ID 41 2 Level 8 Attributes Test Module Error Terminates Sequencer Test the functionality of the CPU and Ecache on the SPARC module e Data Prefetcher Data Cache must be enabled Issue a series of LDDs STDs with Data Prefetcher off then with Data Prefetcher on and compare non prefetched buffers with prefetched buffers The data should be identical e SB Stress Issue a series of stores with Store Buffer off then with Store Buffer on and compare the memory data The data should be identical e Store Buffer Cacheable Issue 8 cacheable store doubles and check the Store Buffer tags as well as the data Read and check the memory data e Store Buffer store load Stall CPU snooping Issue consecutive store load pairs to insure that the loads are stalled until the stores complete Test Descriptions 2 51 e Store Buffer Access Issue stores of all sizes and on all boundaries and check the memory data CC Prefetch Verify the CC prefetch logic When prefetch is enabled a prefetch should occur under the following conditions when the next sequential subblock of the one just fetched is not valid and contained within the same line then prefetch Burst Read Miss Subblock n Prefetch Subblock n 1 Note that prefetch is only issued for burst reads the D
109. ror address X expected 4X observed 4X char lance_rap_wr_rd_txt RAP write write read miscompare char lance_csr0_not_cleared_txt CSRO register not cleared when STOP bit set SPARCserver 1000 POST User s Guide May 1993 No lll Subtest char lance_csrl_stop_txt CS char lance_csr2_stop_txt CS char lance_csr3_stop_txt CS Rl write write read miscompare when CSRO STOP bit set R2 write write read miscompare when CSRO STOP bit set R3 write write read miscompare when CSRO STOP bit set char lance_rdp_rap_wr_rd_b2b_txt J RD P RAP back to back write write read read miscompare Lance Local Loopback ID 45 5 Level 17 e Attributes Test Module Test the Lance transmit and receive functions using an internal loopback Initialize the init block transmit receive pointers Issue stop to Lance chip and verify it stopped Set to internal loopback Initialize the init block parameters Initialize the receive block parameters Initialize the transmit block parameters Load CSR1 2 with the base of the init structure Start timeout loop waiting for Lance chip to init Set up transmit and receive buffer data 32 byte incrementing pattern Load buffer for transmit and clear receive buffer Set up destination address in transmit block Set up source address in transmit block Send transmit command Start timeout loop waiting for transmit confirmation
110. roubleshooting the system Toggle Loop On Error flag Set this flag and the current test will loop on an error till the flag is reset If the flag is not set the current test will try and continue execution once an error occurs Use either key to display this command summary Toggle Loop On Subtest flag Press this key to cause the test sequencer to loop on the current subtest Can be an effective scope loop Go to DEMON menus Set this flag to interrupt the POST run call a DEMON and display the DEMON menu Skip to next subtest Set this flag to cause the current subtest to exit and return to the sequencer The next subtest in the list is then dispatched Useful for skipping long subtests Toggle Print All Errors flag Set this flag to allow POST to display all the errors within each test Reset the flag if only the first error in each test is to be displayed Default is to print one error per subtest 1 6 SPARCserver 1000 POST User s Guide May 1993 lll Table 1 2 User Interface Key Commands Continued Key Action s Toggle Stop POST flag Set this flag to allow POST to stop after it finishes execution and before it transfers control to the OpenBoot firmware The DEMON menu is displayed t Toggle Timestamp flag Set this flag to allow the sequencer to print a timestamp prior to dispatching each subtest Uses TOD clock v Toggle Verbose Print Mode flag Set t
111. rough level3 ptes Test Descriptions 2 67 2 68 Subtest Protect error test e Initialize pte in memory with acc 2 0 0 through 7 e Do access ld st user super data ld st user super instr e If there is an access error verify that you got trap 0x9 and the MMU sync error register is updated correctly If there is no access error verify MMU error register is not updated Repeat for levell through level3 ptes Possible Error Messages No trap on illegal permissions access Wrong mmu fsr on twalk protect error Wrong mmu far on twalk protect error Got unexpected trap Got mfsr fault valid MMU Table Walk With Parity Error e ID 43 9 e Level 17 Attributes Test Module Error Terminates Sequencer Do table walk with parity error e Make pte cacheable in Ecache e Do table walk without parity error e Repeat for different access types e Repeat for level 1 3 ptes e Repeat with parity error Possible Error Messages No trap on twalk parity error Wrong mmu fsr on twalk parity error Wrong mmu far on twalk parity error SPARCserver 1000 POST User s Guide May 1993 No lll Subtest OO0O0O 0000 MMU Table Walk With ECC Error e ID 43 10 Level 17 Attributes Test Module Error Terminates Sequencer Do table walk with ECC error e ptes not cacheable in Ecache e Do table walk with ce error e Repeat for different access types e Repeat for level 1 3 ptes e Repeat w
112. rror Messages Wrong root pointer on 10 probe Wrong 11 entry on 11 probe Wrong root ptp cache Wrong 12 entry on 12 probe Wrong 13 entry on 13 probe Wrong 12 ptp cache Wrong 12 vaddr cache Wrong 13 entry on 13 probe Ref bit is not set Subtest MMU Flush e ID 41 6 Level 17 Attributes Test Module Error Terminates Sequencer Test MMU TLB flush operation Level0 context e Initialize TLBs with unique ctx tags and same vaddr 0 e ctx flush with different ctxs and verify correct TLBs are invalidated after each flush Levell segment e Initialize TLBs with unique tags and same ctx 0 e seg flush with different index1 and verify correct TLBs are invalidated after each flush Level2 region e Initialize TLBs with unique tags and same ctx 0 e reg flush with different index2 and verify correct TLBs are invalidated after each flush 2 56 SPARCserver 1000 POST User s Guide May 1993 No lll Subtest Level3 page e Initialize TLBs with unique tags and same ctx 0 e pag flush with different index3 and verify correct TLBs are invalidated after each flush Level 4 entire e Initialize TLBs with unique tags and ctx e entire flush and verify all TLBs are invalidated This test needs to enable MMU demaps Possible Error Messages Wrong tlb after 10 flush Wrong tlb after 11 flush Wrong tlb after 12 flush Wrong tlb after 13 flush Wrong tlb after flush entire MMU
113. s are always executed at a particular level The higher the level the greater the number of tests that are run and the more thorough the tests Entry Points POST has three entry points corresponding to the power on reset POR reboot RBT and post error ERR cases e When entered at POR POST runs at one of two levels determined by whether the machine s DIAG switch is set or not When entered at RBT POST can be invoked at any level under program control When entered at ERR POST tries to recover from the unexpected error it encountered during the last entry point invocation of POST When POST is invoked using an entry point it executes as a multi thread program the number of threads are equal to the number of processors in the system Each processor keeps a record of where it is in its overall sequence of tests If an error occurs this record can tell POST or a user what a processor was attempting to do just before the error occurred Call back Routines POST also implements a number of call back routines used by the OpenBoot firmware and higher level programs A processor does not keep track of where it is in the overall sequence of its tests when executing a call back routine As a result unexpected asynchronous errors within call back routines are not handled by the ERR entry point SPARCserver 1000 POST User s Guide May 1993 Arbitration System ASIC Backplane Subsystem Bank BARB BBC BBC2
114. s one second to execute If this operation hangs the CPU you see the value 0x02 in the board LED display Note If POST is running in diag mode it displays the resultant BIST signatures e POST now does a basic BootBus NVRAM read write test POST tests 8 bytes of NVRAM at the NVRAM base address 8 If it detects a failure POST attempts to print a message on TTYA then falls into and remains in a write read scope loop for as long as the failure persists If this test fails you see the value 0x04 in the LEDs This is a non destructive test POST saves the 8 bytes prior to the test and later restores them Finally POST does a basic BootBus SRAM read write test POST tests 8 bytes of SRAM at the SRAM base address 8 If a failure is detected POST attempts to print a message on TTYA then falls into and remains in a write read scope loop for as long as the failure persists If this test fails you see the value 0x05 in the LEDs This is a non destructive test POST saves the 8 bytes prior to the test and later restores them SPARCserver 1000 POST User s Guide May 1993 No lll 2 2 Board Level Testing OOOO 0880 Subtest The following series of tests verify all functional elements of CPU A CPU B the System Board components Bootbus BW s IOC s SBI MQH s and all memory present on this board These tests are run while all System Boards are in XDBus loopback EPROMs 0x06 e ID 6 0 e Attributes CO Manda
115. scriptions 2 19 2 20 Subtest Subtest e Write pass write alternate patterns Loop through the cache comparing alternate patterns e Check for parity error e Check for miscompares e Repeat test with mixed parity patterns Possible Error Messages Viking Parity Error address X expected X X observed X X Data XOR X X Part U Q Ecache Enable e ID 14 5 Level 1 e Attributes Error is Fatal Enable the external cache From this point on the cache remains enabled Possible Error Messages This module does not check or report errors Clear CC SRAM e ID 14 4 Level 1 e Attributes Error is Fatal Clear the external cache SRAM This also insures that good parity is established for the SRAM Possible Error Messages This module does not check or report errors SPARCserver 1000 POST User s Guide May 1993 No lll OO0O0 0000 Subtest Subtest BWO Regs 0x12 e ID 18 0 Attributes C0 Mandatory Test e Diagnosis BWAQO BWBO Test the registers and tags on Bus Watcher 0 C_O BW e ID 18 1 Level 1 e Attributes Initialization Module Error is Fatal Establish the board configuration for this test Possible Error Messages This module does not check or report errors BW Registers ID 18 2 Level 8 e Attributes Test Module Initialization Module Test the read and write accessibility of all BW ASIC registers using
116. sts and Sequencers Tests are grouped into ordered sequences called TestLists POST executes in several phases and each phase of POST has its own TestList Each TestList has its own Sequencer which executes each test in the TestList systematically The Sequencer records the status of the current test in a global structure called the TestStatesArray This table driven structure allows tests to be added or removed easily while simplifying control flow B 1 3 Test Levels and Error Levels Whenever a processor executes POST in normal mode it does so at a given Level which is an 8 bit number The higher the level the greater the number of tests and the more exhaustive the tests Every test is assigned a TestLevel and a given test can run only if its level is at or below the current level of POST When POST executes in error mode it uses the ErrorLevel variable instead of the Level variable used in normal mode This variable allows the selection of specific initialization tests that are executed when POST encounters unexpected errors B 1 4 Test Design Tests are designed and organized on the following principles Each component should test itself as much as possible Each component should be tested before it is used A functional component must then be added to a pool of other working components Two components capable of testing themselves must be allowed to interact only after exercising that capability and their interaction m
117. t OA gt OA gt OA gt OA gt OA gt OA gt Bus Ring s Ring bico bicl bic2 bic3 barb H 0 1 30ADA07D 30ADA07D 30ADA07D 30ADA07D 20AD907D 1 1 30ADA07D 30ADA07D 30ADA07D 30ADA07D 20AD907D 2 1 30ADA07D 30ADA07D 30ADA07D 30ADA07D 20AD907D Processor A Ring s H Ring cpuA mxccA bwA H 0 2 0000402F 0000302F 10D3907D 1 2 0000402F 0000302F 10D3907D 2 2 0000402F 0000302F 10D3907D 4 H Memory Ring s 4 H Ring mqh 4 H 0 3 10D8607D 1 3 20D8607D 2 3 10D8607D H IO Ring s H Ring sbi 16c H 0 4 20ADE07D 10ADD07D 1 4 20ADE07D 10ADD07D 2 4 20ADE07D 10ADD07D Processor B Ring s Ring cpuB mxccB bwB 0 5 0000402F 0000302F 10D3907D 1 5 FFFFFFFE FFFFFFFF FFFFFFFE 2p FFFFFFFE FFFFFFFF FFFFFFFE 4 t OA gt Hit any key to continue 0a gt Overview of POST 1 17 System Parameters OA gt Select one of the following functions OA gt Board 0 SIMM Map OA gt xor Set POST Level OA gt Paley Dump Device Table OA gt 2 Display System OA gt x3 Dump Board Registers OA gt 4a Dump Component IDs OA gt 5 Clear Error Logs OA gt 6 Display Simms OA gt 1g Scrub Main Memory OA gt Mee Return Command gt 6 QA gt Which Board
118. t end of a POST run The eight yellow LEDs e Output test ID numbers during a POST run e Indicate boards with failed parts at end of POST e Are always lit on non processor boards The Boot Master constantly runs a Walking 1s pattern on the yellow LEDs 1 2 2 Error Messages In both normal and diag modes error messages are sent to the TTY port and are displayed on any terminal that is connected to that port The ID of the failing test is also displayed in the eight LEDs on the edge of the system board See Chapter 2 Test Descriptions for test LED patterns The general format for a POST error message is as follows bp gt TEST STATUS test_name subtest_name ID LED bp gt Description of Error Address 0x X Data 0x X Table 1 1 explains what each field in the error message means Table 1 1 Error Message Fields Field Description b System board number p Processor A or B TEST_STATUS Status of the test pass or fail test_name Name of the test subtest_name Name of the subtest ID Unique test and subtest id number LED Value hex of the LED display for the test SPARCserver 1000 POST User s Guide May 1993 lll Error messages also show a line explaining the failure and display information from relevant registers Samples of error messages displayed by POST are shown below The first example shows that the test BWO Regs has failed
119. testdata from FAS configuration register 2 Compare and print error message if miscompare testdata Oxff Write byte testdata to FAS configuration register 2 Write byte inverse testdata to byte 0 in Lance buffered memory Read byte testdata from FAS configuration register 2 Compare and print error message if miscompare FAS configuration register 3 write write read test For testdata 0x1 0x2 0x4 0x40 0x80 Write byte testdata to FAS configuration register 3 Write byte inverse testdata to byte 0 in Lance buffered memory Read byte testdata from FAS configuration register 3 Compare and print error message if miscompare testdata Oxff Write byte testdata to FAS configuration register 3 Write byte inverse testdata to byte 0 in Lance buffered memory Read byte testdata from FAS configuration register 3 Compare and print error message if miscompare FAS configuration register 1 2 back to back write write read read test For testdata 0x1 0x2 0x4 0x40 0x80 Write byte inverse testdata to FAS configuration register 1 Write byte testdata to FAS configuration register 2 Write byte inverse testdata to byte 0 in Lance buffered memory Read byte inverse testdata from FAS configuration register 1 Read byte testdata from FAS configuration register 2 Compare and print error message if miscompare testdata Oxff Write byte inverse testdata to FAS configuration register 1 Write byte testdat
120. the interrupt and insure the CPU gets the correct interrupt e Do necessary housekeeping e Clean up before exiting Possible Error Messages Failed to establish new targer id Board x Address X expected observed Incorrect Interrupt State Board x Address X expected observed Test Descriptions 2 95 2 96 O00 80080 Subtest Subtest Incorrect CC Interrupt Pending Board x Slot x Address X expected observed Incorrect BW Interrupt Table Board x Slot x Address X expected observed SBus Interrupt not delivered to CPU Board x Slot x Level x o Trap Type 2x CO NPB SBUS Cards 0x7B e ID 123 0 Attributes NonProcessor Board Test e Diagnosis None Probe each slot on this board to see if a card responds SBI Initialization e ID 123 3 e Level 1 Attributes Error Terminates Sequencer Error is Fatal Initialize all SBI registers to the default values Possible Error Messages This module does not check or report errors Checking for SBUS cards ID 123 5 Level 1 e Attributes Error is Fatal Check each slot to see if a card responds SPARCserver 1000 POST User s Guide May 1993 No lll O 88000 Subtest Subtest Possible Error Messages This module does not check or report errors CO NPB Delay 0x7C e ID 124 0 Attributes NonProcessor Board Test e Diagnosis None Allow the SBus cards time to self in
121. tializes all SBI Registers to the default values Possible Error Messages This module does not check or report errors Checking for SBUS cards ID 34 5 Level 1 e Attributes Error is Fatal Check each slot to see if a card responds SPARCserver 1000 POST User s Guide May 1993 No lll O0e O O0e Subtest Subtest Possible Error Messages This module does not check or report errors CO XDBus Timing 0x23 e ID 35 0 Attributes General Purpose e Diagnosis BootBus Using the TOD compute the system crystal frequency C_0 BW JD 35 1 Level 1 Attributes Error Terminates Sequencer Error is Fatal Establish the board configuration for this test Possible Error Messages This module does not check or report errors Compute XDBus Frequency e ID 35 1 e Level 1 e Attributes Error Terminates Sequencer Error is Fatal Using the TOD compute the System crystal frequency to the nearest Mhz Possible Error Messages This module does not check or report errors Test Descriptions 2 35 Subtest O0e O O 00O0O Subtest TOD Delay e ID 35 1 Level 17 e Attributes Error is Fatal Use the TOD for a timed delay allowing sbus devices to perform self initialization Possible Error Messages This module does not check or report errors CO XPT 0x24 e ID 36 0 Attributes General Purpose Diagnosis SBI Set Configuration 0 and test the IO externa
122. to the System Parameters sub menu This sub menu has several useful features for debugging and troubleshooting POST problems You can view system reports check component IDs clear error logs and dump system board registers SPARCserver 1000 POST User s Guide May 1993 lll Read Write Device Option Type 1 at the main menu prompt to get to the Read Write device sub menu This sub menu allows you to read and write using ASIs address space identifiers Most of the SPARCserver 1000 ASICs can be accessed in this way To use this menu you must have detailed knowledge of how system physical addresses are assigned to the ASICs Software Reset Option The Software Reset DEMON option does not have a menu When you type 2 at the main menu prompt POST issues a software reset to the BootBus reset register The system is reset and POST returns to the DEMON menu NVRAM Management Option Type 3 at the main menu prompt to get to the NVRAM Management sub menu This sub menu is used to manage the memory SIMM test results in BootBus NVRAM It allows you to view and erase the data Error Reporting Option Type 4 at the main menu prompt to get to the Error Reporting sub menu This sub menu is used to print out data saved on the last system watchdog reset The sub menu does not allow you to dump data from boards that are not present If the menu is not used at end of POST only data from the local board can be dumped The d
123. tory Test e Diagnosis BootBus Test the BootBus EPROM EPROM path e ID 6 1 Level 17 e Attributes Test Module Initialization Module Fetch previously stored data from the EPROM and verify that the correct byte halfword and word data gets fetched e Test byte access e Test halfword access e Test word access e Test doubleword access Possible Error Messages Data Compare Error address X expected X observed X Test Descriptions 23 2 4 Subtest OOOO O000 Subtest EPROM checksum ID 6 2 Level 17 e Attributes Test Module Initialization Module Compute a checksum for all addresses of the PROM except the last two bytes of each PROM Read the last two bytes and compare the calculated value with the observed one If an error occurs a message indicates the failing byte Possible Error Messages EPROM d checksum error exp 0x X obs 0x X LEDs 0x08 JD 8 0 e Attributes CO Useful Test e Diagnosis BootBus Test the BootBus LED Register WALK LED e ID 8 1 Level 8 e Attributes Test Module Walk 1s through the LED register e Clear all LEDs e Sequentially light up LEDs from right to left or bottom to top Possible Error Messages This test does not report any errors SPARCserver 1000 POST User s Guide May 1993 No lll OOOO 0000 Subtest Subtest Serial Ports 0x09 e JD 9 0 e Attributes CO Useful Test e Diagnosis
124. ts that failed POST e The memory list The failed memory SIMM group listing These are automatically cleared by POST at power on reset A list of failed memory SIMM pages The list is cleared during a power on reset The System Watchdog error log for each board This error log is saved across power on resets and the log can even be examined if the board is returned to a repair depot A processor can encounter two types of errors expected and unexpected during any phase of POST An expected error is defined as a test failure in which the processor s control flow is not forcibly altered In such a case the Sequencer marks the test as having failed and proceeds to the next test An unexpected error is defined as a failure in which the processor gets reset and hardware forcibly transfers control to location 0xFFO000000 In the case of an unexpected error the processor runs in a special error mode In this mode the Sequencer for each phase traverses its list of tests as before but executes only certain initialization subtests in a process called replay When the processor reaches the test that generated the unexpected failure it marks this test as having failed leaves error mode and proceeds with the normal execution sequence POST Design Concepts B 5 B B 4 Running POST B 6 You can invoke POST in two ways by using entry points and by using call back routines When you use an entry point to invoke POST test
125. ultiprocessor arbitration system The SPARCserver 1000 card cage has 3 system board slots A SPARCserver 1000 system board has four SBus card slots System clocks are generated on the control board The control board generates system clocks and is part of the multiprocessor arbitration system The control board is located outside the card cage The I O Cache IOC ASIC on the system board controls movement of data to and from the SBus card slots The key switch located behind the front panel controls the AC supplies and the modes of system operation System Cabinet LED indicators are on the front panel of the system cabinet Ideally the left and right LEDs should be on and the middle LED should be off however the system can still run reliably if all three LEDs are on Table G 1 Front Panel LED System Status LED Position Condition Left green On DC power supply is receiving AC current Middle yellow On first 60 seconds of AC power self tests are running Off after self tests end no hardware failures On after self tests end hardware failure was detected Right green Off first 60 seconds of AC power self tests are running On after self tests end system is running Off after self tests end system cannot run repair is needed Glossary 3 MOH MXCC NVRAM NVSIMM Power on Position Reset Switch SBI SBus Card Secure Position Glossary 4 System Board
126. us cards provide external interfaces and optional features to the system There are four SBus connectors on a SPARCserver 1000 system board This is one of four positions on the system key switch In this position the reset switch is disabled and the Stop A keyboard combination is disabled SPARCserver 1000 POST User s Guide May 1993 SIMM There are several types of single in line memory modules SIMMs SIMMs are socketed on the system board for easy replacement TLB The SuperSPARC chip translation buffer TODC Time of Day Clock TODC contains the system date and time Every system board has a TODC but only the TODC on the master board is used XDBus The XDBus is the SPARCserver 1000 s system bus Glossary 5 Glossary 6 SPARCserver 1000 POST User s Guide May 1993 Index B Basic CPU test 2 8 board LEDs 1 4 Bus Ring test 2 81 BWO Regs test 2 21 C C0 BP Check test 2 82 CO BW IOC Consistency test 2 45 C0 BW MQH Consistency test 2 37 CO configuration B 4 CO Exit LB test 2 83 CO IOC test 2 28 C0 IOC MQH Consistency test 2 40 CO MQH test 2 25 CO NPB Delay test 2 97 CO NPB IO Ring test 2 89 CO NPB IO test 2 90 CO NPB Loopback Exit test 2 84 CO NPB MQH test 2 85 CO NPB SBI test 2 93 CO NPB SBUS Cards test 2 96 CO NPB XPT test 2 98 CO SBI test 2 31 CO SBUS Cards test 2 34 CO XDBus Timing test 2 35 CO XPT test 2 36 C1 configuration B 4 C2 configurati
127. ust be controlled e As many tests as possible should deal with the normal case tests for handling exceptions should be minimal because they are used infrequently and are hard to debug In the SPARCcenter 2000 and the SPARCserver 1000 system the processor is the only component capable of testing itself as well as other components Thus testing begins at the processor Using the onion skin method the tests work their way outward from the processor collecting a group of tested and functional components SPARCserver 1000 POST User s Guide May 1993 Ss lll B 2 Phases of POST POST execution in a SPARCserver 1000 system takes place in five phases Loopback Exit Reconfiguration Board Level Testing System Masters Selection System Level Testing Each phase has its own TestList and Sequencer A Sequencer traverses its TestList thereby determining the order in which tests are executed POST is a multiprocessor program there are as many threads of control as there are processors in the system A processor enters POST after a reset and leaves POST to hand control to the OpenBoot firmware once the machine has been tested and successfully configured While POST is running processors synchronize with each other at various points to coordinate testing and reconfiguration The overall flow of control for POST is shown in the following diagram Board 0 Board Level Testing Board 1 Board Level Testing Loopback
128. vel OA gt Ay Dump Device Table OA gt yay Display System OA gt 3 Dump Board Registers OA gt 4a Dump Component IDs OA gt eo Clear Error Logs OA gt 6 Display Simms OA gt brad Scrub Main Memory OA gt SET Return Command gt 2 0a gt WARNING Board 2 has failed POST 0a gt 0 failed 1 passed blank untested unavailable sbus l card present 0 card not present x failed OA gt OA gt Slot cpuA bw0 cpuB bw0 bb ioc0 sbi mqh0 mem sbus xd0 OA gt OA gt o0 1 1 1 Hb 1 1 1 1 64 0001 1 OA gt 1 1 1 1 1 1 1 512 1001 1 OA gt 2 0 0 1 1 1 128 0001 1 OA gt OA gt Overview of POST 1 11 lll 0A gt Memory Group Status O failed 1 passed m simm missing c simm mismatch blank unpopulated unused Command gt 3 OA gt Which Board 0 OA gt Probing E0000000 OA gt H 0A gt Slot gO gl ga g3 OA gt oa gt o0 1 1 OA gt 1 E oa 1 1 1 OA gt 2 1 a 1 ak OA gt OA gt Hit any key to continue OA gt System Parameters OA gt Select one of the following functions OA gt OF Set POST Level OA gt Ay Dump Device Table OA gt y2 Display System OA gt 3 Dump Board Registers OA gt 4a Dump Component IDs OA gt 15 Clear Error Logs OA gt 6 Display Simms OA gt 7 Scrub Main Memory OA gt
129. vel 1 e Attributes Test Module A non processor board has been detected Note its presence so that the test sequencer will dispatch tests to test it Possible Error Messages This module does not check or report errors CO NPB MOH 0x77 e ID 119 0 Attributes NonProcessor Board Test Diagnosis MQHO Test MQHs on non processor boards This test is run by the C_0 system master Check BDA e ID 119 1 Level 1 Attributes Error Terminates Sequencer Error is Fatal Insure that the part to be tested next has not already failed in POST Possible Error Messages This module does not check or report errors C_O NPB MQH e ID 119 2 Level 1 Attributes Error Terminates Sequencer Error is Fatal Establish the board configuration for this test Test Descriptions 2 85 2 86 Subtest Possible Error Messages This module does not check or report errors MQH Registers e ID 119 3 e Level 8 Attributes Test Module Error Terminates Sequencer Test the read and write accessibility of the MQH ASIC registers using all access sizes allowed The addresses of the MQH registers are in CSR space If any access causes a data access exception or unexpected interrupt the test aborts with a FAIL status The ECC Error registers are read only Testing is limited to insuring that register access does not cause a trap and that all error bits are cleared The Group Type registers are read only they are

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