Home

KT0801

1. SUPPLY CURRENT SUPPLY CURRENT vs 10 FREE AIR TEMPERATURE SUPPLY VOLTAGE 10 Vpp 5V Mode BTL Mode BTL 9 SHUTDOWN Vpp SHUTDOWN Vpp 8 lt E 7 5 6 8 5 gt 5 4 2 3 a 2 1 0 0 1 40 25 10 5 20 35 50 65 80 95 110 125 0 05 1 15 2 25 3 35 4 45 5 55 TA Free Air Temperature C Vpp Supply Voltage V Figure 13 Figure 14 SUPPLY CURRENT SUPPLY CURRENT vs SUPPLY VOLTAGE SUPPLY VOLTAGE 450 400 350 300 gt 250 5 S 200 150 100 50 4 0 0 05 1 15 2 25 3 35 4 45 5 5 5 005 1 15 2 25 3 35 4 45 5 Vpp Supply Voltage V Vpp Supply Voltage V Figure 15 Figure 16 49 5 INSTRUMENTS www ti com Pp Power Dissipation PER CHANNEL W Po Output Power W TPA6011A4 SLOS392 FEBRUARY 2002 TYPICAL CHARACTERISTICS POWER DISSIPATION PER CHANNEL vs OUTPUT POWER Pp Power Dissipation PER CHANNEL mW 0 0 0 2 04 06 08 1 1 2 14 16 18 2 Output Power W Figure 17 OUTPUT POWER vs LOAD RESISTANCE Vpp 5 V THD N 1 Gain 20 dB BTL Crosstalk dB 0 8 16 24 32 40 48 56 64 Load Resistance 0 Figure 19 35 TEXAS POWER DISSIPATION
2. 1uF VCC5V 5VAUDIO 12V_AMP 125 FB30R 10805 i 132 C133 0 tuF 2 220 16 EC6 0 2 5 0 tuF us 126 08 7 AUDIO AV1 L gt een 14 8 42 4 1 08 YO E 7 AUDIO 1 AUDIO AN n ___ 4 SAUDOLIN 1 0603 5J m1 M AUDIO R IN GND GND 11 c97 4 GND GND c98 220uE 16V IX3 INL OUTL OUT L aj he 0 1 EC6 0 2 5 99 100 101 6 15 6 13 R86 1K AUDIO L IN C102 220uF 16V TroopF NH X OUT 4 gt vAROUT R OUTR am 6 OUT R VEE R87 1K AUDIO R IN C103 2 Nie GND vss v_our H3 T INR MUTE lt m SVR STBY R128 R90 CD40528 Io Um 104 6105 C106 SL7496L DGND 24K T 220uFH6V DGND EC6 0 2 5 R99 L CA 10K bi TV A a DGND L 1 AV R94 300K DGND 1 3 VOLUME c107 1 AUDIO_AV1_L DGND AV 5 4 gt lu n 6 zT 31 8 RTIA lt lt AUDIO R IN A 10 HP DET gt 12 lt lt AUDIO 1 IN Dou 12 VCC12V R123 T PAD
3. 20 100 1k 10k 20k 20 100 1k 10k 20k f Frequency Hz f Frequency Hz Figure 23 Figure 24 49 5 INSTRUMENTS www ti com TYPICAL CHARACTERISTICS INPUT IMPEDANCE vs BTL GAIN 90 80 70 F o 60 S 50 40 5 30 N 20 10 0 40 30 4 20 10 0 10 BTL Gain dB Figure 25 OUTPUT NOISE VOLTAGE vs FREQUENCY 180 Vpp 5V 160 BW 22 Hz to 22 kHz RL 80 22120 5 S 9 100 o o 80 5 60 5 e 40 20 0 10 100 1k 10k 20k f Frequency Hz Figure 26 4 5 INSTRUMENTS www ti com TPA6011A4 SLOS392 FEBRUARY 2002 15 TPA6011A4 SLOS392 FEBRUARY 2002 APPLICATION INFORMATION selection of components Figure 27 and Figure 28 are schematic diagrams of typical notebook computer application circuits Right Y Speaker DD 100 kQ Cs ROUT mop 1kQ Power Supply PVpp Ci Right HP Audio Source In From DAC Right Line M or Audio Source RLINEIN Potentiometer gt DC Voltage Cs O Headphones Ci L C BvP
4. Y Seating Plane 1 20 MAX ats z 0 10 4 0 PINS DIM A MAX A MIN 4073225 F 10 98 NOTES A Alllinear dimensions are in millimeters This drawing is subject to change without notice Body dimensions do not include mold flash or protrusions The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane This pad is electrically and thermally connected to the backside of the die and possibly selected leads Falls within JEDEC MO 153 om m PowerPAD is a trademark of Texas Instruments 8 TEXAS INSTRUMENTS 32 www ti com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warra
5. Xtal1 Xtal2 KTAT0801 Block Diagram XTAL Left In PGA ADC Pre Emph Ee Y gt Digital MPX KTM proprietary p Frequency Synthesizer amp FM modulator Right In PGA ADC Pre Emph i Channel Selector SDA 2 SCL Power Control Amp Register Bandgap amp Reference Calibration RF Out Figure 1 KT0801 System Diagram General Description The KT Micro KT0801 Monolithic Digital FM Transmitter is designed to process high fidelity stereo audio signal and transmit modulated FM signal over a short range The modulated stereo FM signal can be intercepted and played back using any FM radio worldwide The KT0801 features dual 20 bit AX audio ADCs high fidelity digital stereo audio processor and a fully integrated radio frequency RF transmitter An on chip low drop out regulator LDO allows the chip to be integrated in a wide range of low voltage battery operated systems with power supply ranging from 1 6V to 3 6V The 0801 is configured as slave and programmed through the industry standard 2 wire MCU interface Thanks to its high integration level the KT0801 is mounted in a generic 24 pin 4x4 QFN package and only requires a single low voltage supply and a small form factor crystal 7 6MHz or 15 2MHz or an external clock to operate No external tuning is required that makes design in effort minimum KT
6. VCC5V ut L1 FB600R 12VDC AOZ1041 L2 6 8uH 3A T 11206 T 1 vin EX CR53 1 D7 Ror EN SS14 NC Schottky Diode 2 DP __ 2 100 25 V DS R4 T 4100u 25V EC6 0 2 5 i R10 EC6 0 2 5 inF lt 47K 27K MTOuFAOV R6 Haon FB 10K gt place close to 1013 IGNDP KEY VCC OR KEY_ADC RR3 100R LED 1 LED 2 LED 3 LED DAC ro LED 4 LED CL RK10 1008 KEY VCC 1 2 3 4 5 6 74 8 9 o g 9 109 10u NC 74HC164 CN4P FPC KEY_VCC KEY ADC 7 g g OANDARWN 7P FPC VCC3 3V L0805 CF1 2 VIO 10uF 6 1uF 0 1uF EC5 0 2 0 CF4 YF1 CF5 11 30441 CF6 DNS 0 1uF i CF7 0 1uF AUDIO_L_IN gt A 100 CF8 0 1uF AUDIO R IN REZ A 100 E 15pF 7 6MHZ 15pF FMVDD IOVDD AVDD VCM INPUT L AVSS INPUT FM SCL RF3 FM SDA RF4 DVDD AVDD FMVDDRFVDD CF9 CF10 CF11 CF12 10uF D 1uE O0 TuF 5 0 2 0 KI2CSCL 3 I2CSDA 3 J1 RCA JACK PWR 12V IN 12V IN gt gt AV1_IN PWR 12V IN AV1 R IN AV1 L IN AD R OUT AD L OUT AD L OUT AD R OUT VIN L3 15
7. HIGH IMPEDANCE Programmable Microelectronics Corp 19 Issue Date September 2005 Rev 1 0 m FLASH MStar PS25LV512 010 SECTOR ERASE Timing CE 0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 3 BYTE ADDRESS INSTRUCTION 1101 01119 Y 21 Xe X 1 HIGH IMPEDANCE 50 BLOCK ERASE Timing ce N 0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 3 BYTE ADDRESS 4 v Ah N s XXX INSTRUCTION 1101 1000b 22 a HIGH IMPEDANCE 50 CHIP ERASE Timing GER 0 1 2 3 4 5 6 7 SCK S INSTRUCTION 1100 01116 HIGH IMPEDANCE SO Programmable Microelectronics Corp 20 Issue Date September 2005 Rev 1 0 FLASH MStar PS25LV512 010 1 PROGRAM ERASE PERFORMANCE meme __ _ Sector Erase Time ms From writing erase command to erase completion Block Erase Time ms From writing erase command to erase completion Chip Erase Time ms From writing erase command to erase completion Page Programming Time m 3 5 From writing progra
8. SE BTL LOUT 14 8 TEXAS INSTRUMENTS 4 www ti com TPA6011A4 SLOS392 FEBRUARY 2002 functional block diagram RHPIN RIN SE BTL HP LINE VOLUME Power SEDIFF 32 Step Management Volume SEMAX Control FADE LHPIN L LLINEIN MUX HP LINE LIN a NOTE resistor wipers are adjusted with 32 step volume control ROUT ROUT PVpp PGND BYPASS SHUTDOWN AGND LOUT LOUT 9 5 INSTRUMENTS www ti com TPA6011A4 SLOS392 FEBRUARY 2002 Table 1 DC Volume Control BTL Mode Vpp 5 V VOLUME PIN 21 GAIN OF AMPLIFIER Typ Tested production Remaining gain steps are specified by design NOTE For other values of Vpp scale the voltage values in the table by a factor of Vpp 5 8 TEXAS INSTRUMENTS 6 www ti com TPA6011A4 SLOS392 FEBRUARY 2002 Table 2 DC Volume Control SE Mode Vpp 5 V GAIN OF AMPLIFIER oo I 46 T Tested in production Remaining gain steps are specified by design NOTE For other values of Vpp scale the voltage values in the table by a factor of Vpp 5 9 5 INSTRUMENTS www ti com TPA6011A4 SLOS392 FEBRUARY 2002 TYPICAL CHARACTERISTICS Table of Graphs THD4N Total harmonic distortion plus noise BTL THD N Total harmonic
9. T 20mV div D 1A div VLX 10V div 1us div Start up to full load Full load CCM operation T 1us div Full load to turn off IL 1A div Vin Ripple 200mV div Vo Ripple 20mV div VLX 10V div CO I GT REI apa Vin 5V div Vin 5V div Vo 1V div E Vo lin 1V div 1A div i lin I i 1A div Coat DEREN 1ms div 1ms div Load transient Light load to turn off po EE pe ppp e Vin Vo 5V div 50mV div Vo 1V div lo lin 1A div 200mAv div l ae 100us div AOZ1041 Datasheet Rev 0 4 5 CONFIDENTIAL Not to be distributed or copied without the written permission of Alpha amp Omega Semiconductor Alpha amp Omega Semiconductor AOZ1041 Short circuit protection ot Efficiency vs load current 21041 Datasheet Rev 0 4 Short circuit recovery Vo 2V div a canini Vo 2V div IL 1A div CONFIDENTIAL 1ms div Not to be distributed or copied without the written permission of Alpha amp Omega Semiconductor Alpha amp Omega Semiconductor AOZ1041 Detailed Description The AOZ1041 is current mode st
10. www ti com vs vs FREQUENCY FREQUENCY 10 T Vpp 5 V 320 9 2 Gain 14 dB 5 2 SE 2 2 5 s 5 5 05 5 9 a a 02 5 E 5 0 1 5 0 05 S 0 05 2 2 75 mW I 0 02 z 0 02 2 001 20 50 100 200 500 1k 2k 5k 10k 20k 201 50 100 200 500 1k 2k 5k 10k 20k f Frequency Hz f Frequency Hz Figure 3 Figure 4 i 4 TEXAS INSTRUMENTS 8 TPA6011A4 5108392 FEBRUARY 2002 10 THD N Total Harmonic Distortion Noise SE THD N Total Harmonic Distortion Noise BTL TOTAL HARMONIC DISTORTION NOISE SE TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION NOISE BTL vs vs FREQUENCY OUTPUT POWER S 10 Vpp 5V VoD V 5 DD 10 5F 30 Gain 14 dB 20 2L SE 2 BTL 2 2 2 1 m 5 f 20 kHz 5 05 5 0 2 a 45 f 1kHz 0 1 E 0 1 z 0 05 1 VRMS 5 0 05 0 02 i N 0 02 f 20 Hz 0 01 oo 20 50 100 200 500 1k 2k 5k 10k 20k E 0 01 0 1 1 TOTAL HARMONIC DISTORTION NOISE BTL f Frequency Hz Figure 5 vs OUTPUT
11. 150 30 Gain 50 20 Mode BTL 120 20 120 Gain 0 dB 10 e 90 10 90 m Gain 5 1 0 60 9 2 0 60 i 10 30 50 10 30 5 8 2 2 5 8 20 9 d Ph 5 30 30 5 30 30 S lt 9 40 60 40 60 5 90 90 Vpp 5 90 60 120 60 RL 82 120 Mode BTL ae 150 70 Gain 20 dB 150 80 180 E 10 100 1k 10k 100 k 1M 100 1k 10k 100 1 15 f Frequency Hz f Frequency Hz Figure 11 Figure 12 i 4 TEXAS INSTRUMENTS TPA6011A4 SLOS392 FEBRUARY 2002 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION NOISE SE www ti com TOTAL HARMONIC DISTORTION NOISE SE 12 TPA6011A4 5108392 FEBRUARY 2002 I pp Supply Current mA Ipp Supply Current mA TYPICAL CHARACTERISTICS
12. Note 1 The Write Protect WP and Hold signals should be driven High or Low as appropriate Programmable Microelectronics Corp 5 Issue Date September 2005 Rev 1 0 FLASH PS25LV512 010 ea NEN 445 SERIAL INTERFACE DESCRIPTION CONTINUED SPI MODES These devices can be driven by microcontroller with its SPI peripheral running in either ofthe two following modes Mode 0 0 0 Mode 3 1 1 For these two modes input data is latched in on the rising edge of Serial Clock SCK and output data is Figure 2 SPI Modes available from the falling edge of Serial Clock SCK The difference between the two modes as shown in Figure 2 is the clock polarity when the bus master is in Stand by mode and not transfering data Clock remains at 0 0 for Mode 0 0 0 Clock remains at 1 1 for Mode 3 1 1 Mode 0 0 0 SCK Mode3 1 1 SCK NX SI Y X X A 50 X FX X Programmable Microelectronics Corp 6 Issue Date September 2005 Rev 1 0 FLASH MStar PS25LV512 010 4 11 ep The PS25LV512 010 is designed to interface directly with the synchronous serial peripheral interface SPI of the 6800 type series of microcontrollers The PS25LV5
13. ANM 2004 idie chi Figure 31 Shutdown Sequence in the Fade off Mode TEXAS INSTRUMENTS 20 www ti com TPA6011A4 SLOS392 FEBRUARY 2002 APPLICATION INFORMATION VOLUME SEDIFF and SEMAX operation Three pins labeled VOLUME SEDIFF and SEMAX control the BTL volume when driving speakers and the SE volume when driving headphones All of these pins are controlled with a dc voltage which should not exceed When driving speakers in BTL mode the VOLUME pin is the only pin that controls the gain Table 1 shows the gain for the BTL mode The voltages listed in the table are for Vpp 5 V For a different Vpp the values in the table scale linearly If Vpp 4 V multiply all the voltages in the table by 4 V 5 V or 0 8 The TPA60114A4 allows the user to specify a difference between BTL gain and SE gain This is desirable to avoid any listening discomfort when plugging in headphones When switching to SE mode the SEDIFF and SEMAX pins control the singe ended gain proportional to the gain set by the voltage on the VOLUME pin When SEDIFF 0 V the difference between the BTL gain and the SE gain is 6 dB Refer to the section labeled bridged tied load versus single ended load for an explanation on why the gain BTL mode is 2x that of single ended mode or 6dB greater As the voltage on the SEDIFF terminal is increased the gain in SE mode decreases The voltage on the SEDIFF terminal is subtracted from the voltage on the VOLUME t
14. _ RST E i T we C108 1 AKTQ AO _ 71 67 68 069 70 73 C72 1uF 21 10uF NC WP n m 020 CN1 A2 sci 6 157 100 5 1206 Td Ses R59 R59 GND SDA 5 R I2CSDA 5 A a VCC5V 33R ad AT24C16 2 4 R62 1008 SCL TX ScL TX 3 R63 100R SDA RX SDA RX SS DF13 10P 1 25H SDO CP2 FB CP2 N SDI EEP SDA SCK SCL VCCRV CP1 FBS E um EY IR REA HP CTR R3 10K 115 116 33uH 117 22uH R660R R67 7508 C75 0 1uF CTR lt A Tv 5 PAIN gt gt Y1INP AVITV R1 10K R68 330pF 75R 7508 C78 0 1uF U6 4 ET RP4 33RX4 8 Z SDO 2 7 L18 22uH 119 3 3uH 120 22uH R70 R 7508 C80 0 1uF SDI_EEP_SDA SO 0 1uF f gt gt cvBs1P SCK EEP 50 wpa sck 6 VEEN D20 c81 c82 R72 lyss PE 330 330 758 4 R73 750R em 0 tuF ENN 1 X CVBS1M SOIC08 y 4 BAV99 6
15. ALPHA amp OMEGA 021041 SEMICONDUCTOR EZBuck 1 5A Simple Buck Regulator ADVANCED DATASHEET Specifications subject to change Features General Description 4 5V to 16V operating input voltage range The 21041 is a high efficiency simple to use 130 mQ internal PFET switch for high 1 5A buck regulator The AOZ1041 works from a efficiency up to 95 4 5V to 16V input voltage range and provides up to Internal Schottky Diode 1 5A of continuous output current with an output Internal soft start voltage adjustable down to 0 8V Output voltage adjustable to 0 8V 1 5A continuous output current The AOZ1041 comes in an SO 8 package and is Fixed 500kHz PWM operation rated over a 40 C to 85 C ambient temperature Cycle by cycle current limit range Short circuit protection Thermal shutdown Small size SO 8 package Applications Point of load dc dc conversion PCle graphics cards Set top boxes DVD drives and HDD LCD panels Cable modems Telecom Networking Datacom equipment Typical Application 12V Input 22uF Ceramic From uPC VOUT 3 3V Output 15 L gz 22uF Ceramic Figure 1 3 3V 1 5A Buck Down Regulator AOZ1041 Datasheet Rev 0 4 CONFIDENTIAL Not to be distributed or copied without the written permission of Alpha amp Omega Semiconductor Alpha amp Omega Semiconductor AOZ1041 Ordering Information Part Number Ambient Temperature Range Package Environmental 21041
16. Ci cc iss Left Line Audio Source 7 FADE uU I Left HP System Audio Source LHPIN SHUTDOWN Control Power Supply LOUT e Left Speaker lt Cs LOUT PGND NOTE A 0 1 uF ceramic capacitor should be placed as close as possible to the IC For filtering lower frequency noise signals a larger electrolytic capacitor of 10 uF or greater should be placed near the audio power amplifier Figure 27 Typical TPA6011A4 Application Circuit Using Single Ended Inputs and Input MUX 8 TEXAS INSTRUMENTS 16 www ti com TPA6011A4 SLOS392 FEBRUARY 2002 Right Speaker APPLICATION INFORMATION 100 kQ 100 kQ 1 Power Supply From DAC Right Negative or zs Differential Input Signal Potentiometer 4 Right Positive DC Voltage Differential Input Signal Headphones Left Positive _ Differential Input Signal iko Cc Left Negative Differential Input Signal FADE d M LHPIN SHUTDOWN Control Power Supply LOUT e Left Speaker LOUT PGND NOTE 0 1 uF ceramic capacitor should be placed as close as possible to the IC For filtering lower frequency noise signals a larger electrolytic capacitor of 10 uF or greater should be placed near the audio power amplifie
17. _ CE Setup Time Hold Time Data In Setup Time 5 Data in Hold Time 5 Hold Setup Time tos tou zh e Hold Time o Output Disable Time Secter Block Chip Erase Time Page Program Time ty Write Status Register time 100 ns 100 ms lup he 7 e tv tou liz thz tec bop 100 ms Programmable Microelectronics Corp Issue Date September 2005 Rev 1 0 FLASH MStar PS25LV512 010 AC CHARACTERISTICS CONTINUED AC WAVEFORMS t N SE CE lcs lt gt cr cere SCK lt gt lt gt SI WWW VALID IN ANUS de C so Note 1 For SPI Mode 0 0 0 OUTPUT TEST LOAD INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL 3 3 V 3 0 V 1 8K AC Input 1 5 Measurement OUTPUT PIN Level 0 0 V x Programmable Microelectronics Corp 15 Issue Date September 2005 Rev 1 0 FLASH MStar PS25LV512 010 _________ __ ____ ___ _ _____ __ AC CHARACTERISTICS CONTINUED HOLD Timing CE lt P W lup SCK tus gt HOLD i 4 luz 50 gt tz PIN CAPACITANCE f 1 MHz T 25 ow m u 99 7 oe oer e
18. d 11 p WRITE ENABLE WREN The device will power up in the write disable state when Vcc is applied All write instructions must therefore be preceded by the WREN instruction WRITE DISABLE WRDI To protect the device against inadvertent writes the WRDI instruction disables all write commands The WRDI instruction is independent of the status of the WP pin READ STATUS REGISTER RDSR The RDSR instruction provides access to the status register The READY BUSY and write enable status of the device can be determined by the RDSR instruction Similarly the Block Write Protection bits indicate the extent of protection employed These bits are set by using the WRSR instruction During internal write cycles all other commands will be ignored except the RDSR instruction Table 3 Status Register Format Table 4 Read Status Register Bit Definition umm _ _ Bit 0 0 indicates the device is READY Bit Bit 0 1 indicates the write cycle is in progress and the device is BUSY Bit 1 WEN Bit 1 0 indicates the device is not WRITE ENABLED Bit 1 1 indicates the device is WRITE ENABLED Bit 2 BP0 See Table 5 Bit 3 BP1 See Table 5 Bits 4 6 are 0s when device is not in an internal write cycle WPEN 0 blocks the function of Write Protect pin WP Bit 7 WPEN WPEN 1 activates the Write Protect pin WP See Table 6 for details Bits 0 7 are 1s durin
19. f ww a w R30 C31 R32 s 5 Lourie 470K 1 30K 1206 I C34 35 36 37 038 0 1 O3duF R38 M 51K 1 1 1 I Critical Components List Components Designator Function MST720 U4 SCALER MCU Video Decode PM25LV010 U6 FLASH KT0801 UFI TPA6011 UD1 Speaker Audio Amplifier 24C16 U12 E2ROM 21041 U1 dropout voltage regulators MST720A MST720A A sta Small Size LCD TV Processor with Video Decoder Preliminary Data Sheet Version 0 1 semiconductor FEATURES n Video Decoder Programmable startup operating frequency Supports NTSC PAL and SECAM video input and period with output voltage regulation formats Programmable output current regulation 2D NTSC and PAL comb filter for Y C 40KHz 70KHz switching frequency sync to separation of CVBS input HSYNC possible Single CVBS and S video input Burst mode or continuous mode for output Supports Closed caption and V chip current regulation 150Hz 300Hz burst mode AGC and DCGC Digital Chroma Gain frequency sync to VSYNC possible Control Programmable protection level for input n Color Engine voltage and fault detection Brightness contrast saturation and hue n Miscellaneous adjustment Built in MCU 9 tap programmable multi purpose FIR Finite 3
20. The TPA6011A4 employs a shutdown mode of operation designed to reduce supply current Ipp to the absolute minimum level during periods of nonuse for battery power conservation The SHUTDOWN input terminal should be held high during normal operation when the amplifier is in use Pulling SHUTDOWN low causes the outputs to mute and the amplifier to enter a low current state 20 uA SHUTDOWN should never be left unconnected because amplifier operation would be unpredictable Table 3 HP LINE SE BTL and Shutdown Functions t Inputs should never be left unconnected X don t care NOTE The Low and High trip levels can be found in the recommended operating conditions table FADE operation For design flexibility a fade mode is provided to slowly ramp up the amplifier gain when coming out of shutdown mode and conversely ramp the gain down when going into shutdown This mode provides a smooth transition between the active and shutdown states and virtually eliminates any pops or clicks on the outputs When the FADE input is a logic low the device is placed into fade on mode A logic high on this pin places the amplifier in the fade off mode The voltage trip levels for a logic low or logic high can be found in the recommended operating conditions table on page 4 When a logic low is applied to the FADE pin and a logic low is then applied on the SHUTDOWN pin the channel gain steps down from gain step to gain step at a ra
21. 61 VCOM Interface PinName Function Pin VCOMDC Analog Output Reference DC Voltage Output for Common Amplifier VCOMOUT Analog Output Pulse Output for Common Voltage Version 0 1 5 11 22 2005 Copyright 2005 MStar Semiconductor Inc All rights reserved MST720A MST720A A sta Small Size LCD TV Processor with Video Decoder Preliminary Data Sheet Version 0 1 Semia da n Switching Power and PWM Interface Pin Type Function Pin PWMOUT2 Output Switching Pulse Output for DC DC Converter 2 Analog Input Error Voltage Feedback Input Pin for PWM2 voltage 1 2V EN Analog Input Sense Circuit Connection for PWM2 28 IPwMOUTl Output Switching Pulse Output for DC DC Converter mo Analog Input Error Voltage Feedback Input Pin for 1 1 2V as Analog Input Sense Circuit Connection Sense Circuit Connection forPWM1 PWM1 2 o O FB Analog Input Error Voltage Feedback Input Pin for CP2 voltage 1 2V Charge Pump Negative Pulse for DC DC Negative Voltage Converter 2 ES yerfac M fog TS MN ue pa 7 Analog SAR Low Speed ADC Input e SR Amaoginput SAR Low Speed ADC inputi a saro Analog input SAR Low Speed ADCInputo o ECK Output SPI interface Sampling Je m soo sv tolerant 5 interface Datarout CN Output S Interface chip Select s
22. TA lt 25 C DERATING FACTOR TA 70 C 85 C POWER RATING ABOVE TA 25 C POWER RATING POWER RATING PWP 2 7 mW 21 8 mW C 1 7W 1 4W PACKAGE recommended operating conditions MAX UNT SE BTL HP LINE FADE 0 8xVpp High level input voltage VIH SHUTDOWN SE BTL HP LINE FADE 0 6xVpp Operating free air temperature TA 4 85 C 4 0 5 5 2 40 85 8 TEXAS INSTRUMENTS 2 www ti com TPA6011A4 SLOS392 FEBRUARY 2002 electrical characteristics TA 25 C Vpp PVpp 5 5 V unless otherwise noted PARAMETER TEST CONDITIONS TYP MAX UNIT 5 5 V Gain 0 dB SE BTL 0 V mv V Output offset voltage measured differentiall Vool y Vpp 5 5 V Gain 20 dB 50 mV SE BTL 0V PSRR Power supply rejection ratio Vpp PVpp 4 0 V to 5 5 V 42 70 High level input current SE BTL FADE HP LINE Vpp PVpp 5 5 1 SHUTDOWN SEDIFF SEMAX VOLUME V Vpp PVpp H Low level input current SE BTL FADE HP LINE 5 5 V SHUTDOWN SEDIFF SEMAX VOLUME VoD PVpp 5 5V VI 0V 1 60 75 9 0 SE BTL 0 SHUTDOWN 2 V Vpp PVpp 5 5 V SE BTL 5 5 V SHUTDOWN 2 V 3 0 5 6 Vpp 5 PVpp SE BTL 0 V IDD Supply current max power into a 3 O load SHUTDOWN 2 V 30 1 5 ARMS Po 2 W stereo IDD SD Supply current shutdown mode SHUTDOWN 0 0 V operating characteristics TA
23. all write operations to the status register are inhibited HOLD INPUT Hold Pause serial communication with the master device without resetting the serial sequence Programmable Microelectronics Corp 2 Issue Date September 2005 Rev 1 0 m FLASH MStar PS25LV512 010 v d _________ ___ _ PRODUCT ORDERING INFORMATION PS25LVxxx 33 S C E EN Environmental Attribute Lead free Pb free Package Blank Standard Package Temperature Range C Commercial 0 C to 85 C Package Type S 8 pin SOIC 8S Operating Speed 33 33MHz max for Normal and Fast read Products Device Number PS25LV512 512 Kbit PS25LV010 1 Mbit Part Number Operating Frequency MHz Temperature Range PS25LV512 33SC PS25LV512 33SCE 33 88 2 PS25LV010 33SC 0 C to 85 C PS25LV010 33SCE Programmable Microelectronics Corp 3 Issue Date September 2005 Rev 1 0 FLASH MStar PS25LV512 010 ea BLOCK DIAGRAM SPI Chip Block Diagram High Voltage Generator Control Logic Instruction Decoder Serial Parallel convert Logic Address Latch 2KBit Page Buffer Status amp Counter Register 9 m 7 gt X DECODER Programmable Microelectronics Corp 4 Issue Date September 2005 Rev 1 0
24. 25 Vpp Z PVpp 5 V 3 Gain 6dB unless otherwise noted B i 0 IDD Supply current no load mA OM Maximum output power bandwidth THD 5 kHz Supply ripple rejection ratio f 1 kHz Gain 0 dB 0 47 f 20 Hz 1020 kHz Gain 0 dB 0 47 7 Input impedance see figure 25 VOLUME 5 0 V Noise output voltage 9 5 INSTRUMENTS www ti com 3 TPA6011A4 5108392 FEBRUARY 2002 PWP PACKAGE TOP VIEW PGND ROUT ROUT SE BTL PVpp HP LINE RHPIN VOLUME RLINEIN SEDIFF RIN SEMAX Vpp AGND LIN BYPASS LLINEIN FADE LHPIN SHUTDOWN PVpp LOUT LOUT PGND Terminal Functions TERMINAL vo DESCRIPTION NAME NO Power ground RLINEIN RHPIN ROUT ROUT 24 SHUTDOWN ADE Ajo Right channel headphone input selected when HP LINE is held high Right channel negative audio output Right channel positive audio output Places the amplifier in shutdown mode if a TTL logic low is placed on this terminal Places the amplifier in fade mode if a logic low is placed on this terminal normal operation if a logic high is placed on this terminal LLINEIN inputs are selected Output MUX control When this terminal is high SE outputs are selected When this terminal is low BTL outputs are selected Left channel positive audio output BYPASS AGND SEMAX 1 SEDIFF VOLUME 21 HP LINE 22
25. 40 C to 85 C SO 8 RoHS Compliant Pin Configuration PGND 1 8 LX VIN 2 7 LX SO 8 AGND 3 6 EN 4 5 COMP Pin Number Pin Name Pin Function 1 PGND Power ground Electrically needs to be connected to AGND 2 VIN Supply voltage input When VIN rises above the UVLO threshold the device starts up 3 AGND Reference connection for controller section Also used as thermal connection for controller section Electrically needs to be connected to PGND 4 FB The FB pin is used to determine the output voltage via a resistor divider between the output and GND 5 COMP External loop compensation pin 6 EN The enable pin is active high Connect EN pin to VIN if not used Do not leave the EN pin floating 7 8 LX PWM output connection to inductor Thermal connection for output stage AOZ1041 Datasheet Rev 0 4 2 CONFIDENTIAL Not to be distributed or copied without the written permission of Alpha amp Omega Semiconductor Alpha amp Omega Semiconductor AOZ1041 Absolute Maximum Ratings Recommend Operating Ratings Supply Voltage 18V Supply Voltage 4 5V to 16V LX to 0 7V to Viy 0 3V Output Voltage Range 0 8V to EN to AGND 0 3V to Viy 0
26. Interrupt Input for IR Recelver IDA I O w 5V tolerant 3 Wire Serial Bus Data Version 0 1 6 11 22 2005 Copyright 2005 MStar Semiconductor Inc All rights reserved MST720A MST720A A sta Small Size LCD TV Processor with Video Decoder Preliminary Data Sheet Version 0 1 semiconductor ma Pin Name PinType Function __ Input w 5V tolerant 3 Wire Serial Bus Clock POWER ON RSTN CS Input w 5V tolerant Power On Reset Signal 51 Chip Selection for 3 wire Serial Digital PWM Interface o1 Input for 2 Feedback Loop 15 t s 8 wsc mer QT Qp nntifnontilo ft 0 7 nternal ROM Enable 0 Disable 1 Enable Power Pins oe mmm AVDD GMC GMC Power AVDD SAR Power 5V Power Version 0 1 7 11 22 2005 Copyright 2005 MStar Semiconductor Inc All rights reserved MST720A MST720A A sta r Small Size LCD TV Processor with Video Decoder Preliminary Data Sheet Version 0 1 semiconductor ww Function AVDD_MPLL 2 5V Power MPLL Power VDDC 2 5V Power Digital Core Power 23 80 VDDP 3 3V 5V Power Digital Input Output Power 60 76 AVSS_SAR SAR Ground AVSS DPWM Ground Ground Ground rr 24 52 59 81 82 85 89 99 Version 0 1 8 11 22 2005 Copyright 2005 MStar Semiconductor Inc All rights reserved MST720A MST720A A Msta r Small Size
27. PER CHANNEL vs OUTPUT POWER 200 180 160 140 120 100 160 80 60 40 0 50 100 150 200 250 300 Output Power mW Figure 18 CROSSTALK vs FREQUENCY Vpp 5 V Po 1W RL 8 Gain 0dB BTL 20 100 1k 10k 20k f Frequency Hz Figure 20 INSTRUMENTS www ti com 13 TPA6011A4 5108392 FEBRUARY 2002 14 Crosstalk dB PSRR Power Supply Rejection Ratio BTL dB TYPICAL CHARACTERISTICS CROSSTALK vs FREQUENCY Vpp 5 Po 1W RL 80 Gain 20 dB BTL 20 100 1k f Frequency Hz 10k 20k Figure 21 POWER SUPPLY REJECTION RATIO BTL vs FREQUENCY Vpp 5 V RL 80 C BYP 0 47 BTL HP Line Attenuation dB PSRR Power Supply Rejection Ratio SE dB HP LINE ATTENUATION vs FREQUENCY 20 100 1k 10k 20k f Frequency Hz Figure 22 POWER SUPPLY REJECTION RATIO SE vs FREQUENCY Vpp 5V RL 32 0 0 47 SE
28. The trip point where the gain actually changes is different depending on whether the voltage is increased or decreased as a result of the hysteresis about each trip point The gaps in tables 1 and 2 can also be thought of as indeterminate states where the gain could be in the next higher gain step or the lower gain step depending on the direction the voltage is changing If using a DAC to control the volume set the voltage in the middle of each range to ensure that the desired gain is achieved A pictorial representation of the volume control can be found in Figure 33 The graph focuses on three gain steps with the trip points defined in Table 1 for BTL gain The dotted line represents the hysteresis about each gain step TEXAS INSTRUMENTS www ti com 21 TPA6011A4 SLOS392 FEBRUARY 2002 APPLICATION INFORMATION VOLUME SEDIFF and SEMAX operation continued SEDIFF V SEMAX V Is SEMAX gt rN VOLUME SEDIFF VOLUME SEDIFF VOLUME V SE VOLUME V VOLUME V SEDIFF V SE VOLUME V SEMAX V Figure 32 Block Diagram of SE Volume Control BTL Gain dB 2 61 270 2 73 2 81 Voltage on VOLUME Pin V Figure 33 DC Volume Control Operation TEXAS INSTRUMENTS 22 www ti com TPA6011A4 SLOS392 FEBRUARY 2002 APPLICATION INFORMATION input resistance Each gain setting is achieved by varying the input resistance of the amplifier which can range from its smallest
29. Vs Vs VTV 50 YIX 6X5 Y a Y 2 Y 1 NO Oe AC MSB WRSR Timing SCK 0 1 2 8 4 5 6 7 8 9 10 Hl 1213 14 15 DATA IN XY INSTRUCTION 000000046 7 6 5 4 3 2 1 0 HIGH IMPEDANCE READ Timing NS c 0 1 2 3 4 5 6 7 8 9 1011 28 29 30 31 32 33 34 35 36 37 38 A ULL UU Hi 3 BYTE ADDRESS SI INSTRUCTION 0000 00115 23 22 21 X x X X X X HIGH IMPEDANCE 50 74864 5444 342X41 X0 Programmable Microelectronics Corp 18 Issue Date September 2005 Rev 1 0 FLASH MStar PS25LV512 010 ea wd ru ________________ _ FAST READ Timing CE 0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 LII 3 BYTE ADDRESS SCK FIN AV LAR Ad Ry 8 X X INSTRUCTION 0000 10116 28 22 21 3X HIGH IMPEDANCE SO CE 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 CIL HUI 4 NIU UI DUMMY BYTE T o TOTO SI 9 7 X A On 4 Y 3 Y X X b X Y X X X bi DATA OUT 1 DATA OUT 2 HIGH IMPEDANCE 50 76 54 342414047464 5X4 X3K2K1 XO PAGE PROGRAM Timing CE N mo co o 55 5 5 0 1 2 3 4 5 6 7 10 11 28 29 30 31 32 33 34 NN NNN 1st BYTE DATA IN 256th BYTE DATA IN 3 BYTE ADDRESS UNA V SI X X INSTRUCTION 0000 00100 2 22 a y N
30. the audio power amplifier is recommended midrail bypass capacitor 24 The midrail bypass capacitor is the most critical capacitor and serves several important functions During start up or recovery from shutdown mode determines the rate at which the amplifier starts up The second function is to reduce noise produced by the power supply caused by coupling into the output drive signal This noise is from the midrail generation circuit internal to the amplifier which appears as degraded PSRR and THD N Bypass capacitor values of 0 47 uF to 1 uF ceramic ortantalum low ESR capacitors are recommended for the best THD and noise performance For the best pop performance choose a value for that is equal to or greater than the value chosen for Ci This ensures that the input capacitors are charged up to the midrail voltage before C BYP is fully charged to the midrail voltage 9 6 INSTRUMENTS www ti com TPA6011A4 SLOS392 FEBRUARY 2002 APPLICATION INFORMATION output coupling capacitor C c In the typical single supply SE configuration an output coupling capacitor C c is required to block the dc bias at the output of the amplifier thus preventing dc currents in the load As with the input coupling capacitor the output coupling capacitor and impedance of the load form a high pass filter governed by equation 4 3 dB fiw ZaR Cig 4 fc The main disadv
31. 10 of switching frequency The AOZ1041 operates at a fixed 500kHz switching frequency is recommended to choose crossover frequency equal or less than 50kHz 50kHz The strategy for choosing Rc and is to set the cross over frequency with Rc and set the compensator zero with Using selected crossover frequency fc to calculate Rc Vo 2 x Co X Ges Ro fex where fc is desired crossover frequency For best performance fc is set to be about 1 10 of switching frequency Vep is 0 8V Gea is the error amplifier transconductance which is 200 10 A V Ges is the current sense circuit transconductance which is 6 68 A V The compensation capacitor and resistor Rc together make a zero This zero is put somewhere close to the dominate pole f but lower than 1 5 of selected crossover frequency can is selected by _ 1 5 2 X Rc x Equation above can also be simplified to _ Cox R Rc An easy to use application software which helps to design and simulate the compensation loop can be found at www aosmd com Cc AOZ1041 Datasheet Rev 0 4 Thermal management and layout consideration In the AOZ1041 buck regulator circuit high pulsing current flows through two circuit loops The first loop starts from the input capacitors to the VIN pin to the LX pins to the filter inductor to the output capacitor and load and then return to the input capacitor through ground C
32. 20 to 30 of output current When selecting the inductor make sure it is able to handle the peak current without saturation even at the highest operating temperature AOZ1041 Datasheet Rev 0 4 The inductor takes the highest current in a buck circuit The conduction loss on inductor need to be checked for thermal and efficiency requirements Surface mount inductors in different shape and styles are available from Coilcraft Elytone and Murata Shielded inductors are small and radiate less EMI noise But they cost more than unshielded inductors The choice depends on EMI requirement price and size Table below lists some inductors for typical output voltage design Table 2 Vout L1 Manufacture 5 0 V Unshielded 4 7uH MURATA LQH55DN4R7M03 Shielded 4 7uH MURATA LQH66SN4R7M03 Shield 5 8uH ELYTONE ET553 5R8 Un shielded 4 7uH Coilcraft DO3316P 472MLD 3 3 V Unshielded 4 7uH MURATA LQH55DN3R3M03 Shield 4 7uH MURATA LQH66SN3R3M03 Shield 3 3uH ELYTONE ET553 3R3 Un shielded 4 7uH Coilcraft DO3316P 472MLD Un shielded 4 7uH Coilcraft DO1813P 472HC 1 8 V Unshielded 2 2uH MURATA LQH55DN1R5M03 Shield 2 2uH MURATA LOH66SN1R5M03 Shield 2 2uH ELYTONE ET553 2R2 Un shielded 2 2uH Coilcraft DO3316P 222MLD Un shielded 2 2uH Coilcraft DO1813P 222HC Output Capacitor The output capacitor is selected based on the DC output voltage rating output rippl
33. 3V Ambient Temperature 40 C to 85 C FB to AGND 0 3V to 6V Package Thermal Resistance COMP to AGND 0 3V to 6V 50 8 dicet hdc 87 C W PGND to 0 3V to 0 3V Junction Temperature 150 C Storage Temperature Ts 65 C to 150 C Electrical Characteristics 25 C Vin Ven 12V Vout 3 3V unless otherwise specified Specifications in BOLD indicate a ambient temperature range of 40 C to 85 C Parameter Symbol Conditions MIN TYP MAX UNITS Supply Voltage Vin 4 5 16 V Input under voltage Vin rising 4 00 V lockout threshold Vin falling 3 70 V Supply current lin lout 0 VFB 1 2V 2 3 mA Quiescent Ven gt 1 2V Shutdown supply current Ven OV 3 20 Feedback Voltage Vra 0 782 0 8 0 818 V Load regulation 0 5 96 Line regulation 1 96 Feedback voltage input 200 current EN input threshold VEN Off threshold 0 8 V On threshold 2 0 V EN input hysteresis Vuvs 100 mV Modulator Frequency fo 380 480 580 kHz Maximum Duty Cycle Dmax 100 Minimum Duty Cycle Duin 6 Error amplifier voltage 500 VN gain Error amplifier 200 transconductance Protection Current Limit 2 0 3 6 Over temperature rising 155 shutdown limit Ty falling
34. 5 04 03 RMs lo 02 0 1 10 0 0 0 5 1 10 41 Figure 2 vs voltage conversion ratio For reliable operation and best performance the input capacitors must have current rating higher than at worst operating conditions Ceramic capacitors are preferred for input capacitors because of their low ESR and high current rating Depending on the application circuits other low ESR tantalum capacitor may also be used When selecting ceramic capacitors X5R or X7R type dielectric ceramic capacitors should be used for their better temperature and voltage characteristics Note that the ripple current rating from capacitor manufactures are based on certain amount of life time Further de rating may be necessary in practical design Inductor The inductor is used to supply constant current to output when it is driven by a switching voltage For given input and output voltage inductance and switching frequency together decide the inductor ripple current which is Al Vo Mis Ma fx L Vy The peak inductor current is I E Lpeak High inductance gives low inductor ripple current but requires larger size inductor to avoid saturation Low ripple current reduces inductor core losses It also reduces RMS current through inductor and switches which results in less conduction loss Usually peak to peak ripple current on inductor is designed to be
35. FLASH MStar PS25LV512 010 4 d 4 411111 SERIAL INTERFACE DESCRIPTION PS25LV512 010 can be driven by a microcontroller on the SPI bus as shown in Figure 1 The serial communication term definitions are in the following section MASTER The device that generates the serial clock SLAVE Because the Serial Clock pin is always an input the PS25LV512 010 always operates as a slave TRANSMITTER RECEIVER The PS25LV512 010 has separate pins designated for data transmission SO and reception SI MSB The Most Significant Bit MSB is the first bit transmitted and received SERIAL OP CODE After the device is selected with CE going low the first byte will be received This byte contains the op code that defines the operations to be performed INVALID OP CODE If an invalid op code is received no data will be shifted into the PS25LV512 010 and the serial output SO will remain a high impedance state until the falling edge is detected again This will reinitialize the serial communication Figure 1 Bus Master and SPI Memory Devices SPI Interface with nterface wit SDI e 0 0 or 1 DA ec i SO SI sox so SI so SI v Y Y Bus Master SPI Memory SPI Memory SPI Memory Device Device Device CS3 CS2 51 J o A CE WP HOLD WP HOLD CE WP4 HOLD
36. LCD TV Processor with Video Decoder Preliminary Data Sheet Version 0 1 95 semiconductor ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings 3 3V Supply Voltages 0 3 2 5V Supply Voltages 25 0 3 2 75 Input Voltage 5V tolerant inputs 0 3 5 0 Input Voltage non 5V tolerant inputs Vin 0 3 0 Storage Temperature Tsrc 0 125 Junction Temperature 6 3 6 Ex gt 10 lt lt Q t Thermal Resist Note Stress aba e listeg P unt 1 56 permanent dam ge device This is stress rating only ctional of th d vice at these or any other conditions outside of those indicated in the operation sections of this specification is not implied Exposure to absolute maximum ratings for extended periods may affect device reliability ORDERING G LDE Temperature Package Package Range Description Option MST720A 0 C to 70 C 1 100 do 24 VoU Operation Code A Note Product suffix LF represents lead free Vei and A represents extended temperature range Ut 5 DI MER MSTAR SEMI CONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WI THOUT FURTHER NOTI CE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY FUNCTION OR DESIGN NO RESPONSIBILITY 15 ASSUMED BY MSTAR SEMI CONDUCTOR A
37. La ints 0 12 Audio Input Frequency Band 20 m Channel Step EG at SIG PROC lt I gt 1 5 oe 15 2 2 wire Clock So LR s s Pin 17 Pre emphasis Time Constant Crystal External Clock Low Level Input Voltage 17 24 IOVDD 0 25 aes Die 17 24 IOVDD Notes 1 Maximum is given on the condition of PGA gain 12dB 2 Fin 20 15k Hz Copyright 2006 KT Micro Inc KTMicro KT0801 Package and Pin List A 24 pin QFN package is used The chip IO pin out is listed in Table 3 Table 3 KT0801 Pin Out Pin Index Type IOVDD 1 6 3 3V external logic IOVDD or Regulator high supply input 22 enabled All four pins shall be shorted on the PCB 1 to enable 15 2MHz XTAL mode Default 0 7 6MHz XTAL mode Analog Input Left channel audio input ccc M cos ONU N NCI NC2 Reserved Do not connect i O SW2 ____ Digital Input Control bit Chip enable supply mode and clock _____ Set the 4 I2C address bit MSB being the 1 bit SDA jDigitallO SeraldatalO SCL Serial clock input INL GND INR C2 SW2 SDA SCL XI Xx Analog I O Crystal input XO RCLK Analog I O Crystal input or external reference clock input Copyright 2006 KT Micro Inc RSTB GND SW2 SWI NC2 NCI PA OUT
38. The AOZ1041 integrates an internal PPMOSFET as the high side switch Inductor current is sensed by amplifying the voltage drop across the drain to source of the high side power MOSFET Output voltage is divided down by the external voltage divider at the FB pin The difference of the FB pin voltage and reference is amplified by the internal transconductance error amplifier The error voltage which shows on the COMP pin is compared against the current signal which is sum of inductor current signal and ramp compensation signal at PWM comparator input If the current signal is less 21041 Datasheet 0 4 than the error voltage the internal high side switch is on The inductor current flows from the input through the inductor to the output When the current signal exceeds the error voltage the high side switch is off The inductor current is freewheeling through the internal Schottky diode to output The AOZ1041 uses a P Channel MOSFET as the upper switch It saves the bootstrap capacitor normally seen a circuit which is using an NMOS switch It allows 100 turn on of the upper switch to achieve linear regulation mode of operation The minimum voltage drop from Vin to Vo is the load current times DC resistance of MOSFET plus DC resistance of buck inductor It can be calculated by equation below V 1 x Where Vo is the maximum output voltage Vin is the input voltage from 4 5V to 16V lo
39. be ignored while the SO pin is in the high impedance state HARDWARE WRITE PROTECT The PS25LV512 010 has a write lockout feature that can be activated by asserting the write protect pin WP When the lockout feature is activated locked out sectors will be READ only The write protect pin will allow normal read write operations when held high When the WP is brought low and WPEN bit is 1 all write operations to the status register are inhibited WP going low while CE is still low will interrupt a write to the status register If the internal status register write cycle has already been initiated WP going low will have no effect on any write operation to the status register The WP pin function is blocked when the WPEN bit in the status register is 0 This will allow the user to install the PS25LV512 010 in a system with the WP pin tied to ground and still be able to write to the status register All WP pin functions are enabled when the WPEN bit is set to 1 Programmable Microelectronics Corp 11 Issue Date September 2005 Rev 1 0 FLASH MStar PS25LV512 010 a ABSOLUTE MAXIMUM RATINGS 0 5 V to Vcc 0 5 V 0 5 V to Vcc 0 5 V 0 5 V to 6 0 V Notes 1 Stresses under those listed in Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only The functional operation of the device or any other conditions under t
40. he veL Rx4 UD 100 5 4 3 2 1 wii SSMUS Change Bead to Resistance VCOMDC for Glitch Prevention VBOUT RI 10R Keep away of Analog Area VGOUT 7 a vecsv AVDD_DAC C46 20pF VROUT i E O 17 4R7 0603 AYDD pe L 2R D C 2 2 120 0603 AVDD DPWM 3 JAVDD_OPLL L9 28 5 O VDDC R46 NC 4K7 FESSES 0603 tt 5 s e EFA ess 8 E pg C edd 4 lt o m VDDP REM 9 5159 61 zl ceo z L10 4R7 Z 64 ces 59 7P 7P Peres d255432295892295292Eud8868558 VDDP 1 gt gt gt uF Tur 292252235000 o 9995859
41. is the output current from OA to 1 5A Roson 15 the on resistance of internal MOSFET the value is between 97mQ 200mO depending on input voltage and junction temperature Switching Frequency The AOZ1041 switching frequency is fixed and by an internal oscillator The practical switching frequency could range from 380 kHz to 580 kHz due to device variation Output Voltage Programming Output voltage can be set by feeding back the output to the FB pin by using a resistor divider network In the application circuit shown in Figure 1 The resistor divider network includes R4 and Ro Usually a design is started by picking a fixed R value and calculating the required R1 with equation below R Vo 0 8 x 1 R Some standard value of and most used output voltage values are listed in Table 1 CONFIDENTIAL Not to be distributed or copied without the written permission of Alpha amp Omega Semiconductor Alpha amp Omega Semiconductor AOZ1041 Table 1 Vo R1 R2 0 8 1 0 open 1 2 4 99 10 1 5 10 11 5 1 8 12 7 10 2 2 5 21 5 10 3 3 31 1 10 5 0 52 3 10 Combination of R1 and R2 should be large enough to avoid drawing excessive current from the output which will cause power loss Since the switch duty cycle can be as high as 100 the maximum output voltage can be set as high as the input voltage minus the voltage drop on upper PMOS and induc
42. to 1 uF A further consideration for this capacitor is the leakage path from the input source through the input network Cj and the feedback network to the load This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom especially in high gain applications For this reason a low leakage tantalum or ceramic capacitor is the best choice When polarized capacitors are used the positive side of the capacitor should face the amplifier input in most applications as the dc level there is held at Vpp 2 which is likely higher than the source dc level Note that it is important to confirm the capacitor polarity in the application power supply decoupling C s The TPA6011A4 is a high performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion THD is as low as possible Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power supply leads For higher frequency transients spikes or digital hash on the line a good low equivalent series resistance ESR ceramic capacitor typically 0 1 uF placed as close as possible to the device Vpp lead works best For filtering lower frequency noise signals a larger aluminum electrolytic capacitor of 10 uF or greater placed near
43. value to over six times that value As a result if a single capacitor is used in the input high pass filter the 3 dB or cutoff frequency also changes by over six times If an additional resistor is connected from the input pin of the amplifier to ground as shown in the figure below the variation of the cutoff frequency is much reduced IN Input Signal Figure 34 Resistor on Input for Cut Off Frequency The input resistance at each gain setting is given in Figure 34 The 3 dB frequency can be calculated using equation 1 zal _3dB 7 1 input capacitor In the typical application an input capacitor Cj is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation In this case Cj and the input impedance of the amplifier Rj form a high pass filter with the corner frequency determined in equation 2 3 dB ju 2 c highpass 2 TEXAS INSTRUMENTS www ti com 23 TPA6011A4 SLOS392 FEBRUARY 2002 APPLICATION INFORMATION input capacitor C continued The value of is important to consider as it directly affects the bass low frequency performance of the circuit Consider the example where R is 70 and the specification calls for a flat bass response down to 40 Hz Equation 2 is reconfigured as equation 3 1 2xRifc 3 In this example is 56 8 nF so one would likely choose a value in the range of 56 nF
44. 010 two separate instructions must be executed First the device must be write enabled via the WREN instruction Then the PAGE PROGRAM instruction can be executed Also the address of the memory location s to be programmed must be outside the protected address field location selected by the Block Write Protection Level During an internal self timed programming cycle all commands will be ignored except the RDSR instruction The PAGE PROGRAM instruction requires the following sequence After the CE line is pulled low to select the device the PAGE PROGRAM instruction is transmitted via the SI line followed by the address and the data 07 00 to be programmed Refer to Table 7 Programming will start after the CE pin is brought high The low to high transition of the CE pin must occur during the SCK low time immediately after clocking in the DO LSB data bit The READY BUSY status of the device can be determined by initiating a RDSR instruction If Bit 0 1 the program cycle is still in progress If Bit 0 0 the program cycle has ended Only the RDSR instruction is enabled during the program cycle A single PROGRAM instruction programs 1 to 256 consecutive bytes within a page if it is not write protected The starting byte could be anywhere within the page When the end of the page is reached the address will wrap around to the beginning of the same page If the data to be programmed are less than a full page the data of all other bytes on the sa
45. 10 is enabled through the Chip Enable CE and accessed a 3 wire interface consisting of Serial Data Input SI Serial Data Output SO and Serial Clock SCK write cycles are com pletely self timed Block Write protection for top 1 4 top 1 2 or the entire memory array 1M or entire memory array 512 is enabled by programming the status register Separate write enable and write disable instructions are provided for additional data protection Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register The HOLD pin may be used to suspend any serial communication without resetting the serial sequence Programmable Microelectronics Corp 1 Issue Date September 2005 Rev 1 0 FLASH MStar PS25LV512 010 v F4 11 9335 CONNECTION DIAGRAMS 8 Pin SOIC PIN DESCRIPTIONS SYMBOL TYPE DESCRIPTION Chip Enable CE goes low activates the device s internal circuitries for device operation CE goes high deselects the device and switches into CE INPUT standby mode to reduce the power consumption When the device is not selected data will be accepted the serial input SI and the serial output pin SO will remain in a high impedance state Serial Data Clock o eee Me Write Protect When the WP pin brought to low and WPEN bit is 1
46. 100 C Soft Start Interval tss 4 ms Output Stage High side switch on Vin 12V 97 130 resistance Vin 5V 166 200 Notes 1 Exceeding the Absolute Maximum ratings may damage the device 2 The device is not guaranteed to operate beyond the Maximum Operating ratings 3 Devices are inherently ESD sensitive handling precautions are required Human body model rating 1 5KQ in series with 100pF AOZ1041 Datasheet Rev 0 4 CONFIDENTIAL Not to be distributed or copied without the written permission of Alpha amp Omega Semiconductor Alpha amp Omega Semiconductor AOZ1041 Functional Block Diagram 5V LDO REGULATOR Internal 45V REFERENCE amp BIAS SOFTSTART AM PWM CONTROL LOGIC 21041 Datasheet Rev 0 4 Not to be distributed or copied without the written permission of Alpha amp Omega Semiconductor 500Khz OSCILLATOR CONFIDENTIAL LEVEL SHIFTER FET DRIVER PGND Alpha amp Omega Semiconductor AOZ1041 Typical Performance Characteristics Circuit of figure 1 T4 25 C Vin Ven 12V Vout 3 3V unless otherwise specified Light load DCM operation rere Vin Ripple 200mV div Es EN pt
47. 12 010 utilizes an 8 bit instruction register The list of instructions and their operation codes are contained in Table 1 All instructions addresses and data are transferred with the MSB first and start with a high to low transition Write is defined as program and or erase in this specification The following commands PAGE PROGRAM SECTOR ERASE BLOCK ERASE CHIP ERASE and WRSR are write instructions for PS25LV512 010 Table 1 Instruction Set for the PS25LV512 010 WREN 0000 0110 Set Write Enable Latch WRDI 0000 0100 Reset Write Enable Latch RDSR 0000 0101 Read Status register WRSR 0000 0001 Write Status Register READ 0000 0011 READ PRODUCT ID RDID The RDID instruction allows the user to read the manufacturer and product ID of the device The instruction code is followed by three dummy bytes each bit being latched in on Serial Data Input SI during the rising edge of Serial Clock SCK Then the first manufacturer ID 9Dh is shifted out on Serial Data Output SO followed by the device ID 7Bh PS25LV512 7Ch PS25LV010 and the second manufacturer ID 7Fh each bit been shifted out during the falling edge of Serial Clock SCK Table 2 Product Identification Product Identification Manufacturer ID Device ID PS25LV512 PS25LV010 Programmable Microelectronics Corp 7 Issue Date September 2005 Rev 1 0 FLASH MStar PS25LV512 010 PELLIT v
48. 5 100RX aves 200955859922 B 9 OS E 751 ICON15 LKI R48 108 ADC Sor ers S ag 74 14 LK2 iin VOLAMP 29 TCON14 74 TCON13 CLK3 Ts VCC3 3V vi lt TooNi2 L 2 STH2 T AVDD O AVDD_ADC PIN79 Hi Ext 8K ROM 1 STH1 L a NOMOR PIN79 Lo Serial Flash MOD 2 8 Vs1INP U4 toons 88 5 S STINE ICONS REQ 33 L11 FB30R G it Qo cvesip MST720C T TCON6 AVDD MPLL CVBS1M RP 3RX4 112 FB30R AVDD_GMCO 13 64 DA opel HE ME 13 Analog TCON Panel amp DADE FAULTZ TCON2 STV2 DPWM IFB REA AUR 15 Digital 1 1 2570 113 FB30R E 6 PEs CVBS 1 AVDD 55 sar H SAR 3 GPIO 3 1 Gite gt gt VLCDPW 147 28 TER PEM 9 2 avss_DPWMG GPIO0 P0 0 E E din Q2 21 o DHOF MET 100 L RESET MARIA R0603 ai at PwM1D H3 VOLUME PWM AVDD PWM 23 53 EE o 4 bbc Power and Charge Pump 998 9 PWM2D NL U D vecsv AVSS_PWM 2900 a TESTIN 22 RSR lt 9 us 6536 R54 55 59555
49. 5R or X7R dielectric type of ceramic or other low ESR tantalum are recommended to be used as output capacitors In a buck converter output capacitor current is continuous The RMS current of output capacitor is decided by the peak to peak inductor ripple current It can be calculated by _ Ico nus 112 Usually the ripple current rating of the output capacitor is a smaller issue because of the low current stress When the buck inductor is selected to be very small and inductor ripple current is high output capacitor could be overstressed Loop Compensation The AOZ1041 employs peak current mode control for easy use and fast transient response Peak current mode control eliminates the double pole effect of the output L amp C filter It greatly simplifies the compensation loop design 21041 Datasheet Rev 0 4 With peak current mode control the buck power stage can be simplified to be a one pole and one zero system in frequency domain The pole is dominant pole can be calculated by 1 In 27 xC x R The zero is a ESR zero due to output capacitor and its ESR It is can be calculated by 1 2 x Co x ESRco Where is the output filter capacitor is load resistor value 5 is the equivalent series resistance of output capacitor The compensation design is actually to shape the converter control loop transfer function to get desired gain and phase Several different types of compens
50. BRUARY 2002 AVAILABLE OPTIONS TA 24 PIN TSSOP PWP 40 C to 85 C TPA6011A4PWP NOTE The PWP package is available taped and reeled To order a taped and reeled part add the suffix R to the part number e g TPA6011A4PWPR absolute maximum ratings over operating free air temperature unless otherwise noted t Supply voltage PVDD 0 3 V to 6 V Input voltage EI E AE CORP 0 3 V to Vpp 0 3 V Continuous total power dissipation See Dissipation Rating Table Operating free air temperature range TA 40 to 85 C Operating junction temperature range 40 C to 150 C Storage temperature range Tstg enne 65 C to 150 C Lead temperature 1 6 mm 1 16 inch from case for 10 seconds 260 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability DISSIPATION RATING TABLE
51. GND GND VDD XI XO CLK Inc F x LE KTA Figure 2 KT0801 Pin out 4x4 24 Pin QFN Package KT Micro Inc Copyright 2006 L gt KTMicro KT0801 Inc C Compatible 2 Wire Serial Interface General Descriptions The serial interface consists of a serial controller and registers An internal address decoder transfers the content of the data into appropriate registers Both the write and read operations are supported according to the following protocol The write operation is accomplished via a 3 byte sequence Serial address with write command Register address Register data The read operation is accomplished via a 4 byte sequence Serial address with write command Register address Serial address with read command Register data RANDOM REGISTER WRITE PROCEDURE SJo fi 1111111 7 bit address register address data Acknowledge Acknowledge STOP condition START condition WRITE command Acknowledge RANDOM REGISTER READ PROCEDURE 7 bit address register address 7 bit address data Acknowledge Acknowledge Acknowledge START condition WRITE command READ condition NO Acknowledge STOP condition Figure 3 Serial Interface Protocol The x is the optional 4 MSB bit address code that is set by the ADDR pin and is provided to allow a dual transmitter single controller configuration that will enable multi channel surround s
52. Micro Inc 22391 Gilberto Suite D Rancho Santa Margarita CA 92688 Tel 949 713 4000 www ktmicro com Fax 949 713 404 Copyright 2006 KT Micro Inc e KTMicro KT0801 Operation Condition Table 1 Operation Condition Parameter IO Regulator Supply IOVDD RelativetoGND 16 36 Operating Temp Note 1 When LDO enabled no external voltage should be applied to this 1 8V supply Specifications and Features Table 2 FM Transmitter Functional Parameters Unless otherwise noted TA 30 85 C IOVDD 1 6 3 6 V with LDO enabled Fin 1 kHz Parameter Symbol Test Operating Max Units FM Frequency Range ___ Pin Pinio 108 MHz Current Consumption Pin 1 with PA power amp at default power mode 1 Standby Current Signal to Noise Ratio Vin 0 7 Vp p Gin 0 Total Harmonic Distortion Vin 0 7 Vp p Gin 0 Left Right Channel Balance Via 0 Stereo Separation Left lt gt Right Vin 0 7 Vp p Gin 0 Sub Carrier Rejection Ratio Vac Gi 0 6 dB Input Swing Vi Singleendedinpt 03 12 PGA Range for Audio Input PGA Gain Step for Audio Input Required Input Common Mode Pin 4 6 Voltage when DC coupled Power Supply Rejection PORR IOVDD 19959V J 40 Ground Bounce Rejection GSRR IOVDD 19 36V 40 dB Input Resistance Audio Input Input Capacitance Audio Input
53. Network Circuit Using a 1 8 in 3 5 mm stereo headphone jack the control switch is closed when no plug is inserted When closed the 100 1 divider pulls the SE BTL input low When a plug is inserted the 1 kQ resistor is disconnected and the SE BTL input is pulled high When the input goes high the OUT amplifier is shut down causing the speaker to mute open circuits the speaker The OUT amplifier then drives through the output capacitor Co into the headphone jack HP LINE operation The HP LINE input controls the internal input multiplexer MUX Refer to the block diagram in Figure 29 This allows the device to switch between two separate stereo inputs to the amplifier For design flexibility the HP LINE control is independent of the output mode SE or BTL which is controlled by the aforementioned SE BTL pin To allow the amplifier to switch from the LINE inputs to the HP inputs when the output switches from BTL mode to SE mode simply connect the SE BTL control input to the HP LINE input When this input is logic high the RHPIN and LHPIN inputs are selected When this terminal is logic low the RLINEIN and LLINEIN inputs are selected This operation is also detailed in Table and the trip levels for a logic low Vi or logic high be found in the recommended operating conditions table on page 4 TEXAS INSTRUMENTS www ti com TPA6011A4 SLOS392 FEBRUARY 2002 APPLICATION INFORMATION shutdown modes
54. Note that the efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in a nearly flat internal power dissipation over the normal operating range Note that the internal dissipation at full output power is less than in the half power range Calculating the efficiency for a specific system is the key to proper power supply design For a stereo 1 W audio system with 8 0 loads and a 5 V supply the maximum draw on the power supply is almost 3 25 W Table 5 Efficiency vs Output Power in 5 V 8 O BTL Systems Output Power Efficiency Peak Voltage Internal Dissipation W 26 V W aari T High peak voltages cause the THD to increase A final point to remember about Class AB amplifiers either SE or BTL is how to manipulate the terms in the efficiency equation to utmost advantage when possible Note that in equation 8 Vpp is in the denominator This indicates that as Vpp goes down efficiency goes up crest factor and thermal considerations Class AB power amplifiers dissipate a significant amount of heat in the package under normal operating conditions Atypical music CD requires 12 dB to 15 dB of dynamic range or headroom above the average power output to pass the loudest portions of the signal without distortion In other words music typically has a crest factor between 12 dB and 15 dB When determining the optimal ambient operating temperature the internal dissipated
55. PA6011A4 and maximum ambient temperatures is shown in Table 6 Table 6 TPA6011A4 Power Rating 5 V 3 O Stereo PEAK OUTPUT POWER POWER DISSIPATION MAXIMUM AMBIENT AVERAGE OUTPUT FOWER W Channel TEMPERATURE TW 6 4 f ewes os x 58 s Table 7 TPA6011A4 Power Rating 5 V 8 O Stereo POWER DISSIPATION MAXIMUM AMBIENT PEAK OUTPUT POWER W AVERAGE OUTPUT POWER W Channel TEMPERATURE The maximum dissipated power is reached at much lower output power level for an 8 Q load than for a 3 Q load As a result this simple formula for calculating may be used for an 8 Q application P 11 However in the case of 3 Q load the occurs at a point well above the normal operating power level The amplifier may therefore be operated at a higher ambient temperature than required by the PD max formula for a 3 O load TEXAS INSTRUMENTS www ti com TPA6011A4 SLOS392 FEBRUARY 2002 APPLICATION INFORMATION crest factor and thermal considerations continued The maximum ambient temperature depends on the heat sinking ability of tne PCB system The derating factor for the PWP package is shown in the dissipation rating table Use equation 12 to convert this to ER 1 zd JA Derating Factor 0 022 45 C W 12 To calculate maximum ambient temperatures first consider that the numbers from the dissipation graphs
56. POWER 10 10 Vpp 5V 5 RL 40 P 5 Gain 20 dB m BTL 2 2 1 1 5 0 5 20 kHz S 05 2 0 2 1 kHz 2 0 2 20 Hz 5 0 05 8 0 05 5 0 02 gt 002 0 01 0 01 002 0 05 01 02 05 1 2 5 E Po Output Power W Figure 7 i vi TEXAS INSTRUMENTS www ti com Po Output Power W Figure 6 vs OUTPUT POWER 10 TOTAL HARMONIC DISTORTION NOISE BTL 5 80 Gain 20 dB BTL 20 kHz 1 kHz Hz 0 02 0 05 0 1 02 0 5 Output Power W Figure 8 1 2 5 vs vs OUTPUT POWER OUTPUT VOLTAGE 5 10 10 I I G ar 5 Vpp 5 V m Vpp 5V iu DD 2 5 RL 320 1 Gain 14 dB 9 Gain 14 dB 2 2 SE 1 05 S 5 5 5 02 o 95 o o 02 0 05 E 20 Hz E 0 1 5 0 02 T oo 5 o 20kHz 5 005 0 005 0 02 DES 0 002 0 01 0 001 10m 50m 100 200 0 500 1 1 5 2 Output Power W Vo Output Voltage rms Figure 9 Figure 10 CLOSED LOOP RESPONSE CLOSED LOOP RESPONSE 40 180 40 180 Vpp 5 1 30
57. R pH PWMB VDDC 53 PWMD2 GND E AVDD PWM OF od AE u RS E 4 Ds d od i 1 Ls 7 RE F alls alla In coe CEN we t Z lt TILLLLLEELLE amp 2 2 Version 0 1 4 11 22 2005 Copyright 2005 MStar Semiconductor Inc All rights reserved MST720A MST720A A sta Small Size LCD TV Processor with Video Decoder Preliminary Data Sheet Version 0 1 semiconductor mnn PIN DESCRI PTI ON Analog Interface Function CVBSIYC Mode Clamp Voltage Bypass REM internal ADC Bottom De coupling Pin REP Internal ADC Top De coupling Pin fo Analog Input Analog Chroma Input for TV S Videol Analog Composite Input of TV 54 C1I NM Analog Input Reference Ground for Analog Chroma Input of TV S Videol 7 Analog Composite Input of TV 54 YS1INP Analog Input Analog Luma Input of TV S Videol Analog Composite Input of TV CVBS3 511 Analog Input Reference Ground for Analog Luma Input of TV 5 1 cvesin HSYNCIN Trigger Analog Output Blue Channel Output 4 0 Vp p REFM DAC DAC Bottom Reference Voltage Decoupling Cap to Ground REFP DAC DAC Top Reference Voltage Decoupling Cap luF to a TCON 15 1 Output TCON ITCONOuput sss 75 61
58. RI SI OUT OF THE APPLI CATI ON OR USER OF ANY PRODUCT OR CIRCUIT DESCRI BED HEREIN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS Electrostatic charges accumulate on both test equipment and human body and can discharge without detection MST720A comes with ESD protection circuitry however the device may be permanently damaged when subjected to high energy discharges The device should be handled with proper ESD precautions to prevent malfunction and performance degradation REVI SION HISTORY Document Description MST720A ds 01 Initial release Nov 2005 9 11 22 2005 Copyright 2005 MStar Semiconductor Inc All rights reserved Version 0 1 MST720A MST720A A sta Small Size LCD TV Processor with Video Decoder Preliminary Data Sheet Version 0 1 46111 lt 1141014 MECHANICAL DIMENSIONS 7 DU Plane gt Inch _ BES INEI ES GE EIE s 1 35 140 1 45 10 053 0 055 0 057 neum 139 EIE pues uem 16 00 BSC 0 630 BSC 0 50 BSC 0 020 BSC 12 00 0 472 1 00 Ref 0 039 Ref 0 003 R1 o20 ooos 020 Version 0 1 10 11 22 2005 Copyright 2005 MStar Semiconductor Inc All rights reserved
59. S i CONS AMP OUT L 3 SPL TH ND SPR CON SP AMP OUT R icd T 7 2220 VIDEO 0000 6A CVBS RT1 OR l l AUDIO PA AUDIO AUDIO 5 VCCSV s AF_OUT an TV 5V TUNER 5 L RT9 100 use dh i 2 cvs 1 E SV TV DGND 5 CR53 3904 TV OUT 2 CT7 F400u 6 3V 6 0 2 5 E m HK NZ 1 lt I2CSCL 3 DGND RASA 3008 KI2CSDA 3 VCC5V RT16 QT2 T4 l Ah 100 4 DGND 3904 AV1 OUT v l l l l l l DGND TV 239 L AV C 77 AVITV 3 gt U10 VCC12V 5V TUNER T LT4 10805 REIS ZT ATul25V BAOSSFP gt gt TV_CVBS 2 RT21 UTT 51 51 51 510 CT14 TS 00u 10v 0 1uF S2B S2C S2D 2 1 4 3 son 0 3 IN DB DC DD ERN x ist VCC5V L5 TV IVY AV 10805 RX5 470 RT17 VOUT ey our 29 27 T 10u 6 3 bur 10 3906 D4 RT18 75 VCC12V o
60. Service Manual 1 Schematic Circuit Diagram 2 Critical Commpoents List 3 IC Date Sheet amp IC Description 4 Service Tools and Equipment VDD LCD EE LCD CN2 E AVSS yes 22 AVDD r vo SG 23 VG vRSSVR 2 H enp 20 r 19 5 CPH1 CLK2 CLK2 18 5 CPH2 8 lt GLKS 17 lt lt STH1 16 STHR STH2 955 2 15 STHL OEH 14 o B OEH MOD 13 RIL 12 5n LIR VCOM 11 VCOM 10 VCOM OEV1 9 OEV 4 UID 8 E STV2 8 STV1 5 STR ven VGLGUT ad vai 21 VCG VCOMDC 1 3V VCOMAV 7 0V Bottom Contact R81 NC R83 NC R L R75 1K i L Q9 3904 VCOMOUT eee RX1 NC R84 NC 2N3904 N RX3 4 7K VCC5V 9 R74 4 7K LED VEE_LCD VDD_LCD D R52 47K L23 FB30R vecsv nn __ C85 T t0u 6 3V 0 1uF VCC5V VCCP VCOMCOM e 9 L24 FB30R 9 toe R Y R77 07 gt 10uF 16V 12K 1 8 10R H vcc AKT T2 7 R79 Ta NY 08251 L5 VEE 1 2 T 0 1uF 180p R80 Zl 3414 SOP8 1K5 C89 0 tuF ze
61. TSC PAL SECAM car TV application It receives analog NTSC PAL SECAM CVBS and S Video inputs from TV tuners DVD or VCR sources including weak and distorted signals Automatic gain control AGC and 8 bit 3 channel A D converters provide high resolution video quantization With automatic video source and mode detection users can easily switch and adjust variety of signal sources Multiple internal adaptive PLLs precisely extract pixel clock from video source and perform sharp color demodulation Built in line buffer supports adaptive 2 D comb filter 2 D sharpening and synchronization stabler a condense manner The output format MST720A supports 3 5 7 analog TFT LCD modules Version 0 1 3 11 22 2005 Copyright 2005 MStar Semiconductor Inc All rights reserved MST720A MST720A A sta r Small Size LCD TV Processor with Video Decoder Preliminary Data Sheet Version 0 1 11601 de n Ey eee PIN DIAGRAM MST720A 3 QL uQ d 5 5 8 a 5 6 5 zz 5 5 a MEE GND TCON15 VCLAMP TCON14 REFM TCON13 4 TCON12 AVDD ADC TCON11 6 10 C1INM 69 TCON9 58 TCON8 YSIINM TCON7 CVBS1P 10 66 TCON6 5 E TCON4 TCON3 TCON2 8 1 DPWM 16 a VDDP AVDD_SAR GND AVSS SAR 2 ars _DPWM 19 i
62. a e dob Note These parameters are characterized but not 100 tested Programmable Microelectronics Corp 16 Issue Date September 2005 Rev 1 0 FLASH MStar PS25LV512 010 mis munku 4 1 1 1444 zz 444 TIMING DIAGRAMS RDID Timing CE 0 1 7 8 9 31 5 38 39 46 47 54 SCK FU 00000000 gt INSTRUCTION 3 Dummy Bytes NN A SI AAA 1010 10116 b X X 4 HIGH IMPEDANCE N 50 Manufacture 101 Device ID X Manufacture ID2 WREN Timing SCK omnei OOOX 51 A INSTRUCTION 0000 0110b 2 50 Timing SCK PLU LI UU LI UI V i YV VETAT S A AAAAAAAA INSTRUCTION 0000 01000 A A A AA A A A HI Z so Programmable Microelectronics Corp 17 Issue Date September 2005 Rev 1 0 FLASH tax PS25LV512 010 v L L RDSR Timing 00 1 2 3 4 5 8 7 8 9 1 13 14 SCK gt S X INSTRUCTION 0000 0101b DATA OUT HIGH IMPEDANCE
63. a the SI line followed by the byte address to be read Refer to Table 7 Upon completion any data on the SI line will be ignored The data D7 DO at the specified address is then shifted out onto the SO line If only one byte is to be read the CE line should be driven high after the data comes out The READ instruction can be continued since the byte address is automati cally incremented and data will continue to be shifted out For the PS25LV512 010 when the highest address is reached the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous READ instruction FAST READ The device is first selected by driving CE low The FAST READ instruction is followed by a 3 byte address A23 A0 and a dummy byte each bit being latched in during the rising edge of SCK Serial Clock Then the memory contents at that address is shifted out on SO Serial Output each bit being shifted out at a maximum frequency f during the falling edge SCK Serial Clock The first byte addressed can be at any location The address is automatically incremented to the next higher address after each byte of data is shifted out When the highest address is reached the address counter will roll over to the lowest address allowing the entire memory to be read with a single FAST READ instruction The FAST READ instruction is terminated by driving CE high PAGE PROGRAM PG_PROG In order to program P825LV512
64. ameters operation status mode and power controls which can be accessed by the internal digital controller state machines and external micro controllers through the serial interface All registers are 8 bits wide Control logics are active high unless specifically noted SELO Address 0x00 Default 0x81 0x81 CHSEL 7 0 FM Channel Selection 7 0 definition Channel selection code 0 to 108 MHz with 100 kHz step 0x000 corresponds to 0x001 corresponds to 100 kHz and so on Address 0x01 Default 0x03 7 6 RW 0x0 RFGAIN 1 0 Transmission Range Adjust 00 Lowest Range 01 Low Range 10 High Range 11 Highest Range Copyright 2006 KT Micro Inc 5 KTMicro KT0801 Inc 5 3 RW PGA 2 0 Input Audio Gain Control 111 1248 110 101 4dB 100 000 0dB 001 4dB 010 8dB 011 12dB CHSEL 10 8 SIG PROC Address 0x02 Default 0x00 Default 0x0 RW AM Software control of Mute 1 MUTE Enable 0 MUTE Disable RW PLTADJ Pilot Tone Amplitude Adjustment 1 Amplitude high 0 Amplitude low 1 RW RW PHTCNST Pre Emphasis Time Constant Set FTT T 0 7505 USA Japan PA PWR Address 0x13 Default 0x00 7 RW PA HI PW PA Power amplifier power combined with CH SEL 1 7 6 to set up transmission range 1 Enable high power 0 Disable high power 60 Rw joo Reserved Chip Enable and Mode Control Pin 9 and 10 There are 2 external Pi
65. antage from a performance standpoint is the load impedances are typically small which drives the low frequency corner higher degrading the bass response Large values of are required to pass low frequencies into the load Consider the example where a of 330 uF is chosen and loads vary from Q 4 0 8 32 0 10 and 47 Table 4 summarizes the frequency response characteristics of each configuration Table 4 Common Load Impedances Vs Low Frequency Output Characteristics in SE Mode 10 000 Q 330 uF 0 05 Hz 47 000 Q 330 uF 0 01 Hz As Table 4 indicates most of the bass response is attenuated into a 4 Q load an 8 Q load is adequate headphone response is good and drive into line level inputs a home stereo for example is exceptional using low ESR capacitors Low ESR capacitors are recommended throughout this applications section A real as opposed to ideal capacitor can be modeled simply as a resistor in series with an ideal capacitor The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit The lower the equivalent value of this resistance the more the real capacitor behaves like an ideal capacitor TEXAS INSTRUMENTS www ti com 25 TPA6011A4 SLOS392 FEBRUARY 2002 APPLICATION INFORMATION bridged tied load versus single ended lode 26 Figure 35 shows a Class AB audio power amplifier APA in a BTL configuration The TPA6011A4 BTL amplifier c
66. are per channel so the dissipated power needs to be doubled for two channel operation Given JA the maximum allowable junction temperature and the total internal dissipation the maximum ambient temperature can be calculated using equation 13 The maximum recommended junction temperature for the TPA6011A4 is 150 C The internal dissipation figures are taken from the Power Dissipation vs Output Power graphs Pp 13 150 45 0 6 x 2 96 15 dB crest factor NOTE Internal dissipation of 0 6 W is estimated for a 2 W system with 15 dB crest factor per channel Tables 6 and 7 show that some applications require no airflow to keep junction temperatures in the specified range The TPA6011A4 is designed with thermal protection that turns the device off when the junction temperature surpasses 150 C to prevent damageto the IC Table 6 and 7 were calculated for maximum listening volume without distortion When the output level is reduced the numbers in the table change significantly Also using 8 0 speakers increases the thermal performance by increasing amplifier efficiency TEXAS INSTRUMENTS www ti com 31 TPA6011A4 SLOS392 FEBRUARY 2002 MECHANICAL DATA PWP R PDSO G PowerPAD PLASTIC SMALL OUTLINE 20 PINS SHOWN Thermal Pad See Note D 0 15 NOM t Gage Plane 4
67. ation network can be used for AOZ1041 For most cases a series capacitor and resistor network connected to the COMP pin sets the pole zero and is adequate for a stable high bandwidth control loop In the AOZ1041 FB pin and COMP pin are the inverting input and the output of internal error amplifier A series R and C compensation network connected to COMP provides one pole and one zero The pole is 2m x Cc X Gyra Where Gea is the error amplifier transconductance which is 200 10 A V is the error amplifier voltage gain which is 500 V V Cc is compensation capacitor The zero given by the external compensation network capacitor Cc and resistor Rc is located at 1 Je 2 Cc x R lt To design the compensation circuit a target crossover frequency fc for close loop must be selected The system crossover frequency is where control loop has unity gain The crossover is the 10 CONFIDENTIAL Not to be distributed or copied without the written permission of Alpha amp Omega Semiconductor Alpha amp Omega Semiconductor AOZ1041 also called the converter bandwidth Generally a higher bandwidth means faster response to load transient However the bandwidth should not be too high because of system stability concern When designing the compensation loop converter stability under all line and load condition must be considered Usually it is recommended to set the bandwidth to be equal or less than 1
68. de PMOS if the junction temperature exceeds 155 C The regulator will restart automatically under the control of soft start circuit when the junction temperature decreases to 100 C Application Information The basic AOZ1041 application circuit is show in Figure 1 Component selection is explained below Input capacitor The input capacitor must be connected to the Vix pin and PGND pin of the AOZ1041 to maintain steady input voltage and filter out the pulsing input current The voltage rating of input capacitor must be greater than maximum input voltage plus ripple voltage The input ripple voltage can be approximated by equation below f Cy Vin Vin Since the input current is discontinuous in a buck converter the current stress on the input capacitor is another concern when selecting the capacitor For a buck circuit the RMS value of input capacitor current can be calculated by gus 10 X 1 2 IN Vin if we let m equal the conversion ratio Mu Vin The relation between the input capacitor RMS current and voltage conversion ratio is calculated and shown in Fig 2 below It can be seen that when Vo is half of Vin Cin is under the worst current stress The worst current stress on is 0 5 lo CONFIDENTIAL Not to be distributed or copied without the written permission of Alpha amp Omega Semiconductor Alpha amp Omega Semiconductor AOZ1041 0 5 0
69. distortion plus noise SE _________ 9 PSRR Power supply ripple rejection BTL PSRR Power supply ripple rejection SE 8 TEXAS INSTRUMENTS 8 www ti com THD N Total Harmonic Distortion Noise BTL TPA6011A4 SLOS392 FEBRUARY 2002 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION NOISE BTL vs FREQUENCY 10 5 5 Gain 20 dB BTL 0 5 0 5 W 0 2 0 1 0 05 0 02 1 75 W 0 01 20 100 1k f Frequency Hz 10k 20k Figure 1 TOTAL HARMONIC DISTORTION NOISE BTL THD N Total Harmonic Distortion Noise BTL 96 TOTAL HARMONIC DISTORTION NOISE BTL vs FREQUENCY 10 Vpp 5V 57 40 Gain 20 dB 0 5 0 2 4 0 1 0 05 0 02 0 01 20 50 100 200 500 1k 2k f Frequency Hz 5k 10k 20k Figure 2 TOTAL HARMONIC DISTORTION NOISE SE
70. e voltage specification and ripple current rating The selected output capacitor must have a higher rated voltage specification than the maximum desired output voltage including ripple De rating needs to be considered for long term reliability CONFIDENTIAL Not to be distributed or copied without the written permission of Alpha amp Omega Semiconductor Alpha amp Omega Semiconductor AOZ1041 Output ripple voltage specification is another important factor for selecting the output capacitor In a buck converter circuit output ripple voltage is determined by inductor value switching frequency output capacitor value and ESR It can be calculated by the equation below AV M x ESR Lx where is output capacitor value and is the Equivalent Series Resistor of output capacitor When low ESR ceramic capacitor is used as output capacitor the impedance of the capacitor at the switching frequency dominates Output ripple is mainly caused by capacitor value and inductor ripple current The output ripple voltage calculation can be simplified to AV Al x l 8x f x Co If the impedance of ESR at switching frequency dominates the output ripple voltage is mainly decided by capacitor ESR and inductor ripple current The output ripple voltage calculation can be further simplified to AV Al x ESReo For lower output ripple voltage across the entire operating temperature range X
71. ep down regulator with integrated high side PMOS switch and a low side freewheeling Schottky diode It operates from a 4 5V to 16V input voltage range and supplies up to 1 5A of load current The duty cycle can be adjusted from 696 to 10096 allowing a wide range of output voltage Features include enable control Power On Reset input under voltage lockout output over voltage protection fixed internal soft start and thermal shut down The 21041 is available in SO 8 package Enable and Soft Start The AOZ1041 has internal soft start feature to limit in rush current and ensure the output voltage ramps up smoothly to regulation voltage A soft start process begins when the input voltage rises to 4 0V and voltage on EN pin is HIGH In soft start process the output voltage is ramped to regulation voltage in typically 4ms The 8ms soft start time is set internally The EN pin of the AOZ1041 is active high Connect the EN pin to VIN if enable function is not used Pull it to ground will disable the AOZ1041 Do not leave it open The voltage on EN pin must rise above 2 0 V to enable the AOZ1041 When voltage on EN pin falls below 0 8V the AOZ1041 is disabled If an application circuit requires the AOZ1041 to be disabled an open drain or open collector circuit should be used to interface to EN pin Steady State Operation Under steady state conditions the converter operates in fixed frequency and Continuous Conduction Mode CCM
72. erminal and this value is used to determine the SE gain Some audio systems require that the gain be limited in the single ended mode to a level that is comfortable for headphone listening Most volume control devices only have one terminal for setting the gain For example if the speaker gain is 20 dB the gain in the headphone channel is fixed at 14 dB This level of gain could cause discomfort to listeners and the SEMAX pin allows the designer to limit this discomfort when plugging in headphones The SEMAX terminal controls the maximum gain for single ended mode The functionality of the SEDIFF and SEMAX pin are combined to set the SE gain A block diagram of the combined functionality is shown in Figure 32 The value obtained from the block diagram for SE VOLUME is a dc voltage that can be used in conjunction with Table 2 to determine the SE gain Again the voltages listed in the table are for Vpp 5V The values must be scaled for other values of Vpp Tables 1 and 2 show a range of voltages for each gain step There is a gap in the voltage between each gain step This gap represents the hysteresis about each trip point in the internal comparator The hysteresis ensures thatthe gain control is monotonic and does not oscillate from one gain step to another If a potentiometer is used to adjust the voltage on the control terminals the gain increases as the potentiometer is turned in one direction and decreases as itis turned back the other direction
73. g an internal write cycle WRITE STATUS REGISTER WRSR The WRSR instruction allows the user to select one of four levels of protec tion for the PS25LV010 The PS25LV010 is divided into four blocks where the top quarter 1 4 top half 1 2 or all of the memory blocks can be protected locked out from write The PS25LV512 is divided into 2 blocks where all of the memory blocks can be protected locked out from write Any of the locked out blocks will therefore be READ only The locked out block and the corresponding status register control bits are shown in Table 5 The three bits BPO BP1 and WPEN are nonvolatile cells that have the same properties and functions as the regular memory cells e g WREN RDSR Programmable Microelectronics Corp 8 Issue Date September 2005 Rev 1 0 FLASH MStar PS25LV512 010 14 41111 Table 5 Block Write Protect Bits Status Register Bits Status Register Bits Bits PS25LV512 PS25LV010 Array Addresses Locked out Array Addresses Locked out Level Locked Out Block s Locked Out Block s 1 None 018000 01FFFF Block 4 010000 Block 3 4 Blocks 000000 01FFFF 1 4 Blocks 1 2 1 000000 00FFFF The WRSR instruction also allows the user to enable or disable the Write Protect WP pin through the use of the Write Protect Enable WPEN bit Hardware write protection is enabled when the WP pin
74. gic rc POR On Off Optional SDA SCL RSTB SW1 52 Antenna Stereo Audio I Line Input i 7777 Other IOVDD GND VDDs 0801 Figure 6 Typical Application configuration 1 8V systems MCU 3 3V CMOS Logic SDA SCL RSTB Antenna SW SW2 Stereo Audio Line Input KT0801 15 2MHz XTAL Figure 7 Typical Application configuration in 3 3V system Copyright 2006 KT Micro Inc KT0801 1 PIN 1 INDENT p 0 D2 L MILLIMETERS Symbols MIN NOM MAX A 0 80 0 85 0 90 AI 0 00 0 02 0 05 b 0 20 0 25 0 30 C 0 19 0 20 025 D 3 95 4 00 4 05 D2 2 65 2 70 2 75 E 3 95 4 00 4 05 E2 2 65 2 70 2 75 0 5 L 0 30 040 0 50 y 0 00 0 076 Copyright 2006 KT Micro Inc PS25LV512 PS25LV010 512 Kbit 1 Mbit 3 0 Volt only Serial Flash Memory FLASH MPistar With 33 MHz SPI Bus Interface mwa FEATURES Single Power Supply Operation Block Write Protection f f Voltage range 3 0V 3 6V The Block Protect BP1 BP0 bits allow part or entire of the memory to be configured as read only Memory Organization PS25LV512 64K x 8 512 Kbit 2 UE 1 PS25LV010 128K x 8 1 Mbit Write Protect WP pin w
75. hose indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating condition for extended periods may affected device reliability 2 Maximum DC voltage on input or I O pins 0 5 V During voltage transitioning period input or I O pins may overshoot to Vcc 2 0 for a period of time up to 20 ns Minimum DC voltage on input or I O pins are 0 5 V During voltage transitioning period input or I O pins may undershoot GND to 2 0 V for a period of time up to 20 ns DC AND AC OPERATING RANGE PS25LV512 010 0 C to 85 C 3 0V 3 6V Programmable Microelectronics Corp 12 Issue Date September 2005 Rev 1 0 FLASH MStar PS25LV512 010 v d 14 DC CHARACTERISTICS Applicable over recommended operating range from 0 to 85 Voc 43 0 V to 3 6 V unless otherwise noted meme mmm Mamme Programmable Microelectronics Corp 13 Issue Date September 2005 Rev 1 0 FLASH MStar PS25LV512 010 LLLI v d AC CHARACTERISTICS Applicable over recommended operating range from T 0 C to 85 C 43 0 V to 3 6 V SCK Low Time fen fn tri tri C 1TTL Gate and 30 pF unless otherwise noted Input Rise Time 20 ns ba
76. ificing functionality To simplify design the speaker volume level is adjusted by applying a dc voltage to the VOLUME terminal Likewise the delta between speaker volume and headphone volume can be adjusted by applying a dc voltage to the SEDIFF terminal To avoid an unexpected high volume level through the headphones a third terminal SEMAX limits the headphone volume level when a dc voltage is applied Finally to ensure a smooth transition between active and shutdown modes a fade mode ramps the volume up and down DC VOLUME CONTROL 30 20 10 0 BTL Volume 10 a 20 B SE Volume 2 40 SEDIFF Pin 20 0 V M 50 SE Volume 60 SEDIFF Pin 20 1 V 70 80 BTL Volume dB Volume V SE Volume dB Volume V SEDIFF V 90 0 05 1 15 2 25 3 35 4 45 5 Volume Pin 21 V Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters Copyright 2002 Texas Instruments Incorporated 9 5 INSTRUMENTS www ti com 1 TPA6011A4 5108392 FE
77. ill inhibit write operations to the status register Cost Effective Sector Block Architecture Uniform 4 Kbyte sectors Uniform 32 Kbyte blocks 8 sectors per block Two blocks with 32 Kbytes each 512 Kbit Four blocks with 32 Kbytes each 1 Mbit 128 pages per block Page Program up to 256 Bytes Typical 3 ms per page program time Sector Block and Chip Erase Typical 60 ms sector block chip erase time Single Cycle Reprogramming for Status Register Serial Peripheral Interface SPI Compatible Build in erase before programming Supports SPI Modes 0 0 0 and 3 1 1 High Product Endurance Guarantee 10 000 program erase cycles per single sector Minimum 10 years data retention High Performance Read 33MHz clock rate max for NORMAL READ 33MHz clock rate max for FAST READ Page Mode for Program Operations 256 bytes per page Industrial Standard Pin out and Package 8 SOIC Optional lead free Pb free packages GENERAL DESCRIPTION The PS25LV512 010 are 512 Kbit 1 Mbits 3 0 Volt only serial Flash memories These devices are designed to use a single low voltage range from 3 0 Volt to 3 6 Volt power supply to perform read erase and program operations The devices can be programmed in standard EPROM programmers as well The device is optimized for use in many commercial applications where low power and low voltage operation are essential The PS25LV512 0
78. ion the current waveform is a half wave rectified shape whereas in BTL it is a full wave rectified waveform This means RMS conversion factors are different Keep in mind that for most of the waveform both the push and pull transistors are not on atthe same time which supports the fact that each amplifier in the BTL device only draws current from the supply for half the waveform The following equations are the basis for calculating amplifier efficiency P L Efficiency of a BTL amplifier Poup 7 Where 5 YP therefore P P therefore gt L R LRMS 2 L 2 R T zd p gs PV and Pgyp Vpp pp Vg Ippavg 3n 0dt X gr cost 0 P L Therefore 2 Vpp Vp aR L substituting PL and Psup into equation 7 2 Vp Efficiency of BTL amplifier 28 02 Vp 2VppVp 4Vpp Where Vp 2P Therefore 8 n BTL 4 Vpp P Power delivered to load Vp Peak voltage on BTL load Psup Power drawn from power supply Ippavg Average current drawn from the power supply Vi RMS voltage BTL load Vpp Power supply voltage Load resistance NBTL Efficiency of a BTL amplifier 9 TEXAS INSTRUMENTS www ti com TPA6011A4 SLOS392 FEBRUARY 2002 APPLICATION INFORMATION BTL amplifier efficiency continued Table 5 employs equation 8 to calculate efficiencies for four different output power levels
79. is low and the WPEN bit is 1 Hardware write protection is disabled when either the WP5 pin is high or the WPEN bit is When the device is hardware write protected writes to the Status Register including the Block Protect bits and the WPEN bit and the locked out blocks in the memory array are disabled Write is only allowed to blocks of the memory which are not locked out The WRSR instruction is self timed to automatically erase and program BPO BP1 and WPEN bits In order to write the status register the device must first be write enabled via the WREN instruction Then the instruction and data for the three bits are entered During the internal write cycle all instructions will be ignored except RDSR instructions The PS25LV512 010 will automatically return to write disable state at the completion of the WRSR cycle Note When the WPEN bit is hardware write protected it cannot be changed back to 0 as long as the WP pin is held low Table 6 WPEN Operation Protected Protected Protected Protected Writable Writable EZI Ee NN Programmable Microelectronics Corp 9 Issue Date September 2005 Rev 1 0 FLASH MStar PS25LV512 010 a READ Reading the PS25LV512 010 via the SO Serial Output pin requires the following sequence After the CE line is pulled low to select a device the READ instruction is transmitted vi
80. l is held high This puts the negative outputs in a high impedance state and effectively reduces the amplifier s gain by 6 dB BTL amplifier efficiency Class AB amplifiers are inefficient The primary cause of these inefficiencies is voltage drop across the output stage transistors There are two components of the internal voltage drop One is the headroom or dc voltage drop that varies inversely to output power The second component is due to the sinewave nature of the output The total voltage drop can be calculated by subtracting the RMS value of the output voltage from Vpp The internal voltage drop multiplied by the RMS value of the supply current Ipprms determines the internal power dissipation of the amplifier An easy to use equation to calculate efficiency starts out as being equal to the ratio of power from the power supply to the power delivered to the load To accurately calculate the RMS and average values of power in the load and in the amplifier the current and voltage waveform shapes must first be understood see Figure 37 TEXAS INSTRUMENTS www ti com 27 TPA6011A4 5108392 FEBRUARY 2002 APPLICATION INFORMATION BTL amplifier efficiency continued 28 V IDD eo Figure 37 Voltage and Current Waveforms for BTL Amplifiers Although the voltages and currents for SE and BTL are sinusoidal in the load currents from the supply are very different between SE and BTL configurations In an SE applicat
81. lock address is automatically determined if any address within the block is selected The BLOCK ERASE instruction is internally controlled it will automatically be timed to completion During this time all commands will be ignored except instruction The PS25LV512 010 will automatically return to the write disable state at the completion of the BLOCK ERASE cycle CHIP ERASE alternative to the SECTOR BLOCK ERASE the CHIP ERASE instruction will erase every byte in all blocks that are not locked out First the device must be write enabled via the WREN instruction Then the CHIP ERASE instruction can be executed The CHIP ERASE instruction is internally controlled it will automatically be timed to completion The CHIP ERASE cycle time maximum is 100 miliseconds During the internal erase cycle all instructions will be ignored except RDSR The PS25LV512 010 will automatically return to the write disable state at the completion of the CHIP ERASE HOLD The HOLD pin is used in conjunction with the CE pin to select the PS25LV512 010 When the device is selected and a serial sequence is underway HOLD pin can be used to pause the serial communication with the master device without resetting the serial sequence To pause the HOLD pin must be brought low while the SCK pin is low To resume serial communication the HOLD pin is brought high while the SCK pin is low may still toggle during HOLD Inputs to the SI pin will
82. m command to program completion Note These parameters are characterized and are not 100 tested RELIABILITY CHARACTERISTICS Data Retention X Mears JEDEC Standard A103 ESD Human Body Model 2 000 o JEDEC Standard A114 ESD Machine Model Volts Vols JEDEC Standard A115 Standard Standard A115 Latch Up 100 loc ANNI JEDEC Standard 78 Note 1 These parameters are characterized and are not 100 tested 2 Preliminary specification only and will be formalized after cycling qualification test Programmable Microelectronics Corp 21 Issue Date September 2005 Rev 1 0 PS25LV512 010 FLASH U PS25LV512 010 PACKAGE TYPE INFORMATION 8S Top View A 5 00 4 80 q 4 00 3 80 i 6 20 lt 5 80 4 End View Ui 7 J ANKE 0 25 0 19 1 27 0 40 22 Programmable Microelectronics Corp Side View 1 27 BSC 0 25 AM 0 10 175 135 69 8 Pin JEDEC Small Outline Integrated Circuit SOIC Package measure in millimeters Issue Date September 2005 Rev 1 0 m FLASH MStar PS25LV512 010 4 44 a 14 41111 REVISION HISTORY September 2005 Normal Production Spec Programmable Microelectronics Corp 23 Issue Date Se
83. me page will remain unchanged If more than 256 bytes of data are provided the address counter will roll over on the same page and the previous data provided will be replaced The same byte cannot be reprogrammed without erasing the whole sector block first The PS25LV512 010 will automatically return to the write disable state at the completion of the PROGRAM cycle Note If the device is not write enabled WREN the device will ignore the Write instruction and will return to the standby state when CE is brought high A new CE falling edge is required to re initiate the serial communication Table 7 Address Key Programmable Microelectronics Corp 10 Issue Date September 2005 Rev 1 0 FLASH Fis PS25LV512 010 Pro NR ta waa 1 E E 2 00 SECTOR ERASE ERASE Before a byte be reprogrammed the sector block which contains the byte must be erased In order to erase the PS25LV512 010 two separate instructions must be executed First the device must be write enabled via the WREN instruction Then the SECTOR ERASE or BLOCK ERASE instruction can be executed Table 8 Block Addresses Block Address PS25LV512 Block PS25LV010 Block 000000 to 007FFF Block 1 Block 1 008000 to OOFFFF Block 2 Block 2 010000 to 017FFF N A Block 3 018000 to 01FFFF N A Block 4 The BLOCK ERASE instruction erases every byte in the selected block if the block is not locked out B
84. n a Chip SoC High Fidelity Stereo Audio FM Transmitter SNR 2 68 dB Stereo Separation gt 50dB International compatible 76MHz 108MHz Minimal External Component Requirement Crystal optional in lieu of direct feeding of an external clock Ultra Low Power Consumption lt 12 6 mA operation current lt 1 pA standby current Dual Reference Clock Setup Supports both 7 6MHz and 15 2MHz Small Form factor 24 pin 4x4x0 9 mm Pb free and RoHS Compliant Simple Interface Single 1 8V in lieu of 1 6 3 6V regulator feed Industry standard 2 wire C MCU interface compatible Advanced Digital Audio Signal Processing On chip 20 bit AZ Audio ADC On chip DSP core On chip 24dB PGA Automatic calibration against process and temperature On Chip LDO low drop out regulator Accommodates 1 6V 3 6V supply Programmable transmit level Programmable pre emphasis 50 75 us Applications MP3 Players Cellular Phones PDAs Portable Personal Media player Laptop Computers Wireless Speakers Rev 1 1 Information furnished by KT Micro is believed to be accurate and reliable However no responsibility is assumed by KT Micro for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of KT Micro
85. nded environmental conditions Several layout tips are listed below for the best electric and thermal performance 1 Do not use thermal relief connection to the VIN and the PGND pin Pour a maximized copper 11 CONFIDENTIAL Not to be distributed or copied without the written permission of Alpha amp Omega Semiconductor Alpha amp Omega Semiconductor AOZ1041 area to the PGND pin and the VIN pin to help thermal dissipation 2 Input capacitor should be connected to the VIN pin and the PGND pin as close as possible 3 A ground plane is preferred If a ground plane is not used separate PGND from AGND and connect them only at one point to avoid the PGND pin noise coupling to the AGND pin 4 Make the current trace from LX pins to L to Co to the PGND as short as possible 5 Pour copper plane on all unused board area and connect it to stable DC nodes like VIN PGND or SGND 6 Keep sensitive signal trace away from switching node LX The copper pour area connected to the LX pin should be as small as possible to avoid the switching noise on the LX pin coupling to other part of circuit 7 The AOZ1041 EVA document provides an example of proper layout techniques AOZ1041 Datasheet Rev 0 4 12 CONFIDENTIAL Not to be distributed or copied without the written permission of Alpha amp Omega Semiconductor Monolithic Digital Stereo FM Transmitter Radio Station on a Chip KT0801 Features Professional Grade System o
86. ns SW1 and SW2 Pin 9 and 10 which enable chip and define the supply voltage level and clock source of the chip The definition is shown in Table 4 Table 4 Pin SW1 and SW2 vs Chip Supply and Clock Source Chip Mode Chip Supply Clock Source Disabled Bypass XTAL Lo V 1 6 2 0 LDO Disabled Lo V 1 6 2 0V XTAL LDO Enabled Hi V 1 6 3 6V XTAL Application note 1 In low supply mode 1 6 2 0V and operate with LDO disabled tie SW2 to ground and use SW1 as the chip enable For high supply mode and operate with LDO enabled short SW2 to SW1 and use both as chip enable Copyright 2006 KT Micro Inc L gt KTMicro KT0801 Inc Application note 2 In low supply mode IOVDD Pin 1 shall be tied to the system supply which is equal to the logic level High from the MCU system Typical Application Circuits The 08001 be integrated in a wide range of systems by requiring only a single power supply Figure 5 shows a configuration with zero external components Figure 6 and Figure 7 show two typical configurations in 1 8V and 3 3 Vsystems respectively MCU 1 8V CMOS Logic rc POR On Off SDA SCL RSTB SW1 SW2 Antenna INL Stereo Audio Line Input 0801 Other IOVDD GND TI 7 6MHz Clock Figure 5 Zero external components configuration in 1 8V systems Copyright 2006 KT Micro Inc KT0801 MCU 1 8V CMOS Lo
87. nty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed Tl assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfai
88. onsists of two Class AB amplifiers driving both ends of the load There are several potential benefits to this differential drive configuration but initially consider power to the load The differential drive to the speaker means that as one side is slewing up the other side is slewing down and vice versa This in effect doubles the voltage swing on the load as compared to a ground referenced load Plugging 2 x into the power equation where voltage is squared yields 4x the output power from the same supply rail and load impedance see equation 5 5 ms 22 2 Power ms vor gt i RL 2 VO PP Figure 35 Bridge Tied Load Configuration In a typical computer sound channel operating at 5 V bridging raises the power into 8 0 speaker from a singled ended SE ground reference limit of 250 mW to 1 W In sound power that is a 6 dB improvement which is loudness that can be heard In addition to increased power there are frequency response concerns Consider the single supply SE configuration shown in Figure 36 A coupling capacitor is required to block the dc offset voltage from reaching the load These capacitors can be quite large approximately 33 uF to 1000 uF so they tend to be expensive heavy occupy valuable PCB area and have the additional drawback of limiting low fre
89. ound applications ADDR must be externally tied to ground or IOVDD for low or high setup respectively The serial controller supports slave mode only Any register can be addressed randomly Slave Mode Protocol With reference to the clocking scheme shown in Figure 4 the serial interface operates in the following manner Copyright 2006 KT Micro Inc L gt KTMicro KT0801 Acknowledge Start Stop Condtion Condtion Figure 4 Serial Interface Slave Mode Protocol A START condition is defined as a HIGH to LOW transition on the data line while the SCLK line is held high After this has been transmitted by the controller Master the bus is considered busy The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the 8th bit tells whether the master is receiving data from the slave or transmitting data to the slave When ADDR is set to 0 tied to ground the write address is Ox6C and the read address is 0x6D Data transfer with acknowledge is obligatory The transmitter must release the SDA line during the acknowledge pulse The receiver must then pull the SDA line LOW so that it remains stable during the HIGH period of the acknowledge clock pulse A receiver that has been addressed is obligated to generate an acknowledge signal after each byte of data has been received Register Bank The register bank stores channel frequency codes calibration par
90. pass capacitor will begin charging Once the bypass voltage reaches the final value of Vpp 2 the gain increases 2 dB steps from the lowest gain level to the gain level set by the dc voltage applied to the VOLUME SEDIFF and SEMAX pins TEXAS INSTRUMENTS www ti com 19 TPA6011A4 SLOS392 FEBRUARY 2002 APPLICATION INFORMATION FADE operation continued In the fade off mode the amplifier stores the gain value prior to starting the shutdown sequence The output of the amplifier immediately drops to Vpp 2 and the bypass capacitor begins a smooth discharge to ground When shutdown is released the bypass capacitor charges up to Vpp 2 and the channel gain returns immediately to the value stored in memory Figure 31 below is a waveform captured at the output during the shutdown sequence when the part is in the fade off mode The gain is set to the highest level and the output is at Vpp when the amplifier is shut down The power up sequence is different from the shutdown sequence and the voltage on the FADE pin does not change the power up sequence Upon a power up condition the TPA6011A4 begins in the lowest gain setting and steps up 2 dB every 2 clock cycles until the final value is reached as determined by the dc voltage applied to the VOLUME SEDIFF and SEMAX pins 4 Device Shutd ROUT 1 4 Device Shutdown ROUT
91. power at the average output power level must be used From the TPA6011A4 data sheet one can see that when the TPA6011A4 is operating from a 5 V supply into 3 Q speaker that 4 W peaks are available Use equation 9 to convert watts to dB 4W Pw Pup bu uem 10100 6 9 Subtracting the headroom restriction to obtain the average listening level without distortion yields 6 dB 15 dB 9 dB 15 crest factor 6 dB 12 dB 6 GB 12 crest factor 6 dB 9 dB 3 dB 9 crest factor 6 dB 6 dB 0 dB 6 dB crest factor 6 dB 3 dB 3 dB 3 crest factor TEXAS INSTRUMENTS www ti com 29 TPA6011A4 SLOS392 FEBRUARY 2002 APPLICATION INFORMATION crest factor and thermal considerations continued 30 To convert dB back into watts use equation 10 PdB 10 edo B p 10 63 mW 18 db crest factor 125 mW 15 db crest factor 250 mW 12 db crest factor 500 mW 9 db crest factor 1000 mW 6 db crest factor 2000 mW 3 db crest factor This is valuable information to consider when attempting to estimate the heat dissipation requirements for the amplifier system Comparing the worst case which is 2 W of continuous power output with a 3 dB crest factor against 12 dB and 15 dB applications significantly affects maximum ambient temperature ratings for the system Using the power dissipation curves for a 5 V 3 Q system the internal dissipation in the T
92. ptember 2005 Rev 1 0 35 TEXAS TPA6011A4 INSTRUMENTS MA SLOS392 FEBRUARY 2002 2 W STEREO AUDIO POWER AMPLIFIER WITH ADVANCED DC VOLUME CONTROL FEATURES DESCRIPTION Advanced DC Volume Control With 2 dB Steps From 40 dB to 20 dB Fade Mode Maximum Volume Setting for SE Mode Adjustable SE Volume Control Referenced to BTL Volume Control 2W Into 3 Q Speakers Stereo Input MUX Differential Inputs APPLICATIONS Notebook PC LCD Monitors Pocket PC APPLICATION CIRCUIT ROUT Power Supply PVpp Ci Right HP RHPIN Audio Source 6 VOLUME Right Line RLINEIN Audio Source 3 RIN SEMAX Cs Vpp AGND EIN BYPASS Left Line 7 Audio Source EEINEIN FADE Left HP Audio Source LHPIN SHUTDOWN Power Supply PVpp LOUT IT A LOUT PGND 100 100 In From DAC or Potentiometer DC Voltage System Control lt Cc Right Speaker 1kQ Headphones 1kQ Left Speaker The TPA6011A4 is a stereo audio power amplifier that drives 2 W channel of continuous RMS power into a 3 Q load Advanced dc volume control minimizes external components and allows BTL speaker volume control and SE headphone volume control Notebook and pocket PCs benefit from the integrated feature set that minimizes external components without sacr
93. quency performance of the system This frequency limiting effect is due to the high pass filter network created with the speaker impedance and the coupling capacitance and is calculated with equation 6 6 TEXAS INSTRUMENTS www ti com TPA6011A4 SLOS392 FEBRUARY 2002 APPLICATION INFORMATION bridged tied load versus single ended lode continued For example 68 uF capacitor with an 8 Q speaker would attenuate low frequencies below 293 Hz The BTL configuration cancels the dc offsets which eliminates the need for the blocking capacitors Low frequency performance is then limited only by the input network and speaker response Cost and PCB space are also minimized by eliminating the bulky coupling capacitor Vopr ES ic g E UN V 4 Vo PP fc Figure 36 Single Ended Configuration and Frequency Response Increasing power to the load does carry a penalty of increased internal power dissipation The increased dissipation is understandable considering that the BTL configuration produces 4x the output power of the SE configuration Internal dissipation versus output power is discussed further in the crest factor and thermal considerations section single ended operation In SE mode see Figure 36 the load is driven from the primary amplifier output for each channel OUT The amplifier switches single ended operation when the SE BTL termina
94. r Figure 28 Typical TPA6011A4 Application Circuit Using Differential Inputs SE BTL operation The ability of the TPA6011A4 to easily switch between BTL and SE modes is one of its most important cost saving features This feature eliminates the requirement for an additional headphone amplifier in applications where internal stereo speakers are driven in BTL mode but external headphone or speakers must be accommodated Internal to the TPA6011A4 two separate amplifiers drive OUT and OUT The SE BTL input controls the operation of the follower amplifier that drives LOUT and ROUT When SE BTL is held low the amplifier is on and the TPA6011A4 is in the BTL mode When SE BTL is held high the OUT amplifiers are a high output impedance state which configures the TPA6011A4 as an SE driver from LOUT and ROUT is reduced by approximately one third in SE mode Control of the SE BTL input can be from a logic level CMOS source or more typically from a resistor divider network as shown in Figure 29 The trip level for the SE BTL input can be found in the recommended operating conditions table on page 4 TEXAS INSTRUMENTS is www ti com TPA6011A4 SLOS392 FEBRUARY 2002 APPLICATION INFORMATION SE BTL operation continued R 5 MUX 22 HP LINE Y 30 uF L Figure 29 TPA6011A4 Resistor Divider
95. r and deceptive business practice TI is not responsible or liable for such altered documentation Resale of products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2002 Texas Instruments Incorporated Service Tools and Equipment Application Name General DVD testing disk General tools screwdriver ect AV Cable DVD player Special Signal Generator Oscillograph Probe
96. te of two clock cycles per step With a nominal internal clock frequency of 58 Hz this equates to 34 ms 1 24 Hz per step The gain steps down until the lowest gain step is reached The time it takes to reach this step depends on the gain setting prior to placing the device in shutdown For example if the amplifier is in the highest gain mode of 20 dB the time it takes to ramp down the channel gain is 1 05 seconds This number is calculated by taking the number of steps to reach the lowest gain from the highest gain or 31 steps and multiplying by the time per step or 34 ms After the channel gain is stepped down to the lowest gain the amplifier begins discharging the bypass capacitor from the nominal voltage of Vpp 2 to ground This time is dependent on the value of the bypass capacitor For 0 47 uF capacitor that is used in the application diagram in Figure 27 the time is approximately 500 ms This time scales linearly with the value of bypass capacitor For example if a 1 uF capacitor is used for bypass the time period to discharge the capacitor to ground is twice that of the 0 47 uF capacitor or 1 second Figure 30 below is a waveform captured at the output during the shutdown sequence when the part is in fade on mode The gain is set to the highest level and the output is at Vpp when the amplifier is shut down When a logic high is placed on the SHUTDOWN pin and the FADE pin is still held low the device begins the start up process The by
97. tor Protection Features The AOZ1041 has multiple protection features to prevent system circuit damage under abnormal conditions Over Current Protection OCP The sensed inductor current signal is also used for over current protection Since the 21041 employs peak current mode control the COMP pin voltage is proportional to the peak inductor current The COMP pin voltage is limited to be between 0 4V and 2 5V internally The peak inductor current is automatically limited cycle by cycle When the output is shorted to ground under fault conditions the inductor current decays very slow during a switching cycle because of V 0V To prevent catastrophic failure secondary current limit is designed inside the AOZ1041 The measured inductor current is compared against a preset voltage which represents the current limit between 2 5A and 3 6A When the output current is more than current limit the high side switch will be turned off and EN pin will be pulled down The converter will initiate a soft start once the over current condition disappears Power On Reset POR A power on reset circuit monitors the input voltage When the input voltage exceeds 4V the converter starts operation When input voltage falls below 3 7V the converter will be shut down 21041 Datasheet Rev 0 4 Thermal Protection An internal temperature sensor monitors the junction temperature It shuts down the internal control circuit and high si
98. uH 2 3A 1N5819HW L s 2 U2 _ 1540 470 10 1206 ootuF 5 IN R8 62k CTR LED 4 EN mH GND 15k Io If AVDD_SAR 5V 16 1 2V 4R 300mA If AVDD SAR 2 5V Io 0 6V 4R 150mA TAE OPE VCC5V AVDD_DPWM AYDD_SAR RQ c This Part is For CCFL Backlight NC if use LED BL Update 2006 03 20 for CCFL Protection Update 2006 02 04 for CCFL power consumption for 720A for 720C 7 NC CON VCC3 3V 1 al 3 3 27 MMBT3904 12 C13 lt R13 6 3 HoOuF 6 3v 0 146 EC5 0 2 0 0 1 R14 43K 4K7 4 14 VCCN5V 9 R12 1008 C9 99 La0uF A46V 1206 D10 C16 0 1uF T 1 BAV99 EC VCC5V VCC1 8V 9 14 R15 c18 c19 510R 0 tuF WTuF G3V 1 PWM1 gt PWM1 R17 1K 1 1 1 1 1 R22 0 tuF Tiu 30K C1206 I 024 25 26 0 1 22628 R26 1nF 22K f R28 228 D15 D17 BAV99 Bavo f T
99. urrent flows in the first loop when the high side switch is on The second loop starts from inductor to the output capacitors and load to the PGND pin of the AOZ1041 to the LX pins of the AOZ1041 Current flows in the second loop when the low side diode is on In PCB layout minimizing the two loops area reduces the noise of this circuit and improves efficiency A ground plane is strongly recommended to connect input capacitor output capacitor and PGND pin of the AOZ1041 In the AOZ1041 buck regulator circuit the two major power dissipating components are the AOZ141 and output inductor The total power dissipation of converter circuit can be measured by input power minus output power Poa The power dissipation of inductor can approximately calculated by output current and DCR of inductor R indcutor inductor 1 1 The actual junction temperature can be calculated with power dissipation in the AOZ1041 and thermal impedance from junction to ambient niis Pea The maximum junction temperature of 21041 is 150 C which limits the maximum load current capability Please see the thermal de rating curves for the maximum load current of the AOZ1041 under different ambient temperature The thermal performance of the AOZ1041 is strongly affected by the PCB layout Extra care should be taken by users during design to ensure that the IC will operate under the recomme
100. wire serial bus interface for configuration Impulse Response filter setup Differential 3 band peaking engine Built in step down PWM ircuits for input 2 5V Luminance 7 i nprove a adjusting circuits Chromin 1 E 256 programmable Black Level E BEEJ 12 bit color White Level Extension a Favor 3 channek ks Engin Supports i th ion d s ectrul is J 960x234 1200x234 1400x234 and more Optional 3 3 5V pads with F y orts vario n 1 Digital Ar control loop programmable driving current ipa n 7 Version 0 1 1 11 22 2005 Copyright 2005 MStar Semiconductor Inc All rights reserved MST720A MST720A A sta Small Size LCD TV Processor with Video Decoder Preliminary Data Sheet Version 0 1 semiconductor iim eee BLOCK DI AGRAM CVBS Switch 2 Channel Video Decoder YC Separation Chroma S Video SC AFE Timing Generator 2D Comb Filter Demodulator Display Device DPWM Output Flash Memory or External MCU Feedback Voltage EEPROM 07 In AM ROM 7 25 18 Deinterlacer RGB Amplifer Version 0 1 E Copyright 2005 MStar Semiconductor Inc All rights reserved 11 22 2005 MST720A MST720A A sta r Small Size LCD TV Processor with Video Decoder Preliminary Data Sheet Version 0 1 semiconductor mwa GENERAL DESCRI PTI ON 5 720 is a high quality ASIC for N

KT0801

Contents

Download Pdf Manuals

Related Search

Related Contents