32" Chassis
Contents
1. muww I z 5 ma mmy CERTE PO a s r mouw ee o afr r mane jon Z S EN p Um mr TT Dar zs pe fr S pays roma rafal ss J J o S I ajaj rss ETSURTSKCOTSCIKST se ie E po A ES sja e esa 1 A A A reped E E a es a a ajaj ez o ajaj sese ME o MIR A e S sjaj CE P E O MAD ajaj pss oo y mea 4 42 Psa fp _ aspas pests jJ 5 5 WRHBRE jaj peso po WRMWR PEA IG A A A A e p OT uu jaj fra J J fs m a a m a a Pin Mo Control Pin Port Interrupt Pin Timer Pin UART Pin Analog Pin Bus Control Pin HEELS REM _ _ o a ESSE Tn poa ee S T E efs 37 it ee aj PS AMES 762 60 vocz He on ea RO O isis io STE Ce e Y o Fe e eae E AN CI re e es Y fos rese ja pp es parans ser jas 222 fo ojej a e o 519 pei ST pp 2 wn o e NI KN KI A LI NN A jj a RR M uM tmd o mnm mam EAN A E 00 A MO EN NE gt ICAA JE O 5 A A aa ENE AO ES A A nn E JUN TA a a EE po po JAM po oo DB 5 mje mr E 1 ANT y ale roe be als2. Watchdog timer 15 bits i Converter r Three phase motor X 2 channels T7 ewvOCT ports gt iaj NOTES 1 ROM size depends on microcomputer type RAM size depends on microcomputer type Ports P11 to P14 exist only in 128 pin version Use M16C 62PT on VCC1i VCCZ Be Li KJ Figure 1 M16C Block Diagram system clock generation circuit XIM XOLT XCIN XCOLIT PLL frequency synthesizer On chip oscillator Clack synchronous serial I 8 bits x 2 channels Memory ROM t RAM 6 YCC1 ports gt 3 FIESTO 1374 gt Pin Configuration a fn jin sin o fn fm ABOB BABA TOQQQQQOS 86868666 oe 2222222 ZiZIZ 99799 9 ager nore ez 222222 OBOODODOTTTILIATT GANABAN pa bel Sit Pda os ft x a tes dy Bd o kav ib ddd AAAA apar pede PO 7 ANO 7 D7 a 51 PO B ANO 6 D6 a w 82 PO 5 ANO 5 D5 aa 2 PO A ANO 4 D4 a gt 64 PO 3 ANO 3 D3 a gt 85 PO 2 ANO 2 D2 ro 56 PO 1 ANO 1 D lt PO O ANO O DO lt 68 P10_7 AN7 Ki3 e 80 P10 6 ANG KI2 a 20 P10 5 ANSIKTI m 01 P10 4 ANA KIO am 22 P10 3 AN3 aa c P10 2 AN2 ae su P10 1 AN1 e ss AVSS 96 P10 O ANO c 97 VREF AVCC v PO TI DTRG SINA 0 NOTES Figure 2 M16C Pin Configuration 4 vss lt VCC2 gt 2 lt VCC1 gt
3. Front Key gt Osd Menu gt Determines the visibility of menus to the user according to the selection Enable Disable Install Menu Disable All Menus Autosave gt Update Last Data Not Stored
4. 127 Default is 34 e SCART PRESCALE AVL OFF gt If AVL OFF set value in this item is used as prescale value for scart outputs 0 127 Default is 15 e SCART VOLUME AVL OFF gt If AVL OFF set value in this item is used as volume value for scart and scart2 0 127 Default is 122 e 125 prescale gt set value in this item is used as prescale value for HDMI outputs 0 255 Default is 5 12 4 Options e Burn In Mode gt If ON When TV is powered ON Green Blue Red is displayed in sequence until Menu button is pressed Default is OFF e FIRST APS gt If ON First APS menu is displayed when the TV is switched on with the factory default settings Default is OFF e APS Volume gt After First APS function finishes the volume of the TV is that value Default is 15 AGC dB gt Tuner AGC value Default is 8 Power Up Mode gt Mode defines the TV set power on state Default is standby Stand by When TV is ON set is in stand by mode Normal When TV is ON set is in normal mode Last State When TV is ON set is in Last State mode Factory Reset gt OK to activate When OK is pressed on this item factory defaults loaded Enter Flash Mode gt Reset Eeprom gt Initialize default settings e Remote select gt O RC1546 1 RC1549 1602 1082 1055 2 RC1062 3 RC1072 4 RC1558 5 RC1061 6 RC1071 7 RC1110 8 RK18 Default is 2 TV Norm BG gt If ON this standart is supported else not supp
5. 2 P8 4 NT2 ZP SEHE TEHTA ga 2 doc e a T o e E O S obrunivehso d SXXXXXXX4Xx4 Sa UMS os eso 1 pV fl d gt da oacnaddida sal obrede M16C 62P Group M16C 62P M16C 62PT e P8 1 TAAIN U psi Tum P8 2 INTO PS ZANTI a P7 6 TASOUT c gt P8 O TA4OUT U P7 7 TA3IN 50 gt P4 4 CS0 40 A P4 5ICS1 4 o P4 6 CS2 47 no P4 _TICS3 20 P5_7 RDY CLKOUT 38 t P6 O CTSO RTSO 37 se P6 1 CLKO 38 t P6 2 RXDO SCLO 35 P6 YTXDO SDAO 34 gt p6 A CTST RTST CTSO CLKS1 32 HE p6 5 CLK1 32 gt P6 6 RXD1 SCL1 31 gt Ph 7 TXD1 SDA1 Package 100P6S A Pin Ho ar pati ae Araog Pin pus Contro da Papas ee 2 roof ws Jfexs wo pata Jos mw jp pap pas mem mw s s e2 em sours ZEN TA MG CO IE CI mn ss r s Po pm o oBGS Ea e a A A NJI KN e rkews 1 ape ken mr 11 s our rs 12 10 freser y at frou op vws pp op o o o ajap dp O L L pDe wuwct arpas pres fem A A e ZORNIK ZRNI EET U A mmm mmm CI O O a el SNI ol AAA O EE aja CTO mom I SSCS a ayer mau asa rs Jamar AI S 25 23 Jezs tan U a len asja Jera
6. SIF input for single reference Quasi Split Sound QSS mode PLL controlled SIF AGC for gain controlled SIF amplifier single reference QSS mixer able to operate in high performance single reference QSS mode and in intercarrier mode switchable via I2C bus AM demodulator without extra reference circuit Alignment free selective FM PLL demodulator with high linearity and low noise Four selectable I2C bus addresses I2C bus control for all functions I2C bus transceiver with pin programmable Module Address MAD Pin Configuration Symbol Pin Descripion nc metcmmeded AD 6 AFdecouping input for capacitor A 8 audio pat tuner AGC TakeOver Point TOP for resistor adjustment I2C bus data input and output select with resistor ne mtcmweded ne motcomeded HEF VAGC Input VPLL VIF PLL for loop filter SIF differential input 1 and MAD select with resistor SIF differential input 2 and MAD select with resistor DEEM AFD TDAS885T Le PLL AUD SIOMAD 12 MIC T08 Figure 9 TDA9886T Pin Configurations 3 4 SAW Surface Acoustic Wave Filter Epcos X6966M X6966M is a bandpass IF filter at f 36 125 MHz with tinned CuFe alloy terminals Frequency response Figure 10 Frequency Response of X6966M 4 AUDIO PROCESSING 4 1 Sound Processor Micronas MSP 4411K Description MSP 4411K is a single chip TV sound demod
7. 220 TO 220FP TO 3 and D2PAK packages intended for use as positive adjustable voltage regulators They are designed to supply more than 1 5A of load current with an output voltage adjustable over a 1 2 to 37V range The nominal output voltage 1s selected by means of only a resistive divider making the device exceptionally easy to use and eliminating the stocking of many fixed regulators Features Output voltage range 1 2 to 37V Output current in excess of 1 5A 0 1 line and load regulation Floating operation fro high voltages Complete series of protections Current limiting thermal shutdown and SOA control Pin Configuration INPUTS OUTPUT ADJ P11980 D4PAK Figure 27 LM317 Pin Configuration Figure 28 LM317 Application Circuit 6 5 LM1117 800mA Low Dropout Linear Regulator Description The LM1117 is a series of low dropout voltage regulators with a dropout of 1 2V at 800mA of load current It has the same pin out as National Semiconductor s industry standard LM317 The LM1117 is available in an adjustable version which can set the output voltage from 1 25V to 13 8V with only two external resistors In addition it 1s also available in five fixed voltages 1 8V 2 5V 2 85V 3 3V and 5V The LM1117 offers current limiting and thermal shutdown Its circuit includes a zener trimmed bandgap reference to assure output voltage accuracy to within 1 The LM1117 series is available in SOT 223 TO 220 and TO 252 D PAK packa
8. 40 C to 85 C Automotive E 40 C to 125 C Block Diagram Figure 24 24LC02 Block Diagram Pin Configuration Figure 25 24LC02 Pin Configuration 6 3 EEPROM FOR PC DDC ST24LC21 Description The ST24LC21 is a 1K bit electrically erasable programmable memory EEPROM organized by 8 Bits This device can operate in two modes Transmit Only mode and l2C bidirectional mode When powered the device is in Transmit Only mode with EEPROM data clocked out from the rising edge of the signal applied on VCLK The device will switch to the l2C bidirectional mode upon the falling edge of the signal applied on SCL pin The ST24LC21 cannot switch from the l2C bidirectional mode to the Transmit Only mode except when the power supply is removed The device operates with a power supply value as low as 2 5V Both Plastic Dual in Line and Plastic Small Outline packages are available Features 1 Million Erase Write Cycles 40 Years Data Retention 2 5v To 5 5v Single Supply Voltage 400k Hz Compatibility Over The Full Range Of Supply Voltage Two Wire Serial Interface l2c Bus Compatible Page Write Up To 8 Bytes Byte Random And Sequential Read Modes Self Timed Programming Cycle Automatic Address Incrementing Enhanced Esd Latch Up Performances Pin Configuration ST24LC21 Figure 26 24LC21 pin configuration 7 REGULATOR ICS 6 4 LM317 Description The LM117 LM217 LM317 are monolithic integrated circuit in TO
9. 7 PISV330 Pin Descriptions Block Diagram M Da SLA D u d AJ osi M O O m m LJ LJ o II a d ful h LJ LI DO LJ DECODER DRIVERS EN IN Figure 21 PI5V330 Block Diagram 6 HDMI BLOCK 6 1 HDMI Switch AD8190 Description The AD8190 is an HDMI DVI switch featuring equalized TMDS inputs and pre emphasized TMDS outputs ideal for systems with long cable runs Outputs can be set to a high impedance state to reduce the power dissipation and or allow the construction of larger arrays using the wire OR technique The AD8190 is provided in a space saving 56 lead LFCSP surface mount Pb free plastic package and is specified to operate over the 40 C to 85 C temperature range Features e Two inputs one output HDMI DVI links e Enables HDMI 1 2a compliant receiver e Four TMDS channels per link Supports 250 Mbps to 1 65 Gbps data rates Supports 25 MHz to 165 MHz pixel clocks Equalized inputs for operation with long HDMI cables 20 meters at 1080p Fully buffered unidirectional inputs outputs Globally switchable 50 2 on chip terminations Pre emphasized outputs Low added jitter Single supply operation 3 3 V Four auxiliary channels per link Bidirectional unbuffered inputs outputs Flexible supply operation 3 3 V to 5 V HDCP standard compatible Allows switching of DDC bus and two additional signals Output disable feature Reduced power dissipation Output termination removal Two AD81
10. LS VO S VO LS O Power LS O LS O LS VO LS O Positive Analog Supply 3 3 V nominal High Speed Input Complement High Speed Input Negative Analog Supply OV nominal High Speed Input Complement High Speed Input Input Termination Supply Nominally connected to AVEC High Speed Input Complement High Speed Input High Speed Input Complement High Speed Input PC Address LSB Positive Digital Power Supply 3 3 V nominal High Speed Output Complernent High Speed Output Output Termination Supply Nominally connected to AVEC High Speed Output Complernent High Speed Output High Speed Output Complement High Speed Output High Speed Output Complement High Speed Output Configuration Registers Reset This pin is normally pulled up to DVCC BE Clock BE Data High Speed Input Complement High Speed Input High Speed Input Complement High Speed Input High Speed Input Complement High Speed Input High Speed Input Complement High Speed Input Low Speed Input Output Low Speed Input Output Low Speed Input Output Low Speed Input Output Positive Auxiliary Switch Supply 5 V typical Low Speed Common Input Output Low Speed Common Input Output Low Speed Common Input Output Low Speed Common Input Output Negative Digital and Auxiliary Switch Power Supply 0 V nominal Low Speed Input Output Low Speed Input Output Low Speed Input Output Low Speed Input Output 6 2 EEPROM
11. for HDMI DDC 24LC02 Description The Microchip Technology Inc 24AA02 24LC02B 24XX02 is a 2 Kbit Electrically Erasable PROM The device is organized as one block of 256 x 8 bit memory with a 2 wire serial interface Low voltage design permits operation down to 1 8V with standby and active currents of only 1 A and 1 mA respectively The 24X X02 also has a page write capability for up to 8 bytes of data The 24X X02 is available in the standard 8 pin PDIP surface mount OIC TSSOP and MSOP packages and is also available in the 5 lead SOT 23 package Features e Single supply with operation down to 1 8V Low power CMOS technology mA active current typical IuA standby current typical I temp Organized as 1 block of 256 bytes 1 x 256 x 8 e 2 wire serial interface bus I2C compatible Schmitt Trigger inputs for noise suppression Output slope control to eliminate ground bounce e 100 kHz 24AA02 and 400 kHz 24LC02B compatibility e Self timed write cycle including auto erase Page write buffer for up to 8 bytes e 2 ms typical write cycle time for page write Hardware write protect for entire memory Can be operated as a serial ROM e Factory programming QTP available e ESD protection gt 4 000V 1 000 000 erase write cycles Data retention gt 200 years e 8 lead PDIP SOIC TSSOP and MSOP packages e 5 lead SOT 23 package Pb free finish available Available for extended temperature ranges Industrial 1
12. guaranteed endurance of 10 000 cycles Data retention is rated at greater than 100 years The SST39V F088 device is suited for applications that require convenient and economical updating of program configuration or data memory For all system applications they significantly improve performance and reliability while lowering power consumption They inherently use less energy during Erase and Program than alternative flash technologies The total energy consumed is a function of the applied voltage current and time of application Since for any given voltage range the SuperFlash technology uses less current to program and has a shorter erase time the total energy consumed during any Erase or Program operation is less than alternative flash technologies They also improve flexibility while lowering the cost for program data and configuration storage applications The SuperFlash technology provides fixed Erase and Program times independent of the number of Erase Program cycles that have occurred Therefore the system software or hardware does not have to be modified or de rated as 1s necessary with alternative flash technologies whose Erase and Program times increase with accumulated Erase Program cycles To meet high density surface mount requirements the SST39VFOSS is offered in 48 lead TSOP packaging See below figure for pin assignments General Features Organized as 1M x8 e Single Voltage Read and Write Operations 2 7 3 6V e S
13. mai ano 5 Jos rar 7 L es p STE 83 Sd Fes m2 aoz jo Z soje mi TT AO Fe s o 1 Janes jp 8 87 Pio7 K3 Cis O soj se pros H2 e E AAA ZN ZN o A oz sja Pes E EE Fw s Pp82 1 a slej Por I ha ess er Pp Swee O NENNEN NNNM A MEUM 100 38 PS 7 zIH ADTRG roje 2 Table 2 M16C Pin Descriptions 2 2 Flash IC SST39V F088 General Description The SST39VF088 device is a IM x8 CMOS Multi Purpose Flash MPF manufactured with SST s proprietary high performance CMOS SuperFlash technology The split gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches The SST39VF088 writes Program or Erase with a 2 7 3 6V power supply It conforms to JEDEC standard pinouts for x8 memories Featuring high performance Byte Program the SST39VF088 device provides a typical Byte Program time of 14 usec The devices use Toggle Bit or Data Polling to indicate the completion of Program operation To protect against inadvertent write they have on chip hardware and Software Data Protection schemes Designed manufactured and tested for a wide spectrum of applications these devices are offered with a
14. sound menu else invisible Default is ON Menu Virtual Dolby gt If ON visible in sound menu else invisible Default is ON e Carrier Mute gt If ON in the absence of an FM carrier the output is muted else not Default is ON e Virtual Dolby Text gt Active if VIRTUAL DOLBY is ON According to the selection seen in sound menu as SD PANORAMA or VIRTUAL DOLBY Default is 3DS SOUND 2 e AVL gt AVL is controlled from this menu by service user ON OFF Default is ON e Menu AVL gt If ON AVL item is visible in sound menu and AVL can be controlled from sound menu by normal user else AVL is invisible to normal user Default is ON e FM PHESCALE AVL ON gt If AVL ON set value in this item is used as prescale value for the related standard 0 127 Default is 15 NICAM PRESCALE AVL ON gt If AVL ON set value in this item is used as prescale value for the related standard 0 127 Default is 34 e SCART PRESCALE AVL ON gt If AVL ON set value in this item is used as prescale value for scart outputs 0 127 Default is 15 e SCART VOLUME AVL ON gt If AVL ON set value in this item is used as volume value for scart1 and scart2 0 127 Default is 122 e FM PRESCALE AVL OFF gt If AVL OFF set value in this item is used as prescale value for the related standard 0 127 Default is 15 NICAM PRESCALE AVL OFF gt If AVL OFF set value in this item is used as prescale value for the related standard 0
15. triple Features Member of UV1300 MK4 family of small sized UHF VHF tuners e Systems CCIR B G H L L I and l OIRT D K Digitally controlled PLL tuning via I2C bus Fast 400kHz I2C bus protocol compatible with 3 3V and 5V micro controllers Off air S cable and hyperband channels from 48 25 MHz to 863 25MHz inclusive World standardized mechanical dimensions and pinning Horizontal mounting is optionally available Various connector types available e EURO content available Pin Configuration Pin Symbol 1 JAGC Automatic Gain Control Voltage z T Tuning Voltage Monitor Output RC Bus Address Select 4 si I2C Bus Serial Clock 5 Spa DC BusSerial Data 6 NC Not Commected 0 a eee Voltage 5V s me ADG ADCIput 9 Fixed Tuning Supply Voltage 32V 4 out 2 Symmetrical I F output 2 Do not connect d n c for asymmetrical 11 LF out 1 Asymmetrical I F Output Symmetrical I F output 1 M1 M2 M3 M4 Mounting Tags Ground Table 4 UV1316 MK4 Pin Descriptions Block Diagram zi NAS NAE att Figure 6 UV1316 MK4 Block Diagram 3 2 IF Demodulator Micronas DRX3961A DRX 3961A is used to extract CVBS and audio information from the IF output of the tuner Features Multistandard QSS IF processing with a single SAW filter Programmable IF frequency between 30 and 60 MHz DSP based IF processing for the following standards B G D K I L L and M N Standard specific digital sign
16. 2 Audio L R signals are switched via audio switch TEA6420 The outputs of the switch are two L R audio signals MSP4411K is used for audio processing and it covers the sound processing of all analog TV standards worldwide as well as the NICAM digital sound standard Audio outputs are connected to SC1 2 3 connector audio line out headphone Speaker subwoofer and S PDIE connectors The inputs to the MSP441K are two audio signals from audio switch FAV Audio L R SC Audio L R OSS signals from main and pip tuners Tuner2 mono signal and HDMI I2S signal The AD8190 is a DVI HDMI switch featuring egualized TMDS inputs and pre emphasized TMDS outputs ideal for systems with long cable runs between sources and sinks of video data A disable feature sets the outputs to a high impedance state reducing the power dissipation The primary function of the AD8190 is to switch one of two HDMI single link sources to one output Each HDMI source consists of four differential high speed channels and four general purpose control lines The switched HDMI signal is sent to the video processor IC 2 CONTROLLER 2 1 Microcontroller Renesas M16C M30620SPGP General Description The M16C 62P Group M16C 62P M16C 62PT of single chip microcomputers are built using the high performance silicon gate CMOS process using a M16C 60 Series CPU core and are packaged in a 80 pin 100 pin and 128 pin plastic molded QFP These single chip microcomputers operate using so
17. 20 for faster processing The main controller IC is M16C M30620SPGP The I O assignments are as follows NAME TYPE _ DESCRIPTION Port Pin HDMI RELATED 1 HDMI HPLG OUT HotPlug output for HDMI 1 source P1 4 76 device device P8 7 AA cnm na service POWER PANEL RELATED 8 PROTECT IN Indicatesthe power supply status P1 7 9 STBY CPU GO OUT Controls the power supply on or off P13 77 PDP GO 13 PANEL VCC OUT Controls the power supply of the panel P1 0 80 SERIAL DATA COMMUNICATION 272 16 E2 SDA IN OUT I2C serial data line for E2PROM P10 7 89 17 E2 SCL OUT I2Celock line for E2PROM P10 6 90 I8 E2 WP OUT Controls the write protection of the P10 5 91 E2PROM EXTENTI ON MODULES RELATED TVLINK IN TVLank interrupt input data output OUT DMP CTRL Controls DMP module P60 38 L0 MIDORELATED OOO VI DEO RELATED APPLICATION APPLI CATI ON 29 LED 1 OUT j LEDcotol P90 7 30 LED2 OUT LEDcontol2 P91 6 Scart 2 pin8 input measurement SC3 PIN8 ADC IN Scart 3 pin8 input measurement P10 3 KEYB ADC IN Keyboard input P10 0 SWU RX UART receive for software upgrade UART transmit for software upgrade OUT RY BY Ready Busy indication from external P5 flash PC VGA standby detection 512 o Table 1 Microcontroller I O Assignments The PC Audio L R DMP Audio L R IDTV SC3 Audio L R YPbPr Audio L R Scart
18. 90s support HDMI DVI dual link Standards compliant HDMI receiver HDCP DVI Serial I2C slave control interface 36 lead 8 mm x 8 mm LFCSP Pb free package Block Diagram SERJA ERFACE T PAVEC A di CONFIG CONTROL il T EE CECL L INTERFACE LOGIC LP aMUxvcC I2 ADDR AVEE peeeeeememq questo J l LOW SPEED UHEUFFERED BIDIRECTHO RAL Figure 22 AD8190 Block Diagram Pin Configuration CH xv i zu XM ka Xm OH XM C SLE TIM a EMOS XITV EMO In MOD XImg i OWOJ XI TOP VIEW Mot to Scale INDICATOR AD6190 Figure 23 AD8190 Pin Configurations Pin No 1 10 33 42 2 3 4 13 30 39 ePAD 15 21 16 17 18 24 19 20 22 23 25 26 27 28 29 31 32 34 35 37 38 40 41 43 45 46 47 48 49 50 5 52 53 34 55 56 Table 8 AD8190 Pin Descriptions Description AVCC IM Ao IP Ad AVEE IN A1 IP A1 VTTI IN A2 IP A2 IN A3 IP A3 I2C ADDR DW C ONO OP VTTO ONI OPI ON2 OP2 ON3 OP3 zi SCL I2C SDA IM B IP BO IM B1 IP B1 IM B2 IP B2 IM B3 IP B3 AUX B3 AUX B2 AUX B1 AUX Bo AMUXVCC AUX COMS AUX COM2 AUX COMI AUX COMO DVEE AUX A3 AUX A2 AUX AI AUX AQ Power H H Power H5 H5 Power H5 H H5 H5 Control Power HS O H O Power H O H O H O H O H O H O Control Control Control H H H5 H H5 H5 H H L5 VO LS VO L5 VO L5 VO Power L VO
19. Service Manual 32 Chassis 17MB26 1 INTRODUCTION Analog front end consist of a main tuner a pip tuner and IF decoders The PLL tuners supply the IF signals and SAW filters are used for filtering and impedance matching between demodulator ICs and tuners The main IF signal is demodulated by demodulator DRX3961A and the pip IF signal is demodulated by TDA9885T At the outputs of the demodulators CVBS and QSS signals are obtained The main tuner CVBS pip tuner CVBS FAV CVBS Scart CVBS SVHS Y Scart2 CVBS Y DMP CVBS IDTV Scart3 CVBS Y signals are applied to the video matrix switch TEA6415 The outputs of the switch are main CVBS to video processor pip CVBS to video decoder scart out CVBS to scartl scart2_ out CVBS to scart2 scart3 out CVBS to scart3 The video decoder IC VPC3230 decodes to CVBS signal for the pip picture The source for the pip picture can be CVBS from the video matrix switch SVHS Scartl Scart2 Scart3 and DMP The output of the decoder is 8 bits ITU601 PIP signal connected to video processor IC SVP LX66 SVP LX66 can support up to 1920x1080p panel It consists of OSD teletext scaler deinterlacer 8 10 bit dual LVDS transmitter and HDMI blocks The inputs to SVP LX66 are Scart2 RGB DMP RGB SC2 SC3 Chroma SVHS Chroma Scart RGB main CVBS from video matrix switch YPbPr ITU601 PIP HDMI ITU601 IDTV PC RGB The output is the Sbits LVDS signal to the panel The SVP LX66 uses a DDR RAM EM6A93
20. UTS ONBROBMA os ADDR GN LEFT OUTPUTS GAIN Q 2 A 6dB LEFT INPUTS Figure 12 TEA6420 Block Diagram Pin Connections GND CAPACITANCE V L1 L2 L3 NC NC L4 L5 LOUT 1 ROUTI LOUT2 ROUT2 SDA SCL ADDR Ri R2 R3 NC NC 2 3 4 5 6 lj B8 9 R4 R5 ROUTA LOUT4 ROUT3 LOUT3 Figure 13 TEA 6420 Pin Configuration 4 3 Headphone Amplifier Philips TDA1308 Description The TDA1308 is an integrated class AB stereo headphone driver contained in an SO8 or a DIP8 plastic package The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital audio applications Features Operating temperature range 40 to 85 C No switch ON OFF clicks Short circuit resistant signal to noise ratio 110 dB total harmonic distortion 0 001 Block Diagram T1DA1308 OUTA DD INA neg INB neg se INB pos Figure 14 TDA1308 Block Diagram Pin Configuration OUTA DD INA neg OUTB INA pos INB neg INA pos 3 INB pos 7 Voo positive supply Table 6 TDA1308 Pin Descriptions 5 VIDEO PROCESSING 5 1 Video Processor TRIDENT SVP LX66 Description The SVPTMLX66 video processor 1s a highly integrated system on a chip device targeting the converging HDTV ready and PC ready LCD TV PDP TV and DLP TV applications where high precision processing of video and data are the re
21. al processing for channel filtering audio video splitting group delay equalization programmable video AGC and delayed tuner AGC Digital picture carrier recovery e Automatically frequency adjusted Nyquist slope over complete lock in frequency range which eliminates the need of fine tuning e Fast AGC algorithms for tuner video and SIF outputs Programmable tuner take over point TOP No sound traps required for video output FM radio capability without external components and with standard TV tuner I2C bus interface Pin Configuration DYDD Des DVDD CAP DW ES CAP IAC SCL PORTO le SDA PORT RESETS TLHER AGC 7 TEST EM 33 221 3 20 24 27 26 25 24 23 PORTE 34 2 AvsSS DAC PORTA 35 J amp vDD DAC PORTA 36 20 U SIF ADR SEL 37 19 U REF SW PORTS 3 amp 18 CVES Dvpp Apc 39 DRX 396xA 17 TEST2 DESADOS UY 40 16 U TESTI XTAL_IN LJ di 15 Y TESTO XTAL OLIT Y 42 i4 U SHIELD VREF U 42 3l AVSS SYM esM D 44 C 12 U amp VDD S YN 1 Z 3 4 5 6 7 8A 8 10 1i AVISADO L AVES FEdO ANMDD AD ANATSTX AVDD FE4dO IF ANATSTY IFINX AVDD FES AV55 FEdO AVSS FEB Figure 7 DRX 3961A Pin Configurations Block Diagram irai Glock laenernalian IC Figure 8 DRX 3961A Block Diagram 3 3 IF Demodulator TDA9886T Description The TDA9886T is an alignment free multistandard PAL and NTSC vision and sound IF signal PLL demodulator for negative modulation only and FM proc
22. ast Blank FB input integrated A D converters and associated clamp and AGC circuits multi standard sync processing linear horizontal scaling 0 25 4 as well as non linear horizontal scaling Panoramavision PAL preprocessing line locked clock data and sync or 656 output interface peaking contrast brightness color saturation and tint for RGB YCrCb and CVBS S VHS high quality soft mixer controlled by Fast Blank I2C bus interface Block Diagram INU Adaptive Color Y Mixer Y 2D Scaler Output VIN1 Comb Decoder PIP Formatter Filt VIN2O im NTSC cr Cr Panorama ITU R 656 ME PAL 7 Mode ITU R 601 SECAM VINA Cb Cb Contrast Memory Brightness COMI Peaking Saturation VOUTO RGB Sync YCrCb Matrix E FRO Contrast Clock Saturation Generation RGB o Brightness YCrCb Tint 2025 MHz IC Bus Figure 19 VPC3230D Block Diagram 5 4 Video RGB Switch Pericom PI5V330 Description The PI5V330A is a true bidirectional Quad 2 channel multiplexer demultiplexer that is recommended for both RGB and composite video switching applications Features Wide bandwidth 400 MHz typical Low On Resistance 5Q typical Low crosstalk at 10 MHz 56dB Ultra low quiescent power 0 1 WA typical Pin Configurations IN Vec 51A EN SA 310 Da 32D 51g Do 32Bp Sic Dp 320 GND De Figure 20 PI5V330 Pin Configurations sla slp slc SID SZA S2B S2C 32D Analog Video VO Table
23. e e 100 kHz lt 2 5V and 400 kHz 2 5V compatibility e Self timed write cycle including auto erase Page write buffer for up to 32 bytes 2 ms typical write cycle time for page write Hardware write protect for entire memory Can be operated as a serial ROM e Factory programming QTP available ESD protection gt 4 000V 1 000 000 erase write cycles Data retention gt 200 years e 8 lead PDIP SOIC TSSOP and MSOP packages e Standard and Pb free finishes available Available temperature ranges Industrial D 40 C to 85 C Automotive E 40 C to 125 C Block Diagram AD Aj Ao We PP LILI E Page Latches Vioc vss gt Sense Amp RW Control Figure 4 Serial EEPROM Block Diagram Pin Configuration cl XXFC Figure 5 Serial EEPROM Pin Configuration 3 TUNING AND IF DECODING 3 1 Tuner The tuners used in the design are combined VHF UHF tuners suitable for CCIR systems B G H L L IP and D K The tuning is available through the digitally controlled I2C bus PLL Below you will find info on one of the tuners in use Description The UV1316MK4 tuner belongs to the UV1300 family of third generation WSP tuners which are designed to meet a wide range of TV applications It is a full band tuner suitable for CCIR systems B G H L L I and I The low IF output impedance is designed for direct drive of a wide variety of SAW filters with sufficient suppression of
24. essing The TDA9886 is an alignment free multistandard PAL SECAM and NTSC vision and sound IF signal PLL demodulator for positive and negative modulation including sound AM and FM processing Features 5 V supply voltage Gain controlled wide band Vision Intermediate Frequency VIF amplifier AC coupled Multistandard true synchronous demodulation with active carrier regeneration very linear demodulation good intermodulation figures reduced harmonics and excellent pulse response Gated phase detector for L and L accent standard Fully integrated VIF Voltage Controlled Oscillator VCO alignment free frequencies switchable for all negative and positive modulated standards via I2C bus Digital acquisition help VIF frequencies of 33 4 33 9 38 0 38 9 45 75 and 58 75 MHz 4 MHz reference frequency input signal from Phase Locked Loop PLL tuning system or operating as crystal oscillator VIF Automatic Gain Control AGC detector for gain control operating as peak sync detector for negative modulated signals and as a peak white detector for positive modulated signals External AGC setting via pin OPI Precise fully digital Automatic Frequency Control AFC detector with 4 bit digital to analog converter AFC bits readable via I2C bus TakeOver Point TOP adjustable via I2C bus or alternatively with potentiometer Fully integrated sound carrier trap for 4 5 5 5 6 0 and 6 5 MHz controlled by FM PLL oscillator Sound IF
25. etween 0 to 63 Default is 32 e Sharpness gt Slider Bar Changing value between 0 to 31 Default is 22 Colour gt Slider Bar Changing value between 0 to 99 Default is 70 e R gt Slider Bar Changing value between 0 to 31 Default is 31 e G gt Slider Bar Changing value between 0 to 31 Default is 31 e B gt Slider Bar Changing value between 0 to 31 Default is 31 e Backlight gt Slider Bar Changing value between 0 to 255 Default is 30 In this menu preset values for each Mode Contrast Brightness Sharpness Colour values for each Mode NATURAL DYNAMIC CINEMA and for each Colour Temp R G B values for each Colour Temp COOL NORMAL WARM are determined for each source SOUND1 e Menu Subwoofer gt If ON Subwoofer option is available in TV set and the item is visible in sound menu else Subwoofer is not available Default is ON e Subwoofer Level dB gt This value is gain value of Subwoofer output in dB 30 12 Default is 0 e Subwoofer Corner Freq x10Hz gt Last low frequency value that is amplified 5 40 Default is 22 Menu Equalizer gt If ON visible in sound menu else invisible Default is ON e Menu Headphone gt If ON visible in sound menu else invisible Default is ON Menu Effect gt If ON visible in sound menu else invisible Default is ON e Menu Wide Sound gt If ON visible in sound menu else invisible Default is ON e Menu Dynamic Bass gt If ON visible in
26. ge of 40 C to 85 C VCC 3 3V 0 3V Normal Range VCC 2 3V to 3 6V Extended Range CMOS power levels 0 4uW typ static Rail to Rail output swing for increased noise margin All inputs outputs and I O are 5 Volt tolerant Supports hot insertion Pin Configuration ato A na juve Pinnames Desertion 5014 1 zi s012 sA cg aa AS sY di O JB B ZA GND 7 g O 4 1 H HIGH Voltage Level Sorc SSOP TSSOP L LOW Voltage Level RENSE Table 9 IDT74LVC14A Pin Description Figure 31 IDT74LVC14A Pin Configuration APPENDIX A SOFTWARE UPDATE PROCEDURE 1 Open the program ISPWriter3 on your PC 2 SPWriter Fle commPort Propertes Programmer Hehoot Enter SP Clear Remoter View Helg p g AAA g OFEN C EME ELI BIN a Gre REKO comme Gate CLEAR fee a Configure the port from the menu CommPortSetting and adjust the settings as follows You should select Com Port which you want to use MM Communication Settings Baud Rate C 4800 C Scot C 19200 C 38400 C 57600 115200 Cancel m Panty LE Flow Control f None Orr None C Odd C Xon Xolf C Even C RTS C Son ATS CPU M16082 SPANSION S23ALOD8D T DrvFile ISP4M16C62 BIN Diner 3 03 D ateT ime Jun 23 2006 15 49 16 c Click OPEN icon on the toolbar 2 Press the MENU key on the local keyboard of the TV while 1t 1s closed and open
27. ges A minimum of 10uF tantalum capacitor is required at the output to improve the transient response and stability Features Available in 1 8V 2 5V 2 85V 3 3V 5V and Adjustable Versions Space Saving SOT 223 Package Current Limiting and Thermal Protection Output Current 800mA Temperature Range 0 C to 125 C Line Regulation 0 2 Max Load Regulation 0 4 Max Pin Configuration Fixed Output Regulator SOT 223 LM1117 XX Y IN Y NPUT OUT GND Tab is NER OUTPL OUT 10 uF ADJ GHD Tantalum 10 uF Tantalum DS 1009154 Top View Figure 29 LM1117 Pin Configuration Figure 30 LM1117 Application Circuit 6 5 IDT74LVC14A HEX Schmittrigger Inverter Description This IC is used to detect the PC standby The LVC14A Hex Schmitt trigger inverter is built using advanced dual metal CMOS technology This device contains six independent inverters and performs the Boolean function Y A Inputs can be driven from either 3 3V or 5V devices This feature allows the use of this device as a translator in a mixed 3 3V 5V supply system The LVCI4A has been designed with a 24mA output driver This driver is capable of driving a moderate to heavy load while maintaining speed performance Features 0 5 MICRON CMOS Technology ESD gt 2000V per MIL STD 883 Method 3015 200V using machine model C 200pF R 0 1 27mm pitch SOIC 0 65mm pitch SSOP and 0 65mm pitch TSSOP packages Extended commercial ran
28. he main function of the TEA6415C is to switch 8 video input sources on the 6 outputs Each output can be switched to only one of the inputs whereas any single input may be connected to several outputs All switching possibilities are controlled through the Features 20 MHz bandwidth 6 outputs Bus controlled 8 inputs CVBS RGB Chroma Any single input may be connected to several outputs e 6 5 dB gain between any input and output e 55 dB crosstalk at 5 MHz e Full ESD protection Pin Configuration Input Input Data T Ground Input Output E Clock A Output Input 6 Output Input 4 Output 1 Prog 5 Output Input C Output VCC Ground Input Input Figure 17 TEA 6415C Pin Configurations Block Diagram Output Output Output Output Output Output Ground cu E an di si em B Lj ce ude era cli A K KR MR oljne EUN VE TE a MENTA T O Tr AAA Bus Decoder k 3 ex Data Prog Clock WoC Ground Figure 18 TEA 6415C Block Diagram 5 3 Video Decoder Micronas VPC3230D Description The VPC 323xD is a high quality single chip video front end which is targeted for 4 3 and 16 9 50 60 Hz and 100 120 Hz TV sets VPC3230D is used for PIP applications Features adaptive 4H comb filter Y C separator with adjustable vertical peaking multi standard color decoder PAL NTSC SECAM including all substandards four CVBS one S VHS input one CVBS output two RGB YCrCb component inputs one F
29. is low Output Enable Ta gate the data output buffers Write Enable Ta contral the Write operations Power Supply To provide power supply voltage 2 7 3 8V for 3ST39WFDSS Ground No Connection Unconnected pine 1 Aye Most sgnificami address Pags Aig for SSTJOVFOBE Table 3 Flash IC Pin Descriptions 2 5 32K I2C Serial EEPROM 24LC32A General Description The Microchip Technology Inc 24AA32A 24LC32A 24XX32A is a 32 Kbit Electrically Erasable PROM The device is organized as four blocks of 8K x 8 bit memory with a 2 wire serial interface Low voltage design permits operation down to 1 8V with standby and active currents of only 1 A and 1 mA respectively It has been developed for advanced lowpower applications such as personal communications or data acquisition The 24XX32A also has a page write capability for up to 32 bytes of data Functional address lines allow up to eight devices on the same bus for up to 256 Kbits address space The 24XX32A is available in the standard 8 pin PDIP surface mount SOIC TSSOP and MSOP packages General Features e Single supply with operation down to 1 8V Low power CMOS technology mA active current typical 1 A standby current max I temp Organized as 4 blocks of 8K bits 32K bit e 2 wire serial interface bus I2C compatible Cascadable for up to eight devices e Schmitt Trigger inputs for noise suppression Output slope control to eliminate ground bounc
30. orted Default is ON e DK gt If ON this standart is supported else not supported Default is ON e gt If ON this standart is supported else not supported Default is ON e L gt If ON this standart is supported else not supported Default is ON LP gt If ON this standart is supported else not supported Default is ON e M gt If ON this standart is supported else not supported Default is ON 12 6 Features PIP PAP gt If ON enables the PIP PAP Default is ON Blue Background gt If ON Blue Background is visible in Feature Menu else not Default is ON e Menu Transparency gt If ON Menu Transparency is visible in Feature Menu else not Default is ON e Menu Timeout gt If ON Menu Timeout is visible in Feature Menu else not Default is OFF e Backlight gt If ON Backlight is visible in Feature Menu else not Default is OFF e Dynamic WB gt Dynamic White Balance Default is ON e Zoom Mode Blank gt If ON displays blank while changing the zoom mode else not Default is OFF e Dynamic Menu gt lf ON the features covered by some patents will be used else not 12 7 Teletext TOP TXT gt If ON Top Text feature is available else not Default is ON Fast TXT gt If ON Fast Text feature is available else not Default is ON Teletext Language Teletext Language may be controlled from this menu by service user e Menu Teletext Language gt If ON Teletext Language item is visible in Fea
31. phisticated instructions featuring a high level of instruction efficiency With 1M bytes of address space they are capable of executing instructions at high speed In addition this microcomputer contains a multiplier and DMAC which combined with fast instruction processing capability makes it suitable for control of various OA communication and industrial equipment which requires highspeed arithmetic logic operations General Features Main features of M16C are 16 bit Multifunction Timer Timer A and B 11 channels UART Clock Synchronous Serial Interface 3 channels Clock Synchronous Serial Interface 2 channels 10 bit A D Converter 26 channels 8 b1t D A Converter 2 channels DMAC 2 channels CRC Calculation Circuit Watchdog Timer Clock Generation Circuits Main Clock Generation Circuit Sub Clock Generation Circuit On chip Oscillator PLL Synthesizer Oscillation Stop Detection Function Voltage Detection Circuit Option Except for T Version and V Version Interrupts 29 internal factors 8 external factors 4 software factors Data Flash 4KB Flash Memory Version only Block Diagram YOC ports 1414 Internal peripheral functions zu A D converter 10 bits x 8 channels Timer 16 bit Expandable up to 26 channels Output timer Aj 5 UART or nput timer BJ 8 clock synchronous serial HO B bits x 2 channels CRC anthmetc cecum CCITT j Polynemial 1x4 x5 1 conira circuit Mi6C 60 series 16 bit CPU core
32. quirements SVP LX66 has a total of four video input ports one analog port one HDMI port and two digital ports PortA and PortB LVDS output is either dual or single pixel mode Features Integrated HDMi Receiver with HDCP up to 135 MHz Integrated 6th Generation Motion and Edge Adaptive De interlacing Integrated ADC PC Auto Tune Built in dual 8 10 bit LVDS Transmitter Vertical Keystone for Projector Advanced 6th generation cubic 4 image scaling engine Horizontal and vertical mirror image inversion DNR Digital Temporal and Spatial Noise Reduction Filter Advanced Chroma Processing Dynamic Contrast Function Green Color Stretch blue color stretch skin color enhancement Integrated 6th Generation Motion Adaptive 3D Digital Comb Video Decoder with Programmable Filter Inverse Color Space Conversion Trident Proprietary LCD BRITETM Technology for LCD Overdrive Interlaced and Progressive Scan Refresh Block diagram 3CWBS gt A 2 Chroma PC RGB x 1 up to SAGA 60Hz Ypbpr x 2 D1 D2 D3 D4 2FB amp 2 FS SCART 24 8 bit in Din port amp 32 bit Input 8 bit In wc HOMVDYI Signals In a HDMUHDS Flash ROM Figure 16 SVP LX66 Block Diagram DDR SDR 32 bit COR PCLKIHIV Dual dbit 10bit LWDS Channel 1920x108DP Output 23 amp SPDIF CVS Out x 2 Svldeo cut EME be GPIO ac 2x PWM 5 2 Video Matrix Switch ST TEA6415 Description T
33. the TV set from main power switch without releasing the MENU key Keep pressed the MENU key for 3 seconds until following messages are displayed 7 ISPWriter3 Eis ComrPort Properties Erogrammer Reboot EmeriSP Clear Remoter Wew Help Gr i A m M nm BM Up dz z 1 n LoS 155 FH LOBE LPR U ili BiM PROS WERE BEAD commie ati gt I5PHead Aug 21 2006 15 42 45 gt Waiting OR gt Entering ISP mode TSPWriters3 DART 115200 n 4 1 Version 3 03 EHuildTime Jun 26 2006 15 25 02 3 Press the BIN icon to open the binary file to be downloaded Look in E M16C62 HaTi HP Y174826 81N Files of type bin Files bin Cancel J p 4 After selecting file press the PROG button on the toolbar The progress dialog will be displayed as follows Wait until 1t reaches to 100 MATEO 5 After download has completed just close the TV and open again APPENDIX B 12 SERVICE MENU SETTINGS To enter the service menu first enter the MENU by pressing MENU button and then press the digits 1 4 6 and 1 respectively 12 1 Picture Adjust e Source gt All possible sources given with the chasis as a list e Mode gt Three items as a list NATURAL DYNAMIC CINEMA e Colour Temp gt Three items as a list COOL NORMAL WARM Contrast gt Slider Bar Changing value between 0 to 63 Default is 63 e Brightness gt Slider Bar Changing value b
34. ture Menu and Teletext Language can be controlled from Feature Menu by normal user else Teletext Language is invisible to normal user Default is ON e Check Data gt Used to check the teletext data No service usage 12 8 Source e TV SC1 SC2 SC2 SVHS SC3 SC3 SVHS YPBPR FAV SVHS HDMI HDMI2 PC This menu is related with the options of the chassis These items may be ON or OFF If ON the source is available in TV set and the item is visible in source menu else the source may be available but invisible to user Menu Languages 1 4 2 The language options for the Language item in Feature menu can be set ON or OFF from this menu English German French Turkish Spanish Danish Swedish Dutch Italian Greek Portuguese Norwegian Finnish Polish Czech Hungarian Russian Slovak Slovenian Rumanian Bulgarian Croatian Serbian Hebrew 12 9 Tuner options Main tuner gt The main tuner used in the TV is selected PIP tuner gt The pip tuner used in the TV is selected HOTEL MENU SETTINGS To enter the hotel menu first enter the MENU by pressing MENU button and then press the digits 7 9 3 and 5 respectively Hotel mode gt If ON hotel menu settings will be valid else not e Startup position gt The selected source will be active when the TV is on e Volume Level gt The set value will be the volume level when the TV is on and cannot be changed from the menu by the user
35. ulator decoder and baseband audio processor Features Alignment free decoding of all TV audio standards US BTSC audio with DBX noise reduction and SAP decoding Japanese EIA J stereo Digital NICAM stereo All 2 carrier TV Audio standards Very High deviation modes HDEV2 3 Automatic Standard Detection ASD Automatic Sound Select ASS switches mono stereo bilingual without controller interaction Delay line for Lip Sync SRS TruSurround XT optional BBE High Definition Sound optional Virtual Dolby Surround Equalizer Tone control Subwoofer filter Micronas BASS Micronas VOICE Two SIF inputs to the Demodulator 8 channel I S inputs with sampling rate converter Analog stereo line inputs to A D or switched to line outputs Loudspeaker D A for L R Sub channels with analog volume Headphone D A with analog volume rS outputs S PDIF output Block Diagram Sound IFA Sound IF2 intemal axtemal Audio Delay Source Select SCART m ha SOAHTe E SCARTS Figure 11 MSP44xyK MSP46xyK 4 2 Audio Switch ST TEA6420 Description The TEA6420 switches 5 stereo audio inputs on 4stereo outputs All the switching possibilities are changed through the I2C bus Features 5 stereo inputs 4 stereo ouputs Gain Control 0 2 4 6dB Mute for each output Serial Bus Controlled Very low Noise Very low Distortion Block Diagram RIGHT INPUTS GAIN Q 2 4 6dB RIGHT OUTP
36. uperior Reliability Endurance 100 000 Cycles typical Greater than 100 years Data Retention Low Power Consumption typical values at 5 MHz Active Current 12 mA typical Standby Current 4 uA typical e Sector Erase Capability Uniform 4 KByte sectors Block Erase Capability Uniform 64 KByte blocks Fast Read Access Time 70 and 90 ns e Latched Address and Data e Fast Erase and Byte Program Sector Erase Time 18 ms typical Block Erase Time 18 ms typical Chip Erase Time 70 ms typical Byte Program Time 14 us typical Chip Rewrite Time 15 seconds typical e Automatic Write Timing Internal VPP Generation End of Write Detection Toggle Bit Data Polling e CMOS I O Compatibility e JEDEC Standard Flash EEPROM Pinouts and command sets Packages Available 48 lead TSOP 12mm x 20mm Pin Configuration Standard Finout Top View Die Up 1237 484 05 RAMA Figure 3 Flash IC Pin Configuration Mud mem Nm JI Address Inputs Ta provide memory addresses During Sector Erase 4us 412 address lines will select the sector During Slock Erase Auz A c address lines will select the block Data input autput To output data during Read cycles and receive input data during Write cycles Data is internally latched during a Write cycle The outputs are in tri state when OFF or CES is high Chip Enable To activate the device when CES
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