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RM 380Z Service Manual

1. E Mi C O Sv r gt MEL IMI KE o I no ski I S SEL va 15 eal I IT a gt Gei sra DSL A Ver io Ra ps3 JUKA ue mr Ch 12 A A 1000p SERIAL INTERFACE em psi BEN Pp eS psi W Pa Y e CAR E Py RER dn Pa Sint 33 30 ex n 1 1 CR 4 IRES SET Tac 8 157 H I gt tos 4 45393 103 A KISI BU 4 er E 102 ER N 4 a 101 a via I u d poe l 1 7 Gu t7 m log H Jag 12 c c DSR 2807 FLOPPY K2SIEN CS 1 DISC CONTROLLER Joro a Rb RIS mto S101A furos IRESET 44 re Zt Teen CTs d CP ve AU KANING NO Fpc1 onran panwma ato en RE SEARCH MACHINES LTD E vu a 24 is TI ns ipi nn sro ta een vata CLOCK Et ATTORE Su 5v te Lory OLE IS KFACE uc Al dada ba fo V A de dp Tee PS e ar 107 E LER Drs T 106 2 a sn HET d ftp LATA Ga 30 IDS wr se Zi 1502 Ng ES T3 Joy ads cbe AI om AA YAA TRACK ZERO NG gt 103 i m K5 ail oe 122 wf 31 wa F Pored 1D1 lt en es O SECTOR 15 iP 31 v sock NOR vun LE v TS CS 21 x 7 e JAG READY Let lt READY m r ITI EN gt s ud NES Hz O Li o 32 1 Soch LOA D rn 10e D Hep wor vsep moet Ci o 32 22 ond eed wo alan gt Dec WRITE DATA IRtSET a 74 b EDS T i pata karo a ul wA AA XA AA ape 2 24 WRITE GATE MH H 121 rp F Vu ja DISC DRIVE
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3. Data is applied through EV 74LS245 the address is more tricky The high eight bits must be latched in DW 7415273 via DV 74LS245 by writing to a port at FBFE with bit 3 CGSEL of the control port at FBFC set The remaining four bits are written to the latch DU 7415173 which is also mappe at FBFE but which is only available when the screen is closed Note The outputs of this latch are connected to the same lines as the outputs of the multiplexer CT 7415257 This is because the same latch DU is used to supply some of the address bits to the character store when accessing the screen in 80 character mode The multiplexer ET 74LS399 which includes a latch selects either the row counters normal display or DU writing to character generator or during a smooth scroll as the source of the four low character generator address lines Control Control signals from the CPU are buffered by AP 7415244 Whenever possible signals are taken from the bus connector rather than from the 34 way connector The bus buffer direction is controlled by logic contained in CQ 74LS27 DR 74LS02 and FP 74LS266 BS 74LS155 is a decoder for the ports at FBFC to FBFF The signals PORT3 WR and PORT3 RD are sent back to the CPU to enable the user I O port The latches ER 74LS273 and CR 74LS377 supply miscellaneous control bits as shown on the diagrams Half of AP 74LS244 is used to monitor KBDSTB VBLANK and HCPUEN Keyboard C
4. 6 8 10 4 5 7 4 5 6 7 6 8 9 8 10 this is the default option U J N UI J W The internal workspace and sector buffer RAM can be either a 2K by 8 or 8K by 8 RAM The links required for these are as follows 2K by 8 1 2 8K by 8 2 3 Internal Decoding Circuit DC 3 4 The decoding for all the chips accessible by the internal Z80A IC 46 circuit DC 2 4 is done in a 10 input 8 output PAL IC 46 PAL 10L8 using address lines 2 3 7 13 14 and 15 together with control lines RD WR MREQ and IORQ The PAL decodes I O mapped port signals FDCEN DSTRD DRD DWR and CTLWR as well as memory mapped signals ROMEN and RAMEN There are two internal control ports which are enabled by address lines AO TATA LAAT ia ALA PAANAN 3802 IDC Board and Al The decoding is incomplete and therefore many different codes can access the same hardware The nominal memory and port addresses are as follows FDC Chip 00H to 03H 00 Status Register read only 00 Command Register write only 01 Track Register read write 02 Sector Register read write 03 Data read write I F Status 04H to 07H 04 Interface Status read only 05 Interface Status read only 06 Interface Status read only 07 Interface Status read only I F Data 08H to OBH 08 Interface Data Commands read write 09 Interface Data Commands read write OA Interface Data Commands read write 0B Interface Data Com
5. Check change IDCINT PAL IC42 esp RAMEN Check change RAM IC 43 Run ADDFLASH see p 14 em SUNS OS ca AE IDC Diagnostics IDC DIAGNOSTICS Symptom 3 1 LED flashing indicating FAULT 3 ROM fault Tests Check change ROM IC 47 Check change IDCINT esp ROMEN signal IC 42 Run ADDFLASH see p 14 IDC Diagnostics IDC DIAGNOSTICS Symptom 3 2 LED flashing indicating FAULT 4 FDC fault Tests Check change IDCINT esp FDCEN signal IC 42 Check change FDC IC 41 Check change IC 31 LS157 Check FCLK IC 41 24 IC 31 7 2MHz 8 selected 1MHz 5 selected AA a a IDC Diagnostics IDC DIAGNOSTICS Symptom 3 3 LED flashing indicating FAULT 5 CTC fault Tests Check change IDCEXT esp CTCEN signal IC 19 Check change CTC IC 44 Check CLOCK CCTRY IC 45 LS 04 IC 28 LS 393 IC 29 LS 11 IDC Diagnostics IDC DIAGNOSTICS Symptom 3 4 LED flashing indicating FAULT 6 SIO fault Tests Check change IDCEXT esp SIOEN signal IC 19 Check change SIO IC 40 Check CLOCK CCTRY IC 45 LS 04 IC 28 LS 393 IC 29 LS 11 tem ee Pantone a DN N IDC Diagnostics IDC DIAGNOSTICS Symptom 4 LED on but system will not boot Tests Press RESET Press B Is Y C
6. m iis _ AS K S 3 5 O DATA O EDO 34 Lal B A A 3 s s SON m Ja d ID 10 15 HAY MALE 5 TE 44 CANNON D TYPE SO EHAB 290 w aovA 4 Sy SIo i D WRA S1P4 2 Jh en BP J A SES thy wed Orn nm Le aani pe imm mmm mme mm mm e D mmm me ee w DMA OPT104 OEVILES Tr 8 2 C1 RH 2 22 Aile e NATIVE OPTION T e a 4 PPP C LOCK C E anne E i NorT FIT TED HESLLF C USER 1 0 CARLE I str e HEADER D npe l2 1 bag BA N t Me gt De A O wee wi Dr Gis NI d ie er uu 86 Pu 2 12 Papa 0317 5 4 3 p CSA BS Pete O pig 09208 5 maa h1 4 5 3 ta CA i 3 4 RTS 6 DJ d E o Dt ad D e A O 4 PTA A AS BT e O JD aa L D Ju E VOLT ey AME m pa LAT AL p i m ess FT RS KENE e Net tr tt F C were 1 l Ch lt cu n ue amp 1 47 XL b t 74 N CTS e Gui y 4 _ C i a do e esos si EM ja 4 x d Sou P a O D Os KAYA i gt 2 a nn ON UE Sbk OF Tag 1045 ch J d 10 cc i Ct ur 5 t Rb _ 5 Wo A 123 Cr 31 T4 Oa b ste i jt re 517M j Wi d ca ya Bio E ja v SIPS A vy 504 2 denge d al ynt OTMK Takte 07 nato a 11 4 10 Sg e co 6 4 RM giwed Eo 9 8 po 80 E ose p s oO bwa ALT 2 0 In Ee Lives iub BE qvi ad e KY t T e 7 I 7 xi EE ET A x ELFORE 10
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8. F300 Z 1 5Kd Video RAM FB304 Control W F200 2 FB20 Reserved O F 100 7 FB10 HRG ports 7 E E F000 Z FB00 FBOO Port 0 R W Figure 1 3 Page 1 Use of Memory Above F000 1 8 3802 CPU Board FDS MDS FDC board ports Reserved EF r CF OC 8251 masika 8 8 Port 0 E4 F C4 FD1771 EO I O PORTS IN THIS AREA MUST BE FULLY DECODED To allow for future use of greater than 256 ports N B Existing boards are not fully decoded and will appear at every 256 port locations Advised 48 49 duplicated _SIO 6 Loo N B PIO boards occupy 16 consecutive I O ports PIO IEEE board occupies 32 consecutive I O ports Users are advised to fill I O ports from the bottom avoiding 40 to 5F if possible Figure 1 4 Standard 3802 I O Map N L jl D 380Z VDU 40 Board SECTION 2 VDU 40 BOARD INTRODUCTION This section details the circuitry of the VDU board supporting CPU boards with COS versions 3 0 and 3 4 Early versions of the VDU board may have hardware modifications to the latest circuit specification No attempt is mos to document anything other than the current 40 character VDU board CIRCUIT DESCRIPTION Circuit Diagrams 380Z VDU 1 Keyboard and Cassette Interfaces Ports and Video Memory 3802 VDU 2 Video Generation The VDU board comprises Screen generation hardware 1K of static screen memory Cassette handling
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11. 380Z SERVICE MANUAL October 1984 UNSEREN EEE 380Z AND 480Z SYSTEMS SERVICE MANUAL PN 13821 Copyright 6 1984 by Research Machines Limited All rights reserved Copies of this publication may be made by customers exclusively for their own use but otherwise no part of it may be reproduced transmitted transcribed stored in a retrieval system or translated into any language or computer language without the prior written permission of Research Machines Limited Mill St Oxford England OX2 OBW Tel Oxford 0865 249866 Research Machines has a policy of continuous development and improvement of its products and services and the right is reserved to revise this manual or to make changes in the computer software it describes without notice Research Machines endeavour to ensure the accuracy of this manual and that the products described perform correctly according to their descriptions However Research Machines Limited do not accept liability for the consequences of any error or omission Additional copies of this publication may be ordered from Research Machines Limited at the address above Please ask for the title as given above 380Z Service Manual CONTENTS Page SECTION 1 CPU BOARD Introduction Circuit Description Processor and processor support Bus control and buffering EPROM and EPROM support Dynamic RAM and support System
12. C A or IN C A instruction Video output The output stage has to deal with twice the bandwidth as compared to the 40 character VDU board It must provide outputs for wire frame monitor and combine the output from the HRG board with that from the VDU Further it has to process the information contained in the attribute memory Inverse video is achieved using the XNOR gate FP 7418266 This is an open collector gate and the blanking signal is introduced at this point Dim video works as on the 40 character board Two currents are added in the output stage in a crude D to A converter Underlining is performed by modifying an address line to the character generator with gates from GQ 74LS09 and GS 74LS32 so as to display a portion not normally visible which contains the underline In the output stage itself T1 is a common base stage to amplify the HRG signal with T2 after it as an emitter follower The open collector driver BV 7407 buffers the video signals which are added in the resistor network R18 R19 R20 and R23 along with diodes D3 D4 and D5 Diodes D2 and D6 introduce the sync signal D7 is a level shifter to ensure that sync goes down to zero T3 is a final emitter follower stage T4 is used to disable the video signal from and to the HRG board Smooth Scroll This uses hardware which has already been described During normal display the multiplexer ET 74LS399 takes the dot row number from th
13. L a IN 4 1 2 v7 evo P eg Th o LEE Ladan DCA 10 Pe 12 E poi kas SEAN ip sisi Terre I a E VACA uC l x 3 Vos vp V TERM E TRE re 32 3 0 Y 02 TTL l CA c1 ns 37 716 SES Y o Yo 32 22 SACK 32 21 peo pd o R EVL 32 14 SAST 32 MENS 32 24 MCC 42 25 ju BUS Re T T 32 28 SSEL 32 27 RI Up 31 39 Sc D 32 29 j SE SANGA Bos 432 32 SREG 31 239 5 32 32 SI O 32 33 S SIGND DRAWING NO PIO as SASI Tc r cc Hi B 155 2 mie 3 4 JA tag tu 9 42 w P 1001 MII ER had Ye un De ji Dp js du ees HEN bn li 33 7 prp p Les un A PI A Loy ii ds VE Se v4 tos Gi x p ps TS 1 M 1 smn Dk q t i ES p7 PENA p7 M Z6 0oA sas Gm sl 8 SS DMA KAY gro a na m bit m4 1410 ee aan Aro FL LoL K A gan gt Ja An ce Kr 16 pcc wAlt HAS Ca O98 D 2 A 20 au oy pis T SS ES AI GN lan La TOR Te 26 137 iq I Kick wre EAS 31 26 jc 132 EO DMAACT co ge vento BoA CALI fuk 31 24 amp gnrca sita emi no Btuseq 31 27 z Gar poaea0 MACH wii DRAWN BY CHECKED BY Research Machines Tur TITLE DRAWING NO HIG 4 4 VIR DMA CHP Aub SUPPORT 061 974 HiB 15372 w P 100 MODIFICATION BAP KAIT Data Ka CAI BALI Raio LA WW I 2 LET cs Kenly
14. Timing Interrupts Mapping DMA controller Programming the control port Programming the SIO and DMA Programming the CTC baud rate Connectors 4802 Hardware Mapping Transceiver connection Transceiver NIB cable HOST INTERFACE BOARD Introduction Design Objectives The Hardware Modules Bus buffering Bus decoding Memory Interface to SASI ii e n OI Qn n OI OI n OI n UI n VI 8 0 YON NAN UB GA NN a ma O Oh Oh On ON MN sech J OY OI e 8 2 8 gt s zl zl o zl zl zl zl zl o zl zl SJ SJ SJ zl e OOO w A OA Un nun BB r WWNN a 380Z Service Manual FIGURES 1 2 1 3 1 4 RAM Timing Standard 3802 Use of Memory Use of Memory above F000 Standard 3802 I O Map 3802 CPU Board SECTION 1 CPU BOARD INTRODUCTION This section describes the circuitry of the CPU board supporting COS versions 3 0 3 4 and 4 0 There is no hardware alteration between the three COS version CPU boards although differences do exist on boards supporting COS 2 3 or earlier No attempt is made to document these early boards as so few are now in use CIRCUIT DESCRIPTION Circuit 380Z CPU RAM 3802 CPU 2 The CPU board incorporates a Z80 A processor processor support bus control buffering two fully supported 16K banks of dynamic RAM space for three 2716 2708 monitor EPROMS fully supported system clock an 8 bi
15. an IC46 8 03 103 4 Z80ACTC u 103 IC40 lt RXDA Hz mo ZB0ACPU 2 pp 102 102 Z80ASIO 1 rypA AO e 5 p 101 101 313 IRXCA AB Pe pe IDO 106 1 JTXCA RISA A6 52 m LAT IA 8 CTSA BDINT AS 33 24 WAIT TAG IA 16 DTRA N X pl pp 9 pepa 43 033 p22 yp CTCEN SIOEN A2 32 pH MREQ IM1 A IM1 28 RXDB 7 SIOE m I 520 jora TIORA HORA 26 TXDB 30 CTCEO I 27 AQ IRD IRD RXTXCB ve RESET meset P CTSB PHI INT DTRB i DCDB uina 3 KO O IRESET CTSB 12 RI TXCA 4 JRXCA 6 RXCA 6 UNLESS OTHERWISE STATED ASSUME ANGULAR TOLERANCE 1 2 WHOLE UNITS t 0 6mm 1 DECIMAL PLACE 1 0 1mm GEOMETRICAL TOLERANCES SEE BS 308 METRIC THIRD ANGLE PROJECTION 6 Cl RESEARCH MACHINES LTD Mili St Oxford OX2 OBW MATE 22 a d ae TITLE CIRCUIT DIAGRAM IDC 3802 CPU SERIAL INTERFACE 8 CLOCKS gt DEL DRG No 012559 Shi 2 of b TAWEN MT u PM rito pm RV AN aa ana ic OT er v een ner RENTEN MT RET ATR NH FTSE aeneum IC N DEVICE Vee A Al A6 A5 AL A3 A2 Al Ab D1 D2 D7 D6 D5 D3 02 D1 Do 2407 71415244 7416 ULSN LSO GE 74LS109 KW LINK PINS 182 FOR 2K PINS 283 FORBK A0 Vee Vec 2l wR ROMPLA E 26 DEBLOCKING RAM YE AE
16. not depend on CPU board signals being present e g M1 A 4 7 uF capacitor is charged to 45V via a 33kohm resistor Until the voltage upon the capacitor develops to a TTL logic 1 the SET and RESET inputs of the J K flip flop segments in IC 44 are held low and 2400Hz pulses are transferred unconditionally to output pins 15 Q active high and 14 Q active low These outputs are SYSTEM RESET transferred to CPU board and Q is used to reset system port 0 e Manual Reset Users can manually activate the system reset by means of the RESET button When the RESET button is pressed J K flip flop IC 44 12K input goes high With SET RESET J and K inputs high the outputs toggle with the 2400Hz clock input generated in the cassette handling hardware IC 9 11 The 2400Hz signal produced is clocked through the second segment of IC 44 on the falling edge of BM1 ensuring that reset pulses only reach the 280 during an op code fetch and that the contents of RAM are not corrupted There is sufficient time between reset pulses to maintain refresh to the dynamic RAM in the system System port 0 latch IC 1 is reset simultaneously with system reset System Ports Keyboard Port and User Port Decoding Circuit 380Z VDU 1 Coarse port decoding is carried out on the CPU board and the 4 ports are mapped to occupy the following positions within the memory map PORT 0 PORT 1 PORT 2 PORT 3 PAGE O0 1BFCH 1BFDH 1BFEH 1BFFH PAGE 1 FBFCH F
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18. Ae SET n ej s d TUE 105 JIoRQ ED 4 Icc FP e 8 q a uU 105 ed 4 Dt 2e ss pa 102 nou et ca LA Boi 101 Inte Vou Set 32 54 I hened Bus HOUI A Cpo TIAM I BEE uS e M yr 45140 1ost joe Itb 4 MODIFICATION ki sed Gic I8 Yr CI Ini VAZ i l T S 7 2 5 _ l Mgr ONG f 4 is EE 47 een al 02 88 Svsaese a S 45360 I nos l is 84 BF at IRESET 117 3 in ES 4148 R3 CH it Ca 334 jOv M CI6M CuM 48 Af f 7 can aka R ae Je lt 7 coll 29 nani TT al tw AAA ZE JAT ki aal EPX O NGP 45694 MOL as ani 1 502 NN c pf Jt CRAIE o A Aa as Kid 3 A I 15240 3 cen aa ny eta Le gt iS 4 Sol Ze PocnAk bol 9o cHAR OPEN T 12 VELA vu HELANK D ie E ipM A E Mor ani 4206 E 11 3 Bod an 3 E l Din 33 4 BD Disc gt 53 5 BDZ Cum BER ACK 33 6 bz Cin k GITD Boy JA Swap EDS TAC N EN rato ATE 73 59 Boc R 45240 We ATM 32 6 BD Lf yo folu DRAWN BY CHECKED BY 4 3 60 T8 RLA DRAWING NO DAGAT sk of q 60 40 vpu bus rent s hg atte ca wa ma een sooner anemone anne NR REEL rS A ee a s eum Ca 67 asv Ti a BCISuQC oo Dy bec VIDEO NORMAL GD lo R m R24 VID In g gt 14 0 CA TEI LONNELTION TO th wey De toc T AY
19. CONNECTOR d ST STEP SIGNAL 25 Kids 2 HEAD LOAD N SECTOR 21 DIR SIDE LS244 9 HIDEX Ka t0 DEIVE ULI 12 DRIVE Sei 2 DS ltp Deve SEL 3 IL DRIVE SEL 4 e tuto OM Pa Dief SIDE 20 STEP DYA DAVE SELECTA 22 WRITE DATA 24 WEITE GATE AAA D RS E 2 le WACK ZERO r ae gcc u maise SE 3801 2 42 14 FLOPPY Veg o WRITE PEOTECT 2e DISC CONTROLLER Pes lo Loy op Or lt om Tas 122 SEP LATA TO 146 AVUN PAR OWNS 1979 EAA No Poca 24 SEP Cock RESEARCH MACHINES LTD ma a MUD amp 4ouL VETFGOILAY 2 JOUL 40UL f OMIL id FAI idi 13 ls aad 1 vol n o 3 3 o dd T ov O buy pa i 2 2 BRESET 33 1 RESET un 801 33 4 ki P 101 4 01 380Z MOS MOS 2K MDS8K 4802 PHI VERON A uns 34 E 380Z FOS FDS 2K FOS 8K 8MHz Bad 3 11 4 SKS 802 33 5 2 102 102 issues BAR 33 03 TA12 6034 33 6 ICA gt 103 103 eg pas BA13 mE TAB 804 03 7 2 MLS245 104 104 4802 BRO 13 35 IRO BDS e DS d 105 Cy SE ECNHO FOR 9 9 FULL DETAILS OFI BMREA IMREQ LK13 BD6 3 9 106 D6 EARLY 8 LATER Do mr 8 uem BM1 33 38 4 ma 807 ID7 107 OY TT IWD 1wD BCLOCK 33 40 ICLOCK HORQ IWR IRD kh buf IORQ WR RD Wo owo 121 pa 120 i sayad LK13 42 de MOTOR 2 LATE IC12 DLAT
20. HLD delay etc Flip flop IC ES is used extensively to implement the timing of these signals The CTC is clocked from the System 4 MHz buffered clock ICLK2 8251 Usage SIO4 SIO6 Circuit FDC1 To implement a full V24 RS232 serial port a dedicated UART IC ER 8251 is used This makes for very simple operation Access to and from the UART by the CPU is through the block of ports occupied in I O space Input Output from the UART to the serial port is via RS232 level drivers receivers ICs AV and BV Control of data exchange in the port is under software control by the CPU and baud rate for transfer is controlled by the rate of the TXC and RXC clock inputs These are commonly derived from the CTC channel 2 after monostable IC DU produces active low clock pulses of duration 1 5 us approximately Connection to the external peripheral is via J1 2 Dedicated Disc Controller Circuitry Circuit FDC2 Disc I O is largely handled by a dedicated IC controller the FDD 1771 which occupies IC position CS Access to the controller is via the block of ports which it occupies in the I O map Disc control outputs are buffered by open collector driver ICs AS and AT Inputs are pulled up via 150 Ohm resistors to 5V then buffered by IC AU Links are clearly marked on the circuit diagram where hardware differences between full and mini disc systems exist 3802 FDC Board Apart from the FDD 1771 and support a DATA CLOCK separator c
21. J t 1 2 Ti BCiBtC Mn GA SOO Research Machines Ltd MODIFICATION mes m a A M se Ba FE Rind em o mm aae 1 0 NET LECOGLPIG AZ ORL 2 ds KAI OC E gap Qi AA 607 U Er Bob 33 3 805 1 4 BA SD Ss k BP3 G3 e NER A an 60 Gs 1 i GD Boy A BMI QG3 2 1M1 E L 52 uu ja PA BRD Ql cc IRD 4 45293 Bwe G So INR Blora 33 32 A JIORQ D la Icux 1 Barx G3 Lo m YA BRLSET a JRESET AR n jy IC 1cint EE Ic x 2 Is 41 03 4 ve Co uv 9 Ov YA amp rx ky de d UM A ai akma ct t REFUS PNEU binky At Sorn AS Tb kost L TEAS ease ARE nNUCALLY fot Tuo s MLC of trees onan b6 t so gt A Me ka aaa ti MOS KINKS vot WA En oio WO lt JOKE 2 S o PORTS co scr 107 Cal E L k D ke s Gt fps cul 2 A E E _ E wa Dd Nora we Eas AUIL 106 264 7 pido 4 DALE t p e LES Uu T Er LIK s Ho fort pos LF IDS SET bee an ame 1 I we i 3 RE E 2 QNUM IRIS ES Ip ima p Hd cal S 103 Z 80R C1C 8 a5 1D2 Ad T IT ED iin 191 N ZCT1 TA TE r x 1A1 CR 1 AP g3 8 lay 220447 A L Se ca jan ob c I u ud ta Wa gt CICEN Ama gt A IREsET 2012 E N P LM sae AR Sei E cor Es 45373 b4iv amp Eevee E mE t llo a LIL vees FE oo bias 15 a
22. Machines TITLE MCPRRY Any AO MCD ceXNT OL HE 1992 NOT FITTED vapaa Ti o Sim aa Si BWAIT Vee wR Vec AS wk Eann SELECT 2x 6116 Ka i n serra Bn ee tan RD Lk2 Bawn BANK L DUEN D7 DL p 24 p3 DRAWN BY CHECKED BY DRAWING NO HIG 2 Ju mm zm w s MS vam m ANSKOLCT tt CLOCK Vis E SDd FI WRACK ET ORG gt m 36 1 TIRA on 1 4 SDI 173 G bipacw Del RAPo et E o M q Re siss ls als kme ROS SS ib m SEE EEE 2 I _ ma l A B 1 93 2 7 61 42 We een CR F 22 8 vo 51 32 L NI ELOCK VEL x S E ER ts 1 Sps 32 Ww GELALK au eoni Brit 32 M 06 37 12 Gt Qs v FRONS OMA N ER on NE 32 36 SOT AR AS Sei DEL B E gt et SAS GN EM 0516 I PICO A en 22 10 Mt A ASE kai Sie pee stil INT _ BAT ngo Lt mcd VODA 0417 E Arco as ada 7 s ROY eee Ree ZgoA 10 ve A IEN SEE 3 loo Pi a 9 1 285 GOO EN Ir sn A KEN 17 m NA or BUT Kok Ja Ki p oz ue 89 10 pi Ol KOI gavy UI ge ic eve E gt gt a 12 N W 265 ul a TO RESCT mi ai VI Mes Dim ca po le Be E g PAR rei 7 nal ER Am ER EE VEN 667 Y ma po Bis Die RR 3 n 3 4 5 af o DACH De 3 W 2 Ki 6 RVACK BCL M Ice q
23. TAEL ING Rh Lis s T ad E 7 3 E CF s Dd 0 70 st N i DCO S Dun Ze O ET Gil O Kun lt x BS T MN O be E T JON SOCKET mb HEADER TM a E Ge N 9 na cs ta21 IRV L j 4KT A 5 m AG C3 N ZT Py QU Um aa O7 or tani e ED CND 6104 RL 25 waf LE mmm wies Dart i s m e 777 i J2 CHECKED BY MAA E rh Research Machines Ltd GA DRAWING NO NIE pw Z ZONMUNICATIONI WORPD ern MITERIACES 3804 NET 2 Im lt x 107 Ibs 163 192 1p1 IDA IA1 IAG CIC atas CTCL anag Jci 2 Ic x a lloeq 110 7 iMi ah E liitti ire lt T lro ICp CTC1E cTCz CILItO ctelkO HER DER A NTERRUPT P IOKITY ALLOCATios DRAGO C c3 ceuo diodo 37 Q en BIE I MODIFICATION w P 104 D sss Job am nd Ex 2 W 24 27 26 25 tb a 15 to E To 6 231 ep IED Sv 1080 DHA EO 5 croteo CiIcafto BIKI CTC CH ELS gat 45V DAVOD RATE GENETATORS 5 1 mavee P 2 16 ETC Lock a CTC CLOCK FS 8 ZgoA CTC ND CTC o lt CLOCK c g so ms Al O 4 12 Baud Clock JINT Lu E KI JR Dez N Rito c Bo Research Machines Ltd si a TIMING T p B jt e o T Pareki TV HEADER A m Ped Da LOCATION N 2 3 L 5 6 7 INTERRUPT ALTERED PREMIERE e HEADER 8 ThinG RovtinG NOT NORMAL Y INSTALLED BREAK
24. f KBD Brg s16 oo Hte p g forty Fr tun LE 5774 33 54 Mv C vipid 2 lb sao bs GEI Titia bG er To Rar m B 7 RECET 6 MELIA et Lt gt 5 E ET kos A eos 8S e N Ser Kbi ge Bor erg Gun idis KD 516 803 KD3 803 802 KD2 802 801 Kb1 BDI ces lex Bog 125 kz un Kbg 509 CASSETTE REENEN iN ola m KASSETTE 3 amp ni QU SYSTEM 8 ec CASSETTE RIL ik Rm nen C Ota gg 21 120k CASSETTE mem out 5 ces A a H we lt ban PI ees cc DI cc LI a LI Ras E ALL Rc ecs 8M BAS BAL BA Bag 8 BAIA 2b WAY TJepeicrt od to fu Mat p mK by nbi i MDS nd d Mu i L mbb 42 GRAPHICS DA MD1 5V e Rib Lag Stoa Ric 2 me 8 DPI m MD3 al pi sa f Ras gt av KT R35 180R aN MDS 6v te y 143704 R33 Video Il igor ar y R34 ATOR D rer ASTEC UHF MODULATOR N o OUTPUT UM 1111 36 DD RO baa R 3nHz K 15813 Row COUNTER m 3802 VDU 2 VIDEO GENERATION Di 2090 swt 2of 2 Om nn DRAWING 2 15240 Sl AP knIc abg WII W EE pL IY 22 Livi AST Za S EN a b 2 D F U Mea 1G d j N 7 E Ea e C 1 Ans 2 i f lt L 1215 A 2K2 2287 li n G Bp EE AE 5 Si 1
25. flashes A9 flashes A10 flashes I A11 flashes A12 NB if address line short circuits to 5 then next address up will be indicated as faulty so check both 3802 IDC Diagnostics IDC DIAGNOSTICS Further Helpful Hints PALS Interrupts Links Clock Errors Shorts PALS control the selection of the various interface chips so if a particular chip appears not to be working then the chip enable signal is a possible problem IDCEXT white purple orange CTCEN SIOEN HWR HRD BDIR IDCINT white purple yellow ROMEN RAMEN FDCENO DWR DRD CTLWR A few devices on the IDC board generate interrupts which could interfere with the operation of the system The SIO and the CTC put interrupts to the host so if they start continually interrupting the host gets tied up This signal is IINT and is found on IC 44 12 IC 40 5 and appears at J3 30 as BINT after going via IC 1 3 4 Links are worth checking as these could prevent the system working LES select 5 8 link nearest edge of PCB for 8 LK9 select ROM type now pre linked LK10 select RAM type link nearest RAM for 2k RAM It is worth checking that there is no LS where ALS should be An LS04 is used rather than SO4 Check also that 1K2 resistors are used for R28 29 Occasional errors in booting or read write could be due to R3 R5 being missing or having the wrong value They should be 47 Ohm The most common p
26. hardware CPU reset circuitry Keyboard port Three system ports User port control circuitry 0000000 Screen Generation Hardware Circuit 3802 VDU 2 Both IC 30 7415393 and IC 33 741573 comprise a 9 bit binary counter clocked at 8MHz from the CPU board The 9 bit outputs are column counts CCO to CC8 The column count is used to define a horizontal screen position CC4 CC8 are used to count character positions along a screen line row and are fed into the line waveform generating PROM IC 31 coloured green The line PROM produces signals LINE ACCESS LINE BLANKING LINE SYNC and a count output to clock the line counter The signals are then latched by IC 34 on the rising edge of CC3 The LINE COUNT output clocks a 9 bit binary row counter ICs 32 and 37 the outputs of which RCO RC8 define row positions within the screen RC1 to RC8 are used by the FRAME PROM coloured yellow to produce signals FRAME RESET FRAME BLANKING FRAME SWITCH and FRAME ACCESS The LINE and FRAME BLANKING signals are mixed m IC 25 1 2 to give a RR blanking aignal on IC 25 3 FRAME SWITCH is used by the line PROM to invert line sync pulses and double ARI OC RI Pe CD NAAA 380Z VDU 40 Board their frequency during FRAME SYNC to maintain convention with television video sync signals LINE and FRAME ACCESS are available as bits in read port 1 and can be tested to open the Video RAM during line frame blanking A 7 bit word read from t
27. is installed this link must be cut Mapping All ports are I O mapped and controlled by a PAL The CTCs 8 ports the SIO 4 the DMA 1 port switch register 1 and control port 1 are all mapped from DOH to DFH in between the two standard FDC blocks The PAL is designated a number PDn where n shows the mapping configuration The current correct version is PD7 revision C Red Violet Yellow DF Switch Register Read Only DE Control Port Write Only DD Switch Control R W DC DMA A DB SIO B Control DA SIO B Data D9 SIO A Control D8 SIO A Data D7 CTC2 Channel 3 D6 CTC2 Channel 2 SIO B baud rate D5 CTC2 Channel 1 D4 CTC2 Channel 0 D3 CTC1 Channel 3 D2 CTC1 Channel 2 D1 CTC1 Channel 1 DO CTC1 Channel 0 380Z Network Transceiver DMA Controller omitted on standard board Circuit NET 1 When the DMA controller is installed two preset links must be cut one in the interrupt daisy chain and the other in the bus acknowledge daisy chain A bus acknowledgement priority daisy chain has been introduced to enable multiple DMA controllers in one 3802 or server BBAI Yellow and BBAO Blue 2mm patch sockets are provided for cascading and are similar to the Red and Black ones already in use for interrupt priority patching A link is provided to connect BUSAK from the 250 bus to the top of the daisy chain and this must be connected on the first or only board in a DMA system Wait states are introduced
28. on pin 2 of IC 17 thus ensuring that corruption of data does not occur during refresh e PROM M IC 13 produces an output enabling RAS of both banks during the MRO signal active period see figure 1 1 System Clock Circuit 3802 CPU 2 IC 23 4069 is used in a crystal controlled 8MHz feedback oscillator which produces a near sinusoidal waveform on pin 10 Other segments of IC 23 are used to square the 8MHz clock this is then taken to the VDU board J2 9 and to IC 24 which is wired as a divide by two counter with output on pin 9 1 4 3802 CPU Board at 4MHz This output is buffered onto the 50 way bus J3 40 by IC 21 and also buffered by a different segment of IC 21 onto the processor BCLK is the 4MHz system clock and is in phase with the 4MHz clock to the processor Memory Mapped Port Decoding Circuit 3802 CPU RAM Coarse decoding circuitry is used to support memory mapped ports such as system port 0 The screen mapping is also coarsely decoded in this way Using the more significant address lines and one page bit PROMS 13 and 19 produce an output when the address bus contents correspond to either Screen address or memory mapped port addresses Finer decoding of port addresses is carried out by IC 7 which gives an output IOSEL when the address bus content is within the block of 4 port addresses Both VDU SEL and I O SEL are taken to the VDU board on the 37 way bus User Port Latches A buffer IC 3
29. port 0 Port O Circuit FDC1 Port 0 consists of an 8 bit latch IC BS into which the contents of the ID bus may be written It is a write only port and cannot be read back so a mask is held in memory of the contents All software access to the port must be via read modified write sequences Port 0 Bit Allocations Read Bit Write 7 DINT Force disc interrupt IM 6 SET DRIVE EN 5 MSEL Dir side select bit 4 SSEL Side select bit 3 DS4 Motor on 2 DS3 Drive select bit 2 1 DS2 Drive select bit 1 0 DS1 Drive select bit 0 CTC Usage Circuit FDC1 IC DO on the FDC board is a Z80A CTC It is fully supported and is used extensively for both disc control and SIO4 implementation It occupies a block of 4 channels each of which is uniquely decoded by IA0 and IA in 380Z FDC Board I O space For all normal applications used by the monitor interrupt requests are not generated although provision exists for future expansion Channel 1 Drive enable timer Used for drive oa timings Clock input 64ms with DRIVE ENABLE Channel 2 Head load timing register Used for drive software timings Clock input 2ms with HLT and HLD Channel 3 Clock generator for UART Baud rate SIO4 Clock input 2MHz Channel 4 Clock input 64ms For disc control applications the CTC is used under software control by disc I O routines in the monitor to generate disc primitive timings i e DRIVE ENABLE
30. the intelligent double density disc controller board IDC The overall design objectives are first examined followed by the general method by which each individual block or module is used Then the detailed working of each module is considered in some depth Finally the on board firmware together with the option ROM interface is covered with the same top down approach DESIGN OBJECTIVES The IDC board was conceived as an improvement over the present disc controller board FDC in terms of storage per disc speed and ease of use The storage capacity has been increased by using double density MFM recording and also by allowing for the use of 96 TPI mini drives Due to the use of MFM data recording the data is read from the rotating disc at twice the rate previously managed and also due to the use of on board data buffering the data throughput has been increased considerably in most uses As the board is intended to replace the present FDC a serial channel is included with the same connections to the outside world As a more modern serial chip has been used on the IDC than on the FDC there are in fact two independent serial channels Another objective is that the board should be capable of working with a LINK 4802 This has been made possible by allowing communication with the host processor 380Z or 4802 through either the parallel 250 bus or one of the serial channels As the board is required to work with frequent interrupts
31. 10 x q 7 E JA e 17 hp 1 3 gt pt e An AA 8 Ti 33 13 RAIL Eps 803 692 Bo BOP 80 656 805 GD 603 807 BPI NOS E cs 607 Bo BPS BO 803 le an gt 35 31 BAN USER 1 0 3 pg 1 dau Vee adv 7 reu Dy E gon 9k 2708 THSITIE wT _A aid tt We IL kat L SS i 15 01 cl PN be Z 80R CPU tC E d it Jua gt fon RFSH L n 1g 1 lu 2708 o 152716 Ir maan D o GEO tT d Baka WR 9 nm NAT ENAR LE ty Ka Roni 23 239098 gt TMS1T16 a EAM I 3 2 8eest1 RST 243704 CEK Vee op nn An mp Ge A en hs N a Is le D T 8 O TES Lk t Ye 00 i l n i UMS A GALO Baq Cas RAT BAL BAS GAL BA BAI BAI Ung Tr o Hi KID a GE BE al JA A mara GMK e ist 3802 CPU H x else 2 4 EZ2 dx CPU Rom USER fo Timing AND BUS BUFFERING kHz DCAwING 2 RESEARCH MACHINES LTD meg d ge oy momo m e edad Tex yc Fe AE x 7 Po e WI l do n N f N lt oma e tk DER b Ke t VIDEO MEMORY ki Porp vg 2 Ch Put AAL Lts VERS SE no E Bor 3 wm ko 2 aroa EE Wi CASAL COUNTER t rennt t 5 ah ep er Ac ets 1 er p di sii any Ata tie N Bus T 34 20 RT cos PDS M 0 15 46818 we _ T 1 SWITCH elo Co BDE 4 i D 06 IS pb SE S i Button to L vera KD BDS 1200 601 kompa DA foci Cp Hx I
32. 2K HN6116 15 OR 22 ag Ab HK4802 1 WR BK 185565 15 A9 DN AS HN6264P 15 23 Bank LKO 2 2k yy n Bk D RAMEN El d A3 2 No AN 020 RAMEN A 9 11 8 x T j U ps 01 13 D4 D2 1 D3 m IORQ ar MREQ WR 3 13 Ir I 745377 RR RD den RI AIS 6 vp Alh gt D I A13 2 pro A7 11 h A3 CTLWR A2 Ao eech 3 lo jo lu la Ju je ju Im MEC ROMPLB Vcc AB A9 ROMPLC ROMEN A10 ROMPLD D7 D6 D5 D4 D3 ENCOMP UNLESS OTHERWISE STATED ASSUME ANGULAR TOLERANCE 1 2 WHOLE UNITS 1 0 6mm 1 DECIMAL PLACE O timm GEOMETRICAL TOLERANCES SEE 8S308 METRIC THIRD ANGLE PROJECTION O A LK9 ROM SELECT LINKS LK9 2 PRE LINK FOR 2764 OR LINK FOR DEVICES AS SHOWN Vcc 3o ROMOLD IPinitoi Pini INUSE ENCOMP ENCOMP DDEN DDEN BINCH BINCH ENCOMP EARLY kal 1k2 418 gt O a wo 3 200 RESEARCH MACHINES HEREANEN MACHINES LTD Mill 81 Ontora OX2 08W TITLE CIRCUIT DIAGRAM IDC 3802 MEMORY WAIT STATE amp INTERNAL DECODE L EMA wis Asia sof dal 9 Lil u VCL Iwalt1 IS N gy E SE A DS BWAIT J3 28 EREADY 1 2 34 E READY1 ks REV3 XRDY T DR 3 NC S orn 0 TRKO CEED at 16 _ TRo REV 3 RDY Ct 451 415244 5 NETTE en HLO a 2 WRIPRT 72 28 441 24 WPRT V5 8MHz 9 8 Tie 14
33. 3 14 15 16 17 18 19 20 3M Header 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 3M Header 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CD OV OV OV OV CTS DCD Transceiver Present Chassis BPAGE BD1 BD3 BD5 BD7 BA1 BA3 BA5 BA7 BA9 BA11 BA 13 BA15 BWAIT BINT BHALT BWR BMREQ BM1 BCLK 4MHz 5V 12V 12V OV UN 380Z Network Transceiver J5 J6 J7 J8 BBAI 2mm Yellow omitted on standard board BBAO 2mm Blue omitted on standard board BIEI 2mm Red BIEO 2mm Black The standard configuration Network Interface Board is populated with the following ICs only AP AQ AR AS AT AU BP BQ BR BS BT BU BV CP CO CR cs DP DQ DR EP EQ FP FQ FR Odu GS GT GU GV GW GX 74LS244 omit 898 3 R330 74LS 244 omit omit 74LS244 omit 74LS245 omit omit 75188 75189 PAL14L4 DMALOGc Red Violet Green PAL10L8 PD7c Red Violet Yellow omit Z80A S10 0 74LS32 74504 74L5244 74LS74 74LS244 74LS123 74L07 Z80A CTC Z80A CTC omit DIL switch 74LS161 CD4040 74LS30 omit omit omit omit 741504 Power Supply Consumption typical 45V 12V 12V 500mA 10mA 15mA MAA AA aaa GRAIN 3802 Network Transceiver 480Z HARDWARE Mapping All ports are I O mapped and controlled by a PROM JS 18 Switch Register 24 SIO
34. 3 2 4 HBiANKD MAS 3 Of Dr lt t E 3 2 i ne j ec 1 qe e u Ee ed lz ahh 1367 5 j e Al A V V E gu mis Hervew hoz 2 c 6 saa emm KA aemm e MODIFICATION ae l p3p2 ck S Yuc Koti 2 4 e Ca meer M I LIH Di HPkive H AT3 Et QM sA DiM EL sb ab 4 VOU A y 114 Nh 2 DT 15 h MAG JA 3 LS QI vOu AIO TY EM 2 175 gt qui acte MAS VU ei TDi N 5 d M ATIK vou t 101 A ral 14 a 4532 S FRAHEKST 45 Para wR T dr OX Vlt VE Cbn Rotti CRATE Roc soo DA QUCHAR 4r ia s FS F e DAJ E e In A e mg po mi i qD nx Ca E Wes 30 T Gr PEE nva ATI 81 3 A 2 3 FQ Sec A 53 me i FPD ps hori L 2526 RESET AD A Pe ARDSTB CPUA e p RAD Ha lt Ray 1 1D4 ut GED 104 MA 3 MA i SWAD 18 AR Inip G230 Idi ID Roi ME TDI CAG 4a RAZ Jo JD Rore CHI ID 2 a ie SE S 142 MAL RU TAG Q3 30 1 157 TAS 2 33 Ipi 143 Roi Wit TD CAS A KAR j To Gmvy MRDSTE bg m korey GEOD FpU TNR JA M S EM JAS 2 2 16 TAS 37 33 tus Bo CHAR pi tos TRANS Ce res CAy Ha RAT rpt VELAN K mr Di Geet DD rp Re IO MAD l MAY PAGE SFL ig ia TAG 14 GLa SE fen 101 1 7 VD indi CU Ip 15 Je xt v Te 2 RD Gen Pokr J to CPU BO Pont ut ge To T Ut N omtot STATUS Cont KoL Panig DORT P0012 eal 10 08
35. 6 649 GIZLI 36 u i 64 GILD 649 Gi 19 GAL 31 pig toRp vi 31 4 497 Bico Bucser EZ m35 BIEL gt vec amp e cc 31 2 3 Wista CITED i Ti SE PioiEO Sur pik pmaico Grngta Si 36 bmi 104p E Mis o AD io AH Y ccoc lt 1 m ky EMAD cH m I ee RFSH i i N JC REMOVED ete DMA OPTION INSTALLED kes D pnCm 8p 8IEI 5 menody SA ee mae Pec ove IEO ws 1048 PAL a KANZEN M DBMEMEN mi nlb POJA IT mt MAD DMAAT p lomo E 40 8840 3 e INSTALLCD ONLY sina PMA corro WITALLED BBAJ 86VIAK Rf it AT ELN DATE 151782 k A HIB Issue 6 6 DRAWING NO D12662 BUS INTERFACE AWD coWTKOL LOCK T 1 ac MODIFICATION ae ER Er we 4001 opiind t007 gr uc 4 2516 BI Geen BA pe Dios va pa r DEMEMFEN pEio n p Pi p2 4 94 ys Pi yp 1 ti Ae SET Miont o VIL 1 3 VIC DLL NN DNE UN Edo AE mee wp Port en oita Maren ass gt DI pb nl PS a D3 mo ib FS m AI DI Ar ng D pi Pa Gawn p kadus Anni ERAV BANKI BANKS Powt buf LU OP Tei KAM AK rg at ff ER sS YA YL RACH BB e silja e mm w w e Vie T T v c He 240 ok I
36. A Data 25 SIO B Data 26 SIO A Control 27 SIO B Control Transceiver Connection Early 480Zs have a pair of DIL sockets for connecting a piggy back transceiver board NET2 12V isolated 1 14 OV isolated 2 13 12V 3 12 5V OV 4 11 8MHz 800kHz 5 10 IN2 IN1 6 9 Wait OUTO 7 8 SWait NET1 RxD 1 14 RxC TxC 2 13 TxD DTR 3 12 RTS CTS 4 11 DCD 5 10 6 9 7 8 8MHz 3802 Transceiver NIB Connecting Cable For using a 480Z Transceiver with a 380Z Network Interface board 8MHz 1 J2 8 OV 2 800kHz 3 J2 14 OV 4 TxD 5 J2 13 OV 6 RxD 7 J2 1 OV 8 RTS 9 J2 12 CTS 10 J2 4 DTR 11 J2 3 DCD 12 J2 11 12V 13 12V 14 Trcv Present 15 Chassis 16 7 9 gem resistem AY 380Z Host Interface Board SECTION 8 HOST INTERFACE BOARD INTRODUCTION This section describes the low level hardware operation of the Host Interface board HIB The design objectives are considered first followed by the general description and use of the different on board modules DESIGN OBJECTIVES When Research Machines decided to look into winchester systems the most convenient method of interfacing to the 3802 was via the IEEE interface This was mainly due to availability and cost of winchester drives The first non released systems were using 8 inch IMI winchesters with an IEEE interface The introduction of the network system showed the full potential of the winchester and cost and speed o
37. BFDH FBFEH FBFFH Port O Read keyboard port Write system port 0 PORT O BIT ALLOCATION READ BIT WRITE KBD BIT 7 7 PAGE SELECT 0 PAGE 0 KBD BIT 6 6 CLR COUNTER 1 CLEAR KBD BIT 5 5 CTRL 2 Cass motor RE GE ee AN NN RUIN 380Z VDU 40 Board Cont d KBD BIT 3 3 CTRL 1 Cass motor KBD BIT 2 2 VDU ON 1 Screen Open KBD BIT 1 1 NMIEN 0 NIM enabled KBD BIT 0 0 KBD CLR Port 1 Read counter Nriterno port PORT 1 BIT ALLOCATION READ BIT WRITE 62 5 kHz 31 25 kHz 15 625 kHz 7 81 kHz 3 91 kHz 1 95 kHz 975 Hz 487 Hz J A 0 b WN O i Port 2 Read system port 2 Write no port PORT 2 BIT ALLOCATION READ BIT WRITE LINE ACCESS FRAME ACCESS CASSETTE SIGNAL CASSETTE VOLUME RESET BUTTON 1200Hz KBD STROBE O N W d 0 DA J I Port 3 Read user port Write user port IC 23 is used to uniquely decode each of the 4 ports using IOSEL from the CPU board and BAO BA1 MEMRD and MEMWR The keyboard port functions as follows A negative going edge of a keyboard strobe clocks data into two 4 bit latches which form read port 0 KBD STROBE is also available as a bit in system port 2 read port 2 and is tested to detect keyboard input Keyboard data may then be read from port 0 the latches may be cleared by ei bit O in system port 0 2 5 3802 VDU 80 Board SECTION 3 VDU 80 BOARD INTRODUCTION This section details the circuitry of the 80 character VDU VDU 80 board suppo
38. CD are buffered and taken via a ribbon cable to either e a 15 way Cannon D type connector mounted on the rear panel or e an Internal Transceiver Board 12V DC is also provided to the interface to power the transceiver A 7 2 3802 Network Transceiver multi way cable up to 30 feet long connects the computer to the external transceiver Collision status is monitored by the CTS modem input Tx Enable is controlled by the DTR modem output RS232 Interface J2 Circuit NET 2 This is similar to the current SIO 4 but with improvements Standard data rates of 38k4 and 19k2 baud can be accommodated The interface may be driven by polled interrupt or DMA operation All the signals go via a DIL header position Header C to a 20 way header and to the rear panel via a User I O Cable This is a cheaper and more robust alternative to the current SIO 4 cable All signal and modem handshake reallocations are dealt with at the DIL header position thus avoiding the normal confusion regarding soldering cables The header position is prewired for normal DTE operation To convert to DCE operation the PCB links should be cut and pin pairs 1 14 2 13 3 12 4 11 6 9 and 7 8 should be wired together Header C SIO Channel B TxD 1 14 BA RS232 signals RxD 2 13 BB RTS 3 12 CA CTS 4 11 CB 5 10 CC DTR 6 9 CD DCD 7 8 DF Timing There is an on board 16MHz crystal oscillator for all timing This is divide
39. CH is converted to CMOS compatible level via 91 and drives the select input of a 2 1 analogue multiplexer CMOS IC 7 According to the level of SWITCH either 2400Hz or 1200Hz is transferred through IC 7 and appears on IC 7 14 at a much reduced amplitude approximately 100mV pk to pk and via C1 R1 to connector J1 25 as CASSETTE OUT The cassette input is A C coupled via a low pass filter R3 R4 C2 C3 to a segment of op amp IC 8 operated in open loop mode Transitions between supply rails occur at the output pin 1 on each zero potential transition on input pin 2 R11 converts the output level to be TTL compatible and the signal produced is CASSETTE SIGNAL which can be read as a bit in system port 2 Simultaneously a bit is available in system port 2 CASSETTE VOLUME which indicates adeguate inadeguate signal strength on the cassette input line Signal strength is detected by another segment of IC 8 wired as a simple comparator with a DC potential formed by RB and R9 This amplitude detector is sensitive to phase and so the output can be used with CASSETTE SIGNAL to deduce the phase of the cassette input signal All decoding of cassette data is carried out under software control by support routines within COS 380Z VDU 40 Board CPU Board Reset Circuitry Circuit 380Z VDU 1 e Power on Reset When power is first applied to the system a small amount of dedicated circuitry ensures reliable system initialization and does
40. Diagnostics IDC DIAGNOSTICS Symptom 6 System takes a long time to boot or does not quite boot Tests Check LK 6 disc size select Check R3 R5 R47 in place Check Change Data Separator cct IC 17 MB4393 IC 26 MB14323 IC 33 MB14324 IC 32 SMC9216 IC 31 LS157 IC 21 24 25 LS123 IC 2 LS244 IC 38 LS27 6 12 3802 IDC Diagnostics IDC DIAGNOSTICS Notes on the Use of IDCFLASH Insert IDCFLASH in ROM socket and switch on Is LED flashing at about 3Hz Y All data bits are OK on 280 data bus D AO A4 OK on Z80 address N bus A AS A12 on Z80 address bus not shorted high but could be shorted low Check for shorts on Z80 data bus DO D7 Drive select port IC 39 decoded OK Run ADDFLASH next page Check for shorts on Z80 address bus Check change LED Flat nearest J3 Bad intelligence Check around 280 for clock Shorts opens control signals bad Z80 3802 IDC Diagnostics IDC DIAGNOSTICS Notes on the Use of ADDFLASH Insert ADDFLASH in ROM socket and switch on Does LED Y twinkle briefly 280 data bus OK DO D every 3 sec 280 addr bus OK A0 A12 Check Change host interface N Is LED N flashing at a11 If IDCFLASH works OK then check A5 amp A6 The LED flashes slowly pauses for about 3 secs and flashes again indicating the following 280 address bus faults flash A7 flashes AB
41. E BA9 J3 20 71 1 19 6 A bo bo po PERA B d DWR 6 WALSST6 D I pow BAI 3 12 7 A a 8 BOIR DRDWT HWR DHW o 3 e DSTRO DOST sasa co 9 E Do Ne dud 9 PME 4ALS1244 16 HSTRD DHST BAL 13 15 SIOEN BAS 03 16 PAL 1216 2 e HSTRO BAS S HRD RESET 11 13 BPAGE HWR er a Ic j i marro d DRD D DROWT HHA KE Jo um vec 3 HW RESET 112 pS 13 2 H R Q Y D J 3 HTIMED HWR HRDWT c onw ZU HRD Ho BAB RE b IWR HTIMED En i ALS o wenn LK epi s E ae To IC o waro BA7 gt A HRD PR PD HROWT SGP oe 12 10 BAM 33 25 AW un DWRWT 1c22 HE DWIP dd 9 BAIS 33 26 A15 B DWR AA UNLESS OTHERWISE STATED ASSUME N ANGULAR TOLERANCE 1 2 RESEARCH MACHINES WHOLE UNITS t 0 6mm 1 DECIMAL PLACE t 0 1mm RESEARCH MACHINES LTD Mili St Oxford 0x2 08W GEOMETRICAL TOLERANCES SEE BS 308 METRIC TITLE THIRD ANGLE PROJECTION s CTS E CIRCUIT DIAGRAM IDC 3802 A BUS INTERFACE DECODE DRG No D12559 Sht 1 of 4 PAAMPTINTS 0201 st ala Date leen sis oni ssa ASS ret Eoo aa Vcc TXDA 8 Je 123 125 Y A IMA AAA IA RXTXCB Mi Bo 1D6 106 DE SYNCB RN2T ve RTSA 3 9 TXCA 10 LK A13 gt D5 105 105 D tb WAIT1 x en E A2 D4 ID4 Chh ID4 E
42. E a es e ur D2 02 Ni 01 DO SIR SLI R9 l 4KI 8 A WG INLIA P D3 19 100p KO 0 90T RESEARCH MACHINES LTD Mii St Oro 0x2 23802 KEYBOARD UNLESS OTHERWISE STATED ASSUME ANGULAR TOLERANCE 1 2 WHOLE UNITS 0 5mm 1 DECIMAL PLACE 1 0 1mm GEOMETRICAL TOLERANCES SEE BS308 METRIC THIRD ANGLE PROJECTION E AAROUE 4342 83 198 RESEARCH MACHINES LTD KN Gg TR ea dr mn RAR Ti FS2 ri 6 E See Note3j a io SES Ch ia L70nF 4 7pf gu FS3 35v Saves 63A S DELAY s REG 2 tados i 12 7812 C5 2 39V CHASSIS PLUG FILTER D ni 6A 250v Hz ju lal tl Ci l SE B di i Gu 151 910 GE EN M u A a Ci REG3 L ca pee M 78H05 4 ep li ZR WAA 235v co lar Jee Pos 06 i 20nF 4 7pF 4K7 174001 1N4736A A Ui E LK2 d a A AAA 5v O GN EO a 70 i ta Ti lt gt GN S BR3 15 000 pF K7 220nF 4 JpF 4K7 e BYW21 24 J w BEL t 525 ORAE s i SITEN NE CHASSIS DEARTH POINT SYSTEM EARTH NOTES 1 WHEN REG 4 8 ASSOCIATED COMPONENTS ARE e DRAWN BY CHECK z FITTED CUT TRACK AT LK2 Research Machines Ltd 21K1 MAY BE REPLACED WITH A RESISTOR R6 A 3 TO INCREASE OUTPUT VOLTAGE OF REG 3 er TDRAWING NO o 3 FS1 T9 BF LITTLEFUSF TYPE 314 001 OR APPROVED EQUIVALENT 3807 SUPPLY CT DIAG D10875
43. IMED if this time out occurs Also to speed up any INIR or OTIR that may be in progress at this point further wait states are disabled until the status port has been read by the host Z80A This latter function is accomplished using a 74LS107 as the time out flag The 74LS107 also holds off superfluous wait states by grabbing hold of the CLEAR line on the 74LS123 The wait state and time out structure for both directions is similar except for the actual time delay used It is possible that the host system may be interrupted e g if multi tasking and will leave the IDC board alone for quite a while Therefore it is desirable to have a long time out period for the IDC board and avoid the need for dynamic RAMs Since the initial IDC design there has been a great improvement in communications software Consequently wait states and time outs are avoided especially on standalone 3802 D systems where HRG RAM could easily be corrupted External Decoding Circuit DC 1 4 The bus direction signal BDIR is decoded by six address lines IA2 to IA7 together with control signals IIORQ IWR and IRD This is done to i ii iii and iv enable the CTC and SIO CTCEN and SIOEN read the host Z80A status port HSTRD read the internal ZB0A data port HRD write to the host Z80A data port HWR The PAL decodes I O ports as follows 5 4 yes ete A ONO v Ac KTP M m v 3802 IDC Board CTC EOH
44. IP m IWD 116 D WDATA 32 22 RAWREAD 32 30 RDD REV 3 XRDY er 12 D3 SP Pp STEP SECTOR 2 4 BSECT BSECT FCLK D2 Vo Qi s READY 1MHz WA D1 A vc 1 de 19 2MHz Ni MONO BINT XCK5 ROATA REV 5 XRDY JANI DRV3 RDY N RCLK DR REV 3 RDY DC LK6 Ri idi READY1 lo d x MONOS 0 wD DRVO ir XRDY BMHz EE NG READY Ti a _ 47 1K6 LINK PINS18 2 WHEN USING 8 DRIVES 8 BASF MONDE 4 INTRO SA DRIVES LINK PINS283 IF USING YDSZDRIVES RW po 38 VFO DIGITAL MODULE 1 IC26 MB 14323 4 KO 1 Vcc VFO DIGITAL MODULE 2 IC 33 MB 14324 RDD UA 16 8 ZA 32us 20 MONO 5 UNLESS OTHERWISE STATED ASSUME ANGULAR TOLERANCE 1 12 WHOLE UNITS 1 0 5mm 1 DECIMAL PLACE t 0 1mm GEOMETRICAL TOLERANCES SEE BS308 METRIC THIRD ANGLE PROJECTION 6 ci A RESEARCH MACHINES RESEARCH MACHINES LTD Mill t Oxford OX2 OBW E TI EET t os A RESEARCH MACHINES LT CIRCUIT DIAGRAM IDC 3807 DISK DRIVE INTERFACE PP THU DRG No 012559 Sht 4 of L ri ANFRINTO aso 163 ris mea gpd Vo af GE REN tt ae VC 31 45 vec 31 43 Vcc Vu JS feni fp Jo MAP KL fs ES p lt op EL PAC par trib o Mou 1404 boy 114001 E ci c2 13 p QiocN p x Gp
45. OL x WE mi H LOG pi Want JA TY En GU TN namen DBEN N W i nx MAP Y o PMAAT COS 1t An 8 forro E ai nib e EN OKY 0 s ee i EkAo er el lu S _ E iQ 13 PMACN Ta i i z 35 PAK ERO id 1612 IWSTALLCD ONLY SE tdi TArt BivT INT T5 DMA OPTioV 2 sa Da A BEAK gersu Rf SH Ene ORI DRAWN BY CHECKED BY Research Machines Ltd DRAWING NC z lt o ja O O BUS IMTCRE ACO Awp coNTROL LOGIC HIB iss 2 Hif MA AO ji ads emikukinnot PATER nananana A ege TN 2 VL Ma lib eed Lise TN 192 D Ss ni Al M op md VL AYA ennn A Pea poo ee nt NY PAPS AN LN Aid d Di A AI Ay u 0625 i IN pp ja pb Ki PI vt ng po i Py vp D3 pi Y pa E kh pd Bra np Vi d V vz Bech y GAnk v4 GAS Ky ys BANKS Yh y e fu eat fronto z O lt 2 a O d 4 a ni nomas pan Ut 1 v Aw KARI J yE 219 6G NG 49 Ex eeu sio AL KATI si A En gt B A fN A C 1 E pasa Ab a AZA Yi v2 fitv G A7 Ab AS Au A3 n IL as ra Ye e eM N ET seater wrytt Prvoj 12 ew ag a Gera re end get j KA PRE STE eet Vo ik 5 E E An Au 0 vn VI wo D7 vi PS Sayo a a E ar li 25 PC Cow dk RAC 231 2xk 22 ok un 2 STATIC 70 RAM di V AC 22 Tu 7 s3 tb i as l Research
46. PREWIRED KINKY BEFORE FITTING SOCKET A HRADER HEADER C ll Pis Du Sib 26232 USUAGE a NOT WORMALAY INSTALLED Sta DATA k HOMMA ONTROL Sica in Su Polo ki Fort Fria SOCKET xn WEADER a 5 4 7 Pho MEADER GETS A Sa wwe AS pce Mg Fay Du SIOR RS 231 USUAGE NOT NORHALLY WSTALLED CAT VECASCNEY E PATA K obe Cowo SIGNAL PIME HAVE BEN cut ONLY Vani Came N IS 4232 DRAWING NO 3807 NET 3 BOARD CONTROL Weg E pua Se r emie m w vumm Reeg ET rr ew mg zb Ze 8MHr XI 16MH1 3908 RB 340x Pork x Sure i Deeg E di Pk COUPLING 17 v gt CT S A ce 504 LT E J IWArTo FU B Ib 197 2 14 N os Bes IDE TX 3 i CUTA GN Os 05 bs aion Ea 53 IDL IDI WAIT STATE PROTECTION 20 E ID3 ID3 A wart EATY ROUTIN Gr C o Be 192 102 7 10 191 1D1 SS YA Ge 10 Ibg Dia SWITCH REGISTER A pvp OPT ow DEVICES Nor Coco DP 17 42 1 D DMTICH ENAS CREG tag DRAWN BY CHECKED BY Research Machines DRAWING 4807 NET A TITLE KEES NETWORK COMMUNI CATIONS BOARD MISCELLANEOUS FUNCTIONS h w P OGA Pisoni A it I rra a s m mmm mme hi 200mm DO NUI SCALE REMOVE ALL BURRS auaYner U 100 DRG No 446 9070 SK 1 rr L s 1 PIN j KT DIL SOCKET Sv W EN EN mE I 10 p s D6 N 26 DS ee D
47. acter mode four address bits are latched in DU 74LS173 Character and Attribute Memory Circuit VDU 80 2 VDU 80 3 The characters are stored in CW HM6116 while the attribute bits are held in BU and CU 2114 The characters are latched in DW 74LS273 and the attribute bits in part of AS 74LS374 The characters are read and written using DV 74LS245 When a character is written the corresponding attributes are cleared For this purpose 1k2 pull ups are provided on the 1 data lines of EU and CU When the attributes are themselves to be read or x written the data is passed through DR 74LS240 The data bus buffers consist of BR 74LS373 and AQ 74LS244 BR is a latch to hold the data long enough for a write to take place when using the transparent mode Character Generator Circuits VDU 80 1 VDU 80 2 The character generator is the ROM EW 2516 or 2532 together with the RAM GW HM6116P The information from the character latch is applied as an address to these memories along with four bits from the row counters The data is latched in the shift register GV 74LS166 from where it is shifted out as video information The RAM portion of the character generator 3802 VDU 80 Board allows for user definable characters To store these characters both address to select one row of the character and data the dot pattern for that row must be supplied The character generator can also be read back by the CPU
48. and a latch IC 4 on the CPU board together with a 20 way connector form the user port interface Input output is taken directly from the data bus and control circuitry is found on the VDU board 1 5 M A oot SS AAA NU AAA A N St A 3802 CPU Board BuUTUTL WA 210574 Hq3 YN NOILINILENI HLL VOH 07 NOILINWIGNI 21249 ovas wei mo avaa wei 21242 avad wo 08 2 vnan _ 19434 _ 32242 NOILNIIXE NOIL2mi1 NI LIN3WIIVIASIO H83Ud4 33 HSAU Bra WBLSAS gnt 64K address space FFFF H 8000 3802 CPU Board Page 0 Page 1 ex L RS YY See over X XX C000 T 48K Limit Add on RAM Row 1 Bor HRG RAM 4 Memory switched Y 32K Limit 4000 KS S N 3C00 Reserved for SOS SESSION VDU SISI N C 0000 Figure 1 2 Standard 380Z Use of Memo 380Z CPU Board CPU VDU ports FFFF 7 User I O R W 7 Port 1 R FF00 Z Counter R Z cos Port 0 KBD R W FE 00 Y 1K 2 Wworkspace FD00 4 AUX amp RDY W Z Reset W FC00 4 Memory mapped Ctrl status R W ei 256 pests Data R W D FB00 ab m 1 NG E 236 Reserved FA00 7 F900 Z FG40 FBBF 2 Monitor 128 memory ports F800 7 1K ptions reserved for Z extension user application F700 4 A F600 Z VA 7 500 Ya ROM board ports Z Low address W F400 7 High address W DU and HRG KS Data W
49. clock Memory mapped port decoding User port latches amp s ee 4 e 01 Q amp QU Lal N a ma a db ech a bh E L SECTION 2 VDU 40 BOARD Introduction 2 1 Circuit Description 2 1 Screen generation hardware 2 1 IK static screen memory 2 2 Cassette handling hardware 2 3 CPU board reset circuitry 2 3 Port decoding 2 4 SECTION 3 VDU 80 BOARD Introduction Circuit Description Timing Hardware scroll Address multiplexers Character and attribute memory Character generator Control Keyboard Reset Character write signal CTC Video output Smooth scroll e WW GC G WB C 2 Y OI Y W G uy W e gt P d WWW LA N N N N a sch s SECTION 4 FLOPPY DISC CONTROLLER BOARD Introduction 4 Circuit Description 4 Bus buffering and port decoding 4 Port O 4 CTC usage 4 8251 usage SIO4 SIO6 4 Dedicated disc controller 4 i SECTION 5 SECTION 6 SECTION 7 SECTION 8 3802 Service Manual INTELLIGENT DISC CONTROLLER BOARD Introduction Design Objectives Hardware Bus buffering Bus interface External decoding Clock generation Serial interface Memory Internal decoding Control ports Disc control INTELLIGENT DISC CONTROLLER BOARD DIAGNOSTIC NOTES How to Use These Notes Diagnostics Further Helpful Hints 280 Signals Modifications NETWORK TRANSCEIVER OPERATION Description Network Interface Board Network interface RS232 interface
50. d The reset circuitry lies mainly on the VDU board where a 2400Hz signal is synchronized with the M1 cycle so that the processor only receives active low reset during M1 cycles This ensures that RAM contents are not corrupted during reset In the absence of reset due to a CPU board fault which usually results in garbage M1 should toggle to enable reset pulses on the VDU board power on reset excluded When power is applied to the Z80 M is inactive until the processor is reset Absence of power on reset reaching the processor will normally result in inactive M1 and no response to the RESET button The situation can be very Catch 22 if this is not borne in mind when tackling faults around this circuitry Bus reset is buffered by a transistor to drive the bus processor reset is inverted by a segment of IC 20 to drive pin 26 of the Z80A CPU One wait cycle is inserted every memory cycle in the following way on the first rising edge of the system clock after MRQ becomes active low start of memory cycle MRQ is clocked through D type flip flop IC 22 and appears as a high on the Q output pin 8 One system clock cycle later it appears as a low on the Q output pin 5 Both outputs are then NANDed by IC 20 The output of IC 20 is WAIT and is exactly one system clock cycle in duration with a delayed one clock cycle inverted version of itself produced in the other half of IC 22 The output of IC 20 pin 13 is WAIT and is exac
51. d by 26 in hardware to produce a master times sixteen baud clock 615kHz from which all baud clock rates are derived by CTC channels All CTC triggers and zero counts are taken to a DIL header position together with the master baud clock and another divided down signal 600Hz CTC1 is intended for system timing interrupts ims 2ms and 20ms The most usual configuration will be prewired but is easily changed by cutting PCB links and soldering a DIL header in Header B position Header B CTC 1 Tro 1 16 Tro CTC2 SCH 2 15 SCH Tri 3 14 Tr 2C1 4 13 ZC 1 cascaded Tr2 5 12 Tra ZC2 6 11 ZC2 Tr3 7 10 Tr3 600Hz 8 9 Baud Clock 615kHz prewired to 600Hz prewired to baud clock 3802 Network Transceiver PA Interrupts Full standard priority daisy chain patching has been implemented which is compatible with all recent 3802 boards Red BIEI Black BIEO If other boards operating with interrupts are used the daisy chain must be connected using the interrupt patch cable provided with the board The on board priority is prewired at a DIL position but may be changed by cutting the PCB links and using a DIL header The default priority order highest first will be SIO DMA CTC1 CTC2 Header A CTC2EO 1 14 CTC1EO 2 13 CTC2EI DMAEO 3 12 CTC 1EI SIOEO 4 11 DMAEI BIEI 5 10 SEOEI 6 9 DMAEO 7 8 DMAEI DMAEO and DMAEI are shorted with a prewired link between pins 7 and 8 of Header A If the DMA
52. e first stage of the vertical counter FT 74LS390 When the smooth scroll is being performed this multiplexer is switched over to take the dot row number from the latch DU 74LS173 Thus the CPU controls the rows to be displayed In conjunction with the scroll count in CR 7418377 the software can make the picture move by one row of dots per frame giving the appearance of a smooth scroll Se gOS UNA 3802 FDC Board SECTION 4 INTRODUCTION This section details the circuit description of the floppy disc controller board FDC used in all 3802 disc systens Hardware differences between versions for supporting different drive types are included CIRCUIT DESCRIPTION Circuits 380Z Floppy disc controller and SIO4 FDC1 and FDC2 The floppy disc controller board contains circuitry of two types 1 Hardware to support a serial interface with full handshake the SIO4 port 2 Circuitry for dedicated disc controlling purposes The board is accessed as a block of po FD o MDS 5106 _ EF CF 4F miim as so tin E Cui ra cocus os ua aa asan an asa Caca A ken kan CTC E8 C8 48 8251 E4 C4 ss PORT 0 EFE0 C0 FDD 1771 1 Bus Buffering and Port Decoding Circuit FDC1 The least siet Eeler eight bus address lines BAO to BA7 are buffered by IC AQ and b
53. ecome IAO to IA7 The board is accessed using I O instructions such as OUT C A IN C A etc The port address appears on the least significant eight address bits IC BO and BR 3 to 8 line 3802 FDC Board binary select line decoder decode IA2 to IA7 to establish the map in I O space as above IC BR has four outputs CTC EN 8251 EN 1771EN and port 0 enable Each of these represents a block of four ports corresponding to each function All four outputs are ORed by IC BO to produce IOEN Links 10 and 12 select whether the board is to be mapped as a full links cut or mini links present system disc controller board Data is transferred via the bi directional tristate buffer IC AR The direction of transfer is selected by the logic array formed from ICs CP and BP This uses either IOEN and IRD to detect when one of the ports on the board is to be read by the CPU or INT at the first IM1 low with IIORQ to reverse the direction of the buffer IC BP 9 ensures that the direction is reversed only during IORQ operations Bus and CPU control signals are buffered by IC AP On the circuit diagram these signals have the prefix I Port 0 is not fully decoded and occupies all four port addresses within the block assigned to it IC BP 6 3 produces IORD and IOWR from IIORQ IRD and IWR IOWR is active during all I O writes within the system and is used by IC BP 11 to enable the port 0 latch IC BS only during I O writes to
54. es The address bus is buffered from the processor by ICs 8 9 and 10 All 16 bits are transferred directly to the 50 way bus J3 11 26 and the least significant 11 bits BA0 BA10 are transferred to the VDU board via the 34 way bus J2 24 34 With the exception of external bus Request Acknowledge cycles the processor drives the bus exclusively and the address buffers are constantly enabled EPROM and EPROM Support Circuit 380Z CPU 2 There are three 24 pin sockets on the CPU board so that either 2716 or 2708 EPROMS by link connections can function in any socket The sockets are generally known as 0 1 and 2 COS monitor program occupies at least 4K of addressable ROM space and always occupies ROM in sockets 0 and 1 COS 3 0 3 4 or all three sockets COS 3 0 2708 s in 1 and en COS 4 0 and COS 4 2 2716 s in 0 1 and 2 Eleven address lines are required to uniquely address 2K of ROM The least significant addresses BA0 BA10 are used to select the address within ROM to be read Coarse address decoding is performed by PROMs M and P ICs 13 and 19 using the most significant six bus address lines and one page bit In this way ROMn ENAB is generated and each ROM is mapped into address space within a 64K page Two pages are currently available ROM 0 is napped at 0000H on page 0 to execute code on power up and normal 380Z page 1 mapping is gelected on setting the Page Sel bit in system port 0 Once ROMn ENAB is hot
55. ets are detected the transceiver synchronises the 800 kHz clock to the received clock and provides this and the received data to the SIO When the common bus is idle the transceiver must provide a logic 1 data level to the SIO DTR is used as a test mode signal When asserted by the SIO the transceiver should assert DCD to show its presence When DTR is asserted and a collision is detected on the common bus between two other transceivers DCD should be negated for the duration of the collision Collision signals should not be generated by a transceiver in receive mode disconnected from the common bus cable To disable an internal transceiver Research Machines external transceivers should ground the transceiver present line on the network interface 3802 Network Transceiver 3802 NETWORK INTERFACE BOARD This board is a multi purpose board and may be configured either as a Network Interface Board NIB or as a Dual Serial Interface Board The relevant circuit diagrams are 380Z NET 1 Version I 30th March 1982 3802 NET 2 Version F 30th March 1982 380Z NET 3 Version H 30th March 1982 380Z NET 4 Version B 30th March 1982 In this configuration as a Network Interface Board it will upgrade a standard 3802 into a network server when used in conjunction with a 3802 Internal Transceiver Board or an external transceiver The serial interfaces are based around the dual channel Z80 SIO which is capable of operating under various asynchr
56. f access led to deeper research of the winchester market The introduction of the 5 25 inch high capacity winchester brought a reduction in cost A more convenient standard interface the SASI Shugart Associates System Interface was introduced to interface to the new generation of winchesters This meant that a new board would have to be designed in order to interface the 3802 to SASI This new board would also have to work in a heavily interrupted environment and at high data transfer speed The hardware had to be readily available and also of relatively low cost The MEI HIB was therefore introduced with extra options namely an Option Boot ROM 16K by 8 Static RAM and DMA It was soon realised that the options were adding to the cost and no real use could be found to justify the extra cost on a server Although MK1 HIB boards went into production no options were fitted and the basic board design was not changed The MKII HIB has minor differences to MKI and IC positions are indicated by numbers instead of letters Both sets of circuit diagrams for MkI and MkII are included with this section THE HARDWARE MODULES The HIB circuit consists of a few hardware modules together with some logic to interface the various modules Particular attention is paid on grounding the HIB to SASI The modules are as follows Bus Interface To connect the HIB to the 3802 bus e Bus Decoding To decode I O and memory mapped ports Memory The on b
57. he video RAM is decoded in the character generator IC 27 and identifies a unique character The five outputs Y1 to Y5 are the row dot pattern corresponding to the row within the character selected by inputs RCO to RC3 Y1 to Y5 are latched by IC 28 at the start of each new row within a character then fed to IC 29 8 to 1 binary select demultiplexer CCO to CC2 select which of the five column bits to transfer to output pin 5 IC 29 In this way row data is shifted serially through IC 29 and becomes video information on pin 8 of IC 43 if not inhibited by GRAPHICS on pin 11 IC 43 Video information is inhibited by composite blanking in IC 38 and VDU ON in IC 40 VDU ON is used to open the screen to write to the video RAM and is normally only active during screen blanking to prevent flicker A VDU ON is under software control and is a bit in system port 0 Video information VIDG is conditionally duplicated condition white graphics to form VIDW If VIDW is inhibited grey active the video information formed by adding analoque VIDG amp VIDW is half the amplitude that would gars generated with VIDW active and grey intensity results D1 D2 and R25 form the video sync mixer The video output stage is a common collector transistor impedance buffer Output impedance is 75 Ohms and level 1V peak to peak composite video information ve sync Power for the video output stage is derived from the 12V rail via R35 and D3 A s
58. heck disc interface DRIVE O0 LED IC 3 IC 2 IC 38 IC 1 on IC 39 IC 34 amp Data Separator LED indicating Bad intelligence Go back to symptom 2 Short DRVO ICI 12 to OV Is DRIVE 0 LED Suspect drive on Check change drive select cctry IC1 IC39 CTLWR IC39 11 IC42 18 AO IC39 1 6 9 ps IDC Diagnostics IDC DIAGNOSTICS Symptom 5 No boot error message appears instantly 3802 only Tests Press B to boot Go to Front Panel CTRL F amp look at I O E8 type EB Reads FF Y at E8 to EF Check change host interface IC 19 IC 4 N Reads FF Y at EC Check change IC 19 IC 18 IC 27 N Reads 40 Y at EC Check change IC 9 Other Symptoms Breaks 3802 4802 4802 4802 4802 SYMPTOM to Front Panel on boot lt boot fault gt or lt boot err gt lt drive not ready gt lt boot error gt lt disc error gt lt boot gt 3802 IDC Diagnostics CAUSE Probably an unformatted disc Wrong disc or no CP M Could be faulty cable s faulty disc I O buffers IC 1 IC 2 IC 3 IC 8 Could be faulty disc or bad data separator IC 17 IC 26 IC 33 IC 36 IC 31 IC 24 IC 25 IC 32 Could be that the IDC is not communicating Check SIO IC 40 IC 6 IC 7 IC 15 IC 16 and intelligence Use tests in Symptom 2 Wrong or bad disc 3802 IDC
59. ignal HWR DWR by delaying and inverting the signal to give DHWR and DDWR then ANDing the two signals This produces a CLEAR pulse of 125ns less various propagation delays There are two flip flops IC 20 A and B one to represent the state of the data bus interface in each direction Flip flop A is CLEAR 380Z IDC Board HWRWT is low DRDWT is high when data is available to the internal Z80A and thus cannot be written to again by the host ZB80A Flip flop B is CLEAR DWRWT is low HRDWT is high when data is available to the host Z80A and thus cannot be written to again by the internal Z80A Take the flip flop A as the example when the host Z80A writes to the data port the flip flop is set CLEAR at the end of the write cycle by the edge detection mechanism When the internal Z80A comes to read the data port the flip flop is SET at the end of the read cycle using the 74LS74 edge triggered clock input If the host Z80A tries to write to the data port whilst the flip flop is CLEAR or tries to read the data port when flip flop B is set then a wait state is generated and a time out is initiated by triggering a 7415123 IC 30 If the wait state persists for longer then 200us or so a fault has occurred the 74LS123 will terminate and cut off the wait state to the host Z80A It is conceivable that the software could recover from this situation in some circumstances so a flag is set DTIMED or HT
60. imple UHF modulator accepts composite video input and produces a UHF modulated copy Carrier channel is around channel 36 The character generator IC 27 is a TEXAS 7415262 which has a teletext compatible character set and is an industry standard It accepts ASCII coded input for codes in the range 0 to 128 Above these values codes are interpreted by the VDU board as graphics characters These are generated by the dual 4 to 1 binary select multiplexers IC 35 and IC 42 latch from information encoded in the hardware of the logic array formed by ICs 38 39 and 40 Graphics is selected from MD7 ASCII codes greater than 128 and grey intensity is selected from MD6 1X Static Screen Memory Circuit 3802 VDU 1 One page of video information is stored in static RAM on the VDU board to enable screen displays of 40 x 24 characters To uniquely address 40 characters in a line six address lines are required and for 24 lines in a frame 5 address lines are required Thus to specify each unique location on the screen as part of a rectangle would require 11 address lines Using 1K static RAM only 10 address lines are available so it is necessary to address the screen as a 5x5 address square and move part of the square to a screen position such that a 40x24 shape screen results Awa WW a 380Z VDU 40 Board mmodates the transfer of screen address position by detecting when CC8 is valid and adjusting the output of mult
61. ings of two signals controlled from Port 1 IC 34 The 74LS157 multiplexer IC 31 is used to select the different signals for use with 5 25 inch or 8 inch drives The links are pre wired for a YE Data separator but to enable use with the SMC 9216B separator and BASF 610X drives a set of links is provided to change the functions of some pins YE data separator link LK3 2 3 LK3 5 6 LK4 1 2 SMC 9216B link LK3 1 2 LK3 4 5 disconnect LK4 For 5 25 inch drives BASF 6106 6108 link LK3 8 9 YE Data YD 274 link LK3 7 8 For 8 inch drives link LK3 8 9 There are two types of data separator catered for in the design The YE Data 3 chip set e The SMC 9216B single 8 pin device The links required to operate with the two types are described above but it is also necessary to remove the data separator chips that are not required Therefore for use with the YE Data separator remove the 9216 IC 32 for use with the SMC 9216B remove the MB4393 IC 17 MB14323 IC 26 and MB14324 IC 33 The YE Data separator also requires several other components some of which should be of fairly close tolerance The two monostable chains terminated by MONO8 IC 24 and MONO5 IC 25 require the first element to be within 5 of 2 5us and 5 0us respectively i e 0 125us and 0 25us The FDC chip requesting data is used to trigger the monostable IC 21 non critical which decreases the gain on the phase locked loop MB4393 The 100pF capacitor C28 on
62. iplexer IC 14 accordingly With the exception of this complication multiplexers 11 12 and 13 select between access to the screen for reading row and column address specify character position and access to the address bus for writing a character written to a unigue address corresponds to a character position when read back by the screen Ten address lines MAO MA9 address the 1K of video RAM Data input is taken directly from the data bus BDO to BD7 and is written to the RAM when VDUWR is decoded by IC 25 Data output from the RAM forms the bus MDO to MD7 which feeds the character generator and graphic generator circuitry Provision is made to read the video memory to the data bus BDO to BD7 by opening the screen VDU ON inactive and transferring the MD bus to the BD bus via tristate buffer IC 26 Cassette Handling Hardware Circuit 3802 VDU 1 Binary counter IC 9 is clocked by a 16 us clock CC6 It is wired as a divide by 14 counter and the output is further divided by 2 and 4 yielding 2400Hz and 1200Hz on IC 9 10 11 These two clock frequencies are passed through active low pass filters IC 8 and appear as RE waveforms at the fundamental frequencies on IC VT 8 The cassette recording forakt consist of selecting between cycles of 2400Hz and 1200Hz to encode serial information The serial information to be encoded is generated under software control and appears as a bit in system port 0 SWITCH SWIT
63. ircuit VDU 80 1 The keyboard port is CV 74LS374 As this cannot be cleared a separate latch made from two gates in FQ 74LS132 is provided to catch the strobe A filter R11 and C5 is provided on the strobe line One section of the Schmitt trigger EQ 74LS240 is used to clean up the signal which is then differentiated by R9 R10 and C6 to provide a short pulse to set the latch This allows the use of a keyboard which produces a level while a key is held as opposed to a short strobe Reset The reset circuit is similar to the current one as VDU4 Character Write Signal The generation of the weite strobe to the character store is complicated by the transparent access When the CPU performs a write operation it must be delayed until the memory has finished the current character access One section of FT 7415390 is used simply as a flip flop to remember that a write request has occurred This is synchronized to the VDU timing by 3802 VDU 80 Board the latch DY 7415374 and from the latched signal a write strobe is generated by the monostable BP 74221 This strobe also clears the cre The CTC allows interrupts to be generated from the keyboard strobe from the vertical blanking signal or from the line frequency The only non standard thing here is the address decoding To avoid a separate decoder it is mapped in I O space at FBFC to FBFF i e register B must contain OFBH when writing or reading the CTC with an OUT
64. ircuit is included This separates interleaved data and clock pulses from the disc drive READ DATA input into the FDD and FDC inputs to the 1771 It operates in the following way an active high clock pulse FDC is inverted IC ET 8 and loads a 4 bit binary counter CT with 12 The counter counts up with a clock period of 250ns full system or 500ns mini system and places its count output in a BCD to decimal decoder DT When the count is zero the zero output of DT goes low and is used to set an S R flip flop ET whose outputs are DATA WINDOW and NOT DATA WINDOW ET is reset when the binary count reaches 7 and DATA WINDOW is inverted until the next clock pulse and the cycle is repeated Data and clock pulses interleaved are taken from the disc drive and passed through a Schmitt trigger buffer then through a monostable of time constant 120ns approximately before being ANDed EU with DATA WINDOW and NOT DATA WINDOW The resulting outputs are separated data and clock pulses FDD and FDC CU is used to set the phase of DATA WINDOW using the sector header before the sector identifier IC BT is used to multiplex direction and side select information according to MSEL in port 0 Direction is decoded on the drive to be active with STEP otherwise side select information is assumed 3802 IDC Board SECTION 5 INTELLIGENT DISC CONTROLLER BOARD INTRODUCTION This section describes the low level hardware operation of
65. ists of two sub modules 1 FDC chip and buffers 2 Data Separator These various modules will now be described in more detail Bus Buffering This consists mainly of three 74ALS1244N uni directional buffer chips IC 5 IC 10 and IC 11 to receive the addresses and one 74ALS1245 bi directional buffer chip IC 4 which is used for the data transfer channel In addition to these there is one element of an open collector inverter IC 3 which drives the WAIT line on the bus and a three input AND gate IC 29 for the interrupt priority daisy chain The interrupt signal INT from the CTC is also buffered by one segment of IC 1 4 to produce the BINT signal 3802 IDC Board Both the uni and bi directional buffers are permanently enabled with the direction control on the bi directional buffers being driven by a BDIR signal from a PAL Programmable Array Logic 12L6 IC 19 BDIR is low when i the 380Z is reading anything on the IDC and ii the IDC is in the process of an interrupt acknowledge Otherwise BDIR is high The addresses and control lines can be connected to the bus of the IDC processor instead of the host 3802 so that the 480Z version of the board will have access to the externally mapped ports notably the CTC and SIO Bus Interface Circuit DC 1 4 1 Data and status ports are implemented as follows There are two data ports made up of two octal latches IC 9 and IC 18 both SN74ALS574N One supplies da
66. ive follows MRQ timing the 8 bit word stored at the specified address within the EPROM is transferred to the data output lines DO D7 and buffered onto the data bus by IC 11 tristate uni directional IC 11 is enabled by the ANDed function of MEMRD and ROMRD derived form ICs 17 and 19 which ensures that write operations to address space occupied by ROM does not cause a data bus crash Space occupied by ROM is transparent to write operations Dynamic RAM and RAM Support Circuit 3802 CPU RAM There is space on the CPU board for up to 32K of dynamic RAM 4116 or similar organised as two banks of 16K x 1 x 8 bits Bank 0 must contain 16K x 1 bit RAM but provision is made both by hardware and software for bank 1 to be empty or to accept 4K x 1 RAM or to accept 16K x 1 RAM A complete diagram showing RAS and CAS timing within all memory cycles is 1 3 380Z CPU Board shown in figure 1 1 Measurements are taken when executing the following code 0100 LD HL 1000H 0103 LOOP LD HL A 0104 JR LOOP Fourteen address lines are reguired to uniguely address each location within a 16K bank of RAM Bus addresses BAO to BA13 are applied to the inputs of two 2 1 multiplexers ICs 5 and 6 With the exception of a refresh cycle BMRQ is clocked on the first rising edge of the system clock after MRQ becomes active through D type flip flop IC 24 to a low on output Q pin 5 This output is used to switch the multiplexers be
67. laces for shorts are where tracks go between IC pins where there are through holes near IC pins or where modifications have been done especially decoupling capacitors on the back of the PCB lying across tracks 380Z IDC Diagnostics IDC DIAGNOSTICS Z80 Signals The following signals are on the Z80 when IDCFLASH is used A logic probe could be used to check these signals A7 13 1 3 37 40 L A0 6 30 36 I A14 15 4 5 I PHI 6 I D0 7 7 10 12 14 I Vcc 11 H INT 16 L NMI 17 H HALT 18 H MREQ 19 I IORQ 20 I RD 21 I WR 22 I BUSAK 23 H WAIT 24 I BUSRQ 25 H RESET 26 H M1 27 I RFSH 28 I GND 29 L H high L low I changing MA ta 3802 IDC Diagnostics IDC DIAGNOSTIC Modifications The current modifications are FDS Join IC 39 12 to IC 21 3 IC 38 9 to IC 21 2 IC 41 20 to lower side C51 Upper side C51 TO IC 45 14 IC 21 2 to IC 39 12 Under IC 21 to IC 21 3 Add 104 skycap IC 4 20 to IC 3 7 IC 28 14 to IC 28 2 IC 46 29 to IC 46 11 MDS Join As FDS IC 12 11 to R26 end near C48 As FDS IC 12 11 to IC 28 13 Add As FDS AA x Wa 380Z Network Transceiver SECTION 7 NETWORK TRANSCEIVER OPERATION DESCRIPTION A transceiver contains circuitry to encode and decode NRZI data detect carrier and collisions and to isolate the common bus from the station electronics and power supply Data modem handshake lines power and an 8MHz clock are provided by the stati
68. ly The 4MHz signal is passed through an invertor IC 45 9 with a 330 Ohm pull up to generate the CPU clock PHI The 2 MHz signal is used as the trigger input for channels 1 2 and 3 of the CTC IC 44 which can be programmed to generate the desired times 16 5 5 ADDA d 380Z IDC Board clocks for the serial channel A transmit and receive and also for the serial channel B Serial Interface Circuit DC 2 4 The serial interface consists of an SIO chip IC 40 using 75188 line drivers IC 15 and IC 16 and 75189 line receivers IC 6 and IC 7 The signal levels on the lines are nominally 12V and 12V The channel A is selectable to use the Sync pin as Ring Indicate whilst the channel B Sync pin is used for Data Set Ready All the incoming serial control lines have 4K7 pull up resistors to enable sensible use of the interface without the use of the handshake lines The channel A times 16 clocks are also jumper selectable to come from an external pin multiplexed with the Ring Indicate Memory Circuit DC 3 4 There are two sockets on the board capable of taking memory devices One is for EPROMs IC 47 and one for RAMs IC 43 The internal firmware ROM can take any sort of 5V only EPROM up to 8K by 8 by means of a set of links These links are preset to take Intel type 2764 EPROMs The links for other devices are as follows EPROM LINKS 2516 2716 2532 2732 2564 2764 68764 5 8 1 5 6 8
69. mands read write Port O0 OEH Port 1 ODH Buffer RAM EOOOH to FFFFH Internal ROM 0000H to 1FFFH If the ROM is enabled one wait state is generated using half of a 74LS109 IC 23 which is cleared at the end of the cycle Control Ports Circuit DC 3 4 The two ports used to control the static functions of the disc drives such as side and drive select are edge triggered registers They are written with a pulse CTLWR from the internal decoding PAL IC 42 and enabled with two separate address lines Port O IC 39 SN74LS377N contains the signals for drive selects side motor monostable trigger IC 21 SN74LS377N and confidence LED driving The motor signal to the drives is SET by changing the motor bit from a zero to a one The confidence LED is switched on if bit 6 is high and bit 7 is low mm ll s ouz sssss 3802 IDC Board Port 1 IC 34 SN74LS379N contains both the true and the false signals for drive size bit density and write pre compensation enabling and a flag for IDC in use Disc Control Circuit DC 4 4 1 mna All output signals to the disc drives are driven by open collector chips IC 1 IC 3 and IC 8 and input signals are received by Schmitt trigger buffers IC 2 with 150 Ohm pull up resistors S1 The FDC chip used is the 1793 IC 41 or equivalent which can handle 5 25 inch or 8 inch discs in single or double density depending on the sett
70. oard RAM 380Z Host Interface Board PIO chip SASI data SASI control SASI termination A full description of these modules is given below Bus Buffering The address bus is buffered by three SN74LS1244N ICs AA AB and AC and the data bus by IC AF SN74LS1245N The BRFSH signal is buffered by one segment of an inverter IC AK SN74LS14N and outgoing signals BWAIT and BINT are buffered by an open collector IC AL SN7407N Priority daisy chain interrupt is serviced by two segments of IC AI SN74LS10N Bus Decoding The decoding is done by two 12 input 6 output PAL 12L6 ICs AD and AE Addresses A0 to A7 together with control signals IORQ WR RESET and Mi are used to produce decoded signals through PAL IC AD PIOM1 PIOEN MCONTROL and IORD For IC AE addresses A9 to A15 are used together with control signals M1 MREQ and RFSH to produce decoded signals MEMRD and DBMEMEN DBEN Not all decoded signals are mentioned because they are concerned with the original design options Functions of decoded signals are as follows E PIOM1 This signal apart from the M1 cycles to the PIO acts as a PIO reset when RESET is present PIOEN Enables PIO for reading or writing MCONTROL Enables the four most significant bit MSB addresses for the on board memory The four MSB addresses are under software control and the processor will set data bits D2 to D5 accordingly IC BD SN74LS273N latches signals BANK2
71. on Par JEN Be Aw Ramicw p x Di ps d 04 p3 AP 48 Al AS A2 A 10 A3 A mMPEQ AG AZ AS A13 Ab Aig A Als mc FRRY Ae AtSsot ATCD cevThol Vi C vil Ay 34 7 AI MAG ih ne JA AS _ DO NE 2 Ex Parsons SL gai pa RAM sr Jan 2 o EES dd h ea Berro anos AJ RAN dl ev Al Pio An ET SES i RAE N Ab p7 pi ps NOT FITTED Na pu a T ee ee dole gu AIT MAD pif Vas Qawrg 2 13 0 0R MA mk pt Xd ut NE MAS 5 t qa b dio dd 1 seer 2x 6776 RAM MAU m RAM gt ser Bn ere tan A Ens MA ja RD 53 GA K MAI Siet Gg DGE md am MAG sii v GA A Db MAS pi E Ba lE T 02 13 b o mAb n E AA P MAY DRAWN BY CHECKED BY k PA DRAWING NO 012662 46 2 y vro HIB Issue YA Ns pissan SP EDrufemn A YSUCLE TA exc 30 SA SE 331 4 SDi 31 3 Ba 321 6 S92 5s ayatk CLOCK E Oj L HEP d Vs m Ye p 1OKkQ q 1of8 tf ACKUE sp3 61 03 32 19 SP4 33 T a3 HID sw sera Gi w Sp DIM Qu GIO PT G T SAS 16 yy EHE CLOCK Nd VY it fi At 40 JP RVACK DEL AA e QL 106 14 AA IA pi Qs Ses DEL g IEI i des 8518 PILLO eegen JKO Aaf bl as d SEL InT 134 ir agor Ls AKPY q 2 SELACK moy ka 7808 di
72. on The station SIO transmits or receives a SDLC switched packet with a preamble and postamble of flags as defined in the packet descriptions To transmit the SIO asserts RTS and the transceiver asserts CTS if there is no carrier detected If there is a carrier detected i e a packet is being transmitted on the common bus the CTS signal is delayed until the network is idle provided RTS is not withdrawn The transceiver provides an 800kHz clock to the SIO separate from the 8MHz clock Data from the SIO to the transceiver is clocked on positive edges of the 800kHz clock and data from the transceiver to the SIO is clocked on negative edges When CTS becomes true the SIO will start transmitting the packet and upon completion will remove RTS If a collision is detected the transceiver must negate CTS and jam the network with a logic 1 to ensure that other transceivers detect the collision RTS will be negated by the SIO in response to the collision detection The transceiver contains a watchdog monostable which is re triggered by RTS and which is used to limit the transmission time of the transceiver to the maximum packet length The watchdog period has been set to 30us on Research Machines transceivers to allow for future use of 2K packets The transceiver may only transmit onto the common bus while RTS and the watchdog are asserted When not transmitting the transceiver is in receive mode constantly monitoring the common bus When pack
73. on MREQ cycles when the DMA has control of the bus to make memory timing the same as the CPU The Wait Ready signals from each SIO channel are routed to either the Wait line or the DMA ready input under the control of seven bits in the control port register Programming the Control Port omitted on standard board The WRSx signals control the Wait Ready selection Bit 6 is an enable and bits 5 to 0 select any of the 32 possible combinations of SIO channels A and or B operating under Wait state or Ready triggered modes The selections are in a PROM but for fixed non programmable operation a DIL header may be substituted for the PROM Wait Ready A and Wait are connected by a preset cutable link on the standard board Wait Ready Header 16 15 14 13 12 Ready 11 Wait 10 WRA W R B 0 J Ab UN a Programming the SIO and DMA The SIO and DMA devices are treated as a series of internal registers accessible through one I O port address Each SIO channel occupies two ports data read write and control seven write registers and three read registers However these are non symmetrical with certain parts being common to both channels The DMA occupies one port through which all 21 internal registers are accessed by sequences the maximum length is five operations Care should be taken in the initialization and programming of these devices and the use of tables is preferred in all but the most time critical applications The SIO can p
74. onous and synchronous protocols at baud rates not exceeding 800kHz Both channels are capable of polled or interrupt driven operation or operating under DMA or wait state control Channel A is hard configured to be a network interface port and Channel B as an RS232 serial port The SIO may be supported by a Z80 DMA which can be triggered by either of the SIO channels under programmable or soldered DIL header selection The DMA is fully buffered to the Z50 bus and is expandable to allow multiple DMAs in the 3802 The DMA may be programmed to support transfers between the SIO and memory or memory and memory within the 3802 DMA support is an option not normally required the Z80 DMA IC is omitted and the link DMAL connected Baud rate generation is supported by a Z80 CTC and standard rates of up to 38k4 baud may be used Channel A of the SIO has links to select the send and receive baud rates Link A selects the receive rate between CTC2 channel 0 or the transmit rate link B selects the transmit rate between CTC2 channel 1 or the externally provided network clock rate Channel B baud rate is controlled by CTC2 channel 2 CTC1 is available for general system timing An 8 bit switch register as a read only I O port is provided for power up option use The Network Interface J3 Circuit NET 2 This is based on an SIO channel operating in SDLC mode at the maximum clock rate 800kHz Data In and Out Clock In and Out RTS CTS DTR and D
75. pin 1 will go low and a WAIT will be put onto the bus Some types of 8K static RAM may also be used such as the Toshiba type as used on the IDC Interface to SASI The PIO IC CA is the primary unit for interfacing to SASI It handles data and commands through channel A and control signals from and to SASI through channel B Address line A0 is used to select the appropriate channel for data transfer between Z80A CPU and Z80A PIO whilst address A1 defines the type of data transfer to be performed i e data or command Although channel A uses all 8 bits in bi directional mode channel B bits BDO BD1 BD2 BD3 BD6 and BD7 are used as inputs whilst BD4 and BD5 bits are used as outputs The bus clock is fed through one segment of IC AL an open collector buffer with the output pulled up by a 330 Ohm resistor to produce ZCLOCK for the PIO Data transfer between PIO and SASI is done via IC CB an open collector bus transceiver SN74LS642 1N Control to and from SASI is more complicated due to the handshaking procedure Direction of the bus transceiver is under SASI control by signal IN but enabling will not take place at the correct time unless control signals are allowed to settle down This is achieved by taking the acknowledge signals i e select read and write and delaying them by a predetermined factor thus allowing good set up times The delaying takes place at IC CC SN74LS273N by connecting one output to the next inp
76. pins 6 and 7 of the MB4393 sets the free run frequency which should be close to 2MHz RP AA AAA AA AA AA pot e in 3802 IDC Diagnostics SECTION 6 INTELLIGENT DISC CONTROLLER BOARD DIAGNOSTIC NOTES How to Use these Notes These notes look at the various problems that can occur and follow through a logical sequence to trace the fault This may involve visual inspection of a particular section of the board or changing certain components to find the cause of the fault On later boards most ICs are soldered directly into the PCB so swapping of ICs is not advisable until a fault is definitely traced This minimizes damage to the PCB A logic probe would be useful in many places to quickly check that signals are at particular points and that they are not shorted high or low Use these notes in conjunction with circuit diagrams DC1 4 DC4 4 and the board schematic diagram to help understand the fault finding process All symptoms are listed below and each is detailed on the following sheets 1 6 Symptom 1 No COS prompt on power up 2 LED not on 3 LED flashing FAULT 2 1 LED flashing FAULT 3 2 LED flashing FAULT 4 3 LED flashing FAULT 5 4 LED flashing FAULT 6 e LED on no boot e No boot instant error message 6 Long time to boot or does not quite boot Additional notes are appended to this section covering the following o Use of IDCFLASH 9 Use of ADDFLASH e Further helpful hints e Z80
77. roduce up to eight vectored interrupts four per channel In order of priority these are 3802 Network Transceiver Special Conditions Receive overrun End of frame CRC error Receive Character Available Transmit Buffer Empty External Status Change CTC DCD or Synch status change Break Abort detection or CRC detection Channel A has priority over Channel B The DMA can produce four vectored interrupts On Ready before Bus Request On Match with a data byte On End of Block On Match and End of Block Programming the CTC Baud Rate When the CTC triggers are connected to the baud clock standard baud rates may be generated by simple division ratios The control bytes and time constants to provide standard rates are as follows 07H 142 110 Baud 47H 0 150 Baud 47H 128 300 Baud 47H 64 600 Baud 47H 32 1200 Baud 47H 16 2400 Baud 47H 8 4800 Baud 47H 4 9600 Baud 47H 2 19k2 Baud 47H 1 38k4 Baud The relevant byte pair should be loaded to CTC2 channel 2 Mv Bw I TII E n CONNECTORS J1 J3 J4 RS232C Interface HESE Network Interface Clock Out 8MHz Clock In 800MHz TxD RxD RTS DTR 12V 12V 250 BUS BRESET BDO BD2 BD4 BD6 BAO BA2 BAG BAS BA 10 BA 12 BA 14 BUSRQ BUSAK BNMI BIORQ BRD BRFSH OV 5V 5V 5V ov OV 380Z Network Transceiver 3M Header 1 2 3 4 5 6 7 8 9 10 11 12 1
78. rted by COS 4 0 The board operates in two modes 1 24 lines by 80 characters 2 24 lines by 40 characters The circuit is complicated in mode 2 by the need to maintain hardware compatibility with the existing 40 character board CIRCUIT DESCRIPTION Circuits VDU 80 1 80 40 VDU 80 2 80 40 VDU MEMORY VDU 80 3 80 40 VDU BUS BUFFERS VDU 80 4 80 40 VDU OUTPUT Timing Circuits VDU 80 1 gt 80 3 The 80 character display requires a dot rate of 16MHz However to operate correctly in conjunction with the HRG board the 16MHz must be synchronized with the system clock It is derived from the 8MHz available at the 34 way connector This signal is almost sinusoidal and is squared by IC CP 74L221 The two outputs of this monostable drive IC DP 74221 which produces pulses on both rising and falling edges These are combined by EP 74LS02 to give the signal C16M In 80 character mode this signal should be at 16MHz with a 1 1 mark space ratio In 40 character mode alternate pulses should be missing The character rate CRATE is generated by counter GP 74LS169A or 74LS168A or equivalent but not 74LS668 or 74LS669 which counts down from 7 to 0 during each character CRATE indicates that the last dot of a character is being displayed and is used to enable the loading of various registers The main dividers GU 74LS393 FT 74LS390 and FV 74LS393 are similar to the standard 40 character VDU board Their output
79. s drive PROMs FU EU 74LS287 or equivalent which generate blanking and synchronization Signals Separate vertical and horizontal syncs VDRIVE and HDRIVE are available for a wire frame type monitor Note that all the PROMs have 3802 VDU 80 Board 4K7 SIP pull ups on their outputs to allow use of open collector types without needing the piggy back resistor network Hardware Scroll Circuit VDU 80 1 Hardware scroll is performed by adding a number to the output of the row counter modulo 24 This has the effect of scrolling the display by that number of lines The number to be added is in the low 5 bits of CR 74LS377 This is memory mapped at FBFD However the port can only be written to when the screen is closed so it cannot be done directly from the Front Panel The addition is performed by ES 74LS283 and FR CU 74LS287 Address Multiplexers Circuit VDU 80 1 The VDU can be written to transparently That is it is not necessary to wait until line or frame blanking takes place This is achieved by cycling the memories twice per character once to get the character and once for the CPU The CPU and VDU addresses are multiplexed by AR 74LS157 CT 74LS257 and AT 74LS399 CS 74LS399 performs the translation from 32x32 to 24x40 as on the 40 character VDU board The multiplexers CS and AT contain a latch on their outputs clocked twice per character The remaining address lines are latched by DT 74LS175 When in 80 char
80. signals e Modifications IDC Diagnostics Symptom 1 Tests WAIT LINE BWAIT J3 28 1C3 2 should be high IC3 7416 IC35 LS00 Remove IC 3 Press RESET Does the screen change in any way N Check track between IC3 2 and J3 28 IDC DIAGNOSTICS No COS prompt on power up Press RESET Does the screen change in any way Check for correct connections to or shorts on J3 Check HOST INTERFACE IC4 LS245 IC9 ALS574 IC18 ALS574 IC19 IDCEXT IC5 ALS1244 IC10 ALS1244 IC11 ALS1244 Replace IC 3 and remove IC 35 If screen changes when RESET check between IC3 1 amp IC35 11 Otherwise fault must lie before IC35 so check IWAITO amp IWAIT1 from IC35 12 amp 13 to IC14 3 amp IC40 10 30 respectively Refer to cct dia DC1 5 DC2 5 amp DC4 5 rear 79 IDC Diagnostics IDC DIAGNOSTICS Symptom 2 LED not on Tests Run IDCFLASH Does LED Addressing _ Run ADDFLASH flash fault See p 14 Check LED insertion flat nearest connector check change 1C39 LS377 check change IDCINT PAL Check PCB for shorts Check CLOCK CCTRY IC45 LS 04 IC28 LS 393 IC29 LS 11 Check change 7280 IC 46 6 3 Anna SS Ad aaa aes iii dd dd a Str o IDC Diagnostics IDC DIAGNOSTICS Symptom 3 LED flashing indicating FAULT 2 RAM fault Tests Check IK 10
81. such as in a network server it should carry out it tasks autonomously and without failing if interrupted during a data transfer This is achieved by having an on board Z80A microprocessor to handle the sectors coming from or going to the disc in real time and by transmitting the data between the host processor and the IDC under software control 380Z IDC Board THE HARDWARE Circuits 380Z Bus Interface and Decode DC 1 4 Disc Drive Interface DC 4 4 CPU Serial Interface amp Clocks DC 2 4 Memory Wait State and Internal Decode DC 3 4 The circuit consists of several clear cut modules together with a small amount of TTL glue to interface the various modules with each other The main modules are as follows e Bus Buffering to connect the board to the 3802 250 bus e Bus Interface the method of transfer of data and commands to the 380Z This includes two sub modules 1 Data and status registers 2 Wait state generation and time out protection e External Decoding to decode the I O ports used by the 3802 e Clock Generation to generate all clocks for the system including those for the serial interface CPU and disc controller e Serial Interface two channels of RS232 with buffering e Memory on board RAM and EPROM e Internal Decoding to decode the I O ports and memory used by the Z80A on the IDC board e Control Ports to hold static values which control the disc drives e Disc Control which cons
82. t parallel bi directional port user port Processor and Processor Support Circuit 3802 CPU 2 The Z80A processor is clocked at 4MHz from the system clock Interrupt request sequences are not used by the operating system but the 50 way bus allows for external interrupts to be serviced J3 30 Bus Request Acknowledge Req Ack sequences are not used by the operating system but again the 50 way bus allows for future expansion DMA etc Non maskable interrupt NMI routines are used by the operating system to service the single step Front Panel command NMIEN is derived from a bit in system port 0 on the VDU board which then enables counter IC 1 LS90 On the eighth M1 cycle after NMIEN becomes active low an active high output from the counter is inverted to produce active low NMI During this period NMIEN must be disabled within eight M1 cycles or else NMI is activated again and a loop is established The repetition of NMI requests is a very common fault condition associated with garbage on the screen i 380Z CPU Board After a processor reset system port 0 is cleared and NMIEN is active EPROM 0 is mapped to address 0000H 0800H on page 0 where instructions are located within the first two M1 cycles to initialize system port 0 and prevent NMI If these instructions are not executed due to a fault condition the repeated NMI results in a loop in which the screen is not cleared and garbage is displaye
83. ta to the internal Z80 and the other supplies data to the host Z80 bus Both are edge triggered D type flip flops with tristate outputs Given the correct conditions the host Z80 writes to the IDC data port on the low to high transition of the signal HWR this signal is in turn enabled by signal DRD and so data is transferred to the internal ZB0 Similarly when the internal Z80 wants to transfer data to the host Z280 data is latched on the low to high transition of DWR and is read by HRD It is important that communications between processors are kept in order to ensure that both processors do not try to i read or transfer data at the same time ii transfer data before existing data has been read or iii read non existent data This is achieved by setting a status bit whenever data is written to a port This prevents any further writing until the current data has been read by the alternate processor If a further write is attempted or a processor tries to read unwritten data a wait state is generated 2 The wait state generated by attempting to read non present data or to write to a non cleared data port is set and cleared by the positive edge of the relevant cycle As flip flops with an edge triggered SET and an edge triggered CLEAR are unavailable this function has been built using the 74LS74 clock input to set the State and an edge detection mechanism to clear the state The edge detection is done on the write s
84. tly one clock cycle in duration In the absence of interrupt requests and if the HALT output of the processor is active low the processor has executed a halt command the system will be irretrievably locked and can only be restarted by an external interrupt or system reset HALT is available on the 50 way bus for future expansion To produce the signal NOT M1 RD two high speed diodes are used in a diode resistor AND gate to minimize propagation delay The signal is used to select the direction of transfer of data through bi directional tristate buffers ICs 14 and 15 74LS241 Bus Control and Buffering Circuit 3802 CPU 2 Apart from processor control signals the main bus can be divided into two sections e An 8 bit bi directional data bus BD0 BD7 A 16 bit uni directional address bus BAO BA15 The data bus is buffered from the processor by ICs 14 and 15 All 8 bits 1 2 380Z CPU Board are transferred directly to the 50 way bus J3 3 10 and the 37 way bus to the VDU board J2 16 23 With the exception of external bus Request Acknowledge cycles the processor controls the direction of transfer of data in the bus as described under Processor Support above In response to an interrupt request M1 can occur without RD during data transfer to the Z80 so it is necessary to control the bus direction by using the ORed function of M1 and RD All devices which drive the data bus have tristate output stag
85. to BANK5 at the end of the MCONTROL cycle low to high transition IORD When this signal is active PIO is read and signal BUFDIR is active thus pointing data bus direction to the 3802 bus MEMRD Indicates that on board RAM is read by the 380Z and that BUFDIR is active DBMEMEN Enables on board RAM for read write operations This signal is fed through an OR gate and becomes DBEN Interrupt acknowledge is taken care of by ICs AJ SN74LS02N and AH SN7ALS10N BUFDIR will be active when the HIB is in the process of an interrupt acknowledge or when the 380Z is reading either the on board RAM or the PIO The following table shows the mapping of the different ports on the HIB A 380Z Host Interface Board 40H PIO channel A data read write 41H PIO channel B data read write 42H PIO channel A control read write 43H PIO channel B control read write 45H PIO Deblocking RAM control write only F800 to F9FF Deblocking RAM memory space Memory The on board RAM otherwise known as the deblocking RAM is an 8K by 8 pseudostatic RAM D2186 IC BG Deblocking RAM occupies 512 bytes of memory space so it cannot all be read at once the 380Z supplies the four MSB addresses BANK2 to BANK5 thus allowing RAM to be read or written in 1 2K chunks This type of RAM is like the dynamic RAM but produces its own internal refresh cycles If RAM is selected by DBEN going low during an internal refresh cycle
86. to E3H EO CTC channel 0 SIO channel B Rx Tx clock read write E1 CTC channel 1 SIO channel A Tx clock read write E2 CTC channel 2 SIO channel A Rx clock read write E3 CTC channel 3 completion interrupt read write SIO E4H to E7H E4 SIO channel A data read write E5 SIO channel A control read write E6 SIO channel B data read write E7 SIO channel B control read write I F Status E8H to EBH E8 IDC interface status Port 2 read only E8 IDC reset write only E9 IDC reset write only EA IDC reset write only EB IDC reset write only I F Data ECH to EFH EC IDC interface data commands Port 1 read write ED IDC interface data commands Port 1 read write EE IDC interface data commands Port 1 read write EF IDC interface data commands Port 1 read write If the host tries to write to the interface status port both the signals HWR and HSTRD are generated which cause the IDC board to be reset Clock Generation Circuit DC 2 4 The clocks generated on the board fall into three classes e Standard drive clocks of 1MHz 2MHz and 4MHz e A special drive clock of 4MHz Times 16 baud rate clocks with programmable frequencies A basic 8MHz crystal oscillator XTAL IC 45 is used to generate the initial timing This signal is then buffered and passed to a divide by 2 then 4 then 8 counter half of a 74LS393 IC 28 to generate the standard 4MHz 2MHz and 1MHz clocks respective
87. tween row and column addresses at outputs MAO to MA7 CAS becomes active after a delay IC 16 plus a 1000pF capacitor allowing time for addresses to settle and for RAM to process the row address RAS is generated by producing a coarse address decoded output of PROM M IC 13 using BA14 to 16 and one page bit to map one bank of RAM to address space within a 64K page This output selects the bank of RAM for a given 16 bit address and is NANDed with BMRQ to produce RAS active from the falling edge of MRQ CAS is applied common to both banks of RAM RAS is active during read write cycles only to the bank being accessed The precise address within a bank of RAM is selected by the multiplexed addresses Hay to MA7 LINKS L10 L12 adjust address multiplexing to provide outputs suitable for driving 4K x 1 RAM 4027 etc Data input to the RAM is taken directly from the data bus MEMWR is active to instruct RAM to accept data during the memory cycle only during a RAM write operation IC 17 Data output from the RAM is buffered by IC 2 and passed onto the data bus only when RAMRD is active RAMRD is generated by producing a coarse address mapped output from PROM M IC 13 which is ANDed with MREQ and BRD to produce RAMRD only during read operations from RAM RAMRD timing should follow BMRQ timing exactly during RAM read operations RAS only refresh is maintained on all banks of RAM in the following way e CAS is inhibited by applying a high
88. ut and clocking them through using the 4MHz clock WRACK is delayed by a factor of two thus becoming WRACKDEL whilst RDACK and SELACK are delayed by a factor of three and so becoming RDACKDEL and SELDEL IC CC is continuously reset through IC CF SN74LS02N by signal REQ or WRACKDEL or RDACKDEL but also allowing for a reset from the 250 bus The SASI bus transceiver is enabled by signal SDBUFEN in both directions SELACK or WRACK enable IC CB when IN signal is low pointing to SASI and 8 3 Du 380Z Host Interface Board RDACK or RDACKDEL enable IC CB when IN is high PIO reading from SASI WRACKDEK and RDACKDEL are supplying the acknowledge signal to SASI Termination is done at both sides of the transceiver open collector outputs by using a 4K7 resistor network RB at the PIO side pulling the bus to 5V and by a pull up resistor network RC 150 Ohm resistors at SASI side and connecting to a 2 9V terminating voltage Terminating voltage is derived using a three diode chain connected to ground by R2 0 7V drop across each diode Particular attention is taken for grounding SASI control signals a 0 56 Ohm resistor is connected between SASI ground and HIB ground for ground noise elimination maana naan E MEMwe az KERA er f Ran 32 en E ga E t 9 up 6 FASI P pe E T I m NB EI maa E gua 4 2 Zi se 3 KASTI EAIS N 10 pant S gt 4 3f EB 4 Car
89. y ft ja m HEMRD i ED de RANED 6415 F n SH Ge 17 d fa th dod y RAMO 13 3412 2987 b tan 23 3 5 We Ga EA10 PN G Sn 4 Et 1 VDU SEL T Uf poet E q bi P a ROM RD 5 i eo GAIL f x i ps D KR GAI lt srnce be PU BATO 288 SP p Rort3 ENAG DN j D D Romi ENAL e bi P Romiinnk BAS N do NE KM MEMORY HAC PROM BAY Gop cis BAX Bato BAI BALI BAL 32K any 1 C100 32 ADD ON RA He u BAT 100 OLE Waf n1 MONET Bag Coo iba Hio RED YELLOW BA PO Sce ER MIIA M KAL 1 WIRE LINK TO 454 ON ADD ON RAM l i EE MIO ALI HILALIS bod ee N E BAI C kk vest ADO on AH wo USED o D Mb DEAM viib n E XM MEO cue 3801 BACH Row may BE LK or Ib 2 276 PS waite CP RAM Fox Zon GALOS cowl MVAT 66 MK 4716 2r 270g Pb oLanGd arso ADD ON RAM Enea MONITOR Choo 27276 PA 276 e2v270y 3 Onna DRAWING BRE SH AD Ao PI pp n pe er cr s 4 WI 196 INS jy pO hz INI wi f i 3 v qi D D a 3 h lt JO g Ena ELE 1 lag Busan ja J nu purreas Potty PATS Bs Protura rog RD d wR e 3 7 5 k ir ja sis ng Er z q ee Os 33 16 BAIS t nu A un 8 ES ED es x NEEESE ais r h p p Y AO BAI na T ge SKS Ge

RM 380Z Service Manual

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