32” TFT SERVICE MANUAL (17MB08P)
Contents
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3. 30 GNDitc SUPPLYD X Ground LLC Circuitry 31 Y7 OUT GNDy Picture Bus Luma MSB 32 Y6 OUT GNDy Picture Bus Luma 33 Y5 OUT GNDy Picture Bus Luma 34 Y4 OUT GNDy Picture Bus Luma 35 GNDy SUPPLYD X Ground Luma Output Circuitry 36 Vsupy SUPPLYD X Supply Voltage Luma Output Circuitry 37 Y3 OUT GNDy Picture Bus Luma 38 Y2 OUT GNDy Picture Bus Luma 39 Y1 OUT GNDy Picture Bus Luma 40 YO OUT GNDy Picture Bus Luma LSB 41 7 OUT GNDc Picture Bus Chroma MSB 42 C6 OUT GNDc Picture Bus Chroma 43 C5 OUT GNDc Picture Bus Chroma 44 C4 OUT GNDc Picture Bus Chroma 45 Vsupc SUPPLYD X Supply Voltage Chroma Output Circuitry 46 GNDc SUPPLYD X Ground Chroma Output Circuitry 47 OUT GNDc Picture Bus Chroma 48 C2 OUT GNDc Picture Bus Chroma 49 C1 OUT GNDc Picture Bus Chroma 50 CO OUT GNDc Picture Bus Chroma LSB 51 GNDsy SUPPLYD X Ground Sync Pad Circuitry 52 VsuPsv SUPPLYD X Supply Voltage Sync Pad Circuitry 53 INTLC OUT LV Interlace Output 54 AVO OUT LV Active Video Output 55 FSY HC HSYA OUT LV Front Sync Horizontal Clamp Pulse Front End Horizontal Sync Output 56 MSY HS IN OUT LV Main Sync Horizontal Sync Pulse 57 VS OUT LV Vertical Sync Pulse 58 FPDAT VSYA IN OUT LV Front End Back End Data Front End Vertical Sync Output 59 SUPPLYA X Standby Supply Voltage 60 CLK5 OUT LV CCU 5 MHz Clock Out
4. 4 126 BIBTERS tee te rfe e ht een eee 4 12 IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM 5 12 15 eter rooms E 5 12 1 1 General Description 5 12 1 2 5 12 1 3 ER DM ings 5 12 1 4 Connection DIagramis e eere rep Gr e 5 JP AMMIH yc EE 6 12 2 1 General Desctiption e re rediere De eb t eti dd eta tees 6 12 2 2 Featul s toti 6 12 2 3 Pin description oorr n meret ete e rt tede ie beg 6 12 9 AEMS TCI ini itt o emere erii 7 12 3 1 Ee em UM abt te Dei e idi 7 12 3 2 oS ete SA o e 7 124 5124021 iode ee et a aue dete dd e ee 8 12 4 1 Descriptloh RE RR a d A 8 12 4 2 ed p e Re ed Wee 8 12 4 3 PIN CONNCCUONS 8 125 4 een EET 9 12 5 1 General description UR 9 12 5 2 Features ood e t e ee v p
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6. Pin No Pin Name Type Connection Short Description PQFP if not used 80 pin 1 B1 CB1IN IN VREF Blue1 Cb1 Analog Component Input 2 G1 Y1IN IN VREF Green1 Y1 Analog Component Input 3 R1 CR1IN IN VREF Read1 Cr1 Analog Component Input 4 2 2 Blue2 Cb2 Analog Component Input 5 G2 Y2IN IN VREF Green2 Y2 Analog Component Input 6 R2 CR2IN IN VREF Read2 Cr2 Analog Component Input 7 ASGF X Analog Shield GND 8 FFRSTWIN IN LV or GNDp FIFO Reset Write Input 9 VsuPcAP OUT X Digital Decoupling Circuitry Supply Voltage 10 Vsupp SUPPLYD X Supply Voltage Digital Circuitry 11 SUPPLYD X Ground Digital Circuitry 12 GNDcap OUT X Digital Decoupling Circuitry GND 13 SCL IN OUT X Bus Clock 14 SDA IN OUT X Bus Data 15 RESQ IN X Reset Input Active Low 16 TEST IN GNDp Test Pin connect to GNDp 17 VGAV IN GNDp VGAV Input 18 YCOEQ IN GNDp Y C Output Enable Input Active Low 19 FFIE OUT LV FIFO Input Enable 20 FFWE OUT LV FIFO Write Enable 21 FFRSTW OUT LV FIFO Reset Write Read 22 FFRE OUT LV FIFO Read Enable 23 FFOE OUT LV FIFO Output Enable 24 CLK20 IN OUT LV Main Clock output 20 25 MHz 25 GNDPA OUT Pad Decoupling Circuitry GND 26 VsuPPA OUT X Pad Decoupling Circuitry Supply Voltage 27 LLC2 OUT LV Double Clock Output 28 LLC1 IN OUT LV Clock Output 29 VsuPLLC SUPPLYD X Supply Voltage LLC Circuitry 32 TFT TV Service Manual 11 06 03 2006
7. 25MHz Bandwidth Crosstalk 55dB Short circuit to ground or Vcc protected Anti saturation gain changing Video switching 12 5 3 Pin Connections Rs INPUT 16 RouTPUT FB INPUT INPUT G INPUT G OUTPUT G INPUT 5 124 F8 INPUT B INPUT 119 BouTPUT B INPUT 7 109 FB8g INPUT FB INPUT FB OUTPUT 32 TFT TV Service Manual 06 03 2006 12 6 6415 12 6 1 General description The main function of the IC is to switch 8 video input sources on 6 outputs Each output can be switched on only one of each input On each input an alignment of the lowest level of the signal is made bottom of synch top for CVBS or black level for RGB signals Each nominal gain between any input and output is 6 5dB For D2MAC or Chroma signal the alignment is switched off by forcing with an external resistor bridge 5 Vpc on the input Each input can be used as a normal input or as a MAC or Chroma input with external resistor bridge All the switching possibilities are changed through the BUS Driving 750 load needs an external transistor It is possible to have the same input connected to several outputs The starting configuration upon power on power supply 0 to 10V is undetermined In this case 6 words of 16 bits are necessary to determine one configuration In other case 1 word of 16 bits is necessary to determine one configuration 12 6 2 Features 20MHz Bandwidth Cascad
8. Adjusts green level in video Min Value 000 Max Value 255 B Adjusts the blue level in the video Min Value 000 Max Value 255 R Adjusts the red level in the video Min Value 000 Max Value 255 VPC BR Adjusts the brightness level Min Value 000 Max Value 255 30 32 TFT TV Service Manual 06 03 2006 Adjusts the contrast level for RF mode Min Value Max Value VPC CT AV Adjusts the contrast level for AV modes Min Value Max Value VPC SATCB Adjusts the VPC satcb register Min Value Max Value VPC SATCR Adjusts the VPC satcr register Min Value Max Value VPC CIPBR Adjusts the VPC cipbr register Min Value Max Value VPC CIPCT Adjusts the VPC cipct register Min Value Max Value Dimming Adjusts the panel dimming Min Value Max Value 32 TFT TV Service Manual 000 063 000 063 000 063 000 063 000 255 000 063 000 255 31 06 03 2006 13 2 OPTIONS MENU SETTINGS In order to enter Options menu move the cursor to Options parameter by pressing A W buttons in Service Menu and press lt gt button The following menu appears on the screen First APS A P S Headphone Vsr DBE Subwoofer Lineout DolbyPro Equalizer There are 53 items in the OPTIONS menu but 11 of them are seen when you first enter the menu Using buttons remaining items can
9. L OIRT D K 3 Digitally controlled PLL tuning via l C bus 4 Off air channels S cable channels and Hyper band 5 Compact size 6 Complies to CENELEC EN55020 and EN55013 Pinning 1 Gain control voltage AGC 4 0V Max 4 5V 2 Tuning voltage 3 address select 5 5 4 serial clock Min 0 3V 5 5V 5 serial data Min 0 3V 5 5V 6 Not connected 7 PLL supply voltage 5 0V Min 4 75V 5 5V 8 ADC input 9 Tuner supply voltage 33V Min 30V 35V 10 Symmetrical IF output 1 11 Symmetrical IF output 2 3 IF PART TDA9886 The TDA9886 is an alignment free multistandard PAL SECAM and vision and sound IF signal PLL demodulator for positive and negative modulation including sound AM and FM processing The following figure shows the simplified block diagram of the integrated circuit The integrated circuit comprises the following functional blocks VIF amplifier Tuner and VIF AGC VIF AGC detector Frequency Phase Locked Loop FPLL detector VCO and divider Digital acquisition help and AFC Video demodulator and amplifier Sound carrier trap SIF amplifier SIF AGC detector Single reference QSS mixer AM demodulator FM demodulator and acquisition help Audio amplifier and mute time constant I C bus transceivers and MAD module address Internal voltage stabilizer 32 TFT TV Service Manual 06 03
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11. thermal shutdown and safe area compensation making it essentially blow out proof The LM317 serves a wide variety of applications including local on card regulation This device can also be used to make a programmable output regulator or by connecting a fixed resistor between the adjustment and output the LM317 can be used as a precision current regulator 12 3 2 Features Output Current in Excess of 1 5 A Output Adjustable between 1 2 V and 37 V Internal Thermal Overload Protection Internal Short Circuit Current Limiting Constant with Temperature Output Transistor Safe Area Compensation Floating Operation for High Voltage Applications Available in Surface Mount and Standard 3 Lead Transistor Package Eliminates Stocking many Fixed Voltages 32 TFT TV Service Manual 06 03 2006 12 4 ST24LC 1 12 4 1 Description The ST24LC21 is a 1K bit electrically erasable programmable memory organized by 8 bits This device can operate in two modes Transmit Only mode bidirectional mode When powered the device is in Transmit Only mode with EEPROM data clocked out from the rising edge of the signal applied on VCLK The device will switch to the bidirectional mode upon the falling edge of the signal applied SCL pin The ST24LC21 can not switch from the bidirectional mode to the Transmit Only mode except when the power supply is removed The device operates with a power su
12. 2006 VIF LL cr 4 MHz T AR extemal reterence signal ves video output 2 V p p 1 5 V ipp without SINGLE REFERENCE OSS sucio output NTERCARRIER MIXER 315 DEEM AND DEMOOULATOR de emphasis network 6 12 13 14 17 18 26 28 29 32 sound cutput and MAD select I 4 MULTI STANDARD SOUND PROCESSOR The MSP34x0G family of single chip Multistandard Sound Processors covers the sound processing of all analog TV Standards worldwide as well as the NICAM digital sound standards The full TV sound processing starting with analog sound IF signal in down to processed analog AF out is performed on a single chip These TV sound processing ICs include versions for processing the multichannel television sound MTS signal conforming to the standard recommended by the Broadcast Television Systems Committee BTSC The DBX noise reduction or alternatively Micronas Noise Reduction MNR is performed alignment free Other processed standards are the Japanese FM FM multiplex standard EIA J and the FM Stereo Radio standard Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and EIA J The MSP 34x1G has optimum stereo performance without any adjustments 1 Nat connected for TOASBBS 5 VIDEO SWITCH TEA6415 In case of three or more external sources are used the video switch IC TEA6415 is used The main function of this devic
13. Circuit Protection 12 9 3 Pin Connection TOP VIEW oi X OC 68 3 ee 0 FF a 4 4 4 OO 0O0QGQUOOO P amp amp KE 5 7 as 2 41 4 7 LINP 5 VAROUTR LINN VAROUTL AVppREF 7 Sa AGND VREF 22 AVpp VARDIFF 281 COSC VARMAX 10 VOLUME k SI ES 26 AGND REFGND 12 5 BSLN PVCCL 35 5 e LOUTN LOUTP LouTP 14 32 TFT TV Service Manual 06 03 2006 12 10 9885 86 12 10 1 General description The TDA9885 is an alignment free single standard without positive modulation vision and sound IF signal PLL The TDA9886 is an alignment free multistandard PAL SECAM and NTSC vision and sound IF signal PLL demodulator for positive and negative modulation including sound AM and FM processing Both devices can be used for TV VTR PC and set top box applications 12 10 2 Features 5 V supply voltage Gain controlled wide band Vision Intermediate Frequency VIF amplifier AC coupled Multistandard true synchronous demodulation with active carrier regeneration very linear demodulation good intermodulation figures reduced harmonics excellent pulse response Gated phase detector for L L accent standard Fully integrated VIF Voltage Controlled Oscillator VCO alignment free frequencies switchable
14. OUT LV Loudspeaker out right 58 27 23 26 19 VREF2 OBL Reference ground 2 59 26 22 25 18 DACA L OUT LV Headphone out left 60 25 21 24 17 DACA_R OUT LV Headphone out right 23 NC LV Not connected 22 NC LV Not connected 61 24 20 21 16 RESETQ IN OBL Power on reset 62 23 20 15 NC LV Not connected 63 22 19 14 NC LV Not connected 64 21 19 18 13 NC LV Not connected 65 20 18 17 12 128 DA IN2 IN LV l S2 data input 66 19 17 16 11 DVSS OBL Digital ground 15 DVSS OBL Digital ground 14 DVSS OBL Digital ground 67 18 16 13 10 DVSUP OBL Digital power supply 5V 12 DVSUP OBL Digital power supply 5V 11 DVSUP OBL Digital power supply 5V 68 17 15 10 9 ADR CL OUT LV ADR clock 32 TV Service Manual 27 06 03 2006 12 18 DS90C385 12 18 1 General Description The DS90C385 transmitter converts 28 bits of LVCMOS LVTTL data into four LVDS Low Voltage Differential Signaling data streams A phase locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link Every cycle of the transmit clock 28 bits of input data are sampled and transmitted At a transmit clock frequency of 85 MHz 24 bits of RGB data and 3 bits of LCD timing and control data FPLINE FPFRAME DRDY are transmitted at a rate of 595 Mbps per LVDS data channel Using 85 MHz clock the data throughput is 297 5 Mbytes sec Also available is the DS90C365 that conv
15. TDA9886 LM2576 TDA1308T LM317T PI5V330 ST24LC21 GM6015 5114 AD9883A TEA6415 MC 141585 VPC3230D MC34063 SDAS55XX MSP3410G TPA3002D2 DS90C385 NDS8947 12 1 LM1117 12 1 1 General Description The LM1117 is a series of low dropout voltage regulators with a dropout of 1 2V at 800mA of load current It has the same pin out as National Semiconductor s industry standard LM317 The LM1117 is available in an adjustable version which can set the output voltage from 1 25V to 13 8V with only two external resistors In addition it is also available in five fixed voltages 1 8V 2 5V 2 85V 3 3V and 5V The LM1117 offers current limiting and thermal shutdown Its circuit includes a zener trimmed bandgap reference to as sure output voltage accuracy to within 196 The LM1117 series is available in SOT 223 TO 220 and TO 252 D PAK packages A minimum of 10pF tantalum capacitor is required at the output to improve the transient response and stability 12 1 2 Features Available in 1 8V 2 5V 2 85V 3 3V 5V and Adjustable Versions Space Saving SOT 223 Package Current Limiting and Thermal Protection Output Current 800mA Line Regulation 0 296 Max Load Regulation 0 496 Max Temperature Range LM1117 0 C to 125 C LM11171 40 C to 125 C 12 1 3 Applications 2 85V Model for SCSI 2 Active Termination Post Regulator for Switching DC DC Converter High Efficiency Linear Regulators Battery Charger Batt
16. differential input 2 OP1 3 output 1 open collector FMPLL 4 FM PLL for loop filter DEEM 5 de emphasis output for capacitor AFD 6 AF decoupling input for capacitor DGND 7 digital ground AUD 8 audio output TOP 9 tuner AGC TakeOver Point TOP SDA 10 l C bus data input output SCL 11 l C bus clock input SIOMA 12 sound intercarrier output and MAD select 13 not connected TAGC 14 tuner AGC output REF 15 4 MHz crystal or reference input VAGC 16 VIF AGC for capacitor Not connected for TDA9885 CVBS 17 video output AGND 18 analog ground VPLL 19 VIF PLL for loop filter Vp 20 supply voltage 5 V AFC 21 AFC output OP2 22 output 2 open collector SIF1 23 SIF differential input 1 SIF2 24 SIF differential input 2 15 32 TFT TV Service Manual 06 03 2006 12 11 1308 12 11 1 General Description The TDA1308 is an integrated class AB stereo headphone driver contained an 508 or a DIP8 plastic package The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital audio applications 12 11 2 Features Wide temperature range No switch ON OFF clicks Excellent power supply ripple rejection Low power consumption Short circuit resistant High performance high signal to noise ratio High slew rate Low distortion Large output voltage swing 12 11 3 Pinning SYMBOL PIN DESCRIPTION PIN VALUE OU
17. displaying 10X18 font matrix this ratio should not greater than 1280 RESET Pin 6 An active low signal will reset ROW15 and ROW16 control registers Refer to Control Registers section for default set tings A proper RC network have to be tighten to this pin to ensure the device initialize properly during power up Refer to the application diagram SDA Pin 7 Data and control message are being transmitted to this chip from a host MCU via M bus systems This wire is configurated as a uni directional data line Detailed description of protocols will be discussed in the M BUS section SCL Pin 8 A separate synchronizing clock input from the transmitter is required for M Bus protocol Data is read at the rising edge of each clock signal Pin 9 This is the power pin for the digital logic of the chip VSYNC Pin 10 Similar to Pin 5 this pin inputs a vertical synchronize signal to synchronize the vertical control circuit It is negative polarity by default 1 Pin 11 This is the voltage supply of RGB outputs when low intensity of Windows ROW is selected The RBG output level would be equal to VDD l in this case Please refer to Row Attribute Window registers for more detail The input voltage for this pin should be equal to or less than V DD Pin 17 for normal operation FBKG Pin 12 This pin will output a logic high while displaying characters or windows It is defaulted to high impedance state after power on
18. logic It is produced by the internal clock generator and is synchronous with the internal pixel sampling clock When the sampling time is changed by adjusting the PHASE register the output timing is shifted as well The Data DATACK and HSOUT outputs are all moved so the timing relationship among the signals is maintained INPUTS RAIN GAIN BAIN Analog Input for RED Channel Analog Input for GREEN Channel Analog Input for BLUE Channel High impedance inputs that accept the RED GREEN and BLUE channel graphics signals respectively The three channels are identical and can be used for any colors but colors are assigned for convenient reference They accommodate input signals ranging from 0 5 V to 1 0 V full scale Signals should be ac coupled to these pins to support clamp operation HSYNC Horizontal Sync Input This input receives a logic signal that establishes the horizontal timing reference and provides the frequency reference for pixel clock generation The logic sense of this pin is controlled by serial register OEh Bit 6 Hsync Polarity Only the leading edge of Hsync is active the trailing edge is ignored When Hsync Polarity 0 the falling edge of Hsync is used When Hsync Polarity 1 the rising edge is active The input includes a Schmitt trigger for noise immunity with a nominal input threshold of 1 5 V VSYNC Vertical Sync Input This is the input for vertical sync SOGIN Sync on Green Inpu
19. members of the DIGIT3000 IC family such as DDP 331x and or it can be used with 3rd party products The main features of the VPC 323xD are high performance adaptive 4H comb filter Y C separator with adjustable vertical peaking multi standard colour decoder PAL NTSC SECAM including all substandards four CVBS one S VHS input one CVBS output two RGB YCr Cb component inputs one Fast Blank FB input integrated high quality A D converters and associated clamp and AGC circuits multi standard sync processing linear horizontal scaling 0 25 4 as well as non linear horizontal scaling Panorama vision PAL preprocessing line locked clock data and sync or 656 output interface peaking contrast brightness color saturation and tint for RGB YC r C b and CVBS S VHS high quality soft mixer controlled by Fast Blank PIP processing for four picture sizes 1 4 1 9 1 16 or 1 36 of normal size with 8 bit resolution 15 predefined PIP display configurations and expert mode fully programmable control interface for external field memory l C bus interface one 20 25 MHz crystal few external components 80 pin PQFP package 12 7 2 Pin Connections and Short Descriptions NC lt not connected LV if not used leave vacant X obligatory connect as described in circuit diagram SUPPLYA 4 75 5 25 V SUPPLYD 3 15 3 45 V
20. or when there is no output An external 10 O resistor pulled low is recommended to avoid level toggling caused by hand effect when there is no output B G R Pin 13 14 15 LMOSD2 16 color outputs in CMOS level to the host monitor These three signals are open drain outputs if 3 STATE bit is set and the color intensity is inactive Otherwise they are active high push pull outputs See REGISTERS for more information These pins are in high impedance state after power on Vss Pin 24 This is the ground pin for the digital logic of the chip 23 32 TFT TV Service Manual 06 03 2006 12 16 MC34063 12 16 1 Description The MC34063A Series is a monolithic control circuit containing the primary functions required for DC to DC converters These devices consist of an internal temperature compensated reference comparator controlled duty cycle oscillator with an active current limit circuit driver and high current output switch This series was specifically designed to be incorporated in Step Down and Step Up and Voltage Inverting applications with a minimum number of external components 12 16 2 Features Operation from 3 0 V to 40 V Input Low Standby Current Current Limiting Output Switch Current to 1 5 A Output Voltage Adjustable Frequency Operation to 100 kHz Precision 2 Reference 12 16 3 Pin connections Switch 2 Driver Collector Collector Switch mi sense Emilter Timing Vec C Capa
21. 1 2 CL IN OUT OBL clock 10 8 1 64 NC LV Not connected 11 7 6 80 63 STANDBYQ IN OBL Stand by low active 12 6 5 79 62 ADR SEL IN OBL bus address select 13 5 4 78 61 D 0 IN OUT LV D CTR 0 14 4 3 77 60 D 1 IN OUT LV D 1 15 3 76 59 NC LV Not connected 16 2 75 58 NC LV Not connected 17 NC LV Not connected Audio clock output 18 1 2 74 57 AUD CL OUT OUT LV 18 432 MHz 19 64 1 73 56 TP LV Test pin 20 63 52 72 55 XTAL OUT OUT OBL Crystal oscillator 21 62 51 71 54 XTAL IN IN OBL Crystal oscillator 22 61 50 70 53 TESTEN IN OBL Test pin AVSS via IF Input 2 can be left 23 60 49 69 52 ANA IN2 IN vacant only if IF input 1 is 56 pF LV 4 also not use IF common can be left 24 59 48 68 51 ANA IN IN AVSS via vacant only if IF input 1 is 56 pF LV also not use 25 58 47 67 50 ANA 1 1 IN LV IF input 1 26 57 46 66 49 AVSUP OBL Analog power supply 5V 65 AVSUP OBL Analog power supply 5V 64 NC LV Not connected 63 NC LV Not connected 27 56 45 62 48 AVSS OBL Analog ground 61 AVSS OBL Analog ground 28 55 44 60 47 IN LV Mono input 59 NC LV Not connected 29 54 43 58 46 VREFTOP OBL Reference voltage AD 30 53 42 57 45 SC1 IN R IN LV SCART 1 input right 31 52 41 56 44 SC1 IN L IN LV SCART 1 input left 32
22. 15 DAT308 et et e ge det bet ater 16 12 11 1 General Description ood ced re T HU i ERE Rete Doi DO esee 16 1211 2 Features oorrexi tereti 16 12 11 3 PINNING cnet ce eatin eee ine eril 16 12 12 30 tfo ede Fe setae 17 12 12 1 General description 17 12 12 2 17 12 12 3 Pim Descriptions neo Rime rtr E P 17 12 132 9MO015 7 stash putetis aaa 18 12 13 1 General description 18 18 12 14 AD9883A c n ptu Pte Ettore me dtes Ln 19 12 14 1 General description 19 12 4 2 at 19 12 14 32 Descriptions ooo sect t RET 19 12 15 MC 141585 cun idonei deme pipe casa mscr uide fie ros 22 12 15 1 General description ree eie cel avd eei ee EE gon 22 12 15 2 Featur s oid ee et A E EHE eq 22 12 15 3 Pin Description eccere decree endi etta die gd de dt edi e dd cres 22 1246 063 CIE 24 12 16 11 Description oeeie nn eed ed adele 24 12 16 2 ean ER E
23. 32 SERVICE MANUAL 17MBO8P RELEASE DATE 04 03 2005 PREPARED BY VESTEL ELECTRONICS THIS PAGE IS INTENTIONALLY LEFT BLANK TABLE OF CONTENTS 1 INTRODUCTION 2 25 22 icta 1 2 TUNER Lernen rmn LE s ica 1 3 IE BARTCTDA9888 nd tete t etia 1 4 MULTI STANDARD SOUND 5 2 5 VIDEO SWITCH TEA6415 un meten eedem 2 6 AUDIO AMPLIFIER STAGE WITH 0202 2 T POWER A 2 8 MICROCONTROELEER SDADBD5XX ale dat need ee ise 3 8 1 General EeatUres 5 em reto em t bem edt tt as 3 8 2 External Crystal and Programmable Clock Speed sse 3 8 3 Microcontroller EGatures ao eter ta e eder ae P o c Ee a RR 3 8 4 eei rco del eee tt oen 3 8 5 DSS 3 8 6 ROM Characters 7 deti oa eR eer te e ng tu eet 3 8 7 Acquisition Features s oir ere nte eme eut e rte esti dod 4 8 8 POTS I eee 4 9 SERIAL ACCESS CMOS 16K 2048 8 EEPROM 5 24 16 4 10 CLASS AB STEREO HEADPHONE DRIVER 1308
24. 51 55 43 ASG1 AHVSS Analog Shield Ground 1 33 50 40 54 42 SC2_IN_R IN LV SCART 2 input right 34 49 39 53 41 SC2_IN_L IN LV SCART 2 input left 35 48 52 40 ASG2 AHVSS Analog Shield Ground 2 36 47 38 51 39 SC3 IN R IN LV SCART 3 input right 26 32 TV Service Manual 06 03 2006 37 46 37 50 38 SC3 IN L IN LV SCART 3 input left 38 45 49 37 ASG4 AHVSS Analog Shield Ground 4 39 44 48 36 5 4 IN LV SCART 4 input right 40 43 47 35 SCA IN L IN LV SCART 4 input left 41 46 NC LV or AHVSS Not connected 42 42 36 45 34 AGNDC OBL Analog reference voltage 43 41 35 44 33 AHVSS OBL Analog ground 43 AHVSS OBL Analog ground 42 NC LV Not connected 41 NC LV Not connected 44 40 34 40 32 CAPL M OBL Volume capacitor MAIN 45 39 33 39 31 AHVSUP OBL Analog power supply 8V 46 38 32 38 30 CAPL A OBL Volume capacitor AUX 47 37 31 37 29 SC1 OUT L OUT LV SCART output 1 left 48 36 30 36 28 SC1 OUT R OUT LV SCART output 1 right 49 35 29 35 27 VREF1 OBL Reference ground 1 50 34 28 34 26 SC2 OUT L OUT LV SCART output 2 left 51 33 27 33 25 SC2 OUT R OUT LV SCART output 2 right 52 32 NC LV Not connected 53 32 31 24 NC LV Not connected 54 31 26 30 23 DACM SUB OUT LV Subwoofer output 55 30 29 22 NC LV Not connected 56 29 25 28 21 DACM L OUT LV Loudspeaker out left 57 28 24 27 20 DACM R
25. 5V e High density cell design for extremely low Rps on High power and current handling capability in a widely used surface mount package Dual MOSFET in surface mount package 29 32 TFT TV Service Manual 06 03 2006 13 SERVICE MENU SETTINGS All system geometry and white balance alignments are performed in production service mode Before starting the production mode alignments make sure that all manual adjustments are done correctly To start production mode alignments enter the main menu by pressing M button and then press the digits 4 7 2 and 5 respectively The following menu appears on the screen Service Aps WssTest TFT26 Version Time Date After entering the Service menu you can access its items by pressing A V buttons In order to enter selected menu use lt gt buttons To exit the service menu press M button Entire service menu parameters of TFT TV are listed below 13 1 ADJUST MENU SETTINGS In order to enter Adjust menu move the cursor to Adjust parameter by pressing A V buttons Service Menu and press lt gt button The following menu appears on the screen P 08 CNN 5 04 BG 463 There are 12 items in the OPTIONS menu but 11 of them are seen when you first enter the menu Using buttons remaining items can be seen By Pass VLUT On Off Enables disables VLUT bypass R Adjusts the red level in the video Min Value 000 Max Value 299
26. CLK of 80MHz Maximum input resolution of 1580 dots line PIXin HSYNC ratio Wide Operating Frequency max 150KHz for Monitor Fully Programmable Character Array of 15 Rows by 30 Columns 8 Color Selection for Characters with Color Intensity Attribute on Each Row 7 Color Selection for Characters background True 16 Color Selection for Windows Shadowing on Windows with Programmable Shadow Width Height Color Fancy Fade In Fade Out Effects Programmable Height of Character to Meet Multi Sync Requirement Row To Row Spacing Control to Avoid Expansion Distortion Four Programmable Windows with Overlapping Capability Character Bordering or Shadowing Character Symbol Blinking Function Programmable Vertical and Horizontal Positioning for Display Center M BUS Interface with Address 7A 12 15 3 Pin Description Pin Assignment Vss Pin 1 This is the ground pin for the chip PIXin Pin 2 This is the Pixel clock input for chip The MC141585 chip is driven by this pixel clock for all the logics inside 22 32 TFT TV Service Manual 06 03 2006 NC Pin 3 No connection Vpp Pin 4 This is the 5 power pin for the chip HSYNC Pin 5 This pin inputs a horizontal synchronize signal It is negative polarity by default The leading edge of HSYNC synchronizes its internal horizontal timing The maximum input ratio between PIXin HSYNC should not greater than 1580 for displaying 12X18 font matrix For
27. It uses a 1366 768 panel with 16 9 aspect ratio The TV is capable of operation in PAL SECAM NTSC playback colour standards and multiple transmission standards as B G D K and L L including German and NICAM stereo Sound system output is supplying 2x8W 10 THD for stereo 80 speakers The chassis is equipped with many inputs and outputs allowing it to be used as a center of a media system It supports following peripherals 2 SCART s with all of them supporting full SCART features including RGB input input CVBS Stereo Audio 1 SVHS iput 1 Stereo Headphone output 1 D Sub 15 PC input 1 DVI input Optional 1 Audio line out 1 Stereo audio input for PC DVI 2 TUNER As the thickness of the TV set has a limit a horizontal mounted tuner is used in the product which is suitable for CCIR systems B G and D K The tuning is available through the digitally controlled bus PLL Below you will find info on the Tuner in use General description of UV1316 The UV1316 tuner belongs to the UV 1300 family of tuners which are designed to meet a wide range of applications It is combined VHF UHF tuner suitable for CCIR systems B G L and The low IF output impedance has been designed for direct drive of a wide variety of SAW filters with sufficient suppression of triple transient Features of UV1316 1 Member of the UV1300 family small sized UHF VHF tuners 2 Systems CCIR
28. LER SDA55XX 8 1 General Features Feature selection via special function register Simultaneous reception of TTX VPS PDC and WSS line 23 Supply Voltage 2 5 and 3 3 V ROM version is used 8 2 External Crystal and Programmable Clock Speed Single external 6MHz crystal all necessary clocks are generated internally CPU clock speed selectable via special function registers Normal Mode 33 33 MHz CPU clock Power Save mode 8 33 MHz 8 3 Microcontroller Features bit 8051 instruction set compatible CPU 33 33 MHz internal clock max 0 360 hs min instruction cycle Two 16 bit timers Watchdog timer Capture compare timer for infrared remote control decoding Pulse width modulation unit 2 channels 14 bit 6 channels 8 bit ADC 4 channels 8 bit UART rxd txd 8 4 Memory Up to 128 Kilobyte on Chip Program ROM Eight 16 bit data pointer registers DPTR 256 bytes on chip Processor Internal RAM IRAM 128bytes extended stack memory Display RAM and TXT VPS PDC WSS Acquisition Buffer directly accessible via MOVX UP to 16KByte on Chip Extended RAM XRAM consisting of 1 Kilobyte on chip ACQ buffer RAM access via MOVX 1 Kilobyte on chip extended RAM XRAM access via MOVX for user software 3 Kilobyte Display Memory 8 5 Display Features ROM Character set supports all East and West European Languages in single device Mosaic Graphic Character Set Parallel Displ
29. TA 1 Output A Voltage swing Min 0 75V Max 4 25V INA neg 2 Inverting input A Vo clip Min 1400mVrms INA pos 3 Non inverting input A 2 5 Vss 4 Negative supply OV INB pos 5 Non inverting input B 2 5V INB neg 6 Inverting input B Vo clip Min 1400mVrms OUTB 7 Output B Voltage swing Min 0 75V Max 4 25V 8 Positive supply 5V Min 3 0V 7 0V 32 TFT TV Service Manual 16 06 03 2006 12 12 PI5V330 12 12 1 General description Pericom Semiconductors PI5V series of mixed signal video circuits are produced in the Company s advanced CMOS low power technology achieving industry leading performance The PI5V330 is a true bidirectional Quad 2 channel multiplexer demultiplexer that is recommended for both RGB and composite video switching applications The VideoSwitch can be driven from a current output RAMDAC or voltage output composite video source Low ON resistance and wide bandwidth make it ideal for video and other applications Also this device has exceptionally high current capability which is far greater than most analog switches offered today A single 5V supply is all that is required for operation The PI5V330 offers a high performance low cost solution to switch between video sources The application section describes the PI5V330 replacing the HC4053 multiplier and buffer amplifier 12 12 2 Features High performance low cost solution to switch between video sources Wide bandw
30. able with another TEA6415C Internal address can be changed by pin 7 voltage 8 Inputs CVBS RGB MAC CHROMA 6 Outputs Possibility of MAC or chroma signal for each input by switching off the clamp with an external resistor bridge Bus controlled 6 5dB gain between any input and output 55dB crosstalk at 5mHz Fully ESD protected 12 6 3 Pinning 1 Input Max 2Vpp Input Current 1mA 3mA Data 2 Low level 0 3V 1 5V High level 3 0V Max Vcc 0 5V 3 Input Max 2Vpp Input Current 1mA mA 4 Clock 2 Low level 0 3 1 5V High level 3 0V Max Vcc 0 5V 5 Input Max 2Vpp Input Current 1mA 3mA 6 Input Max 2Vpp Input Current 1mA Max 3mA 7 Prog 8 Input Max 2Vpp Input Current 1mA 3mA 9 Vcc 12V 10 Input Max 2Vpp Input Current 1mA 3mA 11 Input Max 2Vpp Input Current 1mA Max 3mA 12 Ground 13 Output 5 5Vpp Min 4 5Vpp 14 Output 5 5Vpp Min 4 5Vpp 15 Output 5 5Vpp Min 4 5Vpp 16 Output 5 5Vpp Min 4 5Vpp 17 Output 5 5Vpp Min 4 5Vpp 18 Output 5 5Vpp Min 4 5Vpp 19 Ground 20 Input Max 2Vpp Input Current 1mA mA 10 32 TFT TV Service Manual 06 03 2006 12 7 VPC3230D 12 7 1 General Description The VPC 323xD is a high quality single chip video front end which is targeted for 4 3 and 16 9 50 60 Hz and 100 120 Hz TV sets It can be combined with other
31. ables disables sound Carrier feature Carrier RC_Options AV 1 AV 2 S VIDEO RC_Options Adjusts the Remote Control type The values are 1 RCMM standard remote control 2 Metz RC 3 Toshiba RC 4 Credit card 2025 Values greater than 4 are invalid and standard RC will be chosen automatically AV 1 On Off Enables disables AV 1 AV 2 On Off Enables disables AV 2 S VIDEO On Off Enables disables S VIDEO AV 3 On Off Enables disables AV 3 35 32 TFT TV Service Manual 06 03 2006 On Off Enables disables PC MENU On Off Enables disables semi transparent MENU MIX Enables disables teletext MIX mode Enable 001 Disable 000 HOTEL MODE On Off Enables disables Hotel mode feature OTHER Adjusts the standard value for APS for Eastern European countries The values are 0 BG standard 1 DK standard LDLY Adjusts the Luna chroma DeLaY value Min Value 000 Max Value 007 AGC Adjusts the Automatic Gain Control value Min Value 000 Max Value 031 AV 3 PC MENU MIX HOTEL MODE X OTHER X LDLY 1 050 0012 00018 4m PIP On Off Enables disables PIP PAP On Off Enables disables PAP Full PC On Off Enables disables Full PC PC AUDIO On Off Enables disables PC AUDIO OSDCLK DLY Adjusts the Osd clock 36 32 TFT TV Service Manual 06 03 2006 Min Value 000 Max Value 003 OSDCLK PINDLY Adjusts the Osd c
32. al sync can always be determined VSOUT Vertical Sync Output A reconstructed and phase aligned version of the video Vsync The polarity of this output can be controlled via a serial bus bit The placement and duration in all modes is set by the graphics transmitter SOGOUT Sync On Green Slicer Output This pin outputs either the signal from the Sync on Green slicer comparator or an unprocessed but delayed version of the Hsync input Note Besides slicing off SOG the output from this pin gets no other additional processing on the AD9883A Vsync separation is performed via the sync separator SERIAL PORT 2 Wire SDA Serial Port Data SCL Serial Port Data Clock Serial Port Address Input 1 For a full description of the 2 wire serial register and how it works refer to the 2 Wire Serial Control Port section 19 32 TFT TV Service Manual 06 03 2006 DATA OUTPUTS RED GREEN BLUE DATA CLOCK OUTPUTS DATACK Data Output RED Channel Data Output GREEN Channel Data Output BLUE Channel The main data outputs Bit 7 is the MSB The delay from pixel sampling time to output is fixed When the sampling time is changed by adjusting the PHASE register the output timing is shifted as well The DATACK and HSOUT outputs are also moved so the timing relationship among the signals is maintained Data Output Clock This is the main clock output signal used to strobe the output data and HSOUT into external
33. ay Attributes Single Double Width Height of Characters Variable Flash Rate Programmable Screen Size 25 Rows x 33 64 Columns Flexible Character Matrixes HxV 12 x 9 16 Up to 256 Dynamical Redefinable Characters in standard mode 1024 Dynamical Redefinable Characters in Enhanced Mode CLUT with up to 4096 colour combinations Up to 16 Colours per DRCS Character One out of 8 Colours for Foreground and Background Colours for 1 bit DRCS and ROM Characters 8 6 ROM Characters Shadowing Contrast Reduction Pixel by Pixel Shiftable Cursor With up to 4 Different Colours Support of Progressive Scan and 100 Hz 3 X 4Bits RGB DACs On Chip Free Programmable Pixel Clock from 10 MHz to 32MHz Pixel Clock Independent from CPU Clock Multinorm H V Display Synchronisation in Master or Slave Mode 32 TFT TV Service Manual 06 03 2006 8 7 Acquisition Features Multistandard Digital Data Slicer Parallel Multi norm Slicing TTX VPS WSS CC G Four Different Framing Codes Available Data Caption only limited by available Memory Programmable VBlI buffer Full Channel Data Slicing Supported Fully Digital Signal Processing Noise Measurement and Controlled Noise Compensation Attenuation Measurement and Compensation Group Delay Measurement and Compensation Exact Decoding of Echo Disturbed Signals 8 8 Ports One 8 bit with open drain output and optional 2 C Bus
34. be seen Hue On Off Enables disables Hue option in Picture menu First APS On Off If ON TV starts with APS menu at Start up A P S On Off Enables disables Automatic Programming System Headphone On Off Enables disables the usage of the HP and HP related items in Sound menu Vsr On Off Enables disables Vsr DBE On Off Enables disables DBE Subwoofer On Off Enables disables Subwoofer Lineout On Off Enables disables Lineout DolbyPro On Off Enables disables dolby prologic system Equalizer On Off Enables disables equalizer system BG On Off Enables disables BG Standard DK On Off Enables disables DK Standard 32 32 TFT TV Service Manual 06 03 2006 t Equalizer BG Enables disables Standard L On Off Enables disables L Standard L On Off Enables disables L Standard AUS On Off Enables disables AUS Standard NZ On Off Enables disables NZ Standard NM On Off Enables disables NM Standard FM Prs Adjusts the FM Prescaler value when Automatic Volume Levelling is Min Value 000 Max Value 255 1 Prs On Nicam Scart Prs Scart Volume Prs Off Nicam Prs Avl Off Scart Prs Avl Off Scart Volume Off HOTEL VoD gt x 027 FFFF 65535 mmm 33 32 TFT TV Service Manual 06 03 2006 Nicam Prs Adjusts the Nicam Prescal
35. citor Comparator inverting input Gnd View 32 TFT TV Service Manual 24 06 03 2006 12 17 MSP34X0G MSP3410G Multistandard Sound Processor Family 12 17 1 Introduction The MSP 34x0G family of single chip Multistandard Sound Processors covers the sound processing of all analog TV Standards worldwide as well as the NICAM digital sound standards The full TV sound processing starting with analog sound IF signal in down to processed analog AF out is performed on a single chip Figure shows a simplified functional block diagram of the MSP 34x0G This new generation of TV sound processing ICs now includes versions for processing the multichannel television sound MTS signal conforming to the standard recommended by the Broadcast Television Systems Committee BTSC The DBX noise reduction or alternatively MICRONAS Noise Reduction MNR is performed alignment free Other processed standards are the Japanese FM FM multiplex standard EIA J and the FM Stereo Radio standard Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and EIA J The MSP 34x0G has optimum stereo performance without any adjustments MSP 34x0G versions are pin and software downward compatible to the MSP 34x0D The MSP 34x0G further simplifies controlling software Standard selection requires a single C transmission only The MSP 34x0G has built in automatic functions The IC is able to detec
36. d 4 tolerance on output voltage within specified input voltages and output load conditions and 10 on the oscillator frequency X296 over 0 C to 125 C External shutdown is included featuring 80 mA typical standby current The output switch includes cycle by cycle current limiting as well as thermal shutdown for full protection under fault conditions 12 2 2 Features 3 3 V 5 0 V 12 V 15 V and Adjustable Output Versions Adjustable Version Output Voltage Range 1 23 to 37 V 4 Maximum Over Line and Load Conditions Guaranteed 3 0 A Output Current Wide Input Voltage Range Requires Only 4 External Components 52 kHz Fixed Frequency Internal Oscillator TTL Shutdown Capability Low Power Standby Mode High Efficiency Uses Readily Available Standard Inductors Thermal Shutdown and Current Limit Protection Moisture Sensitivity Level MSL Equals 1 12 2 3 Pin description TO 220 TO 220 TV SUFFIX T SUFFIX Pin 1 Vin CASE 314B CASE 314D 2 Output 3 Ground 4 Feedback Heatsink surface connected to Pin 3 5 ON OFF 32 TFT TV Service Manual 06 03 2006 12 3 LM317T 12 3 1 Description The LM317T is an adjustable 3 terminal positive voltage regulator capable of supplying in excess of 1 5 amps over an output range of 1 25 to 37 volts This voltage regulator is exceptionally easy to use and requires only two external resistors to set the output voltage Further it employs internal current limiting
37. d DRDY also referred to as HSYNC VSYNC Data Enable TxOUT o 4 Positive LVDS differential data output TxOUT Negative LVDS differential data output TxCLKIN 1 TTL level clock input Pin name TxCLK IN R FB 1 Programmable strobe select See Table 1 TxCLK OUT O 1 Positive LVDS differential clock output TxCLK OUT 1 Negative LVDS differential clock output PWR DOWN 1 TTL level input When asserted low input TRI STATES the outputs ensuring low current at power down Vec 3 Power supply pins for TTL inputs GND 4 Ground pins for TTL inputs PLL 4 1 Power supply pin for PLL PLL GND 2 Ground pins for PLL LVDS 1 Power supply pin for LVDS outputs LVDS GND 1 3 Ground pins for LVDS outputs 28 32 TFT TV Service Manual 06 03 2006 12 19 NDS8947 12 19 1 General Description These P Channel enhancement mode power field effect transistors are produced using Fairchild s proprietary high cell density DMOS technology This very high density process is especially tailored to minimize on state resistance and provide superior switching performance These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching low in line power loss and resistance to transients are needed 12 19 2 Features 30V Roson 0 065W Vos 10V Rbs oN 0 1W Ves 4
38. e a e e e d ded Td ee d eue 9 12 5 3 Pin Connections ien erp eub e a 9 126 TEABE Oi eeu a e adu oe 10 12 6 1 General description de pe nie che e ds Da eia 10 12 6 2 Features epo o ete 10 12 6 3 Pinning edet doe ton 10 12 7 2 e due 11 12 7 1 General t deben teri lle b de diii 11 12 7 2 Pin Connections and Short Descriptions 2 11 12 8 SDA5550 abite bait 13 12 8 1 General d scription eh ob eT 13 129 TPA3003D2 cea t e oet detect eb qa dite cec tius 14 12 9 1 e eb TD tib e 14 12 9 2 14 12 9 3 Pini Gonnectioh 5 2 i b isa 14 12 10 1 2A9885 86 od ede od addet ed Bau uii 15 12 101 gt General description a ioter ede mui dte b Le 15 12 10 02 Features ure ned petenti eerte ee EE Geet Roanne 15 12 10 3 PINNING eure uet te eene Eta nig a Re 15 i 32 TFT TV Service Manual 06 03 2006 12 1
39. e e pl Eee 24 12 16 3 Pin connections aided dic did edd dendi ed tad e egli e esed d de stones 24 12 17 MSP34X0G 5 4100 25 12 17 1 Introduction dnd ee d ecd ec Lc decr 25 12 17 2 Features one nee rd e 25 12 17 3 Pin connections niei dde did 26 1218 D9906385 nau Ae ete eed dele co o odes led aula Ababa aded ed eee da 28 12 18 1 General Description tdt doeet ie 28 12 18 2 FeatUltes Dee nte e e rte teret 28 12 18 3 RING 28 12 19 1 058947 tem 29 12 19 11 General Description sns onion oH bte eic 29 12 19 2 Feat ltes Dette aei p rg taire 29 19 SERVICE MENU SETTINGS itat et ee epe 30 13 17 ADJUST MENU SETTINGS intet eerte uto uit etat pl b Li et deter raga 30 19 2 OPHONS MENU SETTINGS itii eti eret delle 32 13 3 APS WSS TEST MENU ie ie iit e iP etu a c teeta endet 37 14 BLOCK DIAGRAM t ticae t berba n rte sti 38 157 CIRCUIT DIAGRAMS aieo 39 ii 32 TFT TV Service Manual 06 03 2006 1 INTRODUCTION 32 TFT TV is a progressive TV control system with built in de interlacer and scaler
40. e is to switch 8 video input sources on the 6 outputs Each output can be switched on only one of each input On each input an alignment of the lowest level of the signal is made bottom of sync top for CVBS or black level for RGB signals Each nominal gain between any input and output is 6 5dB For D2MAC or Chroma signal the alignment is switched off by forcing with an external resistor bridge 5VDC on the input Each input can be used as a normal input or as a MAC or Chroma input with external Resistor Bridge All the switching possibilities are changed through the BUS Driving 75ohm load needs an external resistor It is possible to have the same input connected to several outputs 6 AUDIO AMPLIFIER STAGE WITH TPA3002D2 The TPA3002D2 is a 9 W per channel efficient Class D audio amplifier for driving bridged tied stereo speakers The TPA3002D2 can drive stereo speakersas low as 8 The high efficiency of the TPA3002D2 eliminates the need for external heatsinks when playing music 7 POWER The LM2576 series of regulators are monolithic integrated circuits ideally suited for easy and convenient design of a step down switching regulator buck converter All circuits of this series are capable of driving a 3 0A load with excellent line and load regulation Two different versions one having a fixed output voltage of 3 3 V and one with 5 0 V of this IC are used in the regulator board 32 TFT TV Service Manual 06 03 2006 8 MICROCONTROL
41. elated reference board that outputs analog YpbPr RGB 12 13 2 Features Dual channel gm6015 based LCD TV system Industry leading Crystal Cinema Plus video scan conversion Inputs i Component analog YPbPr RGB ii 480 5761 480 576 720P and 10801 HD iii Dual NTSC PAL SECAM CVBS and YC iv SVGA XGA PC graphics Separate composite or sync on Y G vi UHF VHF RF NTSC Default output with XGA LCD interface PCB i Component analog YpbPr RGB Other outputs ii 8 16 20 24 bit 4 2 2 4 4 4 digital YCbCr RGB iii 480 5761 480 576P 720P and 10801 HD iv VGA SVGA XGA PC graphics Separate composite or sync on Y G On screen display OSD user interface with automated self running demonstration Small form factor PCB 18 32 TFT TV Service Manual 06 03 2006 12 14 AD9883A 12 14 1 General description The AD9883A is a complete 8 bit 140 MSPS monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations Its 140 MSPS encode rate capability and full power analog bandwidth of 300 MHz supports resolutions up to SXGA 1280 1024 at 75 Hz The AD9883A includes 140 MHz triple ADC with internal 1 25 V reference PLL and programmable gain offset and clamp control The user provides only a 3 3 V power supply analog input and Hsync and COAST signals Three state CMOS outputs may be powered from 2 5 V to 3 3 V The AD9883A s on chip PLL generates a pixel cl
42. emulation support PortO e Two 8 bit multifunction Port1 Port3 One 4 bit port working as digital or analogue inputs for the ADC Port2 One 2 bit I O port with secondary function P4 2 4 3 4 7 One 4 bit I O port with secondary function P4 0 4 1 4 4 Not available in P SDIP 52 9 SERIAL ACCESS CMOS 16K 2048 8 EEPROM ST24C16 The ST24C16 is a 16Kbit electrically erasable programmable memory EEPROM organised as 8 blocks of 256 8 bits The memory is compatible with the standard two wire serial interface which uses a bi directional data bus and serial clock The memory carries a built in 4 bit unique device identification code 1010 corresponding to the bus definition This is used together with 1 chip enable input E so that up to 2 8K devices may be attached to the bus and selected individually 10 CLASS AB STEREO HEADPHONE DRIVER TDA1308 The TDA1308 is an integrated class AB stereo headphone driver contained a DIP8 plastic package The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital audio applications 11 SAW FILTERS K3953M is an IF Filter for Video Applications The package is SIP5K Supported standards are B G D K L L K9656M is an IF Filter for Audio Applications The package is SIP5K Supported standards are B G D K L L 32 TFT TV Service Manual 06 03 2006 12 1 DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM LM1117
43. er operation the pixel clock generator PLL requires an external filter Connect the filter shown in Figure 6 to this pin For optimal performance minimize noise and parasitics on this node POWER SUPPLY Vp Main Power Supply These pins supply power to the main elements of the circuit They should be as quiet and filtered as possible Digital Output Power Supply A large number of output pins up to 25 switching at high speed up to 110 MHz generate a lot of power supply transients noise These supply pins are identified separately from the VD pins so special care can be taken to minimize output noise transferred into the sensitive analog circuitry If the AD9883A is interfacing with lower voltage logic VDD may be connected to a lower supply voltage as low as 2 5 V for compatibility Vp Clock Generator Power Supply The most sensitive portion of the AD9883A is the clock generation circuitry These pins provide power to the clock PLL and help the user design for optimal performance The designer should provide quiet noise free power to these pins GND Ground The ground return for all circuitry on chip It is recommended that the AD9883A be assembled on a single solid ground plane with careful attention to ground current paths 21 32 TFT TV Service Manual 06 03 2006 12 15 141585 12 15 1 General description This is a high performance HCMOS device designed to interface with a micro controller un
44. er value when Automatic Volume Levelling is On Min Value 000 Max Value 255 Scart Prs On Adjusts the Scart Prescaler value when Automatic Volume Levelling is On Min Value 000 Max Value 255 Scart Volume On Adjusts the Scart Volume value when Automatic Volume Levelling is On Min Value 000 Max Value 255 FM Prs Avl Off Adjusts the FM Prescaler value when Automatic Volume Levelling is Off Min Value 000 Max Value 255 Nicam Prs Avl Off Adjusts the Nicam Prescaler value when Automatic Volume Levelling is Off Min Value 000 Max Value 255 Scart Prs Avl Adjusts the Scart Prescaler value when Automatic Volume Levelling is Off Min Value 000 Max Value 255 Scart Volume Off Adjusts the Scart Volume value when Automatic Volume Levelling is Off Min Value 000 Max Value 255 Hotel VoD On Off Enables disables Hotel Video on Demand feature Fast TXT TXT Lang IF Freq Sound Carrier 4 34 32 TFT TV Service Manual 06 03 2006 Enables disables Automatic Volume Levelling feature Top TXT On Off Enables disables TopText feature Fast TXT On Off Enables disables FastText feature TXT Lang Switches between Teletext Language Groups Min Value 000 Max Value 004 IF Freq Adjusts the IF Frequency value Min Value 000 Max Value 255 Sound On Off Enables disables Sound Carrier On Off En
45. erts 21 bits of LVCMOS LVTTL data into three LVDS Low Voltage Differential Signaling data streams Both transmitters can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe Receiver DS90CF386 DS90CF366 without any translation logic The DS90C385 is also offered in 64 ball 0 8mm fine pitch ball grid array FBGA package which provides a 4496 reduction in PCB footprint compared to the TSSOP package This chipset is an ideal means to solve EMI and cable size problems associated with wide high speed TTL interfaces 12 18 2 Features 20 to 85 MHz shift clock support Best in Class Set amp Hold Times on TxINPUTs Tx power consumption 130 mW typ 85MHz Grayscale Tx Power down mode lt 200 Supports SVGA XGA and Single Dual Pixel SXGA Narrow bus reduces cable size and cost Up to 2 38 Gbps throughput Up to 297 5 Megabytes sec bandwidth 345 mV typ swing LVDS devices for low PLL requires no external components Compatible with TIA EIA 644 LVDS standard Low profile 56 lead or 48 lead TSSOP package DS90C385 also available a 64 ball 0 8mm fine pitch ball grid array FBGA package 12 18 3 Pinning Pin Name vo No Description TxIN 28 TTL level input This includes 8 Red 8 Green 8 Blue and 4 control lines FPLINE FPFRAME an
46. ery Powered Instrumentation 12 1 4 Connection Diagrams 507 223 0 252 Inm our T nutut 3 Ml onte 101 582 D5100615 4 05100014 2 inb Top View Top View EAS Top View 32 TFT TV Service Manual 06 03 2006 12 2 1 2576 12 2 1 General Description The LM2576 series of regulators are monolithic integrated circuits ideally suited for easy and convenient design of a step down switching regulator buck converter All circuits of this series are capable of driving a 3 0 A load with excellent line and load regulation These devices are available in fixed output voltages of 3 3 V 5 0 V 12 V 15 V and an adjustable output version These regulators were designed to minimize the number of external components to simplify the power supply design Standard series of inductors optimized for use with the LM2576 are offered by several different inductor manufacturers Since the LM2576 converter is a switch mode power supply its efficiency is significantly higher in comparison with popular three terminal linear regulators especially with higher input voltages In many cases the power dissipated is so low that no heatsink is required or its size could be reduced dramatically A standard series of inductors optimized for use with the LM2576 are available from several different manufacturers This feature greatly simplifies the design of switch mode power supplies The LM2576 features include a guarantee
47. for all negative and positive modulated standards via l C bus Digital acquisition help VIF frequencies of 33 4 33 9 38 0 38 9 45 75 and 58 75 MHz 4 MHz reference frequency input signal from Phase Locked Loop PLL tuning system or operating as crystal oscillator VIF Automatic Gain Control AGC detector for gain control operating as peak sync detector for negative modulated signals and as a peak white detector for positive modulated signals Precise fully digital Automatic Frequency Control AFC detector with 4 bit digital to analog converter AFC bits via bus readable TakeOver Point TOP adjustable or alternatively with potentiometer Fully integrated sound carrier trap for 4 5 5 5 6 0 and 6 5 MHz controlled by FM PLL oscillator Sound IF SIF input for single reference Quasi Split Sound QSS mode PLL controlled SIF AGC for gain controlled SIF amplifier single reference QSS mixer able to operate in high performance single reference QSS mode and in intercarrier mode switchable via C bus AM demodulator without extra reference circuit Alignment free selective FM PLL demodulator with high linearity and low noise control for all functions l C bus transceiver with pin programmable Module Address MAD 12 10 3 Pinning SYMBOL PIN DESCRIPTION VIF1 1 VIF differential input 1 VIF2 2 VIF
48. for minimal overhead SDA 55XX is realized in 0 25 micron technology with 2 5 V supply voltage and 3 3 V I O TTL compatible The software and hardware development environment TEAM is available to simplify and speed up the development of the software and On Screen Display TEAM stands for TVT Expert Application Maker It improves the TV controller software quality in following aspects Shorter time to market Re usability Target independent development Verification and validation before targeting General test concept Graphical interface design requiring minimum programming and controller know how Modular and open tool chain configurable by customer 13 32 TFT TV Service Manual 06 03 2006 12 9 00302 12 9 1 General Description The TPA3002D2 is a 9 W per channel efficient Class D audio amplifier for driving bridged tied stereo speakers The TPA3002D2 can drive stereo speakers as low as 8 amp The high efficiency of the TPA3002D2 eliminates the need for external heatsinks when playing music 12 9 2 Features 9 W Ch Into an 8 O Load From 12 V Supply Efficient Class D Operation Eliminates Heatsinks and Reduces Power Supply Requirements 32 Step DC Volume Control From 40 dB to 36 dB Line Outputs For External Headphone Amplifier With Volume Control Regulated 5 V Supply Output for Powering TPA6110A2 Space Saving Thermally Enhanced PowerPAD Packaging Thermal and Short
49. icrocontroller with television specific hardware features Microcontroller has been enhanced to provide powerful features such as memory banking data pointers and additional interrupts etc The on chip display unit for displaying Level 1 5 teletext data can also be used for customer defined on screen displays Internal XRAM consists of up to16 Kbytes Device has an internal ROM of up to 128 KBytes ROMless versions can access up to 1 MByte of external RAM and ROM The SDA 55XX supports a wide range of standards including PAL NTSC and contains a digital slicer for VPS WSS PDC TTX and Closed Caption an accelerating acquisition hardware module a display generator for Level 1 5 TTX data and powerful On screen Display capabilities based on parallel attributes and Pixel oriented characters DRCS The 8 bit Microcontroller runs at 360 ns cycle time min Controller with dedicated hardware does most of the internal TTX acquisition processing transfers data to from external memory interface and receives transmits data via l C firmware user interface The slicer combined with dedicated hardware stores TTX data in a VBI buffer of 1 Kilobyte The Microcontroller firmware performs all the acquisition tasks hamming and parity checks page search and evaluation of header control bits once per field Additionally the firmware can provide high end Teletext features like Packet 26 handling FLOF TOP and list pages The interface to user software is optimized
50. idth 200 MHz Low ON resistance 3W Low crosstalk at 10 MHz 58 dB Ultra low quiescent power 0 1 pA typical Single supply operation 5 0V Fast switching 10 ns High current output 100 mA Packages available 16 300 mil wide plastic SOIC S 16 pin 150 mil wide plastic SOIC W 16 pin 150 mil wide plastic QSOP Q 12 12 3 Pin Descriptions Pin Name Description Sia S24 Analog Video 516 S25 Sic S2c S1p S2p IN Select Input EN Enable DA Analog Video Dc Dp GND Ground Power 17 32 TFT TV Service Manual 06 03 2006 12 13 GM6015 12 13 1 General description The Genesis Microchip 6015RD1 LCD TV reference board is a complete display processor for LCD PDP and LCOS based televisions The reference board demonstrates the processing capabilities of the Genesis Microchip gm6015 television controller IC The gm6015 IC is a full featured dual channel video processor with Genesis industry leading Crystal Ciema Plus video scan conversion The 6015801 board inputs analog YPbPr RGB NTSC PAL SECAM CVBS YC UHF VHF and outputs digital RGB to an XGA LCD panel A convenient on screen display system provides easy control of the board s processing capabilities The design kit is complete with hardware and software Software includes G Probe debug software G Wizard register calculator and G TV application source code The 6015 1 is a r
51. it to allow colored symbols or characters to be displayed onto a LCD monitor Because of the large number of fonts 512 fonts including 496 standard fonts and 16 multi color fonts LMOSD2 16 is suitable to be adopted for the multi language monitor application especially It minimizes the MCU s burden through its built in RAM By storing a full screen of data and control information this device has a capability to carry out screen refresh without any MCU supervision Programmable hatch pattern generator is added for individual pixel inspection Since there is no clearance between characters special graphics oriented characters can be generated by combining two or more character blocks The full OSD menu is formed of 15 rows x 30 columns which can by freely positioned on anywhere of the monitor screen by changing vertical or horizontal delay Special functions such as character background color blinking bordering or shadowing four level windows with programmable size row double height and double width programmable vertical height of character and row to row spacing and full screen erasing and Fade In Fade Out are also incorporated There are 8 color selections for any individual character display with row intensity attribute and window intensity attribute to expand the color mixture on OSD menu 12 15 2 Features Totally 512 Fonts Including 496 Standard Fonts and 16 Multi Color Fonts 10x18 or 12x18 Font Matrix Selection Maximum Pixel
52. lock Min Value 000 Max Value 003 TUNER OPTION Philips Thomson Selects the tuner type used 13 3 APS WSS TEST MENU In order to enter Aps Wss Test menu move the cursor to Aps Wss Test parameter by pressing A V buttons in Service Menu and press lt gt button The following menu appears on the screen Aps Wss Test gt Programme Search VPS Pdc Format 1 Pdc Format 2 Name Wss CNN 504 BG 463 There are 7 items in the Aps Wss Test menu Programme Search VPS Pdc Format 1 Pdc Format 2 Name Wss 37 32 TFT TV Service Manual 06 03 2006 14 BLOCK DIAGRAM ndn 1 4 SDRAM LVDS m 2MX32bits DS90C385 AMPLIFIER gt TPA3002 S VIDEO IN CVBS IN AUDIO IN 5 9883 j go r m 5 LINE OUT 9 L amp R 2 2 SUBWOOFER 5 o 5 gt m 23 o tc z PRO 9 VPC3230 MCU SDAS5550 tc E BL ON OFF BRT ADJ gt z lt w 9 a o N YPBPRIN YPbPr In SCART2 SCART1 PC AUDIO IN 38 32 TFT TV Service Manual 06 03 2006 15 CIRCUIT DIAGRAMS Yayo vvvvvvvvvy und N A A v eee hehe il vile
53. mable low pass and complementary high pass filter 5 band graphic equalizer for loudspeaker channel 25 32 TFT TV Service Manual 06 03 2006 Spatial effect for loudspeaker channel Four Stereo SCART line inputs one Mono input two Stereo SCART outputs Complete SCART in out switching matrix e Two 125 inputs one 29 output Dolby Pro Logic with DPL 351xA coprocessor All analog FM Stereo A2 and satellite standards AM SECAM L standard Simultaneous demodulation of very high deviation FM Mono and NICAM Adaptive deemphasis for satellite Wegener Panda acc to ASTRA specification ASTRA Digital Radio ADR together with DRP 3510A All NICAM standards Korean FM Stereo A2 standard 12 17 3 Pin connections NC not connected leave vacant LV if not used leave vacant OBL obligatory connect as described in circuit diagram DVSS if not used connect to DVSS AHVSS connect to AHVSS Pin No Pin Name Type ie dg pc PLCC PSDIP PSDIP PQFP PLQFP 68 pin 64 pin 52 pin 80 pin 64 pin Short Description 1 16 14 9 8 ADR WS OUT LV ADR word strobe 2 NC LV Not connected 3 15 13 8 7 ADR DA OUT LV ADR Data Output 4 14 12 7 6 128 DA 1 1 IN LV 51 data input 5 13 11 6 5 128 DA OUT OUT LV 5 data output 6 12 10 5 4 128 WS IN OUT LV 25 word strobe 7 11 9 4 3 I2S_CL IN OUT LV 25 clock 8 10 8 3 2 2 DA IN OUT OBL data 9 9 7 2
54. n not used this pin must be grounded and Clamp Function programmed to 0 COAST Clock Generator Coast Input Optional This input may be used to cause the pixel clock generator to stop synchronizing with Hsync and continue producing a clock at its current frequency and phase This is useful when processing signals from sources that fail to produce horizontal sync 32 TFT TV Service Manual 20 06 03 2006 pulses during the vertical interval The COAST signal is generally not required for PC generated signals The logic sense of this pin is controlled by Coast Polarity register OFH Bit 3 When not used this pin may be grounded and Coast Polarity programmed to 1 or tied HIGH to VD through a 10 k resistor and Coast Polarity programmed to 0 Coast Polarity defaults to 1 at power up REF BYPASS Internal Reference BYPASS Bypass for the internal 1 25 V band gap reference It should be connected to ground through a 0 1 uF capacitor The absolute accuracy of this reference is 4 and the temperature coefficient is 50 ppm which is adequate for most AD9883A applications If higher accuracy is required an external reference may be employed instead MIDSCV Midscale Voltage Reference BYPASS Bypass for the internal midscale voltage reference It should be connected to ground through a 0 1 uF capacitor The exact voltage varies with the gain setting of the BLUE channel FILT External Filter Connection For prop
55. ock from the Hsync input Pixel clock output frequencies range from 12 MHz to 140 MHz PLL clock jitter is 500 ps p p typical at 140 MSPS When the COAST signal is presented the PLL maintains its output frequency in the absence of Hsync A sampling phase adjustment is provided Data Hsync and clock output phase relationships are maintained The AD9883A also offers full sync processing for composite sync and sync on green applications A clamp signal is generated internally or may be provided by the user through the CLAMP input pin This interface is fully programmable via a 2 wire serial interface Fabricated an advanced CMOS process the AD9883A is provided a space saving 80 lead LQFP surface mount plastic package and is specified over the OC to 70C temperature range 12 14 2 Features 140 MSPS Maximum Conversion Rate 300 MHz Analog Bandwidth 0 5 V to 1 0 V Analog Input Range 500 ps p p PLL Clock Jitter at 110 MSPS 3 3 V Power Supply Full Sync Processing Sync Detect for Plugging Midscale Clamping Power Down Mode Low Power 500 mW Typical 4 2 2 Output Format Mode 12 14 3 Pin Descriptions Pin Name Function OUTPUTS HSOUT Horizontal Sync Output A reconstructed and phase aligned version of the Hsync input Both the polarity and duration of this output can be programmed via serial bus registers By maintaining alignment with DATACK and Data data timing with respect to horizont
56. pply value as low as 2 5V Both Plastic Dual in Line and Plastic Small Outline packages are available 12 4 2 Features 1 million Erase Write cycles 40 years data retention 2 5V to 5 5V single supply voltage 400k Hz compatibility over the full range of supply voltage Two wire serial interface PC bus compatible Page Write Up To 8 Bytes Byte random and sequential read modes Self timed programming cycle Automatic address incrementing Enhanced ESD Latch up Performances 12 4 3 Pin connections ST24LC21 ST24LC21 NC C3 NC C2 NC C13 Vss 4 OC 01499 AXI BOO DIP Pin connections CO Pin connections NC Not connected Signal names SDA Serial data Address Input Output SCL Serial Clock Supply voltage Vss Ground VCLK Clock transmit only mode 32 TFT TV Service Manual 06 03 2006 12 5 TEA5114A 12 5 1 General description This integrated circuit provides RGB switching allowing connections between peri TV plug internal RGB generator and video processor in a TV set The input signal black level is tied to the same reference voltage on each input in order to have no differential voltage when switching two RGB generators An AC output signal higher than 2 Vpp makes gain going slowly down to OdBto protect the TV set video amplifier from saturation Fast blanking output is a logical OR between FB1 Pin 8 and FB2 Pin 10 12 5 2 Features
57. put 61 NC LV Not Connected 62 XTAL1 IN X Analog Crystal Input 63 XTAL2 OUT X Analog Crystal Output 64 ASGF X Analog Shield GNDr 65 GNDr SUPPLYA X Ground Analog Front End 66 VRT OUTPUT X Reference Voltage Top Analog 67 I2CSEL IN X Bus Address Select 68 ISGND SUPPLYA X Signal Ground for Analog Input connect to 69 SUPPLYA X Supply Voltage Analog Front End 70 VOUT OUT LV Analog Video Output 71 CIN IN LV Chroma Analog Video 5 Input 72 VIN1 IN VRT Video 1 Analog Input 73 VIN2 IN VRT Video 2 Analog Input 74 VIN3 IN VRT Video 3 Analog Input 75 VIN4 IN VRT Video 4 Analog Input 76 Vsupal SUPPLYA X Supply Voltage Analog Component Inputs Front End 77 GNDAI SUPPLYA X Ground Analog Component Inputs Front End 78 VREF OUTPUT X Reference Voltage Top Analog Component Inputs Front End 79 FB1IN IN VREF Fast Blank Input 80 AISGND SUPPLYA X Signal Ground for Analog Component Inputs connect to GNDAI 32 TV Service Manual 12 06 03 2006 12 8 SDA55XX 50 5550 12 8 1 General description The SDA55XX is a single chip teletext decoder for decoding World System Teletext data as well as Video Programming System VPS Program Delivery Control PDC and Wide Screen Signalling WSS data used for PAL plus transmissions Line 23 The device also supports Closed caption acquisition and decoding The device provides an integrated general purpose fully 8051 compatible M
58. t This input is provided to assist with processing signals with embedded sync typically on the GREEN channel The pin is connected to a high speed comparator with an internally generated threshold The threshold level can be programmed in 10 mV steps to any voltage between 10 mV and 330 mV above the negative peak of the input signal The default voltage threshold is 150 mV When connected to an ac coupled graphics signal with embedded sync it will produce a noninverting digital output on SOGOUT This is usually a composite sync signal containing both vertical and horizontal sync information that must be separated before passing the horizontal sync signal to Hsync When not used this input should be left unconnected For more details on this function and how it should be configured refer to the Sync on Green section CLAMP External Clamp Input This logic input may be used to define the time during which the input signal is clamped to ground It should be exercised when the reference dc level is known to be present on the analog input channels typically during the back porch of the graphics signal The CLAMP pin is enabled by setting control bit Clamp Function to 1 register OFH Bit 7 default is O When disabled this pin is ignored and the clamp timing is determined internally by counting a delay and duration from the trailing edge of the Hsync input The logic sense of this pin is controlled by Clamp Polarity register OFH Bit 6 Whe
59. t the actual sound standard automatically Automatic Standard Detection Furthermore pilot levels and identification signals can be evaluated internally with subsequent switching between mono stereo bilingual no interaction is necessary Automatic Sound Selection Sound E Sound 2 1281 1282 5 Loud spesker o speaker Sound Processing Subwoofer Headphone Sound Processing Headphone Source Select 128 SCARTI SCART2 SCARTI SCART3 SCART4 MONO 4 SCART2 Source Select lS bus interface consists of five pins 1 125 DA IN1 125 DA IN2 For input four channels two channels per line 2 16 bits per sampling cycle 32 kHz are transmitted 2 125 DA OUT For output two channels 2 16 bits per sampling cycle 32 kHz are transmitted 3 I2S CL Gives the timing for the transmission of 125 serial data 1 024 MHz 4 125 WS The 125 WS word strobe line defines the left and right sample 12 17 2 Features Standard Selection with single transmission Automatic Standard Detection of terrestrial TV standards Automatic Sound Selection mono stereo bilingual new registers MODUS STATUS Two selectable sound IF SIF inputs Automatic Carrier Mute function Interrupt output programmable indicating status change Loudspeaker Headphone channel with volume balance bass treble loudness AVC Automatic Volume Correction Subwoofer output with program
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