BEC-Service Manual
Contents
1. 4 C10 m o ra RO Tic AMP F 1 CPU LCD gt 143 1 RESET Ai 3 Frese 1 88 2 1 Merlo sai na E TI I FL KEYBOARD rica EEPROM ela J JN050908 ci3 017 828 015 Ba 20 O O EE n Ria 8 E g 825 CI C4 hh JR E267 ea GARA ll 8418 Lars gl 5 c73 dI pale 9 15 L 285 pai 1 8 El ag O 8115 ee 23 Bl 18 258 127 Es ES DI ctsz Ji 848 2235 RUS gl 71 gl ca SS 1082 8 85 pecs Blas EI a EA 2 a ESE 8 1 299 Ri 20 Bi ng k El 210 R31 184 O ga 102 EE E gt 88 ci35 Sl zl Hi LI IN El caga BA g J aa Ea RESO BE 5 G METE La 18 6123 RIE Sa ci io 1014 Et x er cA ms 3 q 68 3 ET Sela I e m g E A xx El Islslgl 2143 g g a SJL 12199 i ma GQ FU cI tel ES we L J C24 kl o FL2 FL3 g 8 5 EJE El RI LI El C R94 c149 O TS 11 57 Ss sl se 178 1367 Ri79 ci eg ie 6821 8 sz a Q26 Ia La 22. N Else EI Fia GZ 448 m3 iP a FR 8 8 R36 R98 F ez FIERO oo un A 3 Rt1l RI2 Gal 3 gt R27 Rios R28 Bi 04 C20 8 20 R173 EE a a R160 113 as 441 ri 66 gl el Rta 0 A E 118118 gt ez ii c195 18 El Rise 840 z 0186 igs 22 62 R167 tia a 0101 2216 06 c14 R42 er33 857 1 27 028 Ri19 cis 1 1 LI D 194 51 0426 31 rao Rir Rise C33 13 5 21 ess bed nit R164 5 812 Riss ci 28 Sal paga 127 Bas m 2
3. signal The audio signals change the reactance of a diode D29 to modulate an oscillated signal at the VCO circuit Q30 The oscillated signal is amplified at the buffer amplifiers Q31 Q32 Q33 Q35 3 DRIVE POWER AMPLIFIER CIRCUITS The signal from the VCO circuit passes through the buffer Q31 Q32 Q33 Q35 drive Q27 and power amplifier Q26 to obtain 4W of RF power at 7 4V DC The amplified signal passes through the antenna switching circuit D11 and low pass filter and is then applied to the antenna connector The bias current of the drive IC6 and the power amplifier Q26 is controlled by the APC circuit 4 APC CIRCUIT The APC circuit IC6 protects the drive and the power amplifiers from excessive current drive and selects HIGH or LOW output power The signal output from the power detector circuit L82 R177 RR95 RR144 is applied to the differential amplifier IC6 2 3 and the PWC signal from the expander IC6 pin5 controlled by the CPU 1 8 is applied to the other input for reference When the driving current is increased input voltage of the differential amplifier pin 2 will be increased In such cases the differential amplifier output voltage pin 7 is decreased to reduce the driving current 3 PLL Synthesizer Circuit 1 PLL The dividing ratio is obtained by sending data from the CPU IC8 to pin 14 and sending clock pulses to pin 15 of the PLL IC IC13 The oscillated signal from the VCO is amplified
4. DEV Reference sensitivity 12dB SINAD Specified audio output level 200mW at 8 Adjustment Mode High power adjustment mode 1 A same time push 3 key and 9 key Rotate VOL to the power ON Then press 7 key Press the 6 or 9 key set the output power to the value closest to 4 W When the PTT key is released the output power at that time will be stored as the high power setting Press the SQL key to return OB C N Low power adjustment mode 1 A same time push 3 key and 9 key Rotate VOL to the power ON 2 Then press 8 key 3 Press the 6 or 9 key set the output power to the value closest to 1 W 4 When the PTT key is released the output power at that time will be stored as the low power setting 5 Press the SQL key to return Modulation Adjustment STEP CONDITIONS ADJUST READINGS Connect the antenna output via a suitable RF attenuator to a modulation analyzer 2 Apply 1000Hz at a level of 5 0mV to Press the PTT switch a analyzer reading 1 5kHz i oe ma wal Increase the modulation signal iin analyzer reading 2 5kHz BENISON FB 388 Frequency Adjustment STEP CONDITIONS ADJUST READINGS Connect the antenna output via a suitable RF attenuator to a Frequency counter Press the PTT switch Frequency counter 0 2KHz SERVICING AND REPAIR RF RECEIVE CIRCUITS 1 Ensure that the transceiver has not been switched to the battery saving mode 2 Careful
5. is operating correctly a 1kHz sine wave should be present 2 If not then use the oscilloscope to check the second local oscillator to assure that it is operating correctly A probe connected to the case of or pin 16 of IC13 should detect the presence of a 9 BENISON FB 388 38 4MHz sine wave If not then X6 may have failed 3 If a 1kHz signal is measured at pin 9 of IC14 then decrease the output level of the signal generator to 0 35uV If the 1kHz audio signal disappears when the RF level is decreased to this level then 1 14 may be faulty 4 If IC14 appears okay then check IC1 are correct Check for the presence of a 1kHz audio signal at the collector of the pin10 5 Check pin 14 of IC3 to see if there is a 1kHz audio signal present Check pin 10 of IC1 for a presence of a large 1kHz audio signal If the audio output signal is too small or not present then IC1 may be faulty CONTROL PROBLEM If the LCD display becomes faulty then check the drive IC 10 10 BENISON FB 388 PARTS LIST Part Type Designator Footprint C1 1000P C2 1000P C3 1000P C4 1000P C5 1000P C6 1000P C7 1000P C8 1000P C9 1000P C10 1000P C11 1000P C12 1000P C13 1000P C14 1000P C15 1000P C16 1000P C17 1000P C18 1000P C19 1000P C20 1000P C22 1000P C23 1000P C24 1000P C25 1000P C26 1000P C27 1000P C28 1000P C29 1000P C30 1000P C31 1000P C32 1000P C33 1000P C34 1000P C35 1000P C36 1000P C37 1000P C38 1000P C39 1000P C40 100
6. 00MHz miih wY l VCO 030 3 Q35 07 sa 03 PRE DRVE PWR PLLC N DS AMP D11D13 x I N at C13 1 FIL x da TUE BUFF gt dele ee 8 gt al 1 r 1 1 Fr eo z 2 gt ant sw fe be Da LPE ToO T Lino Se pro Gere Tre 4 EEE 2 VEO 025 034 LI 1 N LA LOOP 1 FIL L NBUFF I le L CO I ERNST HZ 1 L n 640686 _ _ _55666636033 P p AFAMP RA 0 FL2FL3 s e i J E Xi A kA WI VOL Nor IN Sa RAN A A 1 IF ts SJ Nr ae gi ee 028 RF AMP a tal i 1 I 1 pp I _ DELI A 1 1 1 Bere oder I bb Se SE AA JACK SP 2 E 228 sli IA Kerne Li 1 1 Tee BT Pet 1 2 1 1 a i a Era i ty sq TIE E er W ___ Jmm e a de 1 ar LCD DRIVE ee nn ina eg le eee SN Aw a a he des we wee oe FS Free
7. 0P C41 1000P C42 1000P C43 1000P C44 1000P 11 BENISON FB 388 C45 1000P C46 1000P C47 1000P C48 1000P C49 1000P C50 1000P C51 1000P C52 1000P C53 1000P C54 1000P C55 1000P C56 1000P C57 1000P C58 0 01 C59 0 01 C60 0 01 C61 0 01 C62 0 01 C63 0 01 C64 0 01 C65 0 01 C66 0 01 C67 0 01 C69 100P C70 1000P C71 0 1 C72 1000P C73 15P C74 10U C75 10U C76 10U C77 10U C78 10U C79 10U C80 10U C81 10U C82 10U C83 10U C84 10U C85 100P C86 100P C87 100P C88 100P C89 100P C90 100P C91 100P 12 BENISON FB 388 C92 100P C93 100P C94 100P C95 100P C96 100P C97 0 1 C98 0 1 C99 0 1 C100 0 1 C101 0 1 C102 0 1 C103 0 1 C104 0 1 C105 0 1 C106 0 1 C107 0 1 C108 0 1 C109 0 1 C110 0 1 C111 0 1 C112 0 1 C113 0 047 C114 0 047 C115 0 047 C116 22P C117 22P C118 22P C119 22P C120 22P C121 22P C122 22P C123 5600P C124 5600P C125 0 022 C126 220P C127 220P C128 220P C129 220P C130 1U C131 1U C132 1U C133 1U C134 1U C135 180P C136 200P C137 10U 13 BENISON FB 388 C138 1U C140 0 22 C141 0 22 C142 0 22 C143 0 22 C144 0 22 C145 0 22 C146 100U C147 100U C148 22U C149 1U C150 1U C151 8200P C152 10P C153 10P C154 10P C155 10P C156 10P C157 10P C158 10P C159 10P C160 470P C161 470P C162 470P C163 470P C164 470P C165 470P C166 470P C167 470P C168 470P C169 10U C170 10U C171 0 1U C172 0 1U C173 102P C174 47P C175 47P C176 4 7U C177 4 7U C178 17P C179 1P
8. 2 470 R63 2K R64 2K R65 T10K R66 15K R67 15K R68 3K3 R69 3K3 R70 3K3 R71 3K3 R72 3K3 R73 3K3 R74 3K3 R75 0 R76 0 R77 0 R78 0 R79 0 R80 0 R81 0 R82 0 R83 0 R84 0 R85 2K7 R86 2K7 R87 100K R88 100K R89 100K R90 100K R91 100K R92 100K 20 BENISON FB 388 R93 100K R94 100K R95 100K R96 100K R97 100K R98 100K R99 1K R100 1K R101 1K R102 1K R103 1K R104 1K R105 1K R106 1K R107 1K R108 1K R109 1K R110 1K R111 1K R112 1K R113 1K R114 1K R115 1K R116 1K R117 1K R118 1K R119 1K R120 220K R121 220K R122 220K R123 220K R124 330K R125 330K R126 10 R127 47 R128 33K R129 0 R130 2K R131 120K R132 33K R133 10 R134 10 R135 22K R136 22K R137 470K R138 1M 21 BENISON FB 388 R139 1M R140 1M R141 1M R142 68K R143 180K R144 180K R145 180K R146 180K R147 3K9 R148 3K9 R149 3K9 R150 1K5 R151 1K5 R152 1K8 R153 47 R154 47 R155 6K8 R156 2 2 157 2K2 R158 2K2 R159 22 R160 22 R161 20K R162 33K R163 33K R164 10K R165 10K R166 10K R167 47K R168 47K R169 100 R170 3K3 R171 680 R172 680 R173 2 2 R174 47 R175 47 R176 150K R177 82K R178 220 R179 220 R180 56K R181 330K R182 82K R183 180K R184 180K BENISON R185 Part Type MC1 SP1 WI W2 W3 505 5 180K Designator Footprint MIC 58dB 8ohm W50K 10K 50K 4M 32 768K 16 8M C24 38 4M 23 FB 388 BENISON FB 388 MEMO 24 FB 388 BLOCK DIAGRAM TCXO 168
9. 2T L2 102T L3 102T L5 102T L6 102T L7 102T L8 102T L9 10UH L11 150N L12 180N L13 2 2UH L14 2 2UH L15 2 2UH L16 2 2UH L17 100N L18 100N L19 100N L20 100N L21 68N L22 470N L23 470N L24 102T L25 102T L26 7T L27 7T L28 7T L29 7T L30 7T BENISON FB 388 L31 1UH L32 301T L33 9T L34 3T L35 2T L36 2 2UH L37 4T L38 5T L39 5T L40 6T Part Type Designator Footprint Q1 5B1 Q2 2SC2712 Q3 2SC2712 Q5 DTA114 Q6 DTA114 Q7 DTA114 Q8 DTA114 Q9 DTA114 Q10 DTA114 Q11 DTA114 Q12 DTA114 Q13 5B1 Q14 5B1 Q15 2SK1588 Q16 DTA114 Q17 DTA114 Q18 DTA114 Q19 DTA114 Q20 DTA114 Q21 DTA114 Q22 DTA114 Q23 2SC4617 Q24 2SC4617 Q25 K52 Q26 R007 Q27 2SK2973 Q28 DUR Q29 DUR Q30 K52 Q31 R24 Q32 R24 Q33 R24 Q36 2SC5195 Part Type Designator Footprint 18 BENISON RI R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 47K 47K 47K 47K 47K 47K 47K 47K 47K 47K 47K 47K 47K 220 220 330 330 330 330 330 330 330 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 4K7 4K7 4K7 4K7 560 560 560 560 100 100 19 FB 388 BENISON FB 388 R47 100 R48 100 R49 100 R50 100 R51 100 R52 100 R53 100 R54 100 R55 100 R56 100 R57 100 R58 100 R59 470 R60 470 R61 470 R6
10. BENISON FB 388 BENISON FB 388 VHF FM TRANSCEIVERS Service Manual BENISON SPECIFICATIONS FB 388 GENERAL Frequency coverage 144 0000 145 9875MHz Type of emission FM FE3 Number of channels 99ch Power supply requirement Current drain approx Frequency stability Usable temperature range Dimensions projections not included Weight with ant BP 512 TRANSMITTER RF output power at 7 4 V DC Modulation system 7 4 V DC negative ground supplied battery pack Transmit at High 4 0 W 1 8 A at Low 1 0 W 700 mA Receive rated audio 250 mA stand by 70 mA 0 001 1 10 CO 60 C 54 W x 112 H x 35 D mm 350 g 4 W 1 W High Low Variable reactance frequency modulation Maximum frequency deviation 2 5 kHz Spurious emissions 70 dB typical Adjacent channel power 60 dB typical Transmitter audio distortion RECEIVER Receive system Intermediate frequencies Sensitivity Squelch sensitivity Adjacent channel selectivity Spurious response rejection Intermodulation rejection ratio Hum and noise Audio output power at 7 4 V DC Less than 3 at 1 kHz 40 deviation Double conversion superheterodyne system 151 38 850 MHz 2nd 450 kHz 0 18 pV at 12 dB SINAD typical 0 25 V at threshold typical 65 dB typical 70 dB typical 70 dB typical 40 dB typical 500 mW typical at 5
11. C180 1P C181 1P C182 15P C183 12P C184 12P 14 BENISON FB 388 C185 12P C186 12P C187 12P C188 12P C189 12P C190 12P C191 0 5P C192 0 5P C193 82P C194 8P C195 18P C196 18P C197 18P C198 18P C199 5 200 4 201 4 C202 7P C203 20P C204 20P C205 33P C206 207 1000 C208 1000P C209 1000P C210 1000P C211 0 01 C212 100P C213 100P C214 100P C215 100P C216 0 1 C217 0 01 C218 0 01 C219 22U C220 1000P C221 1000P C222 1000P C223 1000P C224 1000P C225 1000P C226 1000P C227 1000P C228 1000P C229 1000P C230 100P 15 BENISON Part Type D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 Part Type FL1 FL2 FL3 Part Type IC1 IC2 IC3 IC4 IC5 IC6 IC8 IC10 Designator Footprint LED_Y LED_Y 155372 LED_Y LED_Y A111 LED_Y LED_Y A111 A111 155356 5277 155356 111 111 111 111 111 111 111 LED_G LED_R N 3V HVC375 HVC375 HVC375 HVC375 BB149 Designator Footprint LTC450E 38 85M 38 85M Designator Footprint TA7368F NJM2902V CMX808 24WC08 XC6202P502 NJM2904 EM78P567 HT1621B 16 FB 388 BENISON FB 388 IC13 M64082 IC14 TA31136 Part Type Designator Footprint JACK MIC J2 SMD14P J3 ANT JACK J4 SMD14P J5 SP J Part Type Designator Footprint K1 FUNC K2 MONI K3 PTT K4 RTW K5 POWER SW Part Type Designator Footprint L1 10
12. ated frequency A portion of the VCO signal is amplified at the buffer amplifier Q34 Q31 and is then applied to the receive 1st mixer Q28 or transmit buffer amplifier circuit Q32 4 CPU and Peripheral Circuits 1 LCD Display Circuit The IC10 turns ON the LCD via segment and common terminals with 1 4 the duty and 1 3 the bias at the frame frequency is 100Hz 2 Display Lamp Circuit When the key is pressed is output form pin 24 of CPU IC8 to the bases of Q2 Q2 then turn ON and the LED D1 2 4 5 7 8 light 3 DTMF Encoder The CPU IC8 is equipped with an internal DTMF encoder The DTMF signalis output from pin 8 through 5 BENISON FB 388 C60 and through the microphone amplifier IC2 and is sent to the varicap of the VCO for modulation At the same time the monitoring tone passes through the AF circuit and is output form the speaker 4 CTCSS Encoder The IC3 is equipped with an internal tone encoder The tone signal 67 0 to 254 3Hz is output from pin 18 of the IC3 to the varicap D29 of the VCO for modulation 5 CTCSS Decoder The voice band of the AF output signal from pin 9 of IC 14 is cut by sharp active filter IC3 and amplified The input signal is compared with the programmed tone frequency code in the CPU The squelch will open when they match BENISON FB 388 ADJUSTMENT PROCEDURES Note It is assumed that the unit is supplied with a regulated 8 0 volts during the adjustment procedure Do not us
13. by the buffer Q31 Q34 and input to pin6 or pin11 of IC13 Each programmable divider in IC13 divides the frequency of the input signal by N according to the frequency data to generate a comparison frequency 2 PLL Loop Filter Circuit If a phase difference is found in the phase comparison between the reference frequency and VCO output frequency the charge pump output pin8 pin9 of IC13 generates a pulse signal which is converted to DC voltage by the PLL loop filter and input to the varicap of the VCO unit for oscillation frequency control 3 VCO Circuit A PLL circuit provides stable oscillation of the transmit frequency and receive 1st frequency The PLL output compares the phase of the divided VCO frequency to the reference frequency The PLL output frequency is controlled by the divided ratio N data of a programmable divider The PLL circuit contains the VCO circuit Q25 Q30 The oscillated signal is amplified at the buffer amplifiers Q34 Q31 and then applied to the PLL IC 1 13 The PLL IC contains a prescaler programmable counter programmable divider and phase detector etc The entered signal is divided at the prescaler and programmable counter section by the N data ratio from the CPU The divided signal is detected on phase at the phase detector using the reference frequency If the oscillated signal drifts its phase changes from that of the reference frequency causing a lock voltage change to compensate for the drift in the oscill
14. distortion with an 8 ohmldad All stated specifications are subject to change without notice or obligation 50 CTCSS TONES SQ Hz TONE TONE TONE 203 5 206 5 210 7 218 1 DE n 42 43 44 46 47 48 49 0 100 0 141 3 103 5 146 2 5 i 2 2 gt x 2 2 gt BENISON FB 388 CONTROL AND CONNECTIONS BENISON CONTROL DIAL VOLUME CONTROL POWER SWITCH PTT BUTTON INTERNAL MICROPHONE FUNCTION BUTTON SQL BUTTON KEY PAD FUNCTION DISPLAY MIC JACK SP JACK INTERNAL SPEAKER ANTENNA TX INDICATOR BENISON FB 388 CIRCUIT DESCRIPTION 1 Receiver System The receiver system is a double superheterodyne system with a 38 85MHz first IF and a 450kHz second IF 1 Front End The received signal at any frequency in the 144 0000MHz to 145 9875MHz range is passed through the low pass filter 139 L38 137 C159 C158 C122 C157 C121 C156 and C154 and tuning circuit L19 and C203 and amplified by the RF amplifier Q29 The signal from Q29 is then passed through the tuning circuit L28 L27 L26 and converted into 38 85MHz by the mixer Q28 The local signal from the VCO is passed through the buffer Q34 and supplied to the source of the mixer Q28 The radio uses the lower side of the superheterodyne system 2 IF Circuit The mixer mixes the received signal with the local signal to obtain the sum of and difference between them The crystal filter FL3 FL2 selects 38 850MHz fre
15. e a metal screw driver to adjust the ferrite cores as it causes variations in the inductance whilst adjustments are being performed Use of the wrong size trimming tools can cause damage to the cores A plastic or ceramic trimming tool is recommended ADJUSTMENT 1 Required Test Equipment The following items are required to adjust radio parameters 1 Regulated power supply Supply voltage 5 14V DC Current 3A or more 2 Digital multimeter Voltage range FS Approx 20V Current 10A or more Input resistance High impedance 3 Oscilloscope Measurable frequency Audio frequency 4 Audio dummy load Impedance 8 ohm Dissipation 1W or more Jack 3 5mm 5 SSG Output frequency 200MHz or more Output level 20dBu 0 1uV 120dBu 1V Modulation FM 6 Spectrum Analyzer Measuring range Up to 2GHz or more 7 Power meter Measurable frequency Up to 200MHz Impedance 50 unbalanced Measuring range 0 1W 10W 8 Audio volmeter Measurable frequency Up to 100kHz Sensitivity 1mV to 10V 9 Audio generator Output frequency 67Hz to 10kHz Output impedance 600 unbalanced 10 Distortion meter SINAD meter Measurable frequency 1 2 Input level Up to 40dB Distortion 1 100 BENISON FB 388 11 Frequency counter Measurable frequency Up to 200MHz Measurable stability Approx 0 1ppm 12 Linear detector Measurable frequency Up to 200MHz Characteristics Flat CN 60dB or more Note Standard modulation 1kHz 2 5kHz
16. ly check that all connectors are in a good condition Check that the power supply voltage IC 5 of the receiver circuit is approximately 4 5 5 0V 3 If the correct gain is measured then check that the bias of Q25 or Q30 is Vs 1V and Vd 4 2V Check the signal level at the collector of 1 Q34 the local oscillator output the signal level should be around 10dBm and the spectrum purity should be good TRANSMIT CIRCUIT 1 Carefully check that all connectors are in good condition and check that the power supply voltage is correct 2 Using the frequency counter to check that the operating frequency is correct If not check whether the PLL is locked If the PLL is unlocked check the local oscillator circuit If the PLL is locked check that the RF output is correct If not check from Q31 Q32 Q33 Q35 Q27 Q26 stage by stage to assure that the signal levels are correct First check the bias voltage of each stage and then try to find any voltages which are out of tolerance VOLTAGE REGULATION CIRCUIT Apply 8 0 volts to the power input jack Measure the collector voltage of IC5 The normal value should be approximately 5 0 volts The voltage at the collector of IC5 should hold are approximately 5 0 volts AUDIO OUTPUT 1 Connect a signal generator set to the required frequency at an output level of 1mV deviated with a 1kHz tone and 1 5kHz deviation to the antenna socket Connect a probe to pin 9 the output pin of IC14 If the transceiver
17. n no plug is connected to the jack 5 Squelch Circuit A squelch circuit cuts out AF signals when no RF signals are received By detecting noise components in the AF signals A portion of the AF signals from the FM IF IC IC 14 pin 9 are applied to the squelch switches Q19 20 21 22 the active filter section IC 14 pin 8 where noise components are amplified and detected with an internal noise detector The active filter section amplifies noise components The filtered signals are rectified at the noise detector section and converted into SQI signals at the noise comparator section The SQI signal is applied to the CPU IC8 pin 22 The CPU detects the receiving signal and outputs an AFB signal from pin 39 This signal controls the mute switch Q16 to cut the AF signal line 2 Transmitter System 1 MICROPHONE AMPLIFIER CIRCUIT The microphone amplifier circuit amplifies audio signals with 6 dB octave pre emphasis characteristics from the microphone to a level needed for the modulation circuit The AF signals from the microphone are applied to the microphone amplifier circuit IC2C pin 2 The amplified AF signals are passed through the low pass filter circuit IC 1B pins 5 6 The filtered AF signals are applied to the modulator circuit after being passed through the modulation circuit BENISON FB 388 2 MODULATION CIRCUIT The modulation circuit modulates the VCO oscillating signal RF signal using the microphone audio
18. quency from the results and eliminates the signals of the unwanted frequencies The first IF amplifier Q17 then amplifies the signal of the selected frequency 3 Demodulator Circuit After the signal is amplified by the first IF amplifier Q36 it is input to pin 16 of the demodulator IC 14 The second local signal of 38 4MHz which is oscillated by the internal oscillation circuit in IC14 and crystal X6 Then these two signals are mixed by the internal mixer in IC14 and the result is converted into the second IF signal with a frequency of 450kHz The second IF signal is output from pin of IC 14 to the ceramic filter FL1 where the unwanted frequency band of that signal is eliminated and the resulting signal is sent back to the IC14 through pins 5 The second IF signal input via pin 5 is demodulated by the internal limiter amplifier and quadrature detection circuit in IC14 and output as an audio signal through pin 9 4 Audio Circuit AF signals from the FM IF IC IC 14 pin 9 via the AF filter circuit IC3 pins 12 13 The output signals from pin 14 are applied to the mute switch Q16 are applied to the AF power amplifier IC9 pin 4 after being passed through the VOL control W2 The applied AF signals are amplified at the AF power amplifier circuit IC 1 pin 4 to obtain the specified audio level The amplified AF signals output from pin 10 are applied to the internal speaker SP1 as the SP signal via the SP J jack whe
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