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JS-170FR-xx Service Manual

1. ad 54944444 ee TERI 295 mus i aki i E Bir d i H jl Ji i s jd d 58 85 ee 0 00 0 0 90 0 0 00 00 90 00 0 QU 00 00 00 00 QU 00 0 QU 90 00 00 QU OQ 00 00 00 00 ii INURE agi Hdd HuddH 4 17 4 2 2 MB Parts Location 000000000 000000000 XXX XXX 1 AARATI SELL 4 18 4 2 3 Replacement Parts List Note When ordering replacement parts indecate Part No and Name of Parts RTL mark in Remarks means Repairable PCB Assembly Retention Time Limited RetNo Part 8 Description Ps set Remarks 69 MBPCB 502 R 503 ERDS2TJ272T CARBONFILM RESESTOR 503 ERDS2TJ101 CARBON FILM RESISTOR NN WEB SERE R 504 507 ERDs2TJ223 CARBON FILM RESISTOR Pa E RA 501 C 501 502 CN 502 CN 503 012200000021 RESISTOR RESISTOR R32F104ZF01 CERAMIC CAPACITOR 5 __ 00017
2. LSB MBS KB CLK KBDCK 0 0 1 1 1 0 0 0 0 1 Start bit Key code Odd numbered Start bit ACK 1 parity When Key is released Break Scan code F01C KB DATA KB CLK 58 0000011111 1 0001110000 1 Start bit Key code Key code FC 1C 2 24 2 1 5 6 5 2 mouse controller circuit The IT8673F is used for PS 2 mouse control This IT8673F also functions as a keyboard controller and is accordingly used in common with the PS 2 mouse The IT8673F internally converts the serial data sent from the PS 2 mouse into parallel data and performs interrupt operation to inform the CPU of the entry of a mouse input Since the connector is used in common with the keyboard it is necessary to use a converter connector when a PS 2 mouse is connected PS 2 MOUSE IT8673F 10K TR CN K B S5 GMD KBCLK r 5o KB CLK MSDATA r 10 KB DATA 20 MS DATA 86 82 1 5V 8 A20GATE lt 86 20 TL UN2212 E 81 Ln 777 MINI DIN KBDATA ot 83 RCIN OKRST E 1952212 1 1 746 10 10 746 2212 0100559 105 e 2 25
3. 5 USB low speed jig Series A plug Resistance 1 5kW 1 2 3 4 USB high speed jig Series A plug Resistance 1 5kW Mouse testing jig 6 pin mini DIN connector male 6 pin mini DIN connector female keyboard side on A j N 6 pin mini DIN connector female mouse side oJ A oj 3 49 41 4 1 1 JS 170FR PCB s Main PCB Main PCB Schematic Diagram 1 10 on RaZ GTLREF 1 2401 5 3 1 s Raga Ic PAXISI9HEE 31 AIF 2131 ai Hron 2163 2200p 3 200 CORE ge ADDRESS 0011000t ape tan 73 T avro RA IO LSK LSK x iis om ao co He mw 13 is 11 INTR C ios 3 1415 is 32 sra 25 gt 31 sne 2s ss ts mH 10 Not Mounted d ms 7 LSK aE 10 po 0 2303 100 558 xij 1K SRo Qus
4. 8 8 019 03 1018 03 Di7 03 03 HDi 03 2012 981 10 5 A flash memory of 512K x 8 bits is used for the BIOS ROM s address decoding is undertaken by the chip set The BIOS setting area is 000E0000h OOOFFFFFh or FFFFFFFFh that is the most significant area for the CPU Either address can be accessed When used as a 512K type continuous access becomes possible in the virtual memory area The flash memory is a write enabled memory that requires command control by software when writing The BIOS ROM data bus is connected to the X bus since ROM s fan out is small It is then connected to the system data bus SD bus via the buffer HCT245 Since this system uses the shadow memory method the contents of ROM are written in the main memory when the BIOS is started After the system has been started the CPU disconnects the ROM and works with the RAM The shadow memory method is effective to raise the processing speed by performing system s operation with the RAM the access speed of which is higher than that of the ROM It is possible to separate the programs that are not required in other cases than system start As a result the work area can be expanded 3267283 SAHID 3 lt E 1C Socket MBM2SF 040 03209308 50 0 7 35 O
5. No B side A side 42 SERR GND 43 3 3V PAR 44 1 AD 15 45 AD 14 3 3V 46 GND AD 13 47 AD 12 AD 11 48 AD 10 GND 49 GND AD 09 50 KEY KEY 51 KEY KEY 52 AD 08 0 53 AD 07 3 3V 54 3 3V AD 06 55 AD 05 AD 04 56 AD 03 GND 57 GND AD 02 58 AD 01 AD 00 59 5V I O 5V I O 60 ACK64 REQ64 61 5V 5V 62 5V 5V 44pin Flat cable connector 2 0mm pitch No IN OUT Signal 1 IN IDERST 2 GND 3 IN OUT DATA7 4 IN OUT 5 IN OUT DATA6 6 IN OUT 9 7 IN OUT 5 8 IN OUT DATA10 9 IN OUT DATA4 10 IN OUT DATA11 11 IN OUT 12 IN OUT DATA12 13 IN OUT DATA2 14 IN OUT DATA13 15 IN OUT DATA1 16 IN OUT DATA14 17 IN OUT DATAO 18 IN OUT DATA15 19 GND 20 IN OUT Signal 21 OUT DMARQ 22 GND 23 IN IOW 24 GND 25 IN IOR 26 GND 27 OUT IORDY 28 IN CSEL 29 IN DMACK 30 GND 31 OUT INTRQ 32 33 DA1 34 IN MASTER SLAVE 35 IN DAO 36 IN DA2 37 IN CS1 38 IN CS3 39 OUT DASP 40 GND 41 5V 42 5V 43 GND 44 Dip Switches and Jumpers Dip Switch 1 6 Bit Explanation Model identification bit On 0 for I O 324H bit5 Off 1 for I O 324H bit5 Factory setting Extended I O por
6. CoM3RXDF 3 COM3DSRF RX nm ES ona TxOF 55 CONICTS COH3DTRF aso o 5 7 THIIRSLSS 2 2K by 5 8 5 0221080 592 EE a 71 21 71 71 71 73 71 81 71 C7 71 21 RAG RAG on 412 cigs E i i 1 1 Deco DRVO SOMERS gt gt me FDDIR EUH SiO gt gt KRPRTI MESE lt HEADSEL F DD 52629 2611 x 8 COMIRIF COMIDTRF COMICTSF Coni TxOF COMIRTSF CoMIRXDF COMIDSRF COMICOF FLPTSTB FLPTAF DE FLPTDO FLPTERR FLPTDL FLPTINITS FLPTD FLPTSLING FLPTO3 GND FLPTD4 GNO FLPTDZ GND GND FLPTBUSY GND FLPTPE FLPTSLCT GND CON DTRF COM2CTSF COM2TXDF COM2RTSF COM2RXDF Con2 DSRF 0 0 5 NC COPS DOM EBTI dp COMe MAG SW 73 MG_CARDINI MG CARDINI BLMI18750 1 2 BUMI1B750 3 73 CARDIN MG CARDIN BLI 18759 42 72 TIMING dS nem 73 HG DATa2 4 es
7. SCREW _______ 45 xs TERMINAL SCREW WIWASHER pe rae TERMINAL SCREW WASHER fo f Jo f Ja A a 5 7 _____ RetNo PartName amp Description _ Ps set _ Remarks 4 vueaseses4 pustprotector 2 48 v2 5814084 INSULATOR yssecs125084 LockpLate staintecs 3 o Z o 1246941082 1 1 585 vuskazasB2 psPLavCAsE oO o Sal ves ____ s8 amp ____ _ 1 O Z 5859 vuzses 84 caumotaeEL vuzrsesoB4 Pt vueesseos YJJUX2983083 HING STAY YJJUX29840B3 HING STAY 8 amp 6 7 ToucHpaneLunitT 66 xsBerc 15 66 xvwsrerx reRMNALscREWWWAsHERSTEEL 3 amp vaemsesos MacwETICsHED 1 o ________ ___________ 5
8. 2 33 2 1 7 3 Back Lite control te dee e dad pne eee ep 2 34 ORT Interface ote ete et etr iat etus 2 35 2 1 8 Piezoelectric buzzer circuit 2 36 2 1 9 Hardware reset aie ieee ee eee ne eee 2 37 xd 2 38 2 15 41 CPU POWER PP enl eee ete ed e 2 39 2 1 12 ETHERNET interface circuit 2 40 21 13 Touch panel interface circuit iat d ee eet eed ted eed et erts 2 41 2 1 14 Magnetic card reader interface circuit 2 42 2 1 15 Cash Drawer interface circuit 2 45 2 1 46 Customer display interface 2 46 2 1 17 Power ON OFF 2 47 ON A E 2 47 21 11 22 Power EE iin eeu Wt eh ie eee Me 2 48 2 1 17 3 Battery backup circuit 2 49 2 1 18 GATEARRAY uPD65884GM 019 BED Refer to the 4 8 2 51 2 1 18 1 Internal f rictlOris 2 5 dere ee ded ER d re gente 2 51 2 1 18 2 GATEARRAY Pin Assignment 2 51 2 1 19 Optional interface Refer to the page 4 5 2 54 3 Test Program and Power Supply 3 1 3
9. Warning 1 33 kckckckckckckckckckckck kk Reserved cylinder for DIAGNOSTICS will lose its data Reserved cylinder number 787 or 645 KKK KK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK Hard DISK CONTROLLER Test OK Hard DISK SEEK Test OK Hard DISK Read Write Test OK Reading Cylinder 787 or 645 Head 127 or 239 Sector 63 Sector count 1 When 3 25 GB Test done Press any key F1 STOP CONTINUI F2 STOP F1 STOP CONTINUI 2 5 2 Confirm in the middle of testing that the front LED for HDD blinks in green 3 Finish the test after displaying OK for all the diagnostic items 4 Press any key to obtain a menu screen for the diagnostic program 3 15 6 Video test 1 Enter 6 ENTER through the keyboard LCD DISPLAY TEST 4 6 Video Test Return to MAIN MANU Display Test VRAM Test Select and press E 6 1 Display test 1 2 3 Enter 1 through the keyboard Confirm that the back lite is turned ON OFF three times Since an all white screen is displayed confirm the freedom from any problem such as dot missing and error display If the result is OK press the 1 key In case of press the 2 key LCD DISPLAY TEST 4 6 Video Test ER 1 OK or2 NG Since an all black screen is displayed confir
10. 2 2 2 1 1 CPU PENTIUM II 266MHz or 333MHz Refer to the page 4 1 2 2 2 1 2 Chip set FW82443BX FW82371EB Refer to the page 4 1 and page 4 3 2 2 2 1 2 1 FW82371EB Pin Assignment 2 3 2 1 2 2 Real Time Clock 2 9 2 1 2 3 interface hn tie ect nat eee Nn enti e reet ep 2 10 21 24 5 eee eei EN 2 12 2 1 3 Main eile oe ov ee 2 13 214 JBIOS iue t boi be iei NIE aite teu e Ee ep ed 2 14 2 1 5 co ES Cei 2 15 2 1 5 1 T8673F Pin Assignments ue eie terere Ene e 2 16 2 1 5 2 2 ten bp eic e n Lieben beer eon pre eee ed eda 2 18 2 1 5 3 Parallel port interface circuit 2 20 2 1 5 4 FDD interface clreult e iex ree nt ee Ee uet Ee x uen A vd 2 21 2 1 5 5 Keyboard controller Circuit RR ARR ERE 2 23 2 1 5 6 PS 2 mouse controller 2 25 2 1 6 Serial pot COMI 4 eta 2 26 2 1 7 circuit Refer to page 4 4 2 28 2 1 7 1 SM710 Pin Assignmerit z uinea e eb eter hd eee 2 29 2 1 7 2 LCD interface circuit Refer to the page 4 4
11. 504 00039 CONNECTOR a P 501 502 IMSA9215HGF SOCKET YJ9210B102GF PLUG _ 2 501 00007 EN _______ ______ CABLE 4 19 4 3 Peripheral 4 3 1 Peripheral Schematic Diagram MAG SW MCR CN601 CN602 ST x6 JPK17200B3 A 1 1 1 1 CARDINI i TIMINGS TIMING 1 Mag i CONNECT CARDING CARD IN2 1 1 TIMING2 TIMING2 1 MG DATA2 5 200 200 1 BUZZER FG 5 1 RESETSW IN Esq E F1E 1H1044056 2501 APE132F 104250046 124100 2840 JPIK17200B3 B so SWITCH Buzzer OSKHHLN 2 MCN 1602 SKHFEN LODCFA000003 m DE 1552 PKM33EP 1001 1 LCD BRIGHT 502120000001 1 1 dur S502 1 Volume STN 71 1 104 056 1 RPE 1326 104750001 12N100 PB40 SPPJO EN PLB p d oa AC SWITCH 1 1 TPEO1 wee 2 79 ts 1 0 1 C ___ Zo 1 22 EVLHFKA05853 2 22727 1 Vo 1 1 LED 1 51 K1KA07800027 05551 05553 78 5 LN170WP28 _ 1704238
12. 02A 9 Not implemented O1D O1D O1D 01D 10 IDE interface buffer 215 23 not Q1D cl Q1D implemented 11 LAN LSI driver LSI manufacturer uu oll mmm boum oum o software version up demand 12 disk enhanced From 3 25 GBto5 GB O1F om o Q1F o 13 LAN driver software Software modified eem Q1J m 14 Lower case modified Battery replacement a 1 simplified 15 Lowercase modified Rubber foot frame ____ pope cope 2 2 reinforced Model Number Modification Description F22 F23 F24 F25 20 21 22 23 24 25 W20 W21 W22 W23 W24 W25 24 25 lt n n ou ou imbedded 2 Resistor R430 added 10 added O1A um o ou o o 3 Constant From 1 2 kilo ohms to _ a R181 modified 750 ohms 4 DIMM e
13. co 1 Low 1 1 1 1 t b 1 n 3 Press any key to obtain a menu screen for the diagnostic program Pattern 1 Pattern 2 Pattern 3 Pattern 4 Pattern 5 E E E E E E E E E E E E E E E 1111 E E NH E E E E Note The Customer Display is not mounted on the JS 170FR 21 E G A W U S F C Therefore this test shall be carried out only in the case of PWB inspection 3 28 12 Touch Panel test 1 Enter 11 ENTER through the keyboard LCD DISPLAY EST 11 Touch Panel Test 0 Return to MAIN MANU 1 CALIBRATION 2 TOUCH TEST Select and press E 12 1 Touch panel calibration 1 Enter 1 through the keyboard to perform the calibration test LCD DISPLAY 2 3 Touch the center of each mark 9 points to perform calibration The mark disappears from the screen when it is touched If it is necessary to stop the testing work as a result of touching a wrong point by mistake during calibration touch all the nine points to withdraw from the calib
14. see oe Se e 4 6266 10K 81 RMSRSTE 12 31 PIIX4 PHROK 3 DERESETM3 PLIX4 102 PuRGOOD VRMPGD D RESETE 7 81 3 3 P rivis 13 12 133 3 1039 6 32662 RESETDRV 3 gt cess 680 CORE lee cos Tes je 1 deut cua cus 2 0 Too 9 0lu T 90 pee To 3 cezo dens cus cars 6225 9 0 To 01u To otu To otu To otu 16 12V 250 HK 15007 He 4 10 5 15V 6284 C283 C286 4 L Not Mounted C101 58 039 429 1 2 T t8 AC ON 038 152 EL ul 10 001 80748AN JC TL T 2 uw our Lt Ferl 8 _ gt C10 PWRGOOD lt cel BATT Cj 102 PS gt 5158 caos caos co cs B348 PHDSS 12 CN26 From PSU 5458 R261 EX 8258 10K A MALSE 13038 8377 81 PWR 5 58 R262 MK esvsp 102 0 seo
15. 150011000980 20 Front Counter Register JS 170FR 2001 Matsusita Communication Industrial Co Ltd All right reserved Unauthorized copying distribution is a violation of law NWARNING This service information is designed for experienced repair technicians only and is not designed for use by the general public It does not contain warnings or cautions to advise non technical should be potential dangers in attempting to service a product Products powered by electricity should be serviced or repaired only by experienced professional technicians Any attempt to service or repair the product or products dealt with in this service information by anyone could result in serious injury or death Design and specifications are subject to change without notice Caution 1 High voltage is applied to inverter transformer cable and capacitor on the backlight PCB and backlight connector shown in Fig 1 below Do not touch those parts without switching off JS 170FR expect for probes of oscilloscope or tester for testing or repairing purpose only Fig 1 Do not touch the parts within this spot without switching off JS 170FR Backlight PCB Assy 2 High voltage 230 V DC is applied to heat sink indicated by arrow on Power Supply PCB Unit shown in the Figure below Do not touch this part without switching off JS 170FR Do not touch the parts within this spot
16. YJM20MDI0BA CUSTOMERDISPLAY __ 1 o vMzR 232121 coNECTOR o o 1 1 2401 00020 1 vMp234084 __ 1 y O ________ 2 vpK239084 Po 15 vao y O 1 vwMsreex ass TERMNALSCREWSTEL 4 o oO xsB3s amp FC TERMNALSCREWSTEL 8 o Z o 1t TERMNALSCREWSTEL 5 Oo O _____ xwcaa XYN3 F6 TERMNALSCREWWWASHER 30 ______ 20 1 TERMNALSCREWWWASHER 1 21 vArcst tBA PACKNG 22 YJ2P5109084 NSULATORPOLYCARBONATE 1 spacer ____ 2 vJJux30812283 BASEFRAMEASSY 1 21 YJ2758230888 MOUNTNGBRACKET 1 26 001205825084 J LOCKPLATE STANLESS a o oO 27 vso 1 ______ 28 vszo y O 29 vX25582808 30 vso 31 soo oO _ 32 CORD CLAMPER 1 YJNKAN Jal a wsoss stay _________ gt we 0 HEATPIPEASSY _______ 49 0 242 TERMINALSCREWSTEEL __ TERMINALSCREWSSTEEL
17. 9 THE 8 aee ae ra 12 DIN lt MG 9 10108121 RESET r E C9 5 EE LETT OM Not Mounted MAR 15v Fa we nan AGER 5104 KBDDATA m 5 P097 Dos Lew w 8500605 Haa a TP RXD 5 Qo 81 81 mom am te 33 Teas ut t8 Tees E a ni z 77 LAM z 16K C139 LCs 152 feist 150 C149 1800 18002 s n lae Ap T m 015 DTCI23YK BLMI1B750 80118750 gt TP 8 TP D Ec 5118750 5 844118750 8 119750 878 5 Ok 93 91 Touch Panel CONNECT 73 71 KB DATA 21 MS DATA 23 118750 TCS7567 01 401 Cut 21 16 4 ew 9 0 050 Not Mounied 4 1 1 Schematic Diagram 8 10 21631 gatos 30 71131
18. R100 1K 22 REINE 71 R20GATE mso cd woa e 890 N R32 10K ees 103 PIIX4 gt ox 0302 OSCP4 03 gt M Ce PCLKP4 03 gt ax av 8136 100K RU tna 822 cong 229 Lo 32 768KHz e 22 i HE aus C46 100 i 0 lu 1 man Ip QR K eas 1 Jn Wi 6800 lu mee qv 7 04 T 1 1 1 PIIX4E 324BGA FW8237 1EBSL3 M 97700000003 1 03135 dues LE 8233 803035 ci 3 8029 35 16213 AD 35 wares 15203 AD 35 18193 ADS 35 18183 80535 213 LAT 3 809435 pl 1 2023 35 nn 022 35 9 ML 218 3 8021 35 tj gd 17_3 9020 33 8 s 5 5215 3 ADIS IS NIE 54153 8083501 PRAET 54143 0735 Gd wirt EJER 8016 35 BJ 9015735 Eius Ir 801435 m 54193 8013 35 a T 793 8012 35 3 una we US 528 3 8011 35 TAN 11 SA 3 801035 59 pir 5 63 ADS 35 1 Lr 545 3 an 35 wl un 3 AD 35 UH SA3 80635 410 mL Sa 3 ADS 35 9 De Um Sai 3 804 35 Sao 3 803395 dy n 80235 015 38 i 35 913 35 IT 512 35 5911 35 PE
19. 2 11 17 BLH31P500 1 gt RIBS 560K 1 1 R127 T i 5 4 2 12 RAM circuit 3 3V DIMM 168 pin is used for the main RAM of this system The DIMM can mount an SDRAM or EDO type memory and the installed capacity is controlled by the software The circuit provided with the ECC parity is also available The maximum capacity of a single DIMM is 128Mbytes Therefore it is possible to increase the capacity up to 256Mbytes if two chips are used Both SDRAM and EDO can be mounted in mixture There is no discrimination in mounting positions For the EDO refreshment is controlled by the FW82443BX At every period of about 15 refreshment is carried out by the CAS before RAS system The speed used for the EDO is 60 and 10nsec for the SDRAM no IC DIMM 168P 8 AAA AAARAAAAAAAAAZAALER 3 37 2 13 8 160 03 sna 8181818 818 818 818181818 NM C MN 8 Bn i288 E 8 1 043 03 03 039 03 5038 03 03 5035 03 034 03 03 030 03 03 2222322 x x E 3588858
20. 33 25 5 5 si X RA 10K 31 20 25 J 1 25 C3 1 250 31 C1 CRESET 3308 ELJFC330KF 100 Eg CINTRO NMI 834 835 1836 832 256 62 Mounted 3090 33 Net Mounted owned SESMHz Not Mounted Nol Mounted Nounled 400 Monti Mounted 33HMHz Mounted __ Not Mounted Nol Mounted i T HRESETO C 2 3 9 2 Dx 2 um og 5 m iu cp ue P C reste b Li gt 5 b ij Tc EI PRDYAO i R27 6802 5 el 4 b 2 5 G el x p D 104068 3 6 7 240 gt C102 8 ou i 613 as e Em 15 xt x 2 11 5 22 RI t us A 5 I 23 813 amp 2 z z 8 8388888583888888888888888888888888888888888888888888888888888883888888888858888588888888888888 3 5 P2MOBILE_266 333 agau i E i C300 120
21. D Er o 35 ion a GAB R m PC 35 au n ae De a d Moa 5 amp LIE 500 2 4 gm 5 5K gm M e ae 01065 OR ert J gl 48 902 e a m as mas T T cS m HE Diu i i E 1 i wr LS IDSEL AD REQ REQ2 GNT2 2 40 2 1 13 Touch panel interface circuit RXD4 TXD4 DCD4 DTR4 DSR4 RTS4 CTS4 This system uses a touch panel of the resistance film type Control of the touch panel is effected by COMA of the serial port Where the touch panel is pressed the signal is analyzed by the one chip CPU N0100559V105 and sent to The transfer Baud rate is 9600bps The operation mode is modified through switch setting For SW ON P06 terminal Low Operation conforming to the Panasonic Specification DOS For SW OFF P06 terminal High Operation conforming to Windows 5V UU ow prA123Y DTC123Y ii scade d ae
22. 3V RAJI RAJZ RAIL 8 2K 9 2 8 2K 4 4 1 1 PCB Schematic Diagram 2 10 C12 MECCC 0 C11 mp3 03 C13 9 11 12 3 0810 13 3 0 3 CS 4 3 0 6 89 3 0 1 03 0 3 ay 858 MARGE 3 857 3 123 DIMM CIS8P 0 63 0 03 09 8 7 0 3 063 03 Ics DIMMCIS8 P 3 161 063 03 31s 03 __ 129 3 ERN mh us nez 3 A i i Pe Koi te MIENNE Signal Funct ion High Low NEUEN mns D3 regis 1 31 A Buffer Made Toore Besktop 1477 03 MIT NNNM NN NAA FAB Tristes Norma Nome he E ost 09 xj er p ms BINE 1 2 Start Quick Start Stoe Clock mn 1 MIENNE Deo 4 __ ____ ir A n mss 9 ew 52 5 A m wis SER mae 3 is A x NE 03 NICTENE IMBRE HABLA
23. POWER OFF 620243 57 254 T 10K 101 REM SO 51 LAN WAKEUP Olu 033 i 9 3 2 5 Parts Location 41 2 ic M fa fa etel 9 Tel a iO Og PONE o o o o 90900 a al dat OO 0 4 11 E uns me 00000 o 5 MB Schematic Diagram MB PCB 4 2 4 2 1 58 i in 2 So Labs Lo Go ls Las la Co la La la l la la la lo 4 LL TIT 8 i BER B de 3334 e gd 48 2988 2000 438 0000 0 00 000 0000 00 00 00 00 00 0000 0000 000 gu igi og TETEN d TE Bos iow 55 Sez i SER 2 71 k 5 TETTE TEES EET EE Pe 4925 DODA lt gt 404 35 lt gt 403 35 lt gt 202 35 lt gt 401 35 lt gt
24. 1 2 LOPPY DISK Controller Test OK HD MEDIA IN 1 44 FDD Test OK LOPPY DISK DRIVE 1 44MFD Test OK Test done Press any key F2 STOP MENU F1 STOP CONTINU TY EST RUN 1 5 CONTINUE F2 STOP MENU gt MEME DA A Finish the test after displaying OK for all the diagnostic items Set a 3 5 2HD work diskette write disabled in the FDD Enter 4 ENTER through the keyboard Press the F1 key to start the test LCD DISPLAY TEST 4 4 Floppy Disk Test Insert a 2HD disk into the Drive KKK ck ck ck kk kk KKK Warning 111 KKK KKK KKK KKK KK CONTENTS OF WILL BE DESTROYED KKKK KK KKK KKK KKK KK KKK KKK KKK KKK KK KKK KKK KKK KKK T 1 CONTINUE F2 MENU LOPPY DISK Controller Test HD MEDIA 1 44 FDD Test ormatting Cylinder 0 Head 0 Sector 1 Secyor count 18 03 Write Protected LOPPY DISK DRIVE 1 44MFD Test OK est done Press any key F1 STOP CONTINUI Dd F2 STOP MENU H EST RUN 1 5 CONTINUE F2 STOP MENU 10 Finish the test after displaying 03 Write Protected 11 Press any key to obtain a menu screen for the diagnostic program 3 14 5 Hard Disk test 1 Enter 5 ENTER through the keyboard LCD DISPLAY TEST 5 Hard Disk Test
25. Circuit and Track Magnetic Swipe Reader bit6 5 is Off Off Circuit 1 expects JIS II Japan circuit 2 expects 1502 JIS I track2 Japan bit6 5 is Off On Circuit 1 expects ISO1 JIS I track1 Japan circuit 2 expects JIS II bit6 5 is On Off Circuit 1 expects ISO2 circuit 2 expects 1501 bit6 5 is On On Circuit 1 expects 1501 circuit 2 expects 1502 Combination of these bits tells circuit to decode specified track data For example circuit 1 decodes only ISO1 and circuit 2 decodes only ISO2 if bit 6 5 is On On If ISO2 data is input to circuit 1 it is treated as an error Dip Switch 2 8 1 Bit Explanation 1 Address control for extended I O On Software can enable disable access to extended I O ports Factory setting Off Extended is always enabled When this bit is set to On software can enable disable access to extended I O ports 320H 32DH by output data to 32FH Setting this bit to Off always enables access to extended Software can t disable access to extended I O through 32FH System initializes hardware to disabling extended if this bit is set to On But BIOS setup finally determines initial state of accessibility enable or disable 2 Reserved for future Off Factory setting Extended I O 32DH bit5 reflects to this setting This bit is reserved for future enhancements and any functions are not currently assigned to thi
26. Power consumption Approx 60W Frequency 50 60 Hz Connectors No Interface Number Connector type 1 Serial 3 1 2 D sub connector male CONS modular connector NOTE is shared with Customer Display interface It is possible to switch between Customer Display and External port by software 2 Cash Drawer 1 6pin DIN connector female 3 Parallel 1 25pin D SUB connector female 4 Video 1 15pin D SUB connector female VGA 5 LAN 1 8 pin Modular Jack RJ 45 6 USB 2 USB Connector 7 Keyboard 1 6pin mini DIN connector 8 Floppy Disk 1 26pin mini I O connector See Appendix for pin assignments of each connector 1 4 Operation Condition Temperature 5 40 C 41 F 104 F Humidity 20 RH 85 RH no dew Dimension and Weight Width 250 mm 9 8 inches Crew display 312mm Depth 320 mm 12 6 inches Height 365 mm 14 4 inches with rubber foot Weight Approx 10 kg Tilt angle Material Case body Stainless steel sheet Top cover ABS Supported OS Microsoft MS DOS Windows 95 Windows NT Workstation 4 0 Accessory AC cable 1pc 2 5m Safety Standard Safety Standard T V UL aus FCC Part15 Class A CISPR Class B CE C tick 1 5 5 Same with the area of 00020000 to OOOFFFFF FFFC0000
27. 0 51 16 RES lt gt POLKSLOT2 03 51 PCIAK 510 71 54 S vex 5 5 1 D he x e eub i um ep eps D pre pxRIXE 7 ke Leis Ler las 45 ME me 0 01 Ip ES 4 1 1 PCB Schematic Diagram 3 10 12642652 0031 0 35 12642652 3 0 35 41 3o 13 INT 3 RASS 1264205 tEvstLe 35 lt gt 1264165 FRAMES 35 12642652 12042053 35 12642052 _35 gt 12642653 TRDY4 35 lt gt 12051 SERRES 13051 L0ck 35 12642052 RST4 35 lt 11205 17052 12652 12243 030350 51 PCIINTAS 35 51 35 51 36 43652 0 35 C11 0 25 gt 4 CLJ CIJ mmo IPSIS MIS 2 Tu o cup I ENSEM I 13 Ee a TEREST TY pm 11 5 3 582452 nl 31 USBPI SO M 58 0 5 232 USBPQ 5 31 1 5 gt Rda C3 05306085 gt Idas M ONC t3 m TOLOS 101 24 3 c hut Down R nason ad asea zo mj E 0 12
28. D wm 1 1 5V EE EE d PS A i 2 i 1 DTA123Y DTC123Y 1 777 1 poo 24 1 T f 1 i 1 4 1 1 1777 sw DTA123Y 48 f o o x E A 43 pog P02 22 E 45 5V 77 22 10K 58 44 1K E gt 1 001 P05 A ps2 un ANO lt FL E 560p 0 01u lt lt d 2 FL tH asso ant 5 O 10K lt 53 AN2 122 i 10K 52 P36 PWC 7 5 FL NAT 91 pari w TO E peti 4 FL O 28 4 5 1800p 1800 1555 1800 FL B 6 89635 010 0559 V105 es i AA 4 7 FL 1 2 41 2 1 14 Magnetic card reader interface circuit A magnetic card controller is accommodated in this system in order to enable readout operation for the magnetic card according to the Second Track Specification 5 bits 40 digits recording density 75 of the 1507810 Standard When the serial data input from the magnetic card are identified and correctly read out all the data start code end code check byte etc read from the serial data are converted into the scan codes of the AT keyboard and are transmitted to the keyboard c
29. EX TROY 35 eve eS DEVSELS 35 35 STOPS 35 R258 10 v CRST LOCKE 35 53 R383 0 35 8330 5 9 ERA 35 100 55 IDSEL AD15 REQ REQO GNT 0 858 5 12 CGNDJ 4 C 12v C 12v 1 9 5 5 52 9 CINTA CINTS CINTC 2 Reserve 84 Reserve 6 Reserve CSERIROJ g Reservel CGND1 CCLK03 CCLKI3 CGND 4 CGNT O CREQ 03 5 GNT amp 11 9 52 0 5 11 2 90303 9 93 3 3 2 0281 5 Cana 9 0261 9025 5 90241 4o 20233 3 3 3 tas 2022 84 90213 taD20 60192 1 1 1 C BE2 4 103 32 3 GND 6 CFRAME 3 CIRDY41 3 3V1 CTRDY go CDEVSEL 5 82 STOP41 CLOCK J 3 3v gs 3 3V1 8 CSERR 141 CADIS CADI4 3 3 1 20132 012 70112 CGNDJ CGNDJ CADOS 83 0 2 90021 3 3 C 3 3V 70051 CADOS 0043 CGND CGND 20021 011 20002 0 5 1 0 5 1 5 2 5 1 C Sv C Sv IDSEL AD16 REQ REQI GNT GNTI 4 1 1 Schem
30. 5 1 1 1 220 9205 7 7 _DTC123Y 2851140 820017200 1 1 1 117 FL 082 DRW2 OPN 1 1 a Sus LASSEN 5V 2 1 1 1 1 1 7774 1 1 14K 1 1 1 1 1 1 14320 02 16 AN L 2 1 1 1 5 i 1u O GND 1 5 114 DRWCNT2 6 1K 777 2 45 2 1 16 Customer display interface A fluorescent display light tube of 20 digits x 1 line or 2 lines is used as a customer display The driving voltage for the customer display is 5V the transmission data need be the serial data at the TTL level The serial data are used through the changeover of the TXD signal TTL of by the aid of software Since the TXD signal of is used also as the interface signal TXD3 OUT for the RS 232 C the above mentioned customer display cannot be used while COMS is used externally The reset signals for hardware resetting in case of Power ON and for software control are used as the reset signals for the customer display 152 gt 153 i she 1 CN CUSTOMER 2X 4 7 Le 5 1 5V 1 f outs28h 1 5 1 i AREE Bito FL 3 O RESET FL D
31. MacNETICsHED 1 Z Pw MacNETICSHED 5 _ fax ex p fo 2 23 YJJ5E42480E1 TOP COVER YJJ5E42480F1 YJJ5E42520D2 EE E2 vusE4263008 cover __ OOO manes 6 vette 77 hoo _ _______ 78 _________ _______7 cBE 0 0 0 0 1 80 ove 0 0 0 1 _______ 6 0 00 1 82 0 0 1 89 ove 0 0 0 0 1 _______ 8 ove 0 0 0 1 _______ 55 cBE 0 00 y 86 1 87 13054020184 PowERsUPLYUNT Jafo 88 _______ 89 jBATTERYCASE Jafo 90 xara TERMNALSCREWWWWASHER 2 91 jBArTERYeCOVER 1 _______ 2 __________ cUSHON 4 99 XWG3NYCA8 NLONWASHER 2 eoe screw 04 7 95 YU66550084 14 5 8 Part amp Description Ps set Remarks 96 Ys K265000B4 BATTERY CABLE
32. 0328h bit5 output pin Output Port 0328h bit6 output pin Not used OT328_D7 Output Port 0328h bit7 output pin 0328h RESET_OT Reversed output of REST IN input signal Active Low RESET COM34CSN Active Low Chip Select signal for COM3 and COM4 COM ADDRESS COMSEL Changeover signal for COM3 COM3 High COM4 Low COM ADDRESS TXD3_IN UART CONS TxD signal output pin COMTXD CONS TxD signal CUSTTXD CUSTOMER LCD Data signal CUSTOMER CUST RTN CUSTOMER LCD Reset signal Active Low 0328h WGAT OTN FDD WE control signal Active Low 2 53 FDD 2 1 19 Optional interface Refer to page 4 5 As an optional connector the system is provided with a connector intended to make connections of the PCI Peripheral Component Interconnect buses for two slots When conforming to the PCI Bus Specifications is mounted it becomes possible to have a variety of functions externally The PCI buses conform to the Board Specifications of 5V Signal name 12V Signal name GND Signal name 12V Signal name 12V GND GND 5V 5V INTA INTB INTC INTD Reserve Reserve Reserve SERIRQ Reserve GND RST CLKO GND GNTO REQO GNT1 IREQ1 2 5V 5V AD31 AD30 AD29 3 3V AD2
33. 1520 0 27 CNIG 1211337 peo 211317 me 71132 AEN 711101 71122 oH C102 022 2 amn as DER 101 ama 10K 1 ama n 2 amu A RA amu Bes Snes 101 exon BJ PCRERINTS 10 35 t8 81 532 sat Quan IEARSTA 6 AR 00917 Default OFF 5640 x 480 t10 S4 0N OFF ON 800 x 600 nas Torr 1024 x 768 e era ON ON Reserve BACKLIT ON n 41 BeCKLIT_ON z S 4 5 CUSTOMER Default 3 BACK_ON 41 FPEN 5 5 41 FP FVSYNC Default i Line Type ON 2 Type 42 jSW 3iDrauer TIME OFF OFF 217 Default OFF ON 145 OFF 108msec ON 72 SW 2 Reserve Default OFF Normal ON Reserve SA 1 POS Fort OFF ENABLE Default Software t2 d 192 lt R252 1629 35 1 2 Li 245 10 BDETO E CLON NOTO G
34. NM01 0 20 120 i ep 02041 Ml ones miii enre as Exp ROM See i omes wo LX wal wap Mone meh 808 35 914 08 int ae d mang es mi a mel an wt an so 2 a 0 17 Manes riga 55 me 0 0 2 im bri MMC 17 R372 R373 R324 3751 375 377 R378 379 8159 Not Mounted anis 3s 86038777499 mang v 72 x BUMLIPSOO Uax 09 Heed nitet Manet 1263265 35 RI70 son bibit G2X 35 1 T wa ght 5 160010212 a RI 5 DSTN Noumea Noumea o 04 s vac are 5 B14B FH x 5 gi 5 3 TFT DSIN 12032051 35 5 1000 R290 AAA 33 recone reef 12631651 570435 oc G LCDDI 8105 17031251 735 UE mort moo 5 100027 R30 Fx 39 12632651 mmn 5 1 003 8303 S FLCOD3 14 12113152 18014 35
35. Pin name 18bit TFT 16bit DSTN FDATA23 Not used Not used FDATA22 Not used Not used FDATA21 R5 Not used FDATA20 R4 Not used FDATA19 R3 UD7 FDATA18 R2 UD6 FDATA17 R1 UD5 FDATA16 RO UD4 FDATA15 Note 1 UD3 FDATA14 Note 1 UD2 FDATA13 UD1 FDATA12 UDO FDATA11 Note 1 Not used FDATA10 Note 1 Not used 9 Note 1 Not used Note 1 Not used Note 1 LD7 FDATA6 Note 1 LD6 5 105 FDATA4 LD4 FDATA3 LD3 FDATA2 LD2 FDATA1 LD1 FDATAO LDO Note 1 According to the type of the LCD panel being connected the resistor mounted on the PWB shall be changed 2 33 2 1 7 3 Back Lite control circuit A cold cathode tube is used for the back light of the LCD The 12V power supply for driving is fed from an external inverter Assuming that the LCD is in the display mode the FPEN signal at the high level ON OFF control of the power supply is effected by software This system performs controls two positions 0 Default High that is a general purpose port of the FW82371EB and Bito BACKEN that is the I O address 320H The Back Lite is turned ON when the conditions of both are satisfied Generally the control of FW82371EB is not used Instead ON OFF control is performed by managing the BACKEN signal that is used for the control of the address 320H The control hardware is located inside the gat
36. REQ O 4 9 120 dom HITM C 12 E HTRDYP C ge 5 C gt Ss 204 BREQOP 5 docx C12 lt 8 0 9 11 12 4 3 10 13 3 CS 893 Cs 882 cS CS 89 59813 3 8124 3 MABITO 3 MABIO 3 NABIH KE HAB HARES NARSA KED KED CHp 210 FW824 1 LI veo 43BX 8151513 8 con 1 A010 151 alglg M063 03 03 061 03 060 03 MDS3 03 MDS8 Di MDS 03 056 03 MDSS 03 4054 03 053 03 MDS2 03 MOST 03 MDSO 03 MD43 03 MD48 03 03 MD46 03 045 03 mD44 03 1043 03 1042 03 MD41 03 049 03 M33 03 4038 03 M03 03 035 03 1035 03 4034 03 033 03 032_03 031 03 8030 03 1023 03 03 02 03 03 4025 03 1024 03 03 03 021 03 03 MDIS 03 C MAB O 9 11 12 4 3 MABCIO 13 3 21 65_ 46 3 0 5_8 4 3 0 gt 0 63 0 03 lt gt 7 9 21 O 0 3 2 gt 0 3 cu
37. a Without switching off JS 170FR Power Supply PCB Unit Design and specifications are subject to change without notice International Pentium POS Series Models are classified according to the systems shown below JS 170FR X1 X2 Type of Specifications Country Code X1 Country Code England Germany European Australia Taiwan U S A Canda Scandinavia Canada Type of JS 170FR Specifications Specification RAM size Dip SW Customer Model No Country Cap Color Battery 0 5 MSR Other change timing MB TP MSR Display JS 170FR U20 From begin Yellow 64 Fujitsu 1 2 266 2 Not Standard 1 1 1 1 JS 170FR U22 June 2001 USA Gray 64 Fujitsu 1 2 266 2 Standard 120V 1 l 4 1 14 JS 170FR U24 September 2001 Gray 64 Fujitsu 1 2 333 2 Not Standard JS 170FR U21 From begin Yellow 64 Fujitsu 1 2 266 2 Not Standard 1 1 1 JS 170FR U23 June 2001 USA Gray 64 Fujitsu 1 2 x 266MHz Not Standard 120V 1 l 1 1 14 JS 170FR U25 September 2001 Gray 64 Fujitsu 1 2 x 333MHz Not Standard JS 170FR G20 From begin Yellow 16 00 6 22 2 266MHz Not Standard AC Cable Straight 1 1 JS 17
38. 1437 E E KM angel Pre charge 3HCLK EX SGRAM 4 9144 Not Mounted NMDS RIMS 5 K Not Mounted MIC 04 1 05 Colunn Adde Sbit SGRAM RAS to CAS 2 SHCLK EDO RAM 127802 A Pre charge 2 5MCLK EDO RAM 12632653 350 me vnos 9133 am 3 wu RED anatas rol rich BLM 18750 Ramos s w JP m x3 L40 VGND NIENTE SM 10 256BGA wae alt SEM VMDi0 0 010 1 VMOl0 0 VMDIO I Neves 35 aen GL vans 0 118750 3210820467 8404480 800x600 1024x768 1280 1024 u n 4 Rees re S PN UN ex 1 NI HE TER abit n v CONNECT 014 0 weis RIS 5 m E STO 41 CRTHSYNC O 020735 oms e verc ni RIS pa 2015 35 eb as 018 35 cae v eb RIS NN IE vidi 70 35 wise Vig Der gin 41 ACRES x ep 155 5 Rigo
39. Po j pususwrmcH 1 2 2 4 22 Body Block Disassembling Drawing Body Block T P PCB Unit 202 ON6 the Main CN26 on the Main PCB Unit on the Main PCB Unit PCB Unit on the Main 4 in PCB Unit CN22 on the Main Peripheral PCB Unit 5 1 5 Peripherals Main PCB YJ172617 1 K1U343B00001 5 2 Power Supply Peripherals 5 3 Customer Display Peripherals 5 4 LCD Peripherals yee 4 1 n TJ n 1 M ile 5 5 d HUN 99 4 1 2 3 unnm zn Tuus s NEN SSS SS 5 2 Body Block Replacement Parts List Note When ordering replacement parts indecate Part No and Name of Parts RTL mark in Remarks means Repairable PCB Assembly Retention Time Limited PartNo amp Description Ps set Remarks 158060000 LQUDCRYSTALDISPLAY vNR12C289LU BACK LIGHT a caBE o 1 __ 1 xvNs F6 TERMNALSCREWWWASHER 4 y O vuusAs80408BM4 DUSTPROTECTOR 1 vmo MMOUNTNGBRACKET 1
40. Split Cable of Keyboard and PS 2 Mouse 2 KB CLK Keyboard VDD DIN GMD MS CLK PS 2 Mouse VDD MINI DIN 4 The two 16C550 compatible serial port controllers COMA and COMB incorporated in the 165520 independently of each other With the 1 84MHz clock fixed supplied from the outside a Baud rate clock is generated This port operates in an asynchronous mode The I O addresses of these two controllers are decoded inside the gate array PC16552D address Interrupt level CAMA COM3 3220 3227h IRQ11 or IRQ3 COMB COM4 3228 322Fh IRQ10 The transmission data signal TXD3 of the is used through customer and display changeover The COM4 is used as an interface of the touch panel at the TTL level 1540 0 2 1 153 1044 mu Bla 2 1 7 4 184 35 1801 35 31 J3 9 1803 35 Hot 4 1901035 33 2 26 signal of the 165520 is processed the TTL level Therefore the ADM211 is externally used for the driver and the receiver of the RS 2332 C interface The ADM211 is an IC of 4 outputs and 5 inputs and works only with a single power supply of 5V Register frequency division Hexadecim
41. gt 17 CO 2828112 C3 3 3 gt ae 2 4 amp HZP4 1 gt PAKP D 3 D 12 gt 42 gt 3 52 OP xson m 53 gt Parot 03 53 510 123 277 75 275 19 Cis pu spese 2 38 2111 CPU POWER The LTC1735CS 1 is used as the core power supply circuit for the CPU The input power supply of 4V 15 is fed from the power unit This power unit generates a 1 6V core voltage that is to be supplied to the CPU The maximum current that can be supplied is 12A coil and core rating Other voltages needed for and related to the CPU are 1 8V and 2 5V Tos j PET 1031 10 CPU_CORE estas fi v 4 7 ant a 12A d Pn s ETOPEFIRPHFA 0 008 1 2 15 CORE N 12u12 RH ui ust an 2 foe E dc 1 08528 00 MRNA VEM Raw EX 5 g E 4 M gt lrn 20 Wy au EI 1800 HN 415V Max 128 Lu E E Ui pee oe a Re aut et
42. 44 304 42 03 41 502 40 501 39 500 78 lt 24MHz 2 1 5 1 IT8673F Pin Assignment DENSEL FDD packing density select signal High 500K 1Mbps Low 250K 300Kbps MTRO Motor enable signal to the FDD Drive 0 Active Low DRV1 Select signal to the FDD Drive 1 Active Low DRVO Select signal to the FDD Drive 0 Active Low MTR1 Motor enable signal to the FDD Drive 1 Active Low FDDIR The signal to specify the direction of the FDD head movement Low Step in High Step out STEP The signal to move the head during FDD seek Active Low WDATA FDD write data signal Active Low WGATE Write circuit enable signal for the drive that has seized the FDD Active Low HDSEL FDD head select signal Low Head 1 High Head 0 INDEX The signal to indicate the first FDD track Active Low TRKO Position signal for FDD Track 0 Active Low WPRT FDD write protect write disable signal Active Low RDATA FDD read signal DSKCHG The signal used to indicate that the FDD drive door is open Active High AO System address bus Address latched signal 11 12 1 IOCHRDY The signal that turns low when I O address 210H is accessed SIRQ Serial interrupt signal PCICLK clock for SIRQ sync Read signal to I O device Active Low lOW Write signal to the I O device Active Low DO System data bus IN OUT D3 D4 07 RXD1 COMI serial input data TXD1 COMI serial output data DSR1 C
43. 5 10004 8302 135 1263265 FRent 35 m 5 8301 5 4 33 FCCUDS 155 13 3205 9674 35 mong 83007 32552 0 35 a F 16007 8239 5 12632 03435 5 1008 FLCDOS 3 11 GNT35 3 ait 5 1 lt 009 R29 5 3 FLCDOS 21 030 0010 8936 FLEDDIS 11 3 pu 15 ae 100012 82947 FLCDDI2 ng 31 Werne Wr Tome UE E M Lim 4 c s da eno 5 m SE dre NO d m ho 00 80 2030 0013 R293 0013 1 OE von marni EMEC 0014 232 ya 25 8 5 aw 1 o S ES 0015 R23 FLCDDIS RI68 VOIE Coole FLCDDIE x V 5 ns i wo aL Ws 001 309 VV 3 FLCDD1 Not Mounted A eL VG 308 FBLP 2 218 s LS 174 33 rFPSCLK 1913 Qo 8107 FP a BOE R30 5 FEDE 05 gt LER mn g FPVDDEN 1 vi 5 2 18 0016 FRFPGCLK ona get RISI
44. 8 1 1 test 1 Connect a loopback connector to the COM1 port The lock screw of the loopback connector shall be tightened normally 2 Enter 1 ENTER through the keyboard IN ERNAL LOOPBACK EX ERNAL LOOPBACK RS2 LCD DISPLAY TEST 4 8 Serial port Test Test COMI I O Address 03F8H RS232C Controller Register R W Test rest Test l est done Press any key Finish the test after displaying OK for all the diagnostic items Disconnect the loopback connector that has been connected to the COM1 port 3 4 Press any key to obtain the 8 Test screen 5 6 Enter 1 ENTER through the keyboard LCD DISPLAY TEST 8 Serial port Test Test COM1 I O 32C Controller CTS ERROR Address 03F8H Register R W Test lest Test Test done Press any key 7 The EXTERNAL LOOPBACK Test shall result in CD ERROR and CTS ERROR 8 Press any key to obtain the 8 Test screen 3 24 8 2 2 test 1 Connect loopback connector to the port The lock screw of the loopback connector shall be tightened normally 2 Enter 2 ENTER through the keyboard LCD DISPLAY TEST 4 8 Serial port Test Test I O Address 02 8 RS232C Controller Register R W Test
45. End code d 7 is a check byte Check byte calculation a The header is set in the binary data Result Obh b An exclusive OR is established with 0 of the front ID data Result Obh An exclusive OR is established with 0 of the second ID data Result Obh d An exclusive OR is established with O of the third ID data Result Obh An exclusive OR is established with 1 of the fourth ID data Result Oah f An exclusive OR is established with 2 of the fifth ID data Result 08h g An exclusive OR is established with F of the end data Result 07h h The above mentioned result is compared with 7 for the check byte 2 44 21 15 Cash Drawer interface circuit As an integrated POS two Cash Drawer interface circuits are provided To drive the cash drawer 328H of the I O port is used for interface control Drawer 1 is controlled with Bit 4 of Address 328 while Drawer 2 is controlled with Bit 5 When 1 is written in Bit 4 a high level output is generated at the DRW1 OPN signal Pin 118 of the GATEARRAY uPD65884GM Then Transistor 025 is turned ON 024 and approx 15V is supplied as the 051 signal When 1 is written in Bit 5 a high level output is similarly generated at the DRW2 OPN signal Pin 117 of the GATEARRAY Then Transistor Q26 is turned ON and approx 15V is supplied as the DS2 signal The drawer opening time can be selected by
46. PIIX4 8105854 3 3 33 8105054 3 02 31 30 3 nM 3c 5 105 ROM 2 14 2 1 5 IT8673F circuit The IT8673F is used as LSI for the control of peripheral I O circuits keyboard and mouse The IT8673F functions as the two UART units equivalent to 16C550 the parallel port with the FDC equivalent to DP8473 incorporating the analog data separator and the 8042 compatible keyboard controller having the mouse control function conforming to the PS 2 Specification An address decoder circuit conforming to the Plug amp Play Specification V1 0a is incorporated to realize AT compatible functions The respective functions are set up with the software SD 0 7 SA 0 15 EME RESETDRV AEN IOR IOW IOCHRDY DRQ2 DRQ3 DACK1 DACK2 DACK3 TC SERIRQ PCI CLK RC IN A20GATE SA14 95 SA13 92 5 12 91 SA11 SA10 31 30 28 27 26 25 75 76 AQ A8 AT A6 A5 A4 A3 A2 A1 low IOCHRDY DRQ1 DRQ2 51 88 89 packs TC SIRO PCICLK 83 86 GA20 1 T8763F CLKIN 2 15 47 07 46 806 45 805
47. Video RAM Clock for SGRAM SDCKEN IN OUT Video RAM Clock enable for SGRAM Active High MD63 Video RAM Data bus MD62 MD61 MD60 MD59 MD58 MD57 MD56 IN OUT MD55 MD54 MD53 MD52 MD51 MD50 MD49 MD48 MD47 MD46 MD45 MD44 MD43 MD42 MD41 MD40 2 30 MD39 MD38 Video RAM Data bus MD37 MD36 MD35 MD34 MD33 MD32 MD31 MD30 MD29 MD28 MD27 MD26 MD25 MD24 MD23 MD22 MD21 MD20 MD19 MD18 MD17 MD16 MD15 MD14 MD13 MD12 MD11 MD10 MD9 IN OUT MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MDO CRTHSYNC OUT CRT Horizontal sync signal output OUT CRT Vertical sync signal output BLUE OUT CRT DAC output analog blue signal GREEN OUT CRT DAC output analog green signal RED OUT CRT DAC output analog red signal ACTIVITY IN OUT The status signal to indicate that the memory and I O address are valid ROMEN VGA_BIOS ROM select signal Active Low PDOWN IN Power down enable signal Active Low TESTO IN OUT Test pin TEST1 2 31 FDATA23 LCD Panel data FDATA22 FDATA21 FDATA20 FDATA19 FDATA18 FDATA17 FDATA16 FDATA15 FDATA14 FDATA13 FDATA12 FDATA11 FDATA10 FDATA8 FDATA7 FDATA6 5 4 FDATA2 FDATA1 FDATAO M DE OUT LCD Data validity timing output for TFT color panel Active Low FP FVSYNC OUT LCD Vertical sign
48. cias 253 4 707259 31 O 18750 S y Buzzer sw eri 1 ies cee 2 8 118739 15 RESET SW 193 Cue 118250 lu 18750 9 d d BIGB PH K S 4 4 VOLUME 1129 ELNI 8750 7 OK C 71 NG 8 118750 LED AS 86911750 Len 61 2 BLM 18250 S LN LEDI LED POWER LED 1 STANBY LED 4 1 1 Schematic Diagram 10 10 C248 C247 sour 10398 811 us CPU CORE s md m d 5 1121735 5 288 ren 7 151442001 6233 5 8414 128 um R271 ETOPSE 0 0801 29 1 core Ja 1 20 12 8272 0 008 1 24 14 101 lt Sun 10 001 6310 199 19 15V 1 60 12 Y pertes ce 1 rd Te bog e 0 010 100KC12 41 0207 1 R280 16 0 01 if mo n E ra R281 42 0KCIX bg 1 3 3V VCCP 1 8V 400mA i VIO 2 5V 1 5 1 T 3 3V 2 5V 400mA
49. t81 E DL M gat FP FVSTNC LP FFSTNC Ka malt VMDS br C 50810 641 C81 FP FVSYNC 5 85 lt gt GREENSIO 141 DE 5 1 S rp 42 FFEN T al 1 ap gt CRTHSYNC 043 905 gt CRTVSYNC 4 3 VMD4 4121 Not Mounted i 22 mmg 4 RC24S RCT245 cs 1 gt thee OP Ne ee A mes ig 0 1 2 STN COLOR 42 m ELJFC2R KF s 1 81 1 30 m 27 Dose ras 3 1613 1614 1615 8162 R163 8153 8165 6171 0 1 ean a us 5 5V LCD 00118 02 109 1 609 L man 3V LCD HS acess acess 09 00 08 5 1 vawe 191 e us VGND ran a 1 YS 1 9 er 1 600 C2 3 1 c ELJFC2R KF 678 VIDEO 1 1 eT Tots 0 us nm 58 CAPTURE i Jdem m 2p 1 mg Qr ats shy ccn e ro oan sal os ree ren 145 PLU MIS a IDSEL ADI9 n el Not Mounted ELIFCORPKF REQ
50. 3 34 LCD DISPLAY TEST 4 13 Drawer Test Already open Test done Press any key 9 Check the display of Already open and finish the test 10 Press any key to obtain the 13 Test Menu screen 11 Maintain the condition that the drawer is closed Hold the front section of the drawer by hand to prevent it from opening 12 Enter 1 ENTER through the keyboard LCD DISPLAY TEST 13 Drawer Test Not open Test done Press any key 13 Check the display of Not open and finish the test 14 Press any key to obtain the 13 Test Menu screen 15 Enter 0 ENTER through the keyboard to obtain the test program screen 3 35 15 Inline test 15 1 LAN ID setting 1 Enter 14 ENTER through the keyboard LCD DISPLAY TEST 4 14 Inline Test Return to MAIN MANU Set Configutation Send Data Receive Data Self Test Select and press E 2 Enter 1 ENTER through the keyboard For Set Configuration only keyboard can be operated LCD DISPLAY TEST 4 14 Inline Test EXIT Ethernet Address x x Set EEPROM Select and press E 3 Enter 1 ENTER through the keyboard LCD DISPLAY TEST 4 14 Inline Test Ethernet Address Set 1234567890AB Set and press ENTER key 3 36 Kk KKK KKKKK 4 After entering an Ethernet Address input en
51. 31 mE t31 gt r 3 31 22 CO 3 31 Ones m fe ones 77 REFRESHO_3 32 lt 1066164 35 32 lt ZEROWS 35 31 Ones mw RESETORV_3 622103 7 7 O 108 3 13107183 A O 3 31C71t81 lt I0CHRDY 35 131073 D AEN 3 218 15A Dac 3 71 3 71 C 3 1 lt 060 35 t31 lt ROG 35 531 C1 0805 35 t31 C1 0803 35 t31C72 lt 0802 35 t31t72 0801 35 31073 C1 35 31 RAGS 100K es gt VGAPDHNE 41 Omit 889 7 lt 1803 35 33081 per es pee 121259 w ooo p i21 in o eA 23 LAIT 180 135 233 IROS 35 18010 35 31081 lt 18011725 C3108 mm lt 18012 35 C3 m lt 18014 35 31162 Bv ms lt 18015 35 3266 R3 052071 wee Serani Nee 1 5 RRS4 1 ME sav 10K J we xd C5 53 onm 81 RILI A gt 4 5857 RSM 110102 Ones sus 3 C12 One R402 9 11021 7 SCLKP4 3 12623 ATF INT 3 C1 ous 21 num pae 3 2 Ome 2 12 gt 8 Gatearay RIO ou 10 684 1302
52. 8 9 0 1 Select and Press ENTER Key 0 3 45 22 Input Password The drawer test is locked by the password Execute this test to unlock it 1 Select 19 and press the ENTER key on the main menu LCD DISPLAY PANASONIC JS 170FR TEST PROGRAM V5 X Password Set Set and press E 2 Enter 0427 the keyboard or touch panel LCD DISPLAY PANASONIC JS 170FR TEST PROGRAM 5 01 OK Password is correct Press any key to exit 3 When the screen appears as shown above press any key to return to the main menu If you have failed try again from Step 1 3 46 23 Operation Checks after Diagnostic Services When all test programs have been over arrange the HDD and the BIOS under the shipping condition 1 2 Finish the diagnostic programs and display the DOS prompt After entering the chpos input press the Enter key c gt chpos When gt is displayed turn off the FCR power supply Turn on the power supply for the JS 170FR and confirm that the screen as shown below is displayed Staring MS DOS HIMEM is testing extended memory done C gt C DOS SMARTRV EXENX C gt Dip SW1 on the main PCB factory setting JS 170FR U C EF S A W 1 2 3 4 5 6 OFF OFF ON ON ON ON JS 170FR G2 1 2 3 4 5 6 OF
53. ET a MA He sue scene Nol Mounted INI 50 51 R365 specs gt 9201 Not Mounted 50 53 8355 38 3 5V Od 35 mo 2 2 47000 14 ae Delian EE a 3 sooacks 30 4 200251 WA 5 6K E irm 777 1 Rz03 E Wt 31 IRQS 325 4 1 1 PCB Schematic Diagram 7 10 E Super 1 0 LEF 4 33081 s00 35 11862525 507 35 mo t9 ES B 8 sess H Orsi 191 E Pep Om C9 Ue eee OE ey 32081 5 00 15 3 2232 40 cR 191 San o DECOR M RII 293 5415 3 53 02 SS ares Vs 23 wn gt 752 9 e Pss RxD eT go DERE eme 91 204 5 91 12 ane cae 9 w upto 81 m 93 m o 91 m 91 Letoa 92 m 91 ps 4
54. character color The screened sections keep blinking LCD DISPLAY 80 25 16 10 Text Mode Black Dark Gray White White VGA Text Pa tern 80 X 25 16 Color VGA Text Pattern 80 X 25 16 Color VGA Text Pa tern 80 X 25 16 Color VGA Text Pattern 50 25 E Colors VGA Text Pa tern 80 X 25 16 Color VGA Text Pa tern 80 X 25 16 Color VGA Text Pattern 80 X 25 16 Color VGA Text Pattern 80 X 25 16 Color Red VGA Text Pa tern 80 X 25 16 Color VGA Text Pattern 80 25 16 OF OE Light Red VGA Text Pa tern 80 X 25 16 Color VGA Text Pattern 810 9 745 Color Magenta Light Magenta VGA Text Pa tern 80 X 25 16 Color VGA Text Pattern 80 X 25 16 Color VGA Text Pa tern 80 X 25 16 Color VGA Text Pattern 80 X 25 16 Color Green VGA Text Pa tern 80 X 25 16 Color VGA Text Pattern 80 X 25 16 Color Light Green Brown Light Brown VGA Text Pa tern 80X25 16 VGA Text Pattern 80 X 25 16 Color VGA Text Pa tern 80 X 25 16 Color VGA Text Pattern 20X25 16 Color VGA Text Pa tern 0 19 VGA Text Pattern 902425 Color Light Blue VGA Text Pa tern 80 X 25 16 Color Cyan Light Cyan VGA Text Pa tern 80 X 25 16 Color VGA Text tern 25 Color VGA Text Pa tern 80 X 25 16 Color VGA Text Pattern 80 X 25 16 Color VGA Text Pattern 80 X 25 16 Color VGA T
55. 1 Voltage checks the MAIN PWB 3 1 3 2 Oscillation frequency 3 2 3 3 POWER switch FRONT switch check 3 2 3 4 dei e d t o o diy 3 3 3 5 Current consumption 3 4 3 62 BIDS T 3 4 37 Method of diagnostic program starting 3 9 3 8 Execution of diagnostic 8 3 11 3 9 M Materials for Reference 3 48 4 S nite eeu Neto Whe varia 4 1 4 1 ttu 4 1 42 MUI 4 17 4 3 Perplheral PGB 5nd sederit ue cated ated 4 20 D Body Blocker tee tee anti vi esed Auten 5 1 5 1 Body Block Disassembling 5 1 5 2 Body Block Replacement Parts List nennen 5 7 6 6 1 6 1 Eccc 6 1 1 OVERVIEW General This model has the performance equivalent to an IBM AT machine which uses the Pentium as a CPU This model has its unique functions added to it and is provided with an ETHERNET circuit and touch panel as standard The desi
56. 266MHz Not Standard 1 Scandinavia 4 1 1 4 1 Discontinue June 2001 N A N A N A N A N A N A N A N A JS 170FR F22 June 2001 Gray 64 o N A Fujitsu 1 2 o 266MHz Not Standard 1 1 4 4 4 AC Cable L type JS 170FR F24 September 2001 Gray 64 o N A Fujitsu 1 2 o 333MHz Standard JS 170FR F23 June 2001 Gray 64 Fujitsu 1 2 266MHz Not Standard 1 1 1 4 AC Cable L type JS 170FR F25 September 2001 Gray 64 Fujitsu 1 2 333MHz Standard JS 170FR A20 From begin Yellow 16 DOS 6 22 Gen 2 266MHz Not Standard 1 JS 170FR A22 June 2001 Australia Gray 64 Fujitsu 1 2 266 2 Standard 1 l 1 JS 170FR A24 September 2001 Gray 64 Fujitsu 1 2 333MHz Standard JS 170FR A23 June 2001 Gray 64 Fujitsu 1 2 266 2 Not Standard 1 1 Australia 4 JS 170FR A25 September 2001 Gray 64 Fujitsu 1 2 333MHz Standard JS 170FR W20 From begin Yellow 16 00 6 22 2 266MHz Not Standard 1 1 1 JS 170FR W22 June 2001 Taiwan Gray 64 Fujitsu 1 2 266 2 Not Standard 120V 1 l l 1 JS 170FR W24 September 2001 Gray 64 o N A Fujitsu 1 2 o 333MHz Standard JS 170FR W23 June 2001 Gray 64 o N A Fujitsu 1 2 266 2 Standard Taiwan 1 120V JS 170FR W25 September 2001 Gray 64 Fujitsu 1 2 333MHz Standard JS 170FR C24 April 2002 Canada
57. 3 wi A n m wr HABO 3 a m KOH mien a 14 C1203 A EE aC mm 5 ww 3 Pri t Dat e A Koes Tie Rei our Es Gea ia eee D mei re A udo 18 106 03 4 We Kb Di gt hg od 2 5 Dii das 00 0 3 a pu men Rh A 27 EH HE MD40 03 SEL E LA 5 039 83 5 nisi min mus A Zis 1 gt 21 WD36 03 I A ee ee ee xx Lit 036 03 35 1 ijo ema mis 7 mp mim 030 03 m zs 030 03 A 75 029 03 A MCLKDIM4 03 male 8029 03 A SEDER a be HCLKDINS 03 uj m mi mn HCLKDIHS 03 nie m mh I1 d sl MCLKDIM3 03 153 71 5026 03 MCLKDIM 03 151 im n 03 zE mE oni e ee COC 3 NA 3 Wu 13031 30 1 nj 12632 saxe 3o mni ET miu Dis Di CAM 5
58. 50 MSDATA 10 KB DATA ms DATA 80 Ms CLK A20GATE 86 6 20 4 7 MINI DIN RCIN lt dks 0100559 105 a 2 23 The transistor circuit is intended to control signals of the keyboard the magnetic card controller Control is actually undertaken by the magnetic card controller When the anodes of the diodes D and D are maintained at the high level the transistors of 0104 are turned ON and the keyboard signals are led to the keyboard controller When the anodes are turned low the transistors are turned OFF to separate the keyboard controller from the keyboard The keyboard is then connected to the magnetic card controller In the state of operation ready both of the KBDDATA and KBDCK signals are maintained at the high level Regarding the serial data from the keyboard one data lot is composed of 11 bits as shown below 1 1 bit fixed at low level 2 Key reete 8 bits LSB 3 Odd numbered parity bit 1 bit A StOp bit 1 bit fixed at high level When the keyboard controller receives data from the keyboard the clock line is once turned low as an ACK signal to the keyboard When Key a is pressed Make Scan code 1C KB DATA ccc
59. 54 IN324 Input Port 0324h bit2 input pin 55 IN324_D1 Input Port 0324h bit1 input pin 56 IN324 DO Input Port 0324h bitO input pin IN 032Dh 57 ITEST1 Test pin Not connected 58 SEL160N 170FR 160FR changeover pin DECODE 59 24MHz 24 0 2 clock input pin CLOCK 61 EXISARDN ISA extension bus control signal from outside DATA ISAEX 62 9MSEC OT CLOCK 9msec period output pin 63 71MSC OT CLOCK 7msec period output pin CLOCK 64 SFTRT EN Software reset enable input pin Back Reset 65 ITEST2 Test pin Not connected 66 IORSTN Reset output pin Active Low Back Reset 67 ASEL address select High 3220h Low 03E8h 68 4 ASEL address select High 3228h Low 02E8h 69 COM3_EN hardware control High COM3 Enable Low Disable 70 COM4_EN hardware control High COM4 Enable Low Disable COM ADDRESS 71 IN32C_D7 71 Input Port 032Ch input pin Not used 72 INS2C 06 72 Input Port 032 bit6 input pin 73 IN32C_D5 73 Input 032Ch bit5 input pin 74 IN32C_D4 74 Input 032Ch bit4 input pin 75 IN32C_D3 75 Input 032Ch bit3 input pin 76 IN32C_D2 76 Input Port 032Ch bit2 input pin 77 IN32C_D1 77 Input 03
60. Default or Not Connected 1 9 6 pin DIN Female No IN OUT Signal 1 OUT Drawer_Open 2 GND 3 IN Drawer_Status 4 GND 5 IN Drawer Type 6 GND 25 pin D SUB Female No IN OUT Signal 1 IN OUT STROBE 2 IN OUT Data Bit 0 3 IN OUT Data Bit 1 4 IN OUT Data Bit 2 5 IN OUT Data Bit 3 6 IN OUT Data Bit 4 7 IN OUT Data Bit 5 8 IN OUT Data Bit 6 9 IN OUT Data Bit 7 10 IN 11 BUSY 12 IN PE 13 IN SLCT 14 OUT AUTO FD XT 15 IN ERROR 16 OUT INIT 17 OUT SLCT IN 18 GND 19 GND 20 GND 21 GND 22 GND 23 GND 24 GND 25 GND LAN USB 15 pin D SUB Female No IN OUT Signal 1 OUT Video_Red 2 OUT Video_Green 3 OUT Video Blue 4 NC 5 GND 6 Video GND Red 7 Video GND Green 8 Video GND Blue 9 NC 10 GND 11 NC 12 IN OUT SDA 13 OUT H Sync 14 OUT V Sync 15 IN OUT SCL 8 pin Modular RJ 45 No IN OUT Signal 1 OUT 2 OUT TX 3 IN RX 4 NC 5 NC 6 IN RX 7 NC 8 NC USB Connector No IN OUT Signal 1 5 45V 2 6 IN OUT USB Data 3 7 IN OUT USB Data 4 8 GND Keyboard Floppy Disk 6 pin mini DIN No
61. Exit Discarding Cha Load Setup Defaults Discard Changes Save Changes Setup Confirmation lefault values Load default configuration now ETUP items Yes No Space Select Enter Accept 4 Starting from the screen of 3 above move to Main by means of the leftward arrow mark lt Then using the keys of Tab Space and 4 set time and data at that time point Example 13 January 2000 20 00 PhoenixBIOS Setup Utility Main Advanced Power Boot Exit System Time 20 00 00 Item Specific Help System Date 01 13 2000 Legacy Diskette A 1 44 1 25 MB 3 1 2 Shift Tab or Enter selects field Primary Master MB Primary Slave None Secondary Master None Secondary Slave None Boot Options v vvv emory Cache System Memory Extended Memroy 1 1 N Select Item Change Values F9 Setup Defaults Esc Exit Select Menu Enter Select Sub Menu F10 Save and Exit 3 5 PhoenixBIOS Setup Utility Main Advanced Power Boot Exit Item Specific Help System Time System Date Tab Shift Tab Legacy Diskette A 1 44 1 25 MB 31 2 Enter selects field Primary Slave Secondary Master gt Secondary Slave p Boot Options gt emory Cache System Memory Extended Memory Help T L Select Item 4 Change Values F9 Setup Defaults Exit lt Select
62. Gray 64 Fujitsu 1 2 333 2 Standard 120V JS 170FR C25 April 2002 Canada Gray 64 Fujitsu 1 2 333 2 Standard 120V Serial Number Control Table for Classified Modifications JR 170FR Models Model Number Modification Description 020 021 022 023 024 025 620 021 622 023 G24 G25 20 21 22 23 24 25 520 21 1 Main board modified R430 Jumper wire 01D 01D imbedded 2 Resistor R430 added 10 kilo ohms added O1A Eu o 01A 01A o 01 3 Constant ot resistor From 1 2 kilo ohms to oga orate uuu R181 modified 750 ohms 4 DIMM enhanced From 16 MB to 64 MB O1B O1B 2 01B 5 Baud rate of customer From 2400 bps to 9600 _ mores o p pend display enhanced bps except G version 6 Operating System Not O1B cee O1B ch 01B except G version 7 Power supply modified Manufacturer changed 01D 01D 01D 01D 8 Power supply modified Diffuser panel added 02A 02
63. IN OUT PCI The signal used to indicate the status that the target can perform data transfer IRDY IN OUT The signal used to indicate the status that the initiator can perform data transfer STOP IN OUT PCI Request signal from the target to the initiator for the suspension of execution Active Low DEVSEL IN OUT PCI Device select signal Active Low IDSEL PCI The signal used to specify the target device PCICLK PCI System clock 33MHz 30MHz RST Asynchronous reset signal Active Low REQ Bus request signal Active Low GNT Acknowledge signal to the REQ signal INTA PCI Interrupt signal Connected with PCIINTD CKIN VGA clock input Fixed at 14 3181MHz REFCLK Clock for suspend refresh 32 768MHz MCKIN LVDSCK IN OUT Used as LVDSCK EXCKEN IN Clock select signal Low CKIN High gt MCKIN 2 29 1 Video RAM Memory address MA2 MA3 MA4 5 7 MA8 MA9 BA Video RAM Bank address Video RAM Write enable signal CAS Video RAM Column address strobe signal Active RAS Video RAM Row address strobe signal Active 0 0 Video RAM Chip select signal for SGRAM Active CS1 RAS1 DSF OE Video RAM Block write signal for SGRAM Active DQM0 CASO Video RAM Data mask signal for SGRAM Active DQM1 CAS1 DQM2 CAS2 DQM3 CAS3 DQM4 CAS4 DQM5 CAS5 DQM6 CAS6 DQM7 CAS7 SDCK IN OUT
64. IN OUT Signal 1 IN OUT Keyboard_Data 2 IN OUT Mouse_Data 3 GND 4 5V 5 IN OUT Mouse_Clock 6 IN OUT Keyboard_Clock 26 pin mini I O Connector No IN OUT Signal 1 GND 2 IN INDEX 3 5V 4 DRVO 5 GND 6 IN DCHGO 7 8 9 10 5V 11 OUT MTRO 12 OUT DIR 13 DENSEL 14 OUT STEP 15 GND 16 OUT WDATA 17 GND 18 OUT WGATE 19 GND 20 IN TRKO 21 GND 22 IN WRPRT 23 IN RDATA 24 GND 25 OUT SIDESELO 26 NC PCI Interface 32bit Edge Connector 5V system No B side A side 1 12V TRST 2 TCK 12V 3 GND TMS 4 TDO TDI 5 5V 5V 6 5V INTA 7 INTB INTC 8 INTD 5V 9 PRSNT1 Reserved 10 Reserved 5V I O 11 PRSNT2 Reserved SERIRQ 12 GND GND 13 GND GND 14 Reserved Reserved 15 GND RST 16 CLK 5V I O 17 GND GNT 18 REQ GND 19 5V I O Reserved PME 20 AD 31 AD 30 21 AD 29 3 3V 22 GND AD 28 23 AD 27 AD 26 24 AD 25 GND 25 3 3V AD 24 26 C BE 3 IDSEL 27 AD 23 3 3V 28 GND AD 22 29 AD 21 AD 20 30 AD 19 GND 31 3 3V AD 18 32 AD 17 AD 16 33 2 3 3V 34 GND FRAME 35 IRDY GND 36 3 3V TRDY 37 DEVSEL GND 38 GND STOP 39 LOCK 3 3V 40 PERR SDONE 41 3 3V SBO IDE Interface
65. L 1 1 DE10 850 9 a PPDD9 PPDD4 L 1 DE4 PPDD11 7 1 0 11 120 PDD8 11 B A 7 1 DE3 60 2 PPDD12 7 1 DE12 2O a PPDD2 1 DE2 PPDD13 1 DE13 14 245 PPDD1 1 DE1 PPDD7 PPDD14 1 0 14 0 17 5 PPDD6 PPDDO 7 1 DEO PPDD15 1 DE15 18 O 5_ 19 PPDD4 20 PDDRQ 21 L O 22 02 4 LPD IOW 23 i O PPDD1 0 25 pw PDLIOR LPDIOR 26 DIR 0 PIORDY o 28 9 PDDACK amp LPDDACK 29 O 2 gt AHCT245 31 B R14 pp DEIRA O PDSA1 IDEA 23 PDAQ L 19 o PDCS1 gt A B PDSA0 IDEAO o PDCS3 gt A B PDSA2 fT 1DEA2 36 2 PPDCS1 I DECS1 PDI OR gt A B L PROCS3 LDECS3 382 DE_RESET gt A B o PDIOW gt A B Les 1 19 DiR 5 HDD_LED lt 43 77 5 PDDRA lt PI ORDY 777 lt 777 PDDACK 2 10 PDCS3 PDCS1 PDIOR L Disabled PDIOW L Disabled Data register Data register Error registe Future register Selector counter Selector counter Sector number Sector number Cylinder low Cylinder low Cylinder high Cylinder high Drive head Drive head Status Command High impedance High impedance High impedanc
66. Menu Enter Select p gt Sub Menue F10 Save and Exit 6 After selecting Primary Master MB press the ENTER key to enter the Primary Master setup screen PhoenixBIOS Setup Utility Primary Master MB Item Specific Help Type Cylinders Head Sectors Maximum Capacity Multi Sector Transfers 16 Sections LBA Mode Control Enable 32 Bit Disable Transfer Mode 4 2 Ultra DMA Mode ode2 Help T 4 Select Item 4 Change Values F9 Setup Defaults Exit lt Select Menu Enter Select P Sub Menue F10 Save and Exit 7 Perform the following steps 1 2 and 3 on the Primary Master setup screen 1 Select Type by using 1 4 key on the keyboard then change the choice to Type 2 Select Transfer Mode by using key on the keyboard then change the choice to Transfer 4 by using or key on the keyboard 3 Select Ultra DMA Mode 21 by using or key on the keyboard then change the choice to Ultra sf by using or key on the keyboard by using or 3 6 8 After performing the steps 1 2 3 above verify that the setup of Type Transfer Mode Ultra Mode appears as follows on the Primary Master setup screen Type User Transfer Mode Fast 4 Ultra DMA Mode Disabl
67. P50 O cARD_IN1 2 p54 35 P16 777 34 A P20 gt 2132 gt MAGNG p224 gt KBENABLE 2 42 Magnetic card Second Track Specification Total NO teria Approx 251 clocks a whole Quantity of data 5 x 40 digit 200 bits max Bit configuration 5 bits 4 bits for data 1 for odd parity Start B End lt Separation Timing signal In the spaces from the start to first data bit start code and from the end data bit to the end continuous binary codes 0 are recorded as the timing signal Scan Codes Applicable to the PC AT Keyboard For the Second Track Output scan code Readout data 3 4 Start code Separation code End code 2 43 Specification for Magnetic Card Control Contents of magnetic card control specified for the PENTIUM POS 1 2 3 4 2 5 lt Connected the keyboard connector ISO 7810 compatible Second track ID to be used is of the 5 bytes data with 0 included For reference ID 00012 7 a B is the front byte Start code b 00012 is an ID of the 5 byte data with 0 included is the end byte
68. PORRSTUVWXYZ abcdefghijklmnopqrstuvw RRSTUVWXYZ abcdefghijklmnopqrstuvw 0123456789 lt gt ABCDEFGHIJKLMNOP 0123456789 lt gt ORRSTUVWXYZ abcdefghijklmnopqrstuvwx 2 1 abcdefghijklmnopqrstuvwx 5 Press key to obtain the 7 Test screen 6 Enter 2 ENTER through the keyboard The printer begins to print out characters Paper is cut after the completion of printing Confirm that the following contents are presented i For Printer TM 300 ii For Printer TM T80 Parallel Port test 1 0 Address 0378H Parallel Port test I O Address 0378H 1 28 0123456789 lt gt GABCDEFG 104558 0123456789 lt gt HIJKLMNOPQRRSTUVWXYZ abcdefghijklmno JKLMNOPORRSTUVWXYZ abcdefghijklmno 104558 0123456789 lt gt ABCDEFGH 1896 0123456789 lt gt GABCDEFGHIJ IJKLMNOPORRSTUVWXYZ abcdefghijklmnop KLMNOPQRRSTUVWXYZ abcdefghijklmnop ESSE 0123456789 lt gt ABCDEFGHI ESSE 0123456789 lt gt ABCDEFGHIJK JKLMNOPQRRSTUVWXYZ abcdefghijklmnopq LMNOPORRSTUVWXYZ abcdefghijklmnopq 5 amp 0123456789 lt gt ABCDEFGHIJT 5 amp 0123456789 lt gt ABCDEFGHIJKL KLMNOPORRSTUVWXYZ abcdefghijklmnopqr MNOPORRSTUVWXYZ abcdefghijklmnopqr 588 0123456789
69. TASES eia cise 5 3 015 Loska R246 10 OKC12 Iceg s R250 8810339 1 82KCIX 4 5 BDETO amp R248 10 0K 1 O 0 72 to FPGA 10 57 BOET LeV R238 esy 0 1 30001 Ci68 5 des i VOLTAGE DETECT 1 3 D POST LED 3 D 2071308 10 BRESET he i 5 PCISSS2DV m 9 pm 91 Rts3 91 91 E 9 con acsi 9 33 LJ t31 WOR alg 13 8237 x 3 26 fal REEET QUT ar zsci 0UT 72033 199 amem maea 21 e 03 53 m e o 1800135 32 T AMR 31 ol Mounted 1 3 CUSTOME esten pis es 4 meal 145 e pata CUSTOMER us CONNECT 127 129 amen HE 139 ones GND ascot 8 5 71 15 8244 3 3090 2 025 R23
70. Test done Press any key 6 When data are received from FR 2 FR 1 then displays the following screen LCD DISPLAY TEST 14 Inline Test Receive Data Send Data 1234567890 gt gt gt Receive Data ABCDEF 123456 gt gt gt 1234567890AB Test done Press any key 3 Check the display of OK and finish the test Confirm the middle of testing that the front LED for LAN blinks in green For both FR 1 and FR 2 press any key to obtain a test screen for 14 In addition enter 0 through the keyboard to obtain a menu screen for the diagnostic program 3 38 15 3 Registration of LAN system address For each FR individually register and control the ID address of the network 12 digit hexadecimal number Control numbers Within the range of 0000 010000 0000EBO1FFFF 12 digit hexadecimal number Method of registration 1 Write the above number on the label and stick it to the MAIN PWB 4 30 0000 01000 7 Method of control 1 Irrespective of the product item number this label shall be stuck to the PWB where the LAN controller is mounted Since this method is used for multiple models control must be carefully done to avoid duplication or lack of numbering 3 39 16 Mouse test 1 Turn on the power supply under the condition that the keyboard and the mouse are connected to the keyboard connector t
71. lt gt 555 0123456789 lt gt LMNOPQRRSTUVWXYZ abcdefghijklmnopars NOPQRRSTUVWXYZ abcdefghijklmnopqrs amp 0123456789 2GABCDEFGHIJKL amp 0123456789 lt gt ABCDEFGHIJKLMN MNOPQRRSTUVWXYZ abcdefghijklmnopqrst OPORRSTUVWXYZ abcdefghijklmnopqrst amp 0123456789 lt gt ABCDEFGHIJKLM amp 0123456789 lt gt ABCDEFGHIJKLMNO NOPQRRSTUVWXYZ abcdefghijklmnopqrstu PORRSTUVWXYZ abcdefghijklmnopqrstu 0123456789 lt gt ABCDEFGHIJKLMN 0123456789 lt gt ABCDEFGHIJKLMNOP OPORRSTUVWXYZ abcdefghijklmnopqrstuv QRRSTUVWXYZ abcdefghijklmnopqrstuv 0123456789 lt gt ABCDEFGHIJKLMNOPQ Cut in this position RRSTUVWXYZ abcdefghijklmnopqrstuvw 0123456789 lt gt 8ABCDEFGHIJKLMNOP ORRSTUVWXYZ abcdefghijklmnopqrstuvwx Cut here 7 Press any key to obtain the 7 Test screen 8 Enter 0 ENTER through the keyboard to obtain a menu screen for the diagnostic program 3 22 8 Serial Port test 1 Enter 8 ENTER through the keyboard LCD DISPLAY TEST 4 8 Serial Port Test 0 Return to MAIN MANU 1 Test COMI 2 Test COM2 3 4 Test COM3 Test Select and press 2 No testing is carried out for the item of 4 Test COM 4 3 23
72. more details in regard to the internal circuits refer to the instruction manual for the GATEARRAY separately furnished 2 1 18 1 Internal functions The major functions provided inside the GATEARRAY are as specified below Address decoder for COM3 and COM4 Address decoder for POST LED Control circuit for cash drawer Clock frequency divider circuit FDD gate signal control circuit Customer Display control circuit POS individual control circuit LCD timing control circuit Power supply control circuit 2 1 18 2 GATEARRAY Pin Assignment Pin No 2 WGATE INN FDD WE Write Enable signal input pin Super I O Signal name IN OUT Functions Common IN 156 5 0 SA1 SA2 15 Address bus conforming to the ISA Specifications Common BATEN_IN Battery backup enable input pin Active High AC Detect TMR_SET1 Battery backup time setting 1 Bvack up Timer TMR_SETO Battery backup time setting 2 0322_D7 Output port 0322h bit7 output pin Connected to TMR_SET1 0322 06 Output port 0322h bit6 output pin Connected to 0322 05 Output port 0322h bit5 output pin used 0322_D4 Output port 0322h bit4 output pin 0322 Output port 0322h output pin 0322 2 Output port 0322h bit2 output pin used O322 D2N Reversed output pin of output port 0322h bit2 0322 Output
73. port 0322h bitO output pin 0322h IN32D 04 Battery connection identification input pin High Not connected Low Connected 032Dh 21 D7 Battery level input pin IN321 D6 Battery level input pin IN321 D5 Battery level input pin IN 0321h POWR OFF Secondary side power OFF control output Active Back Reset SW ON IN Secondary side power control signal input pin Active FLAGCLRN AC power OFF detect Flag clear input Active BATT ON Battery backup ON output Active PWRINTN Power OFF interrupt output Active AC ON IN AC power detect input pin Active AC Detect PORTEN Hard enabled pin for POS exclusive port 03201 032Fh Active PORT CNT INS2D 05 Input port O32Dh bit5 input pin 2 51 IN 032Dh Signal Functions Common 45 IN DRAW STO Cash Drawer open time setting BitO 46 DRAW ST1 Cash Drawer open time setting DRAWER 47 INS2D DO Input Port 03201 input pin 48 INS2D D1 Input Port 03201 bit1 input pin 49 INS2D 06 Input Port 03201 bit6 input pin 50 IN32D_D7 Input Port 032Dh bit7 input pin IN 032Dh 51 IN324 D5 Input Port 0324h bit5 input pin 52 IN324_D4 Input Port 0324h bit4 input pin 53 IN324 D3 Input Port 0324h bit3 input pin
74. request signal to the CPU CPU Active High IOCS162 ISA Used to specify the data bus width of I O Low gt 16 bit High 8 bit IOCHKZ GPIO ISA The signal to indicate that a correction impossible error has occurred gt Active Low IOCHRDY ISA Used when the bus cycle is extended Wait signal Active Low lOW IN OUT ISA Write signal to the I O device Active Low IN OUT ISA Read signal to the device Active Low IRDY IN OUT PCI The signal to indicate that the initiator is enabled to transfer data 2 4 Signal name IN OUT Functions System timer interrupt signal being output IRQO IRQ1 Mask enabled interrupt request signal Keyboard controller Active IRQS Mask enabled interrupt request signal lt Serial port 2 Active IRQ4 Mask enabled interrupt request signal lt Serial port 1 Active IRQ5 Mask enabled interrupt request signal Active IRQ6 Mask enabled interrupt request signal lt Active 1807 Mask enabled interrupt request signal lt Parallel port 1 Active IRQ8 GPI6 Mask enabled interrupt request signal lt For RTC Active 1809 Mask enabled interrupt request signal lt ETHERNET Active IRQ10 Mask enabled interrupt request signal lt Serial port 4 Active IR
75. the use of Switches 3 and 4 of the DIPSW2 The default setting is about 140msec Inside the GATEARRAY circuit there is a circuit intended to avoid the simultaneous operation of Drawer 1 and Drawer 2 CDSTATUS1 and CDSTATUS2 are the drawer status signals For the type of a drawer to be connected the logic may be reversed In the present circuit a low level is defined as the status when a drawer is closed When using a drawer for which the logic has been reversed the section is short circuited between Pin 5 and Pin 6 of the connector Arranged with a cable By making DRWCNT1 Pin 119 and DRWCNT2 Pin 114 of the GATEARRAY circuit turned to the high level arrangements for exclusive OR EXOR are made for the signals of DRWST1 Pin 115 and DRWST2 Pin 116 and also for the GATEARRAY interior As aresult the software can conclude the judgment of Open or Close By reading out Address 32D of the I O port the logic can be defined at Bit and 2 DRV 3 3 2W 7 7 1 2W 330u Sag ami GATEARY a202 777 15K 4 DTC123Y N 298440 e i i 2 820 1 2W FL 081 DRW1 OPN 15 GND 777 77 1N320 D3 115 L CDSTATUS1 5V I 470 1u 4 10K GND 118 50 A M 6 DRAWER2 1 18 9
76. transfer has been over Active Note The OUT signals marked by the asterisk are the open drain output signals 2 1 5 2 Serial port 2 178673 incorporates the two 16C550 compatible serial port controllers UART1 and UART2 24MHz signal fixed is 13 frequency divided into 1 8462MHz that is then used to produce Baud rate clock This port operates in an asynchronous mode The two controllers are independent of each other By setting up a configuration port with software address and interrupt assignment can be carried out The basic setting for this system is as specified below IT8673F address Interrupt level UART1 COM1 3F8h 3FFh 1804 UART2 COM2 OUT IRQ3 IT8673F ADM2 11 2 11 TXD1 49 T10UT TXD D 6 2 COM1DTR H RTS 21 T40UT 28 RXD1 48 5 IRIOUT COMI psri 0 20 5 IR20UT 4 COM1 DSR 0 52 26 HZ CTS pep1 0 55 22 R4ouT 23 COM CD D 54 19 asouT 18 L RI SHDN EN GND 2 11 2 11 2 52 7 T1OUT prre 0
77. 0 2 Description of Operation JS 170FR Block Diagram Mobile Pentiumll Proccessor Host Bus Main Memory SDRAM T LCD DIMMx2 9 PCI Slots lt BUS ZN E ues PIIX4E m T 2 2 2 5 P Cl to IS A 2 5 8 HDD a 5 5 4 ISA BUS 20 Super 1 0 UART 16552 Gateara BIOS ROM a D R DR Touch Customer Dispay COMI COM2 K B COM3 C D 2 1 Description PCB Circuits 2 1 1 CPU PENTIUM II 266MHz or 333MHz Refer to the page 4 1 The CPU is operated at an operating clock signal frequency of 66MHz with the use of a mobile PENTIUM II the core voltage of which is 1 6V Details of CPU operation are obtainable from the relevant catalog Chip set FW82443BX FW82371EB Refer to the page 4 1 and page 4 3 As acontrol chip set for CPU s peripheral circuits two units in a pair of FW82443BX and FW82371EB are used The FW82443BX is directly combined with the CPU and it is mainly in charge of memory control and PCI bus control In o
78. 03 17 03 4 ne 5 s 775 Xu E rm s 53 MECC3 1 pe 51 MECC 4 x 4 v a od Cc A A 5 P hi ma wh S z sp wi mpa 5 IC6 152 24 R83 150 1 4 8 47 KCLXDIMO 03 5 3 me H A 3 e xS UN ma Doms r E H 55 4 g24 47 11 mue 2 d EF H ele PAM HCLKDING 03 s 38 927 47 HCLXDIMS 03 HCLXOIMS 03 n HCLXOIN 03 m 2 4 T D aj P D Mad me 3V 1 m n Not Mounted 52 43 3 x e 2 1 uj Rat 0 m ux ss E385 c osce 03 32 1 10 wits 238 4 n gt 05 41 m Fn 0 Not Mounted t1 m 2 Cll 3 3V 12 R82 2 mus REE Demo 17270816112 31 cR 3 gt AMA te custo amm RET 03 3 r3 FCLKP4 D3 31 R62 POLKMTXC_03 17 nup 3 41 FQLKLAN 03 51 3 R64 S 33
79. 0FR G22 July 2001 Germany Friendly Gray 64 o DOS 6 22 Gen 2 o 266MHz Standard AC Cable L type 1 l M 1 1 14 JS 170FR G24 September 2001 Friendly Gray 64 00 6 22 2 333 2 Standard JS 170FR G21 From begin Yellow 16 DOS 6 22 2 266MHz Not Standard AC Cable Straight 1 JS 170FR G23 July 2001 Germany Friendly Gray 64 o DOS 6 22 2 x 266MHz Standard AC Cable L type 1 l M M l JS 170FR G25 September 2001 Friendly Gray 64 005 6 22 2 333MHz Standard JS 170FR E20 From begin Yellow 64 Fujitsu 1 2 266 2 Not Standard 1 1 JS 170FR E22 June 2001 UK Gray 64 Fujitsu 1 2 266MHz Not Standard 1 1 1 JS 170FR E24 September 2001 Gray 64 Fujitsu 1 2 333 2 Standard Customer Specification RAM size Dip SW Model No Ww Country Cap Color Battery o s CPU MSR Other change timing MB TP MSR Display JS 170FR E21 From begin Yellow 64 Fujitsu 1 2 266 2 Not Standard 1 l JS 170FR E23 June 2001 UK Gray 64 Fujitsu 1 2 x 266MHz Not Standard 1 l l 1 JS 170FR E25 September 2001 Gray 64 Fujitsu 1 2 333MHz Standard JS 170FR S20 From begin Yellow 64 Fujitsu 1 2
80. 10 Rig 8190 x n S Not 82 aire ne clits 5 00 15 7 10K cig 136 SS Jes 33 49 3 12 43 302 IDSEL AD17 REQ REQ2 GNT GNT2 rises bR cios 49 9014 B un m i PE 88SI5L Ts C101 L 0 0lu 2kV ces 1 9 31 31 531551 31641 32672 12632642057 21 Cel 11 12632 C11 12632 31151 12632642053 1263264265 3 0 35 12637642053 12632642651 1263264265 1263042051 12632042052 12632 12632052 12632641052 stay 5 C254 d t 35 35 PCLINTC 35 PCLINTD4 35 PCIINTA 35 35 35 PCIINTD 35 a a 0 SERIRO Rus i PCI RST4 3 x 1 77 x PQLKSLOTI 03 O PCLKSLOT2 03 M er 008 35 398 35 TT 5 A 8 liiis jt 80 31 0 35 18 2 5 a gt RBS mum ajaja Ei 2 12 amp i 35 18 aoea as 319 018 35 AS 33 ADI 35 Nara iL s 2 35 35 5 10 35 1901 35 10 5
81. 11 92 3308 ads Hr gt our 92 1 AEN 3 T asv 3181 1084 3 3108 1083 x Bes 10CHRDY 35 oen REES 6228 0801 735 x RE 5 Droz 35 xj gt 097 0803 35 uj ermu 1 _3 se 157 ON C92 pei x gt eet 87 x won 1627 3 10 3 8405 x D fem gt 0 91 34 SERIRO A 191 PCICLK O LPTSLCT 93 9 oa O LPTPE 92 t 91 19 1223 5 lt R229 gt INDEX gt ps INDEXE cg que Due 9 93 D wRO 91 21081 ab p S Sime 93 Bs 93 HOATAS D lt gt 92 BLMIIPSoo IT NotMoutled oT Sm Ds mw 81 No Mounted weer rx DATAS 91 FDD D Gsm 93 D D 9 Tena a cg L3 x xi sax 73 aap 71 8219 9 0 1 H1 19 721 I LL C71 d T p 0100553 105 T p i F PG CARDINI 4m Not Mounted oo
82. 2 824438 TAI t E E 77 2 31 4022330 33682 3157 33 t31 t31 31 33672682 32671683 33 31 320228 3267208 t31 31 gt SPKROUT 9 33073C8 5000 15 35 5V 10CHCHKX 35 IOCHRDY 35 4 35 10 amp 10516625 8108 i34 REFRESH 3 rencsige 35 O 031 21 108 3 M 533 3 GI 3 C3 328 et 3161 A t31 talcs t31 33 73 t31071 31073 t31 31 1 5400 18 3 1 38 BIOSCS _3 MN 3 gt NM 31 5 31 1582045 sie Fis en Los E 15x T5 PIIX4E 2 317500 RINTSMOCO S vel 31 958066 t3 usaPi _s 587 5 1901 35 1904 35 103 35 1805 35 1807 35 1806735 18010 35 1808 35 TROLL 35 0 Tora 35 7 R Rag 19014 35 z 18012_35 on 81 8 2K 18018 35 HAMKI o 080035 080 35 51 3 0801 35 090335 0802 35 0805 35 DROS 35 LH 12 RASI mosas DRO 35 0807 35 4 7K Socket MEM2SF 040 0 0 7 17500 3543125061 8 90 4 1 1 PCB Schematic Diagram 4 10 0 23 rr MN Peres VMOO 1 Refresh SCRAM veo 142 X 01 1 RAS to CAS 3MCLK EX SGRAM Wik Disable External
83. 2 0 INDEX DAA eo ke Ae s Eo et 3 E A 535385 5811555515555 v 2 Ho DRVO INDEX os 4 o GND DRVO 08 50 DCHG DRVI OL 20 O Mri 0 120 35v I 1 D O MTRO STEP 25 DIR WDATA 013 4 130 DENSL WGATE 0 STEP 017 4 150 wert 018 180 WDATA RDATA 019 4 180 WBATES DENSEL 200 GATEARAY 4 1 270 158 20 WPRT WGATE OUT 23 2 RDATA WGATE IN y dus 25 SIDESELO 266 52629 2611 2 21 Outline Operation FDD 1 an outline operation FDD is selected to make the motor run provided that the signals of both DRVO MTRO are set at the low level 2 Each time the motor makes one revolution an input of INDEX signal is generated This signal is used to identify that a diskette is present 3 The SIDESELO signal is set at the high level to select Head 0 The DIR signal is set at the high level to turn the head moving direction to the outer periphery 4 The STEP signal pulse is output to move the head 5 The TRKO signal is checked to confirm whether Track 0 has been detected If detection fails retrial from 4 is performed If Track 0 cannot be detected after the specified number of retries such a condition is regarded as an error When Track 0 is detected the RDATA signal is used to re
84. 2 6 T20UT rts2 61 20 T30UT COM2RTS 21 T40UT 28 58 8 2B psr2 22 S R20uT R2IN 2 0 82 26 0 57 22 R40UT O 1B 2 RI2 56 19 R50UT R5IN 001 0 o IS SHDN EN 5B RESETDRV 2 18 The I O levels of the UART1 2 signals of the IT8673F1 are maintained at the TTL level ADM211 is used outside the UART2 for use as the driver or receiver of the RS 232 C interface The ADM211 is an IC of 4 outputs and 5 inputs and works only with a single power supply of 5V Both COM1 and COM2 are used as the general purpose serial ports toward the outside Register frequency division Hexadecimal Decimal Baud rate Error rate The Baud rate used is based on 1 8462MHz 13 frequency divided from 24 2 19 2 1 5 3 Parallel port interface circuit The IT8673F is used as a parallel port control The parallel port of the IT8673F has both way function When controlled by software the data signals of the 7 0 become both way signals The output signals SLIN INIT AFD STB for parallel port control are pulled up with 4 7 of open drain output However since they are connected to the power supply terminal through di
85. 23456789 lt gt 8 I 5557 0123456789 lt gt ABCDEFGHIJT IJKLMNOPORRSTUVWXYZ abcdefghi jklmnop KLMNOPORRSTUVWXYZ abcdefghijklmnop amp 5 amp 0123456789 lt gt amp 5 amp 0123456789 lt gt JKLMNOPORRSTUVWXYZ abcdefghijklmnopq LMNOPQRRSTUVWXYZ abcdefghijklmnopq amp 0123456789 lt gt 5567 0123456789 lt gt ABCDEFGHIJKL KLMNOPORRSTUVWXYZ abcdefghijklmnopqr MNOPQRRSTUVWXYZ abcdefghijklmnopqr 556 0123456789 lt gt ABCDEFGHIJK 556 0123456789 lt gt ABCDEFGHIJKLM LMNOPQRRSTUVWXYZ abcdefghijklmnopqrs NOPORRSTUVWXYZ abcdefghijklmnopqars 586 0123456789 lt gt ABCDEFGHIJKL 56 0123456789 lt gt ABCDEFGHIJKLMN MNOPORRSTUVWXYZ abcdefghijklmnopqrst OPORRSTUVWXYZ abcdefghijklmnopqrst 0123456789 lt gt amp 0123456789 lt gt ABCDEFGHIJKLMNO NOPORRSTUVWXYZ abcdefghijklmnopqarstu PORRSTUVWXYZ abcdefghijklmnopqrstu 0123456789 lt gt ABCDEFGHIJKLMN 0123456789 lt gt ABCDEFGHIJKLMNOP OPORRSTUVWXYZ abcdefghijklmnopqrstuv ORRSTUVWXYZ abcdefghijklmnopqrstuv 0123456789 lt gt 0 ABCDEFGHIJKLMNO 0123456789 lt gt ABCDEFGHIJKLMNOPQ
86. 2Ch input pin 78 INS2C DO 78 Input Port 032 input pin IN 032Ch 82 ITEST3 Test pin Not connected 83 BACKLTON LCD Back Light control output signal Active 84 BL ON LCD Back Light control input pin Active 85 FPEN IN LCD enable input pin Active 86 LCDPWR LCD power control input pin Active 87 VSYNC Display Vsync input pin 88 LCD 1Q LCD control timing 1 Active 89 LCD 2QN LCD control timing 2 Active 90 LCD LCD control timing 3 Active 91 COLORCRN LCD control timing 4 Active LCD CONT 92 99 SD7 SDO Data bus conforming to the ISA Specifications DATA SD IORN ISA I F control signal I O Read signal Active IOWN ISA I F control signal I O Write signal Active AEN ISA I F control signal Address Enable signal 2 52 Signal Functions Common IN RESET_INN ISA I F control signal RESET input TMODE Test pin Not connected ITESTO Test pin Not connected OTESTO Test pin Not connected 0320 Reversed output of Output Port 0322h Not used O320 D2N O320 D1N Reversed output pin of Output Port 0322h bit2 Not used Reversed output pin of Output Port 0322h bit1 Not used O320 DON Reversed output of Output
87. 316 1 3 1 1 1 VRGNO 15501 5 6021 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 3 2 Peripheral PCB Parts Location JPK1720083 A PERIPHERAL 4 21 4 3 3 Peripheral Replacement Parts List Note When ordering replacement parts indecate Part No and Name of Parts RTL mark in Remarks means Repairable PCB Assembly Retention Time Limited Reno PatNe __ amp Description __ Ps set Remarks pC PERIPHERAL Pes jJpraMESANP transistor 21 6464 ED 0 0 0 0 4 R 651 653 jERDSZTMz camEONFIMRESISTOR R e54 jERDSZI8 camoNFLMRESISTOR 3 o 1 Ress cAREONFIMRESESTOR 1 R ese 1 c 6026035 ceramic capacitor J 2 2 2 Jo JA L 602 610 CHOKE COIL 646 FILTER DELAYLINE Jef o o ezen 1 BUZER 14 enson connectoR 4 enso 1 coNECTOR o Jaf o 651801 connectoR 2 enso 7 o Jaf o y O swo PUsHSWTCH 1 swo 1 pusHswitcH Jaf o y
88. 3227 3 PC16552DV 3228 322F Serial Port COM 4 PC16552DV Note ETHERNET Port Not Fixed 1 7 Interrupt Level Interrupt Level Description Power Management Check Parity Error Power Management Timer Output Keyboard Output Buffer Full IT8763F 8259 Slave Side Interrupt Serial Port COM 2 IT8763F Serial Port COM 1 IT8763F Reserve Diskette Controller Parallel Port1 Real Time Clock 82371EB Serial Port COM 4 PC16552DV Serial Port COM 3 PC16552DV IT8763F IT8763F Mouse apy CP Co processor Hard Disk Primary Hard Disk Secondary Note the jumper of the hardware should change The Interrupt of Power Management ETHERNET Interrupt Level Not Fixed 1 8 Pin assignments Serial COM1 9 pin D SUB Male No IN OUT Signal 1 IN CD 2 IN RD 3 OUT TD 4 OUT DTR 5 GND 6 IN DSR 7 OUT RTS 8 IN CTS 9 IN 2 9 pin D SUB IN OUT Signal 1 IN CD 2 IN RD 3 OUT TD 4 OUT DTR 5 GND 6 IN DSR 7 OUT RTS 8 IN CTS 9 IN 8 pin Modular No IN OUT Signal 1 FG 2 OUT RTS 3 IN RD 4 IN DSR or 5V or CD Default 5 OUT TD 6 OUT DTR 7 GND 8 IN CTS
89. 5010 35 ua ws 509 35 ri 508 35 si 507 35 ant 505 35 505 35 eit n 504 35 P 503 35 lt oe 502 35 501 35 509 35 Toa MNT PODIS 35 rra 998 ray LE 0014 35 i vss mu LENS 0013 35 xs ran LU 0012 35 0011 35 MIU P0010 35 55 09 35 m LA 008 35 m MI 2007 35 a MIL 2006 35 MI 2005 35 no 22 2004 35 os 2 PDD3 35 MEL 2902 35 PEU 901 35 2009 35 1015 50015 35 mulas 50014 35 AS 50013 35 5 su s ong LE 50012 35 vs 50011 35 a way 23 50010 35 un AMETE 5008 35 n 5208 35 91 5007 35 Mar 5006 3 5005 35 o LAU 5004 35 a IO 5003 35 m 5002 35 on 35 5001 35 tis 5009 35 E IDSEL AD18 31 31 gt 5 0 15 3 21482 50 0 15 35 32 gt 5000 7 35 73681232 gt 00 0 15 35 161 0009 15 35 61 O Pla 3 61 mi 3 61 mje PDA0 3 61 gt POIORS_3 51 P gt 3 61 lt PIORDY 35 53 C 35 6 noc 5 PDDACK9 3 62 nen C POCS 3 t61 gt PDCS34 3 61 gt sw 3 62 Spi 3 263 gt 5040 3 6 gt 50108 3 52 gt 501098 3 63 35 6 lt 0080 35 5 00043 672 gt 50516 3 163 gt socs3e_3 61 mon 35 03708 p C 85164 35 3 Co 3
90. 8 AD27 AD26 AD25 AD24 C BE3 AD23 3 3V GND AD22 AD21 AD20 AD19 GND 3 AD18 AD17 AD16 C BE2 3 3 GND FRAME IRDY 3 3V TRDY DEVSEL GND GND STOP LOCK 3 3 3 GND SERR PAR C BE1 AD15 AD14 3 GND AD13 AD12 AD11 AD10 GND GND AD9 AD8 C BEO AD7 3 3V 3 3V AD6 5 AD4 AD3 GND GND AD2 AD1 ADO 45V 45V 45V 45V 2 54 5V 5V Test Program and Power Supply Check 3 1 Voltage checks on the MAIN PWB Prior to inspection all loads such as the LCD unit HDD fluorescent display tube peripheral PWBs etc shall be 4 connected For the AC power supplies each power input shall conform to the requirements of rating Voltage values Item Measuring point Standard V Remarks 3V CN26_8pin TP6 GND 3 3 0 16 5 CN26 18pin TP6 GND 5 0V 0 25 5VSB CN26 1pin TP6 GND 5 0 0 25 12 CN26_4pin TP6 GND 12 0 0 6 12V CN26 28pin TP6 GND 12 0 0 6 15 CN26_2pin TP6 GND 13 5 20 CORE JP8 TP5 GND 1 6 0 13 JP7_3pin TP4 GND 1 8 0 09 2 5 JP8_2pin TP4 GND 2 5 0 12 RTCVCC 3 0 0 4 0 6 with the power Measurement of currents in t
91. 814118750 71 73 BLM 18750 71 A 118750 71 1187 0 7 1142 8750 1 m BLM 15750 1 RESET OUT 1 7 USIMO 1 572 4 Emt 15750 i 3 71 LPTAF DS 4 99118750 1 1 Ocse LPTDO 118750 E ac 1 71 LPTERRI lt LPTERR 504118750 71 o 1 73 LPTINITE Burt 18250 T 3 1 71 LPTD2 LTD 55118750 1 73 LPTSLING gt LPTSLING 2 118750 t2 1 O LPTD4 BUNT 12750 1 1 71 1 i 1 71 PTUS BN118750 CREE a o 1 LeTo a x 1 73 wee o LPTACKS BUN 18250 See ol AC 1 t7 M COME LPTBUSY 18 8 118750 erue T c 1 72 LPTPE 2118750 7 wrsuctra LPTSLCT 122717716 1 1 ne 1 AS Aun js e i 1 2 1 1 1 1 t es c178 1 lu iu Mar 71 xO BLMTIB7S0 t 1 DTR COM2DTR reiv 18750 71 RTS2 COMRTS BLMIIB7SO t 1 RXD2 COMORXD 118750 7 0582 118759 73 BLMITB7SO 71 1 BUMIIB7SS 73 COMRT 1183 750 1 wees 15 Ts itd 10 1c 9 oom im laud m COIGRTS
92. 9 1 268119 CER CASH DRAWER TRAL OPN 820 1 2 CNIS T 021 gt 091 EM ty Y R230 J 242 470 CDSTETUSI 5 11840 Cash css d R380 Testar 5 R382 j 1655076 16 15 1 140nsec OPEN 1 1 8201 23 1 2631440 1 023 ef NolMounted NotWouned bos casa 0574 6278 0274 273 0259 DRH2 0PN I 5 D T 1 10K 1 1 14 maxim Noi Mounted 1 1 1 Not Mounted Be ri 3 9 costetuse 1 34112759 1 cs D M Cash 5 1 lu os 10K 1 Ho Mounted 2 oe 1 mn 1 5 i 1 oe Not Mounted eal T 1 16 56 16 1 6 LC J G 16 2 6 4 1 1 PCB Schematic Diagram 9 10 72182191 RESET OUT 81 81 ce 81 81 81 C180 RDMPIIERRS 192 reum e 13 16 12 x 17 14 a an 10 CN21 t21 BLU 18752 3140 2552 25 71 3 814118750 1 71 1
93. AC 1 4 Short 2 3 Short 640x480 Factory setting 1 4 Short 2 3 Open 1024x768 1 4 Open 2 3 Short 800x600 1 4 Open 2 3 Open 1280x1024 This jumper sets the type of connected LCD to controller JP2 Power fail interrupt 1 2 Short NMI Factory setting 2 3 Short SMI This jumper defines the type of interrupt by power fail JP3 COMS IRQ 1 2 Short IRQ11 Factory setting 2 3 Short IRQ4 This jumper sets IRQ interrupt number used by UART JP4 5 6 Control signal of This jumper defines functions of some control lines 8 pin modular connector of See table below for combination of pins JP7 CPU voltage 1 2 Short 2 5 Factory setting 2 3 Short Reserved JP8 CPU GTL voltage Short GTL CORE voltage Factory setting Open Reserved JP9 Power control Short Boot by main power switch Open Boot by front power switch Factory setting Signal connector 4 Explanation 1 2 Short Pin8 is CTS Factory setting 2 3 Short Pin8 is Ground CTS is always active JP5 JP6 Explanation 1 2 Short 2 3 Short Pin4 is DCD DSR is always active Factory setting 2 3 Short 2 3 Short Pin4 is DSR DCD is always inactive 1 2 Short 1 2 Short 4 is fixed to 5V DSR is always active and DCD is inactive 2 3 Short 1 2 Short 4 is fixed to 5V DSR and DCD are always inactive 1 2
94. ATA 70 Lees 6 out328h GND Bit2 1 T 105 9 RESET gt uPD65884GM 019 2 46 2 1 17 Power ON OFF circuit 2 1 17 1 Power ON The conditions to make power ON are categorized to the following three cases The conditions and conditional sequences are specified below Condition 1 with the primary side switch JP9 is short circuited primary side Power switch is turned ON A power supply of 5VSB is supplied The ON SB signal is turned to the high level Potential at Pin 8 of HCT74 8 is turned low Since JP9 is short circuited the PS signal is turned to the low level The secondary side output of the power supply is turned ON Condition 2 ON with the secondary side power switch Condition Standby state with the primary side turned ON The primary side Power switch is turned ON and the standby state is assumed ON SB at high level secondary side Power switch is turned ON and the PWR_SW signal is turned low Potential at Pin 3 of MB3771 IC47 is turned high and the PS ON signal is turned low The secondary side output of the power supply is turned ON Condition 3 ON through the LAN Condition Standby state with the primary side turned ON The primary side Power switch is turned ON and the standby state is assumed ON SB at high level The command for
95. Enhanced IDE interface circuit for hard disc is incorporated the 82371 The E IDE is provided with two interfaces Primary and Secondary Since the E IDE interface is intended to be exclusively used for AT compatible machines and a control circuit is accommodated on the HDD side it is connected with the parallel data bus with the use of control signals With an I O access action from the CPU side the E IDE interface performs direct access to the register group in the drive in order to control this drive The primary side drive is selected by PDAO PDA 2 and the chip select PDCS1 and PDCS3 1 The read and write functions are selected by the use of the PDIOW and PDIOR signals For interrupt IRQ14 is used on the primary side and IRQ15 is used on the secondary side PDAS AHCT245 DERST E N PDD15 n i PPDD15 L LDERST E 20 PDDi4 ProD A PPDD14 PEDUL 1 DE7 3 PDD13 PPDD13 PPDD8 1 DEB 40 5 PDD12 iy PPDD12 EFDDS L DEG PPDD9 L 1 DE9 50 PDD11 n PPDD11 pem 7 PDD10 B PPDD10 PPDD10
96. External Memory Pre charge Time SGRAM 8 bit column address 9 bit column address 10 bit column address External Memory Column Address Control Reserve Reserve Reserve Reserve Reserve Reserve Color STN Color TFT Color LCD Type Inverted TFT FPCLK Select 1280 x 1024 1024 x 768 800 x 600 640 x 480 LCD Display Size 1 1 T 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 9 bit 3bit R G B 12 bit 4bit R G B 18 bit 6bit R G B 24 bit 8bit R G B 24 bit 12 12bit Analog 36 bit 18 18bit Reserve Color TFT Interface Type 24 bit interface 16 bit interface DSTN Interface Type Reserve GPR70 0 Reserve User configration Bits Reserve GPR70 1 Reserve User configration Bits Reserve User configration Bits Reserve GPR70 2 Reserve GPR70 3 Reserve 2 28 User configration Bits 2 1 7 1 SM710 Pin Assignment AD31 System address data bus AD30 IN OUT AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 ADO IN OUT PCI Command byte enable signal Active Low C BE1 C BE2 C BE3 PAR IN OUT PCI Bus parity signal FRAME IN OUT PCI The signal used to indicate that the bus cycle is currently executed Active Low TRDY
97. F ON ON ON ON ON Confirmation of the CPU operating frequency Observe the product No and CPU operating frequency on the following startup screen Phoenix Bios 4 0 Released 6 0 Copylight 1985 1999 Phoenix Technologies Ltd All Rights Reserved Panasonic JS 170FR Version 1 02 2000 10 05 CPU intel Mobile Pentium II Processor MHz 640K System RAM Passed Observe here Product No Frequency JS 170FR 20 21 22 23 266MHz JS 170FR 24 25 333MHz F U W 3 47 3 9 Materials for Reference 1 COM RS 232C loopback connectors 9 pin D SUB female 5 69 Ph 2 CONS RS 232C loopback connector 8 pin modular connector 4 OQ oO 09 3 Printer cable connection diagram Centronics 36 pin D SUB 25 pin female 1 1 19 19 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 14 14 13 13 10 10 28 20 11 11 29 21 12 12 30 22 16 18 31 16 32 15 36 17 3 48 4 LAN interface cable 8 pin modular connector 8 pin modular connector 1 1
98. GPI2 IN REQB GPI3 REQC GPI4 DMA request signal for the PCI bus Active RSTDRV Reset signal for the ISA system logic Active SAO IN OUT SA1 SA2 SA3 SA4 5 5 5 7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 ISA System address bus 2 6 00 ISA system data bus SD1 IN OUT SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 010 011 012 013 014 015 SBHE IN OUT Used to indicate that SD8 SD15 of the ISA transfer data are effective Active Low SDCS1 OUT The signal that becomes active with E IDE s second I O address 0170 0177h Active Low SDCS3 OUT The signal that becomes active with E IDE s second I O address Active Low SDDO E IDE Secondary data bus SDD1 IN OUT SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 SDD8 SDD9 SDD10 0011 0012 0013 0014 0015 SDAO E IDE Secondary side address SDA1 SDA2 SDDACK E IDE Acknowledge to secondary side PDDREQ SDDREQ E IDE Secondary side DMA request signal SDIOR E IDE Secondary side read signal SDIOW E IDE Secondary side write signal SIORDY E IDE Secondary side ready signal SERR IN OUT PCl system error signal Active SERIRQ GPI7 IN OUT Serial bus interrupt signal SLP Sleep request signal to the PENTIUM II Active SMBALERT IN Interrupt signal for the system management bus SMBCLK IN OUT Clock signal for the system management bus SMBDATA IN OUT Serial data for the sy
99. INTERNAL LOOPBACK Test EXTERNAL LOOPBACK Test l est done Press any key 3 Finish the test after displaying OK for all the diagnostic items 4 Press any key to obtain the 8 Test screen 5 Disconnect the loopback connector that has been connected to the COM port 6 Enter 2 ENTER through the keyboard LCD DISPLAY TEST 4 8 Serial port Test Test I O Address 02 8 RS232C Controller Register R W Test INTE LOOPBACK Test EXTE LOOPBACK Test CD E CTS 1 Test done Press any key 7 The EXTERNAL LOOPBACK Test shall result in ERROR and CTS ERROR 8 Press any key to obtain the 8 Test screen 3 25 8 3 test 1 Connect loopback connector to the The lock screw of the loopback connector shall be tightened normally 2 Enter 3 ENTER through the keyboard LCD DISPLAY TEST 4 8 Serial port Test Test COM3 I O Address 3220H RS232C Controller Register R W Test INTERNAL LOOPBACK Test EXTERNAL LOOPBACK Test l est done Press any key 3 Finish the test after displaying OK for all the diagnostic items 4 Press any key to obtain the 8 Test screen 5 Disconnect the loopback connector that has been connected to the port 6 Enter 3 ENTER through the keyboard LCD DISPLAY TEST 4 8 Serial port Tes
100. LK IN OUT Keyboard CLOCK MDAT IN OUT PS 2 Mouse Data MCLK IN OUT PS 2 Mouse CLOCK KRST Infrared serial receive data pin IRRX Infrared serial receive data pin IRTX Infrared serial transmit data pin GA20 Gate address 20 DACK1 DMA acknowledge signal Active DACK2 DACK3 PSON GP11 IN OUT Output for Power ON General purpose I O port PWRON PME IN OUT Power ON switch output PANSWH Panel switch input pin Active Low SA14 FAN_TAC3 System address bus 14 Address latched signal SA15 FAN_CTL3 IN OUT System address bus 15 Address latched signal COPEN Case open sensor output Active Low SLCT Select signal to be turned high by the selected printer PE Paper empty input signal High No paper remaining BUSY Busy signal sent from the printer Used to indicate that the printer cannot accept data Active High ACK Acknowledge signal sent from the printer Used to indicate that the printer has accepted data Active Low PD7 Parallel port data IN OUT PDO SLIN OUT Printer select signal Active INIT OUT Printer s initial setting signal Active ERR IN Error signal sent from the printer Active AFD OUT Printer s automatic carriage return signal Active STB OUT The signal to indicate that the parallel port data are effective Active AEN Address enable signal Normal High DMA Low RESET Hardware reset signal Active TC The signal to indicate that DMA data
101. OM1 data set ready signal Active RTS1 PIN95SEL COM1 send request signal Active Used at the high level with pin 95 for SA14 when the power supply is ON CTS1 COM send enable signal Active DTR1 PIN96SEL COM data terminal ready signal Active Used at the high level with pin 96 for SA15 when the power supply is ON RI1 ring indicator signal Active DCD1 COM1 data carrier detect signal Active RI2 ring indicator signal Active DCD2 data carrier detect signal Active RXD2 serial input data TXD2 serial output data DSR2 data set ready signal Active Low RTS2 KBC_IROM send request signal Active Low Used at the high level with the KB controller s built in ROM when the power supply is ON CTS2 send enable signal Active Low Used to enable the KB controller at the high level when the power supply is ON DTR2 KBCEN data terminal ready signal Active Low 2 16 _ 1 FAN control signal GP10 General purpose port pin GP17 IN OUT 14 CTL2 GP13 IN OUT FAN control signal FAN TAC2 GP12 IN OUT FAN rpm input pin DRQ1 DMA request signal Active High DRQ2 DRQ3 CLKIN IN External 24MHz clock input pin KDAT IN OUT Keyboard Data KC
102. Port 0322h bitO Not used 0320h DRAWE EN Cash Drawer Enable pin Active High DRAWER DRWONT2 Cash Drawer Type Detect pin IN32D_D3 Drawer1 status input INS2D D2 Drawer2 status input IN 032Dh 2 OPN Cash Drawer2 Open output pin Active High DRAWER DRW1 OPN Cash Drawer1 Open output pin Active High DRAWER DRWCNT1 Cash Drawer1 Type Detect pin McD Type High SECR Type Low IN 032Dh OT 190HN Output Port 0190h output pin for POST LED select Active Low OUT 80HN Output Port 0080h output pin for POST LED select Active Low POST REST OTN In phase output of REST IN input signal Active Low RESET OT329 D7 Output Port 0329h bit7 output pin OTS29 Output Port 0329h bit6 output pin OTS29 05 Output Port 0329h bit5 output pin OT329 D4 Output Port 0329h bit4 output pin OT329 D1 Output Port 0329h bit1 output pin OTS29 DO Output Port 0329h bitO output pin 0329h ISADO ISAD7 Data bus for ISA I F extension DATA ISAEX OT328_D1 Output Port 0328h bit1 output pin Not used 0328h 1_84M_OT 1 13 of the 59 pin input clock output generated 1_84M IN 1 84 2 clock input pin CLOCK OT328_D3 Output Port 0328h bit3 output pin Not used OT328_D4 Output Port 0328h bit4 output pin OT328_D5 OT328_D6 Output
103. Power ON is output through the LAN and the LAN WAKEUP signal is turned high Potential at Pin 6 of HTC74 IC37 is turned low and the PS signal is turned low The secondary side output of the power supply is turned ON 2 47 2 1 17 2 The conditions to make power OFF are as follows secondary side Power switch is pressed The standby state is assumed An OFF command output is generated by software The GPO24 3 signal is turned low An OFF command output is generated by hardware The POWER OFF signal is turned low In particular in this case this condition arises when the power supply is turned off in any case other than the normal state such as a service interruption etc 023 DTCI23YK Sw_D1SABLE 5V5B Rel 10K 5VSB 13 4 RC ON SB O b 2 123 a ro 1038 1 PHRGDOD Vi 4 45V58 j na 5068 u POHER OFF D p 4 558 E q 289 1040 3 R263 47K 027 BICI23YK 2 Loisir CP024 3 D 12 2K 10K 15N5B S 1038 2 5VSB T RESET _5 gt LAN NAKEUP 3 y 137 1 45VSB 14 1640 2 2 48 033 DICH FE A LI D PS 04 2 1 17 3 Battery backup circuit This system is provided with a batte
104. Q11 Mask enabled interrupt request signal Serial port 3 Active IRQ12 M Mask enabled interrupt request signal lt PS 2 mouse Active IRQ14 Mask enabled interrupt request signal lt Active IRQ15 Mask enabled interrupt request signal Active KBCCS GPO26 Chip select signal to the keyboard controller Active LA17 LA18 LA19 LA20 LA21 LA22 LA23 IN OUT ISA An address bus not latched yet 5 An output that is active with address 62h and 66h Active Low MEMCS16 ISA Used to specify the data bus width of the memory Low gt 16 bit High 8 bit MEMR IN OUT ISA The read signal to the memory device All area Active Low MEMW IN OUT ISA write signal to the memory device All area Active Low NMI Non maskable interrupt lower than SMI gt CPU OCO OC1 Overcurrent detector pin of the USB port OSC Clock input for timer counter 8254 Fixed at 14 3181MHz PAR PCI PCI Bus parity signal PCICLK PCI Clock signal for the PCI bus 2 30 2 PCIREQA PCIREQB PCIREQC PCIREQD PCI Bus request signal Active PCIRST Asynchronous reset signal Active PCI_STP Clock stop request signal for PCI gt Clock synthesizer Active PCSO PCS1 Pr
105. REQ3 nou vwe GNT GNT3 NIS me av 07 123 M TT 653 cs4 659 eed tore 1 y mis HVDD 4 70129 cee Less ces ces BLMIIPGOO cal cae cea 68 ERN nw 0 01 To ota 0 01g 0 01u 81 BacKLtT on 5 4 PEN Beck 117 m BACK 11 4 1 1 PCB Schematic Diagram 5 10 12631642051 80 31 0 35 gt 12632641652 8 3 0 9 35 gt 11 31 41 53 35 CO 1263264165 35 gt 13632641651 180 35 12632642052 TRDY 35 gt gt 12632642657 DEVSEL9_35 11231241551 11131152 SERRE 11131 35 11 GNT24 3 31551 35 lt 23 PCLKLAN 03 gt RTL8139B 12632642053 PCI 867 35 32051 R183 IC16 RTL8139B L Rev D Not mounted IC16 RTL8139B L Rev F Mounted 500 5 00 148 35 R200 4 MAZEE 5 PAL EEDT PS 112500 259 19 2 6103 610 0 01410 0 01 10 0 0tu 186 184 10K gt LAN LED tg O n t LAN_WAKEUP t101 LEKUO 7 Ici 879316467 3 00 4 Clos 0
106. ROM s chip select signal for BIOS Active BATLOWZ GPI9 Used as a general purpose input port IN OUT command byte enable signal Active C BE1 C BE2 C BE3 CLK48 IN Clock input for USB Fixed at 48MHz CLKRUN IN OUT PCI bus Clock control signal CONFIG1 IN Configuration CONF 1 PENTUM CONFIG2 CONF G2 Reserve CPURST Reset signal to CPU Active CPU_STP OUT Stop signal to CPU clock gt Clock synthesizer Active DEVSEL IN OUT Device select signal Active 2 3 DACKO ACK signal to DRQ Active Low DACK1 DACK2 DACK3 DACK5 DACK6 DACK7 DRQO DMA transfer request signal Active DRQ1 DRQ2 DRQ3 DRQ5 DRQ6 DRQ7 EXTSMI IN OUT External system management interrupt FRAME IN OUT PCI bus The signal to indicate that the bus cycle is currently executed Active FERR Floating decimal point error signal Active GNTA bus DMA enable signal Active GNTB GNTC Used a general purpose input port GPI14 15 16 GPI17 8 19 GPI20 121 Used general purpose input port GP08 GP027 GP028 GP029 IRQ9_0 GP030 IDSEL PCI The signal used to specify the target device INTR Interrupt request signal 1 0 1 15 Active High IGNNE Output to disregard the floating decimal point error INIT The initialize
107. Reserve 04000000 03 00000 10000000 External RAM DIMM 256M 7FFFF SystemBlOS Option RAM VGA BIOS 60000 01000000 16M Main RAM DIMM 40000 00100000 BIOS ROM 128k 20000 POSDIAG 000 0000 000 000 VGA BIOS 000C0000 Video RAM 128K 000A0000 Main RAM 640k 00000000 Note BIOS ROM always selects after resetting the hardware 1 6 Port Address Devices used for JS 170FR 0000 001F DMA Controller 1 82371EB 0020 0021 Interrupt Controller Master 82371EB 0022 0023 443BX Chip Set 82443 0024 0027 Reserve 0040 005 Timer Controller 82371EB 0060 006 Keyboard Controller IT8763F 0070 007F RTC NMI Mask 0080 7 Segment for POST 0080 009 DMA Page Register 82371EB 00A0 00BF Interrupt Controller Slave 82371EB 00 0 DMA Controller 2 82371EB 00 0 00 Co Processor 190 7 segment LED for Test 0170 1F8 Hard Disk 82371EB 0279 IT8661F 02 0 02 Reserve 02 8 02 Reserve 02 8 2FF 2 IT8763F 0300 031F ETHERNET RTL8139B 0320 032F JS 170FR System Extension Port 0378 037F Parallel Port 1 IT8763F 0380 SVGA Controller SM710 8 Reserve 7 Diskette Controller IT8763F 8 1 IT8763F 0 79 IT8661F 430TX Chip Set 82443 3220
108. ________ 7 RUBBER FOOT 2 287004084 BRACKET 9 40 YJP7FRJ20PIH PERIPHERAL 5 9 Packing Packing _____ Part No Part Name amp Description Faea Remi YJMSFC5EX CHOCK COIL Axx Exx Gxx Sxx Wxx K2CG3EW00001 YJKP30EPHA YJJDA30770B4 YJJDK13920B4 YJKPSV2516Y AC CORD 1 Wxx YJPLT 1M CLAMPER Axx Exx GxxSxx 6 1 Printed in Japan
109. ad out the data from Track 0 Inthe write mode the WRPRT signal is checked If it is at the low level writing is disabled Otherwise writing is enabled The SIDESEL DIR and STEP signals are specified to move the head to the required track The WGATE signal is made to stay at the low level to enable the FDD writing circuit 0 The write data are output from the WDATA signal 1 Upon completion of writing the WGATE signal is made to stay at the high level 2 The replacement of diskette is identified with the DCHNG signal GND INDEX 45V DRVO GND DCHG NC NC 5V MTRO DIR DENSEL STEP GND WDATA GND WGATE GND TRKO GND WRPRT RDATA GND SIDESELO NC 2 22 2 1 5 5 Keyboard controller circuit IT8673F is used for keyboard control The internal memory block of the IT8673F has programs for the keyboard control and the control with the main CPU The IT8673F internally converts the serial data sent from the keyboard into parallel data and performs interrupt operation to inform the CPU of the entry of a key input The operation clock is set at 8MHz in the internal register The fuse connected to Pin 4 of the connector is used to protect the curl cord from burning in case the power supply circuit is short circuited on the keyboard side PS 2MOUSE 1T8673F d
110. al FPSCLK OUT LCD Shift clock signal LP FHSYNC OUT LCD Horizontal data latch signal FPEN OUT LCD Panel enable signal FPVDDEN OUT LCD Power control signal Active High VBIASEN OUT LCD Bias power supply Vee control signal Active High PCLK IN OUT Video Port Pixel clock VREF IN OUT Video Port VSYNC or video decoder HREF IN OUT Video Port HREF or video decoder BLANK TVCLK IN OUT Video Port blank output P15 IN OUT Video Port RGB digital data P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 PO IREF IN Current reference input for CRT USR3 IN OUT General purpose port USR2 USR1 SDA IN OUT Used as an SDA signal with CRT USRO SCL IN OUT Used as an SCL signal with CRT 2 32 2 1 7 2 LCD interface circuit Refer to page 4 4 In regard to the interface signals for the LCD various signals on the main PWB are used in common and the loopback PWB is used in order to enable connections with any type of the LCD In this manner LCD connections are modified The DSTN type color LCD calls for a volume control for brightness adjustment Since the screen is divided the upper screen data UD 7 and the lower screen data LD 7 are output at the same time The TFT type color LCD has a single screen Therefore the display data are output for R G and B respectively In the SM710 the meaning of the output data changes according to the LCD panel mode
111. al Decimal Error rate Baud rate e o 9 o o o O o The Baud rate used is when 1 8432 2 oscillator is used 2 27 VGA circuit Refer to page 4 4 The SM710 is used as a display controller for this system The SM710 is a controller designed in accordance with the SVGA Super VGA Specification that enables color LCD display and CRT display of 640 x 480 and 800 x 600 dots The color TFT is an interface of 18 bits 6 bits x 3 while the color DSTN is an interface of 16 bits 8 bits x 2 The image thickness is controlled by the volume control A memory for Video with a capacity of 4Mbytes is incorporated The interface toward the CPU is connected according to the PCI bus specification The signal level is maintained at the TTL level The basic clock for V RAM access and display is produced by the internal PLL of the LSI based on the 14 318MHz 14MHz clock The SM710 executes initialize setting of the hardware by using the data bus 0 22 of the Video RAM when the reset condition is canceled There are the operational functions that can be set again by software and those available only by hardware setting Signal 7 MCLK 8 MCLK Description External Memory Refresh to Command Delay 3 MCLK 4 MCLK External Memory RAS to CAS Delay SGRAM Reserve Reserve Reserve 3 MCLK
112. and Save your changes to CMOS Space Select Enter Accept 5 Starting from the screen 4 above move to Exit by means of the rightward arrow mark Confirm that Exit Saving Changes has been selected and press the Enter key A sub screen is presented as shown below Then press the Enter key again PhoenixBIOS Setup Utility Main Advanced Power Boot Eit Saving Serup O Exit Discarding Load Setup Defa Discard Changes Save configuration changes and exit now Setup and Save Changes changes to Yes No Space Select Enter Accept If automatic restart occurs and a display of Configuration Error is presented select continue and press the Enter key Execute the procedures of 3 and thereafter 3 8 3 7 Method of diagnostic program starting 1 Diagnostic Program Start Start the diagnostaic program using a connected keyboard or the touch panel With keyboard 1 Connect the keyboard to the keyboard connector and turn on the POWER switch of the JS 170FR 2 When the following screen is shown during the starting process press the INSERT key on the keyboard LCD DISPLAY Phoenix Bios 4 0 Released 6 0 Copylight 1985 1999 Phoenix Technologies Ltd 11 Rights Reserved Panasonic JS 170FR With touch panel Keyboard not used 1 Switch the JS 170FR on 2 When the following screen is shown during the starting process keep pressing the u
113. ates human finger Shape of rubber end R8 Hardness 60 Load 200g Frequency 5 Hz Interface Serial interface using internal TTL level Size 12 1 type Local Area Network Interface Ethernet 10BASE T 100BASE TX Speed 10M 100Mbps Connector 8 pin Modular Jack RJ 45 Wake on LAN Supported Magnetic Card Reader Option U24 U25 type Track 1501 502 Swipe speed 10 120 maximum cm s Maximum swipe speed will be reduced when dual track reader is used Interface Data is received as keyboard data Limitation On MS DOS magnetic card reader doesn t work with USB keyboard Life Over 1 million swipe Buzzer Buzzer volume is fixed LED Four status indicators on front panel D 5 LAN CARD 1 2 3 4 Power Green Running Red Stand by Hard disk Light on access LAN Light on LAN activity Card Reader Green Good Red Error 1 3 Expansion Slot Option Either one of the below can be added on main board as an expansion slot PCMCIA Slot 1 Type or 2 Type Support PCMCIA CardBus PCI Slot 1 PCI Bus Slot Maximum PCI card size mm 174 63x106 68x component side 14 48 rear side 2 67 Supply Voltage Voltage 100V system AC 90V 132V 200V system AC 198V 264V Depending on destination Factory setting Not changeable
114. atic Diagram 6 10 M FRIM RY IDE 31 00 0 150 35 lt gt 0015 35 xl 0015 76 44 2 5 mm 324 1 2 1 TMs D Poo R12 4 2000 3 16 008 R32 5 DN PIDES RC es 9 2009 A 7006 326 9 ____ PODS 35 PIDE a PDUS R324 gt _ PIDES Not Mounted a mi ee es Do ou 2004 8322 WA d 10 4 ig RA 3 P003 93207 Pme 2007 X R313 4 2 cm rue Pos 20013 6 PIDEI3 Z PODI 5 erc amp PI WS A Ed mae 87 a AAE Fons gu Bo eis 1 2000 watt t m IDE o n PODRO 35 R329 9 Aes cus 10K 2 9 GNO 0 0lu is ot Mounted PDIOWS 8335 A 3 d 245 POTORS 8835 LE 85 ceptors t31 PDn2 3 PIORDY 35 8124 60 E MEO dp E erum emo m i eo M gere E ut SEA 31 PDCS34 3 gt 19014 31 LERH t 33 ayy Puta 2 7 NASTER SLAVE P ER z 9 R337 33 3 PHDD LED 31 PlIoRDY 35
115. backup mode Measure the voltages specified below in the backup mode by the use of the Ni Cd battery Item Measuring point Standard V Remarks 3V CN26 8pin TP6 GND 3 3 0 16 5V CN26_18pin TP6 GND 5 0 0 25 5VSB 26_1 TP6 GND 5 0 0 25 Measurement of currents in system backup circuit Measurement shall be carried out after the jigs as shown below have been connected For reference Diode 8A or above Standard current value 2 2 15 Input voltage 8 0V POWER unit 3 3 3 5 3 6 5 Inspection on the battery voltage detector circuit 1 Connect the keyboard to the FCR and turn on the power supply Then finish the diagnostic program DOS prompt display Q gt 2 Execute the inspection program for the battery voltage detector circuit 3 Apply DC 7 0V from the connected jigs and press an arbitrary key when the following display is presented at the LCD gt input voltage 7 0V Press any key to continue 4 Confirm that Battery Check 0 is displayed at the LCD Input voltage 7 0V Press any key to continue Battery Check 0 5 In the same manner apply 7 6V 8 2 and 8 5V and examine the battery check value Input Voltage Battery check value 7 0V 0 7 6V 2 8 2V 6 8 5V 7 Current consumption check 1 Apply the rated voltage that is specified on the main rating plate The measured current value shall be not greater t
116. cuted bus cycle can be finished without the wait state ZZ L2 CACHE control signal 2 8 2 1 2 2 RTC Real Time Clock circuit The FW82371EB incorporates an RTC function The RTC includes the hardware for clock and calendar functions and the battery backup type CMOS RAM that can manage the hardware setup information Operation is compatible with the MC146818 To actuate the RTC it is necessary to install the battery and the oscillator externally The oscillatory frequency is 32 768kHz fixed The clock is also of the backup type FW82371EB RTCVOC 16 N19 RrCx1 R20 RTC 10M x2 22p 32 768KHz 22 NONE This system uses a lithium battery to back up the RTC circuit The battery 1 is a charge disabled coin type primary battery that maintain a voltage of about 3 0 When the power supply is 3 3V is turned to the RTCVCC voltage via D 1 When the power supply is OFF the battery voltage is used as the RTCVCC voltage via D 2 The C 1 capacitor is a backup capacitor to be used during the replacement of battery The battery backup time is only about 2 minutes and therefore care must be taken at the time of replacement RTCVCC 3V 01 TP1 gt 704 R1 0 1u 1K R2 2 100 D 2 7 7 BT 4 CR2450 o 2 9 2 1 2 3 The E IDE
117. df MAXEOICSA Cp 1 EY 191 es 42 0g LS i qm x S T bg 33 3V VCCPGLL BV 400mA VIO 9 5 or 1 5V 1 42 59 40008 ee IE Oe see 2 39 2 1 12 ETHERNET interface circuit As one of the communication methods for this system the ETHERNET is used as the communication line The ETHERNET circuit is composed of the control block on the main PWB and the transceiver block The RTL8139B L is used as a control LSI In the serial EEPROM BR93LC46 connected to the outside interface related information and various information about the addresses interrupt network s ID addresses etc are stored At the time of starting the RTL8139 L is set up based on this EEPROM information The sync clock signal is generated from a 25 2 crystal oscillator connected During the reception of data the serial data received from the transceiver are converted to parallel data and various subsequent processes take place such as comparison with the ID address 32 bit CRC code check 64 bit preamble removal and the extraction of the data s main part Since then the data are transferred to the receiver buffer During data transmission the transmit
118. e PhoenixBIOS Setup Utilit Primary Master MB Item Specific Help Type Cylinders Sectors Maximum Capacity Multi Sector Transfers LBA Mode Control 32 Bit 1 0 Transfer Mode Ultra DMA Mode Help T Exit gt Select Select User BER ae di MB 16 Sectors Enable Disable Fast 4 Disable Item Menu cu Change Values F9 Setup Defaults Enter Select Sub Menue F10 Save and Exit 9 After verifying the setup has been performed correctly press the ESC key on the keyboard to return to the Main menu of the BIOS Setup Utility screen PhoenixBIOS Utility Advanced Power Boot System Date Legacy Diskette A gt Primary Master Primary Slave Secondary Master Secondary Slave gt Boot Options gt Memory Cache System Memory Extended Memory Help T Select Item Item Specific Help 1 44 1 25 31 2 1 MB None None None 640 KB Exit lt Select Menu Change Values F9 Setup Defaults Sub Menue F10 Save and Exit Enter Select 3 7 10 Select the Exit menu by using lt key on the keyboard PhoenixBIOS Setup Utility ain Advanced Power Boot Item Specific Help Exit Discarding Changes Load Setup Defaults Discard Changes Save Changes Exit System Setup
119. e High impedance Alternate status Device control Drive address Not used Tr Address of E IDE register XII 2 11 High impedance High impedance 2 1 2 4 USB interface This system is provided with two circuits of the USB Universal Serial Bus interfaces The power supply fed to the USB connector is a 5V power source that feeds a current at a maximum of 0 75A The USB controller is located in the FW82371EB of the chip set The basic operation clock is maintained at 48MHz The USB port can be connected with the keyboard mouse modem printer etc When a hub is externally connected multiple connections can be made at the same time MINISMDCO S 133 652 45 470K 16 JE 0580 5 lt gt DORMIT LIE PRE LB BLM3 IPS00 MINISMDCO S 2 1 R132 47 R 22uF USB 1 i i 31 580605 R134 560K 1 1 R124 14 00 ol EN o ee ee E 3 1 5 2 e 1 1 123 1 Ts 47 rk 47 15K LIB mnapo 1650 1 1 175 PLIX4E 15
120. e array BACK_ON FPEN FPVDDEN FP FVSYNC 84 85 86 87 GATEARAY BL_ON FPEN_IN BACKLITON LCDPWR VSYNC 12V 2 34 12V GND BACKLIT_ON 2 1 7 4 CRT interface For a standard feature this system is provided with an interface circuit for the CRT Simultaneous display is possible at the LCD and the CRT 43 9 118750 42 8 118750 XXE VGA 242 4 4 42 D Sub Half 15 pin Female Signal name i Signal name 1 O J 2 35 2 1 8 Piezoelectric buzzer circuit For use as a signal for the piezoelectric buzzer a rectangular wave output is generated from Pin 17 of the FW82371EB The diode D_A is used for the prevention of counter electromotive force The driving voltage is 12V 12V FW82371EB LS DTC123YK MA157 SPKR 2 36 Hardware reset circuit MB3771 is used in the hardware reset circuit When this MB3771 is used a low level is maintained at Pin 8 of the RESET output terminal under the condition that the power supply voltage of VCC Pin 5 is below the reference voltage approx 4 2V If the reference voltage is exceeded the potential level at the RESET output terminal is turned high after the lapse of the predetermined time period approx 100msec according to the capacitance connected to Pin 1 In addition t
121. er Test Magnetic Card Data OK Values somewhat change according to the card presently used F1 STOP CONTINUE F2 STOP MENU When the JS 170MG is used JIS1 track 2 ISO2 JIS1 track 1 ISO1 card are used Main PWB SW1 setting 1 2 3 4 5 6 OFF LCD DISPLAY TEST 12 Magnetic Card Reader Test Magnetic Card Data OK Bx KKK KKK KK KK KKK KK ke ke ke ke ke ke kk B Zkkkkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkxk Ckckckckckckckckckckckckckckckckckckckckckckckckckck ck ck ck kc k Dk Values somewhat change according to the card presently used 1 5 CONTINUE F2 STOP MENU 3 32 6 When the OK sign is perceived press any key to obtain a menu screen for the diagnostic program Confirm that the LED is lit in orange when the magnetic card reader unit is disconnected and the power supply is turned on LED color Lighting conditions Green 1 In the state that the card reader is incorporated and the card can be read out Lit in green when the power supply is ON 2 the state that the card is correctly read out The LED is not lit while the card is being read out Red 1 In the state that the card reader is incorporated and the card can be read out 2 In the state that the card is not correctly read out The LED is not lit while the card is being read out 3 When the card is read
122. ext Pattern 80 X 25 16 Color VGA Text Pattern 810 2D 16 Color INTER 1 2 14 screen 640 x 480 16 Color Graphic Mode is displayed Examine the screen and press 1 key if the result is OK Otherwise press the 2 key Confirm in this case that the 16 colors are actually displayed LCD DISPLAY 640 X 480 16 Color Graphic Mode Black Dark Gray Int BEEN Light Green HEN Light Brown ENTER 1 2 3 19 15 A gradation of green blue and red is displayed confirm the freedom from decoloration If the result is press 1 key In case of NG press the 2 key Return to 6 Test Menu LCD DISPLAY FARK TEST 6 Video Test Green gradation 6 scales 0 lue gradation 6 scales Red gradation 6 scales 1 2 NG ENTER 1 or 2 Gradation Thin gt Thick 6 2 VRAM Test 1 Enter 2 ENTER through the keyboard using the 6 Test Menu LCD DISPLAY TEST 4 6 Video Test Return to MAIN MANU Display Test VRAM Test Select and press E While the test is carried out the screen may encounter display turbulence or disappearance However the beep sound generated at the constant intervals indicates that the testing is in progress 3 20 2 Confirm the display belo
123. fter displaying OK for the test result 6 Press any key to obtain the 16 Test screen 7 Remove the test card from Slot 0 8 Enter 1 ENTER through the keyboard LCD DISPLAY TEST 16 PCMCIA Test PCMCIA Slot 0 test ERR CardBUS Bridge not found Test done Press any key 9 The test result shall result in ERR CardBUS Beidge not found 8 41 18 Flash Memory test 1 Enter 17 ENTER through the keyboard LCD DISPLAY ARAM e TS 17 Flash Memory Test FFF80000 FFF9FFFE FFF80000 FFF9FFFE FFF80000 FFF9FFFE FFFA0000 FFFBFFFE FFFA0000 FFFBFFFE FFFA0000 FFFBFFFE FFFC0000 FFFDFFFE FFFC0000 FFFDFFFE FFFC0000 FFFDFFFE FFFE0000 FFFFFFFE FFFE0000 FFFFFFFE FFFE0000 FFFFFFFE Flash Memory OK Test done Press any D W R DE W R PE W R PE 2 test result shall be 55 55 55 55 KKKK ES W ES W ES A W 3 Press any key to obtain a menu screen for the diagnostic program 3 42 A W 19 USB test 1 Enter 18 ENTER through the keyboard LCD DISPLAY TEST 18 USB Test Return to MAIN MENU USB Interface Test USB Keyboard Test Select and press ENTER key 2 Setthe USB low speed devices o
124. han the rated current specified on the main rating plate BIOS setup 1 Connect the keyboard to the keyboard connector of the JS 170FR and turn on the POWER switch 2 When the DEL key is pressed in the middle of POST Power on self test message display a screen as shown below is displayed Note If the BIOS setup is started for the first time an error message be presented in the middle of POST message display according to the initial condition of COMS However such a message shall be disregarded PhoenixBIOS Setup Utility Main Advanced Power Boot Exit System Time XX xXX xx Item Specific Help System Date Exit Legacy Diskette A 1 44 1 25 MB 3 1 2 Shift Tab lt Enter gt selects field gt Primary Master VO MB Primary Slave None Secondary Master None gt Secondary Slave None Boot Options Memory Cache System Memory Extended Memroy F1 Help Select Item Change Values F9 Setup Defaults Esc Exit lt Select Menu Enter Select Sub Menu 10 Save and 8 4 3 Starting from the screen 2 above move to Exit by means the rightward arrow mark Then using the downward arrow mark 2 select Load Setup Defaults and press the Enter key A sub screen is presented as shown below Then press the Enter key again PhoenixBIOS Setup Utility Main Advanced Power Boot 88 Exit Saving Changes
125. he RTC backup circuit Standard value 2 15uA Measuring circuit Main PWB The battery shall be disconnected during measurement Pin 1 of BTI terminal side Pin 2 of BTI terminal side Measurement shall be performed with the power supply turned off Note Standard values shall be obtained through measurements at a room temperature 3 1 3 2 Oscillation frequency check 1 Clock oscillation frequency Measuring point Standard Remarks x1 R85 TP6 GND 14 318Mhz 0 03 2 R123 TP6 GND 32 768Mhz 0 005 X4 C116 TP6 GND 25 000Mhz 0 03 5 C134 TP4 GND 10 000Mhz 2 2 Clock generator output frequency Item Measuring point Standard Remarks HCLKCPU R71 TP6 GND 64 516Mhz 66 9MHz HCLKDIM R76 TP6 GND 64 516Mhz 66 9MHz PCLKSLOT2 R68 TP6 GND 30 03Mhz 33 45MHz VGA_OSC R387 TP6 GND 14 286Mhz 14 925MHz 24MHz R114 TP6 GND 24 0Mhz 160ppm 48MHz R66 TP6 GND 48 0Mhz 160ppm 3 3 POWER switch FRONT switch check 1 Using the POWER switch turned on the power supply POWER Switch 5 FRONT Switch D DI us dun OOOO Pete 1 5 2 9 4 LED POWER 1 3 LAN 4 Magnetic card reader Rest Switch Confirm that the system is started and the POWER LED is lit in green 2 In the state of 1 above press the FRONT switch once Confi
126. he keyboard connector 2 Enter 3 ENTER through the keyboard 3 Select the keyboard type 1 JP 2 US 3 GR and press the Enter key LCD DISPLAY TEST 4 3 Keyboard Test e 12 3 4 5 6 7 8 0 1 2 2 4 5 6 7 9 0 I h u em 1 ded T 8 9 coge Eo de OK Oho x e 4 5 6 2 XCVBNM 5 12 5 goce Ss 0 Press Fl or F2 NG twice OK Test done Press any key 4 Display of the key input shall be as specified above However the lowest line conforms to the keyboard being used 5 When all key inputs have been entered press the F1 key twice in case of OK or the F2 key in case of NG 6 Press any key to obtain a menu screen for the diagnostic program 3 13 4 Floppy Disk test 1 2 4 5 2 3 4 5 Prior to turning ON the FCR power supply connect a 3 5 FDD unit CF VFD11 to the FDD connector Display a diagnostic menu by the method of 10 described previously Set a 3 5 2HD work diskette write enabled in the FDD Enter 4 ENTER through the keyboard Press the F1 key to start the test LCD DISPLAY TEST 4 Floppy Disk Test Insert a 2HD disk into the Drive KKKK KKK KKK kk Warning ttt KKKKKK KKK KK KKK CONTENTS OF WILL BE DESTROYED CK Ck Ck Kk KK CK CK CC CK KC I UK I KA MK ok 2
127. hrough the mouse inspection branch cables 2 Enter a key input of 15 ENTER from the Main Menu LCD DISPLAY TEST 4 15 Mouse Test Mouse Interface Test Mouse Interface OK ER 1 OK or 2 NG 3 Confirm that Mouse Interface OK is displayed and enter an input of the 1 key LCD DISPLAY TEST 4 15 Mouse Test Mouse Interface Test Mouse Interface OK Test done Press any key 4 Press any key to recover the Main Menu 5 Disconnect the mouse from the connector Enter a key input of 15 ENTER again from the Main Menu LCD DISPLAY TEST 4 15 Mouse Test Mouse Interface Test Mouse Interface 1 ER 1 OK or 2 NG 7 Confirm that Mouse Interface ERROR is displayed and enter a key input of 1 ENTER LCD DISPLAY TEST 4 15 Mouse Test Mouse Interface Test Mouse Interface OK Test done Press any key 8 Press any key to recover the Main Menu 3 40 17 PCMCIA test PCI slot test 1 Insert the PCMCIA card 2 Enter 16 ENTER through the keyboard LCD DISPLAY EST 16 PCMCIA Test Return to MAIN MENU Test Slot 0 Test Slot 1 Select and press ENTER key 3 Insert the PCMCIA card in Slot 0 top 4 Enter 1 ENTER through the keyboard LCD DISPLAY TEST 16 PCMCIA Test PCMCIA Slot 0 test OK Test done Press any key 5 Finish the test a
128. in Board Test ROM Checksum Test OK 3 Shutdown byte read write Test OK PIT Test OK Page register read write Test OK DMA controller Test OK Keyboard Test OK PIC Test OK Test OK Test done press any key Date of ROM establishment 2 Finish the test after displaying OK for all the diagnostic items 3 Press any key to obtain a menu screen for the diagnostic program 3 11 2 Random Access Memory test 1 Enter 2 ENTER through the keyboard LCD DISPLAY TEST 2 Random Access Memory Test RAM write Read Test 16384 KB OK RAM Address is up to RAM Refresh Test 16384 KB OK RAM Address Line Test RAM Address Bit 23 OK Test done Press any key F1 STOP CONTINUE F2 STOP MENU 1 5 CONTINUE F2 STOP MENU TEST RUN 2 Finish the test after checking the RAM capacity and displaying OK for all the diagnostic items 3 Press any key to obtain a menu screen for the diagnostic program 4 Inspection on a MAIN PWB unit should be carried out for each slot Otherwise two DIMM units should be mounted for inspection When two 16Mbyte DIMM units are mounted RAM size 32768KB RAM address 1FFFFFFH RAM address bit 24 bits When one 64Mbyte DIMM units is mounted RAM size 65536KB RAM address RAM address bit 25 bits 3 12 3 Keyboard test 1 Connect PC keyboard to t
129. lt gt R205 gt ps 47000 19 PoDR_35 giez 33 3 4 24725 Not Mounted ee cit C132 5 8K 91 womens 312101 3 gt gt ae apes TC S04F 77 18014 35 n sonam SECOUNDARY IDE 80000 15 35 Noon RAGE 50015 35 3 Ld 50015 5001435 8 12 60014 2 71 3 161 BSIDERSTS R340 d 51051 A 4 3 1 GND Wd 51067 3 15 5008 8355 sre 21 LS 5006 355 5 4 sues 5008 GEI 5 5005 R53 4 sue 50010 R352 gt SIDE 0 5004 su 50011 R350 1 SIDELI 5003 RIS 50012 8248 12 SIDEI2 5002 8g A 3 9 n SIDE2 50013 ETE D enel 5201 87157 sei 0014 83 15 SIDE 5000 8343 1059 R342 a E Em 50005 Ho a 91015 42 1 7508 520235 2 f 145000 1 a IDE 8501 27 3 1 35 We DIR 20 Nol Mounted RAGA 50050 35 R357 1 0 Sm E 2 6 SDIOR R363 33 5 150107 31 S082 3 S 3 i 1 SIORDY 35 R362 1 OE as oe tae dE sooo 3 ER Rua 55 3 gt Hi d usacecks 33 0 50 536 3 gt 15 50 53 3 00830 fe a 5016 3 d 18015 mes i 3j Slo SoA sue 29 MASTER SLAVE 13 8358 5 4
130. m the freedom from any problem such as dot missing and error display If the result is OK press the 1 key In case of press the 2 key Since a cross hatch screen is displayed confirm the freedom from any problem such as distortion dot missing and error display If the result is OK press the 1 key In case of press the 2 key 3 16 05 2 2096 6250 550 22 oR 6 Since checkers pattern screen is displayed confirm the freedom from any problem such as dot missing and error display If the result is OK press the 1 key In case of NG press the 2 key LCD DISPLAY OK or2 NG 7 Since a screen is displayed of a checkers pattern that is the reverse of the pattern in 6 above confirm the freedom from any problem such as dot missing and error display If the result is OK press the 1 key In case of NG press the 2 10 screen of 640 x 350 Mono Graphic Mode is displayed Examine the screen press 1 key if the result is Otherwise press the 2 key LCD DISPLAY 640 X 350 Mono Graphic Mode White Int White ER 1 OK or2 NG 3 18 11 A screen of 80 x 25 16 Color Text Mode is displayed Examine screen and press 1 key if the result is OK Otherwise press the 2 key Confirm that the 16 colors are displayed and the actual color is correctly displayed by the
131. mbers starting month of modifying the specifications Ex 2 Measures against locking up during LAN 02 communication Production number 3 Brightened CRT connected to VGA output Production month A January January 2002 February 4 User demand C March D April 5 User demand E May F June 6 User demand H July J August September 7 Attainment of stable parts supplier October November 8 Holding down temperature rise of stainless case N December 9 Elimination of connector for debugging 10 Elimination of Ultra DMA trouble 11 Ceased production of the part 12 Better marketability 13 TP slowdown 14 User demand 15 Prevention of rubber foot frame from being broken 5 TON ERVIEW potete tti utet ete ae bu 1 1 Generalis tin eet e iudei iei e eL En i tan 1 1 System Configurations 1 1 fer teli e MI 1 2 Memory 1 6 VO Pont 1 7 interrupt Level te bet euet Hac Pee Pax 1 8 misEz t1 anni 1 9 Appendix Dip Switches and Jumpers 1 16 2 Description of Operation e Reed e 2 1 JS 170F R Block Diagram scat ett Reate date Ut Eat a ede at tus 2 1 Descriptiori of
132. nhanced From 16 MB to 64 MB O1B O1B o o Baud rate of customer From 2400 bps 9600 wis UAE 5 oom dom O1B O1B display enhanced bps except G version Not pre installed 6 Operating System oom O1B O1B o o sy except version Power supply modified Manufacturer changed O1D OIDE Power supply modified Diffuser panel added O2A oum 02 02 02 9 Not implemented O1D O1D o uu aaa on implemented LAN LSI dri LSI 11 LAN LSI driver 51 manufacturer Pr software version up demand 12 disk enhanced From 3 25 GB to 5 GB O1F O1F pou OIF pom o 13 LAN driver software Software modified pou o Q1Jr 14 Lower case modified Battery replacement oop a coats samad ereas 1 simplified 15 Lower case modified Rubber foot frame _ P 2 Modifica Reason for modification i tion No 1 R430 jumper wire imbedded How to read serial nu
133. o power supply voltage level check the MB3771 functions to receive the forced reset signal from the outside If the following conditions are satisfied as the external factors the potential level at Pin 6 of the MB3771 will be lowered Then similarly as for the case when the power supply voltage is lowered the potential level at Pin 8 of the RESET output terminal is turned low External factors RESETSW signal is turned to the low level RESET switch pressed ISARST is turned to the low level During execution by software The PWRGOOD signal is turned to the low level POWER switch turned off VRMPGD is turned to the low level Supervision of CPU voltage signal is turned to the low level In case of debug gt RSS 103 gt R SRST R 123 gt PLING 32 1 13 mes took ORE 72083 3 3206 RESTDRV IO gt m wn a d 1039 5 1039 6 2 37 2 1 10 Clock The basic clock for this system is fed from the clock generator W150 The basic clock of the W150 is maintained at 14 3181MHz and various clock signals are output for the CPU chip set PCI bus SDRAM USB etc Yt HCLKDIMO 03 t13 a 03 12 3 TA HCLKDIM 03 03 HOLKDING_D3 HCLKDIT D3 AAA 4 gt 05 4_03 t31 0SC t42 Not Mounted gt 12 1
134. odes Device 74LS07 is inserted at an external open collector buffer address and interrupt of the parallel port are set up by the software IT8673F s ux 108 L 42 0 106 8 PD6 06 pps 107 05 108 04 109 5 O 1109 L p2 111 PD1 PDO DO Sax M SLIN INIT 166 INIT AFD 140 AFD 5 L 5 ERR 150 ERR SLCT 130 BUSY L 1 40 12 4 100 ack H80 19 p __ MA152WA ns 777 216 120 1220 250 2 20 2 1 5 4 FDD interface circuit The IT8673F is used as a floppy disc controller The FDC functions of the IT8673F are compatible with Devices 765A DP8473 The interface circuit is made AT compatible All the output signals to the FDD are processed in the open collector mode pulled up with 1kQ All the input signals from the FDD are pulled up with 2 2kQ Protection for the WGATE signal is assured by the hardware using its own signal of FDDEN 5V 1 1K 1K 2 2K 1 8763 P H a 4 4 __
135. ogrammable chip select signal Active PDAO PDA1 PDA2 E IDE Primary side address PDCS1 OUT The signal that is active with I O address 01F0 01F7h of E IDE Active PDCS3 OUT The signal that is active with I O address 03F6 03F6h E IDE Active PDDO PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 IN OUT E IDE Primary data bus 2 5 PDD8 PDD9 IN OUT PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 E IDE Primary data bus Pin No Signal name IN OUT Functions PDDACK E IDE Acknowledge to primary side PDDREQ PDDREQ E IDE Primary side DMA request signal PDIOR E IDE Primary side read signal PDIOW E IDE Primary side write signal PIORDY E IDE Primary side ready signal PHLD PCI bus hold request signal PHLDA Hold acknowledge signal to PHLD PIRQA PIRQB PIRQC PIRQD OCI bus interrupt signal PWRBTN Input pin for system s ON OFF PWROK System power input signal Active RCIN Initialize request signal to the CPU RI GPI12 Used as a general purpose input port RSMRST An input intended to reset the internal suspension state Active RTCALE GP025 RTCCS GP024 Used as a general purpose output port RTCX1 IN OUT RTCX2 Clock signal of 32 768kHz for RTC REFRESH IN OUT Memory refresh signal to the ISA bus Active REQA
136. ontroller At that time the end part of the data is attached with ENTER as a scan code When data are sent to the keyboard controller the CLKEN signal and the DATAEN signal are turned to the low level and the magnetic card controller is disabled in order not to send data to the outside keyboard Because of the requirements of the Standard the card readout speed can cover 8 150cm sec The CPU reads out scan codes from the keyboard controller and again converts them into character codes For example a magnetic card with 00012 written as the data may be read out Then since the start code B the end code F and the check byte 7 are already written in the card the data come to coincide with the result of the 00012 7 Return input from the keyboard in terms of operational sequence In case of failure in reading out the data from the card the keyboard controller does not send out any scan code but the error LED red is lit up 47K 47K 47K 5V CN311 N0100559V105 T 9 41 52 P10 8 40 ND KBDCK P53 P11 5 zal RESET q RST P12 2 P13 5 D p14 E 62 36 6 Pat P15 _ O DATA2 ote s 16 o TIMING2 60 P43 into FL 30 carp_ine 18 NT 100 2 100p T O TIMI 1
137. out in the reverse direction Orange 1 In the state that the card reader is not incorporated and the card cannot be read out 7 Press the F2 key test program to obtain the test program screen Note If the buzzer sounds during testing try to repeat the test again After the completion of testing return the DIP switches to their original positions In the initialized state the drawer test is locked by the password If the screen appears as shown below execute No 19 Input PASSWORD and execute the drawer test again LCD DISPLAY TEST 13 Drawer Test Ckckckckckckckckckck ck kk Warning Ckckckckckckckckckckckckckckckckckckck ck ck kk Input Password in Main menu 19 Press key to exit 3 33 14 Drawer test 1 Connect a drawer JS 170CD to the DRAWER connector 2 Enter 13 ENTER through the keyboard LCD DISPLAY TEST 4 13 Drawer Test 0 Return to MAIN MANU 1 DRAWERI 2 DRAWER2 Select and press E 3 Enter 13 ENTER through the keyboard At that time the drawer shall be connected to DRAWER 1 4 Confirm that the drawer is open LCD DISPLAY EST 4 13 Drawer Test Test done Press any key 5 Finish the test when the OK sign is perceived 6 Press any key to obtain the 13 Test Menu screen 7 Maintain the condition that the drawer is open 8 Enter 1 ENTER through the keyboard
138. pper rightcorner of the touch panel LCD DISPLAY Phoenix Bios 4 0 Released 6 0 Copylight 1985 1999 Phoenix Technologies Ltd 11 Rights Reserved Panasonic JS 170FR Acalibration test with the touch panel in the diagnostic program during ROM startup is cleared when turning off the power because its data is not saved 3 The screen appears as shown below LCD DISPLAY Please Press 9 Points 4 Touch each of the nine points to execute calibration A point disappears from the screen when it is touched 3 9 5 Confirm that a screen as shown below is displayed at the LCD LCD DISPLAY PANASONIC JS 170FR 0 LEE 1 ain Board Test 12 Random Access Memory Test 13 3 Keyboard Test 14 4 Floppy Disk Test 15 3 5 Hard Disk Test 16 RG Video Test 17 7 Parallel Port Test 18 8 Serial Port Test 19 9 Speaker Test 20 5 Customer Display Test EST PROGRAM V5 0 Touch Panel Test agnetic Card Reader Test Drawer Test Inline Test ouse Test PCMCIA Test Flash Memory Test USB Test Heat Run Test Remote Test Select and Press TER Key 5595550 00005 6 Execution of the diagnostic program shall be carried out with the touch panel the keyboard connected 3 10 3 8 Execution of diagnostic services 1 Main PWB test 1 Enter 1 ENTER through the keyboard LCD DISPLAY TEST 1 Ma
139. r 0 ENTER through the keyboard to obtain the test program screen B Select Primary Master MB by using 7 or key on the keyboard Note NG is shown as a result of the calibration test with the touch panel for a model onto which the application has not been installed Accordingly determination whether the result of the calibration test is OK or NG should be made according to the touch panel test after the calibration test Calibration OK Touch panel test OK Calibration Touch panel test The calibration data is cleared when turning off the power because the data is not saved on the disk 3 31 13 Magnetic Card test 1 Prior to turning ON the FR power supply connect a magnetic card reader unit JS 140MG XXX or JS 170MG 010 2 Turn on the power supply and confirm that the LED for the magnetic card is lit in green 3 Enter 12 ENTER through the keyboard 4 Let the magnetic card reader unit read out a card in the reverse direction and confirm that the LED for the magnetic card is lit in red 5 Let the magnetic card reader unit read out a card in the forward direction and confirm that the LED for the magnetic card is not lit in red Confirm also that the card data are correctly displayed on the screen When the JS 140MG is used JIS1 track 2 ISO2 card is used 1 2 3 4 5 6 Main PWB SW1 setting ON ON ON ON LCD DISPLAY TEST 12 Magnetic Card Read
140. r the USB low speed jigs in both slots 3 Enter 1 ENTER through the keyboard LCD DISPLAY x TEST 18 USB Test USB Interface Test PORT 0 Low speed device connected USB Interface Test PORT 1 Low speed device connected ENTER 1 OK or 2 NG 4 Finish the test after displaying Low speed device connected for the test result 5 If the result is OK press the 1 key Otherwise press the 2 key 6 Press any key to obtain a test screen of 19 7 Setthe USB low speed devices or the USB low speed jigs in both slots 8 Enter 1 ENTER through the keyboard LCD DISPLAY TEST 18 USB Test USB Interface Test PORT 0 High speed device connected USB Interface Test PORT 1 High speed device connected ENTER 1 OK or 2 NG 9 Finish the test after displaying High speed device connected for the test result 10 If the result is OK press the 1 key Otherwise press the 2 key 11 Press any key to obtain a test screen of 19 12 Remove the USB jigs from both slots 3 43 13 Enter 1 through the keyboard LCD DISPLAY TEST 18 USB Test USB Interface Test PORT 0 USB device not connected USB Interface Test PORT 1 USB device not connected ENTER 1 OK or 2 NG Finish the test after displaying USB device not connected for the test result If the result is OK press the 1 ke
141. ration screen Since then restart the test from the step of 2 above Upon normal completion of calibration the following screen display is presented LCD DISPLAY TEST 4 11 Touch Panel Test CALIBRATION OK Test done Press any key 4 If CALIBRATION is displayed restart the test from the step of 2 above Press any key to recover the screen of TEST 11 Touch Panel Test 3 29 12 2 Touch Panel test LCD DISPLAY TEST 4 11 Touch Panel Test 0 Return to MAIN MANU 1 CALIBRATION 2 TOUCH TEST Select and press ENTER key 1 Enter 2 ENTER through the keyboard to perform the Touch test LCD DISPLAY sees 21416 2 In the all item touch panel test screen the test shall be carried out on the screened keys of 2 2 2 15 11 8 20 2 and 20 15 Judgment of OK NG shall conform to the example shown below The condition shall be regarded as OK if the keys a b c d f g h i do not show any reaction black amp white reversed in the screen when the area in the inner frame of the e key hatched area is touched 3 30 3 Press 21 16 to recover the screen of TEST 11 Touch Panel Test LCD DISPLAY TEST 4 11 Touch Panel Test 2 TOUCH TEST OK ENTER 1 OK or NG Test done Press any key 4 Ente
142. rder to realize the AT compatibility the FW82371EB is internally equipped with the basic LSI and the control circuit that functions as a bridge circuit between the PCI bus and the ISA bus When the power supply is ON the FW82443BX is used to execute initializing setting for the hardware with the aid of the memory address bus MAB 6 12 For other details refer to the relevant catalogs FUNCTION O Buffer 1 Mobile Desktop 0 1 Tri stste 0 1 0 1 MAB7 MM Config Disable Enable Quick MAB10 Quick Start Start 0 Stop Clock Queue 1 4 Depth 0 1 1 0 MAB9 AGP MAB11 100MHz MAB12 CLOCK 66MHz 2 2 2 1 21 82371 Pin Assignment Signal name IN OUT Functions AEN The signal used to indicate that the DMA cycle is currently executed Active High A20M The signal intended to make the system address line A20 stay in internal mask off state A20GATE IN The gate signal for the address line A20 AD31 system address data bus AD30 IN OUT AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 ADO APICACK APIC Acknowledge signal to APICREQ APICCS APIC chip select signal APICREQ APIC bus request signal BALE Address latch enable signal BIOSCS
143. red system can be built by adding various optional functions Its display is of 800 x 600 SVGA specifications standard using a color LCD It is provided with a 20 digit x 1 line or 2 line fluorescent display tube for customer display In addition it has an interface of up to 2 channels for a Cash Drawer System Configurations Example VGA Monitor 150MS Printer TM 88 2 22 gt Card Reader 170FR CCU Communication Control Unit ISP In Store Processor 170FR Front counter Register 150DC Drive Through Controller 170CD Cash Drawer 150MS Bump Bar 160RD Remote Display 170MG Card Reader 1 1 Specifications Processor Chipset and BIOS CPU Intel Mobile Pentium 266MHz or 333 MHz BGA1 CORE 1 6V Chipset Intel 440BX PIIX4E BIOS Phoenix BIOS Memory e Main memory Capacity 64MB Standard 256MB Maximum Slot 168pin DIMM Slot x 2 One slot occupied by standard memory Type 3 3V SDRAM supported Note One 64 SDRAM is mounted on socket 1 as factory standard Each slot can 16 MB minimum to 128 maximum memory module Maximum height of DIMM 35 65mm EDO isn t being supported e 12 Cache Secondary Cache 256KB on CPU die e Video memory 4MB in VGA Controller Not expandable e BIOS Capacity 512KB Type Flash memory Fujitsu MBM29F040 or compatible Drives Floppy disk drive Option external One 3 5 t
144. res oar 15 Oswsw1 22 Bro sow gt 3 21 AB11 ud o pen 3 Deuxo 3 te1 3 cuum 21 Pel WA gt 0031 0 35 3104105 wes Ads m ETDS TTS 5 CES t os a ADIS 35 2 s ant 3s t e 01357 hear 35 7 803 0 35 be ane 35 A CHEB IS HG CABESE 35 3264205 38 1 ACH 2 35 x5 ADS 35 rela 371 p __ 8 1 35 2 fess soon X 8 2K ex nj C 8E34 3 i ew 1 vera C aA i Cim 35 33051 35 33C51 CREOS 3252 803 35 REO 35 3204 4 35 51 51 3 5 t4 O _ 35 31342053 35 3104305 1804 35 32042051 lt gt TRY 35 32041051 10 35 03204205 O 35 31342051 35 22151 0 35 32053 C3 PCI RST 35 32041051 lt 505 518116 37 lt PHOLDI 31 gt PHLDAS t31 RSM 32010 cwuencc 21 03 C2 ws lt 9 5 840 gi M jam H Qd GTLFEF eum 5 9 le La SD e
145. rm that the LCD display is unlit Confirm that the POWER LED is lit in red and the other LEDs are unlit 3 In the state of 2 above press the FRONT switch once again Confirm that the system is started the same screen as 1 is displayed at the LCD and the POWER LED is lit in green 4 Check rebooting then push the Reset switch 3 4 Backup function check 1 2 Measurement of Ni Cd battery charging current Standard charging current Measuring conditions 63 15 Battery voltage 8 0V Measurement shall be carried out after the jigs as shown below have been connected For reference POWER unit Battery voltage Backup operation check 2 Connect a CRT to the VGA connector and turn on the FCR power supply 3 Withdraw from the diagnostic screen Press Exit once and return to DOS prompt gt 4 Execute the backup operation check program from DOS prompt C gt backup ENTER key input 5 When POWER OFF is displayed at the CRT turn off the AC power supply of the FCR To turn off the AC power supply the POWER switch is turned off or the AC plug is pulled out Confirm that POWER OFF is displayed at the CRT Press the ENTER key once from the keyboard When the display shown below is presented at the CRT screen turn the FCR power supply 3 CQimch POWER OFF Press any key to continue Measurement of circuit voltages in
146. ry backup function to be available in case of a service interruption with a battery connected to the power unit The battery backup circuit is used for functional ON OFF control with the aid of software The software checks the battery voltage BATT_VOLT and switches on the required function when the voltage is found to be above the specified level When the function is turned ON and the AC power supply is turned OFF AC_ON signal turned low the BATT_ON signal is turned high and 5V 3 3V and 5VCPU about 8V are supplied from the battery in the power unit Since the supply of 12V is effected the Back Lite of the LCD cannot be lit up The backup feature is canceled in the following 3 cases When the function is switched OFF with software When forced OFF is executed from hardware in 2 to 5 minutes set by software after the start of backup action When the battery voltage lowers and the 5 voltage is found to be below the specified level approx 4 2V Battery charge is conducted inside the power unit while the AC power supply is ON The battery to be used is of the nickel cadmium type of 7 2V 1 2V x 6 cells 1500mA The control circuit is accommodated in the GATEARRAY For more details refer to the instruction manual for the GATEARRAY and the internal equivalent circuit 2 49 2 50 2 1 18 GATEARRAY uPD65884GM 019 BED Refer to page 4 8 Functions of the GATEARRAY uPD65884GM 019 BED are described below For
147. s bit 4 3 Signal to open drawer bit4 3 is 21705 bit4 3 is Off On 145ms Factory setting bit4 3 is On Off 108ms bit4 3 is On On 72ms These bits define the period to activate signal for drawer open Do not change these bits unless electrical specification of the drawer is modified in future 5 Type of customer display On Dual line type Off One line type This bit is used to get type of customer display one line type or dual This bit actually reflects the status of dip switch 2 bit5 Setting this switch to OFF returns 1 to this bit Extended port 32DH bitO reflects to this bit This bit should be set to indicate the customer display type actually connected if application program has a capability to adjust data for each display type 6 Reserved for future Off Factory setting Extended I O 32DH reflects to this setting This bit is reserved for future enhancements and any functions are not currently assigned to this bit 8 7 Type of LCD bit7 6 is 11 VGA 640x480 10 SVGA 800x600 01 XGA 1024x768 00 Reserved Bit8 7 is Off Off VGA 640x480 Factory setting Bit8 7 is Off On SVGA 800x600 Bit8 7 is On Off XGA 1024x768 Bit8 7 is On On Reserved Extended port 32DH bit6 7 reflects to these bits Jumper pins Jumper numbers and pin numbers are printed on the main board Direction of the jumpers follow the direction of printed numbers 1 4 EE 123 12 Pin Explanation JP1 VG
148. stem management bus SMEMW IN OUT Write signal to the ISA 0 1Mbyte memory device Active Low SMEMR IN OUT Read signal to the ISA 0 1Mbyte memory device Active Low OUT Higher preference non maskable interrupt gt CPU Active Low SPKR OUT Speaker output pin STOP IN OUT PCI Request signal from the target to the initiator for the suspension of execution Active Low STPCLK OUT The signal used to specify the suspension of clock supply to CPU s internal core gt CPU 2 7 Signal name IN OUT Functions SUSA SUSB SUSC Device power supply control signal SUSCLK Suspension clock 32 768kHz SUSSTAT1 SUSSTAT2 Suspension status output signal SYSCLK ISA bus system clock TC Pulse signal to be output when the terminal count of the DMA channel is attained Active High TEST Test pin THRM GPI8 Temperature sensing signal input pin TRDY IN OUT The signal used to indicate that the PCI target is enabled for data transfer USBP0 USBPO IN OUT Serial bus for USB Port 0 USBP1 USBP1 IN OUT Serial bus for USB Port 1 XDIR OUT X bus data transceiver s direction control signal High For write Low For read XOE X bus output enable control signal Active Low ZEROWS ISA The signal to indicate that the currently exe
149. t Test COM3 I O Address 3220H RS232C Controller Register R W Test Test Test l est done Press any key 7 The EXTERNAL LOOPBACK Test shall result in CTS ERROR 8 Press any key to obtain the 8 Test screen 9 Enter 0 ENTER through the keyboard to obtain a menu screen for the diagnostic program 3 26 9 Speaker test 1 Enter 9 ENTER through the keyboard LCD DISPLAY TEST 9 Speaker Test ER OK ER 1 OK or NG 2 If the buzzer tone is confirmed press the 1 key LCD DISPLAY TEST 4 9 Speaker Test ER OK ER 1 OK or NG 3 Press any key to obtain a menu screen for the diagnostic program 10 Customer Display Test 1 Enter 10 ENTER though the keyboard LCD DISPLAY TEST 4 8 Serial Port Test Return to MAIN MANU 2400bps 9600bps Select and press key For JS 170FR G select 1 2400bps For a model other than JS 170FR G select 2 9600bps 3 27 11 Customer Display test 1 Enter 10 ENTER through the keyboard LCD DISPLAY TEST 4 10 Customer Display Test CUSTMER DISUPLAY OK ENTER 1 OK or NG Test done Press any key F1 STOP CONTINUE F2 STOP ME Pattern 1 Pattern 2 Pattern 3 Pattern 4 Pattern 5
150. t 324H bit 5 reflects to this setting Touch panel type On Douwa Carrol Touch type Factory setting for Germany Model only Off Fujitsu type Factory Setting Touch panel has two kinds of operating mode Set this bit to Off Fujitsu type when you use Windows touch panel driver For use with McDonald s application set this bit to On Douwa or Carrol Touch type Circuit for decoding Magnetic card Swipe Reader MSR On Circuit 2 Formerly called as MAG2 Factory setting Off Circuit 1 Formerly called as MAG1 This model has two circuits circuit 1 and 2 to decode data on magnetic stripe of card Combination of a circuit and a track a data stream on the magnetic stripe is determined by dip switch 1 bit 5 6 See below When Single is set by dip switch 1 bit 4 only a circuit set by this bit is used for data decoding When Dual is set by dip switch bit 4 both circuit 1 and 2 can be used to decode data Bit 3 has no effect in this case Single and Dual circuit Magnetic card Swipe Reader MSR On Single Factory setting Off Dual When this bit is set to Single the circuit selected by bit3 is used to decode data and application receives data of a track defined by bit 5 6 through the circuit Dual setting uses both circuit 1 and 2 to decode data and application receives data of two tracks if both are on the card Only data of existing track is returned to application even if this bit is set to Dual
151. ter ENTER through the keyboard 5 If the contents of setting are checked and known to be correct enter 2 ENTER through the keyboard 6 Enter any key input 7 Enter 0 ENTER through the keyboard To the Inline Test Menu 8 Enter 0 ENTER through the keyboard the Main Menu 9 Enter 0 ENTER through the keyboard Withdrawal from the diagnostic program 15 2 Execution of Inline test 1 Connect 2 FR units through the LAN cables via the hub 10BASE T cable FR 1 Machine under test FR 2 Distant machine HUB 2 Enter 14 ENTER through the keyboard for both and FR 2 LCD DISPLAY for FR 1 and FR 2 TEST 14 Inline Test Return to MAIN MANU Set Configutation Send Data Receive Data Self Test Select and press E 3 Send a key input of 3 ENTER to FR 2 Data reception standby state LCD DISPLAY for 2 EST 14 Inline Test Receive Data 4 Send a key input of 2 ENTER to LCD DISPLAY for FR 1 TEST 14 Inline Test KKKKK Send Data 1234567890 FFFPFFFFPFFFE 3 37 5 When data are received from FR 1 FR 2 then displays the following screen LCD DISPLAY for FR 2 TEST 14 Inline Test Receive Data Receive Data 1234567890AB gt gt gt Send Data ABCDEF 123456 gt gt gt 1234567890AB
152. ting data are once stored in the transmitter buffer and conversion is conducted from parallel data to serial data Subsequently the data are sent to the transceiver after the completion of the generation and addition of a 64 bit preamble code and a 32 bit CRC code In case of the occurrence of collision re transmission is carried out In this system it is possible to perform wake up operation of the power supply through the ETHERNET Under the condition that the primary side power supply is switched ON it is possible to accomplish automatic power ON by the use of a command from another equipment LAN E 14 ud RTL8133B 1 16 5000 21 0 35 AD 35 19 8130 35 121 128 25 122 35 121 35 125 8 500 t li 059 1 4 7 54 ADIG 35 8115 35 2 t10 lee cr Olu T e Ti Olu Blu K 3 024 35 A 1152514 MUT T PR 655 asasasasccas TRIER 35 frees e oi IR 35 gt one 35 mw 35 D E Un Wie 35 D 35 gt ds 1 3
153. w which will be presented the meantime LCD DISPLAY TEST 4 6 Video Test VRAM TEST VRAM Size 4 Read Write test Address Line test 21 bit OK Test done Press any key 3 Press any key to recover the 6 Test Menu 4 Press 0 ENTER key to recover the Main Menu 7 Parallel Port test 1 Connect a printer TM 300 TM T80 to the printer port The lock screw of the printer connector shall be tightened normally 5 Display a diagnostic menu by the method of 10 described previously Enter 7 ENTER through the keyboard 5 LCD DISPLAY TEST 7 Paraller Port Test 0 Return to MAIN MANU 1 Display Test 2 Printer Auto Cut Test Select and press E 4 Enter 1 ENTER through the keyboard LCD DISPLAY TEST 4 7 Paraller port Test Paraller Port Test I O Address 0378H Test done Press any key 3 21 printer begins to print out characters Confirm that the following contents are presented i For Printer TM 300 ii For Printer TM T80 Parallel Port test 1 0 Address 0378H 1 5967 0123456789 lt gt ABCDEFG Parallel Port test 1 0 Address 0378H I 58 0123456789 lt gt HIJKLMNOPQRRSTUVWXYZ abcdefghijklmno JKLMNOPQRRSTUVWXYZ abcdefghijklmno I 4 amp 01
154. y Otherwise press the 2 key Press any key to obtain a test screen of 19 Enter 0 ENTER through the keyboard to obtain a menu screen for the diagnostic program 20 HEAT RUN test 1 5 Enter 19 ENTER through the keyboard Enter a key input of F1 to stop the diagnostic services Enter a key input of F2 to display the result of heat run test Confirm that all the error items are O at that time LCD DISPLAY TEST 419 Heat Run Test EST COUNT ERROR TIMES Main Board Test Random Access Memory Test Hard Disk Test Video Test Customer Display Test Inline Test F1 STOP CONTINUE F2 STOP ME Enter a key input of F2 to obtain a menu screen for the diagnostic program 3 44 21 VGA Monitor Display test 1 Connect a VGA monitor to the VGA connector 2 Turn on FCR power supply and confirm that the screen as shown below is displayed LCD DISPLAY PANASONIC JS 170FR TEST PROGRAM V5 X EXIT ain Board Test Random Access Memory Test Keyboard Test Floppy Disk Test Hard Disk Test Video Test Parallel Port Test Serial Port Test Speaker Test Customer Display Test Touch Panel Test Magnetic Card Reader Test Drawer Test Inline Test Mouse Test PCMCIA Test Flash Memory Test USB Test Heat Run Test Remote Test Jo 0 UNO 0 3 1 MS 3 4 5 6 Mos
155. ype drive unit 1 44MB 720KB Hard disk drive Standard internal One 2 5 type EIDE drive unit 4 0GB or more Option internal One 2 5 type EIDE drive unit Clock Tolerance Monthly 3 minutes Temperature 25 C Back up Method e Real Time Clock RTC Battery Lithium battery 560mAh Battery life 8 years need to be changed every 8 years Retention time 8 years On condition that unit is turned on for 12 hours per a day Power supply Battery Ni Cd battery 1200mAh Battery life 2 years need to be changed every 2 years Retention time 2 minutes On condition that the battery is fully charged at installation Registers must be powered on for more than 72 hours for full battery charge No display on the LCD during AC off 1 2 Crew display Display unit TFT type LCD with Dual Back Light Resolution 800 x 600 SVGA Dot pitch 0 3 mm Display size 12 1 type Contrast adjust Not needed Customer display Display unit Fluorescent display tube Color Green Number of digits 20 characters 5 x 7dots 9 x 6 mm 2 lines Interface Serial shared with TTL level It is possible to switch between Customer Display and External COMS3 port by software Touch Panel Type Resistive Life Resistive over 10 million times by finger touch Simul

JS-170FR-xx Service Manual

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